From b97005ea6b5891f1d2251828f38011971545c4f9 Mon Sep 17 00:00:00 2001 From: Gaku Inami Date: Fri, 24 Mar 2017 19:56:34 +0900 Subject: [PATCH 88/92] arm64: dts: r8a7796: Add cpu capacity-dmips-mhz Set the capacity-dmips-mhz for R-CAR M3. This value is based on the result of the evaluation. Signed-off-by: Gaku Inami --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 47b8af0..da26f88 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -98,6 +98,7 @@ <&cluster0_opp_tb3>, <&cluster0_opp_tb4>, <&cluster0_opp_tb5>, <&cluster0_opp_tb6>, <&cluster0_opp_tb7>; + capacity-dmips-mhz = <1024>; }; a57_1: cpu@1 { @@ -113,6 +114,7 @@ <&cluster0_opp_tb3>, <&cluster0_opp_tb4>, <&cluster0_opp_tb5>, <&cluster0_opp_tb6>, <&cluster0_opp_tb7>; + capacity-dmips-mhz = <1024>; }; a53_0: cpu@100 { @@ -124,6 +126,7 @@ dynamic-power-coefficient = <277>; clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; operating-points-v2 = <&cluster1_opp_tb0>; + capacity-dmips-mhz = <362>; }; a53_1: cpu@101 { @@ -133,6 +136,7 @@ next-level-cache = <&L2_CA53>; enable-method = "psci"; operating-points-v2 = <&cluster1_opp_tb0>; + capacity-dmips-mhz = <362>; }; a53_2: cpu@102 { @@ -142,6 +146,7 @@ next-level-cache = <&L2_CA53>; enable-method = "psci"; operating-points-v2 = <&cluster1_opp_tb0>; + capacity-dmips-mhz = <362>; }; a53_3: cpu@103 { @@ -151,6 +156,7 @@ next-level-cache = <&L2_CA53>; enable-method = "psci"; operating-points-v2 = <&cluster1_opp_tb0>; + capacity-dmips-mhz = <362>; }; L2_CA57: cache-controller@0 { -- 1.9.1