From 289fbd4f83543451323d6ce275fad1b5a85b61f1 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Thu, 14 Sep 2017 09:21:52 +0300 Subject: Initial commit for ADAS boards support in 2.23.0 --- .../0040-arm64-dts-renesas-add-ADAS-boards.patch | 17556 +++++++++++++++++++ 1 file changed, 17556 insertions(+) create mode 100644 meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch (limited to 'meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch') diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch new file mode 100644 index 0000000..4acd0f1 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch @@ -0,0 +1,17556 @@ +From 51718d8f768ba719a8a295e013e3456e13b70a98 Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov +Date: Fri, 14 Jul 2017 15:05:42 +0300 +Subject: [PATCH] arm64: dts: renesas: add ADAS boards + +Salvator-X.View board on R8A7795 ES1.x SoC +Salvator-X.View board on R8A7795 SoC +Salvator-X.View board on R8A7796 SoC +H3ULCB.View board on R8A7795 ES1.x SoC +H3ULCB.View board on R8A7795 SoC +M3ULCB.View board on R8A7796 SoC +H3ULCB.HAD board on R8A7795 ES1.x SoC +H3ULCB.HAD board on R8A7795 SoC +Kingfisher board on R8A7795 ES1.x SoC +Kingfisher board on R8A7795 SoC +Kingfisher board on R8A7796 SoC +Videobox board on R8A7795 ES1.x SoC +Videobox board on R8A7795 SoC +Eagle board on R8A7797 SoC +V3MSK board on R8A7797 SoC +Kingfisher board on R8A7797 SoC + +Signed-off-by: Vladimir Barinov +--- + arch/arm64/boot/dts/renesas/Makefile | 16 + + arch/arm64/boot/dts/renesas/legacy/Makefile | 8 + + .../renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts | 1717 +++++++++++++++++++ + .../renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts | 441 +++++ + .../dts/renesas/legacy/r8a7795-h3ulcb-kf-v0.dts | 1724 +++++++++++++++++++ + .../dts/renesas/legacy/r8a7795-h3ulcb-kf-v1.dts | 465 +++++ + .../dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts | 1214 +++++++++++++ + .../dts/renesas/legacy/r8a7796-m3ulcb-kf-v1.dts | 465 +++++ + .../dts/renesas/legacy/r8a7797-v3msk-kf-v0.dts | 20 + + .../boot/dts/renesas/legacy/ulcb-kf-cmos.dtsi | 75 + + .../arm64/boot/dts/renesas/legacy/ulcb-kf-rpi.dtsi | 77 + + .../dts/renesas/r8a7795-es1-h3ulcb-had-alfa.dts | 22 + + .../dts/renesas/r8a7795-es1-h3ulcb-had-beta.dts | 23 + + .../boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi | 225 +++ + .../boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts | 39 + + .../boot/dts/renesas/r8a7795-es1-h3ulcb-vb.dts | 1787 ++++++++++++++++++++ + .../boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts | 546 ++++++ + .../dts/renesas/r8a7795-es1-salvator-x-view.dts | 552 ++++++ + .../boot/dts/renesas/r8a7795-h3ulcb-had-alfa.dts | 22 + + .../boot/dts/renesas/r8a7795-h3ulcb-had-beta.dts | 23 + + .../arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi | 219 +++ + arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts | 39 + + arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb.dts | 1787 ++++++++++++++++++++ + .../arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts | 546 ++++++ + .../boot/dts/renesas/r8a7795-salvator-x-view.dts | 552 ++++++ + arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts | 36 + + .../arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts | 287 ++++ + .../boot/dts/renesas/r8a7796-salvator-x-view.dts | 318 ++++ + arch/arm64/boot/dts/renesas/r8a7797-eagle.dts | 561 ++++++ + arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts | 541 ++++++ + arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts | 294 ++++ + arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi | 518 ++++++ + arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi | 46 + + arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 1520 +++++++++++++++++ + arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi | 515 ++++++ + 35 files changed, 17240 insertions(+) + create mode 100644 arch/arm64/boot/dts/renesas/legacy/Makefile + create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts + create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts + create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-h3ulcb-kf-v0.dts + create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-h3ulcb-kf-v1.dts + create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts + create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7796-m3ulcb-kf-v1.dts + create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7797-v3msk-kf-v0.dts + create mode 100644 arch/arm64/boot/dts/renesas/legacy/ulcb-kf-cmos.dtsi + create mode 100644 arch/arm64/boot/dts/renesas/legacy/ulcb-kf-rpi.dtsi + create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had-alfa.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had-beta.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi + create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vb.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x-view.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-alfa.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-beta.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi + create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-salvator-x-view.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-eagle.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts + create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi + create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi + create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi + create mode 100644 arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi + +diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile +index 32fb4d9..fd17456 100644 +--- a/arch/arm64/boot/dts/renesas/Makefile ++++ b/arch/arm64/boot/dts/renesas/Makefile +@@ -4,5 +4,21 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb + dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb + dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb + ++# ADAS boards ++dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x-view.dtb ++dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-view.dtb ++dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb ++dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x-view.dtb r8a7795-es1-salvator-x-view.dtb ++dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-view.dtb r8a7795-es1-h3ulcb-view.dtb ++dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-had-alfa.dtb r8a7795-h3ulcb-had-beta.dtb r8a7795-es1-h3ulcb-had-alfa.dtb r8a7795-es1-h3ulcb-had-beta.dtb ++dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb r8a7795-es1-h3ulcb-kf.dtb ++dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-vb.dtb r8a7795-es1-h3ulcb-vb.dtb ++dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-eagle.dtb ++dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk.dtb ++dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk-kf.dtb ++ ++# ADAS legacy boards ++subdir-y := legacy ++ + always := $(dtb-y) + clean-files := *.dtb +diff --git a/arch/arm64/boot/dts/renesas/legacy/Makefile b/arch/arm64/boot/dts/renesas/legacy/Makefile +new file mode 100644 +index 0000000..7f25079 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/legacy/Makefile +@@ -0,0 +1,8 @@ ++# Legacy KF board: V0, V1 (V2 is the same as V1), V3 is latest and deployed in default directory ++dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf-v0.dtb r8a7795-es1-h3ulcb-kf-v1.dtb ++dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf-v0.dtb r8a7796-m3ulcb-kf-v1.dtb ++dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf-v0.dtb r8a7795-h3ulcb-kf-v1.dtb ++dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk-kf-v0.dtb ++ ++always := $(dtb-y) ++clean-files := *.dtb +diff --git a/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts b/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts +new file mode 100644 +index 0000000..cd23797 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts +@@ -0,0 +1,1717 @@ ++/* ++ * Device Tree Source for the H3ULCB Kingfisher V0 board on r8a7795 ES1.x ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "../r8a7795-es1-h3ulcb.dts" ++ ++/ { ++ model = "Renesas H3ULCB Kingfisher V0 board based on r8a7795"; ++ ++ aliases { ++ serial1 = &hscif4; ++ }; ++ ++ snd_clk: snd_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24576000>; ++ clock-output-names = "scki"; ++ }; ++ ++ wlan_en: regulator@4 { ++ compatible = "regulator-fixed"; ++ regulator-name = "wlan-en-regulator"; ++ ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_20 4 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ vcc_sdhi3: regulator@41 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "SDHI3 Vcc"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ vccq_sdhi3: regulator@5 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "SDHI3 VccQ"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ codec_en_reg: regulator@6 { ++ compatible = "regulator-fixed"; ++ regulator-name = "codec-en-regulator"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_20 15 0>; ++ ++ /* delay - CHECK */ ++ startup-delay-us = <70000>; ++ enable-active-high; ++ }; ++ ++ amp_en_reg: regulator@7 { ++ compatible = "regulator-fixed"; ++ regulator-name = "amp-en-regulator"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_20 0 0>; ++ ++ startup-delay-us = <0>; ++ enable-active-high; ++ }; ++ ++ lvds_switch: regulator@8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "lvds_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ /* gpio = <&gpio1 24 0>; */ ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ sdio_switch: regulator@9 { ++ compatible = "regulator-fixed"; ++ regulator-name = "wifi_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_20 5 0>; ++ enable-active-low; ++ regulator-always-on; ++ }; ++ ++ sound_switch: regulator@10 { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcm3168a_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_21 5 0>; ++ enable-active-low; ++ regulator-always-on; ++ }; ++ ++ radio_switch: regulator@11 { ++ compatible = "regulator-fixed"; ++ regulator-name = "radio_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_20 13 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ kim { ++ compatible = "kim"; ++ shutdown-gpios = <&gpio_ext_20 3 GPIO_ACTIVE_HIGH>; ++ /* serial1 */ ++ dev_name = "/dev/ttySC1"; ++ flow_cntrl = <1>; ++ /* int div 8 hscif@26.6666656MHz */ ++ baud_rate = <3333332>; ++ }; ++ ++ btwilink { ++ compatible = "btwilink"; ++ }; ++ ++ sound_ext: sound@0 { ++ pinctrl-0 = <&sound_0_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; ++ ++ simple-audio-card,format = "left_j"; ++ simple-audio-card,name = "pcm3168a"; ++ ++ simple-audio-card,bitclock-master = <&sound_ext_master>; ++ simple-audio-card,frame-master = <&sound_ext_master>; ++ sound_ext_master: simple-audio-card,cpu@0 { ++ sound-dai = <&rcar_sound 0>; ++ dai-tdm-slot-num = <8>; ++ dai-tdm-slot-width = <32>; ++ }; ++ ++ simple-audio-card,codec@0 { ++ sound-dai = <&pcm3168a>; ++ dai-tdm-slot-num = <8>; ++ dai-tdm-slot-width = <32>; ++ system-clock-frequency = <24576000>; ++ }; ++ }; ++ ++ /delete-node/sound; ++ ++ rsnd_ak4613: sound@1 { ++ pinctrl-0 = <&sound_1_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; ++ ++ simple-audio-card,format = "left_j"; ++ simple-audio-card,name = "ak4613"; ++ ++ simple-audio-card,bitclock-master = <&sndcpu>; ++ simple-audio-card,frame-master = <&sndcpu>; ++ ++ sndcpu: simple-audio-card,cpu@1 { ++ sound-dai = <&rcar_sound 1>; ++ }; ++ ++ sndcodec: simple-audio-card,codec@1 { ++ sound-dai = <&ak4613>; ++ }; ++ }; ++ ++ sound_radio: sound@2 { ++ pinctrl-0 = <&sound_2_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; ++ ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "radio"; ++ ++ simple-audio-card,bitclock-master = <&sound_radio_master>; ++ simple-audio-card,frame-master = <&sound_radio_master>; ++ simple-audio-card,cpu@2 { ++ sound-dai = <&rcar_sound 2>; ++ }; ++ ++ sound_radio_master: simple-audio-card,codec@2 { ++ sound-dai = <&radio>; ++ system-clock-frequency = <12288000>; ++ }; ++ }; ++ ++ lvds-encoder { ++ compatible = "thine,thc63lvdm83d"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port@0 { ++ reg = <0>; ++ lvds_enc_in: endpoint { ++ remote-endpoint = <&du_out_lvds0>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ lvds_enc_out: endpoint { ++ remote-endpoint = <&lvds_in>; ++ }; ++ }; ++ }; ++ }; ++ ++ lvds { ++ compatible = "lvds-connector"; ++ ++ width-mm = <210>; ++ height-mm = <158>; ++ ++ panel-timing { ++ /* 1280x800 @60Hz */ ++ clock-frequency = <65000000>; ++ hactive = <1280>; ++ vactive = <800>; ++ hsync-len = <40>; ++ hfront-porch = <80>; ++ hback-porch = <40>; ++ vfront-porch = <14>; ++ vback-porch = <14>; ++ vsync-len = <4>; ++ }; ++ ++ port { ++ lvds_in: endpoint { ++ remote-endpoint = <&lvds_enc_out>; ++ }; ++ }; ++ }; ++ ++ radio: si468x@0 { ++ compatible = "si,si468x-pcm"; ++ status = "okay"; ++ ++ #sound-dai-cells = <0>; ++ }; ++}; ++ ++&pfc { ++ hscif4_pins: hscif4 { ++ groups = "hscif4_data_a", "hscif4_ctrl"; ++ function = "hscif4"; ++ }; ++ ++ sdhi3_pins_3v3: sd3_3v3 { ++ groups = "sdhi3_data4", "sdhi3_ctrl"; ++ function = "sdhi3"; ++ power-source = <3300>; ++ }; ++ ++ sound_0_pins: sound0 { ++ groups = "ssi78_ctrl", "ssi7_data", "ssi8_data"; ++ function = "ssi"; ++ }; ++ ++ sound_1_pins: sound1 { ++ groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; ++ function = "ssi"; ++ }; ++ ++ sound_2_pins: sound2 { ++ groups = "ssi6_ctrl", "ssi6_data"; ++ function = "ssi"; ++ }; ++ ++ usb0_pins: usb0 { ++ groups = "usb0"; ++ function = "usb0"; ++ }; ++ ++ can0_pins: can0 { ++ groups = "can0_data_a"; ++ function = "can0"; ++ }; ++ ++ can1_pins: can1 { ++ groups = "can1_data"; ++ function = "can1"; ++ }; ++ ++ canfd0_pins: canfd0 { ++ groups = "canfd0_data_a"; ++ function = "canfd0"; ++ }; ++ ++ canfd1_pins: canfd1 { ++ groups = "canfd1_data"; ++ function = "canfd1"; ++ }; ++}; ++ ++&du { ++ ports { ++ port@3 { ++ endpoint { ++ remote-endpoint = <&lvds_enc_in>; ++ }; ++ }; ++ }; ++}; ++ ++&gpio0 { ++ video_a_irq { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A irq"; ++ }; ++ ++ video_b_irq { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B irq"; ++ }; ++ ++ gpioext_2_20_irq { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "0x20@i2c2 irq"; ++ }; ++}; ++ ++&gpio1 { ++ gpioext_2_21_irq { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "0x21@i2c2 irq"; ++ }; ++ ++ wifi_irq { ++ gpio-hog; ++ gpios = <25 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "wifi irq"; ++ }; ++}; ++ ++&gpio5 { ++ touch_irq { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "touch irq"; ++ }; ++ ++ /* From TI forum */ ++ /* BT_AUD_OUT should be pulled low when WL_EN is activated. */ ++ /* in case it isn't, wilink8 ends up in one of the test modes that introduces various issues */ ++ bt_strap { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "BT strap pin"; ++ }; ++}; ++ ++&gpio7 { ++ gpioext_2_21_irq { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "0x21@i2c4 irq"; ++ }; ++}; ++ ++&hscif4 { ++ pinctrl-0 = <&hscif4_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ ++ status = "okay"; ++}; ++ ++&i2c2 { ++ clock-frequency = <400000>; ++ ++ gpio_ext_20: pca9535@20 { ++ compatible = "nxp,pca9535"; ++ reg = <0x20>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio0>; ++ interrupts = <15 IRQ_TYPE_EDGE_FALLING>; ++ }; ++ ++ gpio_ext_21: pca9535@21 { ++ compatible = "nxp,pca9535"; ++ reg = <0x21>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio1>; ++ interrupts = <15 IRQ_TYPE_EDGE_FALLING>; ++ }; ++ ++ i2cswitch2: pca9548@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x74>; ++ reset-gpios = <&gpio6 5 GPIO_ACTIVE_LOW>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ /* BCM node(s) */ ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ /* USB3.0 HUB node(s) */ ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ /* Power amp node(s) */ ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ /* Radio node(s) */ ++ }; ++ ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ /* A2B node(s) */ ++ }; ++ ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ /* PCIe node(s) */ ++ }; ++ ++ i2c@6 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <6>; ++ /* LVDS display node(s) */ ++ ++ polytouch: edt-ft5x06@38 { ++ compatible = "edt,edt-ft5x06"; ++ reg = <0x38>; ++ interrupt-parent = <&gpio5>; ++ interrupts = <6 IRQ_TYPE_EDGE_FALLING>; ++ }; ++ }; ++ ++ i2c@7 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <7>; ++ /* Audio, GPS and Gyro node(s) */ ++ ++ pcm3168a: audio-codec@44 { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm3168a"; ++ reg = <0x44>; ++ clocks = <&snd_clk>; ++ clock-names = "scki"; ++ tdm; ++ VDD1-supply = <&codec_en_reg>; ++ VDD2-supply = <&codec_en_reg>; ++ VCCAD1-supply = <&codec_en_reg>; ++ VCCAD2-supply = <&codec_en_reg>; ++ VCCDA1-supply = <&_en_reg>; ++ VCCDA2-supply = <&_en_reg>; ++ }; ++ ++ lsm9ds0_acc_mag@1d { ++ compatible = "st,lsm9ds0_accel_magn"; ++ reg = <0x1d>; ++ }; ++ ++ lsm9ds0_gyr@6b { ++ compatible = "st,lsm9ds0_gyro"; ++ reg = <0x6b>; ++ }; ++ ++ /* GPS@ 0x42 */ ++ }; ++ }; ++}; ++ ++&i2c4 { ++ gpio_ext_22: pca9535@21 { ++ compatible = "nxp,pca9535"; ++ reg = <0x22>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio7>; ++ interrupts = <3 IRQ_TYPE_EDGE_FALLING>; ++ ++ cmos_pwdn { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CMOS PWDN"; ++ }; ++ cmos_rst { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CMOS RST"; ++ }; ++ /* pin 12 - CAM_CLK */ ++ rpi_cam_io_1 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "RaspB_IO1"; ++ }; ++ /* pin 11 - CAM_GPIO - assume pwdn */ ++ rpi_cam_io_0 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "RaspB_IO0"; ++ }; ++ }; ++ ++ i2cswitch4: pca9548@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x74>; ++ reset-gpios= <&gpio6 21 GPIO_ACTIVE_LOW>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ /* SAM node(s) */ ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ /* Slot A (CN10) */ ++ ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ ov106xx_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ ov106xx_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; ++ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ ov106xx_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ ov106xx_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; ++ ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ ov106xx_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ ov106xx_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@0 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti964_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti964_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ ti964_des0ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ ti964_des0ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ ti964_csi0ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@0 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_a_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti954_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti954_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ ti954_csi0ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ /* MAX9286 @ 0x2c */ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ /* Slot B (CN11) */ ++ ++ ov106xx@4 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x64>; ++ ++ port@0 { ++ ov106xx_in4: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin4ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ ov106xx_ti964_des1ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep0>; ++ }; ++ ov106xx_ti954_des1ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@5 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x65>; ++ ++ port@0 { ++ ov106xx_in5: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin5ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ ov106xx_ti964_des1ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep1>; ++ }; ++ ov106xx_ti954_des1ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@6 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x66>; ++ ++ port@0 { ++ ov106xx_in6: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin6ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ ov106xx_ti964_des1ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@7 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x67>; ++ ++ port@0 { ++ ov106xx_in7: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin7ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ ov106xx_ti964_des1ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep3>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@1 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti964_des1ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ ti964_des1ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ ti964_des1ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ ti964_des1ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ ti964_csi2ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@1 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_b_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti954_des1ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ ti954_des1ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ }; ++ port@1 { ++ ti954_csi2ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ ++ /* MAX9286 @ 0x2c */ ++ max9286-max9271@1 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des1ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ max9286_des1ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ max9286_des1ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ max9286_des1ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ max9286_csi2ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@6 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <6>; ++ /* Slot B (CN11) */ ++ ++ video_b_ext0: pca9535@27 { ++ compatible = "nxp,pca9535"; ++ reg = <0x27>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_b_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg1"; ++ }; ++ video_b_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg0"; ++ }; ++ video_b_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR_SHDN"; ++ }; ++ video_b_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR0"; ++ }; ++ video_b_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR1"; ++ }; ++ video_b_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR2"; ++ }; ++ video_b_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR3"; ++ }; ++ video_b_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B DES_SHDN"; ++ }; ++ video_b_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B led"; ++ }; ++ }; ++ ++ video_b_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_b_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg2"; ++ }; ++ video_b_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg1"; ++ }; ++ video_b_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg0"; ++ }; ++ video_b_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR_SHDN"; ++ }; ++ video_b_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR0"; ++ }; ++ video_b_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR1"; ++ }; ++ video_b_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR2"; ++ }; ++ video_b_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR3"; ++ }; ++ video_b_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B DES_SHDN"; ++ }; ++ video_b_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B LED"; ++ }; ++ }; ++ }; ++ ++ i2c@7 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <7>; ++ /* Slot A (CN10) */ ++ ++ video_a_ext0: pca9535@26 { ++ compatible = "nxp,pca9535"; ++ reg = <0x26>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; ++ }; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; ++ }; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; ++ }; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A led"; ++ }; ++ }; ++ ++ video_a_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg2"; ++ }; ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; ++ }; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; ++ }; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; ++ }; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A LED"; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&pcie_bus_clk { ++ clock-frequency = <100000000>; ++ status = "okay"; ++}; ++ ++&pciec0 { ++ status = "okay"; ++}; ++ ++&pciec1 { ++ status = "okay"; ++}; ++ ++&vin0 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ vin0_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ vin0_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ vin1_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ vin1_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin2 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ vin2_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin3 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ vin3_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&vin4 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi41"; ++ virtual,channel = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin4_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ vin4_ti964_des1ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep0>; ++ }; ++ vin4_ti954_des1ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin5 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin5ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep1: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin5_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ vin5_ti964_des1ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep1>; ++ }; ++ vin5_ti954_des1ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin6 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin6ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <2>; ++ remote-endpoint = <&ov106xx_in6>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep2: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin6_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ vin6_ti964_des1ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin7 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin7ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <3>; ++ remote-endpoint = <&ov106xx_in7>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep3: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin7_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ vin7_ti964_des1ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&csi2_40 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&csi2_41 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_41_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&rcar_sound { ++ pinctrl-0 = <&sound_clk_pins>; ++ ++ /* Multi DAI */ ++ #sound-dai-cells = <1>; ++ ++ rcar_sound,dai { ++ dai0 { ++ playback = <&ssi7>; ++ capture = <&ssi8>; ++ }; ++ ++ dai1 { ++ playback = <&ssi0 &src0 &dvc0>; ++ capture = <&ssi1 &src1 &dvc1>; ++ }; ++ ++ dai2 { ++ capture = <&ssi6>; ++ }; ++ }; ++}; ++ ++&sdhi3 { ++ pinctrl-0 = <&sdhi3_pins_3v3>; ++ pinctrl-names = "default"; ++ ++ vmmc-supply = <&wlan_en>; ++ vqmmc-supply = <&vccq_sdhi3>; ++ keep-power-in-suspend; ++ enable-sdio-wakeup; ++ bus-width = <4>; ++ no-1-8-v; ++ non-removable; ++ cap-power-off-card; ++ max-frequency = <26000000>; ++ status = "okay"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ wlcore: wlcore@2 { ++ compatible = "ti,wl1837"; ++ reg = <2>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <25 IRQ_TYPE_EDGE_RISING>; ++ }; ++}; ++ ++&usb2_phy0 { ++ pinctrl-0 = <&usb0_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&hsusb { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&xhci0 { ++ status = "okay"; ++}; ++ ++&msiof1 { ++ status = "disabled"; ++}; ++ ++&can0 { ++ pinctrl-0 = <&can0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; ++}; ++ ++&can1 { ++ pinctrl-0 = <&can1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; ++}; ++ ++&canfd { ++ pinctrl-0 = <&canfd0_pins &canfd1_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ ++ channel0 { ++ status = "okay"; ++ }; ++ ++ channel1 { ++ status = "okay"; ++ }; ++}; ++ ++&ssi8 { ++ shared-pin; ++}; ++ ++/* uncomment to enable CN48 on VIN4 */ ++//#include "../ulcb-kf-rpi.dtsi" ++/* uncomment to enable CN47: SD on SDHI3 */ ++//#include "../ulcb-kf-sd3.dtsi" ++/* uncomment to override CN29 (CMOS camera) on VIN5 */ ++//#include "../ulcb-kf-cmos.dtsi" +diff --git a/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts b/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts +new file mode 100644 +index 0000000..ac6a12b +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts +@@ -0,0 +1,441 @@ ++/* ++ * Device Tree Source for the H3ULCB Kingfisher V1 board on r8a7795 ES1.x ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7795-es1-h3ulcb-kf-v0.dts" ++ ++/ { ++ model = "Renesas H3ULCB Kingfisher V1 board based on r8a7795"; ++ ++ aliases { ++ serial1 = &hscif0; ++ serial2 = &hscif1; ++ serial3 = &scif1; ++ }; ++ ++ wlan_en: regulator@4 { ++ compatible = "regulator-fixed"; ++ regulator-name = "wlan-en-regulator"; ++ ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_74 4 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ codec_en_reg: regulator@6 { ++ compatible = "regulator-fixed"; ++ regulator-name = "codec-en-regulator"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_74 15 0>; ++ ++ /* delay - CHECK */ ++ startup-delay-us = <70000>; ++ enable-active-high; ++ }; ++ ++ amp_en_reg: regulator@7 { ++ compatible = "regulator-fixed"; ++ regulator-name = "amp-en-regulator"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_74 0 0>; ++ ++ startup-delay-us = <0>; ++ enable-active-high; ++ }; ++ ++ /delete-node/regulator@8; ++ ++ sdio_switch: regulator@9 { ++ compatible = "regulator-fixed"; ++ regulator-name = "wifi_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_74 5 0>; ++ enable-active-low; ++ regulator-always-on; ++ }; ++ ++ /delete-node/regulator@10; ++ ++ radio_switch: regulator@11 { ++ compatible = "regulator-fixed"; ++ regulator-name = "radio_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_74 13 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ kim { ++ shutdown-gpios = <&gpio_ext_74 3 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ hdmi-out { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con: endpoint { ++ remote-endpoint = <&adv7513_out>; ++ }; ++ }; ++ }; ++}; ++ ++&pfc { ++ /delete-node/hscif4; ++ ++ scif1_pins: scif1 { ++ groups = "scif1_data_b"; ++ function = "scif1"; ++ }; ++ ++ hscif0_pins: hscif0 { ++ groups = "hscif0_data", "hscif0_ctrl"; ++ function = "hscif0"; ++ }; ++ ++ hscif1_pins: hscif1 { ++ groups = "hscif1_data_a", "hscif1_ctrl_a"; ++ function = "hscif1"; ++ }; ++ ++ du_pins: du { ++ groups = "du_rgb888", "du_sync", "du_clk_out_0", "du_disp"; ++ function = "du"; ++ }; ++}; ++ ++&du { ++ pinctrl-0 = <&du_pins>; ++ pinctrl-names = "default"; ++ ++ ports { ++ port@0 { ++ endpoint { ++ remote-endpoint = <&adv7513_in>; ++ }; ++ }; ++ }; ++}; ++ ++&gpio0 { ++ /delete-node/video_a_irq; ++ /delete-node/video_b_irq; ++ /delete-node/gpioext_2_20_irq; ++}; ++ ++&gpio1 { ++ /delete-node/gpioext_2_21_irq; ++ /delete-node/wifi_irq; ++}; ++ ++&gpio2 { ++ bl_pwm { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "BL PWM 100%"; ++ }; ++}; ++ ++&gpio5 { ++ /delete-node/touch_irq; ++ /delete-node/bt_strap; ++}; ++ ++&gpio7 { ++ /delete-node/gpioext_2_21_irq; ++}; ++ ++&scif1 { ++ pinctrl-0 = <&scif1_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&hscif0 { ++ pinctrl-0 = <&hscif0_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ ++ status = "okay"; ++}; ++ ++&hscif1 { ++ pinctrl-0 = <&hscif1_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&hscif4 { ++ /delete-property/pinctrl-0; ++ /delete-property/pinctrl-names; ++ ++ status = "disabled"; ++}; ++ ++&i2c2 { ++ /delete-node/pca9535@20; ++ /delete-node/pca9535@21; ++ ++ gpio_ext_74: pca9539@74 { ++ compatible = "nxp,pca9539"; ++ reg = <0x74>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio6>; ++ interrupts = <8 IRQ_TYPE_EDGE_FALLING>; ++ ++ hub_pwen { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "HUB pwen"; ++ }; ++ hub_rst { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "HUB rst"; ++ }; ++ otg_offvbus { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "OTG off VBUSn"; ++ }; ++ otg_extlpn { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "OTG EXTLPn"; ++ }; ++ otg_stat1 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "OTG Stat1"; ++ }; ++ otg_stat2 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "OTG Stat2"; ++ }; ++ }; ++ ++ gpio_ext_75: pca9539@75 { ++ compatible = "nxp,pca9539"; ++ reg = <0x75>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio6>; ++ interrupts = <4 IRQ_TYPE_EDGE_FALLING>; ++ ++ gps_rst { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "GPS rst"; ++ }; ++ fpdl_shdn { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "FPDLink shdn"; ++ }; ++ }; ++}; ++ ++&i2cswitch2 { ++ reg = <0x71>; ++ reset-gpios= <&gpio5 3 GPIO_ACTIVE_LOW>; ++ ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ ++ hdmi@3d { ++ compatible = "adi,adv7511w"; ++ reg = <0x3d>; ++// interrupt-parent = <&gpio2>; ++// interrupts = <0 IRQ_TYPE_EDGE_BOTH>; ++ pd-gpios = <&gpio_ext_75 5 GPIO_ACTIVE_LOW>; ++ ++ adi,input-depth = <8>; ++ adi,input-colorspace = "rgb"; ++ adi,input-clock = "1x"; ++ adi,input-style = <1>; ++ adi,input-justification = "evenly"; ++ adi,clock-delay = <1200>; ++ adi,clock-max-rate = <100000>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ adv7513_in: endpoint { ++ remote-endpoint = <&du_out_rgb>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ adv7513_out: endpoint { ++ remote-endpoint = <&hdmi_con>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c4 { ++ /delete-node/pca9535@21; ++ ++ gpio_ext_76: pca9539@76 { ++ compatible = "nxp,pca9539"; ++ reg = <0x76>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio7>; ++ interrupts = <3 IRQ_TYPE_EDGE_FALLING>; ++ ++ port_b_a0 { ++ gpio-hog; ++ gpios = <0 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B A0"; ++ }; ++ port_b_a1 { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B A1"; ++ }; ++ port_a_a0 { ++ gpio-hog; ++ gpios = <2 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A A0"; ++ }; ++ port_a_a1 { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A A1"; ++ }; ++ cmos_pwdn { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CMOS PWDN"; ++ }; ++ cmos_rst { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CMOS RST"; ++ }; ++ /* pin 12 - CAM_CLK */ ++ rpi_cam_io_1 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "RaspB_IO1"; ++ }; ++ /* pin 11 - CAM_GPIO - assume pwdn */ ++ rpi_cam_io_0 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "RaspB_IO0"; ++ }; ++ sam_rst { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "SAM RST"; ++ }; ++ sam_pwr { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "SAM PWR"; ++ }; ++ /* 0 - FPDLink output, 1 - LVDS output */ ++ lvds_vs_fpdl { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "LVDS switch"; ++ }; ++ }; ++ ++ gpio_ext_77: pca9539@77 { ++ compatible = "nxp,pca9539"; ++ reg = <0x77>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio5>; ++ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; ++ ++ mpcie_wake { ++ gpio-hog; ++ gpios = <0 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "mPCIe WAKE#"; ++ }; ++ mpcie_wdisable { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "mPCIe W_DISABLE"; ++ }; ++ mpcie_clreq { ++ gpio-hog; ++ gpios = <2 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "mPCIe CLKREQ#"; ++ }; ++ mpcie_ovc { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "mPCIe OVC"; ++ }; ++ }; ++}; ++ ++&i2cswitch4 { ++ reg = <0x71>; ++ reset-gpios= <&gpio3 15 GPIO_ACTIVE_LOW>; ++}; ++ ++&wlcore { ++ interrupts = <25 IRQ_TYPE_EDGE_FALLING>; ++}; +diff --git a/arch/arm64/boot/dts/renesas/legacy/r8a7795-h3ulcb-kf-v0.dts b/arch/arm64/boot/dts/renesas/legacy/r8a7795-h3ulcb-kf-v0.dts +new file mode 100644 +index 0000000..f640350 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/legacy/r8a7795-h3ulcb-kf-v0.dts +@@ -0,0 +1,1724 @@ ++/* ++ * Device Tree Source for the H3ULCB Kingfisher V0 board on r8a7795 ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "../r8a7795-h3ulcb.dts" ++ ++/ { ++ model = "Renesas H3ULCB Kingfisher V0 board based on r8a7795"; ++ ++ aliases { ++ serial1 = &hscif4; ++ }; ++ ++ snd_clk: snd_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24576000>; ++ clock-output-names = "scki"; ++ }; ++ ++ wlan_en: regulator@4 { ++ compatible = "regulator-fixed"; ++ regulator-name = "wlan-en-regulator"; ++ ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_20 4 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ vcc_sdhi3: regulator@41 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "SDHI3 Vcc"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ vccq_sdhi3: regulator@5 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "SDHI3 VccQ"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ codec_en_reg: regulator@6 { ++ compatible = "regulator-fixed"; ++ regulator-name = "codec-en-regulator"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_20 15 0>; ++ ++ /* delay - CHECK */ ++ startup-delay-us = <70000>; ++ enable-active-high; ++ }; ++ ++ amp_en_reg: regulator@7 { ++ compatible = "regulator-fixed"; ++ regulator-name = "amp-en-regulator"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_20 0 0>; ++ ++ startup-delay-us = <0>; ++ enable-active-high; ++ }; ++ ++ lvds_switch: regulator@8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "lvds_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ /* gpio = <&gpio1 24 0>; */ ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ sdio_switch: regulator@9 { ++ compatible = "regulator-fixed"; ++ regulator-name = "wifi_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_20 5 0>; ++ enable-active-low; ++ regulator-always-on; ++ }; ++ ++ sound_switch: regulator@10 { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcm3168a_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_21 5 0>; ++ enable-active-low; ++ regulator-always-on; ++ }; ++ ++ radio_switch: regulator@11 { ++ compatible = "regulator-fixed"; ++ regulator-name = "radio_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_20 13 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ kim { ++ compatible = "kim"; ++ shutdown-gpios = <&gpio_ext_20 3 GPIO_ACTIVE_HIGH>; ++ /* serial1 */ ++ dev_name = "/dev/ttySC1"; ++ flow_cntrl = <1>; ++ /* int div 8 hscif@26.6666656MHz */ ++ baud_rate = <3333332>; ++ }; ++ ++ btwilink { ++ compatible = "btwilink"; ++ }; ++ ++ sound_ext: sound@0 { ++ pinctrl-0 = <&sound_0_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; ++ ++ simple-audio-card,format = "left_j"; ++ simple-audio-card,name = "pcm3168a"; ++ ++ simple-audio-card,bitclock-master = <&sound_ext_master>; ++ simple-audio-card,frame-master = <&sound_ext_master>; ++ sound_ext_master: simple-audio-card,cpu@0 { ++ sound-dai = <&rcar_sound 0>; ++ dai-tdm-slot-num = <8>; ++ dai-tdm-slot-width = <32>; ++ }; ++ ++ simple-audio-card,codec@0 { ++ sound-dai = <&pcm3168a>; ++ dai-tdm-slot-num = <8>; ++ dai-tdm-slot-width = <32>; ++ system-clock-frequency = <24576000>; ++ }; ++ }; ++ ++ /delete-node/sound; ++ ++ rsnd_ak4613: sound@1 { ++ pinctrl-0 = <&sound_1_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; ++ ++ simple-audio-card,format = "left_j"; ++ simple-audio-card,name = "ak4613"; ++ ++ simple-audio-card,bitclock-master = <&sndcpu>; ++ simple-audio-card,frame-master = <&sndcpu>; ++ ++ sndcpu: simple-audio-card,cpu@1 { ++ sound-dai = <&rcar_sound 1>; ++ }; ++ ++ sndcodec: simple-audio-card,codec@1 { ++ sound-dai = <&ak4613>; ++ }; ++ }; ++ ++ sound_radio: sound@2 { ++ pinctrl-0 = <&sound_2_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; ++ ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "radio"; ++ ++ simple-audio-card,bitclock-master = <&sound_radio_master>; ++ simple-audio-card,frame-master = <&sound_radio_master>; ++ simple-audio-card,cpu@2 { ++ sound-dai = <&rcar_sound 2>; ++ }; ++ ++ sound_radio_master: simple-audio-card,codec@2 { ++ sound-dai = <&radio>; ++ system-clock-frequency = <12288000>; ++ }; ++ }; ++ ++ lvds-encoder { ++ compatible = "thine,thc63lvdm83d"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port@0 { ++ reg = <0>; ++ lvds_enc_in: endpoint { ++ remote-endpoint = <&du_out_lvds0>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ lvds_enc_out: endpoint { ++ remote-endpoint = <&lvds_in>; ++ }; ++ }; ++ }; ++ }; ++ ++ lvds { ++ compatible = "lvds-connector"; ++ ++ width-mm = <210>; ++ height-mm = <158>; ++ ++ panel-timing { ++ /* 1280x800 @60Hz */ ++ clock-frequency = <65000000>; ++ hactive = <1280>; ++ vactive = <800>; ++ hsync-len = <40>; ++ hfront-porch = <80>; ++ hback-porch = <40>; ++ vfront-porch = <14>; ++ vback-porch = <14>; ++ vsync-len = <4>; ++ }; ++ ++ port { ++ lvds_in: endpoint { ++ remote-endpoint = <&lvds_enc_out>; ++ }; ++ }; ++ }; ++ ++ radio: si468x@0 { ++ compatible = "si,si468x-pcm"; ++ status = "okay"; ++ ++ #sound-dai-cells = <0>; ++ }; ++}; ++ ++&pfc { ++ hscif4_pins: hscif4 { ++ groups = "hscif4_data_a", "hscif4_ctrl"; ++ function = "hscif4"; ++ }; ++ ++ sdhi3_pins_3v3: sd3_3v3 { ++ groups = "sdhi3_data4", "sdhi3_ctrl"; ++ function = "sdhi3"; ++ power-source = <3300>; ++ }; ++ ++ sound_0_pins: sound0 { ++ groups = "ssi78_ctrl", "ssi7_data", "ssi8_data"; ++ function = "ssi"; ++ }; ++ ++ sound_1_pins: sound1 { ++ groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; ++ function = "ssi"; ++ }; ++ ++ sound_2_pins: sound2 { ++ groups = "ssi6_ctrl", "ssi6_data"; ++ function = "ssi"; ++ }; ++ ++ usb0_pins: usb0 { ++ groups = "usb0"; ++ function = "usb0"; ++ }; ++ ++ can0_pins: can0 { ++ groups = "can0_data_a"; ++ function = "can0"; ++ }; ++ ++ can1_pins: can1 { ++ groups = "can1_data"; ++ function = "can1"; ++ }; ++ ++ canfd0_pins: canfd0 { ++ groups = "canfd0_data_a"; ++ function = "canfd0"; ++ }; ++ ++ canfd1_pins: canfd1 { ++ groups = "canfd1_data"; ++ function = "canfd1"; ++ }; ++}; ++ ++&du { ++ ports { ++ port@3 { ++ endpoint { ++ remote-endpoint = <&lvds_enc_in>; ++ }; ++ }; ++ }; ++}; ++ ++&gpio0 { ++ video_a_irq { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A irq"; ++ }; ++ ++ video_b_irq { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B irq"; ++ }; ++ ++ gpioext_2_20_irq { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "0x20@i2c2 irq"; ++ }; ++}; ++ ++&gpio1 { ++ gpioext_2_21_irq { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "0x21@i2c2 irq"; ++ }; ++ ++ wifi_irq { ++ gpio-hog; ++ gpios = <25 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "wifi irq"; ++ }; ++}; ++ ++&gpio5 { ++ touch_irq { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "touch irq"; ++ }; ++ ++ /* From TI forum */ ++ /* BT_AUD_OUT should be pulled low when WL_EN is activated. */ ++ /* in case it isn't, wilink8 ends up in one of the test modes that introduces various issues */ ++ bt_strap { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "BT strap pin"; ++ }; ++}; ++ ++&gpio7 { ++ gpioext_2_21_irq { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "0x21@i2c4 irq"; ++ }; ++}; ++ ++&hscif4 { ++ pinctrl-0 = <&hscif4_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ ++ status = "okay"; ++}; ++ ++&i2c2 { ++ clock-frequency = <400000>; ++ ++ gpio_ext_20: pca9535@20 { ++ compatible = "nxp,pca9535"; ++ reg = <0x20>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio0>; ++ interrupts = <15 IRQ_TYPE_EDGE_FALLING>; ++ }; ++ ++ gpio_ext_21: pca9535@21 { ++ compatible = "nxp,pca9535"; ++ reg = <0x21>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio1>; ++ interrupts = <15 IRQ_TYPE_EDGE_FALLING>; ++ }; ++ ++ i2cswitch2: pca9548@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x74>; ++ reset-gpios = <&gpio6 5 GPIO_ACTIVE_LOW>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ /* BCM node(s) */ ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ /* USB3.0 HUB node(s) */ ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ /* Power amp node(s) */ ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ /* Radio node(s) */ ++ }; ++ ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ /* A2B node(s) */ ++ }; ++ ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ /* PCIe node(s) */ ++ }; ++ ++ i2c@6 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <6>; ++ /* LVDS display node(s) */ ++ ++ polytouch: edt-ft5x06@38 { ++ compatible = "edt,edt-ft5x06"; ++ reg = <0x38>; ++ interrupt-parent = <&gpio5>; ++ interrupts = <6 IRQ_TYPE_EDGE_FALLING>; ++ }; ++ }; ++ ++ i2c@7 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <7>; ++ /* Audio, GPS and Gyro node(s) */ ++ ++ pcm3168a: audio-codec@44 { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm3168a"; ++ reg = <0x44>; ++ clocks = <&snd_clk>; ++ clock-names = "scki"; ++ tdm; ++ VDD1-supply = <&codec_en_reg>; ++ VDD2-supply = <&codec_en_reg>; ++ VCCAD1-supply = <&codec_en_reg>; ++ VCCAD2-supply = <&codec_en_reg>; ++ VCCDA1-supply = <&_en_reg>; ++ VCCDA2-supply = <&_en_reg>; ++ }; ++ ++ lsm9ds0_acc_mag@1d { ++ compatible = "st,lsm9ds0_accel_magn"; ++ reg = <0x1d>; ++ }; ++ ++ lsm9ds0_gyr@6b { ++ compatible = "st,lsm9ds0_gyro"; ++ reg = <0x6b>; ++ }; ++ ++ /* GPS@ 0x42 */ ++ }; ++ }; ++}; ++ ++&i2c4 { ++ gpio_ext_22: pca9535@21 { ++ compatible = "nxp,pca9535"; ++ reg = <0x22>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio7>; ++ interrupts = <3 IRQ_TYPE_EDGE_FALLING>; ++ ++ cmos_pwdn { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CMOS PWDN"; ++ }; ++ cmos_rst { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CMOS RST"; ++ }; ++ /* pin 12 - CAM_CLK */ ++ rpi_cam_io_1 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "RaspB_IO1"; ++ }; ++ /* pin 11 - CAM_GPIO - assume pwdn */ ++ rpi_cam_io_0 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "RaspB_IO0"; ++ }; ++ }; ++ ++ i2cswitch4: pca9548@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x74>; ++ reset-gpios= <&gpio6 21 GPIO_ACTIVE_LOW>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ /* SAM node(s) */ ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ /* Slot A (CN10) */ ++ ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ ov106xx_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ ov106xx_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; ++ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ ov106xx_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ ov106xx_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; ++ ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ ov106xx_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ ov106xx_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@0 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti964_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti964_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ ti964_des0ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ ti964_des0ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ ti964_csi0ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@0 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_a_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti954_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti954_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ ti954_csi0ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ /* MAX9286 @ 0x2c */ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ /* Slot B (CN11) */ ++ ++ ov106xx@4 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x64>; ++ ++ port@0 { ++ ov106xx_in4: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin4ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ ov106xx_ti964_des1ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep0>; ++ }; ++ ov106xx_ti954_des1ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@5 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x65>; ++ ++ port@0 { ++ ov106xx_in5: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin5ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ ov106xx_ti964_des1ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep1>; ++ }; ++ ov106xx_ti954_des1ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@6 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x66>; ++ ++ port@0 { ++ ov106xx_in6: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin6ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ ov106xx_ti964_des1ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@7 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x67>; ++ ++ port@0 { ++ ov106xx_in7: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin7ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ ov106xx_ti964_des1ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep3>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@1 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti964_des1ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ ti964_des1ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ ti964_des1ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ ti964_des1ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ ti964_csi2ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@1 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_b_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti954_des1ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ ti954_des1ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ }; ++ port@1 { ++ ti954_csi2ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ ++ /* MAX9286 @ 0x2c */ ++ max9286-max9271@1 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des1ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ max9286_des1ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ max9286_des1ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ max9286_des1ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ max9286_csi2ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ /* MOST node(s) */ ++ }; ++ ++ i2c@6 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <6>; ++ /* Slot B (CN11) */ ++ ++ video_b_ext0: pca9535@27 { ++ compatible = "nxp,pca9535"; ++ reg = <0x27>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_b_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg1"; ++ }; ++ video_b_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg0"; ++ }; ++ video_b_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR_SHDN"; ++ }; ++ video_b_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR0"; ++ }; ++ video_b_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR1"; ++ }; ++ video_b_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR2"; ++ }; ++ video_b_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR3"; ++ }; ++ video_b_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B DES_SHDN"; ++ }; ++ video_b_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B led"; ++ }; ++ }; ++ ++ video_b_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_b_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg2"; ++ }; ++ video_b_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg1"; ++ }; ++ video_b_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg0"; ++ }; ++ video_b_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR_SHDN"; ++ }; ++ video_b_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR0"; ++ }; ++ video_b_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR1"; ++ }; ++ video_b_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR2"; ++ }; ++ video_b_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR3"; ++ }; ++ video_b_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B DES_SHDN"; ++ }; ++ video_b_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B LED"; ++ }; ++ }; ++ }; ++ ++ i2c@7 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <7>; ++ /* Slot A (CN10) */ ++ ++ video_a_ext0: pca9535@26 { ++ compatible = "nxp,pca9535"; ++ reg = <0x26>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; ++ }; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; ++ }; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; ++ }; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A led"; ++ }; ++ }; ++ ++ video_a_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg2"; ++ }; ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; ++ }; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; ++ }; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; ++ }; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A LED"; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&pcie_bus_clk { ++ clock-frequency = <100000000>; ++ status = "okay"; ++}; ++ ++&pciec0 { ++ status = "okay"; ++}; ++ ++&pciec1 { ++ status = "okay"; ++}; ++ ++&vin0 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ vin0_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ vin0_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ vin1_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ vin1_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin2 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ vin2_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin3 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ vin3_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&vin4 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi41"; ++ virtual,channel = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin4_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ vin4_ti964_des1ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep0>; ++ }; ++ vin4_ti954_des1ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin5 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin5ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep1: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin5_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ vin5_ti964_des1ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep1>; ++ }; ++ vin5_ti954_des1ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin6 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin6ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <2>; ++ remote-endpoint = <&ov106xx_in6>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep2: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin6_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ vin6_ti964_des1ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin7 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin7ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <3>; ++ remote-endpoint = <&ov106xx_in7>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep3: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin7_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ vin7_ti964_des1ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&csi2_40 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&csi2_41 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_41_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&rcar_sound { ++ pinctrl-0 = <&sound_clk_pins>; ++ ++ /* Multi DAI */ ++ #sound-dai-cells = <1>; ++ ++ rcar_sound,dai { ++ dai0 { ++ playback = <&ssi7>; ++ capture = <&ssi8>; ++ }; ++ ++ dai1 { ++ playback = <&ssi0 &src0 &dvc0>; ++ capture = <&ssi1 &src1 &dvc1>; ++ }; ++ ++ dai2 { ++ capture = <&ssi6>; ++ }; ++ }; ++}; ++ ++&sdhi3 { ++ pinctrl-0 = <&sdhi3_pins_3v3>; ++ pinctrl-names = "default"; ++ ++ vmmc-supply = <&wlan_en>; ++ vqmmc-supply = <&vccq_sdhi3>; ++ keep-power-in-suspend; ++ enable-sdio-wakeup; ++ bus-width = <4>; ++ no-1-8-v; ++ non-removable; ++ cap-power-off-card; ++ max-frequency = <26000000>; ++ status = "okay"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ wlcore: wlcore@2 { ++ compatible = "ti,wl1837"; ++ reg = <2>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <25 IRQ_TYPE_EDGE_RISING>; ++ }; ++}; ++ ++&usb2_phy0 { ++ pinctrl-0 = <&usb0_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&hsusb0 { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&xhci0 { ++ status = "okay"; ++}; ++ ++&msiof1 { ++ status = "disabled"; ++}; ++ ++&can0 { ++ pinctrl-0 = <&can0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; ++}; ++ ++&can1 { ++ pinctrl-0 = <&can1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; ++}; ++ ++&canfd { ++ pinctrl-0 = <&canfd0_pins &canfd1_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ ++ channel0 { ++ status = "okay"; ++ }; ++ ++ channel1 { ++ status = "okay"; ++ }; ++}; ++ ++&ssi8 { ++ shared-pin; ++}; ++ ++/* uncomment to enable CN47: SD on SDHI3 */ ++//#include "../ulcb-kf-sd3.dtsi" ++/* CN48 (Raspberry Pi) on VIN4 */ ++//#include "ulcb-kf-rpi.dtsi" ++/* CN29: (CMOS camera) on VIN5 */ ++//#include "ulcb-kf-cmos.dtsi" +diff --git a/arch/arm64/boot/dts/renesas/legacy/r8a7795-h3ulcb-kf-v1.dts b/arch/arm64/boot/dts/renesas/legacy/r8a7795-h3ulcb-kf-v1.dts +new file mode 100644 +index 0000000..14b6f52 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/legacy/r8a7795-h3ulcb-kf-v1.dts +@@ -0,0 +1,465 @@ ++/* ++ * Device Tree Source for the H3ULCB Kingfisher V1 board ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7795-h3ulcb-kf-v0.dts" ++ ++/ { ++ model = "Renesas H3ULCB Kingfisher V1 board based on r8a7795"; ++ ++ aliases { ++ serial1 = &hscif0; ++ serial2 = &hscif1; ++ serial3 = &scif1; ++ }; ++ ++ wlan_en: regulator@4 { ++ compatible = "regulator-fixed"; ++ regulator-name = "wlan-en-regulator"; ++ ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_74 4 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ codec_en_reg: regulator@6 { ++ compatible = "regulator-fixed"; ++ regulator-name = "codec-en-regulator"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_74 15 0>; ++ ++ /* delay - CHECK */ ++ startup-delay-us = <70000>; ++ enable-active-high; ++ }; ++ ++ amp_en_reg: regulator@7 { ++ compatible = "regulator-fixed"; ++ regulator-name = "amp-en-regulator"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_74 0 0>; ++ ++ startup-delay-us = <0>; ++ enable-active-high; ++ }; ++ ++ /delete-node/regulator@8; ++ ++ sdio_switch: regulator@9 { ++ compatible = "regulator-fixed"; ++ regulator-name = "wifi_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_74 5 0>; ++ enable-active-low; ++ regulator-always-on; ++ }; ++ ++ /delete-node/regulator@10; ++ ++ radio_switch: regulator@11 { ++ compatible = "regulator-fixed"; ++ regulator-name = "radio_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_74 13 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ mpcie_3v3: regulator@12 { ++ compatible = "regulator-fixed"; ++ regulator-name = "mPCIe 3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_77 14 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ mpcie_1v8: regulator@13 { ++ compatible = "regulator-fixed"; ++ regulator-name = "mPCIe 1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ gpio = <&gpio_ext_77 15 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <200000>; ++ enable-active-high; ++ }; ++ ++ kim { ++ shutdown-gpios = <&gpio_ext_74 3 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ hdmi-out { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con: endpoint { ++ remote-endpoint = <&adv7513_out>; ++ }; ++ }; ++ }; ++}; ++ ++&pfc { ++ /delete-node/hscif4; ++ ++ scif1_pins: scif1 { ++ groups = "scif1_data_b"; ++ function = "scif1"; ++ }; ++ ++ hscif0_pins: hscif0 { ++ groups = "hscif0_data", "hscif0_ctrl"; ++ function = "hscif0"; ++ }; ++ ++ hscif1_pins: hscif1 { ++ groups = "hscif1_data_a", "hscif1_ctrl_a"; ++ function = "hscif1"; ++ }; ++ ++ du_pins: du { ++ groups = "du_rgb888", "du_sync", "du_clk_out_0", "du_disp"; ++ function = "du"; ++ }; ++}; ++ ++&du { ++ pinctrl-0 = <&du_pins>; ++ pinctrl-names = "default"; ++ ++ ports { ++ port@0 { ++ endpoint { ++ remote-endpoint = <&adv7513_in>; ++ }; ++ }; ++ }; ++}; ++ ++&gpio0 { ++ /delete-node/video_a_irq; ++ /delete-node/video_b_irq; ++ /delete-node/gpioext_2_20_irq; ++}; ++ ++&gpio1 { ++ /delete-node/gpioext_2_21_irq; ++ /delete-node/wifi_irq; ++}; ++ ++&gpio2 { ++ bl_pwm { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "BL PWM 100%"; ++ }; ++}; ++ ++&gpio5 { ++ /delete-node/touch_irq; ++ /delete-node/bt_strap; ++}; ++ ++&gpio7 { ++ /delete-node/gpioext_2_21_irq; ++}; ++ ++&scif1 { ++ pinctrl-0 = <&scif1_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&hscif0 { ++ pinctrl-0 = <&hscif0_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ ++ status = "okay"; ++}; ++ ++&hscif1 { ++ pinctrl-0 = <&hscif1_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&hscif4 { ++ /delete-property/pinctrl-0; ++ /delete-property/pinctrl-names; ++ ++ status = "disabled"; ++}; ++ ++&i2c2 { ++ /delete-node/pca9535@20; ++ /delete-node/pca9535@21; ++ ++ gpio_ext_74: pca9539@74 { ++ compatible = "nxp,pca9539"; ++ reg = <0x74>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio6>; ++ interrupts = <8 IRQ_TYPE_EDGE_FALLING>; ++ ++ hub_pwen { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "HUB pwen"; ++ }; ++ hub_rst { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "HUB rst"; ++ }; ++ otg_offvbus { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "OTG off VBUSn"; ++ }; ++ otg_extlpn { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "OTG EXTLPn"; ++ }; ++ otg_stat1 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "OTG Stat1"; ++ }; ++ otg_stat2 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "OTG Stat2"; ++ }; ++ }; ++ ++ gpio_ext_75: pca9539@75 { ++ compatible = "nxp,pca9539"; ++ reg = <0x75>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio6>; ++ interrupts = <4 IRQ_TYPE_EDGE_FALLING>; ++ ++ gps_rst { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "GPS rst"; ++ }; ++ fpdl_shdn { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "FPDLink shdn"; ++ }; ++ }; ++}; ++ ++&i2cswitch2 { ++ reg = <0x71>; ++ reset-gpios= <&gpio5 3 GPIO_ACTIVE_LOW>; ++ ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ ++ hdmi@3d { ++ compatible = "adi,adv7511w"; ++ reg = <0x3d>; ++// interrupt-parent = <&gpio2>; ++// interrupts = <0 IRQ_TYPE_EDGE_BOTH>; ++ pd-gpios = <&gpio_ext_75 5 GPIO_ACTIVE_LOW>; ++ ++ adi,input-depth = <8>; ++ adi,input-colorspace = "rgb"; ++ adi,input-clock = "1x"; ++ adi,input-style = <1>; ++ adi,input-justification = "evenly"; ++ adi,clock-delay = <1200>; ++ adi,clock-max-rate = <100000>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ adv7513_in: endpoint { ++ remote-endpoint = <&du_out_rgb>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ adv7513_out: endpoint { ++ remote-endpoint = <&hdmi_con>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c4 { ++ /delete-node/pca9535@21; ++ ++ gpio_ext_76: pca9539@76 { ++ compatible = "nxp,pca9539"; ++ reg = <0x76>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio7>; ++ interrupts = <3 IRQ_TYPE_EDGE_FALLING>; ++ ++ port_b_a0 { ++ gpio-hog; ++ gpios = <0 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B A0"; ++ }; ++ port_b_a1 { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B A1"; ++ }; ++ port_a_a0 { ++ gpio-hog; ++ gpios = <2 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A A0"; ++ }; ++ port_a_a1 { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A A1"; ++ }; ++ cmos_pwdn { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CMOS PWDN"; ++ }; ++ cmos_rst { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CMOS RST"; ++ }; ++ /* pin 12 - CAM_CLK */ ++ rpi_cam_io_1 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "RaspB_IO1"; ++ }; ++ /* pin 11 - CAM_GPIO - assume pwdn */ ++ rpi_cam_io_0 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "RaspB_IO0"; ++ }; ++ sam_rst { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "SAM RST"; ++ }; ++ sam_pwr { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "SAM PWR"; ++ }; ++ /* 0 - FPDLink output, 1 - LVDS output */ ++ lvds_vs_fpdl { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "LVDS switch"; ++ }; ++ }; ++ ++ gpio_ext_77: pca9539@77 { ++ compatible = "nxp,pca9539"; ++ reg = <0x77>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio5>; ++ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; ++ ++ mpcie_wake { ++ gpio-hog; ++ gpios = <0 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "mPCIe WAKE#"; ++ }; ++ mpcie_wdisable { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "mPCIe W_DISABLE"; ++ }; ++ mpcie_clreq { ++ gpio-hog; ++ gpios = <2 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "mPCIe CLKREQ#"; ++ }; ++ mpcie_ovc { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "mPCIe OVC"; ++ }; ++ }; ++}; ++ ++&i2cswitch4 { ++ reg = <0x71>; ++ reset-gpios= <&gpio3 15 GPIO_ACTIVE_LOW>; ++}; ++ ++&wlcore { ++ interrupts = <25 IRQ_TYPE_EDGE_FALLING>; ++}; ++ ++&pciec1 { ++ pcie3v3-supply = <&mpcie_3v3>; ++ pcie1v8-supply = <&mpcie_1v8>; ++}; +diff --git a/arch/arm64/boot/dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts b/arch/arm64/boot/dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts +new file mode 100644 +index 0000000..7be2370 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts +@@ -0,0 +1,1214 @@ ++/* ++ * Device Tree Source for the M3ULCB Kingfisher V0 board on r8a7796 ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "../r8a7796-m3ulcb.dts" ++ ++/ { ++ model = "Renesas M3ULCB Kingfisher V0 board based on r8a7796"; ++ ++ aliases { ++ serial1 = &hscif4; ++ }; ++ ++ snd_clk: snd_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24576000>; ++ clock-output-names = "scki"; ++ }; ++ ++ wlan_en: regulator@4 { ++ compatible = "regulator-fixed"; ++ regulator-name = "wlan-en-regulator"; ++ ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_20 4 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ vcc_sdhi3: regulator@41 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "SDHI3 Vcc"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ vccq_sdhi3: regulator@5 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "SDHI3 VccQ"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ codec_en_reg: regulator@6 { ++ compatible = "regulator-fixed"; ++ regulator-name = "codec-en-regulator"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_20 15 0>; ++ ++ /* delay - CHECK */ ++ startup-delay-us = <70000>; ++ enable-active-high; ++ }; ++ ++ amp_en_reg: regulator@7 { ++ compatible = "regulator-fixed"; ++ regulator-name = "amp-en-regulator"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_20 0 0>; ++ ++ startup-delay-us = <0>; ++ enable-active-high; ++ }; ++ ++ lvds_switch: regulator@8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "lvds_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ /* gpio = <&gpio1 24 0>; */ ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ sdio_switch: regulator@9 { ++ compatible = "regulator-fixed"; ++ regulator-name = "wifi_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_20 5 0>; ++ enable-active-low; ++ regulator-always-on; ++ }; ++ ++ sound_switch: regulator@10 { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcm3168a_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_21 5 0>; ++ enable-active-low; ++ regulator-always-on; ++ }; ++ ++ radio_switch: regulator@11 { ++ compatible = "regulator-fixed"; ++ regulator-name = "radio_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_20 13 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ kim { ++ compatible = "kim"; ++ shutdown-gpios = <&gpio_ext_20 3 GPIO_ACTIVE_HIGH>; ++ /* serial1 */ ++ dev_name = "/dev/ttySC1"; ++ flow_cntrl = <1>; ++ /* int div 8 hscif@26.6666656MHz */ ++ baud_rate = <3333332>; ++ }; ++ ++ btwilink { ++ compatible = "btwilink"; ++ }; ++ ++ sound_ext: sound@0 { ++ pinctrl-0 = <&sound_0_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; ++ ++ simple-audio-card,format = "left_j"; ++ simple-audio-card,name = "pcm3168a"; ++ ++ simple-audio-card,bitclock-master = <&sound_ext_master>; ++ simple-audio-card,frame-master = <&sound_ext_master>; ++ sound_ext_master: simple-audio-card,cpu@0 { ++ sound-dai = <&rcar_sound 0>; ++ dai-tdm-slot-num = <8>; ++ dai-tdm-slot-width = <32>; ++ }; ++ ++ simple-audio-card,codec@0 { ++ sound-dai = <&pcm3168a>; ++ dai-tdm-slot-num = <8>; ++ dai-tdm-slot-width = <32>; ++ system-clock-frequency = <24576000>; ++ }; ++ }; ++ ++ /delete-node/sound; ++ ++ rsnd_ak4613: sound@1 { ++ pinctrl-0 = <&sound_1_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; ++ ++ simple-audio-card,format = "left_j"; ++ simple-audio-card,name = "ak4613"; ++ ++ simple-audio-card,bitclock-master = <&sndcpu>; ++ simple-audio-card,frame-master = <&sndcpu>; ++ ++ sndcpu: simple-audio-card,cpu@1 { ++ sound-dai = <&rcar_sound 1>; ++ }; ++ ++ sndcodec: simple-audio-card,codec@1 { ++ sound-dai = <&ak4613>; ++ }; ++ }; ++ ++ sound_radio: sound@2 { ++ pinctrl-0 = <&sound_2_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; ++ ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "radio"; ++ ++ simple-audio-card,bitclock-master = <&sound_radio_master>; ++ simple-audio-card,frame-master = <&sound_radio_master>; ++ simple-audio-card,cpu@2 { ++ sound-dai = <&rcar_sound 2>; ++ }; ++ ++ sound_radio_master: simple-audio-card,codec@2 { ++ sound-dai = <&radio>; ++ system-clock-frequency = <12288000>; ++ }; ++ }; ++ ++ lvds-encoder { ++ compatible = "thine,thc63lvdm83d"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port@0 { ++ reg = <0>; ++ lvds_enc_in: endpoint { ++ remote-endpoint = <&du_out_lvds0>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ lvds_enc_out: endpoint { ++ remote-endpoint = <&lvds_in>; ++ }; ++ }; ++ }; ++ }; ++ ++ lvds { ++ compatible = "lvds-connector"; ++ ++ width-mm = <210>; ++ height-mm = <158>; ++ ++ panel-timing { ++ /* 1280x800 @60Hz */ ++ clock-frequency = <65000000>; ++ hactive = <1280>; ++ vactive = <800>; ++ hsync-len = <40>; ++ hfront-porch = <80>; ++ hback-porch = <40>; ++ vfront-porch = <14>; ++ vback-porch = <14>; ++ vsync-len = <4>; ++ }; ++ ++ port { ++ lvds_in: endpoint { ++ remote-endpoint = <&lvds_enc_out>; ++ }; ++ }; ++ }; ++ ++ radio: si468x@0 { ++ compatible = "si,si468x-pcm"; ++ status = "okay"; ++ ++ #sound-dai-cells = <0>; ++ }; ++}; ++ ++&pfc { ++ hscif4_pins: hscif4 { ++ groups = "hscif4_data_a", "hscif4_ctrl"; ++ function = "hscif4"; ++ }; ++ ++ sdhi3_pins_3v3: sd3_3v3 { ++ groups = "sdhi3_data4", "sdhi3_ctrl"; ++ function = "sdhi3"; ++ power-source = <3300>; ++ }; ++ ++ sound_0_pins: sound0 { ++ groups = "ssi78_ctrl", "ssi7_data", "ssi8_data"; ++ function = "ssi"; ++ }; ++ ++ sound_1_pins: sound1 { ++ groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data_a"; ++ function = "ssi"; ++ }; ++ ++ sound_2_pins: sound2 { ++ groups = "ssi6_ctrl", "ssi6_data"; ++ function = "ssi"; ++ }; ++ ++ usb0_pins: usb0 { ++ groups = "usb0"; ++ function = "usb0"; ++ }; ++ ++ can0_pins: can0 { ++ groups = "can0_data_a"; ++ function = "can0"; ++ }; ++ ++ can1_pins: can1 { ++ groups = "can1_data"; ++ function = "can1"; ++ }; ++ ++ canfd0_pins: canfd0 { ++ groups = "canfd0_data_a"; ++ function = "canfd0"; ++ }; ++ ++ canfd1_pins: canfd1 { ++ groups = "canfd1_data"; ++ function = "canfd1"; ++ }; ++}; ++ ++&du { ++ ports { ++ port@2 { ++ endpoint { ++ remote-endpoint = <&lvds_enc_in>; ++ }; ++ }; ++ }; ++}; ++ ++&gpio0 { ++ video_a_irq { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A irq"; ++ }; ++ ++ video_b_irq { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B irq"; ++ }; ++ ++ gpioext_2_20_irq { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "0x20@i2c2 irq"; ++ }; ++}; ++ ++&gpio1 { ++ gpioext_2_21_irq { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "0x21@i2c2 irq"; ++ }; ++ ++ wifi_irq { ++ gpio-hog; ++ gpios = <25 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "wifi irq"; ++ }; ++}; ++ ++&gpio5 { ++ touch_irq { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "touch irq"; ++ }; ++ ++ /* From TI forum */ ++ /* BT_AUD_OUT should be pulled low when WL_EN is activated. */ ++ /* in case it isn't, wilink8 ends up in one of the test modes that introduces various issues */ ++ bt_strap { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "BT strap pin"; ++ }; ++}; ++ ++&gpio7 { ++ gpioext_2_21_irq { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "0x21@i2c4 irq"; ++ }; ++}; ++ ++&hscif4 { ++ pinctrl-0 = <&hscif4_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ ++ status = "okay"; ++}; ++ ++&i2c2 { ++ clock-frequency = <400000>; ++ ++ gpio_ext_20: pca9535@20 { ++ compatible = "nxp,pca9535"; ++ reg = <0x20>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio0>; ++ interrupts = <15 IRQ_TYPE_EDGE_FALLING>; ++ }; ++ ++ gpio_ext_21: pca9535@21 { ++ compatible = "nxp,pca9535"; ++ reg = <0x21>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio1>; ++ interrupts = <15 IRQ_TYPE_EDGE_FALLING>; ++ }; ++ ++ i2cswitch2: pca9548@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x74>; ++ reset-gpios = <&gpio6 5 GPIO_ACTIVE_LOW>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ /* BCM node(s) */ ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ /* USB3.0 HUB node(s) */ ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ /* Power amp node(s) */ ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ /* Radio node(s) */ ++ }; ++ ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ /* A2B node(s) */ ++ }; ++ ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ /* PCIe node(s) */ ++ }; ++ ++ i2c@6 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <6>; ++ /* LVDS display node(s) */ ++ ++ polytouch: edt-ft5x06@38 { ++ compatible = "edt,edt-ft5x06"; ++ reg = <0x38>; ++ interrupt-parent = <&gpio5>; ++ interrupts = <6 IRQ_TYPE_EDGE_FALLING>; ++ }; ++ }; ++ ++ i2c@7 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <7>; ++ /* Audio, GPS and Gyro node(s) */ ++ ++ pcm3168a: audio-codec@44 { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm3168a"; ++ reg = <0x44>; ++ clocks = <&snd_clk>; ++ clock-names = "scki"; ++ tdm; ++ VDD1-supply = <&codec_en_reg>; ++ VDD2-supply = <&codec_en_reg>; ++ VCCAD1-supply = <&codec_en_reg>; ++ VCCAD2-supply = <&codec_en_reg>; ++ VCCDA1-supply = <&_en_reg>; ++ VCCDA2-supply = <&_en_reg>; ++ }; ++ ++ lsm9ds0_acc_mag@1d { ++ compatible = "st,lsm9ds0_accel_magn"; ++ reg = <0x1d>; ++ }; ++ ++ lsm9ds0_gyr@6b { ++ compatible = "st,lsm9ds0_gyro"; ++ reg = <0x6b>; ++ }; ++ ++ /* GPS@ 0x42 */ ++ }; ++ }; ++}; ++ ++&i2c4 { ++ gpio_ext_22: pca9535@21 { ++ compatible = "nxp,pca9535"; ++ reg = <0x22>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio7>; ++ interrupts = <3 IRQ_TYPE_EDGE_FALLING>; ++ ++ cmos_pwdn { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CMOS PWDN"; ++ }; ++ cmos_rst { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CMOS RST"; ++ }; ++ /* pin 12 - CAM_CLK */ ++ rpi_cam_io_1 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "RaspB_IO1"; ++ }; ++ /* pin 11 - CAM_GPIO - assume pwdn */ ++ rpi_cam_io_0 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "RaspB_IO0"; ++ }; ++ }; ++ ++ i2cswitch4: pca9548@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x74>; ++ reset-gpios= <&gpio6 21 GPIO_ACTIVE_LOW>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ /* SAM node(s) */ ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ /* Slot A (CN10) */ ++ ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ ov106xx_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ ov106xx_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; ++ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ ov106xx_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ ov106xx_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; ++ ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ ov106xx_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ ov106xx_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@0 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti964_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti964_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ ti964_des0ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ ti964_des0ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ ti964_csi0ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@0 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_a_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti954_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti954_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ ti954_csi0ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ /* MAX9286 @ 0x2c */ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ /* MOST node(s) */ ++ }; ++ ++ i2c@7 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <7>; ++ /* Slot A (CN10) */ ++ ++ video_a_ext0: pca9535@26 { ++ compatible = "nxp,pca9535"; ++ reg = <0x26>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; ++ }; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; ++ }; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; ++ }; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A led"; ++ }; ++ }; ++ ++ video_a_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg2"; ++ }; ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; ++ }; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; ++ }; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; ++ }; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A LED"; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&pcie_bus_clk { ++ clock-frequency = <100000000>; ++ status = "okay"; ++}; ++ ++&pciec0 { ++ status = "okay"; ++}; ++ ++&pciec1 { ++ status = "okay"; ++}; ++ ++&vin0 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ vin0_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ vin0_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ vin1_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ vin1_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin2 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ vin2_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin3 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ vin3_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&csi2_40 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&rcar_sound { ++ pinctrl-0 = <&sound_clk_pins>; ++ ++ /* Multi DAI */ ++ #sound-dai-cells = <1>; ++ ++ rcar_sound,dai { ++ dai0 { ++ playback = <&ssi7>; ++ capture = <&ssi8>; ++ }; ++ ++ dai1 { ++ playback = <&ssi0 &src0 &dvc0>; ++ capture = <&ssi1 &src1 &dvc1>; ++ }; ++ ++ dai2 { ++ capture = <&ssi6>; ++ }; ++ }; ++}; ++ ++&sdhi3 { ++ pinctrl-0 = <&sdhi3_pins_3v3>; ++ pinctrl-names = "default"; ++ ++ vmmc-supply = <&wlan_en>; ++ vqmmc-supply = <&vccq_sdhi3>; ++ keep-power-in-suspend; ++ enable-sdio-wakeup; ++ bus-width = <4>; ++ no-1-8-v; ++ non-removable; ++ cap-power-off-card; ++ max-frequency = <26000000>; ++ status = "okay"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ wlcore: wlcore@2 { ++ compatible = "ti,wl1837"; ++ reg = <2>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <25 IRQ_TYPE_EDGE_RISING>; ++ }; ++}; ++ ++&usb2_phy0 { ++ pinctrl-0 = <&usb0_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&hsusb { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&xhci0 { ++ status = "okay"; ++}; ++ ++&msiof1 { ++ status = "disabled"; ++}; ++ ++&can0 { ++ pinctrl-0 = <&can0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; ++}; ++ ++&can1 { ++ pinctrl-0 = <&can1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; ++}; ++ ++&canfd { ++ pinctrl-0 = <&canfd0_pins &canfd1_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ ++ channel0 { ++ status = "okay"; ++ }; ++ ++ channel1 { ++ status = "okay"; ++ }; ++}; ++ ++&ssi8 { ++ shared-pin; ++}; ++ ++/* uncomment to enable CN47: SD on SDHI3 */ ++//#include "../ulcb-kf-sd3.dtsi" ++/* CN48 (Raspberry Pi) on VIN4 */ ++#include "ulcb-kf-rpi.dtsi" ++/* CN29: (CMOS camera) on VIN5 */ ++#include "ulcb-kf-cmos.dtsi" +diff --git a/arch/arm64/boot/dts/renesas/legacy/r8a7796-m3ulcb-kf-v1.dts b/arch/arm64/boot/dts/renesas/legacy/r8a7796-m3ulcb-kf-v1.dts +new file mode 100644 +index 0000000..637c840 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/legacy/r8a7796-m3ulcb-kf-v1.dts +@@ -0,0 +1,465 @@ ++/* ++ * Device Tree Source for the M3ULCB Kingfisher V1 board ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7796-m3ulcb-kf-v0.dts" ++ ++/ { ++ model = "Renesas M3ULCB Kingfisher V1 board based on r8a7796"; ++ ++ aliases { ++ serial1 = &hscif0; ++ serial2 = &hscif1; ++ serial3 = &scif1; ++ }; ++ ++ wlan_en: regulator@4 { ++ compatible = "regulator-fixed"; ++ regulator-name = "wlan-en-regulator"; ++ ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_74 4 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ codec_en_reg: regulator@6 { ++ compatible = "regulator-fixed"; ++ regulator-name = "codec-en-regulator"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_74 15 0>; ++ ++ /* delay - CHECK */ ++ startup-delay-us = <70000>; ++ enable-active-high; ++ }; ++ ++ amp_en_reg: regulator@7 { ++ compatible = "regulator-fixed"; ++ regulator-name = "amp-en-regulator"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_74 0 0>; ++ ++ startup-delay-us = <0>; ++ enable-active-high; ++ }; ++ ++ /delete-node/regulator@8; ++ ++ sdio_switch: regulator@9 { ++ compatible = "regulator-fixed"; ++ regulator-name = "wifi_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_74 5 0>; ++ enable-active-low; ++ regulator-always-on; ++ }; ++ ++ /delete-node/regulator@10; ++ ++ radio_switch: regulator@11 { ++ compatible = "regulator-fixed"; ++ regulator-name = "radio_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_74 13 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ mpcie_3v3: regulator@12 { ++ compatible = "regulator-fixed"; ++ regulator-name = "mPCIe 3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_77 14 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ mpcie_1v8: regulator@13 { ++ compatible = "regulator-fixed"; ++ regulator-name = "mPCIe 1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ gpio = <&gpio_ext_77 15 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <200000>; ++ enable-active-high; ++ }; ++ ++ kim { ++ shutdown-gpios = <&gpio_ext_74 3 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ hdmi-out { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con: endpoint { ++ remote-endpoint = <&adv7513_out>; ++ }; ++ }; ++ }; ++}; ++ ++&pfc { ++ /delete-node/hscif4; ++ ++ scif1_pins: scif1 { ++ groups = "scif1_data_b"; ++ function = "scif1"; ++ }; ++ ++ hscif0_pins: hscif0 { ++ groups = "hscif0_data", "hscif0_ctrl"; ++ function = "hscif0"; ++ }; ++ ++ hscif1_pins: hscif1 { ++ groups = "hscif1_data_a", "hscif1_ctrl_a"; ++ function = "hscif1"; ++ }; ++ ++ du_pins: du { ++ groups = "du_rgb888", "du_sync", "du_clk_out_0", "du_disp"; ++ function = "du"; ++ }; ++}; ++ ++&du { ++ pinctrl-0 = <&du_pins>; ++ pinctrl-names = "default"; ++ ++ ports { ++ port@0 { ++ endpoint { ++ remote-endpoint = <&adv7513_in>; ++ }; ++ }; ++ }; ++}; ++ ++&gpio0 { ++ /delete-node/video_a_irq; ++ /delete-node/video_b_irq; ++ /delete-node/gpioext_2_20_irq; ++}; ++ ++&gpio1 { ++ /delete-node/gpioext_2_21_irq; ++ /delete-node/wifi_irq; ++}; ++ ++&gpio2 { ++ bl_pwm { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "BL PWM 100%"; ++ }; ++}; ++ ++&gpio5 { ++ /delete-node/touch_irq; ++ /delete-node/bt_strap; ++}; ++ ++&gpio7 { ++ /delete-node/gpioext_2_21_irq; ++}; ++ ++&scif1 { ++ pinctrl-0 = <&scif1_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&hscif0 { ++ pinctrl-0 = <&hscif0_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ ++ status = "okay"; ++}; ++ ++&hscif1 { ++ pinctrl-0 = <&hscif1_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&hscif4 { ++ /delete-property/pinctrl-0; ++ /delete-property/pinctrl-names; ++ ++ status = "disabled"; ++}; ++ ++&i2c2 { ++ /delete-node/pca9535@20; ++ /delete-node/pca9535@21; ++ ++ gpio_ext_74: pca9539@74 { ++ compatible = "nxp,pca9539"; ++ reg = <0x74>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio6>; ++ interrupts = <8 IRQ_TYPE_EDGE_FALLING>; ++ ++ hub_pwen { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "HUB pwen"; ++ }; ++ hub_rst { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "HUB rst"; ++ }; ++ otg_offvbus { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "OTG off VBUSn"; ++ }; ++ otg_extlpn { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "OTG EXTLPn"; ++ }; ++ otg_stat1 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "OTG Stat1"; ++ }; ++ otg_stat2 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "OTG Stat2"; ++ }; ++ }; ++ ++ gpio_ext_75: pca9539@75 { ++ compatible = "nxp,pca9539"; ++ reg = <0x75>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio6>; ++ interrupts = <4 IRQ_TYPE_EDGE_FALLING>; ++ ++ gps_rst { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "GPS rst"; ++ }; ++ fpdl_shdn { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "FPDLink shdn"; ++ }; ++ }; ++}; ++ ++&i2cswitch2 { ++ reg = <0x71>; ++ reset-gpios= <&gpio5 3 GPIO_ACTIVE_LOW>; ++ ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ ++ hdmi@3d { ++ compatible = "adi,adv7511w"; ++ reg = <0x3d>; ++// interrupt-parent = <&gpio2>; ++// interrupts = <0 IRQ_TYPE_EDGE_BOTH>; ++ pd-gpios = <&gpio_ext_75 5 GPIO_ACTIVE_LOW>; ++ ++ adi,input-depth = <8>; ++ adi,input-colorspace = "rgb"; ++ adi,input-clock = "1x"; ++ adi,input-style = <1>; ++ adi,input-justification = "evenly"; ++ adi,clock-delay = <1200>; ++ adi,clock-max-rate = <100000>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ adv7513_in: endpoint { ++ remote-endpoint = <&du_out_rgb>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ adv7513_out: endpoint { ++ remote-endpoint = <&hdmi_con>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c4 { ++ /delete-node/pca9535@21; ++ ++ gpio_ext_76: pca9539@76 { ++ compatible = "nxp,pca9539"; ++ reg = <0x76>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio7>; ++ interrupts = <3 IRQ_TYPE_EDGE_FALLING>; ++ ++ port_b_a0 { ++ gpio-hog; ++ gpios = <0 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B A0"; ++ }; ++ port_b_a1 { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B A1"; ++ }; ++ port_a_a0 { ++ gpio-hog; ++ gpios = <2 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A A0"; ++ }; ++ port_a_a1 { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A A1"; ++ }; ++ cmos_pwdn { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CMOS PWDN"; ++ }; ++ cmos_rst { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CMOS RST"; ++ }; ++ /* pin 12 - CAM_CLK */ ++ rpi_cam_io_1 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "RaspB_IO1"; ++ }; ++ /* pin 11 - CAM_GPIO - assume pwdn */ ++ rpi_cam_io_0 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "RaspB_IO0"; ++ }; ++ sam_rst { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "SAM RST"; ++ }; ++ sam_pwr { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "SAM PWR"; ++ }; ++ /* 0 - FPDLink output, 1 - LVDS output */ ++ lvds_vs_fpdl { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "LVDS switch"; ++ }; ++ }; ++ ++ gpio_ext_77: pca9539@77 { ++ compatible = "nxp,pca9539"; ++ reg = <0x77>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio5>; ++ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; ++ ++ mpcie_wake { ++ gpio-hog; ++ gpios = <0 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "mPCIe WAKE#"; ++ }; ++ mpcie_wdisable { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "mPCIe W_DISABLE"; ++ }; ++ mpcie_clreq { ++ gpio-hog; ++ gpios = <2 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "mPCIe CLKREQ#"; ++ }; ++ mpcie_ovc { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "mPCIe OVC"; ++ }; ++ }; ++}; ++ ++&i2cswitch4 { ++ reg = <0x71>; ++ reset-gpios= <&gpio3 15 GPIO_ACTIVE_LOW>; ++}; ++ ++&wlcore { ++ interrupts = <25 IRQ_TYPE_EDGE_FALLING>; ++}; ++ ++&pciec1 { ++ pcie3v3-supply = <&mpcie_3v3>; ++ pcie1v8-supply = <&mpcie_1v8>; ++}; +diff --git a/arch/arm64/boot/dts/renesas/legacy/r8a7797-v3msk-kf-v0.dts b/arch/arm64/boot/dts/renesas/legacy/r8a7797-v3msk-kf-v0.dts +new file mode 100644 +index 0000000..cc04429 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/legacy/r8a7797-v3msk-kf-v0.dts +@@ -0,0 +1,20 @@ ++/* ++ * Device Tree Source for the V3MSK Kingfisher V0 board on r8a7797 ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "../r8a7797-v3msk-kf.dts" ++ ++/ { ++ model = "Renesas V3MSK Kingfisher V0 board based on r8a7797"; ++}; ++ ++&i2cswitch4 { ++ reg = <0x74>; ++}; +diff --git a/arch/arm64/boot/dts/renesas/legacy/ulcb-kf-cmos.dtsi b/arch/arm64/boot/dts/renesas/legacy/ulcb-kf-cmos.dtsi +new file mode 100644 +index 0000000..2145f5e +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/legacy/ulcb-kf-cmos.dtsi +@@ -0,0 +1,75 @@ ++/* ++ * Device Tree Source for the H3ULCB Kingfisher board: ++ * this adding conflicting resource on VIN5 for CMOS camera ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++/ { ++ camera_clk: camera_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24000000>; ++ clock-output-names = "mclk"; ++ }; ++}; ++ ++&pfc { ++ vin5_pins: vin5 { ++ groups = "vin5_data8", "vin5_sync", "vin5_clk"; ++ function = "vin5"; ++ }; ++}; ++ ++&i2cswitch4 { ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ ++ cmos_camera: ov5642@3c { ++ compatible = "ovti,ov5642"; ++ reg = <0x3c>; ++ clocks = <&camera_clk>; ++ clock-names = "mclk"; ++ ++ port@0 { ++ cmos_camera_in: endpoint { ++ remote-endpoint = <&vin5ep0>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&vin5 { ++ pinctrl-0 = <&vin5_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin5ep0: endpoint@0 { ++ /delete-property/csi,select; ++ /delete-property/virtual,channel; ++ /delete-property/data-lanes; ++ bus-width = <8>; ++ /* #HSYNC, #VSYNC */ ++ vsync-active = <1>; ++ hsync-active = <0>; ++ remote-endpoint = <&cmos_camera_in>; ++ }; ++ }; ++ port@1 { ++ /delete-node/endpoint; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/renesas/legacy/ulcb-kf-rpi.dtsi b/arch/arm64/boot/dts/renesas/legacy/ulcb-kf-rpi.dtsi +new file mode 100644 +index 0000000..bcd9865 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/legacy/ulcb-kf-rpi.dtsi +@@ -0,0 +1,77 @@ ++/* ++ * Device Tree Source for the H3ULCB Kingfisher board: ++ * this adding conflicting resource on VIN4 for Raspberry Pi camera ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++&i2cswitch4 { ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ ++ rpi_camera: ov5647@36 { ++ compatible = "ovti,ov5647"; ++ reg = <0x36>; ++ ++ port@0 { ++ rpi_camera_in: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ remote-endpoint = <&vin4ep0>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&vin4 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi20"; ++ virtual,channel = <0>; ++ remote-endpoint = <&rpi_camera_in>; ++ data-lanes = <1 2>; ++ }; ++ }; ++ port@1 { ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_20_ep>; ++ }; ++ }; ++ }; ++}; ++ ++&csi2_20 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "raw8"; ++ receive,vc = <0>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_20_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ csi-rate = <280>; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had-alfa.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had-alfa.dts +new file mode 100644 +index 0000000..6b13f07 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had-alfa.dts +@@ -0,0 +1,22 @@ ++/* ++ * Device Tree Source for the H3ULCB.HAD board Alfa side on r8a7795 ES1.x ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7795-es1-h3ulcb-had.dtsi" ++ ++/ { ++ model = "Renesas H3ULCB.HAD board Alfa side based on r8a7795"; ++}; ++ ++&pciec0 { ++ status = "okay"; ++ ++ /* Root complex */ ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had-beta.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had-beta.dts +new file mode 100644 +index 0000000..2f8b274 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had-beta.dts +@@ -0,0 +1,23 @@ ++/* ++ * Device Tree Source for the H3ULCB.HAD board Beta side on r8a7795 ES1.x ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7795-es1-h3ulcb-had.dtsi" ++ ++/ { ++ model = "Renesas H3ULCB.HAD board Beta side based on r8a7795"; ++}; ++ ++&pciec0 { ++ status = "okay"; ++ ++ /* Endpoint */ ++ endpoint; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi +new file mode 100644 +index 0000000..d50ff7a +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi +@@ -0,0 +1,225 @@ ++/* ++ * Device Tree Source for the H3ULCB.HAD board on r8a7795 ES1.x ++ * ++ * Copyright (C) 2016-2017 Renesas Electronics Corp. ++ * Copyright (C) 2016-2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++/* ++ * MSIOF0 - /dev/spidev1.0 connected to FPGA ethernet switch (both sides) ++ * MSIOF1 - /dev/spidev2.0 connected to RH850 (sideA to CSIH1, sideB to CSIH0) ++ */ ++ ++#include "r8a7795-es1-h3ulcb-view.dts" ++ ++/ { ++ model = "Renesas H3ULCB.HAD board based on r8a7795"; ++ ++ aliases { ++ serial1 = &scif1; ++ spi1 = &spi0_gpio; ++ spi2 = &spi1_gpio; ++ }; ++ ++ chosen { ++ stdout-path = "serial1:115200n8"; ++ }; ++ ++ spi0_gpio: spi_gpio@0 { ++ compatible = "spi-gpio"; ++ num-chipselects = <1>; ++ gpio-sck = <&gpio5 17 0>; ++ gpio-mosi = <&gpio5 20 0>; ++ gpio-miso = <&gpio5 22 0>; ++ cs-gpios = <&gpio5 19 0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ spidev@0 { ++ compatible = "spi-gpio"; ++ reg = <0>; ++ spi-max-frequency = <2000000>; ++ spi-cpha; ++ spi-cpol; ++ }; ++ }; ++ ++ spi1_gpio: spi_gpio@1 { ++ compatible = "spi-gpio"; ++ num-chipselects = <1>; ++ gpio-sck = <&gpio6 8 0>; ++ gpio-mosi = <&gpio6 7 0>; ++ gpio-miso = <&gpio6 10 0>; ++ cs-gpios = <&gpio6 5 0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ spidev@0 { ++ compatible = "spi-gpio"; ++ reg = <0>; ++ spi-max-frequency = <2000000>; ++ spi-cpha; ++ spi-cpol; ++ }; ++ }; ++ ++ hdmi1-out { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con: endpoint { ++ remote-endpoint = <&rcar_dw_hdmi1_out>; ++ }; ++ }; ++ }; ++}; ++ ++&du { ++ ports { ++ port@1 { ++ endpoint { ++ remote-endpoint = <&rcar_dw_hdmi0_in>; ++ }; ++ }; ++ port@2 { ++ endpoint { ++ remote-endpoint = <&rcar_dw_hdmi1_in>; ++ }; ++ }; ++ }; ++}; ++ ++&hdmi1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port@0 { ++ reg = <0>; ++ rcar_dw_hdmi1_in: endpoint { ++ remote-endpoint = <&du_out_hdmi1>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ rcar_dw_hdmi1_out: endpoint { ++ remote-endpoint = <&hdmi1_con>; ++ }; ++ }; ++ }; ++}; ++ ++&pfc { ++ scif1_pins: scif1 { ++ groups = "scif1_data_a"; ++ function = "scif1"; ++ }; ++ ++ msiof0_pins: spi1 { ++ groups = "msiof0_clk", "msiof0_rxd", "msiof0_txd", ++ "msiof0_ss1"; ++ function = "msiof0"; ++ }; ++ ++ msiof1_pins: spi2 { ++ groups = "msiof1_clk_a", "msiof1_rxd_a", "msiof1_txd_a", ++ "msiof1_ss1_a"; ++ function = "msiof1"; ++ }; ++ ++ sound_clk_pins: sound-clk { ++ groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", ++ "audio_clkout_a" /*, "audio_clkout3_a"*/; ++ function = "audio_clk"; ++ }; ++ ++ usb31_pins: usb31 { ++ groups = "usb31"; ++ function = "usb31"; ++ }; ++ ++ can0_pins: can0 { ++ groups = "can0_data_a"; ++ function = "can0"; ++ }; ++ ++ canfd0_pins: canfd0 { ++ groups = "canfd0_data_a"; ++ function = "canfd0"; ++ }; ++}; ++ ++&scif1 { ++ pinctrl-0 = <&scif1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&avb { ++ /delete-property/phy-handle; ++ /delete-property/phy-gpios; ++ /delete-node/ethernet-phy@0; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++}; ++ ++&msiof0 { ++ pinctrl-0 = <&msiof0_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ cs-gpios = <&gpio5 19 0>; ++ ++ spidev@0 { ++ compatible = "renesas,sh-msiof"; ++ reg = <0>; ++ spi-max-frequency = <66666666>; ++ spi-cpha; ++ spi-cpol; ++ }; ++}; ++ ++&msiof1 { ++ status = "disabled"; ++ cs-gpios = <&gpio6 5 0>; ++}; ++ ++&can0 { ++ pinctrl-0 = <&can0_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ ++ renesas,can-clock-select = <0x0>; ++ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH /* enable - shared with camera board */ ++ &gpio2 7 GPIO_ACTIVE_LOW /* standby */ ++ >; ++}; ++ ++&canfd { ++ pinctrl-0 = <&canfd0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; ++ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH /* enable - shared with camera board */ ++ &gpio2 7 GPIO_ACTIVE_LOW /* standby */ ++ >; ++ ++ channel0 { ++ status = "okay"; ++ }; ++}; ++ ++&xhci1 { ++ status = "okay"; ++ pinctrl-0 = <&usb31_pins>; ++ pinctrl-names = "default"; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts +new file mode 100644 +index 0000000..849afae +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts +@@ -0,0 +1,39 @@ ++/* ++ * Device Tree Source for the H3ULCB Kingfisher board on r8a7795 ES1.x ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7795-es1-h3ulcb.dts" ++#include "ulcb-kf.dtsi" ++ ++/ { ++ model = "Renesas H3ULCB Kingfisher board based on r8a7795"; ++}; ++ ++&du { ++ ports { ++ port@0 { ++ endpoint { ++ remote-endpoint = <&adv7513_in>; ++ }; ++ }; ++ port@3 { ++ endpoint { ++ remote-endpoint = <&lvds_enc_in>; ++ }; ++ }; ++ }; ++}; ++ ++&hsusb { ++ status = "okay"; ++}; ++ ++/* use CN11 instead default CN29/CN48 (H3 only) */ ++//#include "ulcb-kf-cn11.dtsi" +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vb.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vb.dts +new file mode 100644 +index 0000000..e5734aa +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vb.dts +@@ -0,0 +1,1787 @@ ++/* ++ * Device Tree Source for the H3ULCB Videobox board on r8a7795 ES1.x ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7795-es1-h3ulcb.dts" ++ ++/ { ++ model = "Renesas H3ULCB Videobox board based on r8a7795"; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led5 { ++ gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; ++ }; ++ led6 { ++ gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; ++ }; ++ /* D13 - status 0 */ ++ led_ext00 { ++ gpios = <&gpio_ext_led 0 GPIO_ACTIVE_LOW>; ++ /* linux,default-trigger = "heartbeat"; */ ++ }; ++ /* D14 - status 1 */ ++ led_ext01 { ++ gpios = <&gpio_ext_led 1 GPIO_ACTIVE_LOW>; ++ /* linux,default-trigger = "mmc1"; */ ++ }; ++ /* D16 - HDMI1 */ ++ led_ext02 { ++ gpios = <&gpio_ext_led 2 GPIO_ACTIVE_LOW>; ++ }; ++ /* D18 - HDMI0 */ ++ led_ext03 { ++ gpios = <&gpio_ext_led 3 GPIO_ACTIVE_LOW>; ++ }; ++ /* D20 - USB3.0 - 0.1 */ ++ led_ext04 { ++ gpios = <&gpio_ext_led 4 GPIO_ACTIVE_LOW>; ++ }; ++ /* D21 - USB3.0 - 0.2 */ ++ led_ext05 { ++ gpios = <&gpio_ext_led 5 GPIO_ACTIVE_LOW>; ++ }; ++ /* D24 - USB3.0 - 1.1 */ ++ led6_ext06 { ++ gpios = <&gpio_ext_led 6 GPIO_ACTIVE_LOW>; ++ }; ++ /* D25 - USB3.0 - 1.2 */ ++ led_ext07 { ++ gpios = <&gpio_ext_led 7 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ snd_clk: snd_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24576000>; ++ clock-output-names = "scki"; ++ }; ++ ++ vccq_sdhi3: regulator@5 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "SDHI3 VccQ"; ++ /* external voltage translator to 1.8V */ ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ fpdlink_switch: regulator@8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "fpdlink_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio1 20 0>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ hub_reset: regulator@9 { ++ compatible = "regulator-fixed"; ++ regulator-name = "hub_reset"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio5 5 0>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ hub_power: regulator@10 { ++ compatible = "regulator-fixed"; ++ regulator-name = "hub_power"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&gpio6 28 0>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ /delete-node/sound; ++ ++ rsnd_ak4613: sound@0 { ++ pinctrl-0 = <&sound_0_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; ++ ++ simple-audio-card,format = "left_j"; ++ simple-audio-card,name = "ak4613"; ++ ++ simple-audio-card,bitclock-master = <&sndcpu>; ++ simple-audio-card,frame-master = <&sndcpu>; ++ ++ sndcpu: simple-audio-card,cpu@1 { ++ sound-dai = <&rcar_sound>; ++ }; ++ ++ sndcodec: simple-audio-card,codec@1 { ++ sound-dai = <&ak4613>; ++ }; ++ }; ++ ++ lvds-encoder { ++ compatible = "thine,thc63lvdm83d"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port@0 { ++ reg = <0>; ++ lvds_enc_in: endpoint { ++ remote-endpoint = <&du_out_lvds0>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ lvds_enc_out: endpoint { ++ remote-endpoint = <&lvds_in>; ++ }; ++ }; ++ }; ++ }; ++ ++ lvds { ++ compatible = "lvds-connector"; ++ ++ width-mm = <210>; ++ height-mm = <158>; ++ ++ panel-timing { ++ /* 1280x800 @60Hz */ ++ clock-frequency = <65000000>; ++ hactive = <1280>; ++ vactive = <800>; ++ hsync-len = <40>; ++ hfront-porch = <80>; ++ hback-porch = <40>; ++ vfront-porch = <14>; ++ vback-porch = <14>; ++ vsync-len = <4>; ++ }; ++ ++ port { ++ lvds_in: endpoint { ++ remote-endpoint = <&lvds_enc_out>; ++ }; ++ }; ++ }; ++ ++ hdmi1-out { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con: endpoint { ++ remote-endpoint = <&rcar_dw_hdmi1_out>; ++ }; ++ }; ++ }; ++ ++ excan_ref_clk: excan-ref-clock { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <16000000>; ++ }; ++ ++ radio: si468x@0 { ++ compatible = "si,si468x-pcm"; ++ status = "okay"; ++ ++ #sound-dai-cells = <0>; ++ }; ++ ++ spi_gpio_sw { ++ compatible = "spi-gpio"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ gpio-sck = <&gpio0 8 GPIO_ACTIVE_HIGH>; ++ gpio-miso = <&gpio0 10 GPIO_ACTIVE_HIGH>; ++ gpio-mosi = <&gpio0 11 GPIO_ACTIVE_HIGH>; ++ cs-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; ++ num-chipselects = <1>; ++ ++ spidev: spidev@0 { ++ compatible = "spidev", "spi-gpio"; ++ reg = <0>; ++ spi-max-frequency = <25000000>; ++ spi-cpha; ++ spi-cpol; ++ }; ++ }; ++ ++ spi_gpio_can { ++ compatible = "spi-gpio"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ gpio-sck = <&gpio1 2 GPIO_ACTIVE_HIGH>; ++ gpio-miso = <&gpio1 3 GPIO_ACTIVE_HIGH>; ++ gpio-mosi = <&gpio1 1 GPIO_ACTIVE_HIGH>; ++ cs-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH ++ &gpio1 4 GPIO_ACTIVE_HIGH>; ++ num-chipselects = <2>; ++ ++ spican0: spidev@0 { ++ compatible = "microchip,mcp2515"; ++ reg = <0>; ++ clocks = <&excan_ref_clk>; ++ interrupt-parent = <&gpio0>; ++ interrupts = <15 GPIO_ACTIVE_LOW>; ++ spi-max-frequency = <10000000>; ++ }; ++ spican1: spidev@1 { ++ compatible = "microchip,mcp2515"; ++ reg = <1>; ++ clocks = <&excan_ref_clk>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <5 GPIO_ACTIVE_LOW>; ++ spi-max-frequency = <10000000>; ++ }; ++ }; ++}; ++ ++&du { ++ ports { ++ port@1 { ++ endpoint { ++ remote-endpoint = <&rcar_dw_hdmi0_in>; ++ }; ++ }; ++ port@2 { ++ endpoint { ++ remote-endpoint = <&rcar_dw_hdmi1_in>; ++ }; ++ }; ++ port@3 { ++ endpoint { ++ remote-endpoint = <&lvds_enc_in>; ++ }; ++ }; ++ }; ++}; ++ ++&hdmi1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port@0 { ++ reg = <0>; ++ rcar_dw_hdmi1_in: endpoint { ++ remote-endpoint = <&du_out_hdmi1>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ rcar_dw_hdmi1_out: endpoint { ++ remote-endpoint = <&hdmi1_con>; ++ }; ++ }; ++ }; ++}; ++ ++&pfc { ++ hscif4_pins: hscif4 { ++ groups = "hscif4_data_a", "hscif4_ctrl"; ++ function = "hscif4"; ++ }; ++ ++ sdhi3_pins_3v3: sd3_3v3 { ++ groups = "sdhi3_data4", "sdhi3_ctrl"; ++ function = "sdhi3"; ++ power-source = <3300>; ++ }; ++ ++ /delete-node/sound; ++ ++ sound_0_pins: sound1 { ++ groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; ++ function = "ssi"; ++ }; ++ ++ usb0_pins: usb0 { ++ groups = "usb0"; ++ function = "usb0"; ++ }; ++ ++ can0_pins: can0 { ++ groups = "can0_data_a"; ++ function = "can0"; ++ }; ++ ++ can1_pins: can1 { ++ groups = "can1_data"; ++ function = "can1"; ++ }; ++ ++ canfd0_pins: canfd0 { ++ groups = "canfd0_data_a"; ++ function = "canfd0"; ++ }; ++ ++ canfd1_pins: canfd1 { ++ groups = "canfd1_data"; ++ function = "canfd1"; ++ }; ++}; ++ ++&gpio0 { ++ video_a_irq { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A irq"; ++ }; ++ ++ video_b_irq { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B irq"; ++ }; ++ ++ video_c_irq { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-C irq"; ++ }; ++}; ++ ++&gpio1 { ++ gpioext_4_22_irq { ++ gpio-hog; ++ gpios = <25 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "0x22@i2c4 irq"; ++ }; ++ pcie_disable { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "mPCIe W_DISABLE"; ++ }; ++ m2_sleep { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "M.2 SLEEP#"; ++ }; ++ m2_pres { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 Present"; ++ }; ++ m2_pcie_det { ++ gpio-hog; ++ gpios = <18 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 PCIe detected"; ++ }; ++ m2_usb_det { ++ gpio-hog; ++ gpios = <19 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 USB30 detected"; ++ }; ++ m2_usb_det { ++ gpio-hog; ++ gpios = <27 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 SSD detected"; ++ }; ++ eth_phy_reset { ++ gpio-hog; ++ gpios = <16 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "BR phy reset"; ++ }; ++ eth_sw_reset { ++ gpio-hog; ++ gpios = <17 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "BR switch reset"; ++ }; ++}; ++ ++&gpio2 { ++ m2_wake { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 WAKE#"; ++ }; ++ m2_pcie_en { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "M.2 PCIe enable"; ++ }; ++}; ++ ++&gpio3 { ++ m2_power_off { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "M.2 FULL_CARD_POWER_OFF#"; ++ }; ++}; ++ ++&gpio6 { ++ pcie_wake { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "mPCIe WAKE#"; ++ }; ++ pcie_clkreq { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "mPCIe CLKREQ#"; ++ }; ++ m2_rst { ++ gpio-hog; ++ gpios = <21 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "M.2 RESET#"; ++ }; ++}; ++ ++&hscif4 { ++ pinctrl-0 = <&hscif4_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ ++ status = "okay"; ++}; ++ ++&i2c2 { ++ clock-frequency = <400000>; ++ ++ i2cswitch2: pca9548@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x74>; ++ reset-gpios = <&gpio6 5 GPIO_ACTIVE_LOW>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ /* USB3.0 HUB node(s) */ ++ }; ++ ++ i2c@6 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <6>; ++ /* PCIe node(s) */ ++ }; ++ ++ i2c@7 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <7>; ++ /* Slot A (CN10) */ ++ ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ ov106xx_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ ov106xx_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; ++ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ ov106xx_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ ov106xx_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; ++ ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ ov106xx_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ ov106xx_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@0 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "stp"; ++ ++ port@0 { ++ ti964_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti964_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ ti964_des0ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ ti964_des0ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ ti964_csi0ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@0 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_a_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "stp"; ++ ++ port@0 { ++ ti954_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti954_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ ti954_csi0ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ /* MAX9286 @ 0x2c */ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ /* Slot B (CN11) */ ++ ++ ov106xx@4 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x64>; ++ ++ port@0 { ++ ov106xx_in4: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin4ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ ov106xx_ti964_des1ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep0>; ++ }; ++ ov106xx_ti954_des1ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@5 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x65>; ++ ++ port@0 { ++ ov106xx_in5: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin5ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ ov106xx_ti964_des1ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep1>; ++ }; ++ ov106xx_ti954_des1ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@6 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x66>; ++ ++ port@0 { ++ ov106xx_in6: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin6ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ ov106xx_ti964_des1ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@7 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x67>; ++ ++ port@0 { ++ ov106xx_in7: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin7ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ ov106xx_ti964_des1ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep3>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@1 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "stp"; ++ ++ port@0 { ++ ti964_des1ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ ti964_des1ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ ti964_des1ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ ti964_des1ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ ti964_csi2ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@1 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_b_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "stp"; ++ ++ port@0 { ++ ti954_des1ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ ti954_des1ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ }; ++ port@1 { ++ ti954_csi2ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ ++ /* MAX9286 @ 0x2c */ ++ max9286-max9271@1 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des1ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ max9286_des1ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ max9286_des1ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ max9286_des1ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ max9286_csi2ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ /* Slot C (CN12) */ ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ /* Slot A (CN10) */ ++ ++ video_a_ext0: pca9535@26 { ++ compatible = "nxp,pca9535"; ++ reg = <0x26>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; ++ }; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; ++ }; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; ++ }; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A led"; ++ }; ++ }; ++ ++ video_a_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg2"; ++ }; ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; ++ }; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; ++ }; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; ++ }; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A LED"; ++ }; ++ }; ++ }; ++ ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ /* Slot B (CN11) */ ++ ++ video_b_ext0: pca9535@26 { ++ compatible = "nxp,pca9535"; ++ reg = <0x26>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_b_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg1"; ++ }; ++ video_b_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg0"; ++ }; ++ video_b_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR_SHDN"; ++ }; ++ video_b_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR0"; ++ }; ++ video_b_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR1"; ++ }; ++ video_b_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR2"; ++ }; ++ video_b_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR3"; ++ }; ++ video_b_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B DES_SHDN"; ++ }; ++ video_b_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B led"; ++ }; ++ }; ++ ++ video_b_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_b_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg2"; ++ }; ++ video_b_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg1"; ++ }; ++ video_b_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg0"; ++ }; ++ video_b_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR_SHDN"; ++ }; ++ video_b_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR0"; ++ }; ++ video_b_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR1"; ++ }; ++ video_b_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR2"; ++ }; ++ video_b_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR3"; ++ }; ++ video_b_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B DES_SHDN"; ++ }; ++ video_b_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B LED"; ++ }; ++ }; ++ }; ++ ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ /* Slot C (CN12) */ ++ }; ++ }; ++}; ++ ++&i2c4 { ++ i2cswitch4: pca9548@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x74>; ++ reset-gpios= <&gpio5 15 GPIO_ACTIVE_LOW>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ /* FAN node - EMC2103 */ ++ fan_ctrl:ecm2103@2e { ++ compatible = "emc2103"; ++ reg = <0x2e>; ++ }; ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ /* Power nodes - 2 x TPS544x20 */ ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ /* CAN and power board nodes */ ++ ++ gpio_ext_pwr: pca9535@22 { ++ compatible = "nxp,pca9535"; ++ reg = <0x22>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio1>; ++ interrupts = <25 IRQ_TYPE_EDGE_FALLING>; ++ ++ /* enable input DCDC after wake-up signal released */ ++ pwr_hold { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "pwr_hold"; ++ }; ++ ++ /* CAN0 */ ++ can0_stby { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can0_stby"; ++ }; ++ can0_load { ++ gpio-hog; ++ gpios = <0 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can0_120R_load"; ++ }; ++ /* CAN1 */ ++ can1_stby { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can1_stby"; ++ }; ++ can1_load { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can1_120R_load"; ++ }; ++ /* CAN2 */ ++ can2_stby { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can2_stby"; ++ }; ++ can2_load { ++ gpio-hog; ++ gpios = <2 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can2_120R_load"; ++ }; ++ can2_rst { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "can2_rst"; ++ }; ++ /* CAN3 */ ++ can3_stby { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can3_stby"; ++ }; ++ can3_load { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can3_120R_load"; ++ }; ++ can3_rst { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "can3_rst"; ++ }; ++ }; ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ /* FPDLink output node - DS90UH947 */ ++ }; ++ ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ /* BCM switch node */ ++ }; ++ ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ /* LED board node(s) */ ++ ++ gpio_ext_led: pca9535@22 { ++ compatible = "nxp,pca9535"; ++ reg = <0x22>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ /* gpios 0..7 are used for indication LEDs, low-active */ ++ }; ++ }; ++ ++ i2c@6 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <6>; ++ /* M2 connector i2c node(s) */ ++ }; ++ ++ /* port 7 is not used */ ++ }; ++}; ++ ++&pcie_bus_clk { ++ clock-frequency = <100000000>; ++ status = "okay"; ++}; ++ ++&pciec0 { ++ status = "okay"; ++}; ++ ++&pciec1 { ++ status = "okay"; ++}; ++ ++&vin0 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ vin0_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ vin0_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ vin1_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ vin1_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin2 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ vin2_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin3 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ vin3_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&vin4 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi41"; ++ virtual,channel = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin4_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ vin4_ti964_des1ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep0>; ++ }; ++ vin4_ti954_des1ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin5 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin5ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep1: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin5_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ vin5_ti964_des1ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep1>; ++ }; ++ vin5_ti954_des1ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin6 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin6ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <2>; ++ remote-endpoint = <&ov106xx_in6>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep2: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin6_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ vin6_ti964_des1ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin7 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin7ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <3>; ++ remote-endpoint = <&ov106xx_in7>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep3: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin7_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ vin7_ti964_des1ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&csi2_40 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&csi2_41 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_41_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&rcar_sound { ++ pinctrl-0 = <&sound_clk_pins>; ++ ++ /* Multi DAI */ ++ #sound-dai-cells = <1>; ++}; ++ ++&sata { ++ status = "okay"; ++}; ++ ++&ssi1 { ++ /delete-property/shared-pin; ++}; ++ ++&avb { ++ /delete-property/phy-handle; ++ /delete-property/phy-gpios; ++ phy-mode = "rgmii"; ++ ++ /delete-node/ethernet-phy@0; ++ ++ fixed-link { ++ speed = <100>; ++ full-duplex; ++ }; ++}; ++ ++&msiof1 { ++ status = "disabled"; ++}; ++ ++&usb2_phy0 { ++ pinctrl-0 = <&usb0_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&xhci0 { ++ status = "okay"; ++}; ++ ++&hsusb { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&can0 { ++ pinctrl-0 = <&can0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; ++}; ++ ++&can1 { ++ pinctrl-0 = <&can1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; ++}; ++ ++&canfd { ++ pinctrl-0 = <&canfd0_pins &canfd1_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ ++ renesas,can-clock-select = <0x0>; ++ ++ channel0 { ++ status = "okay"; ++ }; ++ ++ channel1 { ++ status = "okay"; ++ }; ++}; ++ ++/* uncomment to enable CN12 on VIN4-7 */ ++//#include "ulcb-vb-cn12.dtsi" +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts +new file mode 100644 +index 0000000..de56fa4 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts +@@ -0,0 +1,546 @@ ++/* ++ * Device Tree Source for the H3ULCB.View board on r8a7795 ES1.x ++ * ++ * Copyright (C) 2016-2017 Renesas Electronics Corp. ++ * Copyright (C) 2016-2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7795-es1-h3ulcb.dts" ++ ++/ { ++ model = "Renesas H3ULCB.View board based on r8a7795"; ++}; ++ ++&i2c4 { ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; ++ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; ++ ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_des0ep3: endpoint { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; ++ }; ++ ++ ov106xx@4 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x64>; ++ ++ port@0 { ++ ov106xx_in4: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin4ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@5 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x65>; ++ ++ port@0 { ++ ov106xx_in5: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin5ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@6 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x66>; ++ ++ port@0 { ++ ov106xx_in6: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin6ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@7 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x67>; ++ ++ port@0 { ++ ov106xx_in7: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin7ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_des1ep3: endpoint { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ }; ++ }; ++ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x4c>; ++ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; ++ maxim,sensor_delay = <0>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ maxim,i2c-quirk = <0x6c>; ++ ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ max9286-max9271@1 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x6c>; ++ gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; ++ maxim,sensor_delay = <0>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des1ep0: endpoint@0 { ++ max9271-addr = <0x54>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ max9286_des1ep1: endpoint@1 { ++ max9271-addr = <0x55>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ max9286_des1ep2: endpoint@2 { ++ max9271-addr = <0x56>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ max9286_des1ep3: endpoint@3 { ++ max9271-addr = <0x57>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ max9286_csi2ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++}; ++ ++&pcie_bus_clk { ++ clock-frequency = <100000000>; ++ status = "okay"; ++}; ++ ++&pciec1 { ++ status = "okay"; ++}; ++ ++&vin0 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin2 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin3 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&vin4 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi41"; ++ virtual,channel = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin4_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin5 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin5ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep1: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin5_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin6 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin6ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <2>; ++ remote-endpoint = <&ov106xx_in6>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep2: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin6_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin7 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin7ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <3>; ++ remote-endpoint = <&ov106xx_in7>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep3: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin7_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&csi2_40 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&csi2_41 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_41_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x-view.dts +new file mode 100644 +index 0000000..3f3d66a +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x-view.dts +@@ -0,0 +1,552 @@ ++/* ++ * Device Tree Source for the Salvator-X.View board on r8a7795 ES1.x ++ * ++ * Copyright (C) 2016-2017 Renesas Electronics Corp. ++ * Copyright (C) 2015-2017 Cogent Embedded, Inc ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7795-es1-salvator-x.dts" ++ ++/ { ++ model = "Renesas Salvator-X.View board based on r8a7795"; ++}; ++ ++&pfc { ++ can0_pins: can0 { ++ groups = "can0_data_a"; ++ function = "can0"; ++ }; ++ ++ can1_pins: can1 { ++ groups = "can1_data"; ++ function = "can1"; ++ }; ++}; ++ ++&i2c4 { ++ /delete-node/hdmi-in@34; ++ /delete-node/composite-in@70; ++ ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; ++ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; ++ ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_des0ep3: endpoint { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; ++ }; ++ ++ ov106xx@4 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x64>; ++ ++ port@0 { ++ ov106xx_in4: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin4ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@5 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x65>; ++ ++ port@0 { ++ ov106xx_in5: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin5ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@6 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x66>; ++ ++ port@0 { ++ ov106xx_in6: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin6ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@7 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x67>; ++ ++ port@0 { ++ ov106xx_in7: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin7ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_des1ep3: endpoint { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ }; ++ }; ++ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x4c>; ++ gpios = <&gpio6 30 GPIO_ACTIVE_LOW>; ++ maxim,sensor_delay = <0>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ maxim,i2c-quirk = <0x6c>; ++ ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ max9286-max9271@1 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x6c>; ++ maxim,sensor_delay = <0>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des1ep0: endpoint@0 { ++ max9271-addr = <0x54>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ max9286_des1ep1: endpoint@1 { ++ max9271-addr = <0x55>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ max9286_des1ep2: endpoint@2 { ++ max9271-addr = <0x56>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ max9286_des1ep3: endpoint@3 { ++ max9271-addr = <0x57>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ max9286_csi2ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++}; ++ ++&vin0 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin1 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin2 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin3 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&vin4 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi41"; ++ virtual,channel = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin4_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin5 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin5ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep1: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin5_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin6 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin6ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <2>; ++ remote-endpoint = <&ov106xx_in6>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep2: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin6_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin7 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin7ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <3>; ++ remote-endpoint = <&ov106xx_in7>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep3: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin7_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&csi2_20 { ++ status = "disabled"; ++ /delete-node/ports; ++}; ++ ++&csi2_40 { ++ /delete-node/ports; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&csi2_41 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_41_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&can0 { ++ pinctrl-0 = <&can0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&can1 { ++ pinctrl-0 = <&can1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-alfa.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-alfa.dts +new file mode 100644 +index 0000000..ae115bd +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-alfa.dts +@@ -0,0 +1,22 @@ ++/* ++ * Device Tree Source for the H3ULCB.HAD board Alfa side ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7795-h3ulcb-had.dtsi" ++ ++/ { ++ model = "Renesas H3ULCB.HAD board Alfa side based on r8a7795"; ++}; ++ ++&pciec0 { ++ status = "okay"; ++ ++ /* Root complex */ ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-beta.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-beta.dts +new file mode 100644 +index 0000000..805067e +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-beta.dts +@@ -0,0 +1,23 @@ ++/* ++ * Device Tree Source for the H3ULCB.HAD board Beta side ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7795-h3ulcb-had.dtsi" ++ ++/ { ++ model = "Renesas H3ULCB.HAD board Beta side based on r8a7795"; ++}; ++ ++&pciec0 { ++ status = "okay"; ++ ++ /* Endpoint */ ++ endpoint; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi +new file mode 100644 +index 0000000..4a00426 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi +@@ -0,0 +1,219 @@ ++/* ++ * Device Tree Source for the H3ULCB.HAD board on r8a7795 ++ * ++ * Copyright (C) 2016-2017 Renesas Electronics Corp. ++ * Copyright (C) 2016-2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++/* ++ * MSIOF0 - /dev/spidev1.0 connected to FPGA ethernet switch (both sides) ++ * MSIOF1 - /dev/spidev2.0 connected to RH850 (sideA to CSIH1, sideB to CSIH0) ++ */ ++ ++#include "r8a7795-h3ulcb-view.dts" ++ ++/ { ++ model = "Renesas H3ULCB.HAD board based on r8a7795"; ++ ++ aliases { ++ serial1 = &scif1; ++ spi1 = &spi0_gpio; ++ spi2 = &spi1_gpio; ++ }; ++ ++ chosen { ++ stdout-path = "serial1:115200n8"; ++ }; ++ ++ spi0_gpio: spi_gpio@0 { ++ compatible = "spi-gpio"; ++ num-chipselects = <1>; ++ gpio-sck = <&gpio5 17 0>; ++ gpio-mosi = <&gpio5 20 0>; ++ gpio-miso = <&gpio5 22 0>; ++ cs-gpios = <&gpio5 19 0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ spidev@0 { ++ compatible = "spi-gpio"; ++ reg = <0>; ++ spi-max-frequency = <2000000>; ++ spi-cpha; ++ spi-cpol; ++ }; ++ }; ++ ++ spi1_gpio: spi_gpio@1 { ++ compatible = "spi-gpio"; ++ num-chipselects = <1>; ++ gpio-sck = <&gpio6 8 0>; ++ gpio-mosi = <&gpio6 7 0>; ++ gpio-miso = <&gpio6 10 0>; ++ cs-gpios = <&gpio6 5 0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ spidev@0 { ++ compatible = "spi-gpio"; ++ reg = <0>; ++ spi-max-frequency = <2000000>; ++ spi-cpha; ++ spi-cpol; ++ }; ++ }; ++ ++ hdmi1-out { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con: endpoint { ++ remote-endpoint = <&rcar_dw_hdmi1_out>; ++ }; ++ }; ++ }; ++}; ++ ++&du { ++ ports { ++ port@1 { ++ endpoint { ++ remote-endpoint = <&rcar_dw_hdmi0_in>; ++ }; ++ }; ++ port@2 { ++ endpoint { ++ remote-endpoint = <&rcar_dw_hdmi1_in>; ++ }; ++ }; ++ }; ++}; ++ ++&hdmi1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port@0 { ++ reg = <0>; ++ rcar_dw_hdmi1_in: endpoint { ++ remote-endpoint = <&du_out_hdmi1>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ rcar_dw_hdmi1_out: endpoint { ++ remote-endpoint = <&hdmi1_con>; ++ }; ++ }; ++ }; ++}; ++ ++&pfc { ++ scif1_pins: scif1 { ++ groups = "scif1_data_a"; ++ function = "scif1"; ++ }; ++ ++ msiof0_pins: spi1 { ++ groups = "msiof0_clk", "msiof0_rxd", "msiof0_txd", ++ "msiof0_ss1"; ++ function = "msiof0"; ++ }; ++ ++ msiof1_pins: spi2 { ++ groups = "msiof1_clk_a", "msiof1_rxd_a", "msiof1_txd_a", ++ "msiof1_ss1_a"; ++ function = "msiof1"; ++ }; ++ ++ sound_clk_pins: sound-clk { ++ groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", ++ "audio_clkout_a" /*, "audio_clkout3_a"*/; ++ function = "audio_clk"; ++ }; ++ ++ usb31_pins: usb31 { ++ groups = "usb31"; ++ function = "usb31"; ++ }; ++ ++ can0_pins: can0 { ++ groups = "can0_data_a"; ++ function = "can0"; ++ }; ++ ++ canfd0_pins: canfd0 { ++ groups = "canfd0_data_a"; ++ function = "canfd0"; ++ }; ++}; ++ ++&scif1 { ++ pinctrl-0 = <&scif1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&avb { ++ /delete-property/phy-handle; ++ /delete-property/phy-gpios; ++ /delete-node/ethernet-phy@0; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++}; ++ ++&msiof0 { ++ pinctrl-0 = <&msiof0_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ cs-gpios = <&gpio5 19 0>; ++ ++ spidev@0 { ++ compatible = "renesas,sh-msiof"; ++ reg = <0>; ++ spi-max-frequency = <66666666>; ++ spi-cpha; ++ spi-cpol; ++ }; ++}; ++ ++&msiof1 { ++ status = "disabled"; ++ cs-gpios = <&gpio6 5 0>; ++}; ++ ++&can0 { ++ pinctrl-0 = <&can0_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ ++ renesas,can-clock-select = <0x0>; ++ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH /* enable - shared with camera board */ ++ &gpio2 7 GPIO_ACTIVE_LOW /* standby */ ++ >; ++}; ++ ++&canfd { ++ pinctrl-0 = <&canfd0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; ++ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH /* enable - shared with camera board */ ++ &gpio2 7 GPIO_ACTIVE_LOW /* standby */ ++ >; ++ ++ channel0 { ++ status = "okay"; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts +new file mode 100644 +index 0000000..4fe67f8 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts +@@ -0,0 +1,39 @@ ++/* ++ * Device Tree Source for the H3ULCB Kingfisher board on r8a7795 ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7795-h3ulcb.dts" ++#include "ulcb-kf.dtsi" ++ ++/ { ++ model = "Renesas H3ULCB Kingfisher board based on r8a7795"; ++}; ++ ++&du { ++ ports { ++ port@0 { ++ endpoint { ++ remote-endpoint = <&adv7513_in>; ++ }; ++ }; ++ port@3 { ++ endpoint { ++ remote-endpoint = <&lvds_enc_in>; ++ }; ++ }; ++ }; ++}; ++ ++&hsusb0 { ++ status = "okay"; ++}; ++ ++/* use CN11 instead default CN29/CN48 (H3 only) */ ++//#include "ulcb-kf-cn11.dtsi" +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb.dts +new file mode 100644 +index 0000000..98b6a08 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb.dts +@@ -0,0 +1,1787 @@ ++/* ++ * Device Tree Source for the H3ULCB Videobox board ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7795-h3ulcb.dts" ++ ++/ { ++ model = "Renesas H3ULCB Videobox board based on r8a7795"; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led5 { ++ gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; ++ }; ++ led6 { ++ gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; ++ }; ++ /* D13 - status 0 */ ++ led_ext00 { ++ gpios = <&gpio_ext_led 0 GPIO_ACTIVE_LOW>; ++ /* linux,default-trigger = "heartbeat"; */ ++ }; ++ /* D14 - status 1 */ ++ led_ext01 { ++ gpios = <&gpio_ext_led 1 GPIO_ACTIVE_LOW>; ++ /* linux,default-trigger = "mmc1"; */ ++ }; ++ /* D16 - HDMI1 */ ++ led_ext02 { ++ gpios = <&gpio_ext_led 2 GPIO_ACTIVE_LOW>; ++ }; ++ /* D18 - HDMI0 */ ++ led_ext03 { ++ gpios = <&gpio_ext_led 3 GPIO_ACTIVE_LOW>; ++ }; ++ /* D20 - USB3.0 - 0.1 */ ++ led_ext04 { ++ gpios = <&gpio_ext_led 4 GPIO_ACTIVE_LOW>; ++ }; ++ /* D21 - USB3.0 - 0.2 */ ++ led_ext05 { ++ gpios = <&gpio_ext_led 5 GPIO_ACTIVE_LOW>; ++ }; ++ /* D24 - USB3.0 - 1.1 */ ++ led6_ext06 { ++ gpios = <&gpio_ext_led 6 GPIO_ACTIVE_LOW>; ++ }; ++ /* D25 - USB3.0 - 1.2 */ ++ led_ext07 { ++ gpios = <&gpio_ext_led 7 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ snd_clk: snd_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24576000>; ++ clock-output-names = "scki"; ++ }; ++ ++ vccq_sdhi3: regulator@5 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "SDHI3 VccQ"; ++ /* external voltage translator to 1.8V */ ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ fpdlink_switch: regulator@8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "fpdlink_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio1 20 0>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ hub_reset: regulator@9 { ++ compatible = "regulator-fixed"; ++ regulator-name = "hub_reset"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio5 5 0>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ hub_power: regulator@10 { ++ compatible = "regulator-fixed"; ++ regulator-name = "hub_power"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&gpio6 28 0>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ /delete-node/sound; ++ ++ rsnd_ak4613: sound@0 { ++ pinctrl-0 = <&sound_0_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; ++ ++ simple-audio-card,format = "left_j"; ++ simple-audio-card,name = "ak4613"; ++ ++ simple-audio-card,bitclock-master = <&sndcpu>; ++ simple-audio-card,frame-master = <&sndcpu>; ++ ++ sndcpu: simple-audio-card,cpu@1 { ++ sound-dai = <&rcar_sound>; ++ }; ++ ++ sndcodec: simple-audio-card,codec@1 { ++ sound-dai = <&ak4613>; ++ }; ++ }; ++ ++ lvds-encoder { ++ compatible = "thine,thc63lvdm83d"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port@0 { ++ reg = <0>; ++ lvds_enc_in: endpoint { ++ remote-endpoint = <&du_out_lvds0>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ lvds_enc_out: endpoint { ++ remote-endpoint = <&lvds_in>; ++ }; ++ }; ++ }; ++ }; ++ ++ lvds { ++ compatible = "lvds-connector"; ++ ++ width-mm = <210>; ++ height-mm = <158>; ++ ++ panel-timing { ++ /* 1280x800 @60Hz */ ++ clock-frequency = <65000000>; ++ hactive = <1280>; ++ vactive = <800>; ++ hsync-len = <40>; ++ hfront-porch = <80>; ++ hback-porch = <40>; ++ vfront-porch = <14>; ++ vback-porch = <14>; ++ vsync-len = <4>; ++ }; ++ ++ port { ++ lvds_in: endpoint { ++ remote-endpoint = <&lvds_enc_out>; ++ }; ++ }; ++ }; ++ ++ hdmi1-out { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con: endpoint { ++ remote-endpoint = <&rcar_dw_hdmi1_out>; ++ }; ++ }; ++ }; ++ ++ excan_ref_clk: excan-ref-clock { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <16000000>; ++ }; ++ ++ radio: si468x@0 { ++ compatible = "si,si468x-pcm"; ++ status = "okay"; ++ ++ #sound-dai-cells = <0>; ++ }; ++ ++ spi_gpio_sw { ++ compatible = "spi-gpio"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ gpio-sck = <&gpio0 8 GPIO_ACTIVE_HIGH>; ++ gpio-miso = <&gpio0 10 GPIO_ACTIVE_HIGH>; ++ gpio-mosi = <&gpio0 11 GPIO_ACTIVE_HIGH>; ++ cs-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; ++ num-chipselects = <1>; ++ ++ spidev: spidev@0 { ++ compatible = "spidev", "spi-gpio"; ++ reg = <0>; ++ spi-max-frequency = <25000000>; ++ spi-cpha; ++ spi-cpol; ++ }; ++ }; ++ ++ spi_gpio_can { ++ compatible = "spi-gpio"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ gpio-sck = <&gpio1 2 GPIO_ACTIVE_HIGH>; ++ gpio-miso = <&gpio1 3 GPIO_ACTIVE_HIGH>; ++ gpio-mosi = <&gpio1 1 GPIO_ACTIVE_HIGH>; ++ cs-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH ++ &gpio1 4 GPIO_ACTIVE_HIGH>; ++ num-chipselects = <2>; ++ ++ spican0: spidev@0 { ++ compatible = "microchip,mcp2515"; ++ reg = <0>; ++ clocks = <&excan_ref_clk>; ++ interrupt-parent = <&gpio0>; ++ interrupts = <15 GPIO_ACTIVE_LOW>; ++ spi-max-frequency = <10000000>; ++ }; ++ spican1: spidev@1 { ++ compatible = "microchip,mcp2515"; ++ reg = <1>; ++ clocks = <&excan_ref_clk>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <5 GPIO_ACTIVE_LOW>; ++ spi-max-frequency = <10000000>; ++ }; ++ }; ++}; ++ ++&du { ++ ports { ++ port@1 { ++ endpoint { ++ remote-endpoint = <&rcar_dw_hdmi0_in>; ++ }; ++ }; ++ port@2 { ++ endpoint { ++ remote-endpoint = <&rcar_dw_hdmi1_in>; ++ }; ++ }; ++ port@3 { ++ endpoint { ++ remote-endpoint = <&lvds_enc_in>; ++ }; ++ }; ++ }; ++}; ++ ++&hdmi1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port@0 { ++ reg = <0>; ++ rcar_dw_hdmi1_in: endpoint { ++ remote-endpoint = <&du_out_hdmi1>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ rcar_dw_hdmi1_out: endpoint { ++ remote-endpoint = <&hdmi1_con>; ++ }; ++ }; ++ }; ++}; ++ ++&pfc { ++ hscif4_pins: hscif4 { ++ groups = "hscif4_data_a", "hscif4_ctrl"; ++ function = "hscif4"; ++ }; ++ ++ sdhi3_pins_3v3: sd3_3v3 { ++ groups = "sdhi3_data4", "sdhi3_ctrl"; ++ function = "sdhi3"; ++ power-source = <3300>; ++ }; ++ ++ /delete-node/sound; ++ ++ sound_0_pins: sound1 { ++ groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; ++ function = "ssi"; ++ }; ++ ++ usb0_pins: usb0 { ++ groups = "usb0"; ++ function = "usb0"; ++ }; ++ ++ can0_pins: can0 { ++ groups = "can0_data_a"; ++ function = "can0"; ++ }; ++ ++ can1_pins: can1 { ++ groups = "can1_data"; ++ function = "can1"; ++ }; ++ ++ canfd0_pins: canfd0 { ++ groups = "canfd0_data_a"; ++ function = "canfd0"; ++ }; ++ ++ canfd1_pins: canfd1 { ++ groups = "canfd1_data"; ++ function = "canfd1"; ++ }; ++}; ++ ++&gpio0 { ++ video_a_irq { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A irq"; ++ }; ++ ++ video_b_irq { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B irq"; ++ }; ++ ++ video_c_irq { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-C irq"; ++ }; ++}; ++ ++&gpio1 { ++ gpioext_4_22_irq { ++ gpio-hog; ++ gpios = <25 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "0x22@i2c4 irq"; ++ }; ++ pcie_disable { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "mPCIe W_DISABLE"; ++ }; ++ m2_sleep { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "M.2 SLEEP#"; ++ }; ++ m2_pres { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 Present"; ++ }; ++ m2_pcie_det { ++ gpio-hog; ++ gpios = <18 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 PCIe detected"; ++ }; ++ m2_usb_det { ++ gpio-hog; ++ gpios = <19 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 USB30 detected"; ++ }; ++ m2_usb_det { ++ gpio-hog; ++ gpios = <27 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 SSD detected"; ++ }; ++ eth_phy_reset { ++ gpio-hog; ++ gpios = <16 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "BR phy reset"; ++ }; ++ eth_sw_reset { ++ gpio-hog; ++ gpios = <17 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "BR switch reset"; ++ }; ++}; ++ ++&gpio2 { ++ m2_wake { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 WAKE#"; ++ }; ++ m2_pcie_en { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "M.2 PCIe enable"; ++ }; ++}; ++ ++&gpio3 { ++ m2_power_off { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "M.2 FULL_CARD_POWER_OFF#"; ++ }; ++}; ++ ++&gpio6 { ++ pcie_wake { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "mPCIe WAKE#"; ++ }; ++ pcie_clkreq { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "mPCIe CLKREQ#"; ++ }; ++ m2_rst { ++ gpio-hog; ++ gpios = <21 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "M.2 RESET#"; ++ }; ++}; ++ ++&hscif4 { ++ pinctrl-0 = <&hscif4_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ ++ status = "okay"; ++}; ++ ++&i2c2 { ++ clock-frequency = <400000>; ++ ++ i2cswitch2: pca9548@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x74>; ++ reset-gpios = <&gpio6 5 GPIO_ACTIVE_LOW>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ /* USB3.0 HUB node(s) */ ++ }; ++ ++ i2c@6 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <6>; ++ /* PCIe node(s) */ ++ }; ++ ++ i2c@7 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <7>; ++ /* Slot A (CN10) */ ++ ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ ov106xx_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ ov106xx_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; ++ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ ov106xx_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ ov106xx_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; ++ ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ ov106xx_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ ov106xx_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@0 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "stp"; ++ ++ port@0 { ++ ti964_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti964_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ ti964_des0ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ ti964_des0ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ ti964_csi0ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@0 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_a_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "stp"; ++ ++ port@0 { ++ ti954_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti954_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ ti954_csi0ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ /* MAX9286 @ 0x2c */ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ /* Slot B (CN11) */ ++ ++ ov106xx@4 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x64>; ++ ++ port@0 { ++ ov106xx_in4: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin4ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ ov106xx_ti964_des1ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep0>; ++ }; ++ ov106xx_ti954_des1ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@5 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x65>; ++ ++ port@0 { ++ ov106xx_in5: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin5ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ ov106xx_ti964_des1ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep1>; ++ }; ++ ov106xx_ti954_des1ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@6 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x66>; ++ ++ port@0 { ++ ov106xx_in6: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin6ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ ov106xx_ti964_des1ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@7 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x67>; ++ ++ port@0 { ++ ov106xx_in7: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin7ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ ov106xx_ti964_des1ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep3>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@1 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "stp"; ++ ++ port@0 { ++ ti964_des1ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ ti964_des1ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ ti964_des1ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ ti964_des1ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ ti964_csi2ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@1 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_b_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "stp"; ++ ++ port@0 { ++ ti954_des1ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ ti954_des1ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ }; ++ port@1 { ++ ti954_csi2ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ ++ /* MAX9286 @ 0x2c */ ++ max9286-max9271@1 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des1ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ max9286_des1ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ max9286_des1ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ max9286_des1ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ max9286_csi2ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ /* Slot C (CN12) */ ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ /* Slot A (CN10) */ ++ ++ video_a_ext0: pca9535@26 { ++ compatible = "nxp,pca9535"; ++ reg = <0x26>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; ++ }; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; ++ }; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; ++ }; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A led"; ++ }; ++ }; ++ ++ video_a_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg2"; ++ }; ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; ++ }; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; ++ }; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; ++ }; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A LED"; ++ }; ++ }; ++ }; ++ ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ /* Slot B (CN11) */ ++ ++ video_b_ext0: pca9535@26 { ++ compatible = "nxp,pca9535"; ++ reg = <0x26>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_b_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg1"; ++ }; ++ video_b_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg0"; ++ }; ++ video_b_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR_SHDN"; ++ }; ++ video_b_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR0"; ++ }; ++ video_b_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR1"; ++ }; ++ video_b_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR2"; ++ }; ++ video_b_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR3"; ++ }; ++ video_b_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B DES_SHDN"; ++ }; ++ video_b_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B led"; ++ }; ++ }; ++ ++ video_b_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_b_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg2"; ++ }; ++ video_b_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg1"; ++ }; ++ video_b_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg0"; ++ }; ++ video_b_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR_SHDN"; ++ }; ++ video_b_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR0"; ++ }; ++ video_b_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR1"; ++ }; ++ video_b_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR2"; ++ }; ++ video_b_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR3"; ++ }; ++ video_b_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B DES_SHDN"; ++ }; ++ video_b_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B LED"; ++ }; ++ }; ++ }; ++ ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ /* Slot C (CN12) */ ++ }; ++ }; ++}; ++ ++&i2c4 { ++ i2cswitch4: pca9548@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x74>; ++ reset-gpios= <&gpio5 15 GPIO_ACTIVE_LOW>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ /* FAN node - EMC2103 */ ++ fan_ctrl:ecm2103@2e { ++ compatible = "emc2103"; ++ reg = <0x2e>; ++ }; ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ /* Power nodes - 2 x TPS544x20 */ ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ /* CAN and power board nodes */ ++ ++ gpio_ext_pwr: pca9535@22 { ++ compatible = "nxp,pca9535"; ++ reg = <0x22>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio1>; ++ interrupts = <25 IRQ_TYPE_EDGE_FALLING>; ++ ++ /* enable input DCDC after wake-up signal released */ ++ pwr_hold { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "pwr_hold"; ++ }; ++ ++ /* CAN0 */ ++ can0_stby { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can0_stby"; ++ }; ++ can0_load { ++ gpio-hog; ++ gpios = <0 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can0_120R_load"; ++ }; ++ /* CAN1 */ ++ can1_stby { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can1_stby"; ++ }; ++ can1_load { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can1_120R_load"; ++ }; ++ /* CAN2 */ ++ can2_stby { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can2_stby"; ++ }; ++ can2_load { ++ gpio-hog; ++ gpios = <2 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can2_120R_load"; ++ }; ++ can2_rst { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "can2_rst"; ++ }; ++ /* CAN3 */ ++ can3_stby { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can3_stby"; ++ }; ++ can3_load { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can3_120R_load"; ++ }; ++ can3_rst { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "can3_rst"; ++ }; ++ }; ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ /* FPDLink output node - DS90UH947 */ ++ }; ++ ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ /* BCM switch node */ ++ }; ++ ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ /* LED board node(s) */ ++ ++ gpio_ext_led: pca9535@22 { ++ compatible = "nxp,pca9535"; ++ reg = <0x22>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ /* gpios 0..7 are used for indication LEDs, low-active */ ++ }; ++ }; ++ ++ i2c@6 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <6>; ++ /* M2 connector i2c node(s) */ ++ }; ++ ++ /* port 7 is not used */ ++ }; ++}; ++ ++&pcie_bus_clk { ++ clock-frequency = <100000000>; ++ status = "okay"; ++}; ++ ++&pciec0 { ++ status = "okay"; ++}; ++ ++&pciec1 { ++ status = "okay"; ++}; ++ ++&vin0 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ vin0_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ vin0_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ vin1_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ vin1_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin2 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ vin2_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin3 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ vin3_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&vin4 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi41"; ++ virtual,channel = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin4_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ vin4_ti964_des1ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep0>; ++ }; ++ vin4_ti954_des1ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin5 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin5ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep1: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin5_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ vin5_ti964_des1ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep1>; ++ }; ++ vin5_ti954_des1ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin6 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin6ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <2>; ++ remote-endpoint = <&ov106xx_in6>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep2: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin6_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ vin6_ti964_des1ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin7 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin7ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <3>; ++ remote-endpoint = <&ov106xx_in7>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep3: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin7_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ vin7_ti964_des1ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&csi2_40 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&csi2_41 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_41_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&rcar_sound { ++ pinctrl-0 = <&sound_clk_pins>; ++ ++ /* Multi DAI */ ++ #sound-dai-cells = <1>; ++}; ++ ++&sata { ++ status = "okay"; ++}; ++ ++&ssi1 { ++ /delete-property/shared-pin; ++}; ++ ++&avb { ++ /delete-property/phy-handle; ++ /delete-property/phy-gpios; ++ phy-mode = "rgmii"; ++ ++ /delete-node/ethernet-phy@0; ++ ++ fixed-link { ++ speed = <100>; ++ full-duplex; ++ }; ++}; ++ ++&msiof1 { ++ status = "disabled"; ++}; ++ ++&usb2_phy0 { ++ pinctrl-0 = <&usb0_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&xhci0 { ++ status = "okay"; ++}; ++ ++&hsusb0 { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&can0 { ++ pinctrl-0 = <&can0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; ++}; ++ ++&can1 { ++ pinctrl-0 = <&can1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; ++}; ++ ++&canfd { ++ pinctrl-0 = <&canfd0_pins &canfd1_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ ++ renesas,can-clock-select = <0x0>; ++ ++ channel0 { ++ status = "okay"; ++ }; ++ ++ channel1 { ++ status = "okay"; ++ }; ++}; ++ ++/* uncomment to enable CN12 on VIN4-7 */ ++//#include "ulcb-vb-cn12.dtsi" +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts +new file mode 100644 +index 0000000..2c24b85 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts +@@ -0,0 +1,546 @@ ++/* ++ * Device Tree Source for the H3ULCB.View board ++ * ++ * Copyright (C) 2016-2017 Renesas Electronics Corp. ++ * Copyright (C) 2016-2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7795-h3ulcb.dts" ++ ++/ { ++ model = "Renesas H3ULCB.View board based on r8a7795"; ++}; ++ ++&i2c4 { ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; ++ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; ++ ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_des0ep3: endpoint { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; ++ }; ++ ++ ov106xx@4 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x64>; ++ ++ port@0 { ++ ov106xx_in4: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin4ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@5 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x65>; ++ ++ port@0 { ++ ov106xx_in5: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin5ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@6 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x66>; ++ ++ port@0 { ++ ov106xx_in6: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin6ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@7 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x67>; ++ ++ port@0 { ++ ov106xx_in7: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin7ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_des1ep3: endpoint { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ }; ++ }; ++ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x4c>; ++ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; ++ maxim,sensor_delay = <0>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ maxim,i2c-quirk = <0x6c>; ++ ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ max9286-max9271@1 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x6c>; ++ gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; ++ maxim,sensor_delay = <0>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des1ep0: endpoint@0 { ++ max9271-addr = <0x54>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ max9286_des1ep1: endpoint@1 { ++ max9271-addr = <0x55>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ max9286_des1ep2: endpoint@2 { ++ max9271-addr = <0x56>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ max9286_des1ep3: endpoint@3 { ++ max9271-addr = <0x57>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ max9286_csi2ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++}; ++ ++&pcie_bus_clk { ++ clock-frequency = <100000000>; ++ status = "okay"; ++}; ++ ++&pciec1 { ++ status = "okay"; ++}; ++ ++&vin0 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin2 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin3 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&vin4 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi41"; ++ virtual,channel = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin4_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin5 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin5ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep1: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin5_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin6 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin6ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <2>; ++ remote-endpoint = <&ov106xx_in6>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep2: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin6_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin7 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin7ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <3>; ++ remote-endpoint = <&ov106xx_in7>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep3: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin7_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&csi2_40 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&csi2_41 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_41_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x-view.dts +new file mode 100644 +index 0000000..fb12a39f3 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x-view.dts +@@ -0,0 +1,552 @@ ++/* ++ * Device Tree Source for the Salvator-X.View board ++ * ++ * Copyright (C) 2016-2017 Renesas Electronics Corp. ++ * Copyright (C) 2015-2017 Cogent Embedded, Inc ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7795-salvator-x.dts" ++ ++/ { ++ model = "Renesas Salvator-X.View board based on r8a7795"; ++}; ++ ++&pfc { ++ can0_pins: can0 { ++ groups = "can0_data_a"; ++ function = "can0"; ++ }; ++ ++ can1_pins: can1 { ++ groups = "can1_data"; ++ function = "can1"; ++ }; ++}; ++ ++&i2c4 { ++ /delete-node/hdmi-in@34; ++ /delete-node/composite-in@70; ++ ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; ++ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; ++ ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_des0ep3: endpoint { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; ++ }; ++ ++ ov106xx@4 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x64>; ++ ++ port@0 { ++ ov106xx_in4: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin4ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@5 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x65>; ++ ++ port@0 { ++ ov106xx_in5: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin5ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@6 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x66>; ++ ++ port@0 { ++ ov106xx_in6: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin6ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@7 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x67>; ++ ++ port@0 { ++ ov106xx_in7: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin7ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_des1ep3: endpoint { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ }; ++ }; ++ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x4c>; ++ gpios = <&gpio6 30 GPIO_ACTIVE_LOW>; ++ maxim,sensor_delay = <0>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ maxim,i2c-quirk = <0x6c>; ++ ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ max9286-max9271@1 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x6c>; ++ maxim,sensor_delay = <0>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des1ep0: endpoint@0 { ++ max9271-addr = <0x54>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ max9286_des1ep1: endpoint@1 { ++ max9271-addr = <0x55>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ max9286_des1ep2: endpoint@2 { ++ max9271-addr = <0x56>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ max9286_des1ep3: endpoint@3 { ++ max9271-addr = <0x57>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ max9286_csi2ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++}; ++ ++&vin0 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin1 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin2 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin3 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&vin4 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi41"; ++ virtual,channel = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin4_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin5 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin5ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep1: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin5_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin6 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin6ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <2>; ++ remote-endpoint = <&ov106xx_in6>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep2: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin6_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin7 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin7ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <3>; ++ remote-endpoint = <&ov106xx_in7>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep3: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin7_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&csi2_20 { ++ status = "disabled"; ++ /delete-node/ports; ++}; ++ ++&csi2_40 { ++ /delete-node/ports; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&csi2_41 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_41_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&can0 { ++ pinctrl-0 = <&can0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&can1 { ++ pinctrl-0 = <&can1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts +new file mode 100644 +index 0000000..730cd2a +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts +@@ -0,0 +1,40 @@ ++/* ++ * Device Tree Source for the M3ULCB Kingfisher board on r8a7796 ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7796-m3ulcb.dts" ++#include "ulcb-kf.dtsi" ++ ++/ { ++ model = "Renesas M3ULCB Kingfisher board based on r8a7796"; ++}; ++ ++&du { ++ ports { ++ port@0 { ++ endpoint { ++ remote-endpoint = <&adv7513_in>; ++ }; ++ }; ++ port@2 { ++ endpoint { ++ remote-endpoint = <&lvds_enc_in>; ++ }; ++ }; ++ }; ++}; ++ ++&hsusb { ++ status = "okay"; ++}; ++ ++&xhci0 { ++ status = "disabled"; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts +new file mode 100644 +index 0000000..1ac0041 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts +@@ -0,0 +1,287 @@ ++/* ++ * Device Tree Source for the M3ULCB.View board on r8a7796 ++ * ++ * Copyright (C) 2016-2017 Renesas Electronics Corp. ++ * Copyright (C) 2016-2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7796-m3ulcb.dts" ++ ++/ { ++ model = "Renesas M3ULCB.View board based on r8a7796"; ++}; ++ ++&i2c4 { ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; ++ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; ++ ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_des0ep3: endpoint { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; ++ }; ++ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x4c>; ++ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; ++ maxim,sensor_delay = <0>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ maxim,i2c-quirk = <0x6c>; ++ ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++}; ++ ++&pcie_bus_clk { ++ clock-frequency = <100000000>; ++ status = "okay"; ++}; ++ ++&pciec1 { ++ status = "okay"; ++}; ++ ++&vin0 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin2 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin3 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&csi2_40 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts +new file mode 100644 +index 0000000..cc6866c +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts +@@ -0,0 +1,318 @@ ++/* ++ * Device Tree Source for the Salvator-X.View board ++ * ++ * Copyright (C) 2016-2017 Renesas Electronics Corp. ++ * Copyright (C) 2016-2017 Cogent Embedded, Inc ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7796-salvator-x.dts" ++ ++/ { ++ model = "Renesas Salvator-X.View board based on r8a7796"; ++}; ++ ++&pfc { ++ can0_pins: can0 { ++ groups = "can0_data_a"; ++ function = "can0"; ++ }; ++ ++ can1_pins: can1 { ++ groups = "can1_data"; ++ function = "can1"; ++ }; ++}; ++ ++&i2c4 { ++ /delete-node/hdmi-in@34; ++ /delete-node/composite-in@70; ++ ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; ++ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; ++ ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_des0ep3: endpoint { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; ++ }; ++ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x4c>; ++ gpios = <&gpio6 30 GPIO_ACTIVE_LOW>; ++ maxim,sensor_delay = <0>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ maxim,i2c-quirk = <0x6c>; ++ ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++}; ++ ++&vin0 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin1 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin2 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin3 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&vin4 { ++ status = "disabled"; ++}; ++ ++&vin5 { ++ status = "disabled"; ++}; ++ ++&vin6 { ++ status = "disabled"; ++}; ++ ++&vin7 { ++ status = "disabled"; ++}; ++ ++&csi2_20 { ++ status = "disabled"; ++ /delete-node/ports; ++}; ++ ++&csi2_40 { ++ /delete-node/ports; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&can0 { ++ pinctrl-0 = <&can0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&can1 { ++ pinctrl-0 = <&can1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts b/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts +new file mode 100644 +index 0000000..f71addf +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts +@@ -0,0 +1,561 @@ ++/* ++ * Device Tree Source for the Eagle board ++ * ++ * Copyright (C) 2016-2017 Renesas Electronics Corp. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++#include "r8a7797.dtsi" ++#include ++ ++/ { ++ model = "Renesas Eagle board based on r8a7797"; ++ compatible = "renesas,eagle", "renesas,r8a7797"; ++ ++ aliases { ++ serial0 = &scif0; ++ ethernet0 = &avb; ++ }; ++ ++ chosen { ++ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@48000000 { ++ device_type = "memory"; ++ /* first 128MB is reserved for secure area. */ ++ reg = <0x0 0x48000000 0x0 0x38000000>; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ /* device specific region for Lossy Decompression */ ++ lossy_decompress: linux,lossy_decompress { ++ no-map; ++ reg = <0x00000000 0x64000000 0x0 0x03000000>; ++ }; ++ ++ /* global autoconfigured region for contiguous allocations */ ++ linux,cma { ++ compatible = "shared-dma-pool"; ++ reusable; ++ reg = <0x00000000 0x67000000 0x0 0x09000000>; ++ linux,cma-default; ++ }; ++ ++ /* device specific region for contiguous allocations */ ++ linux,multimedia { ++ compatible = "shared-dma-pool"; ++ reusable; ++ reg = <0x00000000 0x70000000 0x0 0x10000000>; ++ }; ++ }; ++ ++ mmngr { ++ compatible = "renesas,mmngr"; ++ memory-region = <&lossy_decompress>; ++ }; ++ ++ mmngrbuf { ++ compatible = "renesas,mmngrbuf"; ++ }; ++ ++ vspm_if { ++ compatible = "renesas,vspm_if"; ++ }; ++ ++ lvds-encoder { ++ compatible = "thine,thc63lvdm83d"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ lvds_enc_in: endpoint { ++ remote-endpoint = <&du_out_lvds0>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ lvds_enc_out: endpoint { ++ remote-endpoint = <&lvds_in>; ++ }; ++ }; ++ }; ++ }; ++ ++ lvds { ++ compatible = "lvds-connector"; ++ ++ width-mm = <210>; ++ height-mm = <158>; ++ ++ panel-timing { ++ clock-frequency = <133000000>; ++ hactive = <1024>; ++ vactive = <768>; ++ hsync-len = <136>; ++ hfront-porch = <20>; ++ hback-porch = <160>; ++ vfront-porch = <3>; ++ vback-porch = <29>; ++ vsync-len = <6>; ++ }; ++ ++ port { ++ lvds_in: endpoint { ++ remote-endpoint = <&lvds_enc_out>; ++ }; ++ }; ++ }; ++ ++ hdmi-out { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con: endpoint { ++ remote-endpoint = <&adv7511_out>; ++ }; ++ }; ++ }; ++ ++ dclkin_p0: clock-out0 { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <148500000>; ++ }; ++ ++ msiof_ref_clk: msiof-ref-clock { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <66666666>; ++ }; ++}; ++ ++&du { ++ pinctrl-0 = <&du_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ endpoint { ++ remote-endpoint = <&adv7511_in>; ++ }; ++ }; ++ }; ++}; ++ ++&extal_clk { ++ clock-frequency = <16666666>; ++}; ++ ++&extalr_clk { ++ clock-frequency = <32768>; ++}; ++ ++&pfc { ++ pinctrl-0 = <&scif_clk_pins>; ++ pinctrl-names = "default"; ++ ++ scif0_pins: scif0 { ++ groups = "scif0_data"; ++ function = "scif0"; ++ }; ++ ++ scif_clk_pins: scif_clk { ++ groups = "scif_clk_b"; ++ function = "scif_clk"; ++ }; ++ ++ i2c0_pins: i2c0 { ++ groups = "i2c0"; ++ function = "i2c0"; ++ }; ++ ++ i2c3_pins: i2c3 { ++ groups = "i2c3"; ++ function = "i2c3"; ++ }; ++ ++ avb_pins: avb { ++ groups = "avb0_mdc"; ++ function = "avb0"; ++ }; ++ ++ du_pins: du { ++ groups = "du_rgb666", "du_sync", "du_clk_out_0", "du_disp"; ++ function = "du"; ++ }; ++}; ++ ++&scif0 { ++ pinctrl-0 = <&scif0_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&scif_clk { ++ clock-frequency = <14745600>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ pinctrl-0 = <&i2c0_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++ clock-frequency = <400000>; ++ ++ hdmi@39{ ++ compatible = "adi,adv7511w"; ++ #sound-dai-cells = <0>; ++ reg = <0x39>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <20 IRQ_TYPE_LEVEL_LOW>; ++ ++ adi,input-depth = <8>; ++ adi,input-colorspace = "rgb"; ++ adi,input-clock = "1x"; ++ adi,input-style = <1>; ++ adi,input-justification = "evenly"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ adv7511_in: endpoint { ++ remote-endpoint = <&lvds_enc_out>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ adv7511_out: endpoint { ++ remote-endpoint = <&hdmi_con>; ++ }; ++ }; ++ }; ++ }; ++ ++ gpio_ext: pca9654@20 { ++ compatible = "onsemi,pca9654"; ++ reg = <0x20>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++}; ++ ++&i2c3 { ++ pinctrl-0 = <&i2c3_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++ clock-frequency = <400000>; ++ ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; ++ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; ++ ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_des0ep3: endpoint { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; ++ }; ++ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x48>; ++ gpios = <&gpio_ext 0 GPIO_ACTIVE_LOW>; /* CSI0 DE_PDn */ ++ maxim,gpio0 = <0>; ++ maxim,sensor_delay = <100>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++}; ++ ++&wdt0 { ++ status = "okay"; ++}; ++ ++&avb { ++ pinctrl-0 = <&avb_pins>; ++ pinctrl-names = "default"; ++ renesas,no-ether-link; ++ phy-handle = <&phy0>; ++ status = "okay"; ++ phy-int-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>; ++ ++ phy0: ethernet-phy@0 { ++ rxc-skew-ps = <1500>; ++ rxdv-skew-ps = <420>; /* default */ ++ rxd0-skew-ps = <420>; /* default */ ++ rxd1-skew-ps = <420>; /* default */ ++ rxd2-skew-ps = <420>; /* default */ ++ rxd3-skew-ps = <420>; /* default */ ++ txc-skew-ps = <900>; /* default */ ++ txen-skew-ps = <420>; /* default */ ++ txd0-skew-ps = <420>; /* default */ ++ txd1-skew-ps = <420>; /* default */ ++ txd2-skew-ps = <420>; /* default */ ++ txd3-skew-ps = <420>; /* default */ ++ reg = <0>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <17 IRQ_TYPE_LEVEL_LOW>; ++ max-speed = <1000>; ++ }; ++}; ++ ++&vin0 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin2 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin3 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&csi2_40 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ +diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts +new file mode 100644 +index 0000000..9837e17 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts +@@ -0,0 +1,541 @@ ++/* ++ * Device Tree Source for the V3MSK Kingfisher board on r8a7797 ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7797-v3msk.dts" ++ ++/ { ++ model = "Renesas V3MSK Kingfisher board based on r8a7797"; ++}; ++ ++&i2c0 { ++ /* i2c0 might conflict with pc9548 reset pin on Kingfisher (uncomment if h/w not patched) */ ++// status = "disabled"; ++}; ++ ++&i2c3 { ++ i2cswitch4: pca9548@71 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x71>; ++// reset-gpios= <&gpio3 15 GPIO_ACTIVE_LOW>; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ /* Slot B (CN11) */ ++ ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ ov106xx_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ ov106xx_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; ++ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ ov106xx_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ ov106xx_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; ++ ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ ov106xx_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ ov106xx_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@0 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti964_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti964_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ ti964_des0ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ ti964_des0ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ ti964_csi0ep0: endpoint { ++ csi-rate = <800>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@0 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_a_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti954_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti954_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ ti954_csi0ep0: endpoint { ++ csi-rate = <800>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ /* MAX9286 @ 0x2c */ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@6 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <6>; ++ /* Slot B (CN11) */ ++ ++ video_a_ext0: pca9535@27 { ++ compatible = "nxp,pca9535"; ++ reg = <0x27>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; ++ }; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; ++ }; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; ++ }; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A led"; ++ }; ++ }; ++ ++ video_a_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg2"; ++ }; ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; ++ }; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; ++ }; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; ++ }; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A LED"; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&vin0 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ vin0_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ vin0_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ vin1_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ vin1_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin2 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ vin2_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin3 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ vin3_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&csi2_40 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts +new file mode 100644 +index 0000000..61f7e8b +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts +@@ -0,0 +1,294 @@ ++/* ++ * Device Tree Source for the V3M Starter Kit board on r8a7797 ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++#include "r8a7797.dtsi" ++#include ++ ++/ { ++ model = "Renesas V3M Starter Kit board based on r8a7797"; ++ compatible = "renesas,v3msk", "renesas,r8a7797"; ++ ++ aliases { ++ serial0 = &scif0; ++ ethernet0 = &avb; ++ }; ++ ++ chosen { ++ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@48000000 { ++ device_type = "memory"; ++ /* first 128MB is reserved for secure area. */ ++ reg = <0x0 0x48000000 0x0 0x38000000>; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ /* device specific region for Lossy Decompression */ ++ lossy_decompress: linux,lossy_decompress { ++ no-map; ++ reg = <0x00000000 0x64000000 0x0 0x03000000>; ++ }; ++ ++ /* global autoconfigured region for contiguous allocations */ ++ linux,cma { ++ compatible = "shared-dma-pool"; ++ reusable; ++ reg = <0x00000000 0x67000000 0x0 0x09000000>; ++ linux,cma-default; ++ }; ++ ++ /* device specific region for contiguous allocations */ ++ linux,multimedia { ++ compatible = "shared-dma-pool"; ++ reusable; ++ reg = <0x00000000 0x70000000 0x0 0x10000000>; ++ }; ++ }; ++ ++ mmngr { ++ compatible = "renesas,mmngr"; ++ memory-region = <&lossy_decompress>; ++ }; ++ ++ mmngrbuf { ++ compatible = "renesas,mmngrbuf"; ++ }; ++ ++ vspm_if { ++ compatible = "renesas,vspm_if"; ++ }; ++ ++ lvds-encoder { ++ compatible = "thine,thc63lvdm83d"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ lvds_enc_in: endpoint { ++ remote-endpoint = <&du_out_lvds0>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ lvds_enc_out: endpoint { ++ remote-endpoint = <&lvds_in>; ++ }; ++ }; ++ }; ++ }; ++ ++ lvds { ++ compatible = "lvds-connector"; ++ ++ width-mm = <210>; ++ height-mm = <158>; ++ ++ panel-timing { ++ clock-frequency = <133000000>; ++ hactive = <1024>; ++ vactive = <768>; ++ hsync-len = <136>; ++ hfront-porch = <20>; ++ hback-porch = <160>; ++ vfront-porch = <3>; ++ vback-porch = <29>; ++ vsync-len = <6>; ++ }; ++ ++ port { ++ lvds_in: endpoint { ++ remote-endpoint = <&lvds_enc_out>; ++ }; ++ }; ++ }; ++ ++ hdmi-out { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con: endpoint { ++ remote-endpoint = <&adv7511_out>; ++ }; ++ }; ++ }; ++ ++ dclkin_p0: clock-out0 { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <148500000>; ++ }; ++ ++ msiof_ref_clk: msiof-ref-clock { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <66666666>; ++ }; ++}; ++ ++&du { ++ pinctrl-0 = <&du_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ endpoint { ++ remote-endpoint = <&adv7511_in>; ++ }; ++ }; ++ }; ++}; ++ ++&extal_clk { ++ clock-frequency = <16666666>; ++}; ++ ++&extalr_clk { ++ clock-frequency = <32768>; ++}; ++ ++&pfc { ++ pinctrl-0 = <&scif_clk_pins>; ++ pinctrl-names = "default"; ++ ++ scif0_pins: scif0 { ++ groups = "scif0_data"; ++ function = "scif0"; ++ }; ++ ++ scif_clk_pins: scif_clk { ++ groups = "scif_clk_b"; ++ function = "scif_clk"; ++ }; ++ ++ i2c0_pins: i2c0 { ++ groups = "i2c0"; ++ function = "i2c0"; ++ }; ++ ++ i2c3_pins: i2c3 { ++ groups = "i2c3"; ++ function = "i2c3"; ++ }; ++ ++ avb_pins: avb { ++ groups = "avb0_mdc"; ++ function = "avb0"; ++ }; ++ ++ du_pins: du { ++ groups = "du_rgb666", "du_sync", "du_clk_out_0", "du_disp"; ++ function = "du"; ++ }; ++}; ++ ++&scif0 { ++ pinctrl-0 = <&scif0_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&scif_clk { ++ clock-frequency = <14745600>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ pinctrl-0 = <&i2c0_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++ clock-frequency = <400000>; ++ ++ hdmi@39{ ++ compatible = "adi,adv7511w"; ++ #sound-dai-cells = <0>; ++ reg = <0x39>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <20 IRQ_TYPE_LEVEL_LOW>; ++ ++ adi,input-depth = <8>; ++ adi,input-colorspace = "rgb"; ++ adi,input-clock = "1x"; ++ adi,input-style = <1>; ++ adi,input-justification = "evenly"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ adv7511_in: endpoint { ++ remote-endpoint = <&lvds_enc_out>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ adv7511_out: endpoint { ++ remote-endpoint = <&hdmi_con>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c3 { ++ pinctrl-0 = <&i2c3_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++ clock-frequency = <400000>; ++}; ++ ++&wdt0 { ++ status = "okay"; ++}; ++ ++&avb { ++ pinctrl-0 = <&avb_pins>; ++ pinctrl-names = "default"; ++ renesas,no-ether-link; ++ phy-handle = <&phy0>; ++ status = "okay"; ++ phy-int-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>; ++ ++ phy0: ethernet-phy@0 { ++ rxc-skew-ps = <1500>; ++ rxdv-skew-ps = <420>; /* default */ ++ rxd0-skew-ps = <420>; /* default */ ++ rxd1-skew-ps = <420>; /* default */ ++ rxd2-skew-ps = <420>; /* default */ ++ rxd3-skew-ps = <420>; /* default */ ++ txc-skew-ps = <900>; /* default */ ++ txen-skew-ps = <420>; /* default */ ++ txd0-skew-ps = <420>; /* default */ ++ txd1-skew-ps = <420>; /* default */ ++ txd2-skew-ps = <420>; /* default */ ++ txd3-skew-ps = <420>; /* default */ ++ reg = <0>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <17 IRQ_TYPE_LEVEL_LOW>; ++ max-speed = <1000>; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi +new file mode 100644 +index 0000000..4ca502f +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi +@@ -0,0 +1,518 @@ ++/* ++ * Device Tree Source for the H3ULCB Kingfisher board: ++ * this adding conflicting resource on VIN4/VIN5/VIN6/VIN7 for CN11 ++ * use CN11 instead default CN29/CN48 ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++&i2cswitch4 { ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ /* Slot B (CN11) */ ++ ++ ov106xx@4 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x64>; ++ ++ port@0 { ++ ov106xx_in4: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin4ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ ov106xx_ti964_des1ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep0>; ++ }; ++ ov106xx_ti954_des1ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@5 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x65>; ++ ++ port@0 { ++ ov106xx_in5: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin5ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ ov106xx_ti964_des1ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep1>; ++ }; ++ ov106xx_ti954_des1ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@6 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x66>; ++ port@0 { ++ ov106xx_in6: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin6ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ ov106xx_ti964_des1ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@7 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x67>; ++ port@0 { ++ ov106xx_in7: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin7ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ ov106xx_ti964_des1ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep3>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@1 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti964_des1ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ ti964_des1ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ ti964_des1ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ ti964_des1ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ ti964_csi2ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@1 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_b_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti954_des1ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ ti954_des1ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ }; ++ port@1 { ++ ti954_csi2ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ ++ /* MAX9286 @ 0x2c */ ++ max9286-max9271@1 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des1ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ max9286_des1ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ max9286_des1ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ max9286_des1ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ max9286_csi2ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@6 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <6>; ++ /* Slot B (CN11) */ ++ ++ video_b_ext0: pca9535@27 { ++ compatible = "nxp,pca9535"; ++ reg = <0x27>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_b_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg1"; ++ }; ++ video_b_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg0"; ++ }; ++ video_b_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR_SHDN"; ++ }; ++ video_b_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR0"; ++ }; ++ video_b_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR1"; ++ }; ++ video_b_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR2"; ++ }; ++ video_b_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR3"; ++ }; ++ video_b_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B DES_SHDN"; ++ }; ++ video_b_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B led"; ++ }; ++ }; ++ ++ video_b_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_b_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg2"; ++ }; ++ video_b_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg1"; ++ }; ++ video_b_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg0"; ++ }; ++ video_b_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR_SHDN"; ++ }; ++ video_b_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR0"; ++ }; ++ video_b_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR1"; ++ }; ++ video_b_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR2"; ++ }; ++ video_b_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR3"; ++ }; ++ video_b_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B DES_SHDN"; ++ }; ++ video_b_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B LED"; ++ }; ++ }; ++ }; ++}; ++ ++&vin4 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi41"; ++ virtual,channel = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin4_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ vin4_ti964_des1ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep0>; ++ }; ++ vin4_ti954_des1ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin5 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin5ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep1: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin5_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ vin5_ti964_des1ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep1>; ++ }; ++ vin5_ti954_des1ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin6 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin6ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <2>; ++ remote-endpoint = <&ov106xx_in6>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep2: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin6_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ vin6_ti964_des1ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin7 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin7ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <3>; ++ remote-endpoint = <&ov106xx_in7>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep3: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin7_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ vin7_ti964_des1ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&csi2_41 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_41_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi +new file mode 100644 +index 0000000..b854216 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi +@@ -0,0 +1,46 @@ ++/* ++ * Device Tree Source for the H3/M3ULCB Kingfisher board: ++ * this overrides WIFI in favour SD on SDHI3 ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++&sdio_switch { ++ regulator-name = "sd_on"; ++ enable-active-high; ++}; ++ ++&vccq_sdhi3 { ++ compatible = "regulator-gpio"; ++ ++ regulator-min-microvolt = <1800000>; ++ ++ gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; ++ gpios-states = <1>; ++ states = <3300000 1 ++ 1800000 0>; ++}; ++ ++&sdhi3 { ++ /delete-property/non-removable; ++ /delete-property/cap-power-off-card; ++ /delete-property/keep-power-in-suspend; ++ /delete-property/enable-sdio-wakeup; ++ /delete-property/max-frequency; ++ /delete-property/no-1-8-v; ++ ++ vmmc-supply = <&vcc_sdhi3>; ++ cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; ++ wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; ++// sd-uhs-sdr50; ++// sd-uhs-sdr104; ++}; ++ ++&wlcore { ++ status = "disabled"; ++}; +diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +new file mode 100644 +index 0000000..4ead97a +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +@@ -0,0 +1,1520 @@ ++/* ++ * Device Tree Source for the ULCB Kingfisher board ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++/ { ++ aliases { ++ serial1 = &hscif0; ++ serial2 = &hscif1; ++ serial3 = &scif1; ++ }; ++ ++ snd_clk: snd_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24576000>; ++ clock-output-names = "scki"; ++ }; ++ ++ wlan_en: regulator@4 { ++ compatible = "regulator-fixed"; ++ regulator-name = "wlan-en-regulator"; ++ ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_74 4 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ vcc_sdhi3: regulator@41 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "SDHI3 Vcc"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ vccq_sdhi3: regulator@5 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "SDHI3 VccQ"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ codec_en_reg: regulator@6 { ++ compatible = "regulator-fixed"; ++ regulator-name = "codec-en-regulator"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_74 15 0>; ++ ++ /* delay - CHECK */ ++ startup-delay-us = <70000>; ++ enable-active-high; ++ }; ++ ++ amp_en_reg: regulator@7 { ++ compatible = "regulator-fixed"; ++ regulator-name = "amp-en-regulator"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_74 0 0>; ++ ++ startup-delay-us = <0>; ++ enable-active-high; ++ }; ++ ++ sdio_switch: regulator@9 { ++ compatible = "regulator-fixed"; ++ regulator-name = "wifi_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_74 5 0>; ++ enable-active-low; ++ regulator-always-on; ++ }; ++ ++ radio_switch: regulator@11 { ++ compatible = "regulator-fixed"; ++ regulator-name = "radio_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_74 13 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ mpcie_3v3: regulator@12 { ++ compatible = "regulator-fixed"; ++ regulator-name = "mPCIe 3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_77 14 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ mpcie_1v8: regulator@13 { ++ compatible = "regulator-fixed"; ++ regulator-name = "mPCIe 1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ gpio = <&gpio_ext_77 15 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <200000>; ++ enable-active-high; ++ }; ++ ++ kim { ++ compatible = "kim"; ++ shutdown-gpios = <&gpio_ext_74 3 GPIO_ACTIVE_HIGH>; ++ /* serial1 */ ++ dev_name = "/dev/ttySC1"; ++ flow_cntrl = <1>; ++ /* int div 8 hscif@26.6666656MHz */ ++ baud_rate = <3333332>; ++ }; ++ ++ btwilink { ++ compatible = "btwilink"; ++ }; ++ ++ sound_ext: sound@0 { ++ pinctrl-0 = <&sound_0_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; ++ ++ simple-audio-card,format = "left_j"; ++ simple-audio-card,name = "pcm3168a"; ++ ++ simple-audio-card,bitclock-master = <&sound_ext_master>; ++ simple-audio-card,frame-master = <&sound_ext_master>; ++ sound_ext_master: simple-audio-card,cpu@0 { ++ sound-dai = <&rcar_sound 0>; ++ dai-tdm-slot-num = <8>; ++ dai-tdm-slot-width = <32>; ++ }; ++ ++ simple-audio-card,codec@0 { ++ sound-dai = <&pcm3168a>; ++ dai-tdm-slot-num = <8>; ++ dai-tdm-slot-width = <32>; ++ system-clock-frequency = <24576000>; ++ }; ++ }; ++ ++ /delete-node/sound; ++ ++ rsnd_ak4613: sound@1 { ++ pinctrl-0 = <&sound_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; ++ ++ simple-audio-card,format = "left_j"; ++ simple-audio-card,name = "ak4613"; ++ ++ simple-audio-card,bitclock-master = <&sndcpu>; ++ simple-audio-card,frame-master = <&sndcpu>; ++ ++ sndcpu: simple-audio-card,cpu@1 { ++ sound-dai = <&rcar_sound 1>; ++ }; ++ ++ sndcodec: simple-audio-card,codec@1 { ++ sound-dai = <&ak4613>; ++ }; ++ }; ++ ++ sound_radio: sound@2 { ++ pinctrl-0 = <&sound_2_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; ++ ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "radio"; ++ ++ simple-audio-card,bitclock-master = <&sound_radio_master>; ++ simple-audio-card,frame-master = <&sound_radio_master>; ++ simple-audio-card,cpu@2 { ++ sound-dai = <&rcar_sound 2>; ++ }; ++ ++ sound_radio_master: simple-audio-card,codec@2 { ++ sound-dai = <&radio>; ++ system-clock-frequency = <12288000>; ++ }; ++ }; ++ ++ sound_wl18xx: sound@3 { ++ pinctrl-0 = <&sound_3_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; ++ ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "wl18xx"; ++ ++ simple-audio-card,bitclock-master = <&sound_wl18xx_master>; ++ simple-audio-card,frame-master = <&sound_wl18xx_master>; ++ sound_wl18xx_master: simple-audio-card,cpu@3 { ++ sound-dai = <&rcar_sound 3>; ++ }; ++ ++ simple-audio-card,codec@3 { ++ sound-dai = <&wl18xx_pcm>; ++ }; ++ }; ++ ++ lvds-encoder { ++ compatible = "thine,thc63lvdm83d"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port@0 { ++ reg = <0>; ++ lvds_enc_in: endpoint { ++ remote-endpoint = <&du_out_lvds0>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ lvds_enc_out: endpoint { ++ remote-endpoint = <&lvds_in>; ++ }; ++ }; ++ }; ++ }; ++ ++ lvds { ++ compatible = "lvds-connector"; ++ ++ width-mm = <210>; ++ height-mm = <158>; ++ ++ panel-timing { ++ /* 1280x800 @60Hz */ ++ clock-frequency = <65000000>; ++ hactive = <1280>; ++ vactive = <800>; ++ hsync-len = <40>; ++ hfront-porch = <80>; ++ hback-porch = <40>; ++ vfront-porch = <14>; ++ vback-porch = <14>; ++ vsync-len = <4>; ++ }; ++ ++ port { ++ lvds_in: endpoint { ++ remote-endpoint = <&lvds_enc_out>; ++ }; ++ }; ++ }; ++ ++ hdmi-out { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con: endpoint { ++ remote-endpoint = <&adv7513_out>; ++ }; ++ }; ++ }; ++ ++ radio: si468x@0 { ++ compatible = "si,si468x-pcm"; ++ status = "okay"; ++ ++ #sound-dai-cells = <0>; ++ }; ++ ++ wl18xx_pcm: wl18xx_pcm@0 { ++ compatible = "ti,wl18xx-pcm"; ++ status = "okay"; ++ ++ #sound-dai-cells = <0>; ++ }; ++ ++ camera_clk: camera_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24000000>; ++ clock-output-names = "mclk"; ++ }; ++}; ++ ++&pfc { ++ scif1_pins: scif1 { ++ groups = "scif1_data_b"; ++ function = "scif1"; ++ }; ++ ++ hscif0_pins: hscif0 { ++ groups = "hscif0_data", "hscif0_ctrl"; ++ function = "hscif0"; ++ }; ++ ++ hscif1_pins: hscif1 { ++ groups = "hscif1_data_a", "hscif1_ctrl_a"; ++ function = "hscif1"; ++ }; ++ ++ du_pins: du { ++ groups = "du_rgb888", "du_sync", "du_clk_out_0", "du_disp"; ++ function = "du"; ++ }; ++ ++ sdhi3_pins_3v3: sd3_3v3 { ++ groups = "sdhi3_data4", "sdhi3_ctrl"; ++ function = "sdhi3"; ++ power-source = <3300>; ++ }; ++ ++ sdhi3_pins_1v8: sd3_1v8 { ++ groups = "sdhi3_data4", "sdhi3_ctrl"; ++ function = "sdhi3"; ++ power-source = <1800>; ++ }; ++ ++ sound_0_pins: sound0 { ++ groups = "ssi34_ctrl", "ssi3_data", "ssi4_data"; ++ function = "ssi"; ++ }; ++ ++ /* sound_pins defined in H3 or M3 ulsb file */ ++ ++ sound_2_pins: sound2 { ++ groups = "ssi6_ctrl", "ssi6_data"; ++ function = "ssi"; ++ }; ++ ++ sound_3_pins: sound3 { ++ groups = "ssi78_ctrl", "ssi7_data", "ssi8_data"; ++ function = "ssi"; ++ }; ++ ++ usb0_pins: usb0 { ++ groups = "usb0"; ++ function = "usb0"; ++ }; ++ ++ can0_pins: can0 { ++ groups = "can0_data_a"; ++ function = "can0"; ++ }; ++ ++ can1_pins: can1 { ++ groups = "can1_data"; ++ function = "can1"; ++ }; ++ ++ canfd0_pins: canfd0 { ++ groups = "canfd0_data_a"; ++ function = "canfd0"; ++ }; ++ ++ canfd1_pins: canfd1 { ++ groups = "canfd1_data"; ++ function = "canfd1"; ++ }; ++ ++ vin5_pins: vin5 { ++ groups = "vin5_data8", "vin5_sync", "vin5_clk"; ++ function = "vin5"; ++ }; ++}; ++ ++&du { ++ pinctrl-0 = <&du_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&gpio2 { ++ bl_pwm { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "BL PWM 100%"; ++ }; ++}; ++ ++&gpio6 { ++ audio_sw { ++ gpio-hog; ++ gpios = <21 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Onboard MCh Audio"; ++ }; ++}; ++ ++&scif1 { ++ pinctrl-0 = <&scif1_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&hscif0 { ++ pinctrl-0 = <&hscif0_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ ++ status = "okay"; ++}; ++ ++&hscif1 { ++ pinctrl-0 = <&hscif1_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&i2c2 { ++ clock-frequency = <400000>; ++ ++ gpio_ext_74: pca9539@74 { ++ compatible = "nxp,pca9539"; ++ reg = <0x74>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio6>; ++ interrupts = <8 IRQ_TYPE_EDGE_FALLING>; ++ ++ hub_pwen { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "HUB pwen"; ++ }; ++ hub_rst { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "HUB rst"; ++ }; ++ otg_offvbus { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "OTG off VBUSn"; ++ }; ++ otg_extlpn { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "OTG EXTLPn"; ++ }; ++ otg_stat1 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "OTG Stat1"; ++ }; ++ otg_stat2 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "OTG Stat2"; ++ }; ++ }; ++ ++ gpio_ext_75: pca9539@75 { ++ compatible = "nxp,pca9539"; ++ reg = <0x75>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio6>; ++ interrupts = <4 IRQ_TYPE_EDGE_FALLING>; ++ ++ gps_rst { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "GPS rst"; ++ }; ++ fpdl_shdn { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "FPDLink shdn"; ++ }; ++ }; ++ ++ i2cswitch2: pca9548@71 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x71>; ++ reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ /* BCM node(s) */ ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ /* USB3.0 HUB node(s) */ ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ /* Power amp node(s) */ ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ /* Radio node(s) */ ++ }; ++ ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ ++ hdmi@3d { ++ compatible = "adi,adv7511w"; ++ reg = <0x3d>; ++// interrupt-parent = <&gpio2>; ++// interrupts = <0 IRQ_TYPE_EDGE_BOTH>; ++ pd-gpios = <&gpio_ext_75 5 GPIO_ACTIVE_LOW>; ++ ++ adi,input-depth = <8>; ++ adi,input-colorspace = "rgb"; ++ adi,input-clock = "1x"; ++ adi,input-style = <1>; ++ adi,input-justification = "evenly"; ++ adi,clock-delay = <1200>; ++ adi,clock-max-rate = <100000>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ adv7513_in: endpoint { ++ remote-endpoint = <&du_out_rgb>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ adv7513_out: endpoint { ++ remote-endpoint = <&hdmi_con>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ /* PCIe node(s) */ ++ }; ++ ++ i2c@6 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <6>; ++ /* LVDS display node(s) */ ++ ++ polytouch: edt-ft5x06@38 { ++ compatible = "edt,edt-ft5x06"; ++ reg = <0x38>; ++ interrupt-parent = <&gpio5>; ++ interrupts = <6 IRQ_TYPE_EDGE_FALLING>; ++ }; ++ }; ++ ++ i2c@7 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <7>; ++ /* Audio, GPS and Gyro node(s) */ ++ ++ pcm3168a: audio-codec@44 { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm3168a"; ++ reg = <0x44>; ++ clocks = <&snd_clk>; ++ clock-names = "scki"; ++ tdm; ++ VDD1-supply = <&codec_en_reg>; ++ VDD2-supply = <&codec_en_reg>; ++ VCCAD1-supply = <&codec_en_reg>; ++ VCCAD2-supply = <&codec_en_reg>; ++ VCCDA1-supply = <&_en_reg>; ++ VCCDA2-supply = <&_en_reg>; ++ }; ++ ++ lsm9ds0_acc_mag@1d { ++ compatible = "st,lsm9ds0_accel_magn"; ++ reg = <0x1d>; ++ }; ++ ++ lsm9ds0_gyr@6b { ++ compatible = "st,lsm9ds0_gyro"; ++ reg = <0x6b>; ++ }; ++ ++ /* GPS@ 0x42 */ ++ }; ++ }; ++}; ++ ++&i2c4 { ++ gpio_ext_76: pca9539@76 { ++ compatible = "nxp,pca9539"; ++ reg = <0x76>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio7>; ++ interrupts = <3 IRQ_TYPE_EDGE_FALLING>; ++ ++ port_b_a0 { ++ gpio-hog; ++ gpios = <0 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B A0"; ++ }; ++ port_b_a1 { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B A1"; ++ }; ++ port_a_a0 { ++ gpio-hog; ++ gpios = <2 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A A0"; ++ }; ++ port_a_a1 { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A A1"; ++ }; ++ cmos_pwdn { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CMOS PWDN"; ++ }; ++ cmos_rst { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CMOS RST"; ++ }; ++ /* pin 12 - CAM_CLK */ ++ rpi_cam_io_1 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "RaspB_IO1"; ++ }; ++ /* pin 11 - CAM_GPIO - assume pwdn */ ++ rpi_cam_io_0 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "RaspB_IO0"; ++ }; ++ sam_rst { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "SAM RST"; ++ }; ++ sam_pwr { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "SAM PWR"; ++ }; ++ /* 0 - FPDLink output, 1 - LVDS output */ ++ lvds_vs_fpdl { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "LVDS switch"; ++ }; ++ }; ++ ++ gpio_ext_77: pca9539@77 { ++ compatible = "nxp,pca9539"; ++ reg = <0x77>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio5>; ++ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; ++ ++ mpcie_wake { ++ gpio-hog; ++ gpios = <0 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "mPCIe WAKE#"; ++ }; ++ mpcie_wdisable { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "mPCIe W_DISABLE"; ++ }; ++ mpcie_clreq { ++ gpio-hog; ++ gpios = <2 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "mPCIe CLKREQ#"; ++ }; ++ mpcie_ovc { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "mPCIe OVC"; ++ }; ++ }; ++ ++ i2cswitch4: pca9548@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x71>; ++ reset-gpios= <&gpio3 15 GPIO_ACTIVE_LOW>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ /* SAM node(s) */ ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ /* Slot A (CN10) */ ++ ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ ov106xx_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ ov106xx_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; ++ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ ov106xx_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ ov106xx_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; ++ ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ ov106xx_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ ov106xx_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@0 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti964_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti964_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ ti964_des0ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ ti964_des0ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ ti964_csi0ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@0 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_a_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti954_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti954_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ ti954_csi0ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ /* MAX9286 @ 0x2c */ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ /* MOST node(s) */ ++ }; ++ ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ ++ rpi_camera: ov5647@36 { ++ compatible = "ovti,ov5647"; ++ reg = <0x36>; ++ ++ port@0 { ++ rpi_camera_in: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ remote-endpoint = <&vin4ep0>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ ++ cmos_camera: ov5642@3c { ++ compatible = "ovti,ov5642"; ++ reg = <0x3c>; ++ clocks = <&camera_clk>; ++ clock-names = "mclk"; ++ ++ port@0 { ++ cmos_camera_in: endpoint { ++ remote-endpoint = <&vin5ep0>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@7 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <7>; ++ /* Slot A (CN10) */ ++ ++ video_a_ext0: pca9535@26 { ++ compatible = "nxp,pca9535"; ++ reg = <0x26>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; ++ }; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; ++ }; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; ++ }; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A led"; ++ }; ++ }; ++ ++ video_a_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg2"; ++ }; ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; ++ }; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; ++ }; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; ++ }; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A LED"; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&pcie_bus_clk { ++ clock-frequency = <100000000>; ++ status = "okay"; ++}; ++ ++&pciec0 { ++ status = "okay"; ++}; ++ ++&pciec1 { ++ status = "okay"; ++}; ++ ++&vin0 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ vin0_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ vin0_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ vin1_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ vin1_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin2 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ vin2_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin3 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ vin3_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&vin4 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi20"; ++ virtual,channel = <0>; ++ remote-endpoint = <&rpi_camera_in>; ++ data-lanes = <1 2>; ++ }; ++ }; ++ port@1 { ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_20_ep>; ++ }; ++ }; ++ }; ++}; ++ ++&vin5 { ++ pinctrl-0 = <&vin5_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin5ep0: endpoint@0 { ++ bus-width = <8>; ++ /* #HSYNC, #VSYNC */ ++ vsync-active = <1>; ++ hsync-active = <0>; ++ remote-endpoint = <&cmos_camera_in>; ++ }; ++ }; ++ }; ++}; ++ ++&csi2_40 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&csi2_20 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "raw8"; ++ receive,vc = <0>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_20_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ csi-rate = <280>; ++ }; ++ }; ++}; ++ ++ ++&rcar_sound { ++ pinctrl-0 = <&sound_clk_pins>; ++ pinctrl-names = "default"; ++ ++ /* Multi DAI */ ++ #sound-dai-cells = <1>; ++ ++ rcar_sound,dai { ++ dai0 { ++ playback = <&ssi3>; ++ capture = <&ssi4>; ++ }; ++ ++ dai1 { ++ playback = <&ssi0 &src0 &dvc0>; ++ capture = <&ssi1 &src1 &dvc1>; ++ }; ++ ++ dai2 { ++ capture = <&ssi6>; ++ }; ++ ++ dai3 { ++ playback = <&ssi7>; ++ capture = <&ssi8>; ++ }; ++ }; ++}; ++ ++&sdhi3 { ++ pinctrl-0 = <&sdhi3_pins_3v3>; ++ pinctrl-1 = <&sdhi3_pins_1v8>; ++ pinctrl-names = "default", "state_uhs"; ++ ++ vmmc-supply = <&wlan_en>; ++ vqmmc-supply = <&vccq_sdhi3>; ++ keep-power-in-suspend; ++ enable-sdio-wakeup; ++ bus-width = <4>; ++ no-1-8-v; ++ non-removable; ++ cap-power-off-card; ++ max-frequency = <26000000>; ++ status = "okay"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ wlcore: wlcore@2 { ++ compatible = "ti,wl1837"; ++ reg = <2>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <25 IRQ_TYPE_EDGE_FALLING>; ++ }; ++}; ++ ++&usb2_phy0 { ++ pinctrl-0 = <&usb0_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&xhci0 { ++ status = "okay"; ++}; ++ ++&msiof1 { ++ status = "disabled"; ++}; ++ ++&can0 { ++ pinctrl-0 = <&can0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; ++}; ++ ++&can1 { ++ pinctrl-0 = <&can1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; ++}; ++ ++&canfd { ++ pinctrl-0 = <&canfd0_pins &canfd1_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ ++ channel0 { ++ status = "okay"; ++ }; ++ ++ channel1 { ++ status = "okay"; ++ }; ++}; ++ ++&ssi4 { ++ shared-pin; ++}; ++ ++&ssi8 { ++ shared-pin; ++}; ++ ++&pciec1 { ++ pcie3v3-supply = <&mpcie_3v3>; ++ pcie1v8-supply = <&mpcie_1v8>; ++}; ++ ++/* uncomment to enable CN47: SD on SDHI3 */ ++//#include "ulcb-kf-sd3.dtsi" +diff --git a/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi b/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi +new file mode 100644 +index 0000000..92ed4a4 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi +@@ -0,0 +1,515 @@ ++/* ++ * Device Tree Source for the H3ULCB Videobox board: ++ * this adding conflicting resource on VIN4/VIN5/VIN6/VIN7 for CN12 ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++&i2cswitch2 { ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ /* Slot C (CN12) */ ++ ++ ov106xx@8 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x68>; ++ ++ port@0 { ++ ov106xx_in8: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ remote-endpoint = <&vin4ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des2ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des2ep0>; ++ }; ++ ov106xx_ti964_des2ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des2ep0>; ++ }; ++ ov106xx_ti954_des2ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des2ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@9 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x69>; ++ ++ port@0 { ++ ov106xx_in9: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ remote-endpoint = <&vin5ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des2ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des2ep1>; ++ }; ++ ov106xx_ti964_des2ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des2ep1>; ++ }; ++ ov106xx_ti954_des2ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des2ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@10 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x6a>; ++ ++ port@0 { ++ ov106xx_in10: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ remote-endpoint = <&vin6ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des2ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des2ep2>; ++ }; ++ ov106xx_ti964_des2ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des2ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@11 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x6b>; ++ ++ port@0 { ++ ov106xx_in11: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ remote-endpoint = <&vin7ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des2ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des2ep3>; ++ }; ++ ov106xx_ti964_des2ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des2ep3>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@2 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <2>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti964_des2ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in8>; ++ }; ++ ti964_des2ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in9>; ++ }; ++ ti964_des2ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in10>; ++ }; ++ ti964_des2ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in11>; ++ }; ++ }; ++ port@1 { ++ ti964_csi1ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_20_ep>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@2 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_c_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <2>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti954_des2ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in8>; ++ }; ++ ti954_des2ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in9>; ++ }; ++ }; ++ port@1 { ++ ti954_csi1ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_20_ep>; ++ }; ++ }; ++ }; ++ ++ /* MAX9286 @ 0x2c */ ++ max9286-max9271@2 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <2>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des2ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in8>; ++ }; ++ max9286_des2ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in9>; ++ }; ++ max9286_des2ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in10>; ++ }; ++ max9286_des2ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in11>; ++ }; ++ }; ++ port@1 { ++ max9286_csi1ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_20_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ /* Slot C (CN12) */ ++ ++ video_c_ext0: pca9535@26 { ++ compatible = "nxp,pca9535"; ++ reg = <0x26>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_c_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-C cfg1"; ++ }; ++ video_c_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-C cfg0"; ++ }; ++ video_c_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR_SHDN"; ++ }; ++ video_c_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR0"; ++ }; ++ video_c_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR1"; ++ }; ++ video_c_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR2"; ++ }; ++ video_c_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR3"; ++ }; ++ video_c_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C DES_SHDN"; ++ }; ++ video_c_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-C led"; ++ }; ++ }; ++ ++ video_c_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_c_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-C cfg2"; ++ }; ++ video_c_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-C cfg1"; ++ }; ++ video_c_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-C cfg0"; ++ }; ++ video_c_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR_SHDN"; ++ }; ++ video_c_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR0"; ++ }; ++ video_c_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR1"; ++ }; ++ video_c_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR2"; ++ }; ++ video_c_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR3"; ++ }; ++ video_c_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C DES_SHDN"; ++ }; ++ video_c_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-C LED"; ++ }; ++ }; ++ }; ++}; ++ ++&vin4 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi20"; ++ virtual,channel = <0>; ++ remote-endpoint = <&ov106xx_in8>; ++ data-lanes = <1 2>; ++ }; ++ }; ++ port@1 { ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_20_ep>; ++ }; ++ }; ++ port@2 { ++ vin4_max9286_des2ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des2ep0>; ++ }; ++ vin4_ti964_des2ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des2ep0>; ++ }; ++ vin4_ti954_des2ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des2ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin5 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin5ep0: endpoint@0 { ++ csi,select = "csi20"; ++ virtual,channel = <1>; ++ remote-endpoint = <&ov106xx_in9>; ++ data-lanes = <1 2>; ++ }; ++ }; ++ port@1 { ++ csi2ep1: endpoint { ++ remote-endpoint = <&csi2_20_ep>; ++ }; ++ }; ++ port@2 { ++ vin5_max9286_des2ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des2ep1>; ++ }; ++ vin5_ti964_des2ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des2ep1>; ++ }; ++ vin5_ti954_des2ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des2ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin6 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin6ep0: endpoint@0 { ++ csi,select = "csi20"; ++ virtual,channel = <2>; ++ remote-endpoint = <&ov106xx_in10>; ++ data-lanes = <1 2>; ++ }; ++ }; ++ port@1 { ++ csi2ep2: endpoint { ++ remote-endpoint = <&csi2_20_ep>; ++ }; ++ }; ++ port@2 { ++ vin6_max9286_des2ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des2ep2>; ++ }; ++ vin6_ti964_des2ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des2ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin7 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin7ep0: endpoint@0 { ++ csi,select = "csi20"; ++ virtual,channel = <3>; ++ remote-endpoint = <&ov106xx_in11>; ++ data-lanes = <1 2>; ++ }; ++ }; ++ port@1 { ++ csi2ep3: endpoint { ++ remote-endpoint = <&csi2_20_ep>; ++ }; ++ }; ++ port@2 { ++ vin7_max9286_des2ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des2ep3>; ++ }; ++ vin7_ti964_des2ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des2ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&csi2_20 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_20_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ csi-rate = <300>; ++ }; ++ }; ++}; +-- +1.9.1 + -- cgit 1.2.3-korg From c949a23c050f08fbefef44fd2ec3d4926317b9ed Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Mon, 25 Sep 2017 07:59:11 +0300 Subject: Add MOST --- .../0040-arm64-dts-renesas-add-ADAS-boards.patch | 24 ++- .../0044-pinctrl-r8a779x-add-mlb-pinmux.patch | 154 +++++++++++++++++++ .../0045-clk-r8a779x-add-mlp-clock.patch | 38 +++++ ...6-arm64-dts-renesas-r8a779x-add-mlp-nodes.patch | 87 +++++++++++ .../0073-MOST-dim2-add-device-tree-support.patch | 169 +++++++++++++++++++++ ...ST-dim2-add-R-Car3-related-initialization.patch | 63 ++++++++ ...-MOST-core-fix-memory-allocation-at-arm64.patch | 54 +++++++ .../0076-MOST-dim2-Renesas-R-Car3-variant.patch | 120 +++++++++++++++ .../0077-MOST-dim2-add-timeouts.patch | 46 ++++++ .../linux/linux-renesas_4.9.bbappend | 8 + 10 files changed, 762 insertions(+), 1 deletion(-) create mode 100644 meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0044-pinctrl-r8a779x-add-mlb-pinmux.patch create mode 100644 meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0045-clk-r8a779x-add-mlp-clock.patch create mode 100644 meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0046-arm64-dts-renesas-r8a779x-add-mlp-nodes.patch create mode 100644 meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0073-MOST-dim2-add-device-tree-support.patch create mode 100644 meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0074-MOST-dim2-add-R-Car3-related-initialization.patch create mode 100644 meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0075-MOST-core-fix-memory-allocation-at-arm64.patch create mode 100644 meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0076-MOST-dim2-Renesas-R-Car3-variant.patch create mode 100644 meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0077-MOST-dim2-add-timeouts.patch (limited to 'meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch') diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch index 4acd0f1..dc4649a 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch @@ -15509,7 +15509,7 @@ new file mode 100644 index 0000000..4ead97a --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi -@@ -0,0 +1,1520 @@ +@@ -0,0 +1,1542 @@ +/* + * Device Tree Source for the ULCB Kingfisher board + * @@ -15887,6 +15887,11 @@ index 0000000..4ead97a + groups = "vin5_data8", "vin5_sync", "vin5_clk"; + function = "vin5"; + }; ++ ++ mlp_pins: mlp { ++ groups = "mlb_3pin"; ++ function = "mlb_3pin"; ++ }; +}; + +&du { @@ -15903,6 +15908,15 @@ index 0000000..4ead97a + }; +}; + ++&gpio4 { ++ most_rst { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "MOST RST"; ++ }; ++}; ++ +&gpio6 { + audio_sw { + gpio-hog; @@ -17028,6 +17042,14 @@ index 0000000..4ead97a + pcie1v8-supply = <&mpcie_1v8>; +}; + ++&mlp { ++ pinctrl-0 = <&mlp_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ clock-speed = "1024fs"; ++}; ++ +/* uncomment to enable CN47: SD on SDHI3 */ +//#include "ulcb-kf-sd3.dtsi" diff --git a/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi b/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0044-pinctrl-r8a779x-add-mlb-pinmux.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0044-pinctrl-r8a779x-add-mlb-pinmux.patch new file mode 100644 index 0000000..8541e19 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0044-pinctrl-r8a779x-add-mlb-pinmux.patch @@ -0,0 +1,154 @@ +From 7f797fef45307ed6c5960cc116ce8de65d192269 Mon Sep 17 00:00:00 2001 +From: Andrey Gusakov +Date: Fri, 7 Jul 2017 16:22:40 +0300 +Subject: [PATCH] pinctrl: r8a779x: add mlb pinmux + +Signed-off-by: Andrey Gusakov +Signed-off-by: Vladimir Barinov +--- + drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 14 ++++++++++++++ + drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 14 ++++++++++++++ + drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 14 ++++++++++++++ + 3 files changed, 42 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +index 378065d..f544546 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +@@ -2403,6 +2403,14 @@ enum { + IRQ5_MARK, + }; + ++/* - MLB+ ------------------------------------------------------------------- */ ++static const unsigned int mlb_3pin_pins[] = { ++ RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), ++}; ++static const unsigned int mlb_3pin_mux[] = { ++ MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, ++}; ++ + /* - MSIOF0 ----------------------------------------------------------------- */ + static const unsigned int msiof0_clk_pins[] = { + /* SCK */ +@@ -4266,6 +4274,7 @@ enum { + SH_PFC_PIN_GROUP(intc_ex_irq3), + SH_PFC_PIN_GROUP(intc_ex_irq4), + SH_PFC_PIN_GROUP(intc_ex_irq5), ++ SH_PFC_PIN_GROUP(mlb_3pin), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), +@@ -4682,6 +4691,10 @@ enum { + "intc_ex_irq5", + }; + ++static const char * const mlb_3pin_groups[] = { ++ "mlb_3pin", ++}; ++ + static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", +@@ -5032,6 +5045,7 @@ enum { + SH_PFC_FUNCTION(i2c5), + SH_PFC_FUNCTION(i2c6), + SH_PFC_FUNCTION(intc_ex), ++ SH_PFC_FUNCTION(mlb_3pin), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +index 1198998..928bbbc 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +@@ -2466,6 +2466,14 @@ enum { + IRQ5_MARK, + }; + ++/* - MLB+ ------------------------------------------------------------------- */ ++static const unsigned int mlb_3pin_pins[] = { ++ RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), ++}; ++static const unsigned int mlb_3pin_mux[] = { ++ MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, ++}; ++ + /* - MSIOF0 ----------------------------------------------------------------- */ + static const unsigned int msiof0_clk_pins[] = { + /* SCK */ +@@ -4387,6 +4395,7 @@ enum { + SH_PFC_PIN_GROUP(intc_ex_irq3), + SH_PFC_PIN_GROUP(intc_ex_irq4), + SH_PFC_PIN_GROUP(intc_ex_irq5), ++ SH_PFC_PIN_GROUP(mlb_3pin), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), +@@ -4811,6 +4820,10 @@ enum { + "intc_ex_irq5", + }; + ++static const char * const mlb_3pin_groups[] = { ++ "mlb_3pin", ++}; ++ + static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", +@@ -5169,6 +5182,7 @@ enum { + SH_PFC_FUNCTION(i2c5), + SH_PFC_FUNCTION(i2c6), + SH_PFC_FUNCTION(intc_ex), ++ SH_PFC_FUNCTION(mlb_3pin), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +index 1cef61b..26a69dc 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +@@ -2468,6 +2468,14 @@ enum { + IRQ5_MARK, + }; + ++/* - MLB+ ------------------------------------------------------------------- */ ++static const unsigned int mlb_3pin_pins[] = { ++ RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), ++}; ++static const unsigned int mlb_3pin_mux[] = { ++ MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, ++}; ++ + /* - MSIOF0 ----------------------------------------------------------------- */ + static const unsigned int msiof0_clk_pins[] = { + /* SCK */ +@@ -4310,6 +4318,7 @@ enum { + SH_PFC_PIN_GROUP(intc_ex_irq3), + SH_PFC_PIN_GROUP(intc_ex_irq4), + SH_PFC_PIN_GROUP(intc_ex_irq5), ++ SH_PFC_PIN_GROUP(mlb_3pin), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), +@@ -4722,6 +4731,10 @@ enum { + "intc_ex_irq5", + }; + ++static const char * const mlb_3pin_groups[] = { ++ "mlb_3pin", ++}; ++ + static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", +@@ -5054,6 +5067,7 @@ enum { + SH_PFC_FUNCTION(i2c5), + SH_PFC_FUNCTION(i2c6), + SH_PFC_FUNCTION(intc_ex), ++ SH_PFC_FUNCTION(mlb_3pin), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0045-clk-r8a779x-add-mlp-clock.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0045-clk-r8a779x-add-mlp-clock.patch new file mode 100644 index 0000000..ca473a1 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0045-clk-r8a779x-add-mlp-clock.patch @@ -0,0 +1,38 @@ +From 741e7fcf44527632a06538419f000843b24d9293 Mon Sep 17 00:00:00 2001 +From: Andrey Gusakov +Date: Fri, 7 Jul 2017 16:23:44 +0300 +Subject: [PATCH] clk: r8a779x: add mlp clock + +Signed-off-by: Andrey Gusakov +--- + drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 + + drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 + + 2 files changed, 2 insertions(+) + +diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c +index f833031..38d1f41 100644 +--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c ++++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c +@@ -219,6 +219,7 @@ enum clk_ids { + DEF_MOD("lvds", 727, R8A7795_CLK_S0D4), + DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI), + DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI), ++ DEF_MOD("mlp", 802, R8A7795_CLK_S2D1), + DEF_MOD("vin7", 804, R8A7795_CLK_S0D2), + DEF_MOD("vin6", 805, R8A7795_CLK_S0D2), + DEF_MOD("vin5", 806, R8A7795_CLK_S0D2), +diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c +index b938750..6a5936e 100644 +--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c ++++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c +@@ -194,6 +194,7 @@ enum clk_ids { + DEF_MOD("du0", 724, R8A7796_CLK_S2D1), + DEF_MOD("lvds", 727, R8A7796_CLK_S2D1), + DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI), ++ DEF_MOD("mlp", 802, R8A7796_CLK_S2D1), + DEF_MOD("vin7", 804, R8A7796_CLK_S0D2), + DEF_MOD("vin6", 805, R8A7796_CLK_S0D2), + DEF_MOD("vin5", 806, R8A7796_CLK_S0D2), +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0046-arm64-dts-renesas-r8a779x-add-mlp-nodes.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0046-arm64-dts-renesas-r8a779x-add-mlp-nodes.patch new file mode 100644 index 0000000..1f17f0e --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0046-arm64-dts-renesas-r8a779x-add-mlp-nodes.patch @@ -0,0 +1,87 @@ +From 8d5de721b2e037ce77f886a4307ea5668df9417f Mon Sep 17 00:00:00 2001 +From: Andrey Gusakov +Date: Fri, 7 Jul 2017 16:25:06 +0300 +Subject: [PATCH] arm64: dts: renesas: r8a779x: add mlp nodes + +Signed-off-by: Andrey Gusakov +--- + arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 13 +++++++++++++ + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 13 +++++++++++++ + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 13 +++++++++++++ + 3 files changed, 39 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi +index 89c70bb7738b..44a290b32899 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi +@@ -2072,6 +2072,19 @@ + status = "disabled"; + }; + ++ mlp: mlp@ec520000 { ++ compatible = "rcar,medialb-dim2"; ++ reg = <0 0xec520000 0 0x800>; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ clocks = <&cpg CPG_MOD 802>; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ status = "disabled"; ++ }; ++ + msiof0: spi@e6e90000 { + #address-cells = <1>; + #size-cells = <0>; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +index 89c70bb7738b..44a290b32899 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -2072,6 +2072,19 @@ + status = "disabled"; + }; + ++ mlp: mlp@ec520000 { ++ compatible = "rcar,medialb-dim2"; ++ reg = <0 0xec520000 0 0x800>; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ clocks = <&cpg CPG_MOD 802>; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ status = "disabled"; ++ }; ++ + msiof0: spi@e6e90000 { + #address-cells = <1>; + #size-cells = <0>; +diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +index f430df9df961..565d6e7de4cc 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -1955,6 +1955,19 @@ + status = "disabled"; + }; + ++ mlp: mlp@ec520000 { ++ compatible = "rcar,medialb-dim2"; ++ reg = <0 0xec520000 0 0x800>; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ clocks = <&cpg CPG_MOD 802>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ status = "disabled"; ++ }; ++ + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a7796"; + reg = <0 0xe6ea0000 0 0x0064>; +-- +2.13.0 + diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0073-MOST-dim2-add-device-tree-support.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0073-MOST-dim2-add-device-tree-support.patch new file mode 100644 index 0000000..b3e2e0b --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0073-MOST-dim2-add-device-tree-support.patch @@ -0,0 +1,169 @@ +From cc64770782e6bb01b2d8b76c1731a28d5d06d135 Mon Sep 17 00:00:00 2001 +From: Andrey Gusakov +Date: Fri, 7 Jul 2017 20:42:36 +0300 +Subject: [PATCH] MOST: dim2: add device tree support + +Signed-off-by: Andrey Gusakov +--- + drivers/staging/most/hdm-dim2/dim2_hdm.c | 72 ++++++++++++++++++++++---------- + 1 file changed, 50 insertions(+), 22 deletions(-) + +diff --git a/drivers/staging/most/hdm-dim2/dim2_hdm.c b/drivers/staging/most/hdm-dim2/dim2_hdm.c +index a36449551513..f28f169180fe 100644 +--- a/drivers/staging/most/hdm-dim2/dim2_hdm.c ++++ b/drivers/staging/most/hdm-dim2/dim2_hdm.c +@@ -14,6 +14,7 @@ + #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + + #include ++#include + #include + #include + #include +@@ -21,6 +22,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -101,6 +103,7 @@ struct dim2_hdm { + struct most_interface most_iface; + char name[16 + sizeof "dim2-"]; + void __iomem *io_base; ++ struct clk *clk; + int clk_speed; + struct task_struct *netinfo_task; + wait_queue_head_t netinfo_waitq; +@@ -165,6 +168,27 @@ void dimcb_on_error(u8 error_id, const char *error_message) + error_message); + } + ++static int dim_parce_speed(const char *clock_speed) ++{ ++ if (!strcmp(clock_speed, "256fs")) ++ return CLK_256FS; ++ else if (!strcmp(clock_speed, "512fs")) ++ return CLK_512FS; ++ else if (!strcmp(clock_speed, "1024fs")) ++ return CLK_1024FS; ++ else if (!strcmp(clock_speed, "2048fs")) ++ return CLK_2048FS; ++ else if (!strcmp(clock_speed, "3072fs")) ++ return CLK_3072FS; ++ else if (!strcmp(clock_speed, "4096fs")) ++ return CLK_4096FS; ++ else if (!strcmp(clock_speed, "6144fs")) ++ return CLK_6144FS; ++ else if (!strcmp(clock_speed, "8192fs")) ++ return CLK_8192FS; ++ return -1; ++} ++ + /** + * startup_dim - initialize the dim2 interface + * @pdev: platform device +@@ -178,32 +202,12 @@ static int startup_dim(struct platform_device *pdev) + struct dim2_platform_data *pdata = pdev->dev.platform_data; + u8 hal_ret; + +- dev->clk_speed = -1; +- +- if (clock_speed) { +- if (!strcmp(clock_speed, "256fs")) +- dev->clk_speed = CLK_256FS; +- else if (!strcmp(clock_speed, "512fs")) +- dev->clk_speed = CLK_512FS; +- else if (!strcmp(clock_speed, "1024fs")) +- dev->clk_speed = CLK_1024FS; +- else if (!strcmp(clock_speed, "2048fs")) +- dev->clk_speed = CLK_2048FS; +- else if (!strcmp(clock_speed, "3072fs")) +- dev->clk_speed = CLK_3072FS; +- else if (!strcmp(clock_speed, "4096fs")) +- dev->clk_speed = CLK_4096FS; +- else if (!strcmp(clock_speed, "6144fs")) +- dev->clk_speed = CLK_6144FS; +- else if (!strcmp(clock_speed, "8192fs")) +- dev->clk_speed = CLK_8192FS; +- } ++ if (clock_speed) ++ dev->clk_speed = dim_parce_speed(clock_speed); + + if (dev->clk_speed == -1) { + pr_info("Bad or missing clock speed parameter, using default value: 3072fs\n"); + dev->clk_speed = CLK_3072FS; +- } else { +- pr_info("Selected clock speed: %s\n", clock_speed); + } + if (pdata && pdata->init) { + int ret = pdata->init(pdata, dev->io_base, dev->clk_speed); +@@ -735,6 +739,7 @@ static int dim2_probe(struct platform_device *pdev) + int ret, i; + struct kobject *kobj; + int irq; ++ struct device_node *np = pdev->dev.of_node; + + dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); + if (!dev) +@@ -765,6 +770,14 @@ static int dim2_probe(struct platform_device *pdev) + dev_err(&pdev->dev, "failed to request mlb_int irq %d\n", irq); + return ret; + } ++ ++ dev->clk = devm_clk_get(&pdev->dev, NULL); ++ if (IS_ERR(dev->clk)) { ++ dev_err(&pdev->dev, "cannot get clock\n"); ++ ret = PTR_ERR(dev->clk); ++ return ret; ++ } ++ clk_prepare_enable(dev->clk); + + init_waitqueue_head(&dev->netinfo_waitq); + dev->deliver_netinfo = 0; +@@ -814,6 +827,12 @@ static int dim2_probe(struct platform_device *pdev) + dev->most_iface.poison_channel = poison_channel; + dev->most_iface.request_netinfo = request_netinfo; + ++ if (np) { ++ const char *tmp; ++ if (!of_property_read_string(np, "clock-speed", &tmp)) ++ dev->clk_speed = dim_parce_speed(tmp); ++ } ++ + kobj = most_register_interface(&dev->most_iface); + if (IS_ERR(kobj)) { + ret = PTR_ERR(kobj); +@@ -866,6 +885,8 @@ static int dim2_remove(struct platform_device *pdev) + most_deregister_interface(&dev->most_iface); + kthread_stop(dev->netinfo_task); + ++ clk_disable_unprepare(dev->clk); ++ + /* + * break link to local platform_device_id struct + * to prevent crash by unload platform device module +@@ -882,12 +903,19 @@ static struct platform_device_id dim2_id[] = { + + MODULE_DEVICE_TABLE(platform, dim2_id); + ++static const struct of_device_id dim2_of_match[] = { ++ { .compatible = "rcar,medialb-dim2", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, dim2_of_match); ++ + static struct platform_driver dim2_driver = { + .probe = dim2_probe, + .remove = dim2_remove, + .id_table = dim2_id, + .driver = { + .name = "hdm_dim2", ++ .of_match_table = dim2_of_match, + }, + }; + +-- +2.13.0 + diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0074-MOST-dim2-add-R-Car3-related-initialization.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0074-MOST-dim2-add-R-Car3-related-initialization.patch new file mode 100644 index 0000000..572da2a --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0074-MOST-dim2-add-R-Car3-related-initialization.patch @@ -0,0 +1,63 @@ +From 41d15fa6003b65080f05d271bf495104013754f9 Mon Sep 17 00:00:00 2001 +From: Andrey Gusakov +Date: Fri, 7 Jul 2017 20:43:33 +0300 +Subject: [PATCH 112/114] MOST: dim2: add R-Car3 related initialization + +Signed-off-by: Andrey Gusakov +--- + drivers/staging/most/hdm-dim2/dim2_hdm.c | 28 +++++++++++++++++++++++++++- + 1 file changed, 27 insertions(+), 1 deletion(-) + +diff --git a/drivers/staging/most/hdm-dim2/dim2_hdm.c b/drivers/staging/most/hdm-dim2/dim2_hdm.c +index f28f169180fe..c1beabc28fa8 100644 +--- a/drivers/staging/most/hdm-dim2/dim2_hdm.c ++++ b/drivers/staging/most/hdm-dim2/dim2_hdm.c +@@ -26,6 +26,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -189,6 +191,26 @@ static int dim_parce_speed(const char *clock_speed) + return -1; + } + ++static int dim_rcar_init(struct dim2_hdm *dev) ++{ ++ /* PLL */ ++ __raw_writel(0x04, dev->io_base + 0x600); ++ ++ /* 512FS Enable Register */ ++ if (dev->clk_speed == CLK_512FS) ++ __raw_writel(0x01, dev->io_base + 0x604); ++ else ++ __raw_writel(0x00, dev->io_base + 0x604); ++ ++ udelay(200); ++ ++ /* BBCR = 0b11 */ ++ __raw_writel(0x03, dev->io_base + 0x500); ++ __raw_writel(0x0002FF02, dev->io_base + 0x508); ++ ++ return 0; ++} ++ + /** + * startup_dim - initialize the dim2 interface + * @pdev: platform device +@@ -216,6 +238,10 @@ static int startup_dim(struct platform_device *pdev) + return ret; + } + ++ if (1 /* renesas */) { ++ dim_rcar_init(dev); ++ } ++ + pr_info("sync: num of frames per sub-buffer: %u\n", fcnt); + hal_ret = dim_startup(dev->io_base, dev->clk_speed, fcnt); + if (hal_ret != DIM_NO_ERROR) { +-- +2.13.0 + diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0075-MOST-core-fix-memory-allocation-at-arm64.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0075-MOST-core-fix-memory-allocation-at-arm64.patch new file mode 100644 index 0000000..33a7c3a --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0075-MOST-core-fix-memory-allocation-at-arm64.patch @@ -0,0 +1,54 @@ +From 90bfbf16c895aa53e1d017d4ce7f4f8121e0da3c Mon Sep 17 00:00:00 2001 +From: Andrey Gusakov +Date: Fri, 7 Jul 2017 20:45:01 +0300 +Subject: [PATCH 113/114] MOST: core: fix memory allocation at arm64 + +Provide valid dev pointer to dma_alloc_coherent + +Signed-off-by: Andrey Gusakov +--- + drivers/staging/most/hdm-dim2/dim2_hdm.c | 1 + + drivers/staging/most/mostcore/core.c | 2 +- + drivers/staging/most/mostcore/mostcore.h | 1 + + 3 files changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/staging/most/hdm-dim2/dim2_hdm.c b/drivers/staging/most/hdm-dim2/dim2_hdm.c +index c1beabc28fa8..81edf4f4beb3 100644 +--- a/drivers/staging/most/hdm-dim2/dim2_hdm.c ++++ b/drivers/staging/most/hdm-dim2/dim2_hdm.c +@@ -852,6 +852,7 @@ static int dim2_probe(struct platform_device *pdev) + dev->most_iface.enqueue = enqueue; + dev->most_iface.poison_channel = poison_channel; + dev->most_iface.request_netinfo = request_netinfo; ++ dev->most_iface.dev = &pdev->dev; + + if (np) { + const char *tmp; +diff --git a/drivers/staging/most/mostcore/core.c b/drivers/staging/most/mostcore/core.c +index 7c619feb12d3..ce56d5ca582c 100644 +--- a/drivers/staging/most/mostcore/core.c ++++ b/drivers/staging/most/mostcore/core.c +@@ -1265,7 +1265,7 @@ static int arm_mbo_chain(struct most_c_obj *c, int dir, + mbo->context = c; + mbo->ifp = c->iface; + mbo->hdm_channel_id = c->channel_id; +- mbo->virt_address = dma_alloc_coherent(NULL, ++ mbo->virt_address = dma_alloc_coherent(c->iface->dev, + coherent_buf_size, + &mbo->bus_address, + GFP_KERNEL); +diff --git a/drivers/staging/most/mostcore/mostcore.h b/drivers/staging/most/mostcore/mostcore.h +index 60e018e499ef..334908639067 100644 +--- a/drivers/staging/most/mostcore/mostcore.h ++++ b/drivers/staging/most/mostcore/mostcore.h +@@ -247,6 +247,7 @@ struct most_interface { + struct mbo *mbo); + int (*poison_channel)(struct most_interface *iface, int channel_idx); + void (*request_netinfo)(struct most_interface *iface, int channel_idx); ++ struct device *dev; + void *priv; + }; + +-- +2.13.0 + diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0076-MOST-dim2-Renesas-R-Car3-variant.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0076-MOST-dim2-Renesas-R-Car3-variant.patch new file mode 100644 index 0000000..5ab496b --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0076-MOST-dim2-Renesas-R-Car3-variant.patch @@ -0,0 +1,120 @@ +From d595053486568b5be30fda582becf9240d171c66 Mon Sep 17 00:00:00 2001 +From: Andrey Gusakov +Date: Mon, 25 Sep 2017 7:16:25 +0300 +Subject: [PATCH] MOST: dim2: Renesas R-Car3 variant + +- R-Car H3 has 8 FPSB +- remove not existing registers access + +Signed-off-by: Andrey Gusakov +Signed-off-by: Vladimir Barinov +--- + drivers/staging/most/hdm-dim2/dim2_hal.c | 8 ++++---- + drivers/staging/most/hdm-dim2/dim2_hdm.c | 2 +- + drivers/staging/most/hdm-dim2/dim2_reg.h | 18 +++++++++--------- + 3 files changed, 14 insertions(+), 14 deletions(-) + +diff --git a/drivers/staging/most/hdm-dim2/dim2_hal.c b/drivers/staging/most/hdm-dim2/dim2_hal.c +index 0b9816c..231138c 100644 +--- a/drivers/staging/most/hdm-dim2/dim2_hal.c ++++ b/drivers/staging/most/hdm-dim2/dim2_hal.c +@@ -528,11 +528,11 @@ static void dim2_cleanup(void) + + /* clear status for all dma channels */ + dimcb_io_write(&g.dim2->ACSR0, 0xFFFFFFFF); +- dimcb_io_write(&g.dim2->ACSR1, 0xFFFFFFFF); ++// dimcb_io_write(&g.dim2->ACSR1, 0xFFFFFFFF); + + /* mask interrupts for all channels */ + dimcb_io_write(&g.dim2->ACMR0, 0); +- dimcb_io_write(&g.dim2->ACMR1, 0); ++// dimcb_io_write(&g.dim2->ACMR1, 0); + } + + static void dim2_initialize(bool enable_6pin, u8 mlb_clock) +@@ -548,7 +548,7 @@ static void dim2_initialize(bool enable_6pin, u8 mlb_clock) + + /* activate all HBI channels */ + dimcb_io_write(&g.dim2->HCMR0, 0xFFFFFFFF); +- dimcb_io_write(&g.dim2->HCMR1, 0xFFFFFFFF); ++// dimcb_io_write(&g.dim2->HCMR1, 0xFFFFFFFF); + + /* enable HBI */ + dimcb_io_write(&g.dim2->HCTL, bit_mask(HCTL_EN_BIT)); +@@ -778,7 +778,7 @@ static u8 init_ctrl_async(struct dim_channel *ch, u8 type, u8 is_tx, + void dim_service_mlb_int_irq(void) + { + dimcb_io_write(&g.dim2->MS0, 0); +- dimcb_io_write(&g.dim2->MS1, 0); ++// dimcb_io_write(&g.dim2->MS1, 0); + } + + u16 dim_norm_ctrl_async_buffer_size(u16 buf_size) +diff --git a/drivers/staging/most/hdm-dim2/dim2_hdm.c b/drivers/staging/most/hdm-dim2/dim2_hdm.c +index 195efff..84f56c9 100644 +--- a/drivers/staging/most/hdm-dim2/dim2_hdm.c ++++ b/drivers/staging/most/hdm-dim2/dim2_hdm.c +@@ -54,7 +54,7 @@ + * The values 0, 1, 2, 3, 4, 5, 6 represent corresponding number of frames per + * sub-buffer 1, 2, 4, 8, 16, 32, 64. + */ +-static u8 fcnt = 4; /* (1 << fcnt) frames per subbuffer */ ++static u8 fcnt = 3; /* (1 << fcnt) frames per subbuffer */ + module_param(fcnt, byte, 0); + MODULE_PARM_DESC(fcnt, "Num of frames per sub-buffer for sync channels as a power of 2"); + +diff --git a/drivers/staging/most/hdm-dim2/dim2_reg.h b/drivers/staging/most/hdm-dim2/dim2_reg.h +index 01fe499..54e9b6e 100644 +--- a/drivers/staging/most/hdm-dim2/dim2_reg.h ++++ b/drivers/staging/most/hdm-dim2/dim2_reg.h +@@ -20,28 +20,28 @@ + struct dim2_regs { + /* 0x00 */ u32 MLBC0; + /* 0x01 */ u32 rsvd0[1]; +- /* 0x02 */ u32 MLBPC0; ++ /* 0x02 */ u32 MLBPC0; /* no at R-Car3 */ + /* 0x03 */ u32 MS0; + /* 0x04 */ u32 rsvd1[1]; +- /* 0x05 */ u32 MS1; ++ /* 0x05 */ u32 MS1; /* no at R-Car3 */ + /* 0x06 */ u32 rsvd2[2]; + /* 0x08 */ u32 MSS; + /* 0x09 */ u32 MSD; + /* 0x0A */ u32 rsvd3[1]; + /* 0x0B */ u32 MIEN; + /* 0x0C */ u32 rsvd4[1]; +- /* 0x0D */ u32 MLBPC2; +- /* 0x0E */ u32 MLBPC1; ++ /* 0x0D */ u32 MLBPC2; /* no at R-Car3 */ ++ /* 0x0E */ u32 MLBPC1; /* no at R-Car3 */ + /* 0x0F */ u32 MLBC1; + /* 0x10 */ u32 rsvd5[0x10]; + /* 0x20 */ u32 HCTL; + /* 0x21 */ u32 rsvd6[1]; + /* 0x22 */ u32 HCMR0; +- /* 0x23 */ u32 HCMR1; ++ /* 0x23 */ u32 HCMR1; /* no at R-Car3 */ + /* 0x24 */ u32 HCER0; +- /* 0x25 */ u32 HCER1; ++ /* 0x25 */ u32 HCER1; /* no at R-Car3 */ + /* 0x26 */ u32 HCBR0; +- /* 0x27 */ u32 HCBR1; ++ /* 0x27 */ u32 HCBR1; /* no at R-Car3 */ + /* 0x28 */ u32 rsvd7[8]; + /* 0x30 */ u32 MDAT0; + /* 0x31 */ u32 MDAT1; +@@ -57,9 +57,9 @@ struct dim2_regs { + /* 0xF0 */ u32 ACTL; + /* 0xF1 */ u32 rsvd9[3]; + /* 0xF4 */ u32 ACSR0; +- /* 0xF5 */ u32 ACSR1; ++ /* 0xF5 */ u32 ACSR1; /* no at R-Car3 */ + /* 0xF6 */ u32 ACMR0; +- /* 0xF7 */ u32 ACMR1; ++ /* 0xF7 */ u32 ACMR1; /* no at R-Car3 */ + }; + + #define DIM2_MASK(n) (~((~(u32)0) << (n))) +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0077-MOST-dim2-add-timeouts.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0077-MOST-dim2-add-timeouts.patch new file mode 100644 index 0000000..d47c5c6 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0077-MOST-dim2-add-timeouts.patch @@ -0,0 +1,46 @@ +From f02aa2831e169a9f17eebb2784db4c95944ba927 Mon Sep 17 00:00:00 2001 +From: Andrey Gusakov +Date: Mon, 25 Sep 2017 07:13:29 +0300 +Subject: [PATCH] MOST: dim2: add timeouts + +Get rid from loop hang if device not functional + +Signed-off-by: Andrey Gusakov +Signed-off-by: Vladimir Barinov +--- + drivers/staging/most/hdm-dim2/dim2_hal.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +diff --git a/drivers/staging/most/hdm-dim2/dim2_hal.c b/drivers/staging/most/hdm-dim2/dim2_hal.c +index 231138c..ee0e307 100644 +--- a/drivers/staging/most/hdm-dim2/dim2_hal.c ++++ b/drivers/staging/most/hdm-dim2/dim2_hal.c +@@ -18,6 +18,7 @@ + #include "dim2_errors.h" + #include "dim2_reg.h" + #include ++#include + + /* + * Size factor for isochronous DBR buffer. +@@ -148,11 +149,16 @@ static void free_dbr(int offs, int size) + + static void dim2_transfer_madr(u32 val) + { ++ int timeout = 1000; + dimcb_io_write(&g.dim2->MADR, val); + + /* wait for transfer completion */ +- while ((dimcb_io_read(&g.dim2->MCTL) & 1) != 1) ++ while ((dimcb_io_read(&g.dim2->MCTL) & 1) != 1) { ++ if (--timeout == 0) ++ break; ++ udelay(1); + continue; ++ } + + dimcb_io_write(&g.dim2->MCTL, 0); /* clear transfer complete */ + } +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend index 1bb0580..c65e8ad 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend @@ -43,6 +43,9 @@ SRC_URI_append = " \ file://0041-arm64-dts-renesas-ulcb-enlarge-cma-region.patch \ file://0042-arm64-dts-renesas-r8a7795-es1-h3ulcb-disable-eMMC.patch \ file://0043-arm64-dts-renesas-ulcb-use-versaclock-for-du-rgb-and-lvds.patch \ + file://0044-pinctrl-r8a779x-add-mlb-pinmux.patch \ + file://0045-clk-r8a779x-add-mlp-clock.patch \ + file://0046-arm64-dts-renesas-r8a779x-add-mlp-nodes.patch \ ${@base_conditional("LVDSCAMERA_FIRST4_TYPE1", "1", " file://0050-arm64-dts-Gen3-view-boards-TYPE1-first-4-cameras.patch", "", d)} \ ${@base_conditional("LVDSCAMERA_SECOND4_TYPE1", "1", " file://0051-arm64-dts-Gen3-view-boards-TYPE1-second-4-cameras.patch", "", d)} \ ${@base_conditional("LVDSCAMERA_FIRST4_TYPE2", "1", " file://0052-arm64-dts-Gen3-view-boards-TYPE2-first-4-cameras.patch", "", d)} \ @@ -55,6 +58,11 @@ SRC_URI_append = " \ file://0070-clk-clk-5p49x-add-5P49V5925-chip.patch \ file://0071-ASoC-add-dummy-device-for-WL18xx-PCM-audio.patch \ file://0072-usb-hub-disable-autosuspend-for-SMSC-hubs.patch \ + file://0073-MOST-dim2-add-device-tree-support.patch \ + file://0074-MOST-dim2-add-R-Car3-related-initialization.patch \ + file://0075-MOST-core-fix-memory-allocation-at-arm64.patch \ + file://0076-MOST-dim2-Renesas-R-Car3-variant.patch \ + file://0077-MOST-dim2-add-timeouts.patch \ " SRC_URI_append_h3ulcb = " file://ulcb.cfg" -- cgit 1.2.3-korg From 8d336db9763630f5795aadf1944b2d702176f1fa Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Wed, 27 Sep 2017 04:54:04 +0300 Subject: Name wl18xx dumy pcm card as wl18xx-codec This fixes wifi since it's platform driver uses the same name asoc driver loader in kernel but wifi as a module hence wifi is rejected --- .../linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch | 2 +- .../linux-renesas/0071-ASoC-add-dummy-device-for-WL18xx-PCM-audio.patch | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch') diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch index dc4649a..3b9344d 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch @@ -15715,7 +15715,7 @@ index 0000000..4ead97a + compatible = "simple-audio-card"; + + simple-audio-card,format = "i2s"; -+ simple-audio-card,name = "wl18xx"; ++ simple-audio-card,name = "wl18xx-codec"; + + simple-audio-card,bitclock-master = <&sound_wl18xx_master>; + simple-audio-card,frame-master = <&sound_wl18xx_master>; diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0071-ASoC-add-dummy-device-for-WL18xx-PCM-audio.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0071-ASoC-add-dummy-device-for-WL18xx-PCM-audio.patch index 71be565..9ebca61 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0071-ASoC-add-dummy-device-for-WL18xx-PCM-audio.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0071-ASoC-add-dummy-device-for-WL18xx-PCM-audio.patch @@ -110,7 +110,7 @@ index 000000000000..50ebbd4c0013 + +static struct platform_driver wl18xx_driver = { + .driver = { -+ .name = "wl18xx", ++ .name = "wl18xx-codec", + .of_match_table = wl18xx_of_match, + .owner = THIS_MODULE, + }, -- cgit 1.2.3-korg From d070d7a90e38dccdbce6e7114d412e93e2c31cfb Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Wed, 27 Sep 2017 06:09:33 +0300 Subject: revert snd card name to wl18xx it isokay tohave sound card name as wl18xx since it is not platform driver name This is convenient for use already setup pulseudio config file that uses wl18xx name --- .../linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch') diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch index 3b9344d..dc4649a 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch @@ -15715,7 +15715,7 @@ index 0000000..4ead97a + compatible = "simple-audio-card"; + + simple-audio-card,format = "i2s"; -+ simple-audio-card,name = "wl18xx-codec"; ++ simple-audio-card,name = "wl18xx"; + + simple-audio-card,bitclock-master = <&sound_wl18xx_master>; + simple-audio-card,frame-master = <&sound_wl18xx_master>; -- cgit 1.2.3-korg From 2aa4c8329ed1fd3067dd2c364f9a7f50096be3a5 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Wed, 27 Sep 2017 07:28:39 +0300 Subject: FIX ssi pingroup used for PCM3168A Since 2.23 it is renamed: ssi34_ctrl -> ssi349_ctrl --- .../linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch') diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch index dc4649a..a2a23d3 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch @@ -15842,7 +15842,7 @@ index 0000000..4ead97a + }; + + sound_0_pins: sound0 { -+ groups = "ssi34_ctrl", "ssi3_data", "ssi4_data"; ++ groups = "ssi349_ctrl", "ssi3_data", "ssi4_data"; + function = "ssi"; + }; + -- cgit 1.2.3-korg From bbec61addf4e3a0ba2f0f1eb3af2bafae2c412f6 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Fri, 27 Oct 2017 21:28:49 +0300 Subject: MOST update 1) fix MOST soundcard add during setup 2) optionally add MOST to dtsi via KF_ENABLE_MOST flag in local.conf 3) optionally add SD3 to dtsi via KF_ENABLE_SD3 flag in local.conf 4) add MOST options to kernel config --- .../0040-arm64-dts-renesas-add-ADAS-boards.patch | 78 +++++++++++++--------- ...0047-arm64-dts-renesas-ulcb-kf-enable-sd3.patch | 28 ++++++++ ...048-arm64-dts-renesas-ulcb-kf-enable-most.patch | 28 ++++++++ .../0078-MOST-aim-fix-null-pointer-crash.patch | 29 ++++++++ .../recipes-kernel/linux/linux-renesas/ulcb.cfg | 8 +++ .../linux/linux-renesas_4.9.bbappend | 3 + 6 files changed, 144 insertions(+), 30 deletions(-) create mode 100644 meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0047-arm64-dts-renesas-ulcb-kf-enable-sd3.patch create mode 100644 meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0048-arm64-dts-renesas-ulcb-kf-enable-most.patch create mode 100644 meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0078-MOST-aim-fix-null-pointer-crash.patch (limited to 'meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch') diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch index a2a23d3..b15a4fb 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch @@ -47,17 +47,18 @@ Signed-off-by: Vladimir Barinov arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb.dts | 1787 ++++++++++++++++++++ .../arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts | 546 ++++++ .../boot/dts/renesas/r8a7795-salvator-x-view.dts | 552 ++++++ - arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts | 36 + + arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts | 40 + .../arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts | 287 ++++ .../boot/dts/renesas/r8a7796-salvator-x-view.dts | 318 ++++ arch/arm64/boot/dts/renesas/r8a7797-eagle.dts | 561 ++++++ arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts | 541 ++++++ arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts | 294 ++++ arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi | 518 ++++++ + arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi | 30 + arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi | 46 + - arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 1520 +++++++++++++++++ + arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 1531 +++++++++++++++++ arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi | 515 ++++++ - 35 files changed, 17240 insertions(+) + 36 files changed, 17285 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/legacy/Makefile create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts @@ -89,6 +90,7 @@ Signed-off-by: Vladimir Barinov create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi + create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi create mode 100644 arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi @@ -135,10 +137,10 @@ index 0000000..7f25079 +clean-files := *.dtb diff --git a/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts b/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts new file mode 100644 -index 0000000..cd23797 +index 0000000..ec6d86d --- /dev/null +++ b/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts -@@ -0,0 +1,1717 @@ +@@ -0,0 +1,1710 @@ +/* + * Device Tree Source for the H3ULCB Kingfisher V0 board on r8a7795 ES1.x + * @@ -1849,13 +1851,6 @@ index 0000000..cd23797 +&ssi8 { + shared-pin; +}; -+ -+/* uncomment to enable CN48 on VIN4 */ -+//#include "../ulcb-kf-rpi.dtsi" -+/* uncomment to enable CN47: SD on SDHI3 */ -+//#include "../ulcb-kf-sd3.dtsi" -+/* uncomment to override CN29 (CMOS camera) on VIN5 */ -+//#include "../ulcb-kf-cmos.dtsi" diff --git a/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts b/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts new file mode 100644 index 0000000..ac6a12b @@ -2305,7 +2300,7 @@ index 0000000..ac6a12b +}; diff --git a/arch/arm64/boot/dts/renesas/legacy/r8a7795-h3ulcb-kf-v0.dts b/arch/arm64/boot/dts/renesas/legacy/r8a7795-h3ulcb-kf-v0.dts new file mode 100644 -index 0000000..f640350 +index 0000000..78c766b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/legacy/r8a7795-h3ulcb-kf-v0.dts @@ -0,0 +1,1724 @@ @@ -4506,7 +4501,7 @@ index 0000000..14b6f52 +}; diff --git a/arch/arm64/boot/dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts b/arch/arm64/boot/dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts new file mode 100644 -index 0000000..7be2370 +index 0000000..ffa1879 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts @@ -0,0 +1,1214 @@ @@ -12853,7 +12848,7 @@ index 0000000..fb12a39f3 +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts new file mode 100644 -index 0000000..730cd2a +index 0000000..a409402 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts @@ -0,0 +1,40 @@ @@ -15452,6 +15447,42 @@ index 0000000..4ca502f + }; + }; +}; +diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi +new file mode 100644 +index 0000000..4af5ca0 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi +@@ -0,0 +1,30 @@ ++/* ++ * Device Tree Source for the H3/M3ULCB Kingfisher board: ++ * this overrides GPS in favour MOST on GP5_24/GP5_25 R-CAR pins ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++&pfc { ++ mlp_pins: mlp { ++ groups = "mlb_3pin"; ++ function = "mlb_3pin"; ++ }; ++}; ++ ++&scif1 { ++ status = "disabled"; ++}; ++ ++&mlp { ++ pinctrl-0 = <&mlp_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ clock-speed = "1024fs"; ++}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi new file mode 100644 index 0000000..b854216 @@ -15506,10 +15537,10 @@ index 0000000..b854216 +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi new file mode 100644 -index 0000000..4ead97a +index 0000000..3990648 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi -@@ -0,0 +1,1542 @@ +@@ -0,0 +1,1529 @@ +/* + * Device Tree Source for the ULCB Kingfisher board + * @@ -15887,11 +15918,6 @@ index 0000000..4ead97a + groups = "vin5_data8", "vin5_sync", "vin5_clk"; + function = "vin5"; + }; -+ -+ mlp_pins: mlp { -+ groups = "mlb_3pin"; -+ function = "mlb_3pin"; -+ }; +}; + +&du { @@ -17042,16 +17068,8 @@ index 0000000..4ead97a + pcie1v8-supply = <&mpcie_1v8>; +}; + -+&mlp { -+ pinctrl-0 = <&mlp_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; + -+ clock-speed = "1024fs"; -+}; + -+/* uncomment to enable CN47: SD on SDHI3 */ -+//#include "ulcb-kf-sd3.dtsi" diff --git a/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi b/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi new file mode 100644 index 0000000..92ed4a4 diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0047-arm64-dts-renesas-ulcb-kf-enable-sd3.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0047-arm64-dts-renesas-ulcb-kf-enable-sd3.patch new file mode 100644 index 0000000..81b3dc9 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0047-arm64-dts-renesas-ulcb-kf-enable-sd3.patch @@ -0,0 +1,28 @@ +From a5eed343caa82837c72a2c0e3d53f4db0c5944e4 Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov +Date: Fri, 27 Oct 2017 20:54:47 +0300 +Subject: [PATCH] arm64: dts: renesas: ulcb-kf: enable sd3 + +This enables SD3 on CN47 instead wifi + +Signed-off-by: Vladimir Barinov +--- + arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +index 8ffafb2..ea6cb1b 100644 +--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi ++++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +@@ -1527,3 +1527,8 @@ + + + ++/* enable CN47: SD on SDHI3 */ ++#include "ulcb-kf-sd3.dtsi" ++ ++ ++ +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0048-arm64-dts-renesas-ulcb-kf-enable-most.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0048-arm64-dts-renesas-ulcb-kf-enable-most.patch new file mode 100644 index 0000000..37ad738 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0048-arm64-dts-renesas-ulcb-kf-enable-most.patch @@ -0,0 +1,28 @@ +From ab803d3c36d8444948c7eec238c19926fd036fcc Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov +Date: Fri, 27 Oct 2017 20:58:21 +0300 +Subject: [PATCH] arm64: dts: renesas: ulcb-kf: enable most + +This enables MOST on CN22 instead GPS + +Signed-off-by: Vladimir Barinov +--- + arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +index ea6cb1b..ddd5450 100644 +--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi ++++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +@@ -1532,3 +1532,8 @@ + + + ++/* enable CN22: enable MOST and disable GPS (move R661->R660, R663->R662) */ ++#include "ulcb-kf-most.dtsi" ++ ++ ++ +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0078-MOST-aim-fix-null-pointer-crash.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0078-MOST-aim-fix-null-pointer-crash.patch new file mode 100644 index 0000000..fd66258 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0078-MOST-aim-fix-null-pointer-crash.patch @@ -0,0 +1,29 @@ +From f3c2f6f40c2b3e43a447c89b523de40ce2211e91 Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov +Date: Fri, 27 Oct 2017 17:34:05 +0300 +Subject: [PATCH] MOST: aim: fix null pointer crash + +The snd_card_new now crashes if first argument NULL + +Signed-off-by: Andrey Gusakov +Signed-off-by: Vladimir Barinov +--- + drivers/staging/most/aim-sound/sound.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/staging/most/aim-sound/sound.c b/drivers/staging/most/aim-sound/sound.c +index e4198e5..a2ccc79 100644 +--- a/drivers/staging/most/aim-sound/sound.c ++++ b/drivers/staging/most/aim-sound/sound.c +@@ -595,7 +595,7 @@ static int audio_probe_channel(struct most_interface *iface, int channel_id, + return ret; + } + +- ret = snd_card_new(NULL, -1, card_name, THIS_MODULE, ++ ret = snd_card_new(iface->dev, -1, card_name, THIS_MODULE, + sizeof(*channel), &card); + if (ret < 0) + return ret; +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/ulcb.cfg b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/ulcb.cfg index b199cde..b52636a 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/ulcb.cfg +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/ulcb.cfg @@ -70,3 +70,11 @@ CONFIG_LSM9DS0=y CONFIG_DRM_I2C_ADV7511=y CONFIG_TOUCHSCREEN_EDT_FT5X06=y CONFIG_SERIAL_SH_SCI_DMA=y +CONFIG_STAGING=y +CONFIG_MOST=y +CONFIG_MOSTCORE=y +CONFIG_AIM_CDEV=y +CONFIG_AIM_NETWORK=y +CONFIG_AIM_SOUND=y +CONFIG_AIM_V4L2=y +CONFIG_HDM_DIM2=y diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend index c65e8ad..893d43a 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend @@ -46,6 +46,8 @@ SRC_URI_append = " \ file://0044-pinctrl-r8a779x-add-mlb-pinmux.patch \ file://0045-clk-r8a779x-add-mlp-clock.patch \ file://0046-arm64-dts-renesas-r8a779x-add-mlp-nodes.patch \ + ${@base_conditional("KF_ENABLE_SD3", "1", " file://0047-arm64-dts-renesas-ulcb-kf-enable-sd3.patch", "", d)} \ + ${@base_conditional("KF_ENABLE_MOST", "1", " file://0048-arm64-dts-renesas-ulcb-kf-enable-most.patch", "", d)} \ ${@base_conditional("LVDSCAMERA_FIRST4_TYPE1", "1", " file://0050-arm64-dts-Gen3-view-boards-TYPE1-first-4-cameras.patch", "", d)} \ ${@base_conditional("LVDSCAMERA_SECOND4_TYPE1", "1", " file://0051-arm64-dts-Gen3-view-boards-TYPE1-second-4-cameras.patch", "", d)} \ ${@base_conditional("LVDSCAMERA_FIRST4_TYPE2", "1", " file://0052-arm64-dts-Gen3-view-boards-TYPE2-first-4-cameras.patch", "", d)} \ @@ -63,6 +65,7 @@ SRC_URI_append = " \ file://0075-MOST-core-fix-memory-allocation-at-arm64.patch \ file://0076-MOST-dim2-Renesas-R-Car3-variant.patch \ file://0077-MOST-dim2-add-timeouts.patch \ + file://0078-MOST-aim-fix-null-pointer-crash.patch \ " SRC_URI_append_h3ulcb = " file://ulcb.cfg" -- cgit 1.2.3-korg From 06e06e1312b81efe05481e1218c8d032f53c27f5 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Fri, 3 Nov 2017 18:50:27 +0300 Subject: R8A7797: kernel updates - add CANFD - add V3M videobox board - add CANFD to V3M KF - add eMMC to V3MSK based boards --- ...as-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch | 121 ++- .../0040-arm64-dts-renesas-add-ADAS-boards.patch | 848 +++++++++++++++++---- 2 files changed, 755 insertions(+), 214 deletions(-) (limited to 'meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch') diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch index f1a2cd6..93cf1ec 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch @@ -8,7 +8,7 @@ This adds Renesas R8A7797 SoC support Signed-off-by: Vladimir Barinov --- arch/arm64/Kconfig.platforms | 6 + - arch/arm64/boot/dts/renesas/r8a7797.dtsi | 992 ++++++++++ + arch/arm64/boot/dts/renesas/r8a7797.dtsi | 973 ++++++++++ drivers/clk/renesas/Kconfig | 1 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r8a7797-cpg-mssr.c | 218 +++ @@ -48,7 +48,7 @@ Signed-off-by: Vladimir Barinov drivers/thermal/rcar_gen3_thermal.c | 29 + include/dt-bindings/clock/r8a7797-cpg-mssr.h | 48 + include/dt-bindings/power/r8a7797-sysc.h | 32 + - 41 files changed, 4275 insertions(+), 30 deletions(-) + 41 files changed, 4256 insertions(+), 30 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/r8a7797.dtsi create mode 100644 drivers/clk/renesas/r8a7797-cpg-mssr.c create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a7797.c @@ -75,10 +75,10 @@ index 7c104ca..9380fc6 100644 help diff --git a/arch/arm64/boot/dts/renesas/r8a7797.dtsi b/arch/arm64/boot/dts/renesas/r8a7797.dtsi new file mode 100644 -index 0000000..5bd447a +index 0000000..30638e3 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7797.dtsi -@@ -0,0 +1,992 @@ +@@ -0,0 +1,973 @@ +/* + * Device Tree Source for the r8a7797 SoC + * @@ -554,20 +554,19 @@ index 0000000..5bd447a + #size-cells = <0>; + }; + -+ /* Future + canfd: canfd@e66c0000 { + compatible = "renesas,r8a7797-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , -+ ; ** SPI29:CAN-FD channel, SPI30:CAN-FD global ** ++ ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A7797_CLK_CANFD>, -+ <&can_clk>; ** RMSTPCR9/bit14:CAN-FD ** ++ <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7797_CLK_CANFD>; + assigned-clock-rates = <40000000>; -+ power-domains = <&cpg>; ++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; + status = "disabled"; + + channel0 { @@ -577,7 +576,7 @@ index 0000000..5bd447a + channel1 { + status = "disabled"; + }; -+ }; */ ++ }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7797", "renesas,pwm-rcar"; @@ -911,31 +910,13 @@ index 0000000..5bd447a + status = "disabled"; + }; + -+ + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a7797"; + reg = <0 0xee140000 0 0x2000>; -+ interrupts = ; /* SPI165:SDHI.ch0 */ -+ clocks = <&cpg CPG_MOD 314>; /* RMSTPCR3/bit14:SDIF */ -+ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; -+ renesas,clk-rate = <200000000>; -+ cap-sd-highspeed; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ renesas,mmc-scc-tapnum = <8>; -+ status = "disabled"; -+ }; -+ -+ mmc0: mmc@ee140000 { -+ compatible = "renesas,mmc-r8a7797"; -+ reg = <0 0xee140000 0 0x2000>; -+ interrupts = ; /* SPI165:SDHI.ch0 */ -+ clocks = <&cpg CPG_MOD 314>; /* RMSTPCR3/bit14:SDIF */ ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 314>; + power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; + renesas,clk-rate = <200000000>; -+ cap-mmc-highspeed; -+ mmc-hs200-1_8v; -+ renesas,mmc-scc-tapnum = <8>; + status = "disabled"; + }; + @@ -1097,7 +1078,7 @@ index 1072f76..c6f0abb 100644 obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o clk-div6.o diff --git a/drivers/clk/renesas/r8a7797-cpg-mssr.c b/drivers/clk/renesas/r8a7797-cpg-mssr.c new file mode 100644 -index 0000000..c69bf31 +index 0000000..c8e9a3f --- /dev/null +++ b/drivers/clk/renesas/r8a7797-cpg-mssr.c @@ -0,0 +1,218 @@ @@ -1320,7 +1301,7 @@ index 0000000..c69bf31 + .cpg_clk_register = rcar_gen3_cpg_clk_register, +}; diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c -index f9d1763..96de154 100644 +index 1cd2c05..b145f14 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -26,6 +26,13 @@ @@ -1337,7 +1318,7 @@ index f9d1763..96de154 100644 #define CPG_PLL0CR 0x00d8 #define CPG_PLL2CR 0x002c #define CPG_PLL4CR 0x01f4 -@@ -227,7 +234,10 @@ static unsigned long cpg_z2_clk_recalc_rate(struct clk_hw *hw, +@@ -228,7 +235,10 @@ static unsigned long cpg_z2_clk_recalc_rate(struct clk_hw *hw, unsigned int val; unsigned long rate; @@ -1349,7 +1330,7 @@ index f9d1763..96de154 100644 mult = 32 - val; rate = div_u64((u64)parent_rate * mult + 16, 32); -@@ -339,6 +349,11 @@ static int cpg_z2_clk_set_rate(struct clk_hw *hw, unsigned long rate, +@@ -372,6 +382,11 @@ static int cpg_z2_clk_set_rate(struct clk_hw *hw, unsigned long rate, u32 val, kick; unsigned int i; @@ -1361,7 +1342,7 @@ index f9d1763..96de154 100644 mult = div_u64((u64)rate * 32 + parent_rate/2, parent_rate); mult = clamp(mult, 1U, 32U); -@@ -451,6 +466,19 @@ static struct clk * __init cpg_z2_clk_register(const char *name, +@@ -566,6 +581,19 @@ static struct clk * __init cpg_zg_clk_register(const char *name, /* * SDn Clock */ @@ -1381,7 +1362,7 @@ index f9d1763..96de154 100644 #define CPG_SD_STP_HCK BIT(9) #define CPG_SD_STP_CK BIT(8) -@@ -749,6 +777,14 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, +@@ -864,6 +892,14 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, case CLK_TYPE_GEN3_SD: return cpg_sd_clk_register(core, base, __clk_get_name(parent)); @@ -1396,7 +1377,7 @@ index f9d1763..96de154 100644 case CLK_TYPE_GEN3_RINT: div = cpg_pll_config->rint; break; -@@ -799,5 +835,8 @@ int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, +@@ -917,5 +953,8 @@ int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, if (attr) cpg_quirks = (uintptr_t)attr->data; pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks); @@ -1406,7 +1387,7 @@ index f9d1763..96de154 100644 return 0; } diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h -index 4155023..f0c0a92 100644 +index 51ae7b8..694bedc 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -19,6 +19,8 @@ enum rcar_gen3_clk_types { @@ -1418,7 +1399,7 @@ index 4155023..f0c0a92 100644 CLK_TYPE_GEN3_R, CLK_TYPE_GEN3_Z, CLK_TYPE_GEN3_Z2, -@@ -26,6 +28,10 @@ enum rcar_gen3_clk_types { +@@ -29,6 +31,10 @@ enum rcar_gen3_clk_types { #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) @@ -1471,7 +1452,7 @@ index 29f76a4..809a6e1 100644 { .compatible = "rockchip,rk2928", }, diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c -index f721a89..118e579 100644 +index 7685d31..02e42ba 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -1,7 +1,7 @@ @@ -1483,7 +1464,7 @@ index f721a89..118e579 100644 * Copyright (C) 2013 Magnus Damm * * This program is free software; you can redistribute it and/or modify -@@ -579,6 +579,10 @@ struct gpio_rcar_info { +@@ -363,6 +363,10 @@ struct gpio_rcar_info { /* Gen3 GPIO is identical to Gen2. */ .data = &gpio_rcar_info_gen2, }, { @@ -1495,7 +1476,7 @@ index f721a89..118e579 100644 .data = &gpio_rcar_info_gen1, }, { diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c -index 6295c73..ac9cf2a 100644 +index eb088cb..62612cd 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c @@ -289,6 +289,30 @@ @@ -1538,7 +1519,7 @@ index 6295c73..ac9cf2a 100644 }; diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c -index c15611c..95023bd 100644 +index ccf5159..4c9e008 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c @@ -29,11 +29,17 @@ @@ -1573,7 +1554,7 @@ index c15611c..95023bd 100644 } diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c -index ecae864..42eb45c 100644 +index ecae864..d5fa06c 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c @@ -17,12 +17,18 @@ @@ -1676,7 +1657,7 @@ index 73ff520..306ba97 100644 }; MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c -index 2b380ff..b9ef21a 100644 +index 4cf30c8..3fdd96e 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -1,7 +1,7 @@ @@ -1698,7 +1679,7 @@ index 2b380ff..b9ef21a 100644 /* Terminator */ }, }; -@@ -1640,6 +1643,8 @@ static int __init ipmmu_vmsa_iommu_of_setup(struct device_node *np) +@@ -1643,6 +1646,8 @@ static int __init ipmmu_vmsa_iommu_of_setup(struct device_node *np) ipmmu_vmsa_iommu_of_setup); IOMMU_OF_DECLARE(ipmmu_r8a7796_iommu_of, "renesas,ipmmu-r8a7796", ipmmu_vmsa_iommu_of_setup); @@ -1721,7 +1702,7 @@ index 17178ad..5539c5d 100644 This is a v4l2 driver for the R-Car CSI-2 Interface diff --git a/drivers/media/platform/soc_camera/rcar_csi2.c b/drivers/media/platform/soc_camera/rcar_csi2.c -index 05f623468..5faac64 100644 +index 05f623468..4d95da6 100644 --- a/drivers/media/platform/soc_camera/rcar_csi2.c +++ b/drivers/media/platform/soc_camera/rcar_csi2.c @@ -25,6 +25,7 @@ @@ -2008,10 +1989,10 @@ index 400958b..74fb005 100644 for (i = 0; i < num; i++) { diff --git a/drivers/media/platform/vsp1/vsp1_drv.c b/drivers/media/platform/vsp1/vsp1_drv.c -index 45bd0f3..90f7109 100644 +index 57b1b81..2f711bb 100644 --- a/drivers/media/platform/vsp1/vsp1_drv.c +++ b/drivers/media/platform/vsp1/vsp1_drv.c -@@ -888,6 +888,15 @@ void vsp1_device_put(struct vsp1_device *vsp1) +@@ -893,6 +893,15 @@ void vsp1_device_put(struct vsp1_device *vsp1) .wpf_count = 2, .num_bru_inputs = 5, .header_mode = true, @@ -2072,10 +2053,10 @@ index b442d14..e79f9e6 100644 static const struct vsp1_entity_operations lif_entity_ops = { diff --git a/drivers/media/platform/vsp1/vsp1_regs.h b/drivers/media/platform/vsp1/vsp1_regs.h -index 885f60b..2d863a7 100644 +index fb6d56c..bcba968 100644 --- a/drivers/media/platform/vsp1/vsp1_regs.h +++ b/drivers/media/platform/vsp1/vsp1_regs.h -@@ -788,6 +788,12 @@ +@@ -789,6 +789,12 @@ #define VI6_LIF_CSBTH_LBTH_MASK (0x7ff << 0) #define VI6_LIF_CSBTH_LBTH_SHIFT 0 @@ -2088,7 +2069,7 @@ index 885f60b..2d863a7 100644 /* ----------------------------------------------------------------------------- * Security Control Registers */ -@@ -811,6 +817,7 @@ +@@ -812,6 +818,7 @@ #define VI6_IP_VERSION_MODEL_VSPBD_GEN3 (0x15 << 8) #define VI6_IP_VERSION_MODEL_VSPBC_GEN3 (0x16 << 8) #define VI6_IP_VERSION_MODEL_VSPD_GEN3 (0x17 << 8) @@ -2097,10 +2078,10 @@ index 885f60b..2d863a7 100644 #define VI6_IP_VERSION_SOC_MASK (0xff << 0) #define VI6_IP_VERSION_SOC_H (0x01 << 0) diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c -index 136ebac..fe4e022 100644 +index 359a981..49276282 100644 --- a/drivers/mmc/host/sh_mobile_sdhi.c +++ b/drivers/mmc/host/sh_mobile_sdhi.c -@@ -150,6 +150,8 @@ struct sh_mobile_sdhi_of_data { +@@ -138,6 +138,8 @@ struct sh_mobile_sdhi_of_data { { .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, }, { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, }, { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, }, @@ -2110,10 +2091,10 @@ index 136ebac..fe4e022 100644 }; MODULE_DEVICE_TABLE(of, sh_mobile_sdhi_of_match); diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c -index 6c65426..97c52dd 100644 +index 68019d9..cd4f25a 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c -@@ -1922,6 +1922,7 @@ static int ravb_mdio_release(struct ravb_private *priv) +@@ -1906,6 +1906,7 @@ static int ravb_mdio_release(struct ravb_private *priv) { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 }, { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, { .compatible = "renesas,etheravb-r8a7796", .data = (void *)RCAR_GEN3 }, @@ -2150,7 +2131,7 @@ index 8e08684..10adc18 100644 obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c -index 6399eb1..9bb3665 100644 +index 7ea6c8e..b536aeb 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -5,6 +5,7 @@ @@ -2161,7 +2142,7 @@ index 6399eb1..9bb3665 100644 * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive -@@ -622,6 +623,12 @@ static int sh_pfc_init_ranges(struct sh_pfc *pfc) +@@ -539,6 +540,12 @@ static int sh_pfc_init_ranges(struct sh_pfc *pfc) .data = &r8a7796_pinmux_info, }, #endif @@ -2176,7 +2157,7 @@ index 6399eb1..9bb3665 100644 .compatible = "renesas,pfc-sh73a0", diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7797.c b/drivers/pinctrl/sh-pfc/pfc-r8a7797.c new file mode 100644 -index 0000000..d58ccb3 +index 0000000..9b6127f --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7797.c @@ -0,0 +1,2586 @@ @@ -3794,7 +3775,7 @@ index 0000000..d58ccb3 +}; +static const unsigned int mmc_ctrl_pins[] = { + /* CLK, CMD */ -+ RCAR_GP_PIN(3,10), RCAR_GP_PIN(3, 5), ++ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5), +}; +static const unsigned int mmc_ctrl_mux[] = { + MMC_CLK_MARK, MMC_CMD_MARK, @@ -4767,10 +4748,10 @@ index 0000000..d58ccb3 + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h -index c6a1855..a673a00 100644 +index 93cce90..0da3ee4 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h -@@ -269,6 +269,7 @@ struct sh_pfc_soc_info { +@@ -287,6 +287,7 @@ struct sh_pfc_soc_info { extern const struct sh_pfc_soc_info r8a7795_pinmux_info; extern const struct sh_pfc_soc_info r8a7795_es1_pinmux_info; extern const struct sh_pfc_soc_info r8a7796_pinmux_info; @@ -4778,7 +4759,7 @@ index c6a1855..a673a00 100644 extern const struct sh_pfc_soc_info sh7203_pinmux_info; extern const struct sh_pfc_soc_info sh7264_pinmux_info; extern const struct sh_pfc_soc_info sh7269_pinmux_info; -@@ -374,6 +375,11 @@ struct sh_pfc_soc_info { +@@ -392,6 +393,11 @@ struct sh_pfc_soc_info { PORT_GP_CFG_1(bank, 3, fn, sfx, cfg) #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) @@ -4790,7 +4771,7 @@ index c6a1855..a673a00 100644 #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ PORT_GP_CFG_4(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \ -@@ -420,6 +426,12 @@ struct sh_pfc_soc_info { +@@ -438,6 +444,12 @@ struct sh_pfc_soc_info { PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0) @@ -4888,10 +4869,10 @@ index a6d1c26..2e87293 100644 }; diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c -index 042500a..e6165b6 100644 +index 072f94c..7e59c72 100644 --- a/drivers/soc/renesas/rcar-sysc.c +++ b/drivers/soc/renesas/rcar-sysc.c -@@ -320,6 +320,9 @@ static void __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd) +@@ -321,6 +321,9 @@ static void __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd) #ifdef CONFIG_ARCH_R8A7796 { .compatible = "renesas,r8a7796-sysc", .data = &r8a7796_sysc_info }, #endif @@ -4902,10 +4883,10 @@ index 042500a..e6165b6 100644 }; diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h -index f6e842e..e7980d5 100644 +index cd8bc52..e367715 100644 --- a/drivers/soc/renesas/rcar-sysc.h +++ b/drivers/soc/renesas/rcar-sysc.h -@@ -59,4 +59,5 @@ struct rcar_sysc_info { +@@ -60,4 +60,5 @@ struct rcar_sysc_info { extern const struct rcar_sysc_info r8a7794_sysc_info; extern const struct rcar_sysc_info r8a7795_sysc_info; extern const struct rcar_sysc_info r8a7796_sysc_info; @@ -4993,10 +4974,10 @@ index 996869e..3281dc7 100644 }; MODULE_DEVICE_TABLE(of, sh_msiof_match); diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c -index 39763c7..07b1a2e 100644 +index 6700dda..a9f4d96 100644 --- a/drivers/thermal/rcar_gen3_thermal.c +++ b/drivers/thermal/rcar_gen3_thermal.c -@@ -385,6 +385,30 @@ static int rcar_gen3_r8a7795_thermal_init(struct rcar_thermal_priv *priv) +@@ -391,6 +391,30 @@ static int rcar_gen3_r8a7795_thermal_init(struct rcar_thermal_priv *priv) return 0; } @@ -5027,7 +5008,7 @@ index 39763c7..07b1a2e 100644 /* * Interrupt */ -@@ -466,9 +490,14 @@ static int rcar_gen3_thermal_remove(struct platform_device *pdev) +@@ -472,9 +496,14 @@ static int rcar_gen3_thermal_remove(struct platform_device *pdev) .thermal_init = rcar_gen3_r8a7796_thermal_init, }; diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch index b15a4fb..7b34dce 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch @@ -19,12 +19,13 @@ Videobox board on R8A7795 SoC Eagle board on R8A7797 SoC V3MSK board on R8A7797 SoC Kingfisher board on R8A7797 SoC +Videobox board on R8A7797 SoC Signed-off-by: Vladimir Barinov --- - arch/arm64/boot/dts/renesas/Makefile | 16 + + arch/arm64/boot/dts/renesas/Makefile | 17 + arch/arm64/boot/dts/renesas/legacy/Makefile | 8 + - .../renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts | 1717 +++++++++++++++++++ + .../renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts | 1710 +++++++++++++++++++ .../renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts | 441 +++++ .../dts/renesas/legacy/r8a7795-h3ulcb-kf-v0.dts | 1724 +++++++++++++++++++ .../dts/renesas/legacy/r8a7795-h3ulcb-kf-v1.dts | 465 +++++ @@ -51,14 +52,15 @@ Signed-off-by: Vladimir Barinov .../arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts | 287 ++++ .../boot/dts/renesas/r8a7796-salvator-x-view.dts | 318 ++++ arch/arm64/boot/dts/renesas/r8a7797-eagle.dts | 561 ++++++ - arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts | 541 ++++++ - arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts | 294 ++++ + arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts | 567 +++++++ + arch/arm64/boot/dts/renesas/r8a7797-v3msk-vb.dts | 498 ++++++ + arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts | 320 ++++ arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi | 518 ++++++ arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi | 30 + arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi | 46 + - arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 1531 +++++++++++++++++ + arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 1529 +++++++++++++++++ arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi | 515 ++++++ - 36 files changed, 17285 insertions(+) + 37 files changed, 17827 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/legacy/Makefile create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts @@ -88,6 +90,7 @@ Signed-off-by: Vladimir Barinov create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-eagle.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk-vb.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi @@ -96,10 +99,10 @@ Signed-off-by: Vladimir Barinov create mode 100644 arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile -index 32fb4d9..fd17456 100644 +index 32fb4d9..52d783b 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile -@@ -4,5 +4,21 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb +@@ -4,5 +4,22 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb @@ -115,6 +118,7 @@ index 32fb4d9..fd17456 100644 +dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-eagle.dtb +dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk.dtb +dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk-kf.dtb ++dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk-vb.dtb + +# ADAS legacy boards +subdir-y := legacy @@ -137,7 +141,7 @@ index 0000000..7f25079 +clean-files := *.dtb diff --git a/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts b/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts new file mode 100644 -index 0000000..ec6d86d +index 0000000..2fee788 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts @@ -0,0 +1,1710 @@ @@ -14078,10 +14082,10 @@ index 0000000..f71addf + diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts new file mode 100644 -index 0000000..9837e17 +index 0000000..4467ab3 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts -@@ -0,0 +1,541 @@ +@@ -0,0 +1,567 @@ +/* + * Device Tree Source for the V3MSK Kingfisher board on r8a7797 + * @@ -14099,6 +14103,54 @@ index 0000000..9837e17 + model = "Renesas V3MSK Kingfisher board based on r8a7797"; +}; + ++&canfd { ++ pinctrl-0 = <&canfd0_pins &canfd1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ channel0 { ++ status = "okay"; ++ }; ++ ++ channel1 { ++ status = "okay"; ++ }; ++}; ++ ++&csi2_40 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ +&i2c0 { + /* i2c0 might conflict with pc9548 reset pin on Kingfisher (uncomment if h/w not patched) */ +// status = "disabled"; @@ -14460,6 +14512,18 @@ index 0000000..9837e17 + }; +}; + ++&pfc { ++ canfd0_pins: canfd0 { ++ groups = "canfd0_data_a"; ++ function = "canfd0"; ++ }; ++ ++ canfd1_pins: canfd1 { ++ groups = "canfd1_data"; ++ function = "canfd1"; ++ }; ++}; ++ +&vin0 { + status = "okay"; + @@ -14589,6 +14653,45 @@ index 0000000..9837e17 + }; + }; +}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vb.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vb.dts +new file mode 100644 +index 0000000..edc41ad +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vb.dts +@@ -0,0 +1,498 @@ ++/* ++ * Device Tree Source for the V3MSK Videobox board on r8a7797 ++ * ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7797-v3msk.dts" ++ ++/ { ++ model = "Renesas V3MSK Videobox board based on r8a7797"; ++ ++ aliases { ++ serial1 = &scif3; ++ }; ++}; ++ ++&canfd { ++ pinctrl-0 = <&canfd0_pins &canfd1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ channel0 { ++ status = "okay"; ++ }; ++ ++ channel1 { ++ status = "okay"; ++ }; ++}; + +&csi2_40 { + status = "okay"; @@ -14623,140 +14726,572 @@ index 0000000..9837e17 + }; + }; +}; -diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts -new file mode 100644 -index 0000000..61f7e8b ---- /dev/null -+++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts -@@ -0,0 +1,294 @@ -+/* -+ * Device Tree Source for the V3M Starter Kit board on r8a7797 -+ * -+ * Copyright (C) 2017 Renesas Electronics Corp. -+ * Copyright (C) 2017 Cogent Embedded, Inc. -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ -+ -+/dts-v1/; -+#include "r8a7797.dtsi" -+#include -+ -+/ { -+ model = "Renesas V3M Starter Kit board based on r8a7797"; -+ compatible = "renesas,v3msk", "renesas,r8a7797"; -+ -+ aliases { -+ serial0 = &scif0; -+ ethernet0 = &avb; -+ }; -+ -+ chosen { -+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory@48000000 { -+ device_type = "memory"; -+ /* first 128MB is reserved for secure area. */ -+ reg = <0x0 0x48000000 0x0 0x38000000>; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* device specific region for Lossy Decompression */ -+ lossy_decompress: linux,lossy_decompress { -+ no-map; -+ reg = <0x00000000 0x64000000 0x0 0x03000000>; -+ }; -+ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ reg = <0x00000000 0x67000000 0x0 0x09000000>; -+ linux,cma-default; -+ }; -+ -+ /* device specific region for contiguous allocations */ -+ linux,multimedia { -+ compatible = "shared-dma-pool"; -+ reusable; -+ reg = <0x00000000 0x70000000 0x0 0x10000000>; -+ }; -+ }; -+ -+ mmngr { -+ compatible = "renesas,mmngr"; -+ memory-region = <&lossy_decompress>; -+ }; + -+ mmngrbuf { -+ compatible = "renesas,mmngrbuf"; -+ }; ++&i2c1 { ++ pinctrl-0 = <&i2c1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; + -+ vspm_if { -+ compatible = "renesas,vspm_if"; -+ }; ++ clock-frequency = <400000>; + -+ lvds-encoder { -+ compatible = "thine,thc63lvdm83d"; ++ i2cswitch1: i2c-switch@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x74>; ++ reset-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + -+ ports { ++ i2c@0 { + #address-cells = <1>; + #size-cells = <0>; ++ reg = <0>; + -+ port@0 { -+ reg = <0>; -+ lvds_enc_in: endpoint { -+ remote-endpoint = <&du_out_lvds0>; ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; + }; -+ }; -+ port@1 { -+ reg = <1>; -+ lvds_enc_out: endpoint { -+ remote-endpoint = <&lvds_in>; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ ov106xx_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; + }; + }; -+ }; -+ }; + -+ lvds { -+ compatible = "lvds-connector"; -+ -+ width-mm = <210>; -+ height-mm = <158>; -+ -+ panel-timing { -+ clock-frequency = <133000000>; -+ hactive = <1024>; -+ vactive = <768>; -+ hsync-len = <136>; -+ hfront-porch = <20>; -+ hback-porch = <160>; -+ vfront-porch = <3>; -+ vback-porch = <29>; -+ vsync-len = <6>; -+ }; ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; + -+ port { -+ lvds_in: endpoint { -+ remote-endpoint = <&lvds_enc_out>; ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ ov106xx_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ }; + }; -+ }; -+ }; + -+ hdmi-out { -+ compatible = "hdmi-connector"; -+ type = "a"; ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; + -+ port { -+ hdmi_con: endpoint { ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ ov106xx_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ ov106xx_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ ti964-ti9x3@0 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti964_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti964_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ ti964_des0ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ ti964_des0ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ ti964_csi0ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ ++ gpio_exp_6c: gpio@6c { ++ compatible = "maxim,max7325"; ++ reg = <0x6c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ virq { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video VIRQ"; ++ }; ++ des_cfg { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video CNFG0"; ++ }; ++ pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video PWR_SHDN"; ++ }; ++ cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video PWR0"; ++ }; ++ cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video PWR1"; ++ }; ++ cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video PWR2"; ++ }; ++ cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video PWR3"; ++ }; ++ des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video DES_SHDN"; ++ }; ++ fpdl_shdn { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video FPDL_SHDN"; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&gpio0 { ++ can0stby { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "CAN0STBY"; ++ }; ++ ++ can1_load { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can1_120R_load"; ++ }; ++}; ++ ++&gpio2 { ++ can0_load { ++ gpio-hog; ++ gpios = <16 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can0_120R_load"; ++ }; ++}; ++ ++&pfc { ++ canfd0_pins: canfd0 { ++ groups = "canfd0_data_a"; ++ function = "canfd0"; ++ }; ++ ++ canfd1_pins: canfd1 { ++ groups = "canfd1_data"; ++ function = "canfd1"; ++ }; ++ ++ i2c1_pins: i2c1 { ++ groups = "i2c1"; ++ function = "i2c1"; ++ }; ++ ++ scif3_pins: scif3 { ++ groups = "scif3_data"; ++ function = "scif3"; ++ }; ++}; ++ ++&scif3 { ++ pinctrl-0 = <&scif3_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&vin0 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ vin0_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ vin1_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin2 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ vin2_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin3 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ vin3_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts +new file mode 100644 +index 0000000..fb2976e +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts +@@ -0,0 +1,320 @@ ++/* ++ * Device Tree Source for the V3M Starter Kit board on r8a7797 ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++#include "r8a7797.dtsi" ++#include ++ ++/ { ++ model = "Renesas V3M Starter Kit board based on r8a7797"; ++ compatible = "renesas,v3msk", "renesas,r8a7797"; ++ ++ aliases { ++ serial0 = &scif0; ++ ethernet0 = &avb; ++ }; ++ ++ chosen { ++ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@48000000 { ++ device_type = "memory"; ++ /* first 128MB is reserved for secure area. */ ++ reg = <0x0 0x48000000 0x0 0x38000000>; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ /* device specific region for Lossy Decompression */ ++ lossy_decompress: linux,lossy_decompress { ++ no-map; ++ reg = <0x00000000 0x64000000 0x0 0x03000000>; ++ }; ++ ++ /* global autoconfigured region for contiguous allocations */ ++ linux,cma { ++ compatible = "shared-dma-pool"; ++ reusable; ++ reg = <0x00000000 0x67000000 0x0 0x09000000>; ++ linux,cma-default; ++ }; ++ ++ /* device specific region for contiguous allocations */ ++ linux,multimedia { ++ compatible = "shared-dma-pool"; ++ reusable; ++ reg = <0x00000000 0x70000000 0x0 0x10000000>; ++ }; ++ }; ++ ++ mmngr { ++ compatible = "renesas,mmngr"; ++ memory-region = <&lossy_decompress>; ++ }; ++ ++ mmngrbuf { ++ compatible = "renesas,mmngrbuf"; ++ }; ++ ++ vspm_if { ++ compatible = "renesas,vspm_if"; ++ }; ++ ++ lvds-encoder { ++ compatible = "thine,thc63lvdm83d"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ lvds_enc_in: endpoint { ++ remote-endpoint = <&du_out_lvds0>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ lvds_enc_out: endpoint { ++ remote-endpoint = <&lvds_in>; ++ }; ++ }; ++ }; ++ }; ++ ++ lvds { ++ compatible = "lvds-connector"; ++ ++ width-mm = <210>; ++ height-mm = <158>; ++ ++ panel-timing { ++ /* 1280x800 @60Hz */ ++ clock-frequency = <65000000>; ++ hactive = <1280>; ++ vactive = <800>; ++ hsync-len = <40>; ++ hfront-porch = <80>; ++ hback-porch = <40>; ++ vfront-porch = <14>; ++ vback-porch = <14>; ++ vsync-len = <4>; ++ }; ++ ++ port { ++ lvds_in: endpoint { ++ remote-endpoint = <&lvds_enc_out>; ++ }; ++ }; ++ }; ++ ++ hdmi-out { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; @@ -14773,6 +15308,24 @@ index 0000000..61f7e8b + #clock-cells = <0>; + clock-frequency = <66666666>; + }; ++ ++ vcc_3v3: regulator0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-VCC3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ vcc_vddq_vin0: regulator1 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC-VDDQ-VIN0"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; +}; + +&du { @@ -14816,11 +15369,6 @@ index 0000000..61f7e8b + function = "i2c0"; + }; + -+ i2c3_pins: i2c3 { -+ groups = "i2c3"; -+ function = "i2c3"; -+ }; -+ + avb_pins: avb { + groups = "avb0_mdc"; + function = "avb0"; @@ -14830,6 +15378,12 @@ index 0000000..61f7e8b + groups = "du_rgb666", "du_sync", "du_clk_out_0", "du_disp"; + function = "du"; + }; ++ ++ sdhi2_pins_3v3: sdhi2_3v3 { ++ groups = "mmc_data8", "mmc_ctrl"; ++ function = "mmc"; ++ power-source = <3300>; ++ }; +}; + +&scif0 { @@ -14884,14 +15438,6 @@ index 0000000..61f7e8b + }; +}; + -+&i2c3 { -+ pinctrl-0 = <&i2c3_pins>; -+ pinctrl-names = "default"; -+ -+ status = "okay"; -+ clock-frequency = <400000>; -+}; -+ +&wdt0 { + status = "okay"; +}; @@ -14923,6 +15469,20 @@ index 0000000..61f7e8b + max-speed = <1000>; + }; +}; ++ ++&sdhi2 { ++ /* used for on-board eMMC */ ++ pinctrl-0 = <&sdhi2_pins_3v3>; ++ pinctrl-names = "default"; ++ ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_vddq_vin0>; ++ no-1-8-v; ++ cap-mmc-highspeed; ++ bus-width = <8>; ++ non-removable; ++ status = "okay"; ++}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi new file mode 100644 index 0000000..4ca502f @@ -15537,7 +16097,7 @@ index 0000000..b854216 +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi new file mode 100644 -index 0000000..3990648 +index 0000000..8ffafb2 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -0,0 +1,1529 @@ -- cgit 1.2.3-korg From 22c341549d9f342233ad581390d5c216f4d22a03 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Sun, 5 Nov 2017 18:39:23 +0300 Subject: V3MSK boards update - remove CANFD0 since conflicts with HDMI on pinmux - enable i2c3 on kf - deploy v3msk-vb --- .../0040-arm64-dts-renesas-add-ADAS-boards.patch | 21 ++++++++++++++++----- .../recipes-kernel/linux/linux-renesas_4.9.bbappend | 1 + 2 files changed, 17 insertions(+), 5 deletions(-) (limited to 'meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch') diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch index 7b34dce..1c45cd1 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch @@ -14085,7 +14085,7 @@ new file mode 100644 index 0000000..4467ab3 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts -@@ -0,0 +1,567 @@ +@@ -0,0 +1,578 @@ +/* + * Device Tree Source for the V3MSK Kingfisher board on r8a7797 + * @@ -14104,12 +14104,12 @@ index 0000000..4467ab3 +}; + +&canfd { -+ pinctrl-0 = <&canfd0_pins &canfd1_pins>; ++ pinctrl-0 = ; + pinctrl-names = "default"; + status = "okay"; + + channel0 { -+ status = "okay"; ++ status = "disabled"; + }; + + channel1 { @@ -14157,6 +14157,12 @@ index 0000000..4467ab3 +}; + +&i2c3 { ++ pinctrl-0 = <&i2c3_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ clock-frequency = <400000>; ++ + i2cswitch4: pca9548@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; @@ -14522,6 +14528,11 @@ index 0000000..4467ab3 + groups = "canfd1_data"; + function = "canfd1"; + }; ++ ++ i2c3_pins: i2c3 { ++ groups = "i2c3"; ++ function = "i2c3"; ++ }; +}; + +&vin0 { @@ -14680,12 +14691,12 @@ index 0000000..edc41ad +}; + +&canfd { -+ pinctrl-0 = <&canfd0_pins &canfd1_pins>; ++ pinctrl-0 = ; + pinctrl-names = "default"; + status = "okay"; + + channel0 { -+ status = "okay"; ++ status = "disabled"; + }; + + channel1 { diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend index 893d43a..01446c4 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend @@ -105,4 +105,5 @@ KERNEL_DEVICETREE_append_eagle = " \ KERNEL_DEVICETREE_append_v3msk = " \ renesas/r8a7797-v3msk.dtb \ renesas/r8a7797-v3msk-kf.dtb \ + renesas/r8a7797-v3msk-vb.dtb \ " -- cgit 1.2.3-korg From cb475ff40f872a197d257e95acf7e1c90f8f428c Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Tue, 7 Nov 2017 20:24:31 +0300 Subject: Fix pinmux conflict on V3MSK CANFD0/1 are enabled both now --- .../0040-arm64-dts-renesas-add-ADAS-boards.patch | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch') diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch index 1c45cd1..75bf843 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch @@ -52,7 +52,7 @@ Signed-off-by: Vladimir Barinov .../arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts | 287 ++++ .../boot/dts/renesas/r8a7796-salvator-x-view.dts | 318 ++++ arch/arm64/boot/dts/renesas/r8a7797-eagle.dts | 561 ++++++ - arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts | 567 +++++++ + arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts | 578 +++++++ arch/arm64/boot/dts/renesas/r8a7797-v3msk-vb.dts | 498 ++++++ arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts | 320 ++++ arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi | 518 ++++++ @@ -60,7 +60,7 @@ Signed-off-by: Vladimir Barinov arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi | 46 + arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 1529 +++++++++++++++++ arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi | 515 ++++++ - 37 files changed, 17827 insertions(+) + 37 files changed, 17838 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/legacy/Makefile create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts @@ -14082,7 +14082,7 @@ index 0000000..f71addf + diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts new file mode 100644 -index 0000000..4467ab3 +index 0000000..979cebe --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts @@ -0,0 +1,578 @@ @@ -14104,12 +14104,12 @@ index 0000000..4467ab3 +}; + +&canfd { -+ pinctrl-0 = ; ++ pinctrl-0 = <&canfd0_pins &canfd1_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { -+ status = "disabled"; ++ status = "okay"; + }; + + channel1 { @@ -14666,7 +14666,7 @@ index 0000000..4467ab3 +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vb.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vb.dts new file mode 100644 -index 0000000..edc41ad +index 0000000..1b531d8 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vb.dts @@ -0,0 +1,498 @@ @@ -14691,12 +14691,12 @@ index 0000000..edc41ad +}; + +&canfd { -+ pinctrl-0 = ; ++ pinctrl-0 = <&canfd0_pins &canfd1_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { -+ status = "disabled"; ++ status = "okay"; + }; + + channel1 { @@ -14743,7 +14743,7 @@ index 0000000..edc41ad + pinctrl-names = "default"; + status = "okay"; + -+ clock-frequency = <400000>; ++ clock-frequency = <100000>; + + i2cswitch1: i2c-switch@74 { + compatible = "nxp,pca9548"; @@ -15170,7 +15170,7 @@ index 0000000..edc41ad +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts new file mode 100644 -index 0000000..fb2976e +index 0000000..bf2501e --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts @@ -0,0 +1,320 @@ @@ -15386,7 +15386,7 @@ index 0000000..fb2976e + }; + + du_pins: du { -+ groups = "du_rgb666", "du_sync", "du_clk_out_0", "du_disp"; ++ groups = "du_rgb666", "du_sync", "du_clk_out_0"; + function = "du"; + }; + -- cgit 1.2.3-korg From f9e026dbff6e2d5ef11273cf6440bc60b49f95c2 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Thu, 9 Nov 2017 10:33:26 +0300 Subject: Videobox Mini support 1) V3MSK VideoBox Mini support 2) H3ULCB (es1.x, es2.0) Videobox Mini support 3) Optimize Videobox dts files --- .../0040-arm64-dts-renesas-add-ADAS-boards.patch | 15611 +++++++++---------- .../linux/linux-renesas_4.9.bbappend | 4 +- 2 files changed, 7275 insertions(+), 8340 deletions(-) (limited to 'meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch') diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch index 75bf843..14a7b80 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch @@ -14,23 +14,25 @@ H3ULCB.HAD board on R8A7795 SoC Kingfisher board on R8A7795 ES1.x SoC Kingfisher board on R8A7795 SoC Kingfisher board on R8A7796 SoC +Kingfisher board on R8A7797 SoC Videobox board on R8A7795 ES1.x SoC Videobox board on R8A7795 SoC Eagle board on R8A7797 SoC V3MSK board on R8A7797 SoC -Kingfisher board on R8A7797 SoC -Videobox board on R8A7797 SoC +Videobox Mini board on R8A7795 ES1.x SoC +Videobox Mini board on R8A7795 SoC +Videobox Mini board on R8A7797 SoC Signed-off-by: Vladimir Barinov --- - arch/arm64/boot/dts/renesas/Makefile | 17 + + arch/arm64/boot/dts/renesas/Makefile | 18 + arch/arm64/boot/dts/renesas/legacy/Makefile | 8 + .../renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts | 1710 +++++++++++++++++++ .../renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts | 441 +++++ .../dts/renesas/legacy/r8a7795-h3ulcb-kf-v0.dts | 1724 +++++++++++++++++++ - .../dts/renesas/legacy/r8a7795-h3ulcb-kf-v1.dts | 465 +++++ - .../dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts | 1214 +++++++++++++ - .../dts/renesas/legacy/r8a7796-m3ulcb-kf-v1.dts | 465 +++++ + .../dts/renesas/legacy/r8a7795-h3ulcb-kf-v1.dts | 465 ++++++ + .../dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts | 1214 ++++++++++++++ + .../dts/renesas/legacy/r8a7796-m3ulcb-kf-v1.dts | 465 ++++++ .../dts/renesas/legacy/r8a7797-v3msk-kf-v0.dts | 20 + .../boot/dts/renesas/legacy/ulcb-kf-cmos.dtsi | 75 + .../arm64/boot/dts/renesas/legacy/ulcb-kf-rpi.dtsi | 77 + @@ -38,29 +40,33 @@ Signed-off-by: Vladimir Barinov .../dts/renesas/r8a7795-es1-h3ulcb-had-beta.dts | 23 + .../boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi | 225 +++ .../boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts | 39 + - .../boot/dts/renesas/r8a7795-es1-h3ulcb-vb.dts | 1787 ++++++++++++++++++++ - .../boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts | 546 ++++++ - .../dts/renesas/r8a7795-es1-salvator-x-view.dts | 552 ++++++ + .../boot/dts/renesas/r8a7795-es1-h3ulcb-vb.dts | 69 + + .../boot/dts/renesas/r8a7795-es1-h3ulcb-vbm.dts | 26 + + .../boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts | 546 +++++++ + .../dts/renesas/r8a7795-es1-salvator-x-view.dts | 552 +++++++ .../boot/dts/renesas/r8a7795-h3ulcb-had-alfa.dts | 22 + .../boot/dts/renesas/r8a7795-h3ulcb-had-beta.dts | 23 + .../arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi | 219 +++ arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts | 39 + - arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb.dts | 1787 ++++++++++++++++++++ - .../arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts | 546 ++++++ - .../boot/dts/renesas/r8a7795-salvator-x-view.dts | 552 ++++++ + arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb.dts | 68 + + arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vbm.dts | 26 + + .../arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts | 546 +++++++ + .../boot/dts/renesas/r8a7795-salvator-x-view.dts | 552 +++++++ arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts | 40 + .../arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts | 287 ++++ .../boot/dts/renesas/r8a7796-salvator-x-view.dts | 318 ++++ - arch/arm64/boot/dts/renesas/r8a7797-eagle.dts | 561 ++++++ + arch/arm64/boot/dts/renesas/r8a7797-eagle.dts | 561 +++++++ arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts | 578 +++++++ - arch/arm64/boot/dts/renesas/r8a7797-v3msk-vb.dts | 498 ++++++ + arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts | 498 ++++++ arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts | 320 ++++ arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi | 518 ++++++ arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi | 30 + arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi | 46 + arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 1529 +++++++++++++++++ arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi | 515 ++++++ - 37 files changed, 17838 insertions(+) + arch/arm64/boot/dts/renesas/ulcb-vb.dtsi | 1726 ++++++++++++++++++++ + arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi | 557 +++++++ + 41 files changed, 16737 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/legacy/Makefile create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts @@ -76,6 +82,7 @@ Signed-off-by: Vladimir Barinov create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vb.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vbm.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x-view.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-alfa.dts @@ -83,6 +90,7 @@ Signed-off-by: Vladimir Barinov create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vbm.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-salvator-x-view.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts @@ -90,19 +98,21 @@ Signed-off-by: Vladimir Barinov create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-eagle.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts - create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk-vb.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi create mode 100644 arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi + create mode 100644 arch/arm64/boot/dts/renesas/ulcb-vb.dtsi + create mode 100644 arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile -index 32fb4d9..52d783b 100644 +index 32fb4d9..26d258d2 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile -@@ -4,5 +4,22 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb +@@ -4,5 +4,23 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb @@ -115,10 +125,11 @@ index 32fb4d9..52d783b 100644 +dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-had-alfa.dtb r8a7795-h3ulcb-had-beta.dtb r8a7795-es1-h3ulcb-had-alfa.dtb r8a7795-es1-h3ulcb-had-beta.dtb +dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb r8a7795-es1-h3ulcb-kf.dtb +dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-vb.dtb r8a7795-es1-h3ulcb-vb.dtb ++dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-vbm.dtb r8a7795-es1-h3ulcb-vbm.dtb +dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-eagle.dtb +dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk.dtb +dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk-kf.dtb -+dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk-vb.dtb ++dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk-vbm.dtb + +# ADAS legacy boards +subdir-y := legacy @@ -6719,10 +6730,10 @@ index 0000000..849afae +//#include "ulcb-kf-cn11.dtsi" diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vb.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vb.dts new file mode 100644 -index 0000000..e5734aa +index 0000000..549a717 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vb.dts -@@ -0,0 +1,1787 @@ +@@ -0,0 +1,69 @@ +/* + * Device Tree Source for the H3ULCB Videobox board on r8a7795 ES1.x + * @@ -6735,170 +6746,11 @@ index 0000000..e5734aa + */ + +#include "r8a7795-es1-h3ulcb.dts" ++#include "ulcb-vb.dtsi" + +/ { + model = "Renesas H3ULCB Videobox board based on r8a7795"; + -+ leds { -+ compatible = "gpio-leds"; -+ -+ led5 { -+ gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; -+ }; -+ led6 { -+ gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; -+ }; -+ /* D13 - status 0 */ -+ led_ext00 { -+ gpios = <&gpio_ext_led 0 GPIO_ACTIVE_LOW>; -+ /* linux,default-trigger = "heartbeat"; */ -+ }; -+ /* D14 - status 1 */ -+ led_ext01 { -+ gpios = <&gpio_ext_led 1 GPIO_ACTIVE_LOW>; -+ /* linux,default-trigger = "mmc1"; */ -+ }; -+ /* D16 - HDMI1 */ -+ led_ext02 { -+ gpios = <&gpio_ext_led 2 GPIO_ACTIVE_LOW>; -+ }; -+ /* D18 - HDMI0 */ -+ led_ext03 { -+ gpios = <&gpio_ext_led 3 GPIO_ACTIVE_LOW>; -+ }; -+ /* D20 - USB3.0 - 0.1 */ -+ led_ext04 { -+ gpios = <&gpio_ext_led 4 GPIO_ACTIVE_LOW>; -+ }; -+ /* D21 - USB3.0 - 0.2 */ -+ led_ext05 { -+ gpios = <&gpio_ext_led 5 GPIO_ACTIVE_LOW>; -+ }; -+ /* D24 - USB3.0 - 1.1 */ -+ led6_ext06 { -+ gpios = <&gpio_ext_led 6 GPIO_ACTIVE_LOW>; -+ }; -+ /* D25 - USB3.0 - 1.2 */ -+ led_ext07 { -+ gpios = <&gpio_ext_led 7 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ snd_clk: snd_clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24576000>; -+ clock-output-names = "scki"; -+ }; -+ -+ vccq_sdhi3: regulator@5 { -+ compatible = "regulator-fixed"; -+ -+ regulator-name = "SDHI3 VccQ"; -+ /* external voltage translator to 1.8V */ -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ fpdlink_switch: regulator@8 { -+ compatible = "regulator-fixed"; -+ regulator-name = "fpdlink_on"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio1 20 0>; -+ enable-active-high; -+ regulator-always-on; -+ }; -+ -+ hub_reset: regulator@9 { -+ compatible = "regulator-fixed"; -+ regulator-name = "hub_reset"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio5 5 0>; -+ enable-active-high; -+ regulator-always-on; -+ }; -+ -+ hub_power: regulator@10 { -+ compatible = "regulator-fixed"; -+ regulator-name = "hub_power"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio6 28 0>; -+ enable-active-high; -+ regulator-always-on; -+ }; -+ -+ /delete-node/sound; -+ -+ rsnd_ak4613: sound@0 { -+ pinctrl-0 = <&sound_0_pins>; -+ pinctrl-names = "default"; -+ compatible = "simple-audio-card"; -+ -+ simple-audio-card,format = "left_j"; -+ simple-audio-card,name = "ak4613"; -+ -+ simple-audio-card,bitclock-master = <&sndcpu>; -+ simple-audio-card,frame-master = <&sndcpu>; -+ -+ sndcpu: simple-audio-card,cpu@1 { -+ sound-dai = <&rcar_sound>; -+ }; -+ -+ sndcodec: simple-audio-card,codec@1 { -+ sound-dai = <&ak4613>; -+ }; -+ }; -+ -+ lvds-encoder { -+ compatible = "thine,thc63lvdm83d"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ port@0 { -+ reg = <0>; -+ lvds_enc_in: endpoint { -+ remote-endpoint = <&du_out_lvds0>; -+ }; -+ }; -+ port@1 { -+ reg = <1>; -+ lvds_enc_out: endpoint { -+ remote-endpoint = <&lvds_in>; -+ }; -+ }; -+ }; -+ }; -+ -+ lvds { -+ compatible = "lvds-connector"; -+ -+ width-mm = <210>; -+ height-mm = <158>; -+ -+ panel-timing { -+ /* 1280x800 @60Hz */ -+ clock-frequency = <65000000>; -+ hactive = <1280>; -+ vactive = <800>; -+ hsync-len = <40>; -+ hfront-porch = <80>; -+ hback-porch = <40>; -+ vfront-porch = <14>; -+ vback-porch = <14>; -+ vsync-len = <4>; -+ }; -+ -+ port { -+ lvds_in: endpoint { -+ remote-endpoint = <&lvds_enc_out>; -+ }; -+ }; -+ }; -+ + hdmi1-out { + compatible = "hdmi-connector"; + type = "a"; @@ -6909,76 +6761,10 @@ index 0000000..e5734aa + }; + }; + }; -+ -+ excan_ref_clk: excan-ref-clock { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <16000000>; -+ }; -+ -+ radio: si468x@0 { -+ compatible = "si,si468x-pcm"; -+ status = "okay"; -+ -+ #sound-dai-cells = <0>; -+ }; -+ -+ spi_gpio_sw { -+ compatible = "spi-gpio"; -+ #address-cells = <0x1>; -+ #size-cells = <0x0>; -+ gpio-sck = <&gpio0 8 GPIO_ACTIVE_HIGH>; -+ gpio-miso = <&gpio0 10 GPIO_ACTIVE_HIGH>; -+ gpio-mosi = <&gpio0 11 GPIO_ACTIVE_HIGH>; -+ cs-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; -+ num-chipselects = <1>; -+ -+ spidev: spidev@0 { -+ compatible = "spidev", "spi-gpio"; -+ reg = <0>; -+ spi-max-frequency = <25000000>; -+ spi-cpha; -+ spi-cpol; -+ }; -+ }; -+ -+ spi_gpio_can { -+ compatible = "spi-gpio"; -+ #address-cells = <0x1>; -+ #size-cells = <0x0>; -+ gpio-sck = <&gpio1 2 GPIO_ACTIVE_HIGH>; -+ gpio-miso = <&gpio1 3 GPIO_ACTIVE_HIGH>; -+ gpio-mosi = <&gpio1 1 GPIO_ACTIVE_HIGH>; -+ cs-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH -+ &gpio1 4 GPIO_ACTIVE_HIGH>; -+ num-chipselects = <2>; -+ -+ spican0: spidev@0 { -+ compatible = "microchip,mcp2515"; -+ reg = <0>; -+ clocks = <&excan_ref_clk>; -+ interrupt-parent = <&gpio0>; -+ interrupts = <15 GPIO_ACTIVE_LOW>; -+ spi-max-frequency = <10000000>; -+ }; -+ spican1: spidev@1 { -+ compatible = "microchip,mcp2515"; -+ reg = <1>; -+ clocks = <&excan_ref_clk>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <5 GPIO_ACTIVE_LOW>; -+ spi-max-frequency = <10000000>; -+ }; -+ }; +}; + +&du { + ports { -+ port@1 { -+ endpoint { -+ remote-endpoint = <&rcar_dw_hdmi0_in>; -+ }; -+ }; + port@2 { + endpoint { + remote-endpoint = <&rcar_dw_hdmi1_in>; @@ -6998,6 +6784,7 @@ index 0000000..e5734aa + ports { + #address-cells = <1>; + #size-cells = <0>; ++ + port@0 { + reg = <0>; + rcar_dw_hdmi1_in: endpoint { @@ -7013,2567 +6800,559 @@ index 0000000..e5734aa + }; +}; + -+&pfc { -+ hscif4_pins: hscif4 { -+ groups = "hscif4_data_a", "hscif4_ctrl"; -+ function = "hscif4"; -+ }; ++&hsusb { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vbm.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vbm.dts +new file mode 100644 +index 0000000..323722c +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vbm.dts +@@ -0,0 +1,26 @@ ++/* ++ * Device Tree Source for the H3ULCB Videobox Mini board on r8a7795 ES1.x ++ * ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ + -+ sdhi3_pins_3v3: sd3_3v3 { -+ groups = "sdhi3_data4", "sdhi3_ctrl"; -+ function = "sdhi3"; -+ power-source = <3300>; -+ }; ++#include "r8a7795-es1-h3ulcb.dts" ++#include "ulcb-vbm.dtsi" + -+ /delete-node/sound; ++/ { ++ model = "Renesas H3ULCB Videobox Mini board based on r8a7795"; ++}; + -+ sound_0_pins: sound1 { -+ groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; -+ function = "ssi"; ++&du { ++ ports { ++ port@3 { ++ endpoint { ++ remote-endpoint = <&lvds_enc_in>; ++ }; ++ }; + }; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts +new file mode 100644 +index 0000000..de56fa4 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts +@@ -0,0 +1,546 @@ ++/* ++ * Device Tree Source for the H3ULCB.View board on r8a7795 ES1.x ++ * ++ * Copyright (C) 2016-2017 Renesas Electronics Corp. ++ * Copyright (C) 2016-2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ + -+ usb0_pins: usb0 { -+ groups = "usb0"; -+ function = "usb0"; -+ }; ++#include "r8a7795-es1-h3ulcb.dts" + -+ can0_pins: can0 { -+ groups = "can0_data_a"; -+ function = "can0"; -+ }; ++/ { ++ model = "Renesas H3ULCB.View board based on r8a7795"; ++}; + -+ can1_pins: can1 { -+ groups = "can1_data"; -+ function = "can1"; -+ }; ++&i2c4 { ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; + -+ canfd0_pins: canfd0 { -+ groups = "canfd0_data_a"; -+ function = "canfd0"; ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ }; + }; + -+ canfd1_pins: canfd1 { -+ groups = "canfd1_data"; -+ function = "canfd1"; -+ }; -+}; ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; + -+&gpio0 { -+ video_a_irq { -+ gpio-hog; -+ gpios = <12 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A irq"; ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ }; + }; + -+ video_b_irq { -+ gpio-hog; -+ gpios = <13 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-B irq"; -+ }; ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; + -+ video_c_irq { -+ gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-C irq"; ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ }; + }; -+}; + -+&gpio1 { -+ gpioext_4_22_irq { -+ gpio-hog; -+ gpios = <25 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "0x22@i2c4 irq"; -+ }; -+ pcie_disable { -+ gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "mPCIe W_DISABLE"; -+ }; -+ m2_sleep { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "M.2 SLEEP#"; -+ }; -+ m2_pres { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "M.2 Present"; -+ }; -+ m2_pcie_det { -+ gpio-hog; -+ gpios = <18 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "M.2 PCIe detected"; -+ }; -+ m2_usb_det { -+ gpio-hog; -+ gpios = <19 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "M.2 USB30 detected"; -+ }; -+ m2_usb_det { -+ gpio-hog; -+ gpios = <27 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "M.2 SSD detected"; -+ }; -+ eth_phy_reset { -+ gpio-hog; -+ gpios = <16 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "BR phy reset"; -+ }; -+ eth_sw_reset { -+ gpio-hog; -+ gpios = <17 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "BR switch reset"; -+ }; -+}; ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; + -+&gpio2 { -+ m2_wake { -+ gpio-hog; -+ gpios = <1 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "M.2 WAKE#"; -+ }; -+ m2_pcie_en { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "M.2 PCIe enable"; ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_des0ep3: endpoint { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; + }; -+}; + -+&gpio3 { -+ m2_power_off { -+ gpio-hog; -+ gpios = <15 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "M.2 FULL_CARD_POWER_OFF#"; -+ }; -+}; ++ ov106xx@4 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x64>; + -+&gpio6 { -+ pcie_wake { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "mPCIe WAKE#"; -+ }; -+ pcie_clkreq { -+ gpio-hog; -+ gpios = <10 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "mPCIe CLKREQ#"; -+ }; -+ m2_rst { -+ gpio-hog; -+ gpios = <21 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "M.2 RESET#"; ++ port@0 { ++ ov106xx_in4: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin4ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ }; + }; -+}; -+ -+&hscif4 { -+ pinctrl-0 = <&hscif4_pins>; -+ pinctrl-names = "default"; -+ uart-has-rtscts; -+ -+ status = "okay"; -+}; + -+&i2c2 { -+ clock-frequency = <400000>; ++ ov106xx@5 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x65>; + -+ i2cswitch2: pca9548@74 { -+ compatible = "nxp,pca9548"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x74>; -+ reset-gpios = <&gpio6 5 GPIO_ACTIVE_LOW>; -+ -+ i2c@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ /* USB3.0 HUB node(s) */ ++ port@0 { ++ ov106xx_in5: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin5ep0>; ++ }; + }; -+ -+ i2c@6 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <6>; -+ /* PCIe node(s) */ ++ port@1 { ++ ov106xx_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; + }; ++ }; + -+ i2c@7 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <7>; -+ /* Slot A (CN10) */ -+ -+ ov106xx@0 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x60>; ++ ov106xx@6 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x66>; + -+ port@0 { -+ ov106xx_in0: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin0ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep0>; -+ }; -+ ov106xx_ti964_des0ep0: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep0>; -+ }; -+ ov106xx_ti954_des0ep0: endpoint@2 { -+ remote-endpoint = <&ti954_des0ep0>; -+ }; -+ }; ++ port@0 { ++ ov106xx_in6: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin6ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; + }; ++ }; ++ }; + -+ ov106xx@1 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x61>; ++ ov106xx@7 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x67>; + -+ port@0 { -+ ov106xx_in1: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin1ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep1>; -+ }; -+ ov106xx_ti964_des0ep1: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep1>; -+ }; -+ ov106xx_ti954_des0ep1: endpoint@2 { -+ remote-endpoint = <&ti954_des0ep1>; -+ }; -+ }; ++ port@0 { ++ ov106xx_in7: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin7ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_des1ep3: endpoint { ++ remote-endpoint = <&max9286_des1ep3>; + }; ++ }; ++ }; + -+ ov106xx@2 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x62>; ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x4c>; ++ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; ++ maxim,sensor_delay = <0>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ maxim,i2c-quirk = <0x6c>; + -+ port@0 { -+ ov106xx_in2: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin2ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep2>; -+ }; -+ ov106xx_ti964_des0ep2: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep2>; -+ }; -+ }; ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; + }; ++ }; ++ }; + -+ ov106xx@3 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x63>; ++ max9286-max9271@1 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x6c>; ++ gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; ++ maxim,sensor_delay = <0>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; + -+ port@0 { -+ ov106xx_in3: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin3ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep3>; -+ }; -+ ov106xx_ti964_des0ep3: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep3>; -+ }; -+ }; ++ port@0 { ++ max9286_des1ep0: endpoint@0 { ++ max9271-addr = <0x54>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ max9286_des1ep1: endpoint@1 { ++ max9271-addr = <0x55>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ max9286_des1ep2: endpoint@2 { ++ max9271-addr = <0x56>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ max9286_des1ep3: endpoint@3 { ++ max9271-addr = <0x57>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ max9286_csi2ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_41_ep>; + }; ++ }; ++ }; ++}; + -+ /* DS90UB964 @ 0x3a */ -+ ti964-ti9x3@0 { -+ compatible = "ti,ti964-ti9x3"; -+ reg = <0x3a>; -+ ti,sensor_delay = <350>; -+ ti,links = <4>; -+ ti,lanes = <4>; -+ ti,forwarding-mode = "round-robin"; -+ ti,cable-mode = "stp"; ++&pcie_bus_clk { ++ clock-frequency = <100000000>; ++ status = "okay"; ++}; + -+ port@0 { -+ ti964_des0ep0: endpoint@0 { -+ ti9x3-addr = <0x0c>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ ti964_des0ep1: endpoint@1 { -+ ti9x3-addr = <0x0d>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ ti964_des0ep2: endpoint@2 { -+ ti9x3-addr = <0x0e>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in2>; -+ }; -+ ti964_des0ep3: endpoint@3 { -+ ti9x3-addr = <0x0f>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in3>; -+ }; -+ }; -+ port@1 { -+ ti964_csi0ep0: endpoint { -+ csi-rate = <1450>; -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ }; -+ -+ /* DS90UB954 @ 0x38 */ -+ ti954-ti9x3@0 { -+ compatible = "ti,ti954-ti9x3"; -+ reg = <0x38>; -+ /* gpios = <&video_a_ext1 10 GPIO_ACTIVE_HIGH>; */ -+ ti,sensor_delay = <350>; -+ ti,links = <2>; -+ ti,lanes = <4>; -+ ti,forwarding-mode = "round-robin"; -+ ti,cable-mode = "stp"; ++&pciec1 { ++ status = "okay"; ++}; + -+ port@0 { -+ ti954_des0ep0: endpoint@0 { -+ ti9x3-addr = <0x0c>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ ti954_des0ep1: endpoint@1 { -+ ti9x3-addr = <0x0d>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ }; -+ port@1 { -+ ti954_csi0ep0: endpoint { -+ csi-rate = <1450>; -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ }; ++&vin0 { ++ status = "okay"; + -+ /* MAX9286 @ 0x2c */ -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; -+ reg = <0x2c>; -+ maxim,sensor_delay = <350>; -+ maxim,links = <4>; -+ maxim,lanes = <4>; -+ maxim,resetb-gpio = <1>; -+ maxim,fsync-mode = "automatic"; -+ maxim,timeout = <100>; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ port@0 { -+ max9286_des0ep0: endpoint@0 { -+ max9271-addr = <0x50>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ max9286_des0ep1: endpoint@1 { -+ max9271-addr = <0x51>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ max9286_des0ep2: endpoint@2 { -+ max9271-addr = <0x52>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in2>; -+ }; -+ max9286_des0ep3: endpoint@3 { -+ max9271-addr = <0x53>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in3>; -+ }; -+ }; -+ port@1 { -+ max9286_csi0ep0: endpoint { -+ csi-rate = <700>; -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; + }; + }; ++ }; ++}; + -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <2>; -+ /* Slot B (CN11) */ ++&vin1 { ++ status = "okay"; + -+ ov106xx@4 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x64>; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ port@0 { -+ ov106xx_in4: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin4ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep0>; -+ }; -+ ov106xx_ti964_des1ep0: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep0>; -+ }; -+ ov106xx_ti954_des1ep0: endpoint@2 { -+ remote-endpoint = <&ti954_des1ep0>; -+ }; -+ }; ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; + }; ++ }; ++ }; ++}; + -+ ov106xx@5 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x65>; ++&vin2 { ++ status = "okay"; + -+ port@0 { -+ ov106xx_in5: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin5ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep1>; -+ }; -+ ov106xx_ti964_des1ep1: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep1>; -+ }; -+ ov106xx_ti954_des1ep1: endpoint@2 { -+ remote-endpoint = <&ti954_des1ep1>; -+ }; -+ }; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; + }; ++ }; ++ }; ++}; + -+ ov106xx@6 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x66>; ++&vin3 { ++ status = "okay"; + -+ port@0 { -+ ov106xx_in6: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin6ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep2>; -+ }; -+ ov106xx_ti964_des1ep2: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep2>; -+ }; -+ }; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; + }; ++ }; ++ }; ++}; + -+ ov106xx@7 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x67>; ++&vin4 { ++ status = "okay"; + -+ port@0 { -+ ov106xx_in7: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin7ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep3>; -+ }; -+ ov106xx_ti964_des1ep3: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep3>; -+ }; -+ }; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi41"; ++ virtual,channel = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin4_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; + }; ++ }; ++ }; ++}; + -+ /* DS90UB964 @ 0x3a */ -+ ti964-ti9x3@1 { -+ compatible = "ti,ti964-ti9x3"; -+ reg = <0x3a>; -+ ti,sensor_delay = <350>; -+ ti,links = <4>; -+ ti,lanes = <4>; -+ ti,forwarding-mode = "round-robin"; -+ ti,cable-mode = "stp"; ++&vin5 { ++ status = "okay"; + -+ port@0 { -+ ti964_des1ep0: endpoint@0 { -+ ti9x3-addr = <0x0c>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in4>; -+ }; -+ ti964_des1ep1: endpoint@1 { -+ ti9x3-addr = <0x0d>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in5>; -+ }; -+ ti964_des1ep2: endpoint@2 { -+ ti9x3-addr = <0x0e>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in6>; -+ }; -+ ti964_des1ep3: endpoint@3 { -+ ti9x3-addr = <0x0f>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in7>; -+ }; -+ }; -+ port@1 { -+ ti964_csi2ep0: endpoint { -+ csi-rate = <1450>; -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin5ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep1: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin5_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; + }; ++ }; ++ }; ++}; + -+ /* DS90UB954 @ 0x38 */ -+ ti954-ti9x3@1 { -+ compatible = "ti,ti954-ti9x3"; -+ reg = <0x38>; -+ /* gpios = <&video_b_ext1 10 GPIO_ACTIVE_HIGH>; */ -+ ti,sensor_delay = <350>; -+ ti,links = <2>; -+ ti,lanes = <4>; -+ ti,forwarding-mode = "round-robin"; -+ ti,cable-mode = "stp"; ++&vin6 { ++ status = "okay"; + -+ port@0 { -+ ti954_des1ep0: endpoint@0 { -+ ti9x3-addr = <0x0c>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in4>; -+ }; -+ ti954_des1ep1: endpoint@1 { -+ ti9x3-addr = <0x0d>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in5>; -+ }; -+ }; -+ port@1 { -+ ti954_csi2ep0: endpoint { -+ csi-rate = <1450>; -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin6ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <2>; ++ remote-endpoint = <&ov106xx_in6>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep2: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin6_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; + }; ++ }; ++ }; ++}; + -+ /* MAX9286 @ 0x2c */ -+ max9286-max9271@1 { -+ compatible = "maxim,max9286-max9271"; -+ reg = <0x2c>; -+ maxim,sensor_delay = <350>; -+ maxim,links = <4>; -+ maxim,lanes = <4>; -+ maxim,resetb-gpio = <1>; -+ maxim,fsync-mode = "automatic"; -+ maxim,timeout = <100>; ++&vin7 { ++ status = "okay"; + -+ port@0 { -+ max9286_des1ep0: endpoint@0 { -+ max9271-addr = <0x50>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in4>; -+ }; -+ max9286_des1ep1: endpoint@1 { -+ max9271-addr = <0x51>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in5>; -+ }; -+ max9286_des1ep2: endpoint@2 { -+ max9271-addr = <0x52>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in6>; -+ }; -+ max9286_des1ep3: endpoint@3 { -+ max9271-addr = <0x53>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in7>; -+ }; -+ }; -+ port@1 { -+ max9286_csi2ep0: endpoint { -+ csi-rate = <700>; -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin7ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <3>; ++ remote-endpoint = <&ov106xx_in7>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep3: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin7_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; + }; + }; ++ }; ++}; + -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <3>; -+ /* Slot C (CN12) */ ++&csi2_40 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; + }; ++ }; + -+ i2c@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ /* Slot A (CN10) */ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ video_a_ext0: pca9535@26 { -+ compatible = "nxp,pca9535"; -+ reg = <0x26>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ video_a_des_cfg1 { -+ gpio-hog; -+ gpios = <5 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A cfg1"; -+ }; -+ video_a_des_cfg0 { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A cfg0"; -+ }; -+ video_a_pwr_shdn { -+ gpio-hog; -+ gpios = <3 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR_SHDN"; -+ }; -+ video_a_cam_pwr0 { -+ gpio-hog; -+ gpios = <12 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR0"; -+ }; -+ video_a_cam_pwr1 { -+ gpio-hog; -+ gpios = <13 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR1"; -+ }; -+ video_a_cam_pwr2 { -+ gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR2"; -+ }; -+ video_a_cam_pwr3 { -+ gpio-hog; -+ gpios = <15 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR3"; -+ }; -+ video_a_des_shdn { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A DES_SHDN"; -+ }; -+ video_a_des_led { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "Video-A led"; -+ }; -+ }; -+ -+ video_a_ext1: max7325@5c { -+ compatible = "maxim,max7325"; -+ reg = <0x5c>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ video_a_des_cfg2 { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A cfg2"; -+ }; -+ video_a_des_cfg1 { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A cfg1"; -+ }; -+ video_a_des_cfg0 { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A cfg0"; -+ }; -+ video_a_pwr_shdn { -+ gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR_SHDN"; -+ }; -+ video_a_cam_pwr0 { -+ gpio-hog; -+ gpios = <8 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR0"; -+ }; -+ video_a_cam_pwr1 { -+ gpio-hog; -+ gpios = <9 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR1"; -+ }; -+ video_a_cam_pwr2 { -+ gpio-hog; -+ gpios = <10 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR2"; -+ }; -+ video_a_cam_pwr3 { -+ gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR3"; -+ }; -+ video_a_des_shdn { -+ gpio-hog; -+ gpios = <13 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A DES_SHDN"; -+ }; -+ video_a_led { -+ gpio-hog; -+ gpios = <12 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "Video-A LED"; -+ }; -+ }; -+ }; -+ -+ i2c@5 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <5>; -+ /* Slot B (CN11) */ -+ -+ video_b_ext0: pca9535@26 { -+ compatible = "nxp,pca9535"; -+ reg = <0x26>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ video_b_des_cfg1 { -+ gpio-hog; -+ gpios = <5 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-B cfg1"; -+ }; -+ video_b_des_cfg0 { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-B cfg0"; -+ }; -+ video_b_pwr_shdn { -+ gpio-hog; -+ gpios = <3 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR_SHDN"; -+ }; -+ video_b_cam_pwr0 { -+ gpio-hog; -+ gpios = <12 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR0"; -+ }; -+ video_b_cam_pwr1 { -+ gpio-hog; -+ gpios = <13 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR1"; -+ }; -+ video_b_cam_pwr2 { -+ gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR2"; -+ }; -+ video_b_cam_pwr3 { -+ gpio-hog; -+ gpios = <15 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR3"; -+ }; -+ video_b_des_shdn { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B DES_SHDN"; -+ }; -+ video_b_des_led { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "Video-B led"; -+ }; -+ }; -+ -+ video_b_ext1: max7325@5c { -+ compatible = "maxim,max7325"; -+ reg = <0x5c>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ video_b_des_cfg2 { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-B cfg2"; -+ }; -+ video_b_des_cfg1 { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-B cfg1"; -+ }; -+ video_b_des_cfg0 { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-B cfg0"; -+ }; -+ video_b_pwr_shdn { -+ gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR_SHDN"; -+ }; -+ video_b_cam_pwr0 { -+ gpio-hog; -+ gpios = <8 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR0"; -+ }; -+ video_b_cam_pwr1 { -+ gpio-hog; -+ gpios = <9 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR1"; -+ }; -+ video_b_cam_pwr2 { -+ gpio-hog; -+ gpios = <10 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR2"; -+ }; -+ video_b_cam_pwr3 { -+ gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR3"; -+ }; -+ video_b_des_shdn { -+ gpio-hog; -+ gpios = <13 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B DES_SHDN"; -+ }; -+ video_b_led { -+ gpio-hog; -+ gpios = <12 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "Video-B LED"; -+ }; -+ }; -+ }; -+ -+ i2c@4 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <4>; -+ /* Slot C (CN12) */ -+ }; -+ }; -+}; -+ -+&i2c4 { -+ i2cswitch4: pca9548@74 { -+ compatible = "nxp,pca9548"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x74>; -+ reset-gpios= <&gpio5 15 GPIO_ACTIVE_LOW>; -+ -+ i2c@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ /* FAN node - EMC2103 */ -+ fan_ctrl:ecm2103@2e { -+ compatible = "emc2103"; -+ reg = <0x2e>; -+ }; -+ }; -+ -+ i2c@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ /* Power nodes - 2 x TPS544x20 */ -+ }; -+ -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <2>; -+ /* CAN and power board nodes */ -+ -+ gpio_ext_pwr: pca9535@22 { -+ compatible = "nxp,pca9535"; -+ reg = <0x22>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ interrupt-parent = <&gpio1>; -+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>; -+ -+ /* enable input DCDC after wake-up signal released */ -+ pwr_hold { -+ gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "pwr_hold"; -+ }; -+ -+ /* CAN0 */ -+ can0_stby { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "can0_stby"; -+ }; -+ can0_load { -+ gpio-hog; -+ gpios = <0 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "can0_120R_load"; -+ }; -+ /* CAN1 */ -+ can1_stby { -+ gpio-hog; -+ gpios = <5 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "can1_stby"; -+ }; -+ can1_load { -+ gpio-hog; -+ gpios = <1 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "can1_120R_load"; -+ }; -+ /* CAN2 */ -+ can2_stby { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "can2_stby"; -+ }; -+ can2_load { -+ gpio-hog; -+ gpios = <2 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "can2_120R_load"; -+ }; -+ can2_rst { -+ gpio-hog; -+ gpios = <8 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "can2_rst"; -+ }; -+ /* CAN3 */ -+ can3_stby { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "can3_stby"; -+ }; -+ can3_load { -+ gpio-hog; -+ gpios = <3 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "can3_120R_load"; -+ }; -+ can3_rst { -+ gpio-hog; -+ gpios = <9 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "can3_rst"; -+ }; -+ }; -+ }; -+ -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <3>; -+ /* FPDLink output node - DS90UH947 */ -+ }; -+ -+ i2c@4 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <4>; -+ /* BCM switch node */ -+ }; -+ -+ i2c@5 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <5>; -+ /* LED board node(s) */ -+ -+ gpio_ext_led: pca9535@22 { -+ compatible = "nxp,pca9535"; -+ reg = <0x22>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ /* gpios 0..7 are used for indication LEDs, low-active */ -+ }; -+ }; -+ -+ i2c@6 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <6>; -+ /* M2 connector i2c node(s) */ -+ }; -+ -+ /* port 7 is not used */ -+ }; -+}; -+ -+&pcie_bus_clk { -+ clock-frequency = <100000000>; -+ status = "okay"; -+}; -+ -+&pciec0 { -+ status = "okay"; -+}; -+ -+&pciec1 { -+ status = "okay"; -+}; -+ -+&vin0 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin0ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ }; -+ port@1 { -+ csi0ep0: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ port@2 { -+ vin0_max9286_des0ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep0>; -+ }; -+ vin0_ti964_des0ep0: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep0>; -+ }; -+ vin0_ti954_des0ep0: endpoint@2 { -+ remote-endpoint = <&ti954_des0ep0>; -+ }; -+ }; -+ }; -+}; -+ -+&vin1 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin1ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <1>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ }; -+ port@1 { -+ csi0ep1: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ port@2 { -+ vin1_max9286_des0ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep1>; -+ }; -+ vin1_ti964_des0ep1: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep1>; -+ }; -+ vin1_ti954_des0ep1: endpoint@2 { -+ remote-endpoint = <&ti954_des0ep1>; -+ }; -+ }; -+ }; -+}; -+ -+&vin2 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin2ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <2>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in2>; -+ }; -+ }; -+ port@1 { -+ csi0ep2: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ port@2 { -+ vin2_max9286_des0ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep2>; -+ }; -+ vin2_ti964_des0ep2: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep2>; -+ }; -+ }; -+ }; -+}; -+ -+&vin3 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin3ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <3>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in3>; -+ }; -+ }; -+ port@1 { -+ csi0ep3: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ port@2 { -+ vin3_max9286_des0ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep3>; -+ }; -+ vin3_ti964_des0ep3: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep3>; -+ }; -+ }; -+ }; -+}; -+ -+&vin4 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin4ep0: endpoint { -+ csi,select = "csi41"; -+ virtual,channel = <0>; -+ remote-endpoint = <&ov106xx_in4>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ port@1 { -+ csi2ep0: endpoint { -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; -+ port@2 { -+ vin4_max9286_des1ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep0>; -+ }; -+ vin4_ti964_des1ep0: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep0>; -+ }; -+ vin4_ti954_des1ep0: endpoint@2 { -+ remote-endpoint = <&ti954_des1ep0>; -+ }; -+ }; -+ }; -+}; -+ -+&vin5 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin5ep0: endpoint@0 { -+ csi,select = "csi41"; -+ virtual,channel = <1>; -+ remote-endpoint = <&ov106xx_in5>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ port@1 { -+ csi2ep1: endpoint { -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; -+ port@2 { -+ vin5_max9286_des1ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep1>; -+ }; -+ vin5_ti964_des1ep1: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep1>; -+ }; -+ vin5_ti954_des1ep1: endpoint@2 { -+ remote-endpoint = <&ti954_des1ep1>; -+ }; -+ }; -+ }; -+}; -+ -+&vin6 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin6ep0: endpoint@0 { -+ csi,select = "csi41"; -+ virtual,channel = <2>; -+ remote-endpoint = <&ov106xx_in6>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ port@1 { -+ csi2ep2: endpoint { -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; -+ port@2 { -+ vin6_max9286_des1ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep2>; -+ }; -+ vin6_ti964_des1ep2: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep2>; -+ }; -+ }; -+ }; -+}; -+ -+&vin7 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin7ep0: endpoint@0 { -+ csi,select = "csi41"; -+ virtual,channel = <3>; -+ remote-endpoint = <&ov106xx_in7>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ port@1 { -+ csi2ep3: endpoint { -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; -+ port@2 { -+ vin7_max9286_des1ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep3>; -+ }; -+ vin7_ti964_des1ep3: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep3>; -+ }; -+ }; -+ }; -+}; -+ -+&csi2_40 { -+ status = "okay"; -+ -+ virtual,channel { -+ csi2_vc0 { -+ data,type = "ycbcr422"; -+ receive,vc = <0>; -+ }; -+ csi2_vc1 { -+ data,type = "ycbcr422"; -+ receive,vc = <1>; -+ }; -+ csi2_vc2 { -+ data,type = "ycbcr422"; -+ receive,vc = <2>; -+ }; -+ csi2_vc3 { -+ data,type = "ycbcr422"; -+ receive,vc = <3>; -+ }; -+ }; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ csi2_40_ep: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ csi-rate = <300>; -+ }; -+ }; -+}; -+ -+&csi2_41 { -+ status = "okay"; -+ -+ virtual,channel { -+ csi2_vc0 { -+ data,type = "ycbcr422"; -+ receive,vc = <0>; -+ }; -+ csi2_vc1 { -+ data,type = "ycbcr422"; -+ receive,vc = <1>; -+ }; -+ csi2_vc2 { -+ data,type = "ycbcr422"; -+ receive,vc = <2>; -+ }; -+ csi2_vc3 { -+ data,type = "ycbcr422"; -+ receive,vc = <3>; -+ }; -+ }; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ csi2_41_ep: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ csi-rate = <300>; -+ }; -+ }; -+}; -+ -+&rcar_sound { -+ pinctrl-0 = <&sound_clk_pins>; -+ -+ /* Multi DAI */ -+ #sound-dai-cells = <1>; -+}; -+ -+&sata { -+ status = "okay"; -+}; -+ -+&ssi1 { -+ /delete-property/shared-pin; -+}; -+ -+&avb { -+ /delete-property/phy-handle; -+ /delete-property/phy-gpios; -+ phy-mode = "rgmii"; -+ -+ /delete-node/ethernet-phy@0; -+ -+ fixed-link { -+ speed = <100>; -+ full-duplex; -+ }; -+}; -+ -+&msiof1 { -+ status = "disabled"; -+}; -+ -+&usb2_phy0 { -+ pinctrl-0 = <&usb0_pins>; -+ pinctrl-names = "default"; -+ -+ status = "okay"; -+}; -+ -+&xhci0 { -+ status = "okay"; -+}; -+ -+&hsusb { -+ status = "okay"; -+}; -+ -+&ehci0 { -+ status = "okay"; -+}; -+ -+&ohci0 { -+ status = "okay"; -+}; -+ -+&can0 { -+ pinctrl-0 = <&can0_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ renesas,can-clock-select = <0x0>; -+}; -+ -+&can1 { -+ pinctrl-0 = <&can1_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ renesas,can-clock-select = <0x0>; -+}; -+ -+&canfd { -+ pinctrl-0 = <&canfd0_pins &canfd1_pins>; -+ pinctrl-names = "default"; -+ status = "disabled"; -+ -+ renesas,can-clock-select = <0x0>; -+ -+ channel0 { -+ status = "okay"; -+ }; -+ -+ channel1 { -+ status = "okay"; -+ }; -+}; -+ -+/* uncomment to enable CN12 on VIN4-7 */ -+//#include "ulcb-vb-cn12.dtsi" -diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts -new file mode 100644 -index 0000000..de56fa4 ---- /dev/null -+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts -@@ -0,0 +1,546 @@ -+/* -+ * Device Tree Source for the H3ULCB.View board on r8a7795 ES1.x -+ * -+ * Copyright (C) 2016-2017 Renesas Electronics Corp. -+ * Copyright (C) 2016-2017 Cogent Embedded, Inc. -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ -+ -+#include "r8a7795-es1-h3ulcb.dts" -+ -+/ { -+ model = "Renesas H3ULCB.View board based on r8a7795"; -+}; -+ -+&i2c4 { -+ ov106xx@0 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x60>; -+ -+ port@0 { -+ ov106xx_in0: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin0ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep0>; -+ }; -+ }; -+ }; -+ -+ ov106xx@1 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x61>; -+ -+ port@0 { -+ ov106xx_in1: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin1ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep1>; -+ }; -+ }; -+ }; -+ -+ ov106xx@2 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x62>; -+ -+ port@0 { -+ ov106xx_in2: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin2ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep2>; -+ }; -+ }; -+ }; -+ -+ ov106xx@3 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x63>; -+ -+ port@0 { -+ ov106xx_in3: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin3ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_des0ep3: endpoint { -+ remote-endpoint = <&max9286_des0ep3>; -+ }; -+ }; -+ }; -+ -+ ov106xx@4 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x64>; -+ -+ port@0 { -+ ov106xx_in4: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin4ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep0>; -+ }; -+ }; -+ }; -+ -+ ov106xx@5 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x65>; -+ -+ port@0 { -+ ov106xx_in5: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin5ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep1>; -+ }; -+ }; -+ }; -+ -+ ov106xx@6 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x66>; -+ -+ port@0 { -+ ov106xx_in6: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin6ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep2>; -+ }; -+ }; -+ }; -+ -+ ov106xx@7 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x67>; -+ -+ port@0 { -+ ov106xx_in7: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin7ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_des1ep3: endpoint { -+ remote-endpoint = <&max9286_des1ep3>; -+ }; -+ }; -+ }; -+ -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; -+ reg = <0x4c>; -+ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; -+ maxim,sensor_delay = <0>; -+ maxim,links = <4>; -+ maxim,lanes = <4>; -+ maxim,resetb-gpio = <1>; -+ maxim,fsync-mode = "automatic"; -+ maxim,timeout = <100>; -+ maxim,i2c-quirk = <0x6c>; -+ -+ port@0 { -+ max9286_des0ep0: endpoint@0 { -+ max9271-addr = <0x50>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ max9286_des0ep1: endpoint@1 { -+ max9271-addr = <0x51>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ max9286_des0ep2: endpoint@2 { -+ max9271-addr = <0x52>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in2>; -+ }; -+ max9286_des0ep3: endpoint@3 { -+ max9271-addr = <0x53>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in3>; -+ }; -+ }; -+ port@1 { -+ max9286_csi0ep0: endpoint { -+ csi-rate = <700>; -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ }; -+ -+ max9286-max9271@1 { -+ compatible = "maxim,max9286-max9271"; -+ reg = <0x6c>; -+ gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; -+ maxim,sensor_delay = <0>; -+ maxim,links = <4>; -+ maxim,lanes = <4>; -+ maxim,resetb-gpio = <1>; -+ maxim,fsync-mode = "automatic"; -+ maxim,timeout = <100>; -+ -+ port@0 { -+ max9286_des1ep0: endpoint@0 { -+ max9271-addr = <0x54>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in4>; -+ }; -+ max9286_des1ep1: endpoint@1 { -+ max9271-addr = <0x55>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in5>; -+ }; -+ max9286_des1ep2: endpoint@2 { -+ max9271-addr = <0x56>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in6>; -+ }; -+ max9286_des1ep3: endpoint@3 { -+ max9271-addr = <0x57>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in7>; -+ }; -+ }; -+ port@1 { -+ max9286_csi2ep0: endpoint { -+ csi-rate = <700>; -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; -+ }; -+}; -+ -+&pcie_bus_clk { -+ clock-frequency = <100000000>; -+ status = "okay"; -+}; -+ -+&pciec1 { -+ status = "okay"; -+}; -+ -+&vin0 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin0ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ }; -+ port@1 { -+ csi0ep0: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ port@2 { -+ vin0_max9286_des0ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep0>; -+ }; -+ }; -+ }; -+}; -+ -+&vin1 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin1ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <1>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ }; -+ port@1 { -+ csi0ep1: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ port@2 { -+ vin1_max9286_des0ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep1>; -+ }; -+ }; -+ }; -+}; -+ -+&vin2 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin2ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <2>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in2>; -+ }; -+ }; -+ port@1 { -+ csi0ep2: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ port@2 { -+ vin2_max9286_des0ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep2>; -+ }; -+ }; -+ }; -+}; -+ -+&vin3 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin3ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <3>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in3>; -+ }; -+ }; -+ port@1 { -+ csi0ep3: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ port@2 { -+ vin3_max9286_des0ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep3>; -+ }; -+ }; -+ }; -+}; -+ -+&vin4 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin4ep0: endpoint { -+ csi,select = "csi41"; -+ virtual,channel = <0>; -+ remote-endpoint = <&ov106xx_in4>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ port@1 { -+ csi2ep0: endpoint { -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; -+ port@2 { -+ vin4_max9286_des1ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep0>; -+ }; -+ }; -+ }; -+}; -+ -+&vin5 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin5ep0: endpoint@0 { -+ csi,select = "csi41"; -+ virtual,channel = <1>; -+ remote-endpoint = <&ov106xx_in5>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ port@1 { -+ csi2ep1: endpoint { -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; -+ port@2 { -+ vin5_max9286_des1ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep1>; -+ }; -+ }; -+ }; -+}; -+ -+&vin6 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin6ep0: endpoint@0 { -+ csi,select = "csi41"; -+ virtual,channel = <2>; -+ remote-endpoint = <&ov106xx_in6>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ port@1 { -+ csi2ep2: endpoint { -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; -+ port@2 { -+ vin6_max9286_des1ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep2>; -+ }; -+ }; -+ }; -+}; -+ -+&vin7 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin7ep0: endpoint@0 { -+ csi,select = "csi41"; -+ virtual,channel = <3>; -+ remote-endpoint = <&ov106xx_in7>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ port@1 { -+ csi2ep3: endpoint { -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; -+ port@2 { -+ vin7_max9286_des1ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep3>; -+ }; -+ }; -+ }; -+}; -+ -+&csi2_40 { -+ status = "okay"; -+ -+ virtual,channel { -+ csi2_vc0 { -+ data,type = "ycbcr422"; -+ receive,vc = <0>; -+ }; -+ csi2_vc1 { -+ data,type = "ycbcr422"; -+ receive,vc = <1>; -+ }; -+ csi2_vc2 { -+ data,type = "ycbcr422"; -+ receive,vc = <2>; -+ }; -+ csi2_vc3 { -+ data,type = "ycbcr422"; -+ receive,vc = <3>; -+ }; -+ }; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ csi2_40_ep: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ csi-rate = <300>; -+ }; -+ }; -+}; -+ -+&csi2_41 { -+ status = "okay"; -+ -+ virtual,channel { -+ csi2_vc0 { -+ data,type = "ycbcr422"; -+ receive,vc = <0>; -+ }; -+ csi2_vc1 { -+ data,type = "ycbcr422"; -+ receive,vc = <1>; -+ }; -+ csi2_vc2 { -+ data,type = "ycbcr422"; -+ receive,vc = <2>; -+ }; -+ csi2_vc3 { -+ data,type = "ycbcr422"; -+ receive,vc = <3>; -+ }; -+ }; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ csi2_41_ep: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ csi-rate = <300>; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x-view.dts -new file mode 100644 -index 0000000..3f3d66a ---- /dev/null -+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x-view.dts -@@ -0,0 +1,552 @@ -+/* -+ * Device Tree Source for the Salvator-X.View board on r8a7795 ES1.x -+ * -+ * Copyright (C) 2016-2017 Renesas Electronics Corp. -+ * Copyright (C) 2015-2017 Cogent Embedded, Inc -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ -+ -+#include "r8a7795-es1-salvator-x.dts" -+ -+/ { -+ model = "Renesas Salvator-X.View board based on r8a7795"; -+}; -+ -+&pfc { -+ can0_pins: can0 { -+ groups = "can0_data_a"; -+ function = "can0"; -+ }; -+ -+ can1_pins: can1 { -+ groups = "can1_data"; -+ function = "can1"; -+ }; -+}; -+ -+&i2c4 { -+ /delete-node/hdmi-in@34; -+ /delete-node/composite-in@70; -+ -+ ov106xx@0 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x60>; -+ -+ port@0 { -+ ov106xx_in0: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin0ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep0>; -+ }; -+ }; -+ }; -+ -+ ov106xx@1 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x61>; -+ -+ port@0 { -+ ov106xx_in1: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin1ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep1>; -+ }; -+ }; -+ }; -+ -+ ov106xx@2 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x62>; -+ -+ port@0 { -+ ov106xx_in2: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin2ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep2>; -+ }; -+ }; -+ }; -+ -+ ov106xx@3 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x63>; -+ -+ port@0 { -+ ov106xx_in3: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin3ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_des0ep3: endpoint { -+ remote-endpoint = <&max9286_des0ep3>; -+ }; -+ }; -+ }; -+ -+ ov106xx@4 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x64>; -+ -+ port@0 { -+ ov106xx_in4: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin4ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep0>; -+ }; -+ }; -+ }; -+ -+ ov106xx@5 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x65>; -+ -+ port@0 { -+ ov106xx_in5: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin5ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep1>; -+ }; -+ }; -+ }; -+ -+ ov106xx@6 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x66>; -+ -+ port@0 { -+ ov106xx_in6: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin6ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep2>; -+ }; -+ }; -+ }; -+ -+ ov106xx@7 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x67>; -+ -+ port@0 { -+ ov106xx_in7: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin7ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_des1ep3: endpoint { -+ remote-endpoint = <&max9286_des1ep3>; -+ }; -+ }; -+ }; -+ -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; -+ reg = <0x4c>; -+ gpios = <&gpio6 30 GPIO_ACTIVE_LOW>; -+ maxim,sensor_delay = <0>; -+ maxim,links = <4>; -+ maxim,lanes = <4>; -+ maxim,resetb-gpio = <1>; -+ maxim,fsync-mode = "automatic"; -+ maxim,timeout = <100>; -+ maxim,i2c-quirk = <0x6c>; -+ -+ port@0 { -+ max9286_des0ep0: endpoint@0 { -+ max9271-addr = <0x50>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ max9286_des0ep1: endpoint@1 { -+ max9271-addr = <0x51>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ max9286_des0ep2: endpoint@2 { -+ max9271-addr = <0x52>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in2>; -+ }; -+ max9286_des0ep3: endpoint@3 { -+ max9271-addr = <0x53>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in3>; -+ }; -+ }; -+ port@1 { -+ max9286_csi0ep0: endpoint { -+ csi-rate = <700>; -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ }; -+ -+ max9286-max9271@1 { -+ compatible = "maxim,max9286-max9271"; -+ reg = <0x6c>; -+ maxim,sensor_delay = <0>; -+ maxim,links = <4>; -+ maxim,lanes = <4>; -+ maxim,resetb-gpio = <1>; -+ maxim,fsync-mode = "automatic"; -+ maxim,timeout = <100>; -+ -+ port@0 { -+ max9286_des1ep0: endpoint@0 { -+ max9271-addr = <0x54>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in4>; -+ }; -+ max9286_des1ep1: endpoint@1 { -+ max9271-addr = <0x55>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in5>; -+ }; -+ max9286_des1ep2: endpoint@2 { -+ max9271-addr = <0x56>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in6>; -+ }; -+ max9286_des1ep3: endpoint@3 { -+ max9271-addr = <0x57>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in7>; -+ }; -+ }; -+ port@1 { -+ max9286_csi2ep0: endpoint { -+ csi-rate = <700>; -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; -+ }; -+}; -+ -+&vin0 { -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin0ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ }; -+ port@1 { -+ csi0ep0: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ port@2 { -+ vin0_max9286_des0ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep0>; -+ }; -+ }; -+ }; -+}; -+ -+&vin1 { -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin1ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <1>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ }; -+ port@1 { -+ csi0ep1: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ port@2 { -+ vin1_max9286_des0ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep1>; -+ }; -+ }; -+ }; -+}; -+ -+&vin2 { -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin2ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <2>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in2>; -+ }; -+ }; -+ port@1 { -+ csi0ep2: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ port@2 { -+ vin2_max9286_des0ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep2>; -+ }; -+ }; -+ }; -+}; -+ -+&vin3 { -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin3ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <3>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in3>; -+ }; -+ }; -+ port@1 { -+ csi0ep3: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ port@2 { -+ vin3_max9286_des0ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep3>; -+ }; -+ }; -+ }; -+}; -+ -+&vin4 { -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin4ep0: endpoint { -+ csi,select = "csi41"; -+ virtual,channel = <0>; -+ remote-endpoint = <&ov106xx_in4>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ port@1 { -+ csi2ep0: endpoint { -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; -+ port@2 { -+ vin4_max9286_des1ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep0>; -+ }; -+ }; -+ }; -+}; -+ -+&vin5 { -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin5ep0: endpoint@0 { -+ csi,select = "csi41"; -+ virtual,channel = <1>; -+ remote-endpoint = <&ov106xx_in5>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ port@1 { -+ csi2ep1: endpoint { -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; -+ port@2 { -+ vin5_max9286_des1ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep1>; -+ }; -+ }; -+ }; -+}; -+ -+&vin6 { -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin6ep0: endpoint@0 { -+ csi,select = "csi41"; -+ virtual,channel = <2>; -+ remote-endpoint = <&ov106xx_in6>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ port@1 { -+ csi2ep2: endpoint { -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; -+ port@2 { -+ vin6_max9286_des1ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep2>; -+ }; -+ }; -+ }; -+}; -+ -+&vin7 { -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin7ep0: endpoint@0 { -+ csi,select = "csi41"; -+ virtual,channel = <3>; -+ remote-endpoint = <&ov106xx_in7>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ port@1 { -+ csi2ep3: endpoint { -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; -+ port@2 { -+ vin7_max9286_des1ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep3>; -+ }; -+ }; -+ }; -+}; -+ -+&csi2_20 { -+ status = "disabled"; -+ /delete-node/ports; -+}; -+ -+&csi2_40 { -+ /delete-node/ports; -+ -+ virtual,channel { -+ csi2_vc0 { -+ data,type = "ycbcr422"; -+ receive,vc = <0>; -+ }; -+ csi2_vc1 { -+ data,type = "ycbcr422"; -+ receive,vc = <1>; -+ }; -+ csi2_vc2 { -+ data,type = "ycbcr422"; -+ receive,vc = <2>; -+ }; -+ csi2_vc3 { -+ data,type = "ycbcr422"; -+ receive,vc = <3>; -+ }; -+ }; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ csi2_40_ep: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ csi-rate = <300>; -+ }; -+ }; -+}; ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; + +&csi2_41 { + status = "okay"; @@ -9599,605 +7378,713 @@ index 0000000..3f3d66a + + port { + #address-cells = <1>; -+ #size-cells = <0>; -+ -+ csi2_41_ep: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ csi-rate = <300>; -+ }; -+ }; -+}; -+ -+&can0 { -+ pinctrl-0 = <&can0_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; -+ -+&can1 { -+ pinctrl-0 = <&can1_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; ++ #size-cells = <0>; ++ ++ csi2_41_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; +}; -diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-alfa.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-alfa.dts +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x-view.dts new file mode 100644 -index 0000000..ae115bd +index 0000000..3f3d66a --- /dev/null -+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-alfa.dts -@@ -0,0 +1,22 @@ ++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x-view.dts +@@ -0,0 +1,552 @@ +/* -+ * Device Tree Source for the H3ULCB.HAD board Alfa side ++ * Device Tree Source for the Salvator-X.View board on r8a7795 ES1.x + * -+ * Copyright (C) 2017 Renesas Electronics Corp. -+ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * Copyright (C) 2016-2017 Renesas Electronics Corp. ++ * Copyright (C) 2015-2017 Cogent Embedded, Inc + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + -+#include "r8a7795-h3ulcb-had.dtsi" ++#include "r8a7795-es1-salvator-x.dts" + +/ { -+ model = "Renesas H3ULCB.HAD board Alfa side based on r8a7795"; ++ model = "Renesas Salvator-X.View board based on r8a7795"; +}; + -+&pciec0 { -+ status = "okay"; ++&pfc { ++ can0_pins: can0 { ++ groups = "can0_data_a"; ++ function = "can0"; ++ }; + -+ /* Root complex */ ++ can1_pins: can1 { ++ groups = "can1_data"; ++ function = "can1"; ++ }; +}; -diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-beta.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-beta.dts -new file mode 100644 -index 0000000..805067e ---- /dev/null -+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-beta.dts -@@ -0,0 +1,23 @@ -+/* -+ * Device Tree Source for the H3ULCB.HAD board Beta side -+ * -+ * Copyright (C) 2017 Renesas Electronics Corp. -+ * Copyright (C) 2017 Cogent Embedded, Inc. -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ + -+#include "r8a7795-h3ulcb-had.dtsi" ++&i2c4 { ++ /delete-node/hdmi-in@34; ++ /delete-node/composite-in@70; + -+/ { -+ model = "Renesas H3ULCB.HAD board Beta side based on r8a7795"; -+}; ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; + -+&pciec0 { -+ status = "okay"; ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ }; ++ }; + -+ /* Endpoint */ -+ endpoint; -+}; -diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi -new file mode 100644 -index 0000000..4a00426 ---- /dev/null -+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi -@@ -0,0 +1,219 @@ -+/* -+ * Device Tree Source for the H3ULCB.HAD board on r8a7795 -+ * -+ * Copyright (C) 2016-2017 Renesas Electronics Corp. -+ * Copyright (C) 2016-2017 Cogent Embedded, Inc. -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; + -+/* -+ * MSIOF0 - /dev/spidev1.0 connected to FPGA ethernet switch (both sides) -+ * MSIOF1 - /dev/spidev2.0 connected to RH850 (sideA to CSIH1, sideB to CSIH0) -+ */ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ }; ++ }; + -+#include "r8a7795-h3ulcb-view.dts" ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; + -+/ { -+ model = "Renesas H3ULCB.HAD board based on r8a7795"; ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ }; ++ }; + -+ aliases { -+ serial1 = &scif1; -+ spi1 = &spi0_gpio; -+ spi2 = &spi1_gpio; ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_des0ep3: endpoint { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; + }; + -+ chosen { -+ stdout-path = "serial1:115200n8"; ++ ov106xx@4 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x64>; ++ ++ port@0 { ++ ov106xx_in4: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin4ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ }; + }; + -+ spi0_gpio: spi_gpio@0 { -+ compatible = "spi-gpio"; -+ num-chipselects = <1>; -+ gpio-sck = <&gpio5 17 0>; -+ gpio-mosi = <&gpio5 20 0>; -+ gpio-miso = <&gpio5 22 0>; -+ cs-gpios = <&gpio5 19 0>; -+ #address-cells = <1>; -+ #size-cells = <0>; ++ ov106xx@5 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x65>; + -+ spidev@0 { -+ compatible = "spi-gpio"; -+ reg = <0>; -+ spi-max-frequency = <2000000>; -+ spi-cpha; -+ spi-cpol; ++ port@0 { ++ ov106xx_in5: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin5ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; + }; + }; + -+ spi1_gpio: spi_gpio@1 { -+ compatible = "spi-gpio"; -+ num-chipselects = <1>; -+ gpio-sck = <&gpio6 8 0>; -+ gpio-mosi = <&gpio6 7 0>; -+ gpio-miso = <&gpio6 10 0>; -+ cs-gpios = <&gpio6 5 0>; -+ #address-cells = <1>; -+ #size-cells = <0>; ++ ov106xx@6 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x66>; ++ ++ port@0 { ++ ov106xx_in6: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin6ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@7 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x67>; ++ ++ port@0 { ++ ov106xx_in7: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin7ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_des1ep3: endpoint { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ }; ++ }; ++ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x4c>; ++ gpios = <&gpio6 30 GPIO_ACTIVE_LOW>; ++ maxim,sensor_delay = <0>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ maxim,i2c-quirk = <0x6c>; + -+ spidev@0 { -+ compatible = "spi-gpio"; -+ reg = <0>; -+ spi-max-frequency = <2000000>; -+ spi-cpha; -+ spi-cpol; ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; + }; + }; + -+ hdmi1-out { -+ compatible = "hdmi-connector"; -+ type = "a"; ++ max9286-max9271@1 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x6c>; ++ maxim,sensor_delay = <0>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; + -+ port { -+ hdmi1_con: endpoint { -+ remote-endpoint = <&rcar_dw_hdmi1_out>; ++ port@0 { ++ max9286_des1ep0: endpoint@0 { ++ max9271-addr = <0x54>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ max9286_des1ep1: endpoint@1 { ++ max9271-addr = <0x55>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ max9286_des1ep2: endpoint@2 { ++ max9271-addr = <0x56>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ max9286_des1ep3: endpoint@3 { ++ max9271-addr = <0x57>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ max9286_csi2ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_41_ep>; + }; + }; + }; +}; + -+&du { ++&vin0 { + ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; + port@1 { -+ endpoint { -+ remote-endpoint = <&rcar_dw_hdmi0_in>; ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; + }; + }; + port@2 { -+ endpoint { -+ remote-endpoint = <&rcar_dw_hdmi1_in>; ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; + }; + }; + }; +}; + -+&hdmi1 { -+ status = "okay"; -+ ++&vin1 { + ports { + #address-cells = <1>; + #size-cells = <0>; ++ + port@0 { -+ reg = <0>; -+ rcar_dw_hdmi1_in: endpoint { -+ remote-endpoint = <&du_out_hdmi1>; ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; + }; + }; + port@1 { -+ reg = <1>; -+ rcar_dw_hdmi1_out: endpoint { -+ remote-endpoint = <&hdmi1_con>; ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; + }; + }; + }; +}; + -+&pfc { -+ scif1_pins: scif1 { -+ groups = "scif1_data_a"; -+ function = "scif1"; -+ }; -+ -+ msiof0_pins: spi1 { -+ groups = "msiof0_clk", "msiof0_rxd", "msiof0_txd", -+ "msiof0_ss1"; -+ function = "msiof0"; -+ }; -+ -+ msiof1_pins: spi2 { -+ groups = "msiof1_clk_a", "msiof1_rxd_a", "msiof1_txd_a", -+ "msiof1_ss1_a"; -+ function = "msiof1"; -+ }; -+ -+ sound_clk_pins: sound-clk { -+ groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", -+ "audio_clkout_a" /*, "audio_clkout3_a"*/; -+ function = "audio_clk"; -+ }; -+ -+ usb31_pins: usb31 { -+ groups = "usb31"; -+ function = "usb31"; -+ }; -+ -+ can0_pins: can0 { -+ groups = "can0_data_a"; -+ function = "can0"; -+ }; -+ -+ canfd0_pins: canfd0 { -+ groups = "canfd0_data_a"; -+ function = "canfd0"; -+ }; -+}; -+ -+&scif1 { -+ pinctrl-0 = <&scif1_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; -+ -+&avb { -+ /delete-property/phy-handle; -+ /delete-property/phy-gpios; -+ /delete-node/ethernet-phy@0; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+}; -+ -+&msiof0 { -+ pinctrl-0 = <&msiof0_pins>; -+ pinctrl-names = "default"; -+ status = "disabled"; -+ cs-gpios = <&gpio5 19 0>; -+ -+ spidev@0 { -+ compatible = "renesas,sh-msiof"; -+ reg = <0>; -+ spi-max-frequency = <66666666>; -+ spi-cpha; -+ spi-cpol; -+ }; -+}; -+ -+&msiof1 { -+ status = "disabled"; -+ cs-gpios = <&gpio6 5 0>; -+}; -+ -+&can0 { -+ pinctrl-0 = <&can0_pins>; -+ pinctrl-names = "default"; -+ status = "disabled"; -+ -+ renesas,can-clock-select = <0x0>; -+ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH /* enable - shared with camera board */ -+ &gpio2 7 GPIO_ACTIVE_LOW /* standby */ -+ >; -+}; -+ -+&canfd { -+ pinctrl-0 = <&canfd0_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ renesas,can-clock-select = <0x0>; -+ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH /* enable - shared with camera board */ -+ &gpio2 7 GPIO_ACTIVE_LOW /* standby */ -+ >; -+ -+ channel0 { -+ status = "okay"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts -new file mode 100644 -index 0000000..4fe67f8 ---- /dev/null -+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts -@@ -0,0 +1,39 @@ -+/* -+ * Device Tree Source for the H3ULCB Kingfisher board on r8a7795 -+ * -+ * Copyright (C) 2017 Renesas Electronics Corp. -+ * Copyright (C) 2017 Cogent Embedded, Inc. -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ -+ -+#include "r8a7795-h3ulcb.dts" -+#include "ulcb-kf.dtsi" ++&vin2 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+/ { -+ model = "Renesas H3ULCB Kingfisher board based on r8a7795"; ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ }; ++ }; +}; + -+&du { ++&vin3 { + ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ + port@0 { -+ endpoint { -+ remote-endpoint = <&adv7513_in>; ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; + }; + }; -+ port@3 { -+ endpoint { -+ remote-endpoint = <&lvds_enc_in>; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; + }; + }; + }; +}; + -+&hsusb0 { -+ status = "okay"; -+}; ++&vin4 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+/* use CN11 instead default CN29/CN48 (H3 only) */ -+//#include "ulcb-kf-cn11.dtsi" -diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb.dts -new file mode 100644 -index 0000000..98b6a08 ---- /dev/null -+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb.dts -@@ -0,0 +1,1787 @@ -+/* -+ * Device Tree Source for the H3ULCB Videobox board -+ * -+ * Copyright (C) 2017 Renesas Electronics Corp. -+ * Copyright (C) 2017 Cogent Embedded, Inc. -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi41"; ++ virtual,channel = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin4_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ }; ++ }; ++}; + -+#include "r8a7795-h3ulcb.dts" ++&vin5 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+/ { -+ model = "Renesas H3ULCB Videobox board based on r8a7795"; ++ port@0 { ++ vin5ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep1: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin5_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ }; ++ }; ++}; + -+ leds { -+ compatible = "gpio-leds"; ++&vin6 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ led5 { -+ gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; ++ port@0 { ++ vin6ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <2>; ++ remote-endpoint = <&ov106xx_in6>; ++ data-lanes = <1 2 3 4>; ++ }; + }; -+ led6 { -+ gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; ++ port@1 { ++ csi2ep2: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; + }; -+ /* D13 - status 0 */ -+ led_ext00 { -+ gpios = <&gpio_ext_led 0 GPIO_ACTIVE_LOW>; -+ /* linux,default-trigger = "heartbeat"; */ ++ port@2 { ++ vin6_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; + }; -+ /* D14 - status 1 */ -+ led_ext01 { -+ gpios = <&gpio_ext_led 1 GPIO_ACTIVE_LOW>; -+ /* linux,default-trigger = "mmc1"; */ ++ }; ++}; ++ ++&vin7 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin7ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <3>; ++ remote-endpoint = <&ov106xx_in7>; ++ data-lanes = <1 2 3 4>; ++ }; + }; -+ /* D16 - HDMI1 */ -+ led_ext02 { -+ gpios = <&gpio_ext_led 2 GPIO_ACTIVE_LOW>; ++ port@1 { ++ csi2ep3: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; + }; -+ /* D18 - HDMI0 */ -+ led_ext03 { -+ gpios = <&gpio_ext_led 3 GPIO_ACTIVE_LOW>; ++ port@2 { ++ vin7_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; + }; -+ /* D20 - USB3.0 - 0.1 */ -+ led_ext04 { -+ gpios = <&gpio_ext_led 4 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&csi2_20 { ++ status = "disabled"; ++ /delete-node/ports; ++}; ++ ++&csi2_40 { ++ /delete-node/ports; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; + }; -+ /* D21 - USB3.0 - 0.2 */ -+ led_ext05 { -+ gpios = <&gpio_ext_led 5 GPIO_ACTIVE_LOW>; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; + }; -+ /* D24 - USB3.0 - 1.1 */ -+ led6_ext06 { -+ gpios = <&gpio_ext_led 6 GPIO_ACTIVE_LOW>; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; + }; -+ /* D25 - USB3.0 - 1.2 */ -+ led_ext07 { -+ gpios = <&gpio_ext_led 7 GPIO_ACTIVE_LOW>; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; + }; + }; + -+ snd_clk: snd_clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24576000>; -+ clock-output-names = "scki"; -+ }; -+ -+ vccq_sdhi3: regulator@5 { -+ compatible = "regulator-fixed"; ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ regulator-name = "SDHI3 VccQ"; -+ /* external voltage translator to 1.8V */ -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; + }; ++}; + -+ fpdlink_switch: regulator@8 { -+ compatible = "regulator-fixed"; -+ regulator-name = "fpdlink_on"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio1 20 0>; -+ enable-active-high; -+ regulator-always-on; -+ }; ++&csi2_41 { ++ status = "okay"; + -+ hub_reset: regulator@9 { -+ compatible = "regulator-fixed"; -+ regulator-name = "hub_reset"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio5 5 0>; -+ enable-active-high; -+ regulator-always-on; ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; + }; + -+ hub_power: regulator@10 { -+ compatible = "regulator-fixed"; -+ regulator-name = "hub_power"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio6 28 0>; -+ enable-active-high; -+ regulator-always-on; -+ }; ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ /delete-node/sound; ++ csi2_41_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; + -+ rsnd_ak4613: sound@0 { -+ pinctrl-0 = <&sound_0_pins>; -+ pinctrl-names = "default"; -+ compatible = "simple-audio-card"; ++&can0 { ++ pinctrl-0 = <&can0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; + -+ simple-audio-card,format = "left_j"; -+ simple-audio-card,name = "ak4613"; ++&can1 { ++ pinctrl-0 = <&can1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-alfa.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-alfa.dts +new file mode 100644 +index 0000000..ae115bd +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-alfa.dts +@@ -0,0 +1,22 @@ ++/* ++ * Device Tree Source for the H3ULCB.HAD board Alfa side ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ + -+ simple-audio-card,bitclock-master = <&sndcpu>; -+ simple-audio-card,frame-master = <&sndcpu>; ++#include "r8a7795-h3ulcb-had.dtsi" + -+ sndcpu: simple-audio-card,cpu@1 { -+ sound-dai = <&rcar_sound>; -+ }; ++/ { ++ model = "Renesas H3ULCB.HAD board Alfa side based on r8a7795"; ++}; + -+ sndcodec: simple-audio-card,codec@1 { -+ sound-dai = <&ak4613>; -+ }; -+ }; ++&pciec0 { ++ status = "okay"; + -+ lvds-encoder { -+ compatible = "thine,thc63lvdm83d"; ++ /* Root complex */ ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-beta.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-beta.dts +new file mode 100644 +index 0000000..805067e +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had-beta.dts +@@ -0,0 +1,23 @@ ++/* ++ * Device Tree Source for the H3ULCB.HAD board Beta side ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ + -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ port@0 { -+ reg = <0>; -+ lvds_enc_in: endpoint { -+ remote-endpoint = <&du_out_lvds0>; -+ }; -+ }; -+ port@1 { -+ reg = <1>; -+ lvds_enc_out: endpoint { -+ remote-endpoint = <&lvds_in>; -+ }; -+ }; -+ }; -+ }; ++#include "r8a7795-h3ulcb-had.dtsi" + -+ lvds { -+ compatible = "lvds-connector"; ++/ { ++ model = "Renesas H3ULCB.HAD board Beta side based on r8a7795"; ++}; + -+ width-mm = <210>; -+ height-mm = <158>; ++&pciec0 { ++ status = "okay"; + -+ panel-timing { -+ /* 1280x800 @60Hz */ -+ clock-frequency = <65000000>; -+ hactive = <1280>; -+ vactive = <800>; -+ hsync-len = <40>; -+ hfront-porch = <80>; -+ hback-porch = <40>; -+ vfront-porch = <14>; -+ vback-porch = <14>; -+ vsync-len = <4>; -+ }; ++ /* Endpoint */ ++ endpoint; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi +new file mode 100644 +index 0000000..4a00426 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi +@@ -0,0 +1,219 @@ ++/* ++ * Device Tree Source for the H3ULCB.HAD board on r8a7795 ++ * ++ * Copyright (C) 2016-2017 Renesas Electronics Corp. ++ * Copyright (C) 2016-2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ + -+ port { -+ lvds_in: endpoint { -+ remote-endpoint = <&lvds_enc_out>; -+ }; -+ }; -+ }; ++/* ++ * MSIOF0 - /dev/spidev1.0 connected to FPGA ethernet switch (both sides) ++ * MSIOF1 - /dev/spidev2.0 connected to RH850 (sideA to CSIH1, sideB to CSIH0) ++ */ + -+ hdmi1-out { -+ compatible = "hdmi-connector"; -+ type = "a"; ++#include "r8a7795-h3ulcb-view.dts" + -+ port { -+ hdmi1_con: endpoint { -+ remote-endpoint = <&rcar_dw_hdmi1_out>; -+ }; -+ }; -+ }; ++/ { ++ model = "Renesas H3ULCB.HAD board based on r8a7795"; + -+ excan_ref_clk: excan-ref-clock { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <16000000>; ++ aliases { ++ serial1 = &scif1; ++ spi1 = &spi0_gpio; ++ spi2 = &spi1_gpio; + }; + -+ radio: si468x@0 { -+ compatible = "si,si468x-pcm"; -+ status = "okay"; -+ -+ #sound-dai-cells = <0>; ++ chosen { ++ stdout-path = "serial1:115200n8"; + }; + -+ spi_gpio_sw { ++ spi0_gpio: spi_gpio@0 { + compatible = "spi-gpio"; -+ #address-cells = <0x1>; -+ #size-cells = <0x0>; -+ gpio-sck = <&gpio0 8 GPIO_ACTIVE_HIGH>; -+ gpio-miso = <&gpio0 10 GPIO_ACTIVE_HIGH>; -+ gpio-mosi = <&gpio0 11 GPIO_ACTIVE_HIGH>; -+ cs-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; ++ gpio-sck = <&gpio5 17 0>; ++ gpio-mosi = <&gpio5 20 0>; ++ gpio-miso = <&gpio5 22 0>; ++ cs-gpios = <&gpio5 19 0>; ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ spidev: spidev@0 { -+ compatible = "spidev", "spi-gpio"; ++ spidev@0 { ++ compatible = "spi-gpio"; + reg = <0>; -+ spi-max-frequency = <25000000>; ++ spi-max-frequency = <2000000>; + spi-cpha; + spi-cpol; + }; + }; + -+ spi_gpio_can { ++ spi1_gpio: spi_gpio@1 { + compatible = "spi-gpio"; -+ #address-cells = <0x1>; -+ #size-cells = <0x0>; -+ gpio-sck = <&gpio1 2 GPIO_ACTIVE_HIGH>; -+ gpio-miso = <&gpio1 3 GPIO_ACTIVE_HIGH>; -+ gpio-mosi = <&gpio1 1 GPIO_ACTIVE_HIGH>; -+ cs-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH -+ &gpio1 4 GPIO_ACTIVE_HIGH>; -+ num-chipselects = <2>; ++ num-chipselects = <1>; ++ gpio-sck = <&gpio6 8 0>; ++ gpio-mosi = <&gpio6 7 0>; ++ gpio-miso = <&gpio6 10 0>; ++ cs-gpios = <&gpio6 5 0>; ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ spican0: spidev@0 { -+ compatible = "microchip,mcp2515"; ++ spidev@0 { ++ compatible = "spi-gpio"; + reg = <0>; -+ clocks = <&excan_ref_clk>; -+ interrupt-parent = <&gpio0>; -+ interrupts = <15 GPIO_ACTIVE_LOW>; -+ spi-max-frequency = <10000000>; ++ spi-max-frequency = <2000000>; ++ spi-cpha; ++ spi-cpol; + }; -+ spican1: spidev@1 { -+ compatible = "microchip,mcp2515"; -+ reg = <1>; -+ clocks = <&excan_ref_clk>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <5 GPIO_ACTIVE_LOW>; -+ spi-max-frequency = <10000000>; ++ }; ++ ++ hdmi1-out { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con: endpoint { ++ remote-endpoint = <&rcar_dw_hdmi1_out>; ++ }; + }; + }; +}; @@ -10211,12 +8098,7 @@ index 0000000..98b6a08 + }; + port@2 { + endpoint { -+ remote-endpoint = <&rcar_dw_hdmi1_in>; -+ }; -+ }; -+ port@3 { -+ endpoint { -+ remote-endpoint = <&lvds_enc_in>; ++ remote-endpoint = <&rcar_dw_hdmi1_in>; + }; + }; + }; @@ -10230,13 +8112,13 @@ index 0000000..98b6a08 + #size-cells = <0>; + port@0 { + reg = <0>; -+ rcar_dw_hdmi1_in: endpoint { ++ rcar_dw_hdmi1_in: endpoint { + remote-endpoint = <&du_out_hdmi1>; + }; + }; + port@1 { + reg = <1>; -+ rcar_dw_hdmi1_out: endpoint { ++ rcar_dw_hdmi1_out: endpoint { + remote-endpoint = <&hdmi1_con>; + }; + }; @@ -10244,27 +8126,32 @@ index 0000000..98b6a08 +}; + +&pfc { -+ hscif4_pins: hscif4 { -+ groups = "hscif4_data_a", "hscif4_ctrl"; -+ function = "hscif4"; ++ scif1_pins: scif1 { ++ groups = "scif1_data_a"; ++ function = "scif1"; + }; + -+ sdhi3_pins_3v3: sd3_3v3 { -+ groups = "sdhi3_data4", "sdhi3_ctrl"; -+ function = "sdhi3"; -+ power-source = <3300>; ++ msiof0_pins: spi1 { ++ groups = "msiof0_clk", "msiof0_rxd", "msiof0_txd", ++ "msiof0_ss1"; ++ function = "msiof0"; + }; + -+ /delete-node/sound; ++ msiof1_pins: spi2 { ++ groups = "msiof1_clk_a", "msiof1_rxd_a", "msiof1_txd_a", ++ "msiof1_ss1_a"; ++ function = "msiof1"; ++ }; + -+ sound_0_pins: sound1 { -+ groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; -+ function = "ssi"; ++ sound_clk_pins: sound-clk { ++ groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", ++ "audio_clkout_a" /*, "audio_clkout3_a"*/; ++ function = "audio_clk"; + }; + -+ usb0_pins: usb0 { -+ groups = "usb0"; -+ function = "usb0"; ++ usb31_pins: usb31 { ++ groups = "usb31"; ++ function = "usb31"; + }; + + can0_pins: can0 { @@ -10272,1060 +8159,1044 @@ index 0000000..98b6a08 + function = "can0"; + }; + -+ can1_pins: can1 { -+ groups = "can1_data"; -+ function = "can1"; -+ }; -+ + canfd0_pins: canfd0 { + groups = "canfd0_data_a"; + function = "canfd0"; + }; ++}; + -+ canfd1_pins: canfd1 { -+ groups = "canfd1_data"; -+ function = "canfd1"; -+ }; ++&scif1 { ++ pinctrl-0 = <&scif1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; +}; + -+&gpio0 { -+ video_a_irq { -+ gpio-hog; -+ gpios = <12 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A irq"; -+ }; ++&avb { ++ /delete-property/phy-handle; ++ /delete-property/phy-gpios; ++ /delete-node/ethernet-phy@0; + -+ video_b_irq { -+ gpio-hog; -+ gpios = <13 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-B irq"; ++ fixed-link { ++ speed = <1000>; ++ full-duplex; + }; ++}; + -+ video_c_irq { -+ gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-C irq"; ++&msiof0 { ++ pinctrl-0 = <&msiof0_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ cs-gpios = <&gpio5 19 0>; ++ ++ spidev@0 { ++ compatible = "renesas,sh-msiof"; ++ reg = <0>; ++ spi-max-frequency = <66666666>; ++ spi-cpha; ++ spi-cpol; + }; +}; + -+&gpio1 { -+ gpioext_4_22_irq { -+ gpio-hog; -+ gpios = <25 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "0x22@i2c4 irq"; -+ }; -+ pcie_disable { -+ gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "mPCIe W_DISABLE"; -+ }; -+ m2_sleep { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "M.2 SLEEP#"; -+ }; -+ m2_pres { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "M.2 Present"; -+ }; -+ m2_pcie_det { -+ gpio-hog; -+ gpios = <18 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "M.2 PCIe detected"; ++&msiof1 { ++ status = "disabled"; ++ cs-gpios = <&gpio6 5 0>; ++}; ++ ++&can0 { ++ pinctrl-0 = <&can0_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ ++ renesas,can-clock-select = <0x0>; ++ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH /* enable - shared with camera board */ ++ &gpio2 7 GPIO_ACTIVE_LOW /* standby */ ++ >; ++}; ++ ++&canfd { ++ pinctrl-0 = <&canfd0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; ++ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH /* enable - shared with camera board */ ++ &gpio2 7 GPIO_ACTIVE_LOW /* standby */ ++ >; ++ ++ channel0 { ++ status = "okay"; + }; -+ m2_usb_det { -+ gpio-hog; -+ gpios = <19 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "M.2 USB30 detected"; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts +new file mode 100644 +index 0000000..4fe67f8 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts +@@ -0,0 +1,39 @@ ++/* ++ * Device Tree Source for the H3ULCB Kingfisher board on r8a7795 ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7795-h3ulcb.dts" ++#include "ulcb-kf.dtsi" ++ ++/ { ++ model = "Renesas H3ULCB Kingfisher board based on r8a7795"; ++}; ++ ++&du { ++ ports { ++ port@0 { ++ endpoint { ++ remote-endpoint = <&adv7513_in>; ++ }; ++ }; ++ port@3 { ++ endpoint { ++ remote-endpoint = <&lvds_enc_in>; ++ }; ++ }; + }; -+ m2_usb_det { -+ gpio-hog; -+ gpios = <27 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "M.2 SSD detected"; ++}; ++ ++&hsusb0 { ++ status = "okay"; ++}; ++ ++/* use CN11 instead default CN29/CN48 (H3 only) */ ++//#include "ulcb-kf-cn11.dtsi" +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb.dts +new file mode 100644 +index 0000000..330bba2 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb.dts +@@ -0,0 +1,68 @@ ++/* ++ * Device Tree Source for the H3ULCB Videobox board on r8a7795 ++ * ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7795-h3ulcb.dts" ++#include "ulcb-vb.dtsi" ++ ++/ { ++ model = "Renesas H3ULCB Videobox board based on r8a7795"; ++ ++ hdmi1-out { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con: endpoint { ++ remote-endpoint = <&rcar_dw_hdmi1_out>; ++ }; ++ }; + }; -+ eth_phy_reset { -+ gpio-hog; -+ gpios = <16 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "BR phy reset"; ++}; ++ ++&du { ++ ports { ++ port@2 { ++ endpoint { ++ remote-endpoint = <&rcar_dw_hdmi1_in>; ++ }; ++ }; ++ port@3 { ++ endpoint { ++ remote-endpoint = <&lvds_enc_in>; ++ }; ++ }; + }; -+ eth_sw_reset { -+ gpio-hog; -+ gpios = <17 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "BR switch reset"; ++}; ++ ++&hdmi1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ rcar_dw_hdmi1_in: endpoint { ++ remote-endpoint = <&du_out_hdmi1>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ rcar_dw_hdmi1_out: endpoint { ++ remote-endpoint = <&hdmi1_con>; ++ }; ++ }; + }; +}; + -+&gpio2 { -+ m2_wake { -+ gpio-hog; -+ gpios = <1 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "M.2 WAKE#"; -+ }; -+ m2_pcie_en { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "M.2 PCIe enable"; -+ }; ++&hsusb0 { ++ status = "okay"; +}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vbm.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vbm.dts +new file mode 100644 +index 0000000..87f1889 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vbm.dts +@@ -0,0 +1,26 @@ ++/* ++ * Device Tree Source for the H3ULCB Videobox Mini board on r8a7795 ES1.x ++ * ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ + -+&gpio3 { -+ m2_power_off { -+ gpio-hog; -+ gpios = <15 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "M.2 FULL_CARD_POWER_OFF#"; -+ }; ++#include "r8a7795-h3ulcb.dts" ++#include "ulcb-vbm.dtsi" ++ ++/ { ++ model = "Renesas H3ULCB Videobox Mini board based on r8a7795"; +}; + -+&gpio6 { -+ pcie_wake { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "mPCIe WAKE#"; -+ }; -+ pcie_clkreq { -+ gpio-hog; -+ gpios = <10 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "mPCIe CLKREQ#"; -+ }; -+ m2_rst { -+ gpio-hog; -+ gpios = <21 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "M.2 RESET#"; ++&du { ++ ports { ++ port@3 { ++ endpoint { ++ remote-endpoint = <&lvds_enc_in>; ++ }; ++ }; + }; +}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts +new file mode 100644 +index 0000000..2c24b85 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts +@@ -0,0 +1,546 @@ ++/* ++ * Device Tree Source for the H3ULCB.View board ++ * ++ * Copyright (C) 2016-2017 Renesas Electronics Corp. ++ * Copyright (C) 2016-2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ + -+&hscif4 { -+ pinctrl-0 = <&hscif4_pins>; -+ pinctrl-names = "default"; -+ uart-has-rtscts; ++#include "r8a7795-h3ulcb.dts" + -+ status = "okay"; ++/ { ++ model = "Renesas H3ULCB.View board based on r8a7795"; +}; + -+&i2c2 { -+ clock-frequency = <400000>; ++&i2c4 { ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; + -+ i2cswitch2: pca9548@74 { -+ compatible = "nxp,pca9548"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x74>; -+ reset-gpios = <&gpio6 5 GPIO_ACTIVE_LOW>; ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ }; ++ }; + -+ i2c@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ /* USB3.0 HUB node(s) */ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; ++ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; + }; ++ }; + -+ i2c@6 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <6>; -+ /* PCIe node(s) */ ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; ++ ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; + }; ++ }; + -+ i2c@7 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <7>; -+ /* Slot A (CN10) */ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; + -+ ov106xx@0 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x60>; ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_des0ep3: endpoint { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; ++ }; + -+ port@0 { -+ ov106xx_in0: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin0ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep0>; -+ }; -+ ov106xx_ti964_des0ep0: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep0>; -+ }; -+ ov106xx_ti954_des0ep0: endpoint@2 { -+ remote-endpoint = <&ti954_des0ep0>; -+ }; -+ }; ++ ov106xx@4 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x64>; ++ ++ port@0 { ++ ov106xx_in4: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin4ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; + }; ++ }; ++ }; + -+ ov106xx@1 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x61>; ++ ov106xx@5 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x65>; + -+ port@0 { -+ ov106xx_in1: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin1ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep1>; -+ }; -+ ov106xx_ti964_des0ep1: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep1>; -+ }; -+ ov106xx_ti954_des0ep1: endpoint@2 { -+ remote-endpoint = <&ti954_des0ep1>; -+ }; -+ }; ++ port@0 { ++ ov106xx_in5: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin5ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; + }; ++ }; ++ }; + -+ ov106xx@2 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x62>; ++ ov106xx@6 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x66>; + -+ port@0 { -+ ov106xx_in2: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin2ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep2>; -+ }; -+ ov106xx_ti964_des0ep2: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep2>; -+ }; -+ }; ++ port@0 { ++ ov106xx_in6: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin6ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; + }; ++ }; ++ }; + -+ ov106xx@3 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x63>; ++ ov106xx@7 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x67>; + -+ port@0 { -+ ov106xx_in3: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin3ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep3>; -+ }; -+ ov106xx_ti964_des0ep3: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep3>; -+ }; -+ }; ++ port@0 { ++ ov106xx_in7: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin7ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_des1ep3: endpoint { ++ remote-endpoint = <&max9286_des1ep3>; + }; ++ }; ++ }; + -+ /* DS90UB964 @ 0x3a */ -+ ti964-ti9x3@0 { -+ compatible = "ti,ti964-ti9x3"; -+ reg = <0x3a>; -+ ti,sensor_delay = <350>; -+ ti,links = <4>; -+ ti,lanes = <4>; -+ ti,forwarding-mode = "round-robin"; -+ ti,cable-mode = "stp"; ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x4c>; ++ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; ++ maxim,sensor_delay = <0>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ maxim,i2c-quirk = <0x6c>; + -+ port@0 { -+ ti964_des0ep0: endpoint@0 { -+ ti9x3-addr = <0x0c>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ ti964_des0ep1: endpoint@1 { -+ ti9x3-addr = <0x0d>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ ti964_des0ep2: endpoint@2 { -+ ti9x3-addr = <0x0e>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in2>; -+ }; -+ ti964_des0ep3: endpoint@3 { -+ ti9x3-addr = <0x0f>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in3>; -+ }; -+ }; -+ port@1 { -+ ti964_csi0ep0: endpoint { -+ csi-rate = <1450>; -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; + }; ++ }; ++ }; + -+ /* DS90UB954 @ 0x38 */ -+ ti954-ti9x3@0 { -+ compatible = "ti,ti954-ti9x3"; -+ reg = <0x38>; -+ /* gpios = <&video_a_ext1 10 GPIO_ACTIVE_HIGH>; */ -+ ti,sensor_delay = <350>; -+ ti,links = <2>; -+ ti,lanes = <4>; -+ ti,forwarding-mode = "round-robin"; -+ ti,cable-mode = "stp"; ++ max9286-max9271@1 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x6c>; ++ gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; ++ maxim,sensor_delay = <0>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; + -+ port@0 { -+ ti954_des0ep0: endpoint@0 { -+ ti9x3-addr = <0x0c>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ ti954_des0ep1: endpoint@1 { -+ ti9x3-addr = <0x0d>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ }; -+ port@1 { -+ ti954_csi0ep0: endpoint { -+ csi-rate = <1450>; -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; ++ port@0 { ++ max9286_des1ep0: endpoint@0 { ++ max9271-addr = <0x54>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in4>; + }; ++ max9286_des1ep1: endpoint@1 { ++ max9271-addr = <0x55>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ max9286_des1ep2: endpoint@2 { ++ max9271-addr = <0x56>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ max9286_des1ep3: endpoint@3 { ++ max9271-addr = <0x57>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ max9286_csi2ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++}; + -+ /* MAX9286 @ 0x2c */ -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; -+ reg = <0x2c>; -+ maxim,sensor_delay = <350>; -+ maxim,links = <4>; -+ maxim,lanes = <4>; -+ maxim,resetb-gpio = <1>; -+ maxim,fsync-mode = "automatic"; -+ maxim,timeout = <100>; -+ -+ port@0 { -+ max9286_des0ep0: endpoint@0 { -+ max9271-addr = <0x50>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ max9286_des0ep1: endpoint@1 { -+ max9271-addr = <0x51>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ max9286_des0ep2: endpoint@2 { -+ max9271-addr = <0x52>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in2>; -+ }; -+ max9286_des0ep3: endpoint@3 { -+ max9271-addr = <0x53>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in3>; -+ }; -+ }; -+ port@1 { -+ max9286_csi0ep0: endpoint { -+ csi-rate = <700>; -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; ++&pcie_bus_clk { ++ clock-frequency = <100000000>; ++ status = "okay"; ++}; ++ ++&pciec1 { ++ status = "okay"; ++}; ++ ++&vin0 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; + }; + }; ++ }; ++}; + -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <2>; -+ /* Slot B (CN11) */ ++&vin1 { ++ status = "okay"; + -+ ov106xx@4 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x64>; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ port@0 { -+ ov106xx_in4: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin4ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep0>; -+ }; -+ ov106xx_ti964_des1ep0: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep0>; -+ }; -+ ov106xx_ti954_des1ep0: endpoint@2 { -+ remote-endpoint = <&ti954_des1ep0>; -+ }; -+ }; ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; + }; ++ }; ++ }; ++}; + -+ ov106xx@5 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x65>; ++&vin2 { ++ status = "okay"; + -+ port@0 { -+ ov106xx_in5: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin5ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep1>; -+ }; -+ ov106xx_ti964_des1ep1: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep1>; -+ }; -+ ov106xx_ti954_des1ep1: endpoint@2 { -+ remote-endpoint = <&ti954_des1ep1>; -+ }; -+ }; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; + }; ++ }; ++ }; ++}; + -+ ov106xx@6 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x66>; ++&vin3 { ++ status = "okay"; + -+ port@0 { -+ ov106xx_in6: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin6ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep2>; -+ }; -+ ov106xx_ti964_des1ep2: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep2>; -+ }; -+ }; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; + }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; ++ }; ++}; + -+ ov106xx@7 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x67>; ++&vin4 { ++ status = "okay"; + -+ port@0 { -+ ov106xx_in7: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin7ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep3>; -+ }; -+ ov106xx_ti964_des1ep3: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep3>; -+ }; -+ }; -+ }; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ /* DS90UB964 @ 0x3a */ -+ ti964-ti9x3@1 { -+ compatible = "ti,ti964-ti9x3"; -+ reg = <0x3a>; -+ ti,sensor_delay = <350>; -+ ti,links = <4>; -+ ti,lanes = <4>; -+ ti,forwarding-mode = "round-robin"; -+ ti,cable-mode = "stp"; ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi41"; ++ virtual,channel = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin4_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ }; ++ }; ++}; + -+ port@0 { -+ ti964_des1ep0: endpoint@0 { -+ ti9x3-addr = <0x0c>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in4>; -+ }; -+ ti964_des1ep1: endpoint@1 { -+ ti9x3-addr = <0x0d>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in5>; -+ }; -+ ti964_des1ep2: endpoint@2 { -+ ti9x3-addr = <0x0e>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in6>; -+ }; -+ ti964_des1ep3: endpoint@3 { -+ ti9x3-addr = <0x0f>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in7>; -+ }; -+ }; -+ port@1 { -+ ti964_csi2ep0: endpoint { -+ csi-rate = <1450>; -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; ++&vin5 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin5ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep1: endpoint { ++ remote-endpoint = <&csi2_41_ep>; + }; ++ }; ++ port@2 { ++ vin5_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ }; ++ }; ++}; + -+ /* DS90UB954 @ 0x38 */ -+ ti954-ti9x3@1 { -+ compatible = "ti,ti954-ti9x3"; -+ reg = <0x38>; -+ /* gpios = <&video_b_ext1 10 GPIO_ACTIVE_HIGH>; */ -+ ti,sensor_delay = <350>; -+ ti,links = <2>; -+ ti,lanes = <4>; -+ ti,forwarding-mode = "round-robin"; -+ ti,cable-mode = "stp"; ++&vin6 { ++ status = "okay"; + -+ port@0 { -+ ti954_des1ep0: endpoint@0 { -+ ti9x3-addr = <0x0c>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in4>; -+ }; -+ ti954_des1ep1: endpoint@1 { -+ ti9x3-addr = <0x0d>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in5>; -+ }; -+ }; -+ port@1 { -+ ti954_csi2ep0: endpoint { -+ csi-rate = <1450>; -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin6ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <2>; ++ remote-endpoint = <&ov106xx_in6>; ++ data-lanes = <1 2 3 4>; + }; ++ }; ++ port@1 { ++ csi2ep2: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin6_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ }; ++ }; ++}; + -+ /* MAX9286 @ 0x2c */ -+ max9286-max9271@1 { -+ compatible = "maxim,max9286-max9271"; -+ reg = <0x2c>; -+ maxim,sensor_delay = <350>; -+ maxim,links = <4>; -+ maxim,lanes = <4>; -+ maxim,resetb-gpio = <1>; -+ maxim,fsync-mode = "automatic"; -+ maxim,timeout = <100>; ++&vin7 { ++ status = "okay"; + -+ port@0 { -+ max9286_des1ep0: endpoint@0 { -+ max9271-addr = <0x50>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in4>; -+ }; -+ max9286_des1ep1: endpoint@1 { -+ max9271-addr = <0x51>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in5>; -+ }; -+ max9286_des1ep2: endpoint@2 { -+ max9271-addr = <0x52>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in6>; -+ }; -+ max9286_des1ep3: endpoint@3 { -+ max9271-addr = <0x53>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in7>; -+ }; -+ }; -+ port@1 { -+ max9286_csi2ep0: endpoint { -+ csi-rate = <700>; -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin7ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <3>; ++ remote-endpoint = <&ov106xx_in7>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep3: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin7_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; + }; + }; ++ }; ++}; + -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <3>; -+ /* Slot C (CN12) */ ++&csi2_40 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; + }; ++ }; + -+ i2c@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ /* Slot A (CN10) */ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ video_a_ext0: pca9535@26 { -+ compatible = "nxp,pca9535"; -+ reg = <0x26>; -+ gpio-controller; -+ #gpio-cells = <2>; ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; + -+ video_a_des_cfg1 { -+ gpio-hog; -+ gpios = <5 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A cfg1"; -+ }; -+ video_a_des_cfg0 { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A cfg0"; -+ }; -+ video_a_pwr_shdn { -+ gpio-hog; -+ gpios = <3 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR_SHDN"; -+ }; -+ video_a_cam_pwr0 { -+ gpio-hog; -+ gpios = <12 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR0"; -+ }; -+ video_a_cam_pwr1 { -+ gpio-hog; -+ gpios = <13 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR1"; -+ }; -+ video_a_cam_pwr2 { -+ gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR2"; -+ }; -+ video_a_cam_pwr3 { -+ gpio-hog; -+ gpios = <15 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR3"; -+ }; -+ video_a_des_shdn { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A DES_SHDN"; -+ }; -+ video_a_des_led { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "Video-A led"; -+ }; -+ }; ++&csi2_41 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; + -+ video_a_ext1: max7325@5c { -+ compatible = "maxim,max7325"; -+ reg = <0x5c>; -+ gpio-controller; -+ #gpio-cells = <2>; ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ video_a_des_cfg2 { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A cfg2"; -+ }; -+ video_a_des_cfg1 { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A cfg1"; -+ }; -+ video_a_des_cfg0 { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A cfg0"; -+ }; -+ video_a_pwr_shdn { -+ gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR_SHDN"; -+ }; -+ video_a_cam_pwr0 { -+ gpio-hog; -+ gpios = <8 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR0"; -+ }; -+ video_a_cam_pwr1 { -+ gpio-hog; -+ gpios = <9 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR1"; -+ }; -+ video_a_cam_pwr2 { -+ gpio-hog; -+ gpios = <10 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR2"; -+ }; -+ video_a_cam_pwr3 { -+ gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR3"; -+ }; -+ video_a_des_shdn { -+ gpio-hog; -+ gpios = <13 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A DES_SHDN"; -+ }; -+ video_a_led { -+ gpio-hog; -+ gpios = <12 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "Video-A LED"; -+ }; -+ }; ++ csi2_41_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; + }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x-view.dts +new file mode 100644 +index 0000000..fb12a39f3 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x-view.dts +@@ -0,0 +1,552 @@ ++/* ++ * Device Tree Source for the Salvator-X.View board ++ * ++ * Copyright (C) 2016-2017 Renesas Electronics Corp. ++ * Copyright (C) 2015-2017 Cogent Embedded, Inc ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ + -+ i2c@5 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <5>; -+ /* Slot B (CN11) */ ++#include "r8a7795-salvator-x.dts" + -+ video_b_ext0: pca9535@26 { -+ compatible = "nxp,pca9535"; -+ reg = <0x26>; -+ gpio-controller; -+ #gpio-cells = <2>; ++/ { ++ model = "Renesas Salvator-X.View board based on r8a7795"; ++}; + -+ video_b_des_cfg1 { -+ gpio-hog; -+ gpios = <5 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-B cfg1"; -+ }; -+ video_b_des_cfg0 { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-B cfg0"; -+ }; -+ video_b_pwr_shdn { -+ gpio-hog; -+ gpios = <3 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR_SHDN"; -+ }; -+ video_b_cam_pwr0 { -+ gpio-hog; -+ gpios = <12 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR0"; -+ }; -+ video_b_cam_pwr1 { -+ gpio-hog; -+ gpios = <13 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR1"; -+ }; -+ video_b_cam_pwr2 { -+ gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR2"; -+ }; -+ video_b_cam_pwr3 { -+ gpio-hog; -+ gpios = <15 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR3"; -+ }; -+ video_b_des_shdn { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B DES_SHDN"; -+ }; -+ video_b_des_led { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "Video-B led"; -+ }; -+ }; ++&pfc { ++ can0_pins: can0 { ++ groups = "can0_data_a"; ++ function = "can0"; ++ }; + -+ video_b_ext1: max7325@5c { -+ compatible = "maxim,max7325"; -+ reg = <0x5c>; -+ gpio-controller; -+ #gpio-cells = <2>; ++ can1_pins: can1 { ++ groups = "can1_data"; ++ function = "can1"; ++ }; ++}; + -+ video_b_des_cfg2 { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-B cfg2"; -+ }; -+ video_b_des_cfg1 { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-B cfg1"; -+ }; -+ video_b_des_cfg0 { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-B cfg0"; -+ }; -+ video_b_pwr_shdn { -+ gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR_SHDN"; -+ }; -+ video_b_cam_pwr0 { -+ gpio-hog; -+ gpios = <8 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR0"; -+ }; -+ video_b_cam_pwr1 { -+ gpio-hog; -+ gpios = <9 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR1"; -+ }; -+ video_b_cam_pwr2 { -+ gpio-hog; -+ gpios = <10 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR2"; -+ }; -+ video_b_cam_pwr3 { -+ gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR3"; -+ }; -+ video_b_des_shdn { -+ gpio-hog; -+ gpios = <13 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B DES_SHDN"; -+ }; -+ video_b_led { -+ gpio-hog; -+ gpios = <12 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "Video-B LED"; -+ }; ++&i2c4 { ++ /delete-node/hdmi-in@34; ++ /delete-node/composite-in@70; ++ ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; + }; + }; ++ }; + -+ i2c@4 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <4>; -+ /* Slot C (CN12) */ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; ++ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; + }; + }; -+}; + -+&i2c4 { -+ i2cswitch4: pca9548@74 { -+ compatible = "nxp,pca9548"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x74>; -+ reset-gpios= <&gpio5 15 GPIO_ACTIVE_LOW>; ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; + -+ i2c@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ /* FAN node - EMC2103 */ -+ fan_ctrl:ecm2103@2e { -+ compatible = "emc2103"; -+ reg = <0x2e>; ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; + }; + }; ++ }; + -+ i2c@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ /* Power nodes - 2 x TPS544x20 */ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_des0ep3: endpoint { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; + }; ++ }; + -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <2>; -+ /* CAN and power board nodes */ ++ ov106xx@4 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x64>; + -+ gpio_ext_pwr: pca9535@22 { -+ compatible = "nxp,pca9535"; -+ reg = <0x22>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ interrupt-parent = <&gpio1>; -+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>; ++ port@0 { ++ ov106xx_in4: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin4ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ }; ++ }; + -+ /* enable input DCDC after wake-up signal released */ -+ pwr_hold { -+ gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "pwr_hold"; -+ }; ++ ov106xx@5 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x65>; + -+ /* CAN0 */ -+ can0_stby { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "can0_stby"; -+ }; -+ can0_load { -+ gpio-hog; -+ gpios = <0 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "can0_120R_load"; -+ }; -+ /* CAN1 */ -+ can1_stby { -+ gpio-hog; -+ gpios = <5 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "can1_stby"; -+ }; -+ can1_load { -+ gpio-hog; -+ gpios = <1 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "can1_120R_load"; -+ }; -+ /* CAN2 */ -+ can2_stby { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "can2_stby"; -+ }; -+ can2_load { -+ gpio-hog; -+ gpios = <2 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "can2_120R_load"; -+ }; -+ can2_rst { -+ gpio-hog; -+ gpios = <8 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "can2_rst"; -+ }; -+ /* CAN3 */ -+ can3_stby { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "can3_stby"; -+ }; -+ can3_load { -+ gpio-hog; -+ gpios = <3 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "can3_120R_load"; -+ }; -+ can3_rst { -+ gpio-hog; -+ gpios = <9 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "can3_rst"; -+ }; ++ port@0 { ++ ov106xx_in5: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin5ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; + }; + }; ++ }; + -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <3>; -+ /* FPDLink output node - DS90UH947 */ ++ ov106xx@6 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x66>; ++ ++ port@0 { ++ ov106xx_in6: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin6ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@7 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x67>; ++ ++ port@0 { ++ ov106xx_in7: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin7ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_des1ep3: endpoint { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ }; ++ }; ++ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x4c>; ++ gpios = <&gpio6 30 GPIO_ACTIVE_LOW>; ++ maxim,sensor_delay = <0>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ maxim,i2c-quirk = <0x6c>; ++ ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; + }; -+ -+ i2c@4 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <4>; -+ /* BCM switch node */ ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; + }; ++ }; + -+ i2c@5 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <5>; -+ /* LED board node(s) */ -+ -+ gpio_ext_led: pca9535@22 { -+ compatible = "nxp,pca9535"; -+ reg = <0x22>; -+ gpio-controller; -+ #gpio-cells = <2>; ++ max9286-max9271@1 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x6c>; ++ maxim,sensor_delay = <0>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; + -+ /* gpios 0..7 are used for indication LEDs, low-active */ ++ port@0 { ++ max9286_des1ep0: endpoint@0 { ++ max9271-addr = <0x54>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ max9286_des1ep1: endpoint@1 { ++ max9271-addr = <0x55>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ max9286_des1ep2: endpoint@2 { ++ max9271-addr = <0x56>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ max9286_des1ep3: endpoint@3 { ++ max9271-addr = <0x57>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in7>; + }; + }; -+ -+ i2c@6 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <6>; -+ /* M2 connector i2c node(s) */ ++ port@1 { ++ max9286_csi2ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; + }; -+ -+ /* port 7 is not used */ + }; +}; + -+&pcie_bus_clk { -+ clock-frequency = <100000000>; -+ status = "okay"; -+}; -+ -+&pciec0 { -+ status = "okay"; -+}; -+ -+&pciec1 { -+ status = "okay"; -+}; -+ +&vin0 { -+ status = "okay"; -+ + ports { + #address-cells = <1>; + #size-cells = <0>; @@ -11347,19 +9218,11 @@ index 0000000..98b6a08 + vin0_max9286_des0ep0: endpoint@0 { + remote-endpoint = <&max9286_des0ep0>; + }; -+ vin0_ti964_des0ep0: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep0>; -+ }; -+ vin0_ti954_des0ep0: endpoint@2 { -+ remote-endpoint = <&ti954_des0ep0>; -+ }; + }; + }; +}; + +&vin1 { -+ status = "okay"; -+ + ports { + #address-cells = <1>; + #size-cells = <0>; @@ -11381,19 +9244,11 @@ index 0000000..98b6a08 + vin1_max9286_des0ep1: endpoint@0 { + remote-endpoint = <&max9286_des0ep1>; + }; -+ vin1_ti964_des0ep1: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep1>; -+ }; -+ vin1_ti954_des0ep1: endpoint@2 { -+ remote-endpoint = <&ti954_des0ep1>; -+ }; + }; + }; +}; + +&vin2 { -+ status = "okay"; -+ + ports { + #address-cells = <1>; + #size-cells = <0>; @@ -11415,16 +9270,11 @@ index 0000000..98b6a08 + vin2_max9286_des0ep2: endpoint@0 { + remote-endpoint = <&max9286_des0ep2>; + }; -+ vin2_ti964_des0ep2: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep2>; -+ }; + }; + }; +}; + +&vin3 { -+ status = "okay"; -+ + ports { + #address-cells = <1>; + #size-cells = <0>; @@ -11446,16 +9296,11 @@ index 0000000..98b6a08 + vin3_max9286_des0ep3: endpoint@0 { + remote-endpoint = <&max9286_des0ep3>; + }; -+ vin3_ti964_des0ep3: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep3>; -+ }; + }; + }; +}; + +&vin4 { -+ status = "okay"; -+ + ports { + #address-cells = <1>; + #size-cells = <0>; @@ -11477,19 +9322,11 @@ index 0000000..98b6a08 + vin4_max9286_des1ep0: endpoint@0 { + remote-endpoint = <&max9286_des1ep0>; + }; -+ vin4_ti964_des1ep0: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep0>; -+ }; -+ vin4_ti954_des1ep0: endpoint@2 { -+ remote-endpoint = <&ti954_des1ep0>; -+ }; + }; + }; +}; + +&vin5 { -+ status = "okay"; -+ + ports { + #address-cells = <1>; + #size-cells = <0>; @@ -11511,19 +9348,11 @@ index 0000000..98b6a08 + vin5_max9286_des1ep1: endpoint@0 { + remote-endpoint = <&max9286_des1ep1>; + }; -+ vin5_ti964_des1ep1: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep1>; -+ }; -+ vin5_ti954_des1ep1: endpoint@2 { -+ remote-endpoint = <&ti954_des1ep1>; -+ }; + }; + }; +}; + +&vin6 { -+ status = "okay"; -+ + ports { + #address-cells = <1>; + #size-cells = <0>; @@ -11545,16 +9374,11 @@ index 0000000..98b6a08 + vin6_max9286_des1ep2: endpoint@0 { + remote-endpoint = <&max9286_des1ep2>; + }; -+ vin6_ti964_des1ep2: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep2>; -+ }; + }; + }; +}; + +&vin7 { -+ status = "okay"; -+ + ports { + #address-cells = <1>; + #size-cells = <0>; @@ -11576,15 +9400,17 @@ index 0000000..98b6a08 + vin7_max9286_des1ep3: endpoint@0 { + remote-endpoint = <&max9286_des1ep3>; + }; -+ vin7_ti964_des1ep3: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep3>; -+ }; + }; + }; +}; + ++&csi2_20 { ++ status = "disabled"; ++ /delete-node/ports; ++}; ++ +&csi2_40 { -+ status = "okay"; ++ /delete-node/ports; + + virtual,channel { + csi2_vc0 { @@ -11651,103 +9477,71 @@ index 0000000..98b6a08 + }; +}; + -+&rcar_sound { -+ pinctrl-0 = <&sound_clk_pins>; -+ -+ /* Multi DAI */ -+ #sound-dai-cells = <1>; -+}; -+ -+&sata { -+ status = "okay"; -+}; -+ -+&ssi1 { -+ /delete-property/shared-pin; -+}; -+ -+&avb { -+ /delete-property/phy-handle; -+ /delete-property/phy-gpios; -+ phy-mode = "rgmii"; -+ -+ /delete-node/ethernet-phy@0; -+ -+ fixed-link { -+ speed = <100>; -+ full-duplex; -+ }; -+}; -+ -+&msiof1 { -+ status = "disabled"; -+}; -+ -+&usb2_phy0 { -+ pinctrl-0 = <&usb0_pins>; -+ pinctrl-names = "default"; -+ -+ status = "okay"; -+}; -+ -+&xhci0 { -+ status = "okay"; -+}; -+ -+&hsusb0 { -+ status = "okay"; -+}; -+ -+&ehci0 { -+ status = "okay"; -+}; -+ -+&ohci0 { -+ status = "okay"; -+}; -+ +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + status = "okay"; -+ -+ renesas,can-clock-select = <0x0>; +}; + +&can1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + status = "okay"; -+ -+ renesas,can-clock-select = <0x0>; +}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts +new file mode 100644 +index 0000000..a409402 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts +@@ -0,0 +1,40 @@ ++/* ++ * Device Tree Source for the M3ULCB Kingfisher board on r8a7796 ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ + -+&canfd { -+ pinctrl-0 = <&canfd0_pins &canfd1_pins>; -+ pinctrl-names = "default"; -+ status = "disabled"; ++#include "r8a7796-m3ulcb.dts" ++#include "ulcb-kf.dtsi" + -+ renesas,can-clock-select = <0x0>; ++/ { ++ model = "Renesas M3ULCB Kingfisher board based on r8a7796"; ++}; + -+ channel0 { -+ status = "okay"; ++&du { ++ ports { ++ port@0 { ++ endpoint { ++ remote-endpoint = <&adv7513_in>; ++ }; ++ }; ++ port@2 { ++ endpoint { ++ remote-endpoint = <&lvds_enc_in>; ++ }; ++ }; + }; ++}; + -+ channel1 { -+ status = "okay"; -+ }; ++&hsusb { ++ status = "okay"; +}; + -+/* uncomment to enable CN12 on VIN4-7 */ -+//#include "ulcb-vb-cn12.dtsi" -diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts ++&xhci0 { ++ status = "disabled"; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts new file mode 100644 -index 0000000..2c24b85 +index 0000000..1ac0041 --- /dev/null -+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts -@@ -0,0 +1,546 @@ ++++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts +@@ -0,0 +1,287 @@ +/* -+ * Device Tree Source for the H3ULCB.View board ++ * Device Tree Source for the M3ULCB.View board on r8a7796 + * + * Copyright (C) 2016-2017 Renesas Electronics Corp. + * Copyright (C) 2016-2017 Cogent Embedded, Inc. @@ -11757,10 +9551,10 @@ index 0000000..2c24b85 + * kind, whether express or implied. + */ + -+#include "r8a7795-h3ulcb.dts" ++#include "r8a7796-m3ulcb.dts" + +/ { -+ model = "Renesas H3ULCB.View board based on r8a7795"; ++ model = "Renesas M3ULCB.View board based on r8a7796"; +}; + +&i2c4 { @@ -11836,78 +9630,6 @@ index 0000000..2c24b85 + }; + }; + -+ ov106xx@4 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x64>; -+ -+ port@0 { -+ ov106xx_in4: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin4ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep0>; -+ }; -+ }; -+ }; -+ -+ ov106xx@5 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x65>; -+ -+ port@0 { -+ ov106xx_in5: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin5ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep1>; -+ }; -+ }; -+ }; -+ -+ ov106xx@6 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x66>; -+ -+ port@0 { -+ ov106xx_in6: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin6ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep2>; -+ }; -+ }; -+ }; -+ -+ ov106xx@7 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x67>; -+ -+ port@0 { -+ ov106xx_in7: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin7ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_des1ep3: endpoint { -+ remote-endpoint = <&max9286_des1ep3>; -+ }; -+ }; -+ }; -+ + max9286-max9271@0 { + compatible = "maxim,max9286-max9271"; + reg = <0x4c>; @@ -11924,196 +9646,43 @@ index 0000000..2c24b85 + max9286_des0ep0: endpoint@0 { + max9271-addr = <0x50>; + dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ max9286_des0ep1: endpoint@1 { -+ max9271-addr = <0x51>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ max9286_des0ep2: endpoint@2 { -+ max9271-addr = <0x52>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in2>; -+ }; -+ max9286_des0ep3: endpoint@3 { -+ max9271-addr = <0x53>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in3>; -+ }; -+ }; -+ port@1 { -+ max9286_csi0ep0: endpoint { -+ csi-rate = <700>; -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ }; -+ -+ max9286-max9271@1 { -+ compatible = "maxim,max9286-max9271"; -+ reg = <0x6c>; -+ gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; -+ maxim,sensor_delay = <0>; -+ maxim,links = <4>; -+ maxim,lanes = <4>; -+ maxim,resetb-gpio = <1>; -+ maxim,fsync-mode = "automatic"; -+ maxim,timeout = <100>; -+ -+ port@0 { -+ max9286_des1ep0: endpoint@0 { -+ max9271-addr = <0x54>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in4>; -+ }; -+ max9286_des1ep1: endpoint@1 { -+ max9271-addr = <0x55>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in5>; -+ }; -+ max9286_des1ep2: endpoint@2 { -+ max9271-addr = <0x56>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in6>; -+ }; -+ max9286_des1ep3: endpoint@3 { -+ max9271-addr = <0x57>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in7>; -+ }; -+ }; -+ port@1 { -+ max9286_csi2ep0: endpoint { -+ csi-rate = <700>; -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; -+ }; -+}; -+ -+&pcie_bus_clk { -+ clock-frequency = <100000000>; -+ status = "okay"; -+}; -+ -+&pciec1 { -+ status = "okay"; -+}; -+ -+&vin0 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin0ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ }; -+ port@1 { -+ csi0ep0: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ port@2 { -+ vin0_max9286_des0ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep0>; -+ }; -+ }; -+ }; -+}; -+ -+&vin1 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin1ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <1>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ }; -+ port@1 { -+ csi0ep1: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ port@2 { -+ vin1_max9286_des0ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep1>; -+ }; -+ }; -+ }; -+}; -+ -+&vin2 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin2ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <2>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in2>; -+ }; -+ }; -+ port@1 { -+ csi0ep2: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ port@2 { -+ vin2_max9286_des0ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep2>; -+ }; -+ }; -+ }; -+}; -+ -+&vin3 { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin3ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <3>; -+ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; + remote-endpoint = <&ov106xx_in3>; + }; + }; + port@1 { -+ csi0ep3: endpoint { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; + remote-endpoint = <&csi2_40_ep>; + }; + }; -+ port@2 { -+ vin3_max9286_des0ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep3>; -+ }; -+ }; + }; +}; + -+&vin4 { ++&pcie_bus_clk { ++ clock-frequency = <100000000>; ++ status = "okay"; ++}; ++ ++&pciec1 { ++ status = "okay"; ++}; ++ ++&vin0 { + status = "okay"; + + ports { @@ -12121,27 +9690,27 @@ index 0000000..2c24b85 + #size-cells = <0>; + + port@0 { -+ vin4ep0: endpoint { -+ csi,select = "csi41"; ++ vin0ep0: endpoint { ++ csi,select = "csi40"; + virtual,channel = <0>; -+ remote-endpoint = <&ov106xx_in4>; + data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; + }; + }; + port@1 { -+ csi2ep0: endpoint { -+ remote-endpoint = <&csi2_41_ep>; ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; + }; + }; + port@2 { -+ vin4_max9286_des1ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep0>; ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; + }; + }; + }; +}; + -+&vin5 { ++&vin1 { + status = "okay"; + + ports { @@ -12149,27 +9718,27 @@ index 0000000..2c24b85 + #size-cells = <0>; + + port@0 { -+ vin5ep0: endpoint@0 { -+ csi,select = "csi41"; ++ vin1ep0: endpoint { ++ csi,select = "csi40"; + virtual,channel = <1>; -+ remote-endpoint = <&ov106xx_in5>; + data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; + }; + }; + port@1 { -+ csi2ep1: endpoint { -+ remote-endpoint = <&csi2_41_ep>; ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; + }; + }; + port@2 { -+ vin5_max9286_des1ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep1>; ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; + }; + }; + }; +}; + -+&vin6 { ++&vin2 { + status = "okay"; + + ports { @@ -12177,27 +9746,27 @@ index 0000000..2c24b85 + #size-cells = <0>; + + port@0 { -+ vin6ep0: endpoint@0 { -+ csi,select = "csi41"; ++ vin2ep0: endpoint { ++ csi,select = "csi40"; + virtual,channel = <2>; -+ remote-endpoint = <&ov106xx_in6>; + data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; + }; + }; + port@1 { -+ csi2ep2: endpoint { -+ remote-endpoint = <&csi2_41_ep>; ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; + }; + }; + port@2 { -+ vin6_max9286_des1ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep2>; ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; + }; + }; + }; +}; + -+&vin7 { ++&vin3 { + status = "okay"; + + ports { @@ -12205,21 +9774,21 @@ index 0000000..2c24b85 + #size-cells = <0>; + + port@0 { -+ vin7ep0: endpoint@0 { -+ csi,select = "csi41"; ++ vin3ep0: endpoint { ++ csi,select = "csi40"; + virtual,channel = <3>; -+ remote-endpoint = <&ov106xx_in7>; + data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; + }; + }; + port@1 { -+ csi2ep3: endpoint { -+ remote-endpoint = <&csi2_41_ep>; ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; + }; + }; + port@2 { -+ vin7_max9286_des1ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep3>; ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; + }; + }; + }; @@ -12258,61 +9827,27 @@ index 0000000..2c24b85 + }; + }; +}; -+ -+&csi2_41 { -+ status = "okay"; -+ -+ virtual,channel { -+ csi2_vc0 { -+ data,type = "ycbcr422"; -+ receive,vc = <0>; -+ }; -+ csi2_vc1 { -+ data,type = "ycbcr422"; -+ receive,vc = <1>; -+ }; -+ csi2_vc2 { -+ data,type = "ycbcr422"; -+ receive,vc = <2>; -+ }; -+ csi2_vc3 { -+ data,type = "ycbcr422"; -+ receive,vc = <3>; -+ }; -+ }; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ csi2_41_ep: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ csi-rate = <300>; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x-view.dts +diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts new file mode 100644 -index 0000000..fb12a39f3 +index 0000000..cc6866c --- /dev/null -+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x-view.dts -@@ -0,0 +1,552 @@ ++++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts +@@ -0,0 +1,318 @@ +/* + * Device Tree Source for the Salvator-X.View board + * + * Copyright (C) 2016-2017 Renesas Electronics Corp. -+ * Copyright (C) 2015-2017 Cogent Embedded, Inc ++ * Copyright (C) 2016-2017 Cogent Embedded, Inc + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + -+#include "r8a7795-salvator-x.dts" ++#include "r8a7796-salvator-x.dts" + +/ { -+ model = "Renesas Salvator-X.View board based on r8a7795"; ++ model = "Renesas Salvator-X.View board based on r8a7796"; +}; + +&pfc { @@ -12403,78 +9938,6 @@ index 0000000..fb12a39f3 + }; + }; + -+ ov106xx@4 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x64>; -+ -+ port@0 { -+ ov106xx_in4: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin4ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep0>; -+ }; -+ }; -+ }; -+ -+ ov106xx@5 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x65>; -+ -+ port@0 { -+ ov106xx_in5: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin5ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep1>; -+ }; -+ }; -+ }; -+ -+ ov106xx@6 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x66>; -+ -+ port@0 { -+ ov106xx_in6: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin6ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep2>; -+ }; -+ }; -+ }; -+ -+ ov106xx@7 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x67>; -+ -+ port@0 { -+ ov106xx_in7: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin7ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_des1ep3: endpoint { -+ remote-endpoint = <&max9286_des1ep3>; -+ }; -+ }; -+ }; -+ + max9286-max9271@0 { + compatible = "maxim,max9286-max9271"; + reg = <0x4c>; @@ -12506,53 +9969,13 @@ index 0000000..fb12a39f3 + max9286_des0ep3: endpoint@3 { + max9271-addr = <0x53>; + dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in3>; -+ }; -+ }; -+ port@1 { -+ max9286_csi0ep0: endpoint { -+ csi-rate = <700>; -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ }; -+ -+ max9286-max9271@1 { -+ compatible = "maxim,max9286-max9271"; -+ reg = <0x6c>; -+ maxim,sensor_delay = <0>; -+ maxim,links = <4>; -+ maxim,lanes = <4>; -+ maxim,resetb-gpio = <1>; -+ maxim,fsync-mode = "automatic"; -+ maxim,timeout = <100>; -+ -+ port@0 { -+ max9286_des1ep0: endpoint@0 { -+ max9271-addr = <0x54>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in4>; -+ }; -+ max9286_des1ep1: endpoint@1 { -+ max9271-addr = <0x55>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in5>; -+ }; -+ max9286_des1ep2: endpoint@2 { -+ max9271-addr = <0x56>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in6>; -+ }; -+ max9286_des1ep3: endpoint@3 { -+ max9271-addr = <0x57>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in7>; ++ remote-endpoint = <&ov106xx_in3>; + }; + }; + port@1 { -+ max9286_csi2ep0: endpoint { ++ max9286_csi0ep0: endpoint { + csi-rate = <700>; -+ remote-endpoint = <&csi2_41_ep>; ++ remote-endpoint = <&csi2_40_ep>; + }; + }; + }; @@ -12663,263 +10086,345 @@ index 0000000..fb12a39f3 +}; + +&vin4 { -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; ++ status = "disabled"; ++}; + -+ port@0 { -+ vin4ep0: endpoint { -+ csi,select = "csi41"; -+ virtual,channel = <0>; -+ remote-endpoint = <&ov106xx_in4>; -+ data-lanes = <1 2 3 4>; -+ }; ++&vin5 { ++ status = "disabled"; ++}; ++ ++&vin6 { ++ status = "disabled"; ++}; ++ ++&vin7 { ++ status = "disabled"; ++}; ++ ++&csi2_20 { ++ status = "disabled"; ++ /delete-node/ports; ++}; ++ ++&csi2_40 { ++ /delete-node/ports; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; + }; -+ port@1 { -+ csi2ep0: endpoint { -+ remote-endpoint = <&csi2_41_ep>; -+ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; + }; -+ port@2 { -+ vin4_max9286_des1ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep0>; -+ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; + }; + }; -+}; + -+&vin5 { -+ ports { ++ port { + #address-cells = <1>; + #size-cells = <0>; + -+ port@0 { -+ vin5ep0: endpoint@0 { -+ csi,select = "csi41"; -+ virtual,channel = <1>; -+ remote-endpoint = <&ov106xx_in5>; -+ data-lanes = <1 2 3 4>; -+ }; ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; + }; -+ port@1 { -+ csi2ep1: endpoint { -+ remote-endpoint = <&csi2_41_ep>; -+ }; ++ }; ++}; ++ ++&can0 { ++ pinctrl-0 = <&can0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&can1 { ++ pinctrl-0 = <&can1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts b/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts +new file mode 100644 +index 0000000..f71addf +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts +@@ -0,0 +1,561 @@ ++/* ++ * Device Tree Source for the Eagle board ++ * ++ * Copyright (C) 2016-2017 Renesas Electronics Corp. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++#include "r8a7797.dtsi" ++#include ++ ++/ { ++ model = "Renesas Eagle board based on r8a7797"; ++ compatible = "renesas,eagle", "renesas,r8a7797"; ++ ++ aliases { ++ serial0 = &scif0; ++ ethernet0 = &avb; ++ }; ++ ++ chosen { ++ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@48000000 { ++ device_type = "memory"; ++ /* first 128MB is reserved for secure area. */ ++ reg = <0x0 0x48000000 0x0 0x38000000>; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ /* device specific region for Lossy Decompression */ ++ lossy_decompress: linux,lossy_decompress { ++ no-map; ++ reg = <0x00000000 0x64000000 0x0 0x03000000>; + }; -+ port@2 { -+ vin5_max9286_des1ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep1>; -+ }; ++ ++ /* global autoconfigured region for contiguous allocations */ ++ linux,cma { ++ compatible = "shared-dma-pool"; ++ reusable; ++ reg = <0x00000000 0x67000000 0x0 0x09000000>; ++ linux,cma-default; ++ }; ++ ++ /* device specific region for contiguous allocations */ ++ linux,multimedia { ++ compatible = "shared-dma-pool"; ++ reusable; ++ reg = <0x00000000 0x70000000 0x0 0x10000000>; + }; + }; -+}; + -+&vin6 { -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; ++ mmngr { ++ compatible = "renesas,mmngr"; ++ memory-region = <&lossy_decompress>; ++ }; + -+ port@0 { -+ vin6ep0: endpoint@0 { -+ csi,select = "csi41"; -+ virtual,channel = <2>; -+ remote-endpoint = <&ov106xx_in6>; -+ data-lanes = <1 2 3 4>; ++ mmngrbuf { ++ compatible = "renesas,mmngrbuf"; ++ }; ++ ++ vspm_if { ++ compatible = "renesas,vspm_if"; ++ }; ++ ++ lvds-encoder { ++ compatible = "thine,thc63lvdm83d"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ lvds_enc_in: endpoint { ++ remote-endpoint = <&du_out_lvds0>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ lvds_enc_out: endpoint { ++ remote-endpoint = <&lvds_in>; ++ }; + }; + }; -+ port@1 { -+ csi2ep2: endpoint { -+ remote-endpoint = <&csi2_41_ep>; ++ }; ++ ++ lvds { ++ compatible = "lvds-connector"; ++ ++ width-mm = <210>; ++ height-mm = <158>; ++ ++ panel-timing { ++ clock-frequency = <133000000>; ++ hactive = <1024>; ++ vactive = <768>; ++ hsync-len = <136>; ++ hfront-porch = <20>; ++ hback-porch = <160>; ++ vfront-porch = <3>; ++ vback-porch = <29>; ++ vsync-len = <6>; ++ }; ++ ++ port { ++ lvds_in: endpoint { ++ remote-endpoint = <&lvds_enc_out>; + }; + }; -+ port@2 { -+ vin6_max9286_des1ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ ++ hdmi-out { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con: endpoint { ++ remote-endpoint = <&adv7511_out>; + }; + }; + }; ++ ++ dclkin_p0: clock-out0 { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <148500000>; ++ }; ++ ++ msiof_ref_clk: msiof-ref-clock { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <66666666>; ++ }; +}; + -+&vin7 { ++&du { ++ pinctrl-0 = <&du_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ + ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ + port@0 { -+ vin7ep0: endpoint@0 { -+ csi,select = "csi41"; -+ virtual,channel = <3>; -+ remote-endpoint = <&ov106xx_in7>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ port@1 { -+ csi2ep3: endpoint { -+ remote-endpoint = <&csi2_41_ep>; -+ }; -+ }; -+ port@2 { -+ vin7_max9286_des1ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep3>; ++ endpoint { ++ remote-endpoint = <&adv7511_in>; + }; + }; + }; +}; + -+&csi2_20 { -+ status = "disabled"; -+ /delete-node/ports; ++&extal_clk { ++ clock-frequency = <16666666>; +}; + -+&csi2_40 { -+ /delete-node/ports; ++&extalr_clk { ++ clock-frequency = <32768>; ++}; + -+ virtual,channel { -+ csi2_vc0 { -+ data,type = "ycbcr422"; -+ receive,vc = <0>; -+ }; -+ csi2_vc1 { -+ data,type = "ycbcr422"; -+ receive,vc = <1>; -+ }; -+ csi2_vc2 { -+ data,type = "ycbcr422"; -+ receive,vc = <2>; -+ }; -+ csi2_vc3 { -+ data,type = "ycbcr422"; -+ receive,vc = <3>; -+ }; -+ }; ++&pfc { ++ pinctrl-0 = <&scif_clk_pins>; ++ pinctrl-names = "default"; + -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; ++ scif0_pins: scif0 { ++ groups = "scif0_data"; ++ function = "scif0"; ++ }; + -+ csi2_40_ep: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ csi-rate = <300>; -+ }; ++ scif_clk_pins: scif_clk { ++ groups = "scif_clk_b"; ++ function = "scif_clk"; + }; -+}; + -+&csi2_41 { -+ status = "okay"; ++ i2c0_pins: i2c0 { ++ groups = "i2c0"; ++ function = "i2c0"; ++ }; + -+ virtual,channel { -+ csi2_vc0 { -+ data,type = "ycbcr422"; -+ receive,vc = <0>; -+ }; -+ csi2_vc1 { -+ data,type = "ycbcr422"; -+ receive,vc = <1>; -+ }; -+ csi2_vc2 { -+ data,type = "ycbcr422"; -+ receive,vc = <2>; -+ }; -+ csi2_vc3 { -+ data,type = "ycbcr422"; -+ receive,vc = <3>; -+ }; ++ i2c3_pins: i2c3 { ++ groups = "i2c3"; ++ function = "i2c3"; + }; + -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; ++ avb_pins: avb { ++ groups = "avb0_mdc"; ++ function = "avb0"; ++ }; + -+ csi2_41_ep: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ csi-rate = <300>; -+ }; ++ du_pins: du { ++ groups = "du_rgb666", "du_sync", "du_clk_out_0", "du_disp"; ++ function = "du"; + }; +}; + -+&can0 { -+ pinctrl-0 = <&can0_pins>; ++&scif0 { ++ pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; ++ + status = "okay"; +}; + -+&can1 { -+ pinctrl-0 = <&can1_pins>; -+ pinctrl-names = "default"; ++&scif_clk { ++ clock-frequency = <14745600>; + status = "okay"; +}; -diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts -new file mode 100644 -index 0000000..a409402 ---- /dev/null -+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts -@@ -0,0 +1,40 @@ -+/* -+ * Device Tree Source for the M3ULCB Kingfisher board on r8a7796 -+ * -+ * Copyright (C) 2017 Renesas Electronics Corp. -+ * Copyright (C) 2017 Cogent Embedded, Inc. -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ + -+#include "r8a7796-m3ulcb.dts" -+#include "ulcb-kf.dtsi" ++&i2c0 { ++ pinctrl-0 = <&i2c0_pins>; ++ pinctrl-names = "default"; + -+/ { -+ model = "Renesas M3ULCB Kingfisher board based on r8a7796"; -+}; ++ status = "okay"; ++ clock-frequency = <400000>; + -+&du { -+ ports { -+ port@0 { -+ endpoint { -+ remote-endpoint = <&adv7513_in>; ++ hdmi@39{ ++ compatible = "adi,adv7511w"; ++ #sound-dai-cells = <0>; ++ reg = <0x39>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <20 IRQ_TYPE_LEVEL_LOW>; ++ ++ adi,input-depth = <8>; ++ adi,input-colorspace = "rgb"; ++ adi,input-clock = "1x"; ++ adi,input-style = <1>; ++ adi,input-justification = "evenly"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ adv7511_in: endpoint { ++ remote-endpoint = <&lvds_enc_out>; ++ }; + }; -+ }; -+ port@2 { -+ endpoint { -+ remote-endpoint = <&lvds_enc_in>; ++ port@1 { ++ reg = <1>; ++ adv7511_out: endpoint { ++ remote-endpoint = <&hdmi_con>; ++ }; + }; + }; + }; -+}; -+ -+&hsusb { -+ status = "okay"; -+}; + -+&xhci0 { -+ status = "disabled"; ++ gpio_ext: pca9654@20 { ++ compatible = "onsemi,pca9654"; ++ reg = <0x20>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; +}; -diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts -new file mode 100644 -index 0000000..1ac0041 ---- /dev/null -+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts -@@ -0,0 +1,287 @@ -+/* -+ * Device Tree Source for the M3ULCB.View board on r8a7796 -+ * -+ * Copyright (C) 2016-2017 Renesas Electronics Corp. -+ * Copyright (C) 2016-2017 Cogent Embedded, Inc. -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ + -+#include "r8a7796-m3ulcb.dts" ++&i2c3 { ++ pinctrl-0 = <&i2c3_pins>; ++ pinctrl-names = "default"; + -+/ { -+ model = "Renesas M3ULCB.View board based on r8a7796"; -+}; ++ status = "okay"; ++ clock-frequency = <400000>; + -+&i2c4 { + ov106xx@0 { + compatible = "ovti,ov106xx"; + reg = <0x60>; @@ -12994,15 +10499,15 @@ index 0000000..1ac0041 + + max9286-max9271@0 { + compatible = "maxim,max9286-max9271"; -+ reg = <0x4c>; -+ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; -+ maxim,sensor_delay = <0>; ++ reg = <0x48>; ++ gpios = <&gpio_ext 0 GPIO_ACTIVE_LOW>; /* CSI0 DE_PDn */ ++ maxim,gpio0 = <0>; ++ maxim,sensor_delay = <100>; + maxim,links = <4>; + maxim,lanes = <4>; + maxim,resetb-gpio = <1>; + maxim,fsync-mode = "automatic"; + maxim,timeout = <100>; -+ maxim,i2c-quirk = <0x6c>; + + port@0 { + max9286_des0ep0: endpoint@0 { @@ -13035,15 +10540,38 @@ index 0000000..1ac0041 + }; +}; + -+&pcie_bus_clk { -+ clock-frequency = <100000000>; -+ status = "okay"; -+}; -+ -+&pciec1 { -+ status = "okay"; -+}; -+ ++&wdt0 { ++ status = "okay"; ++}; ++ ++&avb { ++ pinctrl-0 = <&avb_pins>; ++ pinctrl-names = "default"; ++ renesas,no-ether-link; ++ phy-handle = <&phy0>; ++ status = "okay"; ++ phy-int-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>; ++ ++ phy0: ethernet-phy@0 { ++ rxc-skew-ps = <1500>; ++ rxdv-skew-ps = <420>; /* default */ ++ rxd0-skew-ps = <420>; /* default */ ++ rxd1-skew-ps = <420>; /* default */ ++ rxd2-skew-ps = <420>; /* default */ ++ rxd3-skew-ps = <420>; /* default */ ++ txc-skew-ps = <900>; /* default */ ++ txen-skew-ps = <420>; /* default */ ++ txd0-skew-ps = <420>; /* default */ ++ txd1-skew-ps = <420>; /* default */ ++ txd2-skew-ps = <420>; /* default */ ++ txd3-skew-ps = <420>; /* default */ ++ reg = <0>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <17 IRQ_TYPE_LEVEL_LOW>; ++ max-speed = <1000>; ++ }; ++}; ++ +&vin0 { + status = "okay"; + @@ -13189,161 +10717,465 @@ index 0000000..1ac0041 + }; + }; +}; -diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts ++ +diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts new file mode 100644 -index 0000000..cc6866c +index 0000000..979cebe --- /dev/null -+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts -@@ -0,0 +1,318 @@ ++++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts +@@ -0,0 +1,578 @@ +/* -+ * Device Tree Source for the Salvator-X.View board ++ * Device Tree Source for the V3MSK Kingfisher board on r8a7797 + * -+ * Copyright (C) 2016-2017 Renesas Electronics Corp. -+ * Copyright (C) 2016-2017 Cogent Embedded, Inc ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + -+#include "r8a7796-salvator-x.dts" ++#include "r8a7797-v3msk.dts" + +/ { -+ model = "Renesas Salvator-X.View board based on r8a7796"; ++ model = "Renesas V3MSK Kingfisher board based on r8a7797"; +}; + -+&pfc { -+ can0_pins: can0 { -+ groups = "can0_data_a"; -+ function = "can0"; ++&canfd { ++ pinctrl-0 = <&canfd0_pins &canfd1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ channel0 { ++ status = "okay"; + }; + -+ can1_pins: can1 { -+ groups = "can1_data"; -+ function = "can1"; ++ channel1 { ++ status = "okay"; + }; +}; + -+&i2c4 { -+ /delete-node/hdmi-in@34; -+ /delete-node/composite-in@70; -+ -+ ov106xx@0 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x60>; ++&csi2_40 { ++ status = "okay"; + -+ port@0 { -+ ov106xx_in0: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin0ep0>; -+ }; ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; + }; -+ port@1 { -+ ov106xx_max9286_des0ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep0>; -+ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; + }; + }; + -+ ov106xx@1 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x61>; ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ port@0 { -+ ov106xx_in1: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin1ep0>; -+ }; ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; + }; -+ port@1 { -+ ov106xx_max9286_des0ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep1>; ++ }; ++}; ++ ++&i2c0 { ++ /* i2c0 might conflict with pc9548 reset pin on Kingfisher (uncomment if h/w not patched) */ ++// status = "disabled"; ++}; ++ ++&i2c3 { ++ pinctrl-0 = <&i2c3_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ clock-frequency = <400000>; ++ ++ i2cswitch4: pca9548@71 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x71>; ++// reset-gpios= <&gpio3 15 GPIO_ACTIVE_LOW>; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ /* Slot B (CN11) */ ++ ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ ov106xx_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ ov106xx_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; ++ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ ov106xx_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ ov106xx_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; ++ ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ ov106xx_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ ov106xx_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@0 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti964_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti964_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ ti964_des0ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ ti964_des0ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ ti964_csi0ep0: endpoint { ++ csi-rate = <800>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; + }; -+ }; -+ }; + -+ ov106xx@2 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x62>; ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@0 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_a_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; + -+ port@0 { -+ ov106xx_in2: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin2ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep2>; ++ port@0 { ++ ti954_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti954_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ ti954_csi0ep0: endpoint { ++ csi-rate = <800>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; + }; -+ }; -+ }; + -+ ov106xx@3 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x63>; ++ /* MAX9286 @ 0x2c */ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; + -+ port@0 { -+ ov106xx_in3: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin3ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_des0ep3: endpoint { -+ remote-endpoint = <&max9286_des0ep3>; ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; + }; + }; -+ }; + -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; -+ reg = <0x4c>; -+ gpios = <&gpio6 30 GPIO_ACTIVE_LOW>; -+ maxim,sensor_delay = <0>; -+ maxim,links = <4>; -+ maxim,lanes = <4>; -+ maxim,resetb-gpio = <1>; -+ maxim,fsync-mode = "automatic"; -+ maxim,timeout = <100>; -+ maxim,i2c-quirk = <0x6c>; ++ i2c@6 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <6>; ++ /* Slot B (CN11) */ + -+ port@0 { -+ max9286_des0ep0: endpoint@0 { -+ max9271-addr = <0x50>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ max9286_des0ep1: endpoint@1 { -+ max9271-addr = <0x51>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ max9286_des0ep2: endpoint@2 { -+ max9271-addr = <0x52>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in2>; -+ }; -+ max9286_des0ep3: endpoint@3 { -+ max9271-addr = <0x53>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in3>; ++ video_a_ext0: pca9535@27 { ++ compatible = "nxp,pca9535"; ++ reg = <0x27>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; ++ }; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; ++ }; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; ++ }; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A led"; ++ }; + }; -+ }; -+ port@1 { -+ max9286_csi0ep0: endpoint { -+ csi-rate = <700>; -+ remote-endpoint = <&csi2_40_ep>; ++ ++ video_a_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg2"; ++ }; ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; ++ }; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; ++ }; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; ++ }; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A LED"; ++ }; + }; + }; + }; +}; + ++&pfc { ++ canfd0_pins: canfd0 { ++ groups = "canfd0_data_a"; ++ function = "canfd0"; ++ }; ++ ++ canfd1_pins: canfd1 { ++ groups = "canfd1_data"; ++ function = "canfd1"; ++ }; ++ ++ i2c3_pins: i2c3 { ++ groups = "i2c3"; ++ function = "i2c3"; ++ }; ++}; ++ +&vin0 { ++ status = "okay"; ++ + ports { + #address-cells = <1>; + #size-cells = <0>; @@ -13365,573 +11197,490 @@ index 0000000..cc6866c + vin0_max9286_des0ep0: endpoint@0 { + remote-endpoint = <&max9286_des0ep0>; + }; -+ }; -+ }; -+}; -+ -+&vin1 { -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin1ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <1>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ }; -+ port@1 { -+ csi0ep1: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ port@2 { -+ vin1_max9286_des0ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep1>; -+ }; -+ }; -+ }; -+}; -+ -+&vin2 { -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin2ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <2>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in2>; -+ }; -+ }; -+ port@1 { -+ csi0ep2: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ port@2 { -+ vin2_max9286_des0ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep2>; -+ }; -+ }; -+ }; -+}; -+ -+&vin3 { -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin3ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <3>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in3>; -+ }; -+ }; -+ port@1 { -+ csi0ep3: endpoint { -+ remote-endpoint = <&csi2_40_ep>; ++ vin0_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; + }; -+ }; -+ port@2 { -+ vin3_max9286_des0ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep3>; ++ vin0_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; + }; + }; + }; -+}; -+ -+&vin4 { -+ status = "disabled"; -+}; -+ -+&vin5 { -+ status = "disabled"; -+}; -+ -+&vin6 { -+ status = "disabled"; -+}; -+ -+&vin7 { -+ status = "disabled"; -+}; -+ -+&csi2_20 { -+ status = "disabled"; -+ /delete-node/ports; -+}; -+ -+&csi2_40 { -+ /delete-node/ports; -+ -+ virtual,channel { -+ csi2_vc0 { -+ data,type = "ycbcr422"; -+ receive,vc = <0>; -+ }; -+ csi2_vc1 { -+ data,type = "ycbcr422"; -+ receive,vc = <1>; -+ }; -+ csi2_vc2 { -+ data,type = "ycbcr422"; -+ receive,vc = <2>; -+ }; -+ csi2_vc3 { -+ data,type = "ycbcr422"; -+ receive,vc = <3>; -+ }; -+ }; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ csi2_40_ep: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ csi-rate = <300>; -+ }; -+ }; -+}; -+ -+&can0 { -+ pinctrl-0 = <&can0_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; -+ -+&can1 { -+ pinctrl-0 = <&can1_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts b/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts -new file mode 100644 -index 0000000..f71addf ---- /dev/null -+++ b/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts -@@ -0,0 +1,561 @@ -+/* -+ * Device Tree Source for the Eagle board -+ * -+ * Copyright (C) 2016-2017 Renesas Electronics Corp. -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ -+ -+/dts-v1/; -+#include "r8a7797.dtsi" -+#include -+ -+/ { -+ model = "Renesas Eagle board based on r8a7797"; -+ compatible = "renesas,eagle", "renesas,r8a7797"; -+ -+ aliases { -+ serial0 = &scif0; -+ ethernet0 = &avb; -+ }; -+ -+ chosen { -+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory@48000000 { -+ device_type = "memory"; -+ /* first 128MB is reserved for secure area. */ -+ reg = <0x0 0x48000000 0x0 0x38000000>; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* device specific region for Lossy Decompression */ -+ lossy_decompress: linux,lossy_decompress { -+ no-map; -+ reg = <0x00000000 0x64000000 0x0 0x03000000>; -+ }; -+ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ reg = <0x00000000 0x67000000 0x0 0x09000000>; -+ linux,cma-default; -+ }; -+ -+ /* device specific region for contiguous allocations */ -+ linux,multimedia { -+ compatible = "shared-dma-pool"; -+ reusable; -+ reg = <0x00000000 0x70000000 0x0 0x10000000>; -+ }; -+ }; -+ -+ mmngr { -+ compatible = "renesas,mmngr"; -+ memory-region = <&lossy_decompress>; -+ }; -+ -+ mmngrbuf { -+ compatible = "renesas,mmngrbuf"; -+ }; -+ -+ vspm_if { -+ compatible = "renesas,vspm_if"; -+ }; ++}; + -+ lvds-encoder { -+ compatible = "thine,thc63lvdm83d"; ++&vin1 { ++ status = "okay"; + -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ port@0 { -+ reg = <0>; -+ lvds_enc_in: endpoint { -+ remote-endpoint = <&du_out_lvds0>; -+ }; ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; + }; -+ port@1 { -+ reg = <1>; -+ lvds_enc_out: endpoint { -+ remote-endpoint = <&lvds_in>; -+ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ vin1_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ vin1_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; + }; + }; + }; ++}; + -+ lvds { -+ compatible = "lvds-connector"; ++&vin2 { ++ status = "okay"; + -+ width-mm = <210>; -+ height-mm = <158>; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ panel-timing { -+ clock-frequency = <133000000>; -+ hactive = <1024>; -+ vactive = <768>; -+ hsync-len = <136>; -+ hfront-porch = <20>; -+ hback-porch = <160>; -+ vfront-porch = <3>; -+ vback-porch = <29>; -+ vsync-len = <6>; ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; + }; -+ -+ port { -+ lvds_in: endpoint { -+ remote-endpoint = <&lvds_enc_out>; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; + }; + }; -+ }; -+ -+ hdmi-out { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con: endpoint { -+ remote-endpoint = <&adv7511_out>; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ vin2_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; + }; + }; + }; -+ -+ dclkin_p0: clock-out0 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <148500000>; -+ }; -+ -+ msiof_ref_clk: msiof-ref-clock { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <66666666>; -+ }; +}; + -+&du { -+ pinctrl-0 = <&du_pins>; -+ pinctrl-names = "default"; ++&vin3 { + status = "okay"; + + ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ + port@0 { -+ endpoint { -+ remote-endpoint = <&adv7511_in>; ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ vin3_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; + }; + }; + }; +}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts +new file mode 100644 +index 0000000..28a0b92 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts +@@ -0,0 +1,498 @@ ++/* ++ * Device Tree Source for the V3MSK Videobox Mini board on r8a7797 ++ * ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ + -+&extal_clk { -+ clock-frequency = <16666666>; -+}; ++#include "r8a7797-v3msk.dts" + -+&extalr_clk { -+ clock-frequency = <32768>; ++/ { ++ model = "Renesas V3MSK Videobox Mini board based on r8a7797"; ++ ++ aliases { ++ serial1 = &scif3; ++ }; +}; + -+&pfc { -+ pinctrl-0 = <&scif_clk_pins>; ++&canfd { ++ pinctrl-0 = <&canfd0_pins &canfd1_pins>; + pinctrl-names = "default"; ++ status = "okay"; + -+ scif0_pins: scif0 { -+ groups = "scif0_data"; -+ function = "scif0"; ++ channel0 { ++ status = "okay"; + }; + -+ scif_clk_pins: scif_clk { -+ groups = "scif_clk_b"; -+ function = "scif_clk"; ++ channel1 { ++ status = "okay"; + }; ++}; + -+ i2c0_pins: i2c0 { -+ groups = "i2c0"; -+ function = "i2c0"; -+ }; ++&csi2_40 { ++ status = "okay"; + -+ i2c3_pins: i2c3 { -+ groups = "i2c3"; -+ function = "i2c3"; ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; + }; + -+ avb_pins: avb { -+ groups = "avb0_mdc"; -+ function = "avb0"; -+ }; ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ du_pins: du { -+ groups = "du_rgb666", "du_sync", "du_clk_out_0", "du_disp"; -+ function = "du"; ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; + }; +}; + -+&scif0 { -+ pinctrl-0 = <&scif0_pins>; ++&i2c1 { ++ pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; -+ + status = "okay"; -+}; + -+&scif_clk { -+ clock-frequency = <14745600>; -+ status = "okay"; -+}; ++ clock-frequency = <100000>; + -+&i2c0 { -+ pinctrl-0 = <&i2c0_pins>; -+ pinctrl-names = "default"; ++ i2cswitch1: i2c-switch@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x74>; ++ reset-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + -+ status = "okay"; -+ clock-frequency = <400000>; ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ ov106xx_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ }; ++ }; + -+ hdmi@39{ -+ compatible = "adi,adv7511w"; -+ #sound-dai-cells = <0>; -+ reg = <0x39>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>; ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; + -+ adi,input-depth = <8>; -+ adi,input-colorspace = "rgb"; -+ adi,input-clock = "1x"; -+ adi,input-style = <1>; -+ adi,input-justification = "evenly"; ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ ov106xx_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ }; ++ }; + -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; + -+ port@0 { -+ reg = <0>; -+ adv7511_in: endpoint { -+ remote-endpoint = <&lvds_enc_out>; ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; + }; -+ }; -+ port@1 { -+ reg = <1>; -+ adv7511_out: endpoint { -+ remote-endpoint = <&hdmi_con>; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ ov106xx_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; + }; + }; -+ }; -+ }; -+ -+ gpio_ext: pca9654@20 { -+ compatible = "onsemi,pca9654"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+}; + -+&i2c3 { -+ pinctrl-0 = <&i2c3_pins>; -+ pinctrl-names = "default"; ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; + -+ status = "okay"; -+ clock-frequency = <400000>; ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ ov106xx_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; + -+ ov106xx@0 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x60>; ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; + -+ port@0 { -+ ov106xx_in0: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin0ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep0>; ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; + }; -+ }; -+ }; + -+ ov106xx@1 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x61>; ++ ti964-ti9x3@0 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; + -+ port@0 { -+ ov106xx_in1: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin1ep0>; ++ port@0 { ++ ti964_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti964_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ ti964_des0ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ ti964_des0ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ ti964_csi0ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; + }; + }; -+ port@1 { -+ ov106xx_max9286_des0ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep1>; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ ++ gpio_exp_6c: gpio@6c { ++ compatible = "maxim,max7325"; ++ reg = <0x6c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ virq { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video VIRQ"; ++ }; ++ des_cfg { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video CNFG0"; ++ }; ++ pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video PWR_SHDN"; ++ }; ++ cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video PWR0"; ++ }; ++ cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video PWR1"; ++ }; ++ cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video PWR2"; ++ }; ++ cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video PWR3"; ++ }; ++ des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video DES_SHDN"; ++ }; ++ fpdl_shdn { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video FPDL_SHDN"; ++ }; + }; + }; + }; ++}; + -+ ov106xx@2 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x62>; ++&gpio0 { ++ can0stby { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "CAN0STBY"; ++ }; + -+ port@0 { -+ ov106xx_in2: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin2ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep2>; -+ }; -+ }; ++ can1_load { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can1_120R_load"; + }; ++}; + -+ ov106xx@3 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x63>; ++&gpio2 { ++ can0_load { ++ gpio-hog; ++ gpios = <16 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can0_120R_load"; ++ }; ++}; + -+ port@0 { -+ ov106xx_in3: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin3ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_des0ep3: endpoint { -+ remote-endpoint = <&max9286_des0ep3>; -+ }; -+ }; ++&pfc { ++ canfd0_pins: canfd0 { ++ groups = "canfd0_data_a"; ++ function = "canfd0"; + }; + -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; -+ reg = <0x48>; -+ gpios = <&gpio_ext 0 GPIO_ACTIVE_LOW>; /* CSI0 DE_PDn */ -+ maxim,gpio0 = <0>; -+ maxim,sensor_delay = <100>; -+ maxim,links = <4>; -+ maxim,lanes = <4>; -+ maxim,resetb-gpio = <1>; -+ maxim,fsync-mode = "automatic"; -+ maxim,timeout = <100>; ++ canfd1_pins: canfd1 { ++ groups = "canfd1_data"; ++ function = "canfd1"; ++ }; + -+ port@0 { -+ max9286_des0ep0: endpoint@0 { -+ max9271-addr = <0x50>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ max9286_des0ep1: endpoint@1 { -+ max9271-addr = <0x51>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ max9286_des0ep2: endpoint@2 { -+ max9271-addr = <0x52>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in2>; -+ }; -+ max9286_des0ep3: endpoint@3 { -+ max9271-addr = <0x53>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in3>; -+ }; -+ }; -+ port@1 { -+ max9286_csi0ep0: endpoint { -+ csi-rate = <700>; -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; ++ i2c1_pins: i2c1 { ++ groups = "i2c1"; ++ function = "i2c1"; + }; -+}; + -+&wdt0 { -+ status = "okay"; ++ scif3_pins: scif3 { ++ groups = "scif3_data"; ++ function = "scif3"; ++ }; +}; + -+&avb { -+ pinctrl-0 = <&avb_pins>; ++&scif3 { ++ pinctrl-0 = <&scif3_pins>; + pinctrl-names = "default"; -+ renesas,no-ether-link; -+ phy-handle = <&phy0>; -+ status = "okay"; -+ phy-int-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>; + -+ phy0: ethernet-phy@0 { -+ rxc-skew-ps = <1500>; -+ rxdv-skew-ps = <420>; /* default */ -+ rxd0-skew-ps = <420>; /* default */ -+ rxd1-skew-ps = <420>; /* default */ -+ rxd2-skew-ps = <420>; /* default */ -+ rxd3-skew-ps = <420>; /* default */ -+ txc-skew-ps = <900>; /* default */ -+ txen-skew-ps = <420>; /* default */ -+ txd0-skew-ps = <420>; /* default */ -+ txd1-skew-ps = <420>; /* default */ -+ txd2-skew-ps = <420>; /* default */ -+ txd3-skew-ps = <420>; /* default */ -+ reg = <0>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>; -+ max-speed = <1000>; -+ }; ++ status = "okay"; +}; + +&vin0 { @@ -13958,6 +11707,9 @@ index 0000000..f71addf + vin0_max9286_des0ep0: endpoint@0 { + remote-endpoint = <&max9286_des0ep0>; + }; ++ vin0_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; + }; + }; +}; @@ -13986,6 +11738,9 @@ index 0000000..f71addf + vin1_max9286_des0ep1: endpoint@0 { + remote-endpoint = <&max9286_des0ep1>; + }; ++ vin1_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; + }; + }; +}; @@ -14014,6 +11769,9 @@ index 0000000..f71addf + vin2_max9286_des0ep2: endpoint@0 { + remote-endpoint = <&max9286_des0ep2>; + }; ++ vin2_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; + }; + }; +}; @@ -14042,599 +11800,768 @@ index 0000000..f71addf + vin3_max9286_des0ep3: endpoint@0 { + remote-endpoint = <&max9286_des0ep3>; + }; ++ vin3_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; + }; + }; +}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts +new file mode 100644 +index 0000000..bf2501e +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts +@@ -0,0 +1,320 @@ ++/* ++ * Device Tree Source for the V3M Starter Kit board on r8a7797 ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ + -+&csi2_40 { -+ status = "okay"; ++/dts-v1/; ++#include "r8a7797.dtsi" ++#include + -+ virtual,channel { -+ csi2_vc0 { -+ data,type = "ycbcr422"; -+ receive,vc = <0>; ++/ { ++ model = "Renesas V3M Starter Kit board based on r8a7797"; ++ compatible = "renesas,v3msk", "renesas,r8a7797"; ++ ++ aliases { ++ serial0 = &scif0; ++ ethernet0 = &avb; ++ }; ++ ++ chosen { ++ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@48000000 { ++ device_type = "memory"; ++ /* first 128MB is reserved for secure area. */ ++ reg = <0x0 0x48000000 0x0 0x38000000>; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ /* device specific region for Lossy Decompression */ ++ lossy_decompress: linux,lossy_decompress { ++ no-map; ++ reg = <0x00000000 0x64000000 0x0 0x03000000>; + }; -+ csi2_vc1 { -+ data,type = "ycbcr422"; -+ receive,vc = <1>; ++ ++ /* global autoconfigured region for contiguous allocations */ ++ linux,cma { ++ compatible = "shared-dma-pool"; ++ reusable; ++ reg = <0x00000000 0x67000000 0x0 0x09000000>; ++ linux,cma-default; + }; -+ csi2_vc2 { -+ data,type = "ycbcr422"; -+ receive,vc = <2>; ++ ++ /* device specific region for contiguous allocations */ ++ linux,multimedia { ++ compatible = "shared-dma-pool"; ++ reusable; ++ reg = <0x00000000 0x70000000 0x0 0x10000000>; + }; -+ csi2_vc3 { -+ data,type = "ycbcr422"; -+ receive,vc = <3>; ++ }; ++ ++ mmngr { ++ compatible = "renesas,mmngr"; ++ memory-region = <&lossy_decompress>; ++ }; ++ ++ mmngrbuf { ++ compatible = "renesas,mmngrbuf"; ++ }; ++ ++ vspm_if { ++ compatible = "renesas,vspm_if"; ++ }; ++ ++ lvds-encoder { ++ compatible = "thine,thc63lvdm83d"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ lvds_enc_in: endpoint { ++ remote-endpoint = <&du_out_lvds0>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ lvds_enc_out: endpoint { ++ remote-endpoint = <&lvds_in>; ++ }; ++ }; + }; + }; + -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; ++ lvds { ++ compatible = "lvds-connector"; + -+ csi2_40_ep: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ csi-rate = <300>; ++ width-mm = <210>; ++ height-mm = <158>; ++ ++ panel-timing { ++ /* 1280x800 @60Hz */ ++ clock-frequency = <65000000>; ++ hactive = <1280>; ++ vactive = <800>; ++ hsync-len = <40>; ++ hfront-porch = <80>; ++ hback-porch = <40>; ++ vfront-porch = <14>; ++ vback-porch = <14>; ++ vsync-len = <4>; ++ }; ++ ++ port { ++ lvds_in: endpoint { ++ remote-endpoint = <&lvds_enc_out>; ++ }; + }; + }; -+}; + -diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts -new file mode 100644 -index 0000000..979cebe ---- /dev/null -+++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts -@@ -0,0 +1,578 @@ -+/* -+ * Device Tree Source for the V3MSK Kingfisher board on r8a7797 -+ * -+ * Copyright (C) 2017 Renesas Electronics Corp. -+ * Copyright (C) 2017 Cogent Embedded, Inc. -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ ++ hdmi-out { ++ compatible = "hdmi-connector"; ++ type = "a"; + -+#include "r8a7797-v3msk.dts" ++ port { ++ hdmi_con: endpoint { ++ remote-endpoint = <&adv7511_out>; ++ }; ++ }; ++ }; + -+/ { -+ model = "Renesas V3MSK Kingfisher board based on r8a7797"; -+}; ++ dclkin_p0: clock-out0 { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <148500000>; ++ }; + -+&canfd { -+ pinctrl-0 = <&canfd0_pins &canfd1_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; ++ msiof_ref_clk: msiof-ref-clock { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <66666666>; ++ }; + -+ channel0 { -+ status = "okay"; ++ vcc_3v3: regulator0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-VCC3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; + }; + -+ channel1 { -+ status = "okay"; ++ vcc_vddq_vin0: regulator1 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC-VDDQ-VIN0"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; + }; +}; + -+&csi2_40 { ++&du { ++ pinctrl-0 = <&du_pins>; ++ pinctrl-names = "default"; + status = "okay"; + -+ virtual,channel { -+ csi2_vc0 { -+ data,type = "ycbcr422"; -+ receive,vc = <0>; -+ }; -+ csi2_vc1 { -+ data,type = "ycbcr422"; -+ receive,vc = <1>; -+ }; -+ csi2_vc2 { -+ data,type = "ycbcr422"; -+ receive,vc = <2>; -+ }; -+ csi2_vc3 { -+ data,type = "ycbcr422"; -+ receive,vc = <3>; ++ ports { ++ port@0 { ++ endpoint { ++ remote-endpoint = <&adv7511_in>; ++ }; + }; + }; ++}; + -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ csi2_40_ep: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ csi-rate = <300>; -+ }; -+ }; ++&extal_clk { ++ clock-frequency = <16666666>; +}; + -+&i2c0 { -+ /* i2c0 might conflict with pc9548 reset pin on Kingfisher (uncomment if h/w not patched) */ -+// status = "disabled"; ++&extalr_clk { ++ clock-frequency = <32768>; +}; + -+&i2c3 { -+ pinctrl-0 = <&i2c3_pins>; ++&pfc { ++ pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; -+ status = "okay"; + -+ clock-frequency = <400000>; ++ scif0_pins: scif0 { ++ groups = "scif0_data"; ++ function = "scif0"; ++ }; + -+ i2cswitch4: pca9548@71 { -+ compatible = "nxp,pca9548"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x71>; -+// reset-gpios= <&gpio3 15 GPIO_ACTIVE_LOW>; ++ scif_clk_pins: scif_clk { ++ groups = "scif_clk_b"; ++ function = "scif_clk"; ++ }; + -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <2>; -+ /* Slot B (CN11) */ ++ i2c0_pins: i2c0 { ++ groups = "i2c0"; ++ function = "i2c0"; ++ }; + -+ ov106xx@0 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x60>; ++ avb_pins: avb { ++ groups = "avb0_mdc"; ++ function = "avb0"; ++ }; + -+ port@0 { -+ ov106xx_in0: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin0ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep0>; -+ }; -+ ov106xx_ti964_des0ep0: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep0>; -+ }; -+ ov106xx_ti954_des0ep0: endpoint@2 { -+ remote-endpoint = <&ti954_des0ep0>; -+ }; -+ }; -+ }; ++ du_pins: du { ++ groups = "du_rgb666", "du_sync", "du_clk_out_0"; ++ function = "du"; ++ }; + -+ ov106xx@1 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x61>; ++ sdhi2_pins_3v3: sdhi2_3v3 { ++ groups = "mmc_data8", "mmc_ctrl"; ++ function = "mmc"; ++ power-source = <3300>; ++ }; ++}; + -+ port@0 { -+ ov106xx_in1: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin1ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep1>; -+ }; -+ ov106xx_ti964_des0ep1: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep1>; -+ }; -+ ov106xx_ti954_des0ep1: endpoint@2 { -+ remote-endpoint = <&ti954_des0ep1>; -+ }; -+ }; -+ }; ++&scif0 { ++ pinctrl-0 = <&scif0_pins>; ++ pinctrl-names = "default"; + -+ ov106xx@2 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x62>; ++ status = "okay"; ++}; + -+ port@0 { -+ ov106xx_in2: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin2ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep2>; -+ }; -+ ov106xx_ti964_des0ep2: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep2>; -+ }; -+ }; -+ }; ++&scif_clk { ++ clock-frequency = <14745600>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ pinctrl-0 = <&i2c0_pins>; ++ pinctrl-names = "default"; + -+ ov106xx@3 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x63>; ++ status = "okay"; ++ clock-frequency = <400000>; + -+ port@0 { -+ ov106xx_in3: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin3ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep3>; -+ }; -+ ov106xx_ti964_des0ep3: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep3>; -+ }; -+ }; -+ }; ++ hdmi@39{ ++ compatible = "adi,adv7511w"; ++ #sound-dai-cells = <0>; ++ reg = <0x39>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + -+ /* DS90UB964 @ 0x3a */ -+ ti964-ti9x3@0 { -+ compatible = "ti,ti964-ti9x3"; -+ reg = <0x3a>; -+ ti,sensor_delay = <350>; -+ ti,links = <4>; -+ ti,lanes = <4>; -+ ti,forwarding-mode = "round-robin"; -+ ti,cable-mode = "coax"; ++ adi,input-depth = <8>; ++ adi,input-colorspace = "rgb"; ++ adi,input-clock = "1x"; ++ adi,input-style = <1>; ++ adi,input-justification = "evenly"; + -+ port@0 { -+ ti964_des0ep0: endpoint@0 { -+ ti9x3-addr = <0x0c>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ ti964_des0ep1: endpoint@1 { -+ ti9x3-addr = <0x0d>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ ti964_des0ep2: endpoint@2 { -+ ti9x3-addr = <0x0e>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in2>; -+ }; -+ ti964_des0ep3: endpoint@3 { -+ ti9x3-addr = <0x0f>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in3>; -+ }; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ adv7511_in: endpoint { ++ remote-endpoint = <&lvds_enc_out>; + }; -+ port@1 { -+ ti964_csi0ep0: endpoint { -+ csi-rate = <800>; -+ remote-endpoint = <&csi2_40_ep>; -+ }; ++ }; ++ port@1 { ++ reg = <1>; ++ adv7511_out: endpoint { ++ remote-endpoint = <&hdmi_con>; + }; + }; ++ }; ++ }; ++}; + -+ /* DS90UB954 @ 0x38 */ -+ ti954-ti9x3@0 { -+ compatible = "ti,ti954-ti9x3"; -+ reg = <0x38>; -+ /* gpios = <&video_a_ext1 10 GPIO_ACTIVE_HIGH>; */ -+ ti,sensor_delay = <350>; -+ ti,links = <2>; -+ ti,lanes = <4>; -+ ti,forwarding-mode = "round-robin"; -+ ti,cable-mode = "coax"; ++&wdt0 { ++ status = "okay"; ++}; + -+ port@0 { -+ ti954_des0ep0: endpoint@0 { -+ ti9x3-addr = <0x0c>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ ti954_des0ep1: endpoint@1 { -+ ti9x3-addr = <0x0d>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ }; -+ port@1 { -+ ti954_csi0ep0: endpoint { -+ csi-rate = <800>; -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ }; ++&avb { ++ pinctrl-0 = <&avb_pins>; ++ pinctrl-names = "default"; ++ renesas,no-ether-link; ++ phy-handle = <&phy0>; ++ status = "okay"; ++ phy-int-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>; + -+ /* MAX9286 @ 0x2c */ -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; -+ reg = <0x2c>; -+ maxim,sensor_delay = <350>; -+ maxim,links = <4>; -+ maxim,lanes = <4>; -+ maxim,resetb-gpio = <1>; -+ maxim,fsync-mode = "automatic"; -+ maxim,timeout = <100>; ++ phy0: ethernet-phy@0 { ++ rxc-skew-ps = <1500>; ++ rxdv-skew-ps = <420>; /* default */ ++ rxd0-skew-ps = <420>; /* default */ ++ rxd1-skew-ps = <420>; /* default */ ++ rxd2-skew-ps = <420>; /* default */ ++ rxd3-skew-ps = <420>; /* default */ ++ txc-skew-ps = <900>; /* default */ ++ txen-skew-ps = <420>; /* default */ ++ txd0-skew-ps = <420>; /* default */ ++ txd1-skew-ps = <420>; /* default */ ++ txd2-skew-ps = <420>; /* default */ ++ txd3-skew-ps = <420>; /* default */ ++ reg = <0>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <17 IRQ_TYPE_LEVEL_LOW>; ++ max-speed = <1000>; ++ }; ++}; + -+ port@0 { -+ max9286_des0ep0: endpoint@0 { -+ max9271-addr = <0x50>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ max9286_des0ep1: endpoint@1 { -+ max9271-addr = <0x51>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ max9286_des0ep2: endpoint@2 { -+ max9271-addr = <0x52>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in2>; -+ }; -+ max9286_des0ep3: endpoint@3 { -+ max9271-addr = <0x53>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in3>; -+ }; -+ }; -+ port@1 { -+ max9286_csi0ep0: endpoint { -+ csi-rate = <700>; -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ }; -+ }; ++&sdhi2 { ++ /* used for on-board eMMC */ ++ pinctrl-0 = <&sdhi2_pins_3v3>; ++ pinctrl-names = "default"; + -+ i2c@6 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <6>; -+ /* Slot B (CN11) */ ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_vddq_vin0>; ++ no-1-8-v; ++ cap-mmc-highspeed; ++ bus-width = <8>; ++ non-removable; ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi +new file mode 100644 +index 0000000..4ca502f +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi +@@ -0,0 +1,518 @@ ++/* ++ * Device Tree Source for the H3ULCB Kingfisher board: ++ * this adding conflicting resource on VIN4/VIN5/VIN6/VIN7 for CN11 ++ * use CN11 instead default CN29/CN48 ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ + -+ video_a_ext0: pca9535@27 { -+ compatible = "nxp,pca9535"; -+ reg = <0x27>; -+ gpio-controller; -+ #gpio-cells = <2>; ++&i2cswitch4 { ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ /* Slot B (CN11) */ + -+ video_a_des_cfg1 { -+ gpio-hog; -+ gpios = <5 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A cfg1"; -+ }; -+ video_a_des_cfg0 { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A cfg0"; ++ ov106xx@4 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x64>; ++ ++ port@0 { ++ ov106xx_in4: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin4ep0>; + }; -+ video_a_pwr_shdn { -+ gpio-hog; -+ gpios = <3 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR_SHDN"; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; + }; -+ video_a_cam_pwr0 { -+ gpio-hog; -+ gpios = <12 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR0"; ++ ov106xx_ti964_des1ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep0>; + }; -+ video_a_cam_pwr1 { -+ gpio-hog; -+ gpios = <13 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR1"; ++ ov106xx_ti954_des1ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep0>; + }; -+ video_a_cam_pwr2 { -+ gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR2"; ++ }; ++ }; ++ ++ ov106xx@5 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x65>; ++ ++ port@0 { ++ ov106xx_in5: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin5ep0>; + }; -+ video_a_cam_pwr3 { -+ gpio-hog; -+ gpios = <15 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR3"; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; + }; -+ video_a_des_shdn { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A DES_SHDN"; ++ ov106xx_ti964_des1ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep1>; + }; -+ video_a_des_led { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "Video-A led"; ++ ov106xx_ti954_des1ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep1>; + }; + }; ++ }; + -+ video_a_ext1: max7325@5c { -+ compatible = "maxim,max7325"; -+ reg = <0x5c>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ video_a_des_cfg2 { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A cfg2"; ++ ov106xx@6 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x66>; ++ port@0 { ++ ov106xx_in6: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin6ep0>; + }; -+ video_a_des_cfg1 { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A cfg1"; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; + }; -+ video_a_des_cfg0 { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A cfg0"; ++ ov106xx_ti964_des1ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep2>; + }; -+ video_a_pwr_shdn { -+ gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR_SHDN"; ++ }; ++ }; ++ ++ ov106xx@7 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x67>; ++ port@0 { ++ ov106xx_in7: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin7ep0>; + }; -+ video_a_cam_pwr0 { -+ gpio-hog; -+ gpios = <8 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR0"; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; + }; -+ video_a_cam_pwr1 { -+ gpio-hog; -+ gpios = <9 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR1"; ++ ov106xx_ti964_des1ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep3>; + }; -+ video_a_cam_pwr2 { -+ gpio-hog; -+ gpios = <10 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR2"; ++ }; ++ }; ++ ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@1 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti964_des1ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in4>; + }; -+ video_a_cam_pwr3 { -+ gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR3"; ++ ti964_des1ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in5>; + }; -+ video_a_des_shdn { -+ gpio-hog; -+ gpios = <13 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A DES_SHDN"; ++ ti964_des1ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in6>; + }; -+ video_a_led { -+ gpio-hog; -+ gpios = <12 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "Video-A LED"; ++ ti964_des1ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ ti964_csi2ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_41_ep>; + }; + }; + }; -+ }; -+}; + -+&pfc { -+ canfd0_pins: canfd0 { -+ groups = "canfd0_data_a"; -+ function = "canfd0"; -+ }; ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@1 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_b_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; + -+ canfd1_pins: canfd1 { -+ groups = "canfd1_data"; -+ function = "canfd1"; -+ }; ++ port@0 { ++ ti954_des1ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ ti954_des1ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ }; ++ port@1 { ++ ti954_csi2ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; + -+ i2c3_pins: i2c3 { -+ groups = "i2c3"; -+ function = "i2c3"; ++ /* MAX9286 @ 0x2c */ ++ max9286-max9271@1 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des1ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ max9286_des1ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ max9286_des1ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ max9286_des1ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ max9286_csi2ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; + }; -+}; -+ -+&vin0 { -+ status = "okay"; + -+ ports { ++ i2c@6 { + #address-cells = <1>; + #size-cells = <0>; ++ reg = <6>; ++ /* Slot B (CN11) */ + -+ port@0 { -+ vin0ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in0>; ++ video_b_ext0: pca9535@27 { ++ compatible = "nxp,pca9535"; ++ reg = <0x27>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_b_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg1"; + }; -+ }; -+ port@1 { -+ csi0ep0: endpoint { -+ remote-endpoint = <&csi2_40_ep>; ++ video_b_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg0"; ++ }; ++ video_b_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR_SHDN"; ++ }; ++ video_b_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR0"; ++ }; ++ video_b_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR1"; ++ }; ++ video_b_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR2"; ++ }; ++ video_b_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR3"; ++ }; ++ video_b_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B DES_SHDN"; ++ }; ++ video_b_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B led"; + }; + }; -+ port@2 { -+ vin0_max9286_des0ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep0>; ++ ++ video_b_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_b_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg2"; + }; -+ vin0_ti964_des0ep0: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep0>; ++ video_b_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg1"; + }; -+ vin0_ti954_des0ep0: endpoint@2 { -+ remote-endpoint = <&ti954_des0ep0>; ++ video_b_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg0"; ++ }; ++ video_b_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR_SHDN"; ++ }; ++ video_b_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR0"; ++ }; ++ video_b_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR1"; ++ }; ++ video_b_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR2"; ++ }; ++ video_b_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR3"; ++ }; ++ video_b_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B DES_SHDN"; ++ }; ++ video_b_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B LED"; + }; + }; + }; +}; + -+&vin1 { -+ status = "okay"; -+ ++&vin4 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { -+ vin1ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <1>; ++ vin4ep0: endpoint { ++ csi,select = "csi41"; ++ virtual,channel = <0>; ++ remote-endpoint = <&ov106xx_in4>; + data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in1>; + }; + }; + port@1 { -+ csi0ep1: endpoint { -+ remote-endpoint = <&csi2_40_ep>; ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_41_ep>; + }; + }; + port@2 { -+ vin1_max9286_des0ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep1>; ++ vin4_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; + }; -+ vin1_ti964_des0ep1: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep1>; ++ vin4_ti964_des1ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep0>; + }; -+ vin1_ti954_des0ep1: endpoint@2 { -+ remote-endpoint = <&ti954_des0ep1>; ++ vin4_ti954_des1ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep0>; + }; + }; + }; +}; + -+&vin2 { -+ status = "okay"; -+ ++&vin5 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { -+ vin2ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <2>; ++ vin5ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <1>; ++ remote-endpoint = <&ov106xx_in5>; + data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in2>; + }; + }; + port@1 { -+ csi0ep2: endpoint { -+ remote-endpoint = <&csi2_40_ep>; ++ csi2ep1: endpoint { ++ remote-endpoint = <&csi2_41_ep>; + }; + }; + port@2 { -+ vin2_max9286_des0ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep2>; ++ vin5_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; + }; -+ vin2_ti964_des0ep2: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep2>; ++ vin5_ti964_des1ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep1>; ++ }; ++ vin5_ti954_des1ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep1>; + }; + }; + }; +}; + -+&vin3 { ++&vin6 { + status = "okay"; + + ports { @@ -14642,69 +12569,61 @@ index 0000000..979cebe + #size-cells = <0>; + + port@0 { -+ vin3ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <3>; ++ vin6ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <2>; ++ remote-endpoint = <&ov106xx_in6>; + data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in3>; + }; + }; + port@1 { -+ csi0ep3: endpoint { -+ remote-endpoint = <&csi2_40_ep>; ++ csi2ep2: endpoint { ++ remote-endpoint = <&csi2_41_ep>; + }; + }; + port@2 { -+ vin3_max9286_des0ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep3>; ++ vin6_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; + }; -+ vin3_ti964_des0ep3: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep3>; ++ vin6_ti964_des1ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep2>; + }; + }; + }; +}; -diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vb.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vb.dts -new file mode 100644 -index 0000000..1b531d8 ---- /dev/null -+++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vb.dts -@@ -0,0 +1,498 @@ -+/* -+ * Device Tree Source for the V3MSK Videobox board on r8a7797 -+ * -+ * Copyright (C) 2017 Cogent Embedded, Inc. -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ -+ -+#include "r8a7797-v3msk.dts" -+ -+/ { -+ model = "Renesas V3MSK Videobox board based on r8a7797"; -+ -+ aliases { -+ serial1 = &scif3; -+ }; -+}; + -+&canfd { -+ pinctrl-0 = <&canfd0_pins &canfd1_pins>; -+ pinctrl-names = "default"; ++&vin7 { + status = "okay"; + -+ channel0 { -+ status = "okay"; -+ }; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ channel1 { -+ status = "okay"; ++ port@0 { ++ vin7ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <3>; ++ remote-endpoint = <&ov106xx_in7>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep3: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin7_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ vin7_ti964_des1ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep3>; ++ }; ++ }; + }; +}; + -+&csi2_40 { ++&csi2_41 { + status = "okay"; + + virtual,channel { @@ -14730,1200 +12649,1351 @@ index 0000000..1b531d8 + #address-cells = <1>; + #size-cells = <0>; + -+ csi2_40_ep: endpoint { ++ csi2_41_ep: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + csi-rate = <300>; + }; + }; +}; +diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi +new file mode 100644 +index 0000000..4af5ca0 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi +@@ -0,0 +1,30 @@ ++/* ++ * Device Tree Source for the H3/M3ULCB Kingfisher board: ++ * this overrides GPS in favour MOST on GP5_24/GP5_25 R-CAR pins ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++&pfc { ++ mlp_pins: mlp { ++ groups = "mlb_3pin"; ++ function = "mlb_3pin"; ++ }; ++}; + -+&i2c1 { -+ pinctrl-0 = <&i2c1_pins>; ++&scif1 { ++ status = "disabled"; ++}; ++ ++&mlp { ++ pinctrl-0 = <&mlp_pins>; + pinctrl-names = "default"; + status = "okay"; + -+ clock-frequency = <100000>; ++ clock-speed = "1024fs"; ++}; +diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi +new file mode 100644 +index 0000000..b854216 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi +@@ -0,0 +1,46 @@ ++/* ++ * Device Tree Source for the H3/M3ULCB Kingfisher board: ++ * this overrides WIFI in favour SD on SDHI3 ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ + -+ i2cswitch1: i2c-switch@74 { -+ compatible = "nxp,pca9548"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x74>; -+ reset-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; ++&sdio_switch { ++ regulator-name = "sd_on"; ++ enable-active-high; ++}; + -+ i2c@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; ++&vccq_sdhi3 { ++ compatible = "regulator-gpio"; + -+ ov106xx@0 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x60>; ++ regulator-min-microvolt = <1800000>; + -+ port@0 { -+ ov106xx_in0: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin0ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep0>; -+ }; -+ ov106xx_ti964_des0ep0: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep0>; -+ }; -+ }; -+ }; ++ gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; ++ gpios-states = <1>; ++ states = <3300000 1 ++ 1800000 0>; ++}; + -+ ov106xx@1 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x61>; ++&sdhi3 { ++ /delete-property/non-removable; ++ /delete-property/cap-power-off-card; ++ /delete-property/keep-power-in-suspend; ++ /delete-property/enable-sdio-wakeup; ++ /delete-property/max-frequency; ++ /delete-property/no-1-8-v; + -+ port@0 { -+ ov106xx_in1: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin1ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep1>; -+ }; -+ ov106xx_ti964_des0ep1: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep1>; -+ }; -+ }; -+ }; ++ vmmc-supply = <&vcc_sdhi3>; ++ cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; ++ wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; ++// sd-uhs-sdr50; ++// sd-uhs-sdr104; ++}; + -+ ov106xx@2 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x62>; ++&wlcore { ++ status = "disabled"; ++}; +diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +new file mode 100644 +index 0000000..8ffafb2 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +@@ -0,0 +1,1529 @@ ++/* ++ * Device Tree Source for the ULCB Kingfisher board ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ + -+ port@0 { -+ ov106xx_in2: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin2ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep2>; -+ }; -+ ov106xx_ti964_des0ep2: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep2>; -+ }; -+ }; -+ }; ++/ { ++ aliases { ++ serial1 = &hscif0; ++ serial2 = &hscif1; ++ serial3 = &scif1; ++ }; + -+ ov106xx@3 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x63>; ++ snd_clk: snd_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24576000>; ++ clock-output-names = "scki"; ++ }; + -+ port@0 { -+ ov106xx_in3: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin3ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des0ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep3>; -+ }; -+ ov106xx_ti964_des0ep3: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep3>; -+ }; -+ }; -+ }; ++ wlan_en: regulator@4 { ++ compatible = "regulator-fixed"; ++ regulator-name = "wlan-en-regulator"; + -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; -+ reg = <0x2c>; -+ maxim,sensor_delay = <350>; -+ maxim,links = <4>; -+ maxim,lanes = <4>; -+ maxim,resetb-gpio = <1>; -+ maxim,fsync-mode = "automatic"; -+ maxim,timeout = <100>; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ext_74 4 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ vcc_sdhi3: regulator@41 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "SDHI3 Vcc"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ vccq_sdhi3: regulator@5 { ++ compatible = "regulator-fixed"; + -+ port@0 { -+ max9286_des0ep0: endpoint@0 { -+ max9271-addr = <0x50>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ max9286_des0ep1: endpoint@1 { -+ max9271-addr = <0x51>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ max9286_des0ep2: endpoint@2 { -+ max9271-addr = <0x52>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in2>; -+ }; -+ max9286_des0ep3: endpoint@3 { -+ max9271-addr = <0x53>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in3>; -+ }; -+ }; -+ port@1 { -+ max9286_csi0ep0: endpoint { -+ csi-rate = <700>; -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ }; ++ regulator-name = "SDHI3 VccQ"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; + -+ ti964-ti9x3@0 { -+ compatible = "ti,ti964-ti9x3"; -+ reg = <0x3a>; -+ ti,sensor_delay = <350>; -+ ti,links = <4>; -+ ti,lanes = <4>; -+ ti,forwarding-mode = "round-robin"; -+ ti,cable-mode = "coax"; ++ codec_en_reg: regulator@6 { ++ compatible = "regulator-fixed"; ++ regulator-name = "codec-en-regulator"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; + -+ port@0 { -+ ti964_des0ep0: endpoint@0 { -+ ti9x3-addr = <0x0c>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ ti964_des0ep1: endpoint@1 { -+ ti9x3-addr = <0x0d>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ ti964_des0ep2: endpoint@2 { -+ ti9x3-addr = <0x0e>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in2>; -+ }; -+ ti964_des0ep3: endpoint@3 { -+ ti9x3-addr = <0x0f>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in3>; -+ }; -+ }; -+ port@1 { -+ ti964_csi0ep0: endpoint { -+ csi-rate = <1450>; -+ remote-endpoint = <&csi2_40_ep>; -+ }; -+ }; -+ }; -+ }; ++ gpio = <&gpio_ext_74 15 0>; + -+ i2c@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; ++ /* delay - CHECK */ ++ startup-delay-us = <70000>; ++ enable-active-high; ++ }; + -+ gpio_exp_6c: gpio@6c { -+ compatible = "maxim,max7325"; -+ reg = <0x6c>; -+ gpio-controller; -+ #gpio-cells = <2>; ++ amp_en_reg: regulator@7 { ++ compatible = "regulator-fixed"; ++ regulator-name = "amp-en-regulator"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; + -+ virq { -+ gpio-hog; -+ gpios = <5 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video VIRQ"; -+ }; -+ des_cfg { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video CNFG0"; -+ }; -+ pwr_shdn { -+ gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video PWR_SHDN"; -+ }; -+ cam_pwr0 { -+ gpio-hog; -+ gpios = <8 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video PWR0"; -+ }; -+ cam_pwr1 { -+ gpio-hog; -+ gpios = <9 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video PWR1"; -+ }; -+ cam_pwr2 { -+ gpio-hog; -+ gpios = <10 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video PWR2"; -+ }; -+ cam_pwr3 { -+ gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video PWR3"; -+ }; -+ des_shdn { -+ gpio-hog; -+ gpios = <13 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video DES_SHDN"; -+ }; -+ fpdl_shdn { -+ gpio-hog; -+ gpios = <15 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video FPDL_SHDN"; -+ }; -+ }; -+ }; ++ gpio = <&gpio_ext_74 0 0>; ++ ++ startup-delay-us = <0>; ++ enable-active-high; + }; -+}; + -+&gpio0 { -+ can0stby { -+ gpio-hog; -+ gpios = <12 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "CAN0STBY"; ++ sdio_switch: regulator@9 { ++ compatible = "regulator-fixed"; ++ regulator-name = "wifi_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_74 5 0>; ++ enable-active-low; ++ regulator-always-on; + }; + -+ can1_load { -+ gpio-hog; -+ gpios = <13 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "can1_120R_load"; ++ radio_switch: regulator@11 { ++ compatible = "regulator-fixed"; ++ regulator-name = "radio_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_74 13 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ regulator-always-on; + }; -+}; + -+&gpio2 { -+ can0_load { -+ gpio-hog; -+ gpios = <16 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "can0_120R_load"; ++ mpcie_3v3: regulator@12 { ++ compatible = "regulator-fixed"; ++ regulator-name = "mPCIe 3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio_ext_77 14 GPIO_ACTIVE_HIGH>; ++ enable-active-high; + }; -+}; + -+&pfc { -+ canfd0_pins: canfd0 { -+ groups = "canfd0_data_a"; -+ function = "canfd0"; ++ mpcie_1v8: regulator@13 { ++ compatible = "regulator-fixed"; ++ regulator-name = "mPCIe 1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ gpio = <&gpio_ext_77 15 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <200000>; ++ enable-active-high; + }; + -+ canfd1_pins: canfd1 { -+ groups = "canfd1_data"; -+ function = "canfd1"; ++ kim { ++ compatible = "kim"; ++ shutdown-gpios = <&gpio_ext_74 3 GPIO_ACTIVE_HIGH>; ++ /* serial1 */ ++ dev_name = "/dev/ttySC1"; ++ flow_cntrl = <1>; ++ /* int div 8 hscif@26.6666656MHz */ ++ baud_rate = <3333332>; + }; + -+ i2c1_pins: i2c1 { -+ groups = "i2c1"; -+ function = "i2c1"; ++ btwilink { ++ compatible = "btwilink"; + }; + -+ scif3_pins: scif3 { -+ groups = "scif3_data"; -+ function = "scif3"; ++ sound_ext: sound@0 { ++ pinctrl-0 = <&sound_0_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; ++ ++ simple-audio-card,format = "left_j"; ++ simple-audio-card,name = "pcm3168a"; ++ ++ simple-audio-card,bitclock-master = <&sound_ext_master>; ++ simple-audio-card,frame-master = <&sound_ext_master>; ++ sound_ext_master: simple-audio-card,cpu@0 { ++ sound-dai = <&rcar_sound 0>; ++ dai-tdm-slot-num = <8>; ++ dai-tdm-slot-width = <32>; ++ }; ++ ++ simple-audio-card,codec@0 { ++ sound-dai = <&pcm3168a>; ++ dai-tdm-slot-num = <8>; ++ dai-tdm-slot-width = <32>; ++ system-clock-frequency = <24576000>; ++ }; + }; -+}; + -+&scif3 { -+ pinctrl-0 = <&scif3_pins>; -+ pinctrl-names = "default"; ++ /delete-node/sound; + -+ status = "okay"; -+}; ++ rsnd_ak4613: sound@1 { ++ pinctrl-0 = <&sound_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; + -+&vin0 { -+ status = "okay"; ++ simple-audio-card,format = "left_j"; ++ simple-audio-card,name = "ak4613"; + -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; ++ simple-audio-card,bitclock-master = <&sndcpu>; ++ simple-audio-card,frame-master = <&sndcpu>; + -+ port@0 { -+ vin0ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in0>; -+ }; -+ }; -+ port@1 { -+ csi0ep0: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; ++ sndcpu: simple-audio-card,cpu@1 { ++ sound-dai = <&rcar_sound 1>; + }; -+ port@2 { -+ vin0_max9286_des0ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep0>; -+ }; -+ vin0_ti964_des0ep0: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep0>; -+ }; ++ ++ sndcodec: simple-audio-card,codec@1 { ++ sound-dai = <&ak4613>; + }; + }; -+}; + -+&vin1 { -+ status = "okay"; ++ sound_radio: sound@2 { ++ pinctrl-0 = <&sound_2_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; + -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "radio"; + -+ port@0 { -+ vin1ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <1>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in1>; -+ }; -+ }; -+ port@1 { -+ csi0ep1: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; ++ simple-audio-card,bitclock-master = <&sound_radio_master>; ++ simple-audio-card,frame-master = <&sound_radio_master>; ++ simple-audio-card,cpu@2 { ++ sound-dai = <&rcar_sound 2>; + }; -+ port@2 { -+ vin1_max9286_des0ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep1>; -+ }; -+ vin1_ti964_des0ep1: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep1>; -+ }; ++ ++ sound_radio_master: simple-audio-card,codec@2 { ++ sound-dai = <&radio>; ++ system-clock-frequency = <12288000>; + }; + }; -+}; + -+&vin2 { -+ status = "okay"; ++ sound_wl18xx: sound@3 { ++ pinctrl-0 = <&sound_3_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; + -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "wl18xx"; + -+ port@0 { -+ vin2ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <2>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in2>; -+ }; ++ simple-audio-card,bitclock-master = <&sound_wl18xx_master>; ++ simple-audio-card,frame-master = <&sound_wl18xx_master>; ++ sound_wl18xx_master: simple-audio-card,cpu@3 { ++ sound-dai = <&rcar_sound 3>; + }; -+ port@1 { -+ csi0ep2: endpoint { -+ remote-endpoint = <&csi2_40_ep>; -+ }; ++ ++ simple-audio-card,codec@3 { ++ sound-dai = <&wl18xx_pcm>; + }; -+ port@2 { -+ vin2_max9286_des0ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ ++ lvds-encoder { ++ compatible = "thine,thc63lvdm83d"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port@0 { ++ reg = <0>; ++ lvds_enc_in: endpoint { ++ remote-endpoint = <&du_out_lvds0>; ++ }; + }; -+ vin2_ti964_des0ep2: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep2>; ++ port@1 { ++ reg = <1>; ++ lvds_enc_out: endpoint { ++ remote-endpoint = <&lvds_in>; ++ }; + }; + }; + }; -+}; + -+&vin3 { -+ status = "okay"; ++ lvds { ++ compatible = "lvds-connector"; + -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; ++ width-mm = <210>; ++ height-mm = <158>; + -+ port@0 { -+ vin3ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <3>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in3>; -+ }; ++ panel-timing { ++ /* 1280x800 @60Hz */ ++ clock-frequency = <65000000>; ++ hactive = <1280>; ++ vactive = <800>; ++ hsync-len = <40>; ++ hfront-porch = <80>; ++ hback-porch = <40>; ++ vfront-porch = <14>; ++ vback-porch = <14>; ++ vsync-len = <4>; + }; -+ port@1 { -+ csi0ep3: endpoint { -+ remote-endpoint = <&csi2_40_ep>; ++ ++ port { ++ lvds_in: endpoint { ++ remote-endpoint = <&lvds_enc_out>; + }; + }; -+ port@2 { -+ vin3_max9286_des0ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep3>; -+ }; -+ vin3_ti964_des0ep3: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ ++ hdmi-out { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con: endpoint { ++ remote-endpoint = <&adv7513_out>; + }; + }; + }; ++ ++ radio: si468x@0 { ++ compatible = "si,si468x-pcm"; ++ status = "okay"; ++ ++ #sound-dai-cells = <0>; ++ }; ++ ++ wl18xx_pcm: wl18xx_pcm@0 { ++ compatible = "ti,wl18xx-pcm"; ++ status = "okay"; ++ ++ #sound-dai-cells = <0>; ++ }; ++ ++ camera_clk: camera_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24000000>; ++ clock-output-names = "mclk"; ++ }; +}; -diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts -new file mode 100644 -index 0000000..bf2501e ---- /dev/null -+++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts -@@ -0,0 +1,320 @@ -+/* -+ * Device Tree Source for the V3M Starter Kit board on r8a7797 -+ * -+ * Copyright (C) 2017 Renesas Electronics Corp. -+ * Copyright (C) 2017 Cogent Embedded, Inc. -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ + -+/dts-v1/; -+#include "r8a7797.dtsi" -+#include ++&pfc { ++ scif1_pins: scif1 { ++ groups = "scif1_data_b"; ++ function = "scif1"; ++ }; ++ ++ hscif0_pins: hscif0 { ++ groups = "hscif0_data", "hscif0_ctrl"; ++ function = "hscif0"; ++ }; ++ ++ hscif1_pins: hscif1 { ++ groups = "hscif1_data_a", "hscif1_ctrl_a"; ++ function = "hscif1"; ++ }; ++ ++ du_pins: du { ++ groups = "du_rgb888", "du_sync", "du_clk_out_0", "du_disp"; ++ function = "du"; ++ }; ++ ++ sdhi3_pins_3v3: sd3_3v3 { ++ groups = "sdhi3_data4", "sdhi3_ctrl"; ++ function = "sdhi3"; ++ power-source = <3300>; ++ }; ++ ++ sdhi3_pins_1v8: sd3_1v8 { ++ groups = "sdhi3_data4", "sdhi3_ctrl"; ++ function = "sdhi3"; ++ power-source = <1800>; ++ }; ++ ++ sound_0_pins: sound0 { ++ groups = "ssi349_ctrl", "ssi3_data", "ssi4_data"; ++ function = "ssi"; ++ }; ++ ++ /* sound_pins defined in H3 or M3 ulsb file */ + -+/ { -+ model = "Renesas V3M Starter Kit board based on r8a7797"; -+ compatible = "renesas,v3msk", "renesas,r8a7797"; ++ sound_2_pins: sound2 { ++ groups = "ssi6_ctrl", "ssi6_data"; ++ function = "ssi"; ++ }; + -+ aliases { -+ serial0 = &scif0; -+ ethernet0 = &avb; ++ sound_3_pins: sound3 { ++ groups = "ssi78_ctrl", "ssi7_data", "ssi8_data"; ++ function = "ssi"; + }; + -+ chosen { -+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; -+ stdout-path = "serial0:115200n8"; ++ usb0_pins: usb0 { ++ groups = "usb0"; ++ function = "usb0"; + }; + -+ memory@48000000 { -+ device_type = "memory"; -+ /* first 128MB is reserved for secure area. */ -+ reg = <0x0 0x48000000 0x0 0x38000000>; ++ can0_pins: can0 { ++ groups = "can0_data_a"; ++ function = "can0"; + }; + -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; ++ can1_pins: can1 { ++ groups = "can1_data"; ++ function = "can1"; ++ }; + -+ /* device specific region for Lossy Decompression */ -+ lossy_decompress: linux,lossy_decompress { -+ no-map; -+ reg = <0x00000000 0x64000000 0x0 0x03000000>; -+ }; ++ canfd0_pins: canfd0 { ++ groups = "canfd0_data_a"; ++ function = "canfd0"; ++ }; + -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ reg = <0x00000000 0x67000000 0x0 0x09000000>; -+ linux,cma-default; -+ }; ++ canfd1_pins: canfd1 { ++ groups = "canfd1_data"; ++ function = "canfd1"; ++ }; + -+ /* device specific region for contiguous allocations */ -+ linux,multimedia { -+ compatible = "shared-dma-pool"; -+ reusable; -+ reg = <0x00000000 0x70000000 0x0 0x10000000>; -+ }; ++ vin5_pins: vin5 { ++ groups = "vin5_data8", "vin5_sync", "vin5_clk"; ++ function = "vin5"; + }; ++}; + -+ mmngr { -+ compatible = "renesas,mmngr"; -+ memory-region = <&lossy_decompress>; ++&du { ++ pinctrl-0 = <&du_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&gpio2 { ++ bl_pwm { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "BL PWM 100%"; + }; ++}; + -+ mmngrbuf { -+ compatible = "renesas,mmngrbuf"; ++&gpio4 { ++ most_rst { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "MOST RST"; + }; ++}; + -+ vspm_if { -+ compatible = "renesas,vspm_if"; ++&gpio6 { ++ audio_sw { ++ gpio-hog; ++ gpios = <21 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Onboard MCh Audio"; + }; ++}; + -+ lvds-encoder { -+ compatible = "thine,thc63lvdm83d"; ++&scif1 { ++ pinctrl-0 = <&scif1_pins>; ++ pinctrl-names = "default"; + -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; ++ status = "okay"; ++}; + -+ port@0 { -+ reg = <0>; -+ lvds_enc_in: endpoint { -+ remote-endpoint = <&du_out_lvds0>; -+ }; -+ }; -+ port@1 { -+ reg = <1>; -+ lvds_enc_out: endpoint { -+ remote-endpoint = <&lvds_in>; -+ }; -+ }; -+ }; -+ }; ++&hscif0 { ++ pinctrl-0 = <&hscif0_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; + -+ lvds { -+ compatible = "lvds-connector"; ++ status = "okay"; ++}; + -+ width-mm = <210>; -+ height-mm = <158>; ++&hscif1 { ++ pinctrl-0 = <&hscif1_pins>; ++ pinctrl-names = "default"; + -+ panel-timing { -+ /* 1280x800 @60Hz */ -+ clock-frequency = <65000000>; -+ hactive = <1280>; -+ vactive = <800>; -+ hsync-len = <40>; -+ hfront-porch = <80>; -+ hback-porch = <40>; -+ vfront-porch = <14>; -+ vback-porch = <14>; -+ vsync-len = <4>; ++ status = "okay"; ++}; ++ ++&i2c2 { ++ clock-frequency = <400000>; ++ ++ gpio_ext_74: pca9539@74 { ++ compatible = "nxp,pca9539"; ++ reg = <0x74>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio6>; ++ interrupts = <8 IRQ_TYPE_EDGE_FALLING>; ++ ++ hub_pwen { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "HUB pwen"; ++ }; ++ hub_rst { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "HUB rst"; ++ }; ++ otg_offvbus { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "OTG off VBUSn"; ++ }; ++ otg_extlpn { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "OTG EXTLPn"; ++ }; ++ otg_stat1 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "OTG Stat1"; ++ }; ++ otg_stat2 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "OTG Stat2"; + }; ++ }; + -+ port { -+ lvds_in: endpoint { -+ remote-endpoint = <&lvds_enc_out>; -+ }; ++ gpio_ext_75: pca9539@75 { ++ compatible = "nxp,pca9539"; ++ reg = <0x75>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio6>; ++ interrupts = <4 IRQ_TYPE_EDGE_FALLING>; ++ ++ gps_rst { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "GPS rst"; ++ }; ++ fpdl_shdn { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "FPDLink shdn"; + }; + }; + -+ hdmi-out { -+ compatible = "hdmi-connector"; -+ type = "a"; ++ i2cswitch2: pca9548@71 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x71>; ++ reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + -+ port { -+ hdmi_con: endpoint { -+ remote-endpoint = <&adv7511_out>; -+ }; ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ /* BCM node(s) */ ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ /* USB3.0 HUB node(s) */ ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ /* Power amp node(s) */ + }; -+ }; + -+ dclkin_p0: clock-out0 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <148500000>; -+ }; ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ /* Radio node(s) */ ++ }; + -+ msiof_ref_clk: msiof-ref-clock { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <66666666>; -+ }; ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; + -+ vcc_3v3: regulator0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-VCC3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; ++ hdmi@3d { ++ compatible = "adi,adv7511w"; ++ reg = <0x3d>; ++// interrupt-parent = <&gpio2>; ++// interrupts = <0 IRQ_TYPE_EDGE_BOTH>; ++ pd-gpios = <&gpio_ext_75 5 GPIO_ACTIVE_LOW>; + -+ vcc_vddq_vin0: regulator1 { -+ compatible = "regulator-fixed"; -+ regulator-name = "VCC-VDDQ-VIN0"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+}; ++ adi,input-depth = <8>; ++ adi,input-colorspace = "rgb"; ++ adi,input-clock = "1x"; ++ adi,input-style = <1>; ++ adi,input-justification = "evenly"; ++ adi,clock-delay = <1200>; ++ adi,clock-max-rate = <100000>; + -+&du { -+ pinctrl-0 = <&du_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ ports { -+ port@0 { -+ endpoint { -+ remote-endpoint = <&adv7511_in>; ++ port@0 { ++ reg = <0>; ++ adv7513_in: endpoint { ++ remote-endpoint = <&du_out_rgb>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ adv7513_out: endpoint { ++ remote-endpoint = <&hdmi_con>; ++ }; ++ }; ++ }; + }; + }; -+ }; -+}; -+ -+&extal_clk { -+ clock-frequency = <16666666>; -+}; + -+&extalr_clk { -+ clock-frequency = <32768>; -+}; ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ /* PCIe node(s) */ ++ }; + -+&pfc { -+ pinctrl-0 = <&scif_clk_pins>; -+ pinctrl-names = "default"; ++ i2c@6 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <6>; ++ /* LVDS display node(s) */ + -+ scif0_pins: scif0 { -+ groups = "scif0_data"; -+ function = "scif0"; -+ }; ++ polytouch: edt-ft5x06@38 { ++ compatible = "edt,edt-ft5x06"; ++ reg = <0x38>; ++ interrupt-parent = <&gpio5>; ++ interrupts = <6 IRQ_TYPE_EDGE_FALLING>; ++ }; ++ }; + -+ scif_clk_pins: scif_clk { -+ groups = "scif_clk_b"; -+ function = "scif_clk"; -+ }; ++ i2c@7 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <7>; ++ /* Audio, GPS and Gyro node(s) */ + -+ i2c0_pins: i2c0 { -+ groups = "i2c0"; -+ function = "i2c0"; -+ }; ++ pcm3168a: audio-codec@44 { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm3168a"; ++ reg = <0x44>; ++ clocks = <&snd_clk>; ++ clock-names = "scki"; ++ tdm; ++ VDD1-supply = <&codec_en_reg>; ++ VDD2-supply = <&codec_en_reg>; ++ VCCAD1-supply = <&codec_en_reg>; ++ VCCAD2-supply = <&codec_en_reg>; ++ VCCDA1-supply = <&_en_reg>; ++ VCCDA2-supply = <&_en_reg>; ++ }; + -+ avb_pins: avb { -+ groups = "avb0_mdc"; -+ function = "avb0"; -+ }; ++ lsm9ds0_acc_mag@1d { ++ compatible = "st,lsm9ds0_accel_magn"; ++ reg = <0x1d>; ++ }; + -+ du_pins: du { -+ groups = "du_rgb666", "du_sync", "du_clk_out_0"; -+ function = "du"; -+ }; ++ lsm9ds0_gyr@6b { ++ compatible = "st,lsm9ds0_gyro"; ++ reg = <0x6b>; ++ }; + -+ sdhi2_pins_3v3: sdhi2_3v3 { -+ groups = "mmc_data8", "mmc_ctrl"; -+ function = "mmc"; -+ power-source = <3300>; ++ /* GPS@ 0x42 */ ++ }; + }; +}; + -+&scif0 { -+ pinctrl-0 = <&scif0_pins>; -+ pinctrl-names = "default"; -+ -+ status = "okay"; -+}; ++&i2c4 { ++ gpio_ext_76: pca9539@76 { ++ compatible = "nxp,pca9539"; ++ reg = <0x76>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio7>; ++ interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + -+&scif_clk { -+ clock-frequency = <14745600>; -+ status = "okay"; -+}; ++ port_b_a0 { ++ gpio-hog; ++ gpios = <0 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B A0"; ++ }; ++ port_b_a1 { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B A1"; ++ }; ++ port_a_a0 { ++ gpio-hog; ++ gpios = <2 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A A0"; ++ }; ++ port_a_a1 { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A A1"; ++ }; ++ cmos_pwdn { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CMOS PWDN"; ++ }; ++ cmos_rst { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CMOS RST"; ++ }; ++ /* pin 12 - CAM_CLK */ ++ rpi_cam_io_1 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "RaspB_IO1"; ++ }; ++ /* pin 11 - CAM_GPIO - assume pwdn */ ++ rpi_cam_io_0 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "RaspB_IO0"; ++ }; ++ sam_rst { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "SAM RST"; ++ }; ++ sam_pwr { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "SAM PWR"; ++ }; ++ /* 0 - FPDLink output, 1 - LVDS output */ ++ lvds_vs_fpdl { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "LVDS switch"; ++ }; ++ }; + -+&i2c0 { -+ pinctrl-0 = <&i2c0_pins>; -+ pinctrl-names = "default"; ++ gpio_ext_77: pca9539@77 { ++ compatible = "nxp,pca9539"; ++ reg = <0x77>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio5>; ++ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + -+ status = "okay"; -+ clock-frequency = <400000>; ++ mpcie_wake { ++ gpio-hog; ++ gpios = <0 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "mPCIe WAKE#"; ++ }; ++ mpcie_wdisable { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "mPCIe W_DISABLE"; ++ }; ++ mpcie_clreq { ++ gpio-hog; ++ gpios = <2 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "mPCIe CLKREQ#"; ++ }; ++ mpcie_ovc { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "mPCIe OVC"; ++ }; ++ }; + -+ hdmi@39{ -+ compatible = "adi,adv7511w"; -+ #sound-dai-cells = <0>; -+ reg = <0x39>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>; ++ i2cswitch4: pca9548@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x71>; ++ reset-gpios= <&gpio3 15 GPIO_ACTIVE_LOW>; + -+ adi,input-depth = <8>; -+ adi,input-colorspace = "rgb"; -+ adi,input-clock = "1x"; -+ adi,input-style = <1>; -+ adi,input-justification = "evenly"; ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ /* SAM node(s) */ ++ }; + -+ ports { ++ i2c@1 { + #address-cells = <1>; + #size-cells = <0>; ++ reg = <1>; ++ /* Slot A (CN10) */ + -+ port@0 { -+ reg = <0>; -+ adv7511_in: endpoint { -+ remote-endpoint = <&lvds_enc_out>; ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; + }; -+ }; -+ port@1 { -+ reg = <1>; -+ adv7511_out: endpoint { -+ remote-endpoint = <&hdmi_con>; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ ov106xx_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ ov106xx_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; ++ }; + }; + }; -+ }; -+ }; -+}; -+ -+&wdt0 { -+ status = "okay"; -+}; -+ -+&avb { -+ pinctrl-0 = <&avb_pins>; -+ pinctrl-names = "default"; -+ renesas,no-ether-link; -+ phy-handle = <&phy0>; -+ status = "okay"; -+ phy-int-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>; + -+ phy0: ethernet-phy@0 { -+ rxc-skew-ps = <1500>; -+ rxdv-skew-ps = <420>; /* default */ -+ rxd0-skew-ps = <420>; /* default */ -+ rxd1-skew-ps = <420>; /* default */ -+ rxd2-skew-ps = <420>; /* default */ -+ rxd3-skew-ps = <420>; /* default */ -+ txc-skew-ps = <900>; /* default */ -+ txen-skew-ps = <420>; /* default */ -+ txd0-skew-ps = <420>; /* default */ -+ txd1-skew-ps = <420>; /* default */ -+ txd2-skew-ps = <420>; /* default */ -+ txd3-skew-ps = <420>; /* default */ -+ reg = <0>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>; -+ max-speed = <1000>; -+ }; -+}; ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; + -+&sdhi2 { -+ /* used for on-board eMMC */ -+ pinctrl-0 = <&sdhi2_pins_3v3>; -+ pinctrl-names = "default"; ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ ov106xx_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ ov106xx_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; ++ }; ++ }; ++ }; + -+ vmmc-supply = <&vcc_3v3>; -+ vqmmc-supply = <&vcc_vddq_vin0>; -+ no-1-8-v; -+ cap-mmc-highspeed; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi -new file mode 100644 -index 0000000..4ca502f ---- /dev/null -+++ b/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi -@@ -0,0 +1,518 @@ -+/* -+ * Device Tree Source for the H3ULCB Kingfisher board: -+ * this adding conflicting resource on VIN4/VIN5/VIN6/VIN7 for CN11 -+ * use CN11 instead default CN29/CN48 -+ * -+ * Copyright (C) 2017 Renesas Electronics Corp. -+ * Copyright (C) 2017 Cogent Embedded, Inc. -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; + -+&i2cswitch4 { -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <2>; -+ /* Slot B (CN11) */ ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ ov106xx_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; + -+ ov106xx@4 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x64>; ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; + -+ port@0 { -+ ov106xx_in4: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin4ep0>; ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; + }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep0>; ++ port@1 { ++ ov106xx_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ ov106xx_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; + }; -+ ov106xx_ti964_des1ep0: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep0>; ++ }; ++ ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@0 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti964_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti964_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ ti964_des0ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ ti964_des0ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; + }; -+ ov106xx_ti954_des1ep0: endpoint@2 { -+ remote-endpoint = <&ti954_des1ep0>; ++ port@1 { ++ ti964_csi0ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; + }; + }; -+ }; + -+ ov106xx@5 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x65>; ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@0 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_a_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; + -+ port@0 { -+ ov106xx_in5: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin5ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep1>; -+ }; -+ ov106xx_ti964_des1ep1: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep1>; ++ port@0 { ++ ti954_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti954_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; + }; -+ ov106xx_ti954_des1ep1: endpoint@2 { -+ remote-endpoint = <&ti954_des1ep1>; ++ port@1 { ++ ti954_csi0ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; + }; + }; -+ }; + -+ ov106xx@6 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x66>; ++ /* MAX9286 @ 0x2c */ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ + port@0 { -+ ov106xx_in6: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin6ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des1ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep2>; ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; + }; -+ ov106xx_ti964_des1ep2: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep2>; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; + }; + }; + }; + -+ ov106xx@7 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x67>; ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ /* MOST node(s) */ ++ }; ++ ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ ++ rpi_camera: ov5647@36 { ++ compatible = "ovti,ov5647"; ++ reg = <0x36>; ++ + port@0 { -+ ov106xx_in7: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2 3 4>; -+ remote-endpoint = <&vin7ep0>; ++ rpi_camera_in: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ remote-endpoint = <&vin4ep0>; ++ }; + }; + }; -+ port@1 { -+ ov106xx_max9286_des1ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep3>; -+ }; -+ ov106xx_ti964_des1ep3: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep3>; ++ }; ++ ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ ++ cmos_camera: ov5642@3c { ++ compatible = "ovti,ov5642"; ++ reg = <0x3c>; ++ clocks = <&camera_clk>; ++ clock-names = "mclk"; ++ ++ port@0 { ++ cmos_camera_in: endpoint { ++ remote-endpoint = <&vin5ep0>; ++ }; + }; + }; + }; + -+ /* DS90UB964 @ 0x3a */ -+ ti964-ti9x3@1 { -+ compatible = "ti,ti964-ti9x3"; -+ reg = <0x3a>; -+ ti,sensor_delay = <350>; -+ ti,links = <4>; -+ ti,lanes = <4>; -+ ti,forwarding-mode = "round-robin"; -+ ti,cable-mode = "coax"; ++ i2c@7 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <7>; ++ /* Slot A (CN10) */ + -+ port@0 { -+ ti964_des1ep0: endpoint@0 { -+ ti9x3-addr = <0x0c>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in4>; ++ video_a_ext0: pca9535@26 { ++ compatible = "nxp,pca9535"; ++ reg = <0x26>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; + }; -+ ti964_des1ep1: endpoint@1 { -+ ti9x3-addr = <0x0d>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in5>; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; + }; -+ ti964_des1ep2: endpoint@2 { -+ ti9x3-addr = <0x0e>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in6>; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; + }; -+ ti964_des1ep3: endpoint@3 { -+ ti9x3-addr = <0x0f>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in7>; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; + }; -+ }; -+ port@1 { -+ ti964_csi2ep0: endpoint { -+ csi-rate = <1450>; -+ remote-endpoint = <&csi2_41_ep>; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; + }; -+ }; -+ }; -+ -+ /* DS90UB954 @ 0x38 */ -+ ti954-ti9x3@1 { -+ compatible = "ti,ti954-ti9x3"; -+ reg = <0x38>; -+ /* gpios = <&video_b_ext1 10 GPIO_ACTIVE_HIGH>; */ -+ ti,sensor_delay = <350>; -+ ti,links = <2>; -+ ti,lanes = <4>; -+ ti,forwarding-mode = "round-robin"; -+ ti,cable-mode = "coax"; -+ -+ port@0 { -+ ti954_des1ep0: endpoint@0 { -+ ti9x3-addr = <0x0c>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in4>; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; + }; -+ ti954_des1ep1: endpoint@1 { -+ ti9x3-addr = <0x0d>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in5>; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; + }; -+ }; -+ port@1 { -+ ti954_csi2ep0: endpoint { -+ csi-rate = <1450>; -+ remote-endpoint = <&csi2_41_ep>; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A led"; + }; + }; -+ }; + -+ /* MAX9286 @ 0x2c */ -+ max9286-max9271@1 { -+ compatible = "maxim,max9286-max9271"; -+ reg = <0x2c>; -+ maxim,sensor_delay = <350>; -+ maxim,links = <4>; -+ maxim,lanes = <4>; -+ maxim,resetb-gpio = <1>; -+ maxim,fsync-mode = "automatic"; -+ maxim,timeout = <100>; ++ video_a_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; + -+ port@0 { -+ max9286_des1ep0: endpoint@0 { -+ max9271-addr = <0x50>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in4>; ++ video_a_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg2"; + }; -+ max9286_des1ep1: endpoint@1 { -+ max9271-addr = <0x51>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in5>; ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; + }; -+ max9286_des1ep2: endpoint@2 { -+ max9271-addr = <0x52>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in6>; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; + }; -+ max9286_des1ep3: endpoint@3 { -+ max9271-addr = <0x53>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in7>; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; + }; -+ }; -+ port@1 { -+ max9286_csi2ep0: endpoint { -+ csi-rate = <700>; -+ remote-endpoint = <&csi2_41_ep>; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A LED"; + }; + }; + }; + }; ++}; + -+ i2c@6 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <6>; -+ /* Slot B (CN11) */ -+ -+ video_b_ext0: pca9535@27 { -+ compatible = "nxp,pca9535"; -+ reg = <0x27>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ video_b_des_cfg1 { -+ gpio-hog; -+ gpios = <5 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-B cfg1"; -+ }; -+ video_b_des_cfg0 { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-B cfg0"; -+ }; -+ video_b_pwr_shdn { -+ gpio-hog; -+ gpios = <3 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR_SHDN"; -+ }; -+ video_b_cam_pwr0 { -+ gpio-hog; -+ gpios = <12 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR0"; -+ }; -+ video_b_cam_pwr1 { -+ gpio-hog; -+ gpios = <13 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR1"; -+ }; -+ video_b_cam_pwr2 { -+ gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR2"; -+ }; -+ video_b_cam_pwr3 { -+ gpio-hog; -+ gpios = <15 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR3"; -+ }; -+ video_b_des_shdn { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B DES_SHDN"; -+ }; -+ video_b_des_led { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "Video-B led"; -+ }; -+ }; ++&pcie_bus_clk { ++ clock-frequency = <100000000>; ++ status = "okay"; ++}; + -+ video_b_ext1: max7325@5c { -+ compatible = "maxim,max7325"; -+ reg = <0x5c>; -+ gpio-controller; -+ #gpio-cells = <2>; ++&pciec0 { ++ status = "okay"; ++}; + -+ video_b_des_cfg2 { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-B cfg2"; -+ }; -+ video_b_des_cfg1 { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-B cfg1"; -+ }; -+ video_b_des_cfg0 { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-B cfg0"; -+ }; -+ video_b_pwr_shdn { -+ gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR_SHDN"; -+ }; -+ video_b_cam_pwr0 { -+ gpio-hog; -+ gpios = <8 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR0"; -+ }; -+ video_b_cam_pwr1 { -+ gpio-hog; -+ gpios = <9 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR1"; -+ }; -+ video_b_cam_pwr2 { -+ gpio-hog; -+ gpios = <10 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR2"; -+ }; -+ video_b_cam_pwr3 { -+ gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR3"; -+ }; -+ video_b_des_shdn { -+ gpio-hog; -+ gpios = <13 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B DES_SHDN"; -+ }; -+ video_b_led { -+ gpio-hog; -+ gpios = <12 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "Video-B LED"; -+ }; -+ }; -+ }; ++&pciec1 { ++ status = "okay"; +}; + -+&vin4 { ++&vin0 { ++ status = "okay"; ++ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { -+ vin4ep0: endpoint { -+ csi,select = "csi41"; ++ vin0ep0: endpoint { ++ csi,select = "csi40"; + virtual,channel = <0>; -+ remote-endpoint = <&ov106xx_in4>; + data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; + }; + }; + port@1 { -+ csi2ep0: endpoint { -+ remote-endpoint = <&csi2_41_ep>; ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; + }; + }; + port@2 { -+ vin4_max9286_des1ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep0>; ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; + }; -+ vin4_ti964_des1ep0: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep0>; ++ vin0_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; + }; -+ vin4_ti954_des1ep0: endpoint@2 { -+ remote-endpoint = <&ti954_des1ep0>; ++ vin0_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; + }; + }; + }; +}; + -+&vin5 { ++&vin1 { ++ status = "okay"; ++ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { -+ vin5ep0: endpoint@0 { -+ csi,select = "csi41"; ++ vin1ep0: endpoint { ++ csi,select = "csi40"; + virtual,channel = <1>; -+ remote-endpoint = <&ov106xx_in5>; + data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; + }; + }; + port@1 { -+ csi2ep1: endpoint { -+ remote-endpoint = <&csi2_41_ep>; ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; + }; + }; + port@2 { -+ vin5_max9286_des1ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep1>; ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; + }; -+ vin5_ti964_des1ep1: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep1>; ++ vin1_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; + }; -+ vin5_ti954_des1ep1: endpoint@2 { -+ remote-endpoint = <&ti954_des1ep1>; ++ vin1_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; + }; + }; + }; +}; + -+&vin6 { ++&vin2 { + status = "okay"; + + ports { @@ -15931,30 +14001,30 @@ index 0000000..4ca502f + #size-cells = <0>; + + port@0 { -+ vin6ep0: endpoint@0 { -+ csi,select = "csi41"; ++ vin2ep0: endpoint { ++ csi,select = "csi40"; + virtual,channel = <2>; -+ remote-endpoint = <&ov106xx_in6>; + data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; + }; + }; + port@1 { -+ csi2ep2: endpoint { -+ remote-endpoint = <&csi2_41_ep>; ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; + }; + }; + port@2 { -+ vin6_max9286_des1ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep2>; ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; + }; -+ vin6_ti964_des1ep2: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep2>; ++ vin2_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; + }; + }; + }; +}; + -+&vin7 { ++&vin3 { + status = "okay"; + + ports { @@ -15962,30 +14032,74 @@ index 0000000..4ca502f + #size-cells = <0>; + + port@0 { -+ vin7ep0: endpoint@0 { -+ csi,select = "csi41"; ++ vin3ep0: endpoint { ++ csi,select = "csi40"; + virtual,channel = <3>; -+ remote-endpoint = <&ov106xx_in7>; + data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; + }; + }; + port@1 { -+ csi2ep3: endpoint { -+ remote-endpoint = <&csi2_41_ep>; ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; + }; + }; + port@2 { -+ vin7_max9286_des1ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des1ep3>; ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; + }; -+ vin7_ti964_des1ep3: endpoint@1 { -+ remote-endpoint = <&ti964_des1ep3>; ++ vin3_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; + }; + }; + }; +}; + -+&csi2_41 { ++&vin4 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi20"; ++ virtual,channel = <0>; ++ remote-endpoint = <&rpi_camera_in>; ++ data-lanes = <1 2>; ++ }; ++ }; ++ port@1 { ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_20_ep>; ++ }; ++ }; ++ }; ++}; ++ ++&vin5 { ++ pinctrl-0 = <&vin5_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin5ep0: endpoint@0 { ++ bus-width = <8>; ++ /* #HSYNC, #VSYNC */ ++ vsync-active = <1>; ++ hsync-active = <0>; ++ remote-endpoint = <&cmos_camera_in>; ++ }; ++ }; ++ }; ++}; ++ ++&csi2_40 { + status = "okay"; + + virtual,channel { @@ -16011,109 +14125,169 @@ index 0000000..4ca502f + #address-cells = <1>; + #size-cells = <0>; + -+ csi2_41_ep: endpoint { ++ csi2_40_ep: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + csi-rate = <300>; + }; + }; +}; -diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi -new file mode 100644 -index 0000000..4af5ca0 ---- /dev/null -+++ b/arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi -@@ -0,0 +1,30 @@ -+/* -+ * Device Tree Source for the H3/M3ULCB Kingfisher board: -+ * this overrides GPS in favour MOST on GP5_24/GP5_25 R-CAR pins -+ * -+ * Copyright (C) 2017 Renesas Electronics Corp. -+ * Copyright (C) 2017 Cogent Embedded, Inc. -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ + -+&pfc { -+ mlp_pins: mlp { -+ groups = "mlb_3pin"; -+ function = "mlb_3pin"; ++&csi2_20 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "raw8"; ++ receive,vc = <0>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_20_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ csi-rate = <280>; ++ }; + }; +}; + -+&scif1 { ++ ++&rcar_sound { ++ pinctrl-0 = <&sound_clk_pins>; ++ pinctrl-names = "default"; ++ ++ /* Multi DAI */ ++ #sound-dai-cells = <1>; ++ ++ rcar_sound,dai { ++ dai0 { ++ playback = <&ssi3>; ++ capture = <&ssi4>; ++ }; ++ ++ dai1 { ++ playback = <&ssi0 &src0 &dvc0>; ++ capture = <&ssi1 &src1 &dvc1>; ++ }; ++ ++ dai2 { ++ capture = <&ssi6>; ++ }; ++ ++ dai3 { ++ playback = <&ssi7>; ++ capture = <&ssi8>; ++ }; ++ }; ++}; ++ ++&sdhi3 { ++ pinctrl-0 = <&sdhi3_pins_3v3>; ++ pinctrl-1 = <&sdhi3_pins_1v8>; ++ pinctrl-names = "default", "state_uhs"; ++ ++ vmmc-supply = <&wlan_en>; ++ vqmmc-supply = <&vccq_sdhi3>; ++ keep-power-in-suspend; ++ enable-sdio-wakeup; ++ bus-width = <4>; ++ no-1-8-v; ++ non-removable; ++ cap-power-off-card; ++ max-frequency = <26000000>; ++ status = "okay"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ wlcore: wlcore@2 { ++ compatible = "ti,wl1837"; ++ reg = <2>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <25 IRQ_TYPE_EDGE_FALLING>; ++ }; ++}; ++ ++&usb2_phy0 { ++ pinctrl-0 = <&usb0_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&xhci0 { ++ status = "okay"; ++}; ++ ++&msiof1 { + status = "disabled"; +}; + -+&mlp { -+ pinctrl-0 = <&mlp_pins>; ++&can0 { ++ pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + status = "okay"; + -+ clock-speed = "1024fs"; ++ renesas,can-clock-select = <0x0>; +}; -diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi -new file mode 100644 -index 0000000..b854216 ---- /dev/null -+++ b/arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi -@@ -0,0 +1,46 @@ -+/* -+ * Device Tree Source for the H3/M3ULCB Kingfisher board: -+ * this overrides WIFI in favour SD on SDHI3 -+ * -+ * Copyright (C) 2017 Renesas Electronics Corp. -+ * Copyright (C) 2017 Cogent Embedded, Inc. -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ + -+&sdio_switch { -+ regulator-name = "sd_on"; -+ enable-active-high; ++&can1 { ++ pinctrl-0 = <&can1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; +}; + -+&vccq_sdhi3 { -+ compatible = "regulator-gpio"; ++&canfd { ++ pinctrl-0 = <&canfd0_pins &canfd1_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; + -+ regulator-min-microvolt = <1800000>; ++ channel0 { ++ status = "okay"; ++ }; + -+ gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; -+ gpios-states = <1>; -+ states = <3300000 1 -+ 1800000 0>; ++ channel1 { ++ status = "okay"; ++ }; +}; + -+&sdhi3 { -+ /delete-property/non-removable; -+ /delete-property/cap-power-off-card; -+ /delete-property/keep-power-in-suspend; -+ /delete-property/enable-sdio-wakeup; -+ /delete-property/max-frequency; -+ /delete-property/no-1-8-v; ++&ssi4 { ++ shared-pin; ++}; + -+ vmmc-supply = <&vcc_sdhi3>; -+ cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; -+ wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; -+// sd-uhs-sdr50; -+// sd-uhs-sdr104; ++&ssi8 { ++ shared-pin; +}; + -+&wlcore { -+ status = "disabled"; ++&pciec1 { ++ pcie3v3-supply = <&mpcie_3v3>; ++ pcie1v8-supply = <&mpcie_1v8>; +}; -diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi ++ ++ ++ +diff --git a/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi b/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi new file mode 100644 -index 0000000..8ffafb2 +index 0000000..92ed4a4 --- /dev/null -+++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi -@@ -0,0 +1,1529 @@ ++++ b/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi +@@ -0,0 +1,515 @@ +/* -+ * Device Tree Source for the ULCB Kingfisher board ++ * Device Tree Source for the H3ULCB Videobox board: ++ * this adding conflicting resource on VIN4/VIN5/VIN6/VIN7 for CN12 + * + * Copyright (C) 2017 Renesas Electronics Corp. + * Copyright (C) 2017 Cogent Embedded, Inc. @@ -16123,768 +14297,954 @@ index 0000000..8ffafb2 + * kind, whether express or implied. + */ + -+/ { -+ aliases { -+ serial1 = &hscif0; -+ serial2 = &hscif1; -+ serial3 = &scif1; -+ }; -+ -+ snd_clk: snd_clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24576000>; -+ clock-output-names = "scki"; -+ }; -+ -+ wlan_en: regulator@4 { -+ compatible = "regulator-fixed"; -+ regulator-name = "wlan-en-regulator"; -+ -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ gpio = <&gpio_ext_74 4 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ vcc_sdhi3: regulator@41 { -+ compatible = "regulator-fixed"; -+ -+ regulator-name = "SDHI3 Vcc"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ vccq_sdhi3: regulator@5 { -+ compatible = "regulator-fixed"; -+ -+ regulator-name = "SDHI3 VccQ"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ codec_en_reg: regulator@6 { -+ compatible = "regulator-fixed"; -+ regulator-name = "codec-en-regulator"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ gpio = <&gpio_ext_74 15 0>; -+ -+ /* delay - CHECK */ -+ startup-delay-us = <70000>; -+ enable-active-high; -+ }; -+ -+ amp_en_reg: regulator@7 { -+ compatible = "regulator-fixed"; -+ regulator-name = "amp-en-regulator"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ gpio = <&gpio_ext_74 0 0>; -+ -+ startup-delay-us = <0>; -+ enable-active-high; -+ }; -+ -+ sdio_switch: regulator@9 { -+ compatible = "regulator-fixed"; -+ regulator-name = "wifi_on"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio_ext_74 5 0>; -+ enable-active-low; -+ regulator-always-on; -+ }; -+ -+ radio_switch: regulator@11 { -+ compatible = "regulator-fixed"; -+ regulator-name = "radio_on"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio_ext_74 13 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-always-on; -+ }; -+ -+ mpcie_3v3: regulator@12 { -+ compatible = "regulator-fixed"; -+ regulator-name = "mPCIe 3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio_ext_77 14 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ mpcie_1v8: regulator@13 { -+ compatible = "regulator-fixed"; -+ regulator-name = "mPCIe 1v8"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ gpio = <&gpio_ext_77 15 GPIO_ACTIVE_HIGH>; -+ startup-delay-us = <200000>; -+ enable-active-high; -+ }; -+ -+ kim { -+ compatible = "kim"; -+ shutdown-gpios = <&gpio_ext_74 3 GPIO_ACTIVE_HIGH>; -+ /* serial1 */ -+ dev_name = "/dev/ttySC1"; -+ flow_cntrl = <1>; -+ /* int div 8 hscif@26.6666656MHz */ -+ baud_rate = <3333332>; -+ }; -+ -+ btwilink { -+ compatible = "btwilink"; -+ }; -+ -+ sound_ext: sound@0 { -+ pinctrl-0 = <&sound_0_pins>; -+ pinctrl-names = "default"; -+ compatible = "simple-audio-card"; -+ -+ simple-audio-card,format = "left_j"; -+ simple-audio-card,name = "pcm3168a"; ++&i2cswitch2 { ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ /* Slot C (CN12) */ + -+ simple-audio-card,bitclock-master = <&sound_ext_master>; -+ simple-audio-card,frame-master = <&sound_ext_master>; -+ sound_ext_master: simple-audio-card,cpu@0 { -+ sound-dai = <&rcar_sound 0>; -+ dai-tdm-slot-num = <8>; -+ dai-tdm-slot-width = <32>; -+ }; ++ ov106xx@8 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x68>; + -+ simple-audio-card,codec@0 { -+ sound-dai = <&pcm3168a>; -+ dai-tdm-slot-num = <8>; -+ dai-tdm-slot-width = <32>; -+ system-clock-frequency = <24576000>; ++ port@0 { ++ ov106xx_in8: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ remote-endpoint = <&vin4ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des2ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des2ep0>; ++ }; ++ ov106xx_ti964_des2ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des2ep0>; ++ }; ++ ov106xx_ti954_des2ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des2ep0>; ++ }; ++ }; + }; -+ }; -+ -+ /delete-node/sound; + -+ rsnd_ak4613: sound@1 { -+ pinctrl-0 = <&sound_pins>; -+ pinctrl-names = "default"; -+ compatible = "simple-audio-card"; ++ ov106xx@9 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x69>; + -+ simple-audio-card,format = "left_j"; -+ simple-audio-card,name = "ak4613"; ++ port@0 { ++ ov106xx_in9: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ remote-endpoint = <&vin5ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des2ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des2ep1>; ++ }; ++ ov106xx_ti964_des2ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des2ep1>; ++ }; ++ ov106xx_ti954_des2ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des2ep1>; ++ }; ++ }; ++ }; + -+ simple-audio-card,bitclock-master = <&sndcpu>; -+ simple-audio-card,frame-master = <&sndcpu>; ++ ov106xx@10 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x6a>; + -+ sndcpu: simple-audio-card,cpu@1 { -+ sound-dai = <&rcar_sound 1>; ++ port@0 { ++ ov106xx_in10: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ remote-endpoint = <&vin6ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des2ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des2ep2>; ++ }; ++ ov106xx_ti964_des2ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des2ep2>; ++ }; ++ }; + }; + -+ sndcodec: simple-audio-card,codec@1 { -+ sound-dai = <&ak4613>; ++ ov106xx@11 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x6b>; ++ ++ port@0 { ++ ov106xx_in11: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ remote-endpoint = <&vin7ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des2ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des2ep3>; ++ }; ++ ov106xx_ti964_des2ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des2ep3>; ++ }; ++ }; + }; -+ }; + -+ sound_radio: sound@2 { -+ pinctrl-0 = <&sound_2_pins>; -+ pinctrl-names = "default"; -+ compatible = "simple-audio-card"; ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@2 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <2>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; + -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,name = "radio"; ++ port@0 { ++ ti964_des2ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in8>; ++ }; ++ ti964_des2ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in9>; ++ }; ++ ti964_des2ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in10>; ++ }; ++ ti964_des2ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in11>; ++ }; ++ }; ++ port@1 { ++ ti964_csi1ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_20_ep>; ++ }; ++ }; ++ }; + -+ simple-audio-card,bitclock-master = <&sound_radio_master>; -+ simple-audio-card,frame-master = <&sound_radio_master>; -+ simple-audio-card,cpu@2 { -+ sound-dai = <&rcar_sound 2>; ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@2 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_c_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <2>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti954_des2ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in8>; ++ }; ++ ti954_des2ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in9>; ++ }; ++ }; ++ port@1 { ++ ti954_csi1ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_20_ep>; ++ }; ++ }; + }; + -+ sound_radio_master: simple-audio-card,codec@2 { -+ sound-dai = <&radio>; -+ system-clock-frequency = <12288000>; ++ /* MAX9286 @ 0x2c */ ++ max9286-max9271@2 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <2>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des2ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in8>; ++ }; ++ max9286_des2ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in9>; ++ }; ++ max9286_des2ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in10>; ++ }; ++ max9286_des2ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in11>; ++ }; ++ }; ++ port@1 { ++ max9286_csi1ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_20_ep>; ++ }; ++ }; + }; + }; + -+ sound_wl18xx: sound@3 { -+ pinctrl-0 = <&sound_3_pins>; -+ pinctrl-names = "default"; -+ compatible = "simple-audio-card"; -+ -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,name = "wl18xx"; ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ /* Slot C (CN12) */ + -+ simple-audio-card,bitclock-master = <&sound_wl18xx_master>; -+ simple-audio-card,frame-master = <&sound_wl18xx_master>; -+ sound_wl18xx_master: simple-audio-card,cpu@3 { -+ sound-dai = <&rcar_sound 3>; -+ }; ++ video_c_ext0: pca9535@26 { ++ compatible = "nxp,pca9535"; ++ reg = <0x26>; ++ gpio-controller; ++ #gpio-cells = <2>; + -+ simple-audio-card,codec@3 { -+ sound-dai = <&wl18xx_pcm>; ++ video_c_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-C cfg1"; ++ }; ++ video_c_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-C cfg0"; ++ }; ++ video_c_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR_SHDN"; ++ }; ++ video_c_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR0"; ++ }; ++ video_c_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR1"; ++ }; ++ video_c_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR2"; ++ }; ++ video_c_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR3"; ++ }; ++ video_c_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C DES_SHDN"; ++ }; ++ video_c_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-C led"; ++ }; + }; -+ }; + -+ lvds-encoder { -+ compatible = "thine,thc63lvdm83d"; ++ video_c_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; + -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ port@0 { -+ reg = <0>; -+ lvds_enc_in: endpoint { -+ remote-endpoint = <&du_out_lvds0>; -+ }; ++ video_c_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-C cfg2"; + }; -+ port@1 { -+ reg = <1>; -+ lvds_enc_out: endpoint { -+ remote-endpoint = <&lvds_in>; -+ }; ++ video_c_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-C cfg1"; ++ }; ++ video_c_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-C cfg0"; ++ }; ++ video_c_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR_SHDN"; ++ }; ++ video_c_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR0"; ++ }; ++ video_c_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR1"; ++ }; ++ video_c_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR2"; ++ }; ++ video_c_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C PWR3"; ++ }; ++ video_c_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-C DES_SHDN"; ++ }; ++ video_c_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-C LED"; + }; + }; + }; ++}; + -+ lvds { -+ compatible = "lvds-connector"; -+ -+ width-mm = <210>; -+ height-mm = <158>; ++&vin4 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ panel-timing { -+ /* 1280x800 @60Hz */ -+ clock-frequency = <65000000>; -+ hactive = <1280>; -+ vactive = <800>; -+ hsync-len = <40>; -+ hfront-porch = <80>; -+ hback-porch = <40>; -+ vfront-porch = <14>; -+ vback-porch = <14>; -+ vsync-len = <4>; ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi20"; ++ virtual,channel = <0>; ++ remote-endpoint = <&ov106xx_in8>; ++ data-lanes = <1 2>; ++ }; + }; -+ -+ port { -+ lvds_in: endpoint { -+ remote-endpoint = <&lvds_enc_out>; ++ port@1 { ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_20_ep>; + }; + }; -+ }; -+ -+ hdmi-out { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con: endpoint { -+ remote-endpoint = <&adv7513_out>; ++ port@2 { ++ vin4_max9286_des2ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des2ep0>; ++ }; ++ vin4_ti964_des2ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des2ep0>; ++ }; ++ vin4_ti954_des2ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des2ep0>; + }; + }; + }; -+ -+ radio: si468x@0 { -+ compatible = "si,si468x-pcm"; -+ status = "okay"; -+ -+ #sound-dai-cells = <0>; -+ }; -+ -+ wl18xx_pcm: wl18xx_pcm@0 { -+ compatible = "ti,wl18xx-pcm"; -+ status = "okay"; -+ -+ #sound-dai-cells = <0>; -+ }; -+ -+ camera_clk: camera_clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "mclk"; -+ }; +}; + -+&pfc { -+ scif1_pins: scif1 { -+ groups = "scif1_data_b"; -+ function = "scif1"; -+ }; -+ -+ hscif0_pins: hscif0 { -+ groups = "hscif0_data", "hscif0_ctrl"; -+ function = "hscif0"; -+ }; -+ -+ hscif1_pins: hscif1 { -+ groups = "hscif1_data_a", "hscif1_ctrl_a"; -+ function = "hscif1"; -+ }; -+ -+ du_pins: du { -+ groups = "du_rgb888", "du_sync", "du_clk_out_0", "du_disp"; -+ function = "du"; -+ }; -+ -+ sdhi3_pins_3v3: sd3_3v3 { -+ groups = "sdhi3_data4", "sdhi3_ctrl"; -+ function = "sdhi3"; -+ power-source = <3300>; -+ }; -+ -+ sdhi3_pins_1v8: sd3_1v8 { -+ groups = "sdhi3_data4", "sdhi3_ctrl"; -+ function = "sdhi3"; -+ power-source = <1800>; -+ }; -+ -+ sound_0_pins: sound0 { -+ groups = "ssi349_ctrl", "ssi3_data", "ssi4_data"; -+ function = "ssi"; -+ }; -+ -+ /* sound_pins defined in H3 or M3 ulsb file */ -+ -+ sound_2_pins: sound2 { -+ groups = "ssi6_ctrl", "ssi6_data"; -+ function = "ssi"; -+ }; -+ -+ sound_3_pins: sound3 { -+ groups = "ssi78_ctrl", "ssi7_data", "ssi8_data"; -+ function = "ssi"; -+ }; -+ -+ usb0_pins: usb0 { -+ groups = "usb0"; -+ function = "usb0"; -+ }; -+ -+ can0_pins: can0 { -+ groups = "can0_data_a"; -+ function = "can0"; -+ }; -+ -+ can1_pins: can1 { -+ groups = "can1_data"; -+ function = "can1"; -+ }; -+ -+ canfd0_pins: canfd0 { -+ groups = "canfd0_data_a"; -+ function = "canfd0"; -+ }; -+ -+ canfd1_pins: canfd1 { -+ groups = "canfd1_data"; -+ function = "canfd1"; -+ }; ++&vin5 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ vin5_pins: vin5 { -+ groups = "vin5_data8", "vin5_sync", "vin5_clk"; -+ function = "vin5"; ++ port@0 { ++ vin5ep0: endpoint@0 { ++ csi,select = "csi20"; ++ virtual,channel = <1>; ++ remote-endpoint = <&ov106xx_in9>; ++ data-lanes = <1 2>; ++ }; ++ }; ++ port@1 { ++ csi2ep1: endpoint { ++ remote-endpoint = <&csi2_20_ep>; ++ }; ++ }; ++ port@2 { ++ vin5_max9286_des2ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des2ep1>; ++ }; ++ vin5_ti964_des2ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des2ep1>; ++ }; ++ vin5_ti954_des2ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des2ep1>; ++ }; ++ }; + }; +}; + -+&du { -+ pinctrl-0 = <&du_pins>; -+ pinctrl-names = "default"; -+}; ++&vin6 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+&gpio2 { -+ bl_pwm { -+ gpio-hog; -+ gpios = <3 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "BL PWM 100%"; ++ port@0 { ++ vin6ep0: endpoint@0 { ++ csi,select = "csi20"; ++ virtual,channel = <2>; ++ remote-endpoint = <&ov106xx_in10>; ++ data-lanes = <1 2>; ++ }; ++ }; ++ port@1 { ++ csi2ep2: endpoint { ++ remote-endpoint = <&csi2_20_ep>; ++ }; ++ }; ++ port@2 { ++ vin6_max9286_des2ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des2ep2>; ++ }; ++ vin6_ti964_des2ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des2ep2>; ++ }; ++ }; + }; +}; + -+&gpio4 { -+ most_rst { -+ gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "MOST RST"; -+ }; -+}; ++&vin7 { ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+&gpio6 { -+ audio_sw { -+ gpio-hog; -+ gpios = <21 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Onboard MCh Audio"; ++ port@0 { ++ vin7ep0: endpoint@0 { ++ csi,select = "csi20"; ++ virtual,channel = <3>; ++ remote-endpoint = <&ov106xx_in11>; ++ data-lanes = <1 2>; ++ }; ++ }; ++ port@1 { ++ csi2ep3: endpoint { ++ remote-endpoint = <&csi2_20_ep>; ++ }; ++ }; ++ port@2 { ++ vin7_max9286_des2ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des2ep3>; ++ }; ++ vin7_ti964_des2ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des2ep3>; ++ }; ++ }; + }; +}; + -+&scif1 { -+ pinctrl-0 = <&scif1_pins>; -+ pinctrl-names = "default"; -+ ++&csi2_20 { + status = "okay"; -+}; -+ -+&hscif0 { -+ pinctrl-0 = <&hscif0_pins>; -+ pinctrl-names = "default"; -+ uart-has-rtscts; + -+ status = "okay"; -+}; ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; + -+&hscif1 { -+ pinctrl-0 = <&hscif1_pins>; -+ pinctrl-names = "default"; ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ status = "okay"; ++ csi2_20_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ csi-rate = <300>; ++ }; ++ }; +}; +diff --git a/arch/arm64/boot/dts/renesas/ulcb-vb.dtsi b/arch/arm64/boot/dts/renesas/ulcb-vb.dtsi +new file mode 100644 +index 0000000..193153e +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/ulcb-vb.dtsi +@@ -0,0 +1,1726 @@ ++/* ++ * Device Tree Source for the ULCB Videobox board ++ * ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ + -+&i2c2 { -+ clock-frequency = <400000>; -+ -+ gpio_ext_74: pca9539@74 { -+ compatible = "nxp,pca9539"; -+ reg = <0x74>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ interrupt-parent = <&gpio6>; -+ interrupts = <8 IRQ_TYPE_EDGE_FALLING>; ++/ { ++ leds { ++ compatible = "gpio-leds"; + -+ hub_pwen { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "HUB pwen"; ++ led5 { ++ gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + }; -+ hub_rst { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "HUB rst"; ++ led6 { ++ gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; + }; -+ otg_offvbus { -+ gpio-hog; -+ gpios = <8 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "OTG off VBUSn"; ++ /* D13 - status 0 */ ++ led_ext00 { ++ gpios = <&gpio_ext_led 0 GPIO_ACTIVE_LOW>; ++ /* linux,default-trigger = "heartbeat"; */ + }; -+ otg_extlpn { -+ gpio-hog; -+ gpios = <9 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "OTG EXTLPn"; ++ /* D14 - status 1 */ ++ led_ext01 { ++ gpios = <&gpio_ext_led 1 GPIO_ACTIVE_LOW>; ++ /* linux,default-trigger = "mmc1"; */ + }; -+ otg_stat1 { -+ gpio-hog; -+ gpios = <10 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "OTG Stat1"; ++ /* D16 - HDMI1 */ ++ led_ext02 { ++ gpios = <&gpio_ext_led 2 GPIO_ACTIVE_LOW>; + }; -+ otg_stat2 { -+ gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "OTG Stat2"; ++ /* D18 - HDMI0 */ ++ led_ext03 { ++ gpios = <&gpio_ext_led 3 GPIO_ACTIVE_LOW>; ++ }; ++ /* D20 - USB3.0 - 0.1 */ ++ led_ext04 { ++ gpios = <&gpio_ext_led 4 GPIO_ACTIVE_LOW>; ++ }; ++ /* D21 - USB3.0 - 0.2 */ ++ led_ext05 { ++ gpios = <&gpio_ext_led 5 GPIO_ACTIVE_LOW>; ++ }; ++ /* D24 - USB3.0 - 1.1 */ ++ led6_ext06 { ++ gpios = <&gpio_ext_led 6 GPIO_ACTIVE_LOW>; ++ }; ++ /* D25 - USB3.0 - 1.2 */ ++ led_ext07 { ++ gpios = <&gpio_ext_led 7 GPIO_ACTIVE_LOW>; + }; + }; + -+ gpio_ext_75: pca9539@75 { -+ compatible = "nxp,pca9539"; -+ reg = <0x75>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ interrupt-parent = <&gpio6>; -+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>; ++ snd_clk: snd_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24576000>; ++ clock-output-names = "scki"; ++ }; ++ ++ vccq_sdhi3: regulator@5 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "SDHI3 VccQ"; ++ /* external voltage translator to 1.8V */ ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ fpdlink_switch: regulator@8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "fpdlink_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio1 20 0>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ hub_reset: regulator@9 { ++ compatible = "regulator-fixed"; ++ regulator-name = "hub_reset"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio5 5 0>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ hub_power: regulator@10 { ++ compatible = "regulator-fixed"; ++ regulator-name = "hub_power"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&gpio6 28 0>; ++ enable-active-high; ++ regulator-always-on; ++ }; + -+ gps_rst { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "GPS rst"; ++ /delete-node/sound; ++ ++ rsnd_ak4613: sound@0 { ++ pinctrl-0 = <&sound_0_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; ++ ++ simple-audio-card,format = "left_j"; ++ simple-audio-card,name = "ak4613"; ++ ++ simple-audio-card,bitclock-master = <&sndcpu>; ++ simple-audio-card,frame-master = <&sndcpu>; ++ ++ sndcpu: simple-audio-card,cpu@1 { ++ sound-dai = <&rcar_sound>; + }; -+ fpdl_shdn { -+ gpio-hog; -+ gpios = <9 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "FPDLink shdn"; ++ ++ sndcodec: simple-audio-card,codec@1 { ++ sound-dai = <&ak4613>; + }; + }; + -+ i2cswitch2: pca9548@71 { -+ compatible = "nxp,pca9548"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x71>; -+ reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; ++ lvds-encoder { ++ compatible = "thine,thc63lvdm83d"; + -+ i2c@0 { ++ ports { + #address-cells = <1>; + #size-cells = <0>; -+ reg = <0>; -+ /* BCM node(s) */ ++ port@0 { ++ reg = <0>; ++ lvds_enc_in: endpoint { ++ remote-endpoint = <&du_out_lvds0>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ lvds_enc_out: endpoint { ++ remote-endpoint = <&lvds_in>; ++ }; ++ }; + }; ++ }; + -+ i2c@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ /* USB3.0 HUB node(s) */ -+ }; ++ lvds { ++ compatible = "lvds-connector"; + -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <2>; -+ /* Power amp node(s) */ -+ }; ++ width-mm = <210>; ++ height-mm = <158>; + -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <3>; -+ /* Radio node(s) */ ++ panel-timing { ++ /* 1280x800 @60Hz */ ++ clock-frequency = <65000000>; ++ hactive = <1280>; ++ vactive = <800>; ++ hsync-len = <40>; ++ hfront-porch = <80>; ++ hback-porch = <40>; ++ vfront-porch = <14>; ++ vback-porch = <14>; ++ vsync-len = <4>; + }; + -+ i2c@4 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <4>; ++ port { ++ lvds_in: endpoint { ++ remote-endpoint = <&lvds_enc_out>; ++ }; ++ }; ++ }; + -+ hdmi@3d { -+ compatible = "adi,adv7511w"; -+ reg = <0x3d>; -+// interrupt-parent = <&gpio2>; -+// interrupts = <0 IRQ_TYPE_EDGE_BOTH>; -+ pd-gpios = <&gpio_ext_75 5 GPIO_ACTIVE_LOW>; ++ excan_ref_clk: excan-ref-clock { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <16000000>; ++ }; + -+ adi,input-depth = <8>; -+ adi,input-colorspace = "rgb"; -+ adi,input-clock = "1x"; -+ adi,input-style = <1>; -+ adi,input-justification = "evenly"; -+ adi,clock-delay = <1200>; -+ adi,clock-max-rate = <100000>; ++ radio: si468x@0 { ++ compatible = "si,si468x-pcm"; ++ status = "okay"; + -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; ++ #sound-dai-cells = <0>; ++ }; + -+ port@0 { -+ reg = <0>; -+ adv7513_in: endpoint { -+ remote-endpoint = <&du_out_rgb>; -+ }; -+ }; ++ spi_gpio_sw { ++ compatible = "spi-gpio"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ gpio-sck = <&gpio0 8 GPIO_ACTIVE_HIGH>; ++ gpio-miso = <&gpio0 10 GPIO_ACTIVE_HIGH>; ++ gpio-mosi = <&gpio0 11 GPIO_ACTIVE_HIGH>; ++ cs-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; ++ num-chipselects = <1>; + -+ port@1 { -+ reg = <1>; -+ adv7513_out: endpoint { -+ remote-endpoint = <&hdmi_con>; -+ }; -+ }; -+ }; -+ }; ++ spidev: spidev@0 { ++ compatible = "spidev", "spi-gpio"; ++ reg = <0>; ++ spi-max-frequency = <25000000>; ++ spi-cpha; ++ spi-cpol; + }; ++ }; + -+ i2c@5 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <5>; -+ /* PCIe node(s) */ ++ spi_gpio_can { ++ compatible = "spi-gpio"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ gpio-sck = <&gpio1 2 GPIO_ACTIVE_HIGH>; ++ gpio-miso = <&gpio1 3 GPIO_ACTIVE_HIGH>; ++ gpio-mosi = <&gpio1 1 GPIO_ACTIVE_HIGH>; ++ cs-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH ++ &gpio1 4 GPIO_ACTIVE_HIGH>; ++ num-chipselects = <2>; ++ ++ spican0: spidev@0 { ++ compatible = "microchip,mcp2515"; ++ reg = <0>; ++ clocks = <&excan_ref_clk>; ++ interrupt-parent = <&gpio0>; ++ interrupts = <15 GPIO_ACTIVE_LOW>; ++ spi-max-frequency = <10000000>; + }; ++ spican1: spidev@1 { ++ compatible = "microchip,mcp2515"; ++ reg = <1>; ++ clocks = <&excan_ref_clk>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <5 GPIO_ACTIVE_LOW>; ++ spi-max-frequency = <10000000>; ++ }; ++ }; ++}; + -+ i2c@6 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <6>; -+ /* LVDS display node(s) */ ++&pfc { ++ hscif4_pins: hscif4 { ++ groups = "hscif4_data_a", "hscif4_ctrl"; ++ function = "hscif4"; ++ }; + -+ polytouch: edt-ft5x06@38 { -+ compatible = "edt,edt-ft5x06"; -+ reg = <0x38>; -+ interrupt-parent = <&gpio5>; -+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>; -+ }; -+ }; ++ sdhi3_pins_3v3: sd3_3v3 { ++ groups = "sdhi3_data4", "sdhi3_ctrl"; ++ function = "sdhi3"; ++ power-source = <3300>; ++ }; + -+ i2c@7 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <7>; -+ /* Audio, GPS and Gyro node(s) */ ++ /delete-node/sound; + -+ pcm3168a: audio-codec@44 { -+ #sound-dai-cells = <0>; -+ compatible = "ti,pcm3168a"; -+ reg = <0x44>; -+ clocks = <&snd_clk>; -+ clock-names = "scki"; -+ tdm; -+ VDD1-supply = <&codec_en_reg>; -+ VDD2-supply = <&codec_en_reg>; -+ VCCAD1-supply = <&codec_en_reg>; -+ VCCAD2-supply = <&codec_en_reg>; -+ VCCDA1-supply = <&_en_reg>; -+ VCCDA2-supply = <&_en_reg>; -+ }; ++ sound_0_pins: sound1 { ++ groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; ++ function = "ssi"; ++ }; ++ ++ usb0_pins: usb0 { ++ groups = "usb0"; ++ function = "usb0"; ++ }; ++ ++ can0_pins: can0 { ++ groups = "can0_data_a"; ++ function = "can0"; ++ }; + -+ lsm9ds0_acc_mag@1d { -+ compatible = "st,lsm9ds0_accel_magn"; -+ reg = <0x1d>; -+ }; ++ can1_pins: can1 { ++ groups = "can1_data"; ++ function = "can1"; ++ }; + -+ lsm9ds0_gyr@6b { -+ compatible = "st,lsm9ds0_gyro"; -+ reg = <0x6b>; -+ }; ++ canfd0_pins: canfd0 { ++ groups = "canfd0_data_a"; ++ function = "canfd0"; ++ }; + -+ /* GPS@ 0x42 */ -+ }; ++ canfd1_pins: canfd1 { ++ groups = "canfd1_data"; ++ function = "canfd1"; + }; +}; + -+&i2c4 { -+ gpio_ext_76: pca9539@76 { -+ compatible = "nxp,pca9539"; -+ reg = <0x76>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ interrupt-parent = <&gpio7>; -+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>; ++&gpio0 { ++ video_a_irq { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A irq"; ++ }; + -+ port_b_a0 { -+ gpio-hog; -+ gpios = <0 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "Video-B A0"; -+ }; -+ port_b_a1 { -+ gpio-hog; -+ gpios = <1 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B A1"; -+ }; -+ port_a_a0 { -+ gpio-hog; -+ gpios = <2 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "Video-A A0"; -+ }; -+ port_a_a1 { -+ gpio-hog; -+ gpios = <3 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A A1"; -+ }; -+ cmos_pwdn { -+ gpio-hog; -+ gpios = <8 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "CMOS PWDN"; -+ }; -+ cmos_rst { -+ gpio-hog; -+ gpios = <9 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "CMOS RST"; -+ }; -+ /* pin 12 - CAM_CLK */ -+ rpi_cam_io_1 { -+ gpio-hog; -+ gpios = <10 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "RaspB_IO1"; -+ }; -+ /* pin 11 - CAM_GPIO - assume pwdn */ -+ rpi_cam_io_0 { -+ gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "RaspB_IO0"; -+ }; -+ sam_rst { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "SAM RST"; -+ }; -+ sam_pwr { -+ gpio-hog; -+ gpios = <5 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "SAM PWR"; -+ }; -+ /* 0 - FPDLink output, 1 - LVDS output */ -+ lvds_vs_fpdl { -+ gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "LVDS switch"; -+ }; ++ video_b_irq { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B irq"; + }; + -+ gpio_ext_77: pca9539@77 { -+ compatible = "nxp,pca9539"; -+ reg = <0x77>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ interrupt-parent = <&gpio5>; -+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; ++ video_c_irq { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-C irq"; ++ }; ++}; + -+ mpcie_wake { -+ gpio-hog; -+ gpios = <0 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "mPCIe WAKE#"; -+ }; -+ mpcie_wdisable { -+ gpio-hog; -+ gpios = <1 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "mPCIe W_DISABLE"; -+ }; -+ mpcie_clreq { -+ gpio-hog; -+ gpios = <2 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "mPCIe CLKREQ#"; -+ }; -+ mpcie_ovc { -+ gpio-hog; -+ gpios = <3 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "mPCIe OVC"; -+ }; ++&gpio1 { ++ gpioext_4_22_irq { ++ gpio-hog; ++ gpios = <25 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "0x22@i2c4 irq"; ++ }; ++ pcie_disable { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "mPCIe W_DISABLE"; ++ }; ++ m2_sleep { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "M.2 SLEEP#"; ++ }; ++ m2_pres { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 Present"; ++ }; ++ m2_pcie_det { ++ gpio-hog; ++ gpios = <18 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 PCIe detected"; ++ }; ++ m2_usb_det { ++ gpio-hog; ++ gpios = <19 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 USB30 detected"; ++ }; ++ m2_usb_det { ++ gpio-hog; ++ gpios = <27 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 SSD detected"; ++ }; ++ eth_phy_reset { ++ gpio-hog; ++ gpios = <16 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "BR phy reset"; ++ }; ++ eth_sw_reset { ++ gpio-hog; ++ gpios = <17 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "BR switch reset"; ++ }; ++}; ++ ++&gpio2 { ++ m2_wake { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 WAKE#"; ++ }; ++ m2_pcie_en { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "M.2 PCIe enable"; ++ }; ++}; ++ ++&gpio3 { ++ m2_power_off { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "M.2 FULL_CARD_POWER_OFF#"; ++ }; ++}; ++ ++&gpio6 { ++ pcie_wake { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "mPCIe WAKE#"; ++ }; ++ pcie_clkreq { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "mPCIe CLKREQ#"; ++ }; ++ m2_rst { ++ gpio-hog; ++ gpios = <21 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "M.2 RESET#"; + }; ++}; ++ ++&hscif4 { ++ pinctrl-0 = <&hscif4_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; + -+ i2cswitch4: pca9548@74 { ++ status = "okay"; ++}; ++ ++&i2c2 { ++ clock-frequency = <400000>; ++ ++ i2cswitch2: pca9548@74 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; -+ reg = <0x71>; -+ reset-gpios= <&gpio3 15 GPIO_ACTIVE_LOW>; ++ reg = <0x74>; ++ reset-gpios = <&gpio6 5 GPIO_ACTIVE_LOW>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; -+ /* SAM node(s) */ ++ /* USB3.0 HUB node(s) */ + }; + -+ i2c@1 { ++ i2c@6 { + #address-cells = <1>; + #size-cells = <0>; -+ reg = <1>; ++ reg = <6>; ++ /* PCIe node(s) */ ++ }; ++ ++ i2c@7 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <7>; + /* Slot A (CN10) */ + + ov106xx@0 { @@ -16985,7 +15345,7 @@ index 0000000..8ffafb2 + ti,links = <4>; + ti,lanes = <4>; + ti,forwarding-mode = "round-robin"; -+ ti,cable-mode = "coax"; ++ ti,cable-mode = "stp"; + + port@0 { + ti964_des0ep0: endpoint@0 { @@ -17026,7 +15386,7 @@ index 0000000..8ffafb2 + ti,links = <2>; + ti,lanes = <4>; + ti,forwarding-mode = "round-robin"; -+ ti,cable-mode = "coax"; ++ ti,cable-mode = "stp"; + + port@0 { + ti954_des0ep0: endpoint@0 { @@ -17090,55 +15450,226 @@ index 0000000..8ffafb2 + }; + }; + -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <3>; -+ /* MOST node(s) */ -+ }; -+ -+ i2c@4 { ++ i2c@2 { + #address-cells = <1>; + #size-cells = <0>; -+ reg = <4>; ++ reg = <2>; ++ /* Slot B (CN11) */ + -+ rpi_camera: ov5647@36 { -+ compatible = "ovti,ov5647"; -+ reg = <0x36>; ++ ov106xx@4 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x64>; + + port@0 { -+ rpi_camera_in: endpoint { ++ ov106xx_in4: endpoint { + clock-lanes = <0>; -+ data-lanes = <1 2>; ++ data-lanes = <1 2 3 4>; + remote-endpoint = <&vin4ep0>; + }; + }; ++ port@1 { ++ ov106xx_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ ov106xx_ti964_des1ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep0>; ++ }; ++ ov106xx_ti954_des1ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep0>; ++ }; ++ }; + }; -+ }; + -+ i2c@5 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <5>; -+ -+ cmos_camera: ov5642@3c { -+ compatible = "ovti,ov5642"; -+ reg = <0x3c>; -+ clocks = <&camera_clk>; -+ clock-names = "mclk"; ++ ov106xx@5 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x65>; + + port@0 { -+ cmos_camera_in: endpoint { ++ ov106xx_in5: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; + remote-endpoint = <&vin5ep0>; + }; + }; ++ port@1 { ++ ov106xx_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ ov106xx_ti964_des1ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep1>; ++ }; ++ ov106xx_ti954_des1ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@6 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x66>; ++ ++ port@0 { ++ ov106xx_in6: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin6ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ ov106xx_ti964_des1ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@7 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x67>; ++ ++ port@0 { ++ ov106xx_in7: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin7ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ ov106xx_ti964_des1ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep3>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@1 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "stp"; ++ ++ port@0 { ++ ti964_des1ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ ti964_des1ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ ti964_des1ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ ti964_des1ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ ti964_csi2ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@1 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_b_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "stp"; ++ ++ port@0 { ++ ti954_des1ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ ti954_des1ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ }; ++ port@1 { ++ ti954_csi2ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ ++ /* MAX9286 @ 0x2c */ ++ max9286-max9271@1 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des1ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ max9286_des1ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ max9286_des1ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ max9286_des1ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ max9286_csi2ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; + }; + }; + -+ i2c@7 { ++ i2c@3 { + #address-cells = <1>; + #size-cells = <0>; -+ reg = <7>; ++ reg = <3>; ++ /* Slot C (CN12) */ ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; + /* Slot A (CN10) */ + + video_a_ext0: pca9535@26 { @@ -17185,92 +15716,393 @@ index 0000000..8ffafb2 + }; + video_a_cam_pwr3 { + gpio-hog; -+ gpios = <15 GPIO_ACTIVE_HIGH>; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A led"; ++ }; ++ }; ++ ++ video_a_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg2"; ++ }; ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; ++ }; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; ++ }; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; ++ }; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A LED"; ++ }; ++ }; ++ }; ++ ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ /* Slot B (CN11) */ ++ ++ video_b_ext0: pca9535@26 { ++ compatible = "nxp,pca9535"; ++ reg = <0x26>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_b_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg1"; ++ }; ++ video_b_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg0"; ++ }; ++ video_b_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR_SHDN"; ++ }; ++ video_b_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR0"; ++ }; ++ video_b_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR1"; ++ }; ++ video_b_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR2"; ++ }; ++ video_b_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR3"; ++ }; ++ video_b_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B DES_SHDN"; ++ }; ++ video_b_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B led"; ++ }; ++ }; ++ ++ video_b_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_b_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg2"; ++ }; ++ video_b_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg1"; ++ }; ++ video_b_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg0"; ++ }; ++ video_b_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR_SHDN"; ++ }; ++ video_b_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR0"; ++ }; ++ video_b_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR1"; ++ }; ++ video_b_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR2"; ++ }; ++ video_b_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR3"; ++ }; ++ video_b_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B DES_SHDN"; ++ }; ++ video_b_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B LED"; ++ }; ++ }; ++ }; ++ ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ /* Slot C (CN12) */ ++ }; ++ }; ++}; ++ ++&i2c4 { ++ i2cswitch4: pca9548@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x74>; ++ reset-gpios= <&gpio5 15 GPIO_ACTIVE_LOW>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ /* FAN node - EMC2103 */ ++ fan_ctrl:ecm2103@2e { ++ compatible = "emc2103"; ++ reg = <0x2e>; ++ }; ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ /* Power nodes - 2 x TPS544x20 */ ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ /* CAN and power board nodes */ ++ ++ gpio_ext_pwr: pca9535@22 { ++ compatible = "nxp,pca9535"; ++ reg = <0x22>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio1>; ++ interrupts = <25 IRQ_TYPE_EDGE_FALLING>; ++ ++ /* enable input DCDC after wake-up signal released */ ++ pwr_hold { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; + output-high; -+ line-name = "Video-A PWR3"; ++ line-name = "pwr_hold"; + }; -+ video_a_des_shdn { ++ ++ /* CAN0 */ ++ can0_stby { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A DES_SHDN"; ++ output-low; ++ line-name = "can0_stby"; + }; -+ video_a_des_led { ++ can0_load { + gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; ++ gpios = <0 GPIO_ACTIVE_HIGH>; + output-low; -+ line-name = "Video-A led"; ++ line-name = "can0_120R_load"; + }; -+ }; -+ -+ video_a_ext1: max7325@5c { -+ compatible = "maxim,max7325"; -+ reg = <0x5c>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ video_a_des_cfg2 { ++ /* CAN1 */ ++ can1_stby { + gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A cfg2"; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can1_stby"; + }; -+ video_a_des_cfg1 { ++ can1_load { + gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A cfg1"; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can1_120R_load"; + }; -+ video_a_des_cfg0 { ++ /* CAN2 */ ++ can2_stby { + gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-A cfg0"; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can2_stby"; + }; -+ video_a_pwr_shdn { ++ can2_load { + gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR_SHDN"; ++ gpios = <2 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can2_120R_load"; + }; -+ video_a_cam_pwr0 { ++ can2_rst { + gpio-hog; + gpios = <8 GPIO_ACTIVE_HIGH>; + output-high; -+ line-name = "Video-A PWR0"; -+ }; -+ video_a_cam_pwr1 { -+ gpio-hog; -+ gpios = <9 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR1"; ++ line-name = "can2_rst"; + }; -+ video_a_cam_pwr2 { ++ /* CAN3 */ ++ can3_stby { + gpio-hog; -+ gpios = <10 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR2"; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can3_stby"; + }; -+ video_a_cam_pwr3 { ++ can3_load { + gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR3"; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can3_120R_load"; + }; -+ video_a_des_shdn { ++ can3_rst { + gpio-hog; -+ gpios = <13 GPIO_ACTIVE_HIGH>; ++ gpios = <9 GPIO_ACTIVE_HIGH>; + output-high; -+ line-name = "Video-A DES_SHDN"; -+ }; -+ video_a_led { -+ gpio-hog; -+ gpios = <12 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "Video-A LED"; ++ line-name = "can3_rst"; + }; + }; + }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ /* FPDLink output node - DS90UH947 */ ++ }; ++ ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ /* BCM switch node */ ++ }; ++ ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ /* LED board node(s) */ ++ ++ gpio_ext_led: pca9535@22 { ++ compatible = "nxp,pca9535"; ++ reg = <0x22>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ /* gpios 0..7 are used for indication LEDs, low-active */ ++ }; ++ }; ++ ++ i2c@6 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <6>; ++ /* M2 connector i2c node(s) */ ++ }; ++ ++ /* port 7 is not used */ + }; +}; + @@ -17348,14 +16180,110 @@ index 0000000..8ffafb2 + vin1_ti964_des0ep1: endpoint@1 { + remote-endpoint = <&ti964_des0ep1>; + }; -+ vin1_ti954_des0ep1: endpoint@2 { -+ remote-endpoint = <&ti954_des0ep1>; ++ vin1_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin2 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ vin2_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin3 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ vin3_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&vin4 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi41"; ++ virtual,channel = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin4_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ vin4_ti964_des1ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep0>; ++ }; ++ vin4_ti954_des1ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep0>; + }; + }; + }; +}; + -+&vin2 { ++&vin5 { + status = "okay"; + + ports { @@ -17363,30 +16291,33 @@ index 0000000..8ffafb2 + #size-cells = <0>; + + port@0 { -+ vin2ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <2>; ++ vin5ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <1>; ++ remote-endpoint = <&ov106xx_in5>; + data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in2>; + }; + }; + port@1 { -+ csi0ep2: endpoint { -+ remote-endpoint = <&csi2_40_ep>; ++ csi2ep1: endpoint { ++ remote-endpoint = <&csi2_41_ep>; + }; + }; + port@2 { -+ vin2_max9286_des0ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep2>; ++ vin5_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; + }; -+ vin2_ti964_des0ep2: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep2>; ++ vin5_ti964_des1ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep1>; ++ }; ++ vin5_ti954_des1ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep1>; + }; + }; + }; +}; + -+&vin3 { ++&vin6 { + status = "okay"; + + ports { @@ -17394,30 +16325,30 @@ index 0000000..8ffafb2 + #size-cells = <0>; + + port@0 { -+ vin3ep0: endpoint { -+ csi,select = "csi40"; -+ virtual,channel = <3>; ++ vin6ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <2>; ++ remote-endpoint = <&ov106xx_in6>; + data-lanes = <1 2 3 4>; -+ remote-endpoint = <&ov106xx_in3>; + }; + }; + port@1 { -+ csi0ep3: endpoint { -+ remote-endpoint = <&csi2_40_ep>; ++ csi2ep2: endpoint { ++ remote-endpoint = <&csi2_41_ep>; + }; + }; + port@2 { -+ vin3_max9286_des0ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des0ep3>; ++ vin6_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; + }; -+ vin3_ti964_des0ep3: endpoint@1 { -+ remote-endpoint = <&ti964_des0ep3>; ++ vin6_ti964_des1ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep2>; + }; + }; + }; +}; + -+&vin4 { ++&vin7 { + status = "okay"; + + ports { @@ -17425,37 +16356,24 @@ index 0000000..8ffafb2 + #size-cells = <0>; + + port@0 { -+ vin4ep0: endpoint { -+ csi,select = "csi20"; -+ virtual,channel = <0>; -+ remote-endpoint = <&rpi_camera_in>; -+ data-lanes = <1 2>; ++ vin7ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <3>; ++ remote-endpoint = <&ov106xx_in7>; ++ data-lanes = <1 2 3 4>; + }; + }; + port@1 { -+ csi2ep0: endpoint { -+ remote-endpoint = <&csi2_20_ep>; ++ csi2ep3: endpoint { ++ remote-endpoint = <&csi2_41_ep>; + }; + }; -+ }; -+}; -+ -+&vin5 { -+ pinctrl-0 = <&vin5_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ vin5ep0: endpoint@0 { -+ bus-width = <8>; -+ /* #HSYNC, #VSYNC */ -+ vsync-active = <1>; -+ hsync-active = <0>; -+ remote-endpoint = <&cmos_camera_in>; ++ port@2 { ++ vin7_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ vin7_ti964_des1ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep3>; + }; + }; + }; @@ -17495,84 +16413,72 @@ index 0000000..8ffafb2 + }; +}; + -+&csi2_20 { ++&csi2_41 { + status = "okay"; + + virtual,channel { + csi2_vc0 { -+ data,type = "raw8"; ++ data,type = "ycbcr422"; + receive,vc = <0>; + }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; + }; + + port { + #address-cells = <1>; + #size-cells = <0>; + -+ csi2_20_ep: endpoint { ++ csi2_41_ep: endpoint { + clock-lanes = <0>; -+ data-lanes = <1 2>; -+ csi-rate = <280>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; + }; + }; +}; + -+ +&rcar_sound { + pinctrl-0 = <&sound_clk_pins>; -+ pinctrl-names = "default"; + + /* Multi DAI */ + #sound-dai-cells = <1>; ++}; + -+ rcar_sound,dai { -+ dai0 { -+ playback = <&ssi3>; -+ capture = <&ssi4>; -+ }; -+ -+ dai1 { -+ playback = <&ssi0 &src0 &dvc0>; -+ capture = <&ssi1 &src1 &dvc1>; -+ }; -+ -+ dai2 { -+ capture = <&ssi6>; -+ }; ++&sata { ++ status = "okay"; ++}; + -+ dai3 { -+ playback = <&ssi7>; -+ capture = <&ssi8>; -+ }; -+ }; ++&ssi1 { ++ /delete-property/shared-pin; +}; + -+&sdhi3 { -+ pinctrl-0 = <&sdhi3_pins_3v3>; -+ pinctrl-1 = <&sdhi3_pins_1v8>; -+ pinctrl-names = "default", "state_uhs"; ++&avb { ++ /delete-property/phy-handle; ++ /delete-property/phy-gpios; ++ phy-mode = "rgmii"; + -+ vmmc-supply = <&wlan_en>; -+ vqmmc-supply = <&vccq_sdhi3>; -+ keep-power-in-suspend; -+ enable-sdio-wakeup; -+ bus-width = <4>; -+ no-1-8-v; -+ non-removable; -+ cap-power-off-card; -+ max-frequency = <26000000>; -+ status = "okay"; ++ /delete-node/ethernet-phy@0; + -+ #address-cells = <1>; -+ #size-cells = <0>; -+ wlcore: wlcore@2 { -+ compatible = "ti,wl1837"; -+ reg = <2>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>; ++ fixed-link { ++ speed = <100>; ++ full-duplex; + }; +}; + ++&msiof1 { ++ status = "disabled"; ++}; ++ +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; @@ -17580,6 +16486,10 @@ index 0000000..8ffafb2 + status = "okay"; +}; + ++&xhci0 { ++ status = "okay"; ++}; ++ +&ehci0 { + status = "okay"; +}; @@ -17588,28 +16498,120 @@ index 0000000..8ffafb2 + status = "okay"; +}; + -+&xhci0 { -+ status = "okay"; -+}; ++&can0 { ++ pinctrl-0 = <&can0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; ++}; ++ ++&can1 { ++ pinctrl-0 = <&can1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; ++}; ++ ++&canfd { ++ pinctrl-0 = <&canfd0_pins &canfd1_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ ++ renesas,can-clock-select = <0x0>; ++ ++ channel0 { ++ status = "okay"; ++ }; ++ ++ channel1 { ++ status = "okay"; ++ }; ++}; ++ ++/* uncomment to enable CN12 on VIN4-7 */ ++//#include "ulcb-vb-cn12.dtsi" +diff --git a/arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi b/arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi +new file mode 100644 +index 0000000..3d4bcde +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi +@@ -0,0 +1,557 @@ ++/* ++ * Device Tree Source for the ULCB Videobox Mini board ++ * ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++/ { ++ aliases { ++ serial1 = &scif1; ++ }; ++ ++ lvds-encoder { ++ compatible = "thine,thc63lvdm83d"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ lvds_enc_in: endpoint { ++ remote-endpoint = <&du_out_lvds0>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ lvds_enc_out: endpoint { ++ remote-endpoint = <&lvds_in>; ++ }; ++ }; ++ }; ++ }; ++ ++ lvds { ++ compatible = "lvds-connector"; ++ ++ width-mm = <210>; ++ height-mm = <158>; ++ ++ panel-timing { ++ /* 1280x800 @60Hz */ ++ clock-frequency = <65000000>; ++ hactive = <1280>; ++ vactive = <800>; ++ hsync-len = <40>; ++ hfront-porch = <80>; ++ hback-porch = <40>; ++ vfront-porch = <14>; ++ vback-porch = <14>; ++ vsync-len = <4>; ++ }; + -+&msiof1 { -+ status = "disabled"; ++ port { ++ lvds_in: endpoint { ++ remote-endpoint = <&lvds_enc_out>; ++ }; ++ }; ++ }; +}; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + status = "okay"; -+ -+ renesas,can-clock-select = <0x0>; +}; -+ ++ +&can1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + status = "okay"; -+ -+ renesas,can-clock-select = <0x0>; +}; + +&canfd { @@ -17626,542 +16628,473 @@ index 0000000..8ffafb2 + }; +}; + -+&ssi4 { -+ shared-pin; -+}; ++&csi2_41 { ++ status = "okay"; + -+&ssi8 { -+ shared-pin; -+}; ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; + -+&pciec1 { -+ pcie3v3-supply = <&mpcie_3v3>; -+ pcie1v8-supply = <&mpcie_1v8>; -+}; ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; + ++ csi2_41_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; + ++&i2c1 { ++ pinctrl-0 = <&i2c1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; + -diff --git a/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi b/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi -new file mode 100644 -index 0000000..92ed4a4 ---- /dev/null -+++ b/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi -@@ -0,0 +1,515 @@ -+/* -+ * Device Tree Source for the H3ULCB Videobox board: -+ * this adding conflicting resource on VIN4/VIN5/VIN6/VIN7 for CN12 -+ * -+ * Copyright (C) 2017 Renesas Electronics Corp. -+ * Copyright (C) 2017 Cogent Embedded, Inc. -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ ++ clock-frequency = <100000>; + -+&i2cswitch2 { -+ i2c@3 { ++ i2cswitch1: i2c-switch@74 { ++ compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; -+ reg = <3>; -+ /* Slot C (CN12) */ -+ -+ ov106xx@8 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x68>; -+ -+ port@0 { -+ ov106xx_in8: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2>; -+ remote-endpoint = <&vin4ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des2ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des2ep0>; -+ }; -+ ov106xx_ti964_des2ep0: endpoint@1 { -+ remote-endpoint = <&ti964_des2ep0>; -+ }; -+ ov106xx_ti954_des2ep0: endpoint@2 { -+ remote-endpoint = <&ti954_des2ep0>; -+ }; -+ }; -+ }; -+ -+ ov106xx@9 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x69>; ++ reg = <0x74>; ++ reset-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + -+ port@0 { -+ ov106xx_in9: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2>; -+ remote-endpoint = <&vin5ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des2ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des2ep1>; -+ }; -+ ov106xx_ti964_des2ep1: endpoint@1 { -+ remote-endpoint = <&ti964_des2ep1>; -+ }; -+ ov106xx_ti954_des2ep1: endpoint@2 { -+ remote-endpoint = <&ti954_des2ep1>; -+ }; -+ }; -+ }; ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; + -+ ov106xx@10 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x6a>; ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; + -+ port@0 { -+ ov106xx_in10: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2>; -+ remote-endpoint = <&vin6ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des2ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des2ep2>; ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin4ep0>; ++ }; + }; -+ ov106xx_ti964_des2ep2: endpoint@1 { -+ remote-endpoint = <&ti964_des2ep2>; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ ov106xx_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; + }; + }; -+ }; + -+ ov106xx@11 { -+ compatible = "ovti,ov106xx"; -+ reg = <0x6b>; ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; + -+ port@0 { -+ ov106xx_in11: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2>; -+ remote-endpoint = <&vin7ep0>; -+ }; -+ }; -+ port@1 { -+ ov106xx_max9286_des2ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des2ep3>; ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin5ep0>; ++ }; + }; -+ ov106xx_ti964_des2ep3: endpoint@1 { -+ remote-endpoint = <&ti964_des2ep3>; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ ov106xx_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; + }; + }; -+ }; + -+ /* DS90UB964 @ 0x3a */ -+ ti964-ti9x3@2 { -+ compatible = "ti,ti964-ti9x3"; -+ reg = <0x3a>; -+ ti,sensor_delay = <350>; -+ ti,links = <4>; -+ ti,lanes = <2>; -+ ti,forwarding-mode = "round-robin"; -+ ti,cable-mode = "coax"; ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; + -+ port@0 { -+ ti964_des2ep0: endpoint@0 { -+ ti9x3-addr = <0x0c>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in8>; -+ }; -+ ti964_des2ep1: endpoint@1 { -+ ti9x3-addr = <0x0d>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in9>; -+ }; -+ ti964_des2ep2: endpoint@2 { -+ ti9x3-addr = <0x0e>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in10>; ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin6ep0>; ++ }; + }; -+ ti964_des2ep3: endpoint@3 { -+ ti9x3-addr = <0x0f>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in11>; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ ov106xx_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; + }; + }; -+ port@1 { -+ ti964_csi1ep0: endpoint { -+ csi-rate = <1450>; -+ remote-endpoint = <&csi2_20_ep>; ++ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin7ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ ov106xx_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; + }; + }; -+ }; + -+ /* DS90UB954 @ 0x38 */ -+ ti954-ti9x3@2 { -+ compatible = "ti,ti954-ti9x3"; -+ reg = <0x38>; -+ /* gpios = <&video_c_ext1 10 GPIO_ACTIVE_HIGH>; */ -+ ti,sensor_delay = <350>; -+ ti,links = <2>; -+ ti,lanes = <2>; -+ ti,forwarding-mode = "round-robin"; -+ ti,cable-mode = "coax"; ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; + -+ port@0 { -+ ti954_des2ep0: endpoint@0 { -+ ti9x3-addr = <0x0c>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in8>; ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; + }; -+ ti954_des2ep1: endpoint@1 { -+ ti9x3-addr = <0x0d>; -+ dvp-order = <0>; -+ remote-endpoint = <&ov106xx_in9>; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; + }; + }; -+ port@1 { -+ ti954_csi1ep0: endpoint { -+ csi-rate = <1450>; -+ remote-endpoint = <&csi2_20_ep>; ++ ++ ti964-ti9x3@0 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "coax"; ++ ++ port@0 { ++ ti964_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti964_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ ti964_des0ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ ti964_des0ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ ti964_csi0ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; + }; + }; + }; + -+ /* MAX9286 @ 0x2c */ -+ max9286-max9271@2 { -+ compatible = "maxim,max9286-max9271"; -+ reg = <0x2c>; -+ maxim,sensor_delay = <350>; -+ maxim,links = <4>; -+ maxim,lanes = <2>; -+ maxim,resetb-gpio = <1>; -+ maxim,fsync-mode = "automatic"; -+ maxim,timeout = <100>; ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; + -+ port@0 { -+ max9286_des2ep0: endpoint@0 { -+ max9271-addr = <0x50>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in8>; ++ gpio_exp_6c: gpio@6c { ++ compatible = "maxim,max7325"; ++ reg = <0x6c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ virq { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video VIRQ"; + }; -+ max9286_des2ep1: endpoint@1 { -+ max9271-addr = <0x51>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in9>; ++ des_cfg { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video CNFG0"; + }; -+ max9286_des2ep2: endpoint@2 { -+ max9271-addr = <0x52>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in10>; ++ pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video PWR_SHDN"; + }; -+ max9286_des2ep3: endpoint@3 { -+ max9271-addr = <0x53>; -+ dvp-order = <1>; -+ remote-endpoint = <&ov106xx_in11>; ++ cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video PWR0"; + }; -+ }; -+ port@1 { -+ max9286_csi1ep0: endpoint { -+ csi-rate = <700>; -+ remote-endpoint = <&csi2_20_ep>; ++ cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video PWR1"; ++ }; ++ cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video PWR2"; ++ }; ++ cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video PWR3"; ++ }; ++ des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video DES_SHDN"; ++ }; ++ fpdl_shdn { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video FPDL_SHDN"; + }; + }; + }; -+ }; -+ -+ i2c@4 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <4>; -+ /* Slot C (CN12) */ -+ -+ video_c_ext0: pca9535@26 { -+ compatible = "nxp,pca9535"; -+ reg = <0x26>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ video_c_des_cfg1 { -+ gpio-hog; -+ gpios = <5 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-C cfg1"; -+ }; -+ video_c_des_cfg0 { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-C cfg0"; -+ }; -+ video_c_pwr_shdn { -+ gpio-hog; -+ gpios = <3 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-C PWR_SHDN"; -+ }; -+ video_c_cam_pwr0 { -+ gpio-hog; -+ gpios = <12 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-C PWR0"; -+ }; -+ video_c_cam_pwr1 { -+ gpio-hog; -+ gpios = <13 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-C PWR1"; -+ }; -+ video_c_cam_pwr2 { -+ gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-C PWR2"; -+ }; -+ video_c_cam_pwr3 { -+ gpio-hog; -+ gpios = <15 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-C PWR3"; -+ }; -+ video_c_des_shdn { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-C DES_SHDN"; -+ }; -+ video_c_des_led { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "Video-C led"; -+ }; -+ }; ++ }; ++}; + -+ video_c_ext1: max7325@5c { -+ compatible = "maxim,max7325"; -+ reg = <0x5c>; -+ gpio-controller; -+ #gpio-cells = <2>; ++&gpio1 { ++ can0stby { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "CAN0STBY"; ++ }; ++}; + -+ video_c_des_cfg2 { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-C cfg2"; -+ }; -+ video_c_des_cfg1 { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-C cfg1"; -+ }; -+ video_c_des_cfg0 { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "Video-C cfg0"; -+ }; -+ video_c_pwr_shdn { -+ gpio-hog; -+ gpios = <14 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-C PWR_SHDN"; -+ }; -+ video_c_cam_pwr0 { -+ gpio-hog; -+ gpios = <8 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-C PWR0"; -+ }; -+ video_c_cam_pwr1 { -+ gpio-hog; -+ gpios = <9 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-C PWR1"; -+ }; -+ video_c_cam_pwr2 { -+ gpio-hog; -+ gpios = <10 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-C PWR2"; -+ }; -+ video_c_cam_pwr3 { -+ gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-C PWR3"; -+ }; -+ video_c_des_shdn { -+ gpio-hog; -+ gpios = <13 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-C DES_SHDN"; -+ }; -+ video_c_led { -+ gpio-hog; -+ gpios = <12 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "Video-C LED"; -+ }; -+ }; ++&gpio2 { ++ can0_load { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "CAN0Loff"; ++ }; ++}; ++ ++&pfc { ++ can0_pins: can0 { ++ groups = "can0_data_a"; ++ function = "can0"; ++ }; ++ ++ can1_pins: can1 { ++ groups = "can1_data"; ++ function = "can1"; ++ }; ++ ++ canfd0_pins: canfd0 { ++ groups = "canfd0_data_a"; ++ function = "canfd0"; ++ }; ++ ++ canfd1_pins: canfd1 { ++ groups = "canfd1_data"; ++ function = "canfd1"; ++ }; ++ ++ i2c1_pins: i2c1 { ++ groups = "i2c1_b"; ++ function = "i2c1"; ++ }; ++ ++ scif1_pins: scif1 { ++ groups = "scif1_data_a"; ++ function = "scif1"; + }; +}; + ++&scif1 { ++ pinctrl-0 = <&scif1_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ +&vin4 { ++ status = "okay"; ++ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + vin4ep0: endpoint { -+ csi,select = "csi20"; ++ csi,select = "csi41"; + virtual,channel = <0>; -+ remote-endpoint = <&ov106xx_in8>; -+ data-lanes = <1 2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; + }; + }; + port@1 { -+ csi2ep0: endpoint { -+ remote-endpoint = <&csi2_20_ep>; ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_41_ep>; + }; + }; + port@2 { -+ vin4_max9286_des2ep0: endpoint@0 { -+ remote-endpoint = <&max9286_des2ep0>; -+ }; -+ vin4_ti964_des2ep0: endpoint@1 { -+ remote-endpoint = <&ti964_des2ep0>; ++ vin4_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; + }; -+ vin4_ti954_des2ep0: endpoint@2 { -+ remote-endpoint = <&ti954_des2ep0>; ++ vin4_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; + }; + }; + }; +}; + +&vin5 { ++ status = "okay"; ++ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { -+ vin5ep0: endpoint@0 { -+ csi,select = "csi20"; ++ vin5ep0: endpoint { ++ csi,select = "csi41"; + virtual,channel = <1>; -+ remote-endpoint = <&ov106xx_in9>; -+ data-lanes = <1 2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; + }; + }; + port@1 { -+ csi2ep1: endpoint { -+ remote-endpoint = <&csi2_20_ep>; ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_41_ep>; + }; + }; + port@2 { -+ vin5_max9286_des2ep1: endpoint@0 { -+ remote-endpoint = <&max9286_des2ep1>; -+ }; -+ vin5_ti964_des2ep1: endpoint@1 { -+ remote-endpoint = <&ti964_des2ep1>; ++ vin5_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; + }; -+ vin5_ti954_des2ep1: endpoint@2 { -+ remote-endpoint = <&ti954_des2ep1>; ++ vin5_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; + }; + }; + }; +}; + +&vin6 { ++ status = "okay"; ++ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { -+ vin6ep0: endpoint@0 { -+ csi,select = "csi20"; ++ vin6ep0: endpoint { ++ csi,select = "csi41"; + virtual,channel = <2>; -+ remote-endpoint = <&ov106xx_in10>; -+ data-lanes = <1 2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; + }; + }; + port@1 { -+ csi2ep2: endpoint { -+ remote-endpoint = <&csi2_20_ep>; ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_41_ep>; + }; + }; + port@2 { -+ vin6_max9286_des2ep2: endpoint@0 { -+ remote-endpoint = <&max9286_des2ep2>; ++ vin6_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; + }; -+ vin6_ti964_des2ep2: endpoint@1 { -+ remote-endpoint = <&ti964_des2ep2>; ++ vin6_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; + }; + }; + }; +}; + +&vin7 { ++ status = "okay"; ++ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { -+ vin7ep0: endpoint@0 { -+ csi,select = "csi20"; ++ vin7ep0: endpoint { ++ csi,select = "csi41"; + virtual,channel = <3>; -+ remote-endpoint = <&ov106xx_in11>; -+ data-lanes = <1 2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; + }; + }; + port@1 { -+ csi2ep3: endpoint { -+ remote-endpoint = <&csi2_20_ep>; ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_41_ep>; + }; + }; + port@2 { -+ vin7_max9286_des2ep3: endpoint@0 { -+ remote-endpoint = <&max9286_des2ep3>; ++ vin7_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; + }; -+ vin7_ti964_des2ep3: endpoint@1 { -+ remote-endpoint = <&ti964_des2ep3>; ++ vin7_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; + }; + }; + }; +}; -+ -+&csi2_20 { -+ status = "okay"; -+ -+ virtual,channel { -+ csi2_vc0 { -+ data,type = "ycbcr422"; -+ receive,vc = <0>; -+ }; -+ csi2_vc1 { -+ data,type = "ycbcr422"; -+ receive,vc = <1>; -+ }; -+ csi2_vc2 { -+ data,type = "ycbcr422"; -+ receive,vc = <2>; -+ }; -+ csi2_vc3 { -+ data,type = "ycbcr422"; -+ receive,vc = <3>; -+ }; -+ }; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ csi2_20_ep: endpoint { -+ clock-lanes = <0>; -+ data-lanes = <1 2>; -+ csi-rate = <300>; -+ }; -+ }; -+}; -- 1.9.1 diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend index 7421ef9..57a1ee6 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend @@ -81,11 +81,13 @@ KERNEL_DEVICETREE_append_h3ulcb = " \ renesas/r8a7795-es1-h3ulcb-had-beta.dtb \ renesas/r8a7795-es1-h3ulcb-kf.dtb \ renesas/r8a7795-es1-h3ulcb-vb.dtb \ + renesas/r8a7795-es1-h3ulcb-vbm.dtb \ renesas/r8a7795-h3ulcb-view.dtb \ renesas/r8a7795-h3ulcb-had-alfa.dtb \ renesas/r8a7795-h3ulcb-had-beta.dtb \ renesas/r8a7795-h3ulcb-kf.dtb \ renesas/r8a7795-h3ulcb-vb.dtb \ + renesas/r8a7795-h3ulcb-vbm.dtb \ " KERNEL_DEVICETREE_append_m3ulcb = " \ @@ -106,5 +108,5 @@ KERNEL_DEVICETREE_append_eagle = " \ KERNEL_DEVICETREE_append_v3msk = " \ renesas/r8a7797-v3msk.dtb \ renesas/r8a7797-v3msk-kf.dtb \ - renesas/r8a7797-v3msk-vb.dtb \ + renesas/r8a7797-v3msk-vbm.dtb \ " -- cgit 1.2.3-korg From 3c441bc9a5e5936747c58f49029edf63d0fe96e3 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Tue, 14 Nov 2017 20:47:13 +0300 Subject: V3M: support MSIOF on KF V0 1) support MSIOF2/3/4 on Kingfisher V0 board 2) remove unused pins on V3MSK from dts file --- .../recipes-bsp/spidev-dbg/files/spidev-dbg.tar.gz | Bin 5496 -> 5503 bytes .../0040-arm64-dts-renesas-add-ADAS-boards.patch | 83 +++++++++++++++++---- 2 files changed, 69 insertions(+), 14 deletions(-) (limited to 'meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch') diff --git a/meta-rcar-gen3-adas/recipes-bsp/spidev-dbg/files/spidev-dbg.tar.gz b/meta-rcar-gen3-adas/recipes-bsp/spidev-dbg/files/spidev-dbg.tar.gz index 49e3192..5556478 100644 Binary files a/meta-rcar-gen3-adas/recipes-bsp/spidev-dbg/files/spidev-dbg.tar.gz and b/meta-rcar-gen3-adas/recipes-bsp/spidev-dbg/files/spidev-dbg.tar.gz differ diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch index 14a7b80..1825776 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch @@ -33,7 +33,7 @@ Signed-off-by: Vladimir Barinov .../dts/renesas/legacy/r8a7795-h3ulcb-kf-v1.dts | 465 ++++++ .../dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts | 1214 ++++++++++++++ .../dts/renesas/legacy/r8a7796-m3ulcb-kf-v1.dts | 465 ++++++ - .../dts/renesas/legacy/r8a7797-v3msk-kf-v0.dts | 20 + + .../dts/renesas/legacy/r8a7797-v3msk-kf-v0.dts | 82 + .../boot/dts/renesas/legacy/ulcb-kf-cmos.dtsi | 75 + .../arm64/boot/dts/renesas/legacy/ulcb-kf-rpi.dtsi | 77 + .../dts/renesas/r8a7795-es1-h3ulcb-had-alfa.dts | 22 + @@ -58,7 +58,7 @@ Signed-off-by: Vladimir Barinov arch/arm64/boot/dts/renesas/r8a7797-eagle.dts | 561 +++++++ arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts | 578 +++++++ arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts | 498 ++++++ - arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts | 320 ++++ + arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts | 313 ++++ arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi | 518 ++++++ arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi | 30 + arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi | 46 + @@ -66,7 +66,7 @@ Signed-off-by: Vladimir Barinov arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi | 515 ++++++ arch/arm64/boot/dts/renesas/ulcb-vb.dtsi | 1726 ++++++++++++++++++++ arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi | 557 +++++++ - 41 files changed, 16737 insertions(+) + 41 files changed, 16792 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/legacy/Makefile create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts @@ -6207,10 +6207,10 @@ index 0000000..637c840 +}; diff --git a/arch/arm64/boot/dts/renesas/legacy/r8a7797-v3msk-kf-v0.dts b/arch/arm64/boot/dts/renesas/legacy/r8a7797-v3msk-kf-v0.dts new file mode 100644 -index 0000000..cc04429 +index 0000000..674d3bf --- /dev/null +++ b/arch/arm64/boot/dts/renesas/legacy/r8a7797-v3msk-kf-v0.dts -@@ -0,0 +1,20 @@ +@@ -0,0 +1,82 @@ +/* + * Device Tree Source for the V3MSK Kingfisher V0 board on r8a7797 + * @@ -6231,6 +6231,68 @@ index 0000000..cc04429 +&i2cswitch4 { + reg = <0x74>; +}; ++ ++&msiof1 { ++ pinctrl-0 = <&msiof1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ spidev@0 { ++ compatible = "renesas,sh-msiof"; ++ reg = <0>; ++ spi-max-frequency = <66666666>; ++ spi-cpha; ++ spi-cpol; ++ }; ++}; ++ ++&msiof2 { ++ pinctrl-0 = <&msiof2_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ spidev@0 { ++ compatible = "renesas,sh-msiof"; ++ reg = <0>; ++ spi-max-frequency = <66666666>; ++ spi-cpha; ++ spi-cpol; ++ }; ++}; ++ ++&msiof3 { ++ pinctrl-0 = <&msiof3_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ spidev@0 { ++ compatible = "renesas,sh-msiof"; ++ reg = <0>; ++ spi-max-frequency = <66666666>; ++ spi-cpha; ++ spi-cpol; ++ }; ++}; ++ ++&pfc { ++ msiof1_pins: spi2 { ++ groups = "msiof1_clk", "msiof1_sync", "msiof1_rxd", ++ "msiof1_txd"; ++ function = "msiof1"; ++ }; ++ ++ msiof2_pins: spi3 { ++ groups = "msiof2_clk", "msiof2_sync", "msiof2_rxd", ++ "msiof2_txd"; ++ function = "msiof2"; ++ }; ++ ++ msiof3_pins: spi4 { ++ groups = "msiof3_clk", "msiof3_sync", "msiof3_rxd", ++ "msiof3_txd"; ++ function = "msiof3"; ++ }; ++}; diff --git a/arch/arm64/boot/dts/renesas/legacy/ulcb-kf-cmos.dtsi b/arch/arm64/boot/dts/renesas/legacy/ulcb-kf-cmos.dtsi new file mode 100644 index 0000000..2145f5e @@ -11808,10 +11870,10 @@ index 0000000..28a0b92 +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts new file mode 100644 -index 0000000..bf2501e +index 0000000..f683ec3 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts -@@ -0,0 +1,320 @@ +@@ -0,0 +1,313 @@ +/* + * Device Tree Source for the V3M Starter Kit board on r8a7797 + * @@ -11978,8 +12040,6 @@ index 0000000..bf2501e +}; + +&du { -+ pinctrl-0 = <&du_pins>; -+ pinctrl-names = "default"; + status = "okay"; + + ports { @@ -12023,11 +12083,6 @@ index 0000000..bf2501e + function = "avb0"; + }; + -+ du_pins: du { -+ groups = "du_rgb666", "du_sync", "du_clk_out_0"; -+ function = "du"; -+ }; -+ + sdhi2_pins_3v3: sdhi2_3v3 { + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; -- cgit 1.2.3-korg From 8a92de0ca46277305839c838a5cf72f37646b196 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Mon, 20 Nov 2017 15:43:00 +0300 Subject: R8A7797: enable IMR resourses in kernel --- ...as-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch | 50 +++++++++++++++++++--- .../0040-arm64-dts-renesas-add-ADAS-boards.patch | 12 +++--- 2 files changed, 49 insertions(+), 13 deletions(-) (limited to 'meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch') diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch index 93cf1ec..d9b00f6 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch @@ -8,10 +8,10 @@ This adds Renesas R8A7797 SoC support Signed-off-by: Vladimir Barinov --- arch/arm64/Kconfig.platforms | 6 + - arch/arm64/boot/dts/renesas/r8a7797.dtsi | 973 ++++++++++ + arch/arm64/boot/dts/renesas/r8a7797.dtsi | 1005 ++++++++++ drivers/clk/renesas/Kconfig | 1 + drivers/clk/renesas/Makefile | 1 + - drivers/clk/renesas/r8a7797-cpg-mssr.c | 218 +++ + drivers/clk/renesas/r8a7797-cpg-mssr.c | 222 +++ drivers/clk/renesas/rcar-gen3-cpg.c | 41 +- drivers/clk/renesas/rcar-gen3-cpg.h | 6 + drivers/clk/renesas/renesas-cpg-mssr.c | 6 + @@ -48,7 +48,7 @@ Signed-off-by: Vladimir Barinov drivers/thermal/rcar_gen3_thermal.c | 29 + include/dt-bindings/clock/r8a7797-cpg-mssr.h | 48 + include/dt-bindings/power/r8a7797-sysc.h | 32 + - 41 files changed, 4256 insertions(+), 30 deletions(-) + 41 files changed, 4292 insertions(+), 30 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/r8a7797.dtsi create mode 100644 drivers/clk/renesas/r8a7797-cpg-mssr.c create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a7797.c @@ -75,10 +75,10 @@ index 7c104ca..9380fc6 100644 help diff --git a/arch/arm64/boot/dts/renesas/r8a7797.dtsi b/arch/arm64/boot/dts/renesas/r8a7797.dtsi new file mode 100644 -index 0000000..30638e3 +index 0000000..1be93e8 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7797.dtsi -@@ -0,0 +1,973 @@ +@@ -0,0 +1,1005 @@ +/* + * Device Tree Source for the r8a7797 SoC + * @@ -1050,6 +1050,38 @@ index 0000000..30638e3 + power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; + status = "okay"; + }; ++ ++ imrlx4_ch0: imr-lx4@fe860000 { ++ compatible = "renesas,imr-lx4"; ++ reg = <0 0xfe860000 0 0x2000>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 823>; ++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; ++ }; ++ ++ imrlx4_ch1: imr-lx4@fe870000 { ++ compatible = "renesas,imr-lx4"; ++ reg = <0 0xfe870000 0 0x2000>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 822>; ++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; ++ }; ++ ++ imrlx4_ch2: imr-lx4@fe880000 { ++ compatible = "renesas,imr-lx4"; ++ reg = <0 0xfe880000 0 0x2000>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 821>; ++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; ++ }; ++ ++ imrlx4_ch3: imr-lx4@fe890000 { ++ compatible = "renesas,imr-lx4"; ++ reg = <0 0xfe890000 0 0x2000>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 820>; ++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; ++ }; + }; +}; diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig @@ -1078,10 +1110,10 @@ index 1072f76..c6f0abb 100644 obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o clk-div6.o diff --git a/drivers/clk/renesas/r8a7797-cpg-mssr.c b/drivers/clk/renesas/r8a7797-cpg-mssr.c new file mode 100644 -index 0000000..c8e9a3f +index 0000000..29dfe4a --- /dev/null +++ b/drivers/clk/renesas/r8a7797-cpg-mssr.c -@@ -0,0 +1,218 @@ +@@ -0,0 +1,222 @@ +/* + * r8a7797 Clock Pulse Generator / Module Standby and Software Reset + * @@ -1209,6 +1241,10 @@ index 0000000..c8e9a3f + DEF_MOD("vin0", 811, R8A7797_CLK_S2D1), + DEF_MOD("etheravb", 812, R8A7797_CLK_S2D2), + DEF_MOD("isp", 817, R8A7797_CLK_S2D1), /* @@ Unknown Module Clock */ ++ DEF_MOD("imr3", 820, R8A7797_CLK_S2D1), ++ DEF_MOD("imr2", 821, R8A7797_CLK_S2D1), ++ DEF_MOD("imr1", 822, R8A7797_CLK_S2D1), ++ DEF_MOD("imr0", 823, R8A7797_CLK_S2D1), + DEF_MOD("gpio5", 907, R8A7797_CLK_CP), + DEF_MOD("gpio4", 908, R8A7797_CLK_CP), + DEF_MOD("gpio3", 909, R8A7797_CLK_CP), diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch index 1825776..fb75157 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch @@ -10261,14 +10261,14 @@ index 0000000..f71addf + /* device specific region for Lossy Decompression */ + lossy_decompress: linux,lossy_decompress { + no-map; -+ reg = <0x00000000 0x64000000 0x0 0x03000000>; ++ reg = <0x00000000 0x6c000000 0x0 0x03000000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; -+ reg = <0x00000000 0x67000000 0x0 0x09000000>; ++ reg = <0x00000000 0x6f000000 0x0 0x10000000>; + linux,cma-default; + }; + @@ -10276,7 +10276,7 @@ index 0000000..f71addf + linux,multimedia { + compatible = "shared-dma-pool"; + reusable; -+ reg = <0x00000000 0x70000000 0x0 0x10000000>; ++ reg = <0x00000000 0x7f000000 0x0 0x01000000>; + }; + }; + @@ -11917,14 +11917,14 @@ index 0000000..f683ec3 + /* device specific region for Lossy Decompression */ + lossy_decompress: linux,lossy_decompress { + no-map; -+ reg = <0x00000000 0x64000000 0x0 0x03000000>; ++ reg = <0x00000000 0x6c000000 0x0 0x03000000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; -+ reg = <0x00000000 0x67000000 0x0 0x09000000>; ++ reg = <0x00000000 0x6f000000 0x0 0x10000000>; + linux,cma-default; + }; + @@ -11932,7 +11932,7 @@ index 0000000..f683ec3 + linux,multimedia { + compatible = "shared-dma-pool"; + reusable; -+ reg = <0x00000000 0x70000000 0x0 0x10000000>; ++ reg = <0x00000000 0x7f000000 0x0 0x01000000>; + }; + }; + -- cgit 1.2.3-korg From 3943570b206ec95bf37fc31027cb975a49e8e7be Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Tue, 21 Nov 2017 20:15:20 +0300 Subject: V3M View board support --- .../0040-arm64-dts-renesas-add-ADAS-boards.patch | 320 ++++++++++++++++++++- 1 file changed, 314 insertions(+), 6 deletions(-) (limited to 'meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch') diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch index fb75157..b9bcc7e 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch @@ -19,13 +19,14 @@ Videobox board on R8A7795 ES1.x SoC Videobox board on R8A7795 SoC Eagle board on R8A7797 SoC V3MSK board on R8A7797 SoC +V3MSK.View board on R8A7797 SoC Videobox Mini board on R8A7795 ES1.x SoC Videobox Mini board on R8A7795 SoC Videobox Mini board on R8A7797 SoC Signed-off-by: Vladimir Barinov --- - arch/arm64/boot/dts/renesas/Makefile | 18 + + arch/arm64/boot/dts/renesas/Makefile | 19 + arch/arm64/boot/dts/renesas/legacy/Makefile | 8 + .../renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts | 1710 +++++++++++++++++++ .../renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts | 441 +++++ @@ -58,6 +59,7 @@ Signed-off-by: Vladimir Barinov arch/arm64/boot/dts/renesas/r8a7797-eagle.dts | 561 +++++++ arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts | 578 +++++++ arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts | 498 ++++++ + arch/arm64/boot/dts/renesas/r8a7797-v3msk-view.dts | 298 ++++ arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts | 313 ++++ arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi | 518 ++++++ arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi | 30 + @@ -66,7 +68,7 @@ Signed-off-by: Vladimir Barinov arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi | 515 ++++++ arch/arm64/boot/dts/renesas/ulcb-vb.dtsi | 1726 ++++++++++++++++++++ arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi | 557 +++++++ - 41 files changed, 16792 insertions(+) + 42 files changed, 17091 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/legacy/Makefile create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts @@ -99,6 +101,7 @@ Signed-off-by: Vladimir Barinov create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-eagle.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk-view.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi @@ -109,10 +112,10 @@ Signed-off-by: Vladimir Barinov create mode 100644 arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile -index 32fb4d9..26d258d2 100644 +index 32fb4d9..1321e4f 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile -@@ -4,5 +4,23 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb +@@ -4,5 +4,24 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb @@ -128,6 +131,7 @@ index 32fb4d9..26d258d2 100644 +dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-vbm.dtb r8a7795-es1-h3ulcb-vbm.dtb +dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-eagle.dtb +dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk.dtb ++dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk-view.dtb +dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk-kf.dtb +dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk-vbm.dtb + @@ -10215,7 +10219,7 @@ index 0000000..cc6866c +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts b/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts new file mode 100644 -index 0000000..f71addf +index 0000000..eef10af --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts @@ -0,0 +1,561 @@ @@ -11868,9 +11872,313 @@ index 0000000..28a0b92 + }; + }; +}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk-view.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-view.dts +new file mode 100644 +index 0000000..573e2bc +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-view.dts +@@ -0,0 +1,298 @@ ++/* ++ * Device Tree Source for the V3MSK View board on r8a7797 ++ * ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7797-v3msk.dts" ++ ++/ { ++ model = "Renesas V3MSK View board based on r8a7797"; ++}; ++ ++&csi2_40 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&i2c3 { ++ pinctrl-0 = <&i2c3_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ clock-frequency = <400000>; ++ ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; ++ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; ++ ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; ++ }; ++ ++ max9286-max9271@0 { ++ compatible = "maxim,max9286-max9271"; ++ reg = <0x6c>; ++ gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; ++ maxim,sensor_delay = <0>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++}; ++ ++&gpio2 { ++ gpio_pwdn1 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "GPIO_PWDN1#"; ++ }; ++}; ++ ++&pfc { ++ i2c3_pins: i2c3 { ++ groups = "i2c3"; ++ function = "i2c3"; ++ }; ++}; ++ ++&vin0 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin2 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin3 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ }; ++ }; ++}; diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts new file mode 100644 -index 0000000..f683ec3 +index 0000000..efb1576 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts @@ -0,0 +1,313 @@ -- cgit 1.2.3-korg From a741482ab005ed90c717af54d41f4626420224dc Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Sun, 26 Nov 2017 21:50:19 +0300 Subject: LVDS stability update 1) use POC regulators in driver and power cameras one after one 2) set sensors reset during POC channels setup 3) fix wizard setup for ov490 based caemras by waiting it's firmware start all internal apps 4) support AR0132 with MAX9286 5) due to stability fixed then increase i2c bus speed on Videobox Mini 6) support MAX96705 serializer with MAX9286 --- .../linux-renesas/0030-Gen3-LVDS-cameras.patch | 239 ++++++++++---- .../0040-arm64-dts-renesas-add-ADAS-boards.patch | 357 +++++++++++++-------- .../linux/linux-renesas_4.9.bbappend | 1 + 3 files changed, 405 insertions(+), 192 deletions(-) (limited to 'meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch') diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0030-Gen3-LVDS-cameras.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0030-Gen3-LVDS-cameras.patch index aca7198..781e456 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0030-Gen3-LVDS-cameras.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0030-Gen3-LVDS-cameras.patch @@ -11,20 +11,20 @@ Signed-off-by: Vladimir Barinov --- drivers/media/i2c/soc_camera/Kconfig | 47 + drivers/media/i2c/soc_camera/Makefile | 7 + - drivers/media/i2c/soc_camera/ar0132.c | 548 +++++++++++ + drivers/media/i2c/soc_camera/ar0132.c | 581 +++++++++++ drivers/media/i2c/soc_camera/ar0132.h | 213 ++++ - drivers/media/i2c/soc_camera/max9286_max9271.c | 567 +++++++++++ - drivers/media/i2c/soc_camera/max9286_max9271.h | 243 +++++ - drivers/media/i2c/soc_camera/ov10635.c | 759 ++++++++++++++ + drivers/media/i2c/soc_camera/max9286_max9271.c | 607 ++++++++++++ + drivers/media/i2c/soc_camera/max9286_max9271.h | 244 +++++ + drivers/media/i2c/soc_camera/ov10635.c | 758 ++++++++++++++ drivers/media/i2c/soc_camera/ov10635.h | 1139 ++++++++++++++++++++++ drivers/media/i2c/soc_camera/ov10635_debug.h | 54 + drivers/media/i2c/soc_camera/ov106xx.c | 106 ++ - drivers/media/i2c/soc_camera/ov490_ov10640.c | 1046 ++++++++++++++++++++ - drivers/media/i2c/soc_camera/ov490_ov10640.h | 88 ++ + drivers/media/i2c/soc_camera/ov490_ov10640.c | 1064 ++++++++++++++++++++ + drivers/media/i2c/soc_camera/ov490_ov10640.h | 93 ++ drivers/media/i2c/soc_camera/ov495_ov2775.c | 658 +++++++++++++ drivers/media/i2c/soc_camera/ov495_ov2775.h | 23 + - drivers/media/i2c/soc_camera/ti954_ti9x3.c | 417 ++++++++ - drivers/media/i2c/soc_camera/ti964_ti9x3.c | 385 ++++++++ + drivers/media/i2c/soc_camera/ti954_ti9x3.c | 431 ++++++++ + drivers/media/i2c/soc_camera/ti964_ti9x3.c | 399 ++++++++ drivers/media/i2c/soc_camera/ti9x4_ti9x3.h | 153 +++ drivers/media/platform/soc_camera/rcar_csi2.c | 297 ++++-- drivers/media/platform/soc_camera/rcar_vin.c | 174 +++- @@ -32,7 +32,7 @@ Signed-off-by: Vladimir Barinov drivers/media/platform/soc_camera/soc_mediabus.c | 16 + include/media/drv-intf/soc_mediabus.h | 3 + include/media/soc_camera.h | 1 + - 23 files changed, 6852 insertions(+), 109 deletions(-) + 23 files changed, 6976 insertions(+), 109 deletions(-) create mode 100644 drivers/media/i2c/soc_camera/ar0132.c create mode 100644 drivers/media/i2c/soc_camera/ar0132.h create mode 100644 drivers/media/i2c/soc_camera/max9286_max9271.c @@ -129,10 +129,10 @@ index 6f994f9..7d4c1ab 100644 obj-$(CONFIG_SOC_CAMERA_OV6650) += ov6650.o diff --git a/drivers/media/i2c/soc_camera/ar0132.c b/drivers/media/i2c/soc_camera/ar0132.c new file mode 100644 -index 0000000..284c522 +index 0000000..decbf5f --- /dev/null +++ b/drivers/media/i2c/soc_camera/ar0132.c -@@ -0,0 +1,548 @@ +@@ -0,0 +1,581 @@ +/* + * Aptina AR0132 sensor camera driver + * @@ -177,6 +177,8 @@ index 0000000..284c522 + int autogain; + int dvp_order; + /* serializers */ ++ int max9286_addr; ++ int max9271_addr; + int ti964_addr; + int ti954_addr; + int ti9x3_addr; @@ -191,6 +193,19 @@ index 0000000..284c522 + return container_of(i2c_get_clientdata(client), struct ar0132_priv, sd); +} + ++static void ar0132_s_port(struct i2c_client *client, int fwd_en) ++{ ++ struct ar0132_priv *priv = to_ar0132(client); ++ int tmp_addr; ++ ++ if (priv->max9286_addr) { ++ tmp_addr = client->addr; ++ client->addr = priv->max9286_addr; /* Deserializer I2C address */ ++ reg8_write(client, 0x0a, fwd_en ? 0x11 << priv->port : 0); /* Enable/disable reverse/forward control for this port */ ++ client->addr = tmp_addr; ++ }; ++} ++ +static int ar0132_set_regs(struct i2c_client *client, + const struct ar0132_reg *regs, int nr_regs) +{ @@ -456,6 +471,8 @@ index 0000000..284c522 + u16 pid = 0; + int ret = 0; + ++ ar0132_s_port(client, 1); ++ + /* check and show model ID */ + reg16_read16(client, AR0132_PID, &pid); + @@ -479,6 +496,8 @@ index 0000000..284c522 + dev_info(&client->dev, "ar0132 PID %x, res %dx%d, OTP_ID %02x:%02x:%02x:%02x:%02x:%02x\n", + pid, AR0132_MAX_WIDTH, AR0132_MAX_HEIGHT, priv->id[0], priv->id[1], priv->id[2], priv->id[3], priv->id[4], priv->id[5]); +err: ++ ar0132_s_port(client, 0); ++ + return ret; +} + @@ -502,6 +521,11 @@ index 0000000..284c522 + if (!rendpoint) + continue; + ++ if (!of_property_read_u32(rendpoint, "max9271-addr", &priv->max9271_addr) && ++ !of_property_read_u32(rendpoint->parent->parent, "reg", &priv->max9286_addr) && ++ !kstrtouint(strrchr(rendpoint->full_name, '@') + 1, 0, &priv->port)) ++ break; ++ + if (!of_property_read_u32(rendpoint, "ti9x3-addr", &priv->ti9x3_addr) && + !of_property_match_string(rendpoint->parent->parent, "compatible", "ti,ti964-ti9x3") && + !of_property_read_u32(rendpoint->parent->parent, "reg", &priv->ti964_addr) && @@ -515,13 +539,22 @@ index 0000000..284c522 + break; + } + -+ if (!priv->ti964_addr && !priv->ti954_addr) { -+ dev_err(&client->dev, "deserializer does not present\n"); ++ if (!priv->max9286_addr && !priv->ti964_addr && !priv->ti954_addr) { ++ dev_err(&client->dev, "deserializer does not present for AR0132\n"); + return -EINVAL; + } + ++ ar0132_s_port(client, 1); ++ + /* setup I2C translator address */ + tmp_addr = client->addr; ++ if (priv->max9286_addr) { ++ client->addr = priv->max9271_addr; /* Serializer I2C address */ ++ ++ reg8_write(client, 0x09, tmp_addr << 1); /* Sensor translated I2C address */ ++ reg8_write(client, 0x0A, AR0132_I2C_ADDR << 1); /* Sensor native I2C address */ ++ usleep_range(2000, 2500); /* wait 2ms */ ++ }; + if (priv->ti964_addr) { + client->addr = priv->ti964_addr; /* Deserializer I2C address */ + @@ -902,10 +935,10 @@ index 0000000..055841d +}; diff --git a/drivers/media/i2c/soc_camera/max9286_max9271.c b/drivers/media/i2c/soc_camera/max9286_max9271.c new file mode 100644 -index 0000000..9797d24 +index 0000000..91223a0 --- /dev/null +++ b/drivers/media/i2c/soc_camera/max9286_max9271.c -@@ -0,0 +1,567 @@ +@@ -0,0 +1,607 @@ +/* + * MAXIM max9286-max9271 GMSL driver + * @@ -920,9 +953,10 @@ index 0000000..9797d24 +#include +#include +#include ++#include +#include ++#include +#include -+#include + +#include +#include @@ -959,10 +993,12 @@ index 0000000..9797d24 + u32 csi2_outord; + struct i2c_client *client; + int max9271_addr_map[4]; ++ struct regulator *poc_supply[4]; /* PoC power supply */ +}; + +static int force_conf_link; -+ ++static int force_poc_trig; ++#ifndef MODULE +static __init int max9286_max9271_force_conf_link(char *str) +{ + /* force configuration link */ @@ -972,6 +1008,16 @@ index 0000000..9797d24 +} +early_param("force_conf_link", max9286_max9271_force_conf_link); + ++static __init int max9286_max9271_force_poc_trig(char *str) ++{ ++ /* force PoC triggering during reverse channel setup */ ++ /* to be used on systems with dedicated PoC and unstable ser-des lock */ ++ force_poc_trig = 1; ++ return 0; ++} ++early_param("force_poc_trig", max9286_max9271_force_poc_trig); ++#endif ++ +static void max9286_max9271_preinit(struct i2c_client *client, int addr) +{ + client->addr = addr; /* MAX9286-CAMx I2C */ @@ -980,27 +1026,32 @@ index 0000000..9797d24 + usleep_range(2000, 2500); /* wait 2ms after any change of reverse channel settings */ +} + -+static void max9286_max9271_sensor_reset(struct i2c_client *client, int addr) ++static void max9286_max9271_sensor_reset(struct i2c_client *client, int addr, int reset_on) +{ + struct max9286_max9271_priv *priv = i2c_get_clientdata(client); + + if (priv->gpio_resetb < 1 || priv->gpio_resetb > 5) + return; + -+ /* get out from sensor reset */ ++ /* sensor reset/unreset */ + client->addr = addr; /* MAX9271-CAMx I2C */ -+ reg8_write(client, 0x0f, (0xfe & ~BIT(priv->gpio_resetb)) | -+ (priv->active_low_resetb ? 0 : BIT(priv->gpio_resetb))); /* set GPIOn value to reset */ ++ reg8_write(client, 0x0f, (0xfe & ~BIT(priv->gpio_resetb)) | /* set GPIOn value to reset/unreset */ ++ ((priv->active_low_resetb ? BIT(priv->gpio_resetb) : 0) ^ reset_on)); + reg8_write(client, 0x0e, 0x42 | BIT(priv->gpio_resetb)); /* set GPIOn direction output */ -+ usleep_range(2000, 2500); /* wait 2ms */ -+ reg8_write(client, 0x0f, (0xfe & ~BIT(priv->gpio_resetb)) | -+ (priv->active_low_resetb ? BIT(priv->gpio_resetb) : 0)); /* set GPIOn value to un-reset */ -+ usleep_range(2000, 2500); /* wait 2ms */ +} + +static void max9286_max9271_postinit(struct i2c_client *client, int addr) +{ + struct max9286_max9271_priv *priv = i2c_get_clientdata(client); ++ int idx; ++ ++ for (idx = 0; idx < priv->links; idx++) { ++ client->addr = priv->des_addr; /* MAX9286 I2C */ ++ reg8_write(client, 0x0a, 0x11 << idx); /* enable reverse/forward control for CAMx */ ++ ++ client->addr = priv->max9271_addr_map[idx]; /* MAX9271-CAMx I2C */ ++ max9286_max9271_sensor_reset(client, client->addr, 0); /* sensor unreset */ ++ } + + client->addr = addr; /* MAX9286 I2C */ + reg8_write(client, 0x0a, 0x00); /* disable reverse control for all cams */ @@ -1016,6 +1067,7 @@ index 0000000..9797d24 + struct max9286_max9271_priv *priv = i2c_get_clientdata(client); + u8 val = 0; + int timeout = priv->timeout; ++ char timeout_str[10]; + int ret = 0; + + /* Reverse channel enable */ @@ -1033,7 +1085,10 @@ index 0000000..9797d24 + usleep_range(2000, 2500); /* wait 2ms after any change of reverse channel settings */ + + client->addr = 0x40; /* MAX9271-CAMx I2C */ ++ reg8_write(client, 0x04, 0x43); /* wake-up, enable reverse_control/conf_link */ ++ usleep_range(2000, 2500); /* wait 2ms after any change of reverse channel settings */ + reg8_write(client, 0x08, 0x1); /* reverse channel receiver high threshold enable */ ++ reg8_write(client, 0x97, 0x5f); /* enable reverse control channel programming (MAX96705-MAX96711 only) */ + usleep_range(2000, 2500); /* wait 2ms after any change of reverse channel settings */ + + client->addr = priv->des_addr; /* MAX9286-CAMx I2C */ @@ -1041,26 +1096,32 @@ index 0000000..9797d24 + usleep_range(2000, 2500); /* wait 2ms after any change of reverse channel settings */ + + client->addr = 0x40; /* MAX9271-CAMx I2C */ -+ reg8_write(client, 0x04, 0x43); /* wake-up, enable reverse_control/conf_link */ -+ usleep_range(2000, 2500); /* wait 2ms after any change of reverse channel settings */ -+ -+ client->addr = 0x40; /* MAX9271-CAMx I2C */ + reg8_read(client, 0x1e, &val); /* read max9271 ID */ -+ if (val == MAX9271_ID || --timeout == 0) ++ if (val == MAX9271_ID || val == MAX96705_ID || --timeout == 0) + break; + + /* Check if already initialized (after reboot/reset ?) */ + client->addr = priv->max9271_addr_map[idx]; /* MAX9271-CAMx I2C */ + reg8_read(client, 0x1e, &val); /* read max9271 ID */ -+ if (val == MAX9271_ID) { ++ if (val == MAX9271_ID || val == MAX96705_ID) { + reg8_write(client, 0x04, 0x43); /* enable reverse_control/conf_link */ + usleep_range(2000, 2500); /* wait 2ms after any change of reverse channel settings */ + ret = -EADDRINUSE; + break; + } ++ ++ if (timeout == priv->timeout / 2 && force_poc_trig) { ++ if (!IS_ERR(priv->poc_supply[idx])) { ++ if (regulator_disable(priv->poc_supply[idx])) ++ dev_err(&client->dev, "fail to disable POC%d regulator\n", idx); ++ mdelay(200); ++ if (regulator_enable(priv->poc_supply[idx])) ++ dev_err(&client->dev, "fail to enable POC%d regulator\n", idx); ++ } ++ } + } + -+ max9286_max9271_sensor_reset(client, client->addr); /* sensor reset */ ++ max9286_max9271_sensor_reset(client, client->addr, 1); /* sensor reset */ + + if (!timeout) { + ret = -ETIMEDOUT; @@ -1072,9 +1133,11 @@ index 0000000..9797d24 + priv->csi2_outord |= ((hweight8(priv->links_mask) - 1) << (idx * 2)); + +out: -+ dev_info(&client->dev, "link%d MAX9271 %sat 0x%x %s\n", idx, ++ sprintf(timeout_str, "retries=%d", priv->timeout - timeout); ++ dev_info(&client->dev, "link%d MAX9271 %sat 0x%x %s %s\n", idx, + ret == -EADDRINUSE ? "already " : "", priv->max9271_addr_map[idx], -+ ret == -ETIMEDOUT ? "not found: timeout GMSL link establish" : ""); ++ ret == -ETIMEDOUT ? "not found: timeout GMSL link establish" : "", ++ priv->timeout - timeout? timeout_str : ""); + + return ret; +} @@ -1176,6 +1239,11 @@ index 0000000..9797d24 + max9286_max9271_initial_setup(client); + + for (idx = 0; idx < priv->links; idx++) { ++ if (!IS_ERR(priv->poc_supply[idx])) { ++ if (regulator_enable(priv->poc_supply[idx])) ++ dev_err(&client->dev, "fail to enable POC%d regulator\n", idx); ++ } ++ + ret = max9286_max9271_reverse_channel_setup(client, idx); + if (ret) + continue; @@ -1391,6 +1459,7 @@ index 0000000..9797d24 +{ + struct max9286_max9271_priv *priv; + int err, i; ++ char supply_name[10]; + + priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) @@ -1406,6 +1475,11 @@ index 0000000..9797d24 + if (err) + goto out; + ++ for (i = 0; i < 4; i++) { ++ sprintf(supply_name, "POC%d", i); ++ priv->poc_supply[i] = devm_regulator_get_optional(&client->dev, supply_name); ++ } ++ + err = max9286_max9271_initialize(client); + if (err < 0) + goto out; @@ -1428,7 +1502,6 @@ index 0000000..9797d24 + if (err < 0) + goto out; + } -+ +out: + return err; +} @@ -1475,10 +1548,10 @@ index 0000000..9797d24 +MODULE_LICENSE("GPL"); diff --git a/drivers/media/i2c/soc_camera/max9286_max9271.h b/drivers/media/i2c/soc_camera/max9286_max9271.h new file mode 100644 -index 0000000..0016f28a +index 0000000..6c2a9e0 --- /dev/null +++ b/drivers/media/i2c/soc_camera/max9286_max9271.h -@@ -0,0 +1,243 @@ +@@ -0,0 +1,244 @@ +/* + * MAXIM max9286-max9271 GMSL driver include file + * @@ -1504,6 +1577,7 @@ index 0000000..0016f28a +#define REG8_NUM_RETRIES 1 /* number of read/write retries */ +#define REG16_NUM_RETRIES 10 /* number of read/write retries */ +#define MAX9271_ID 0x9 ++#define MAX96705_ID 0x41 +#define MAX9286_ID 0x40 +#define BROADCAST 0x6f + @@ -1724,10 +1798,10 @@ index 0000000..0016f28a +#endif /* _MAX9286_MAX9271_H */ diff --git a/drivers/media/i2c/soc_camera/ov10635.c b/drivers/media/i2c/soc_camera/ov10635.c new file mode 100644 -index 0000000..45169de +index 0000000..6296647 --- /dev/null +++ b/drivers/media/i2c/soc_camera/ov10635.c -@@ -0,0 +1,759 @@ +@@ -0,0 +1,758 @@ +/* + * OmniVision ov10635 sensor camera driver + * @@ -1798,7 +1872,7 @@ index 0000000..45169de + + if (priv->max9286_addr) { + tmp_addr = client->addr; -+ client->addr = priv->max9286_addr; /* Deserializer I2C address */ ++ client->addr = priv->max9286_addr; /* Deserializer I2C address */ + reg8_write(client, 0x0a, fwd_en ? 0x11 << priv->port : 0); /* Enable/disable reverse/forward control for this port */ + client->addr = tmp_addr; + }; @@ -2265,7 +2339,6 @@ index 0000000..45169de + + dev_info(&client->dev, "ov10635 Product ID %x Manufacturer ID %x OTP_ID %02x:%02x:%02x:%02x:%02x:%02x\n", + pid, ver, priv->id[0], priv->id[1], priv->id[2], priv->id[3], priv->id[4], priv->id[5]); -+ +out: + ov10635_s_port(client, 0); + @@ -2311,7 +2384,7 @@ index 0000000..45169de + } + + if (!priv->max9286_addr && !priv->ti964_addr && !priv->ti954_addr) { -+ dev_err(&client->dev, "deserializer does not present\n"); ++ dev_err(&client->dev, "deserializer does not present for OV10635\n"); + return -EINVAL; + } + @@ -2489,7 +2562,7 @@ index 0000000..45169de +#endif diff --git a/drivers/media/i2c/soc_camera/ov10635.h b/drivers/media/i2c/soc_camera/ov10635.h new file mode 100644 -index 0000000..66cc490 +index 0000000..a0e510d --- /dev/null +++ b/drivers/media/i2c/soc_camera/ov10635.h @@ -0,0 +1,1139 @@ @@ -3806,10 +3879,10 @@ index 0000000..f2bb706 +MODULE_LICENSE("GPL"); diff --git a/drivers/media/i2c/soc_camera/ov490_ov10640.c b/drivers/media/i2c/soc_camera/ov490_ov10640.c new file mode 100644 -index 0000000..15acc51 +index 0000000..bee9293 --- /dev/null +++ b/drivers/media/i2c/soc_camera/ov490_ov10640.c -@@ -0,0 +1,1046 @@ +@@ -0,0 +1,1064 @@ +/* + * OmniVision ov490-ov10640 sensor camera driver + * @@ -4553,10 +4626,28 @@ index 0000000..15acc51 + reg16_write(client, 0xFFFD, 0x80); + reg16_write(client, 0xFFFE, 0x29); + usleep_range(100, 150); /* wait 100 us */ -+ timeout = 300; -+ for (;;) { ++ for (timeout = 300; timeout > 0; timeout--) { + reg16_read(client, 0xd000, &val); -+ if (val == 0x0c || --timeout == 0) ++ if (val == 0x0c) ++ break; ++ mdelay(1); ++ } ++ ++ /* wait firmware apps started by reading OV10640 ID */ ++ for (;timeout > 0; timeout--) { ++ reg16_write(client, 0xFFFD, 0x80); ++ reg16_write(client, 0xFFFE, 0x19); ++ usleep_range(100, 150); /* wait 100 us */ ++ reg16_write(client, 0x5000, 0x01); ++ reg16_write(client, 0x5001, 0x30); ++ reg16_write(client, 0x5002, 0x0a); ++ reg16_write(client, 0xFFFE, 0x80); ++ usleep_range(100, 150); /* wait 100 us */ ++ reg16_write(client, 0xC0, 0xc1); ++ reg16_write(client, 0xFFFE, 0x19); ++ usleep_range(1000, 1500); /* wait 1 ms */ ++ reg16_read(client, 0x5000, &val); ++ if (val == 0xa6) + break; + mdelay(1); + } @@ -4658,7 +4749,7 @@ index 0000000..15acc51 + } + + if (!priv->max9286_addr && !priv->ti964_addr && !priv->ti954_addr) { -+ dev_err(&client->dev, "deserializer does not present\n"); ++ dev_err(&client->dev, "deserializer does not present for OV490\n"); + return -EINVAL; + } + @@ -4858,7 +4949,7 @@ index 0000000..15acc51 +#endif diff --git a/drivers/media/i2c/soc_camera/ov490_ov10640.h b/drivers/media/i2c/soc_camera/ov490_ov10640.h new file mode 100644 -index 0000000..d3290c7 +index 0000000..8c9ecf1 --- /dev/null +++ b/drivers/media/i2c/soc_camera/ov490_ov10640.h @@ -0,0 +1,93 @@ @@ -4957,7 +5048,7 @@ index 0000000..d3290c7 +}; diff --git a/drivers/media/i2c/soc_camera/ov495_ov2775.c b/drivers/media/i2c/soc_camera/ov495_ov2775.c new file mode 100644 -index 0000000..881615e +index 0000000..6dc0675 --- /dev/null +++ b/drivers/media/i2c/soc_camera/ov495_ov2775.c @@ -0,0 +1,658 @@ @@ -5447,7 +5538,7 @@ index 0000000..881615e + } + + if (!priv->ti960_addr && !priv->ti954_addr) { -+ dev_err(&client->dev, "deserializer does not present\n"); ++ dev_err(&client->dev, "deserializer does not present for OV495\n"); + return -EINVAL; + } + @@ -5650,10 +5741,10 @@ index 0000000..3f53689 +}; diff --git a/drivers/media/i2c/soc_camera/ti954_ti9x3.c b/drivers/media/i2c/soc_camera/ti954_ti9x3.c new file mode 100644 -index 0000000..fc7ccda +index 0000000..1672173 --- /dev/null +++ b/drivers/media/i2c/soc_camera/ti954_ti9x3.c -@@ -0,0 +1,417 @@ +@@ -0,0 +1,431 @@ +/* + * TI ti954-(ti913/ti953) FPDLinkIII driver + * @@ -5668,9 +5759,10 @@ index 0000000..fc7ccda +#include +#include +#include ++#include +#include ++#include +#include -+#include + +#include +#include @@ -5692,6 +5784,7 @@ index 0000000..fc7ccda + struct i2c_client *client; + int ti9x3_addr_map[4]; + char chip_id[6]; ++ struct regulator *poc_supply[4]; /* PoC power supply */ + int xtal_gpio; +}; + @@ -5824,8 +5917,14 @@ index 0000000..fc7ccda + + ti954_ti9x3_initial_setup(client); + -+ for (idx = 0; idx < priv->links; idx++) ++ for (idx = 0; idx < priv->links; idx++) { ++ if (!IS_ERR(priv->poc_supply[idx])) { ++ if (regulator_enable(priv->poc_supply[idx])) ++ dev_err(&client->dev, "fail to enable POC%d regulator\n", idx); ++ } ++ + ti954_ti9x3_fpdlink3_setup(client, idx); ++ } + + client->addr = priv->des_addr; + @@ -5992,6 +6091,7 @@ index 0000000..fc7ccda +{ + struct ti954_ti9x3_priv *priv; + int err, i; ++ char supply_name[10]; + + priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) @@ -6006,6 +6106,11 @@ index 0000000..fc7ccda + if (err) + goto out; + ++ for (i = 0; i < 4; i++) { ++ sprintf(supply_name, "POC%d", i); ++ priv->poc_supply[i] = devm_regulator_get_optional(&client->dev, supply_name); ++ } ++ + err = ti954_ti9x3_initialize(client); + if (err < 0) + goto out; @@ -6073,10 +6178,10 @@ index 0000000..fc7ccda +MODULE_LICENSE("GPL"); diff --git a/drivers/media/i2c/soc_camera/ti964_ti9x3.c b/drivers/media/i2c/soc_camera/ti964_ti9x3.c new file mode 100644 -index 0000000..8dd0f99 +index 0000000..770d306 --- /dev/null +++ b/drivers/media/i2c/soc_camera/ti964_ti9x3.c -@@ -0,0 +1,385 @@ +@@ -0,0 +1,399 @@ +/* + * TI (ti964/ti960)-(ti913/ti953) FPDLinkIII driver + * @@ -6091,9 +6196,10 @@ index 0000000..8dd0f99 +#include +#include +#include ++#include +#include ++#include +#include -+#include + +#include +#include @@ -6115,6 +6221,7 @@ index 0000000..8dd0f99 + struct i2c_client *client; + int ti9x3_addr_map[4]; + char chip_id[6]; ++ struct regulator *poc_supply[4]; /* PoC power supply */ +}; + +static void ti964_ti9x3_read_chipid(struct i2c_client *client) @@ -6220,8 +6327,14 @@ index 0000000..8dd0f99 + + ti964_ti9x3_initial_setup(client); + -+ for (idx = 0; idx < priv->links; idx++) ++ for (idx = 0; idx < priv->links; idx++) { ++ if (!IS_ERR(priv->poc_supply[idx])) { ++ if (regulator_enable(priv->poc_supply[idx])) ++ dev_err(&client->dev, "fail to enable POC%d regulator\n", idx); ++ } ++ + ti964_ti9x3_fpdlink3_setup(client, idx); ++ } + + client->addr = priv->des_addr; + @@ -6383,6 +6496,7 @@ index 0000000..8dd0f99 +{ + struct ti964_ti9x3_priv *priv; + int err, i; ++ char supply_name[10]; + + priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) @@ -6397,6 +6511,11 @@ index 0000000..8dd0f99 + if (err) + goto out; + ++ for (i = 0; i < 4; i++) { ++ sprintf(supply_name, "POC%d", i); ++ priv->poc_supply[i] = devm_regulator_get_optional(&client->dev, supply_name); ++ } ++ + err = ti964_ti9x3_initialize(client); + if (err < 0) + goto out; diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch index b9bcc7e..20adbaf 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch @@ -56,19 +56,19 @@ Signed-off-by: Vladimir Barinov arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts | 40 + .../arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts | 287 ++++ .../boot/dts/renesas/r8a7796-salvator-x-view.dts | 318 ++++ - arch/arm64/boot/dts/renesas/r8a7797-eagle.dts | 561 +++++++ + arch/arm64/boot/dts/renesas/r8a7797-eagle.dts | 560 +++++++ arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts | 578 +++++++ - arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts | 498 ++++++ + arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts | 518 ++++++ arch/arm64/boot/dts/renesas/r8a7797-v3msk-view.dts | 298 ++++ - arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts | 313 ++++ - arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi | 518 ++++++ + arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts | 314 ++++ + arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi | 545 ++++++ arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi | 30 + arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi | 46 + - arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 1529 +++++++++++++++++ + arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 1554 ++++++++++++++++++ arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi | 515 ++++++ arch/arm64/boot/dts/renesas/ulcb-vb.dtsi | 1726 ++++++++++++++++++++ - arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi | 557 +++++++ - 42 files changed, 17091 insertions(+) + arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi | 578 +++++++ + 42 files changed, 17184 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/legacy/Makefile create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts @@ -10219,10 +10219,10 @@ index 0000000..cc6866c +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts b/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts new file mode 100644 -index 0000000..eef10af +index 0000000..3fb3bf1 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts -@@ -0,0 +1,561 @@ +@@ -0,0 +1,560 @@ +/* + * Device Tree Source for the Eagle board + * @@ -10783,7 +10783,6 @@ index 0000000..eef10af + }; + }; +}; -+ diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts new file mode 100644 index 0000000..979cebe @@ -11370,10 +11369,10 @@ index 0000000..979cebe +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts new file mode 100644 -index 0000000..28a0b92 +index 0000000..4292b7b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts -@@ -0,0 +1,498 @@ +@@ -0,0 +1,518 @@ +/* + * Device Tree Source for the V3MSK Videobox Mini board on r8a7797 + * @@ -11392,6 +11391,42 @@ index 0000000..28a0b92 + aliases { + serial1 = &scif3; + }; ++ ++ pwr0: regulator-pwr0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "PWR0"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ gpio = <&gpio_exp_6c 8 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ pwr1: regulator-pwr1 { ++ compatible = "regulator-fixed"; ++ regulator-name = "PWR1"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ gpio = <&gpio_exp_6c 9 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ pwr2: regulator-pwr2 { ++ compatible = "regulator-fixed"; ++ regulator-name = "PWR2"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ gpio = <&gpio_exp_6c 10 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ pwr3: regulator-pwr3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "PWR3"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ gpio = <&gpio_exp_6c 11 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; +}; + +&canfd { @@ -11447,7 +11482,7 @@ index 0000000..28a0b92 + pinctrl-names = "default"; + status = "okay"; + -+ clock-frequency = <100000>; ++ clock-frequency = <400000>; + + i2cswitch1: i2c-switch@74 { + compatible = "nxp,pca9548"; @@ -11554,6 +11589,10 @@ index 0000000..28a0b92 + maxim,resetb-gpio = <1>; + maxim,fsync-mode = "automatic"; + maxim,timeout = <100>; ++ POC0-supply = <&pwr0>; ++ POC1-supply = <&pwr1>; ++ POC2-supply = <&pwr2>; ++ POC3-supply = <&pwr3>; + + port@0 { + max9286_des0ep0: endpoint@0 { @@ -11593,6 +11632,10 @@ index 0000000..28a0b92 + ti,lanes = <4>; + ti,forwarding-mode = "round-robin"; + ti,cable-mode = "coax"; ++ POC0-supply = <&pwr0>; ++ POC1-supply = <&pwr1>; ++ POC2-supply = <&pwr2>; ++ POC3-supply = <&pwr3>; + + port@0 { + ti964_des0ep0: endpoint@0 { @@ -11640,55 +11683,31 @@ index 0000000..28a0b92 + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + input; -+ line-name = "Video VIRQ"; ++ line-name = "VIRQ"; + }; + des_cfg { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + input; -+ line-name = "Video CNFG0"; ++ line-name = "CNFG0"; + }; + pwr_shdn { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-high; -+ line-name = "Video PWR_SHDN"; -+ }; -+ cam_pwr0 { -+ gpio-hog; -+ gpios = <8 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video PWR0"; -+ }; -+ cam_pwr1 { -+ gpio-hog; -+ gpios = <9 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video PWR1"; -+ }; -+ cam_pwr2 { -+ gpio-hog; -+ gpios = <10 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video PWR2"; -+ }; -+ cam_pwr3 { -+ gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video PWR3"; ++ line-name = "PWR_SHDN"; + }; + des_shdn { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-high; -+ line-name = "Video DES_SHDN"; ++ line-name = "Des_SHDN"; + }; + fpdl_shdn { + gpio-hog; + gpios = <15 GPIO_ACTIVE_HIGH>; + output-high; -+ line-name = "Video FPDL_SHDN"; ++ line-name = "FPDL_SHDN"; + }; + }; + }; @@ -12178,10 +12197,10 @@ index 0000000..573e2bc +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts new file mode 100644 -index 0000000..efb1576 +index 0000000..91d10c5 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts -@@ -0,0 +1,313 @@ +@@ -0,0 +1,314 @@ +/* + * Device Tree Source for the V3M Starter Kit board on r8a7797 + * @@ -12354,6 +12373,7 @@ index 0000000..efb1576 + port@0 { + endpoint { + remote-endpoint = <&adv7511_in>; ++// remote-endpoint = <&lvds_in>; + }; + }; + }; @@ -12497,10 +12517,10 @@ index 0000000..efb1576 +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi new file mode 100644 -index 0000000..4ca502f +index 0000000..589a774 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi -@@ -0,0 +1,518 @@ +@@ -0,0 +1,545 @@ +/* + * Device Tree Source for the H3ULCB Kingfisher board: + * this adding conflicting resource on VIN4/VIN5/VIN6/VIN7 for CN11 @@ -12514,6 +12534,44 @@ index 0000000..4ca502f + * kind, whether express or implied. + */ + ++/ { ++ pwr0B: regulator-pwr0B { ++ compatible = "regulator-fixed"; ++ regulator-name = "PWR0B"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ gpio = <&gpio_exp_b_5c 8 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ pwr1B: regulator-pwr1B { ++ compatible = "regulator-fixed"; ++ regulator-name = "PWR1B"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ gpio = <&gpio_exp_b_5c 9 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ pwr2B: regulator-pwr2B { ++ compatible = "regulator-fixed"; ++ regulator-name = "PWR2B"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ gpio = <&gpio_exp_b_5c 10 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ pwr3B: regulator-pwr3B { ++ compatible = "regulator-fixed"; ++ regulator-name = "PWR3B"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ gpio = <&gpio_exp_b_5c 11 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++}; ++ +&i2cswitch4 { + i2c@2 { + #address-cells = <1>; @@ -12618,6 +12676,10 @@ index 0000000..4ca502f + ti,lanes = <4>; + ti,forwarding-mode = "round-robin"; + ti,cable-mode = "coax"; ++ POC0-supply = <&pwr0B>; ++ POC1-supply = <&pwr1B>; ++ POC2-supply = <&pwr2B>; ++ POC3-supply = <&pwr3B>; + + port@0 { + ti964_des1ep0: endpoint@0 { @@ -12659,6 +12721,10 @@ index 0000000..4ca502f + ti,lanes = <4>; + ti,forwarding-mode = "round-robin"; + ti,cable-mode = "coax"; ++ POC0-supply = <&pwr0B>; ++ POC1-supply = <&pwr1B>; ++ POC2-supply = <&pwr2B>; ++ POC3-supply = <&pwr3B>; + + port@0 { + ti954_des1ep0: endpoint@0 { @@ -12690,6 +12756,10 @@ index 0000000..4ca502f + maxim,resetb-gpio = <1>; + maxim,fsync-mode = "automatic"; + maxim,timeout = <100>; ++ POC0-supply = <&pwr0B>; ++ POC1-supply = <&pwr1B>; ++ POC2-supply = <&pwr2B>; ++ POC3-supply = <&pwr3B>; + + port@0 { + max9286_des1ep0: endpoint@0 { @@ -12728,7 +12798,8 @@ index 0000000..4ca502f + reg = <6>; + /* Slot B (CN11) */ + -+ video_b_ext0: pca9535@27 { ++ /* PCA9535 is a redundand/deprecated card */ ++ gpio_exp_b_27: gpio@27 { + compatible = "nxp,pca9535"; + reg = <0x27>; + gpio-controller; @@ -12790,7 +12861,7 @@ index 0000000..4ca502f + }; + }; + -+ video_b_ext1: max7325@5c { ++ gpio_exp_b_5c: gpio@5c { + compatible = "maxim,max7325"; + reg = <0x5c>; + gpio-controller; @@ -12820,30 +12891,6 @@ index 0000000..4ca502f + output-high; + line-name = "Video-B PWR_SHDN"; + }; -+ video_b_cam_pwr0 { -+ gpio-hog; -+ gpios = <8 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR0"; -+ }; -+ video_b_cam_pwr1 { -+ gpio-hog; -+ gpios = <9 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR1"; -+ }; -+ video_b_cam_pwr2 { -+ gpio-hog; -+ gpios = <10 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR2"; -+ }; -+ video_b_cam_pwr3 { -+ gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-B PWR3"; -+ }; + video_b_des_shdn { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; @@ -13109,10 +13156,10 @@ index 0000000..b854216 +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi new file mode 100644 -index 0000000..8ffafb2 +index 0000000..917dbab --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi -@@ -0,0 +1,1529 @@ +@@ -0,0 +1,1554 @@ +/* + * Device Tree Source for the ULCB Kingfisher board + * @@ -13232,6 +13279,42 @@ index 0000000..8ffafb2 + enable-active-high; + }; + ++ pwr0A: regulator-pwr0A { ++ compatible = "regulator-fixed"; ++ regulator-name = "PWR0A"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ gpio = <&gpio_exp_a_5c 8 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ pwr1A: regulator-pwr1A { ++ compatible = "regulator-fixed"; ++ regulator-name = "PWR1A"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ gpio = <&gpio_exp_a_5c 9 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ pwr2A: regulator-pwr2A { ++ compatible = "regulator-fixed"; ++ regulator-name = "PWR2A"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ gpio = <&gpio_exp_a_5c 10 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ pwr3A: regulator-pwr3A { ++ compatible = "regulator-fixed"; ++ regulator-name = "PWR3A"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ gpio = <&gpio_exp_a_5c 11 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ + kim { + compatible = "kim"; + shutdown-gpios = <&gpio_ext_74 3 GPIO_ACTIVE_HIGH>; @@ -13987,6 +14070,10 @@ index 0000000..8ffafb2 + ti,lanes = <4>; + ti,forwarding-mode = "round-robin"; + ti,cable-mode = "coax"; ++ POC0-supply = <&pwr0A>; ++ POC1-supply = <&pwr1A>; ++ POC2-supply = <&pwr2A>; ++ POC3-supply = <&pwr3A>; + + port@0 { + ti964_des0ep0: endpoint@0 { @@ -14028,6 +14115,10 @@ index 0000000..8ffafb2 + ti,lanes = <4>; + ti,forwarding-mode = "round-robin"; + ti,cable-mode = "coax"; ++ POC0-supply = <&pwr0A>; ++ POC1-supply = <&pwr1A>; ++ POC2-supply = <&pwr2A>; ++ POC3-supply = <&pwr3A>; + + port@0 { + ti954_des0ep0: endpoint@0 { @@ -14059,6 +14150,10 @@ index 0000000..8ffafb2 + maxim,resetb-gpio = <1>; + maxim,fsync-mode = "automatic"; + maxim,timeout = <100>; ++ POC0-supply = <&pwr0A>; ++ POC1-supply = <&pwr1A>; ++ POC2-supply = <&pwr2A>; ++ POC3-supply = <&pwr3A>; + + port@0 { + max9286_des0ep0: endpoint@0 { @@ -14142,7 +14237,8 @@ index 0000000..8ffafb2 + reg = <7>; + /* Slot A (CN10) */ + -+ video_a_ext0: pca9535@26 { ++ /* PCA9535 is a redundant/deprecated card */ ++ gpio_exp_a_26: gpio@26 { + compatible = "nxp,pca9535"; + reg = <0x26>; + gpio-controller; @@ -14204,7 +14300,7 @@ index 0000000..8ffafb2 + }; + }; + -+ video_a_ext1: max7325@5c { ++ gpio_exp_a_5c: gpio@5c { + compatible = "maxim,max7325"; + reg = <0x5c>; + gpio-controller; @@ -14234,30 +14330,6 @@ index 0000000..8ffafb2 + output-high; + line-name = "Video-A PWR_SHDN"; + }; -+ video_a_cam_pwr0 { -+ gpio-hog; -+ gpios = <8 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR0"; -+ }; -+ video_a_cam_pwr1 { -+ gpio-hog; -+ gpios = <9 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR1"; -+ }; -+ video_a_cam_pwr2 { -+ gpio-hog; -+ gpios = <10 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR2"; -+ }; -+ video_a_cam_pwr3 { -+ gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video-A PWR3"; -+ }; + video_a_des_shdn { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; @@ -16897,10 +16969,10 @@ index 0000000..193153e +//#include "ulcb-vb-cn12.dtsi" diff --git a/arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi b/arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi new file mode 100644 -index 0000000..3d4bcde +index 0000000..beb52e9 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi -@@ -0,0 +1,557 @@ +@@ -0,0 +1,578 @@ +/* + * Device Tree Source for the ULCB Videobox Mini board + * @@ -16916,6 +16988,42 @@ index 0000000..3d4bcde + serial1 = &scif1; + }; + ++ pwr0: regulator-pwr0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "PWR0"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ gpio = <&gpio_exp_6c 8 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ pwr1: regulator-pwr1 { ++ compatible = "regulator-fixed"; ++ regulator-name = "PWR1"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ gpio = <&gpio_exp_6c 9 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ pwr2: regulator-pwr2 { ++ compatible = "regulator-fixed"; ++ regulator-name = "PWR2"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ gpio = <&gpio_exp_6c 10 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ pwr3: regulator-pwr3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "PWR3"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ gpio = <&gpio_exp_6c 11 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ + lvds-encoder { + compatible = "thine,thc63lvdm83d"; + @@ -17030,7 +17138,7 @@ index 0000000..3d4bcde + pinctrl-names = "default"; + status = "okay"; + -+ clock-frequency = <100000>; ++ clock-frequency = <400000>; + + i2cswitch1: i2c-switch@74 { + compatible = "nxp,pca9548"; @@ -17137,6 +17245,10 @@ index 0000000..3d4bcde + maxim,resetb-gpio = <1>; + maxim,fsync-mode = "automatic"; + maxim,timeout = <100>; ++ POC0-supply = <&pwr0>; ++ POC1-supply = <&pwr1>; ++ POC2-supply = <&pwr2>; ++ POC3-supply = <&pwr3>; + + port@0 { + max9286_des0ep0: endpoint@0 { @@ -17176,6 +17288,10 @@ index 0000000..3d4bcde + ti,lanes = <4>; + ti,forwarding-mode = "round-robin"; + ti,cable-mode = "coax"; ++ POC0-supply = <&pwr0>; ++ POC1-supply = <&pwr1>; ++ POC2-supply = <&pwr2>; ++ POC3-supply = <&pwr3>; + + port@0 { + ti964_des0ep0: endpoint@0 { @@ -17223,55 +17339,31 @@ index 0000000..3d4bcde + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + input; -+ line-name = "Video VIRQ"; ++ line-name = "VIRQ"; + }; + des_cfg { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + input; -+ line-name = "Video CNFG0"; ++ line-name = "CNFG0"; + }; + pwr_shdn { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-high; -+ line-name = "Video PWR_SHDN"; -+ }; -+ cam_pwr0 { -+ gpio-hog; -+ gpios = <8 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video PWR0"; -+ }; -+ cam_pwr1 { -+ gpio-hog; -+ gpios = <9 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video PWR1"; -+ }; -+ cam_pwr2 { -+ gpio-hog; -+ gpios = <10 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video PWR2"; -+ }; -+ cam_pwr3 { -+ gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "Video PWR3"; ++ line-name = "PWR_SHDN"; + }; + des_shdn { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-high; -+ line-name = "Video DES_SHDN"; ++ line-name = "Des_SHDN"; + }; + fpdl_shdn { + gpio-hog; + gpios = <15 GPIO_ACTIVE_HIGH>; + output-high; -+ line-name = "Video FPDL_SHDN"; ++ line-name = "FPDL_SHDN"; + }; + }; + }; @@ -17458,6 +17550,7 @@ index 0000000..3d4bcde + }; + }; +}; ++ -- 1.9.1 diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend index bb658d1..c1b71e7 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend @@ -39,6 +39,7 @@ SRC_URI_append = " \ file://0032-media-i2c-Add-ov5642-sensor.patch \ file://0033-media-soc-camera-fix-parallel-i-f-in-VIN.patch \ file://0034-media-soc_camera-Fix-VIDIOC_S_SELECTION-ioctl-miscal.patch \ + file://0035-regulator-fixed-probe-after-i2c.patch \ file://0040-arm64-dts-renesas-add-ADAS-boards.patch \ file://0041-arm64-dts-renesas-ulcb-enlarge-cma-region.patch \ file://0042-arm64-dts-renesas-r8a7795-es1-h3ulcb-disable-eMMC.patch \ -- cgit 1.2.3-korg From 0b40877700a3fbd9d10e6eeb23d5e4c6759721e1 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Tue, 5 Dec 2017 00:28:48 +0300 Subject: Release ADAS boards in BSP2.23.1 --- ...m-renesas-Add-Renesas-R8A7797-SoC-support.patch | 95 ++++----- .../0015-board-renesas-Add-V3M-Eagle-board.patch | 32 +-- .../0017-board-renesas-Add-V3MSK-board.patch | 6 +- ...as-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch | 236 +++++++++------------ .../0040-arm64-dts-renesas-add-ADAS-boards.patch | 6 +- .../0079-ASoC-fix-pcm-creation-regression.patch | 173 --------------- ...ngine-rcar-dmac-use-TCRB-instead-of-TCR-f.patch | 29 +++ .../linux-renesas/0100-LVDS-ar0132-use-raw12.patch | 2 +- .../linux/linux-renesas_4.9.bbappend | 2 +- 9 files changed, 199 insertions(+), 382 deletions(-) delete mode 100644 meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0079-ASoC-fix-pcm-creation-regression.patch create mode 100644 meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0079-Revert-dmaengine-rcar-dmac-use-TCRB-instead-of-TCR-f.patch (limited to 'meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch') diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch index 9033114..8545634 100644 --- a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch @@ -8,12 +8,12 @@ This adds Renesas R8A7797 SoC support Signed-off-by: Vladimir Barinov --- arch/arm/cpu/armv8/Kconfig | 3 + - arch/arm/cpu/armv8/rcar_gen3/Makefile | 2 + + arch/arm/cpu/armv8/rcar_gen3/Makefile | 3 + arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7797.c | 39 + arch/arm/cpu/armv8/rcar_gen3/cpu_info.c | 8 + - arch/arm/cpu/armv8/rcar_gen3/pfc.c | 2 + arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7797.c | 2764 ++++++++++++++++++++ - arch/arm/cpu/armv8/rcar_gen3/prr_depend.c | 29 + + arch/arm/cpu/armv8/rcar_gen3/pfc.c | 2 + + arch/arm/cpu/armv8/rcar_gen3/prr_depend.c | 27 + arch/arm/include/asm/arch-rcar_gen3/gpio.h | 4 + arch/arm/include/asm/arch-rcar_gen3/r8a7797-gpio.h | 456 ++++ arch/arm/include/asm/arch-rcar_gen3/r8a7797.h | 33 + @@ -21,19 +21,19 @@ Signed-off-by: Vladimir Barinov arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h | 2 + drivers/serial/serial_sh.h | 3 +- include/configs/rcar-gen3-common.h | 12 + - 14 files changed, 3361 insertions(+), 1 deletion(-) + 14 files changed, 3360 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7797.c create mode 100644 arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7797.c create mode 100644 arch/arm/include/asm/arch-rcar_gen3/r8a7797-gpio.h create mode 100644 arch/arm/include/asm/arch-rcar_gen3/r8a7797.h diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig -index 415a9ee..36b7983 100644 +index 01646e9..dfd9bab 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig -@@ -27,6 +27,9 @@ config R8A7795 - config R8A7796 - bool "Renesas SoC R8A7796" +@@ -35,6 +35,9 @@ config R8A77965 + bool "Renesas SoC R8A77965" + select R8A7796X +config R8A7797 + bool "Renesas SoC R8A7797" @@ -42,11 +42,11 @@ index 415a9ee..36b7983 100644 config SYS_SOC diff --git a/arch/arm/cpu/armv8/rcar_gen3/Makefile b/arch/arm/cpu/armv8/rcar_gen3/Makefile -index 2bf2416..e85ca94 100644 +index 01ecaa1..a7a8f79 100644 --- a/arch/arm/cpu/armv8/rcar_gen3/Makefile +++ b/arch/arm/cpu/armv8/rcar_gen3/Makefile -@@ -13,3 +13,6 @@ obj-$(CONFIG_R8A7795) += lowlevel_init.o cpu_info-r8a7795.o \ - obj-$(CONFIG_R8A7796) += lowlevel_init.o cpu_info-r8a7796.o \ +@@ -15,3 +15,6 @@ obj-$(CONFIG_R8A7795) += lowlevel_init.o cpu_info-r8a7795.o \ + obj-$(CONFIG_R8A7796X) += lowlevel_init.o cpu_info-r8a7796.o \ pfc.o pfc-r8a7796.o prr_depend.o \ board.o +obj-$(CONFIG_R8A7797) += lowlevel_init.o cpu_info-r8a7797.o \ @@ -98,10 +98,10 @@ index 0000000..cc8e1e6 + return (u32)(product & 0x0000000F); +} diff --git a/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c b/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c -index c3fd92b..1d5127d 100644 +index 1a699e4..0046c75 100644 --- a/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c +++ b/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c -@@ -73,6 +73,14 @@ int print_cpuinfo(void) +@@ -81,6 +81,14 @@ int print_cpuinfo(void) CONFIG_RCAR_TARGET_STRING); } break; @@ -116,18 +116,6 @@ index c3fd92b..1d5127d 100644 } return 0; } -diff --git a/arch/arm/cpu/armv8/rcar_gen3/pfc.c b/arch/arm/cpu/armv8/rcar_gen3/pfc.c -index b7158b0..dc7d0ab 100644 ---- a/arch/arm/cpu/armv8/rcar_gen3/pfc.c -+++ b/arch/arm/cpu/armv8/rcar_gen3/pfc.c -@@ -20,5 +20,7 @@ void pinmux_init(void) - r8a7795_pinmux_init(); - #elif defined(CONFIG_R8A7796) - r8a7796_pinmux_init(); -+#elif defined(CONFIG_R8A7797) -+ r8a7797_pinmux_init(); - #endif - } diff --git a/arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7797.c b/arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7797.c new file mode 100644 index 0000000..3b2f75e @@ -2898,26 +2886,23 @@ index 0000000..3b2f75e +{ + register_pinmux(&r8a7797_pinmux_info); +} +diff --git a/arch/arm/cpu/armv8/rcar_gen3/pfc.c b/arch/arm/cpu/armv8/rcar_gen3/pfc.c +index 0543f11..bd3aa0a 100644 +--- a/arch/arm/cpu/armv8/rcar_gen3/pfc.c ++++ b/arch/arm/cpu/armv8/rcar_gen3/pfc.c +@@ -20,5 +20,7 @@ void pinmux_init(void) + r8a7795_pinmux_init(); + #elif defined(CONFIG_R8A7796X) + r8a7796_pinmux_init(); ++#elif defined(CONFIG_R8A7797) ++ r8a7797_pinmux_init(); + #endif + } diff --git a/arch/arm/cpu/armv8/rcar_gen3/prr_depend.c b/arch/arm/cpu/armv8/rcar_gen3/prr_depend.c -index 27e40aa..67d3838 100644 +index 776c596..8de3a16 100644 --- a/arch/arm/cpu/armv8/rcar_gen3/prr_depend.c +++ b/arch/arm/cpu/armv8/rcar_gen3/prr_depend.c -@@ -16,12 +16,14 @@ - /* PRR PRODUCT for RCAR */ - #define PRR_PRODUCT_RCAR_H3 (0x4f00ul) - #define PRR_PRODUCT_RCAR_M3 (0x5200ul) -+#define PRR_PRODUCT_RCAR_V3M (0x5400ul) - #define PRR_PRODUCT_MASK (0x7f00ul) - - /* PRR PRODUCT and CUT for RCAR */ - #define PRR_PRODUCT_CUT_RCAR_H3_WS10 (PRR_PRODUCT_RCAR_H3 | 0x00ul) - #define PRR_PRODUCT_CUT_RCAR_H3_WS11 (PRR_PRODUCT_RCAR_H3 | 0x01ul) - #define PRR_PRODUCT_CUT_RCAR_M3_ES10 (PRR_PRODUCT_RCAR_M3 | 0x00ul) -+#define PRR_PRODUCT_CUT_RCAR_V3M_ES10 (PRR_PRODUCT_RCAR_V3M | 0x00ul) - #define PRR_PRODUCT_CUT_MASK (PRR_PRODUCT_MASK | 0xfful) - - #define RCAR_PRR_INIT() rcar_prr_init() -@@ -93,10 +95,37 @@ int rcar_need_reconfig_sdhi_drvctrl(void) +@@ -98,10 +98,37 @@ int rcar_need_reconfig_sdhi_drvctrl(void) #define SDH800_SD200 (SD_SRCFC_DIV1 | SD_FC_DIV4) #define SDH400_SD200 (SD_SRCFC_DIV1 | SD_FC_DIV2) @@ -2950,18 +2935,18 @@ index 27e40aa..67d3838 100644 { if (RCAR_PRR_IS_PRODUCT(H3) && (!RCAR_PRR_CHK_CUT(H3, WS10))) return SDH400_SD200; -+ else if (RCAR_PRR_IS_PRODUCT(V3M) && (!RCAR_PRR_CHK_CUT(V3M, ES10))) ++ else if (RCAR_PRR_IS_PRODUCT(V3M)) + return (SD_SDHFC_DIV2 | SD_SD0FC_DIV8); else return SDH800_SD200; } diff --git a/arch/arm/include/asm/arch-rcar_gen3/gpio.h b/arch/arm/include/asm/arch-rcar_gen3/gpio.h -index 339da49..01d3c59 100644 +index c58edf4..fb8b758 100644 --- a/arch/arm/include/asm/arch-rcar_gen3/gpio.h +++ b/arch/arm/include/asm/arch-rcar_gen3/gpio.h @@ -16,6 +16,8 @@ #include - #elif defined(CONFIG_R8A7796) + #elif defined(CONFIG_R8A7796X) #include +#elif defined(CONFIG_R8A7797) +#include @@ -2970,7 +2955,7 @@ index 339da49..01d3c59 100644 #if defined(CONFIG_R8A7795) @@ -23,6 +25,8 @@ void r8a7795_pinmux_init(void); void r8a7795_es_pinmux_init(void); - #elif defined(CONFIG_R8A7796) + #elif defined(CONFIG_R8A7796X) void r8a7796_pinmux_init(void); +#elif defined(CONFIG_R8A7797) +void r8a7797_pinmux_init(void); @@ -3479,7 +3464,7 @@ index 0000000..09e83ba + +#endif /* __ASM_ARCH_R8A7797_H */ diff --git a/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h b/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h -index dde46ea..a51a060 100644 +index 18c1a74..fa24fc4 100644 --- a/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h +++ b/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h @@ -70,6 +70,11 @@ @@ -3495,12 +3480,12 @@ index dde46ea..a51a060 100644 #define CONFIG_SYS_I2C_SH_BASE0 0xE60B0000 diff --git a/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h b/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h -index 584bd1c..568fc6e 100644 +index b412fad..c2ba0fb 100644 --- a/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h +++ b/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h @@ -14,6 +14,8 @@ #include - #elif defined(CONFIG_R8A7796) + #elif defined(CONFIG_R8A7796X) #include + #elif defined(CONFIG_R8A7797) + #include @@ -3508,21 +3493,21 @@ index 584bd1c..568fc6e 100644 #error "SOC Name not defined" #endif diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h -index d4efe9a..0d532c2 100644 +index fe71e9a..478824e 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -226,7 +226,8 @@ struct uart_port { # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) || \ -- defined(CONFIG_R8A7795) || defined(CONFIG_R8A7796) -+ defined(CONFIG_R8A7795) || defined(CONFIG_R8A7796) || \ +- defined(CONFIG_R8A7795) || defined(CONFIG_R8A7796X) ++ defined(CONFIG_R8A7795) || defined(CONFIG_R8A7796X) || \ + defined(CONFIG_R8A7797) # define SCIF_ORER 0x0001 # define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30) /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h -index 2fe7d3c..32cd265 100644 +index 0a959f7..ec20aba 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -93,7 +93,11 @@ @@ -3537,8 +3522,8 @@ index 2fe7d3c..32cd265 100644 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7fff0) -@@ -118,6 +122,14 @@ - #define PHYS_SDRAM_2_SIZE ((unsigned long)0x80000000) +@@ -124,6 +128,14 @@ + #define PHYS_SDRAM_1_SIZE ((unsigned long)(0x80000000 - DRAM_RSV_SIZE)) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE +#elif defined(CONFIG_R8A7797) diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0015-board-renesas-Add-V3M-Eagle-board.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0015-board-renesas-Add-V3M-Eagle-board.patch index 35ff456..5b300eb 100644 --- a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0015-board-renesas-Add-V3M-Eagle-board.patch +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0015-board-renesas-Add-V3M-Eagle-board.patch @@ -7,14 +7,14 @@ V3M Eagle is a board based on R-Car V3M SoC (R8A7797) Signed-off-by: Vladimir Barinov --- - arch/arm/cpu/armv8/Kconfig | 6 - board/renesas/eagle/Kconfig | 15 + - board/renesas/eagle/MAINTAINERS | 6 - board/renesas/eagle/Makefile | 9 - board/renesas/eagle/eagle.c | 398 ++++++++++++++++++++++++++++++++++++++++ - configs/r8a7797_eagle_defconfig | 9 - include/configs/r8a7797_eagle.h | 155 +++++++++++++++ - 7 files changed, 597 insertions(+), 1 deletion(-) + arch/arm/cpu/armv8/Kconfig | 4 + + board/renesas/eagle/Kconfig | 15 +++ + board/renesas/eagle/MAINTAINERS | 6 ++ + board/renesas/eagle/Makefile | 9 ++ + board/renesas/eagle/eagle.c | 224 ++++++++++++++++++++++++++++++++++++++++ + configs/r8a7797_eagle_defconfig | 9 ++ + include/configs/r8a7797_eagle.h | 152 +++++++++++++++++++++++++++ + 7 files changed, 419 insertions(+) create mode 100644 board/renesas/eagle/Kconfig create mode 100644 board/renesas/eagle/MAINTAINERS create mode 100644 board/renesas/eagle/Makefile @@ -23,10 +23,10 @@ Signed-off-by: Vladimir Barinov create mode 100644 include/configs/r8a7797_eagle.h diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig -index 2daadc9..a645e21 100644 +index dfd9bab..c857214 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig -@@ -13,6 +13,9 @@ choice +@@ -16,6 +16,9 @@ config TARGET_SALVATOR_X config TARGET_ULCB bool "ULCB board" @@ -35,8 +35,8 @@ index 2daadc9..a645e21 100644 + endchoice - choice -@@ -40,5 +43,6 @@ config SYS_SOC + config R8A7796X +@@ -45,5 +48,6 @@ config SYS_SOC source "board/renesas/salvator-x/Kconfig" source "board/renesas/ulcb/Kconfig" @@ -45,7 +45,7 @@ index 2daadc9..a645e21 100644 endif diff --git a/board/renesas/eagle/Kconfig b/board/renesas/eagle/Kconfig new file mode 100644 -index 0000000..3024836 +index 0000000..dffbbeb --- /dev/null +++ b/board/renesas/eagle/Kconfig @@ -0,0 +1,15 @@ @@ -93,7 +93,7 @@ index 0000000..87d63e1 +obj-y := eagle.o ../rcar-gen3-common/common.o diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c new file mode 100644 -index 0000000..137097d +index 0000000..4eda15c --- /dev/null +++ b/board/renesas/eagle/eagle.c @@ -0,0 +1,224 @@ @@ -323,7 +323,7 @@ index 0000000..137097d +#endif diff --git a/configs/r8a7797_eagle_defconfig b/configs/r8a7797_eagle_defconfig new file mode 100644 -index 0000000..fd745a8 +index 0000000..d68e28f --- /dev/null +++ b/configs/r8a7797_eagle_defconfig @@ -0,0 +1,9 @@ @@ -338,7 +338,7 @@ index 0000000..fd745a8 +CONFIG_SPI_FLASH_SPANSION=y diff --git a/include/configs/r8a7797_eagle.h b/include/configs/r8a7797_eagle.h new file mode 100644 -index 0000000..c4e3e5e +index 0000000..a4ae6bf --- /dev/null +++ b/include/configs/r8a7797_eagle.h @@ -0,0 +1,152 @@ diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0017-board-renesas-Add-V3MSK-board.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0017-board-renesas-Add-V3MSK-board.patch index e10bf40..773ca26 100644 --- a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0017-board-renesas-Add-V3MSK-board.patch +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0017-board-renesas-Add-V3MSK-board.patch @@ -27,7 +27,7 @@ Signed-off-by: Vladimir Barinov create mode 100644 include/configs/v3msk.h diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig -index fb2806d..761f4e6 100644 +index c857214..343b121 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -19,6 +19,9 @@ config TARGET_ULCB @@ -39,8 +39,8 @@ index fb2806d..761f4e6 100644 + endchoice - choice -@@ -41,5 +44,6 @@ config SYS_SOC + config R8A7796X +@@ -49,5 +52,6 @@ config SYS_SOC source "board/renesas/salvator-x/Kconfig" source "board/renesas/ulcb/Kconfig" source "board/renesas/eagle/Kconfig" diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch index d9b00f6..68570b3 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch @@ -8,7 +8,7 @@ This adds Renesas R8A7797 SoC support Signed-off-by: Vladimir Barinov --- arch/arm64/Kconfig.platforms | 6 + - arch/arm64/boot/dts/renesas/r8a7797.dtsi | 1005 ++++++++++ + arch/arm64/boot/dts/renesas/r8a7797.dtsi | 1002 ++++++++++ drivers/clk/renesas/Kconfig | 1 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r8a7797-cpg-mssr.c | 222 +++ @@ -21,7 +21,6 @@ Signed-off-by: Vladimir Barinov drivers/gpu/drm/rcar-du/rcar_du_drv.c | 25 + drivers/gpu/drm/rcar-du/rcar_du_group.c | 12 +- drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c | 38 +- - drivers/hwspinlock/rcar_hwspinlock.c | 8 +- drivers/i2c/busses/i2c-rcar.c | 1 + drivers/iommu/ipmmu-vmsa.c | 7 +- drivers/media/platform/soc_camera/Kconfig | 2 +- @@ -30,7 +29,7 @@ Signed-off-by: Vladimir Barinov drivers/media/platform/vsp1/vsp1_drv.c | 9 + drivers/media/platform/vsp1/vsp1_lif.c | 12 +- drivers/media/platform/vsp1/vsp1_regs.h | 7 + - drivers/mmc/host/sh_mobile_sdhi.c | 2 + + drivers/mmc/host/sh_mobile_sdhi.c | 1 + drivers/net/ethernet/renesas/ravb_main.c | 1 + drivers/pinctrl/sh-pfc/Kconfig | 5 + drivers/pinctrl/sh-pfc/Makefile | 1 + @@ -48,7 +47,7 @@ Signed-off-by: Vladimir Barinov drivers/thermal/rcar_gen3_thermal.c | 29 + include/dt-bindings/clock/r8a7797-cpg-mssr.h | 48 + include/dt-bindings/power/r8a7797-sysc.h | 32 + - 41 files changed, 4292 insertions(+), 30 deletions(-) + 40 files changed, 4281 insertions(+), 29 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/r8a7797.dtsi create mode 100644 drivers/clk/renesas/r8a7797-cpg-mssr.c create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a7797.c @@ -57,12 +56,12 @@ Signed-off-by: Vladimir Barinov create mode 100644 include/dt-bindings/power/r8a7797-sysc.h diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms -index 7c104ca..9380fc6 100644 +index ebe0a37..d3b6771 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms -@@ -160,6 +160,12 @@ config ARCH_R8A7796 +@@ -166,6 +166,12 @@ config ARCH_R8A77965 help - This enables support for the Renesas R-Car M3-W SoC. + This enables support for the Renesas R-Car M3N SoC. +config ARCH_R8A7797 + bool "Renesas R-Car V3M SoC Platform" @@ -75,10 +74,10 @@ index 7c104ca..9380fc6 100644 help diff --git a/arch/arm64/boot/dts/renesas/r8a7797.dtsi b/arch/arm64/boot/dts/renesas/r8a7797.dtsi new file mode 100644 -index 0000000..1be93e8 +index 0000000..6eaa5ba --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7797.dtsi -@@ -0,0 +1,1005 @@ +@@ -0,0 +1,1002 @@ +/* + * Device Tree Source for the r8a7797 SoC + * @@ -697,8 +696,8 @@ index 0000000..1be93e8 + <&scif_clk>; /* RMSTPCR2/bit7:SCIF0 */ + /*clock-names = "fck", "sck", "brg_int", "scif_clk"; */ + clock-names = "fck"; -+ dmas = <&dmac1 0x51>, <&dmac1 0x50>; -+ dma-names = "tx", "rx"; ++// dmas = <&dmac1 0x51>, <&dmac1 0x50>; ++// dma-names = "tx", "rx"; + power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; + status = "disabled"; + }; @@ -1034,20 +1033,17 @@ index 0000000..1be93e8 + mfis: mfis@e6260000 { + compatible = "renesas,mfis-r8a7797", "renesas,mfis"; + reg = <0 0xe6260000 0 0x0200>; -+ interrupts = ; /* SPI180:MFIS eicr0 */ -+ interrupt-names = "eicr0"; -+ clocks = <&cpg CPG_MOD 213>; /* RMSTPCR2/bit13:MFIS */ ++ clocks = <&cpg CPG_MOD 213>; + clock-names = "mfis"; -+ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; ++ interrupts = ; ++ interrupt-names = "eicr0"; + status = "okay"; + }; + -+ mfis_lock: mfis-lock { ++ mfis_lock: mfis-lock@e62600c0 { + compatible = "renesas,mfis-lock-r8a7797", + "renesas,mfis-lock"; -+ reg = <0 0xe62600c0 0 0x0750>; /* @@ transitional 0x20->0x750 */ -+ clocks = <&cpg CPG_MOD 213>; /* RMSTPCR2/bit13:MFIS */ -+ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; ++ reg = <0 0xe62600c0 0 0x0020>; + status = "okay"; + }; + @@ -1085,25 +1081,25 @@ index 0000000..1be93e8 + }; +}; diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig -index 2586dfa..f86f2bf 100644 +index bbd9701..b52e907 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig -@@ -4,6 +4,7 @@ config CLK_RENESAS_CPG_MSSR - default y if ARCH_R8A7745 +@@ -5,6 +5,7 @@ config CLK_RENESAS_CPG_MSSR default y if ARCH_R8A7795 default y if ARCH_R8A7796 + default y if ARCH_R8A77965 + default y if ARCH_R8A7797 config CLK_RENESAS_CPG_MSTP bool diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile -index 1072f76..c6f0abb 100644 +index 2c224e9..c2ef11e 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile -@@ -13,6 +13,7 @@ obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-div6.o - obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-div6.o +@@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-div6.o obj-$(CONFIG_ARCH_R8A7795) += r8a7795-cpg-mssr.o rcar-gen3-cpg.o obj-$(CONFIG_ARCH_R8A7796) += r8a7796-cpg-mssr.o rcar-gen3-cpg.o + obj-$(CONFIG_ARCH_R8A77965) += r8a77965-cpg-mssr.o rcar-gen3-cpg.o +obj-$(CONFIG_ARCH_R8A7797) += r8a7797-cpg-mssr.o rcar-gen3-cpg.o obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-div6.o @@ -1447,11 +1443,11 @@ index 51ae7b8..694bedc 100644 struct rcar_gen3_cpg_pll_config { unsigned int extal_div; diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c -index 494e4e8..e523ab7 100644 +index 8c261e1..bd901a6 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c -@@ -588,6 +588,12 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev, - .data = &r8a7796_cpg_mssr_info, +@@ -594,6 +594,12 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev, + .data = &r8a77965_cpg_mssr_info, }, #endif +#ifdef CONFIG_ARCH_R8A7797 @@ -1464,31 +1460,31 @@ index 494e4e8..e523ab7 100644 }; diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h -index 148f4f0a..77c27d8 100644 +index 145b738..ce3546a 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h -@@ -134,6 +134,7 @@ struct cpg_mssr_info { - extern const struct cpg_mssr_info r8a7745_cpg_mssr_info; +@@ -135,6 +135,7 @@ struct cpg_mssr_info { extern const struct cpg_mssr_info r8a7795_cpg_mssr_info; extern const struct cpg_mssr_info r8a7796_cpg_mssr_info; + extern const struct cpg_mssr_info r8a77965_cpg_mssr_info; +extern const struct cpg_mssr_info r8a7797_cpg_mssr_info; /* diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c -index 29f76a4..809a6e1 100644 +index 515d0e7..5a2ec23 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c -@@ -59,6 +59,7 @@ - { .compatible = "renesas,r8a7794", }, +@@ -60,6 +60,7 @@ { .compatible = "renesas,r8a7795", }, { .compatible = "renesas,r8a7796", }, + { .compatible = "renesas,r8a77965", }, + { .compatible = "renesas,r8a7797", }, { .compatible = "renesas,sh73a0", }, { .compatible = "rockchip,rk2928", }, diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c -index 7685d31..02e42ba 100644 +index 6917932..fd15649 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -1,7 +1,7 @@ @@ -1500,7 +1496,7 @@ index 7685d31..02e42ba 100644 * Copyright (C) 2013 Magnus Damm * * This program is free software; you can redistribute it and/or modify -@@ -363,6 +363,10 @@ struct gpio_rcar_info { +@@ -367,6 +367,10 @@ struct gpio_rcar_info { /* Gen3 GPIO is identical to Gen2. */ .data = &gpio_rcar_info_gen2, }, { @@ -1512,11 +1508,11 @@ index 7685d31..02e42ba 100644 .data = &gpio_rcar_info_gen1, }, { diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c -index eb088cb..62612cd 100644 +index b234918..f74f264 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c -@@ -289,6 +289,30 @@ - {/*sentinel*/} +@@ -312,6 +312,30 @@ + .skip_ch = BIT(2), }; +static const struct rcar_du_device_info rcar_du_r8a7797_info = { @@ -1543,19 +1539,19 @@ index eb088cb..62612cd 100644 + .dpll_ch = BIT(1), +}; + - static const struct of_device_id rcar_du_of_table[] = { - { .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info }, - { .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info }, -@@ -298,6 +322,7 @@ - { .compatible = "renesas,du-r8a7794", .data = &rcar_du_r8a7794_info }, + static const struct soc_device_attribute ths_quirks_match[] = { + { .soc_id = "r8a7795", .revision = "ES1.*", + .data = (void *)(RCAR_DU_DPLL_DUTY_RATE_WA +@@ -335,6 +359,7 @@ { .compatible = "renesas,du-r8a7795", .data = &rcar_du_r8a7795_info }, { .compatible = "renesas,du-r8a7796", .data = &rcar_du_r8a7796_info }, + { .compatible = "renesas,du-r8a77965", .data = &rcar_du_r8a77965_info }, + { .compatible = "renesas,du-r8a7797", .data = &rcar_du_r8a7797_info }, { } }; diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c -index ccf5159..4c9e008 100644 +index 1af5eb7..3916b63 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c @@ -29,11 +29,17 @@ @@ -1576,7 +1572,7 @@ index ccf5159..4c9e008 100644 u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg) { return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg); -@@ -147,8 +153,10 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) +@@ -155,8 +161,10 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) /* Apply planes to CRTCs association. */ mutex_lock(&rgrp->lock); @@ -1658,42 +1654,20 @@ index ecae864..d5fa06c 100644 usleep_range(100, 150); lvdcr0 |= LVDCR0_LVRES; -diff --git a/drivers/hwspinlock/rcar_hwspinlock.c b/drivers/hwspinlock/rcar_hwspinlock.c -index b92db1b..a656c0a 100644 ---- a/drivers/hwspinlock/rcar_hwspinlock.c -+++ b/drivers/hwspinlock/rcar_hwspinlock.c -@@ -21,10 +21,16 @@ - #include - #include - #include -+#include - - #include "hwspinlock_internal.h" - --#define RCAR_HWSPINLOCK_NUM (8) -+static const struct soc_device_attribute r8a7797[] = { -+ { .soc_id = "r8a7797" }, -+ { } -+}; -+ -+#define RCAR_HWSPINLOCK_NUM (soc_device_match(r8a7797) ? 64 : 8) - - static int rcar_hwspinlock_trylock(struct hwspinlock *lock) - { diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c -index 73ff520..306ba97 100644 +index 74c17d8..149c107 100644 --- a/drivers/i2c/busses/i2c-rcar.c +++ b/drivers/i2c/busses/i2c-rcar.c @@ -807,6 +807,7 @@ static u32 rcar_i2c_func(struct i2c_adapter *adap) - { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 }, + { .compatible = "renesas,i2c-r8a77965", .data = (void *)I2C_RCAR_GEN3 }, + { .compatible = "renesas,i2c-r8a7797", .data = (void *)I2C_RCAR_GEN3 }, {}, }; MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c -index 4cf30c8..3fdd96e 100644 +index e2baed1..1ae9174 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -1,7 +1,7 @@ @@ -1705,7 +1679,7 @@ index 4cf30c8..3fdd96e 100644 * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by -@@ -1274,6 +1274,9 @@ static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu) +@@ -1277,6 +1277,9 @@ static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu) .compatible = "renesas,ipmmu-r8a7796", .data = &ipmmu_features_rcar_gen3, }, { @@ -1715,7 +1689,7 @@ index 4cf30c8..3fdd96e 100644 /* Terminator */ }, }; -@@ -1643,6 +1646,8 @@ static int __init ipmmu_vmsa_iommu_of_setup(struct device_node *np) +@@ -1648,6 +1651,8 @@ static int __init ipmmu_vmsa_iommu_of_setup(struct device_node *np) ipmmu_vmsa_iommu_of_setup); IOMMU_OF_DECLARE(ipmmu_r8a7796_iommu_of, "renesas,ipmmu-r8a7796", ipmmu_vmsa_iommu_of_setup); @@ -2025,7 +1999,7 @@ index 400958b..74fb005 100644 for (i = 0; i < num; i++) { diff --git a/drivers/media/platform/vsp1/vsp1_drv.c b/drivers/media/platform/vsp1/vsp1_drv.c -index 57b1b81..2f711bb 100644 +index cdaa097..6daeab4 100644 --- a/drivers/media/platform/vsp1/vsp1_drv.c +++ b/drivers/media/platform/vsp1/vsp1_drv.c @@ -893,6 +893,15 @@ void vsp1_device_put(struct vsp1_device *vsp1) @@ -2089,7 +2063,7 @@ index b442d14..e79f9e6 100644 static const struct vsp1_entity_operations lif_entity_ops = { diff --git a/drivers/media/platform/vsp1/vsp1_regs.h b/drivers/media/platform/vsp1/vsp1_regs.h -index fb6d56c..bcba968 100644 +index 9134dbd..6c971f7 100644 --- a/drivers/media/platform/vsp1/vsp1_regs.h +++ b/drivers/media/platform/vsp1/vsp1_regs.h @@ -789,6 +789,12 @@ @@ -2110,41 +2084,40 @@ index fb6d56c..bcba968 100644 #define VI6_IP_VERSION_MODEL_VSPBC_GEN3 (0x16 << 8) #define VI6_IP_VERSION_MODEL_VSPD_GEN3 (0x17 << 8) +#define VI6_IP_VERSION_MODEL_VSPD_V3M (0x18 << 8) - #define VI6_IP_VERSION_MODEL_VSPDL_H3 (0x19 << 8) + #define VI6_IP_VERSION_MODEL_VSPDL_GEN3 (0x19 << 8) + #define VI6_IP_VERSION_SOC_MASK (0xff << 0) - #define VI6_IP_VERSION_SOC_H (0x01 << 0) diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c -index 359a981..49276282 100644 +index a7fb054..040f474 100644 --- a/drivers/mmc/host/sh_mobile_sdhi.c +++ b/drivers/mmc/host/sh_mobile_sdhi.c -@@ -138,6 +138,8 @@ struct sh_mobile_sdhi_of_data { - { .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, }, - { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, }, +@@ -140,6 +140,7 @@ struct sh_mobile_sdhi_of_data { { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, }, + { .compatible = "renesas,sdhi-r8a77965", + .data = &of_rcar_gen3_compatible, }, + { .compatible = "renesas,sdhi-r8a7797", .data = &of_rcar_gen3_compatible, }, -+ { .compatible = "renesas,mmc-r8a7797", .data = &of_rcar_gen3_compatible, }, {}, }; MODULE_DEVICE_TABLE(of, sh_mobile_sdhi_of_match); diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c -index 68019d9..cd4f25a 100644 +index 5ad4d13..73fa286 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c -@@ -1906,6 +1906,7 @@ static int ravb_mdio_release(struct ravb_private *priv) - { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 }, +@@ -1920,6 +1920,7 @@ static int ravb_mdio_release(struct ravb_private *priv) { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, { .compatible = "renesas,etheravb-r8a7796", .data = (void *)RCAR_GEN3 }, + { .compatible = "renesas,etheravb-r8a77965", .data = (void *)RCAR_GEN3 }, + { .compatible = "renesas,etheravb-r8a7797", .data = (void *)RCAR_GEN3 }, { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 }, { } }; diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig -index 07eca54..002541f 100644 +index 6d2cdf8..4aaf0be 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig -@@ -79,6 +79,11 @@ config PINCTRL_PFC_R8A7796 - depends on ARCH_R8A7796 - select PINCTRL_SH_PFC +@@ -84,6 +84,11 @@ config PINCTRL_PFC_R8A77965 + depends on ARCH_R8A77965 + select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A7797 + def_bool y @@ -2155,19 +2128,19 @@ index 07eca54..002541f 100644 def_bool y depends on CPU_SUBTYPE_SH7203 diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile -index 8e08684..10adc18 100644 +index f12017b..e263c14 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile -@@ -13,6 +13,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o - obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o +@@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o + obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o +obj-$(CONFIG_PINCTRL_PFC_R8A7797) += pfc-r8a7797.o obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c -index 7ea6c8e..b536aeb 100644 +index a6a8f65..9aba933 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -5,6 +5,7 @@ @@ -2178,8 +2151,8 @@ index 7ea6c8e..b536aeb 100644 * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive -@@ -539,6 +540,12 @@ static int sh_pfc_init_ranges(struct sh_pfc *pfc) - .data = &r8a7796_pinmux_info, +@@ -545,6 +546,12 @@ static int sh_pfc_init_ranges(struct sh_pfc *pfc) + .data = &r8a77965_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A7797 @@ -4784,18 +4757,18 @@ index 0000000..9b6127f + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h -index 93cce90..0da3ee4 100644 +index 5a0da3c..062af89 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h -@@ -287,6 +287,7 @@ struct sh_pfc_soc_info { - extern const struct sh_pfc_soc_info r8a7795_pinmux_info; +@@ -288,6 +288,7 @@ struct sh_pfc_soc_info { extern const struct sh_pfc_soc_info r8a7795_es1_pinmux_info; extern const struct sh_pfc_soc_info r8a7796_pinmux_info; + extern const struct sh_pfc_soc_info r8a77965_pinmux_info; +extern const struct sh_pfc_soc_info r8a7797_pinmux_info; extern const struct sh_pfc_soc_info sh7203_pinmux_info; extern const struct sh_pfc_soc_info sh7264_pinmux_info; extern const struct sh_pfc_soc_info sh7269_pinmux_info; -@@ -392,6 +393,11 @@ struct sh_pfc_soc_info { +@@ -393,6 +394,11 @@ struct sh_pfc_soc_info { PORT_GP_CFG_1(bank, 3, fn, sfx, cfg) #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) @@ -4807,7 +4780,7 @@ index 93cce90..0da3ee4 100644 #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ PORT_GP_CFG_4(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \ -@@ -438,6 +444,12 @@ struct sh_pfc_soc_info { +@@ -439,6 +445,12 @@ struct sh_pfc_soc_info { PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0) @@ -4821,29 +4794,31 @@ index 93cce90..0da3ee4 100644 PORT_GP_CFG_18(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \ diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile -index 504fb05..37cca0b 100644 +index 29b8a4d..2ba6a76 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile -@@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_RCAR_GEN1) += rcar-rst.o - obj-$(CONFIG_ARCH_RCAR_GEN2) += rcar-rst.o +@@ -5,6 +5,7 @@ obj-$(CONFIG_ARCH_RCAR_GEN2) += rcar-rst.o obj-$(CONFIG_ARCH_R8A7795) += rcar-rst.o obj-$(CONFIG_ARCH_R8A7796) += rcar-rst.o + obj-$(CONFIG_ARCH_R8A77965) += rcar-rst.o +obj-$(CONFIG_ARCH_R8A7797) += rcar-rst.o obj-$(CONFIG_ARCH_R8A7743) += rcar-sysc.o r8a7743-sysc.o obj-$(CONFIG_ARCH_R8A7745) += rcar-sysc.o r8a7745-sysc.o -@@ -16,11 +17,14 @@ obj-$(CONFIG_ARCH_R8A7793) += rcar-sysc.o r8a7791-sysc.o - obj-$(CONFIG_ARCH_R8A7794) += rcar-sysc.o r8a7794-sysc.o +@@ -18,13 +19,16 @@ obj-$(CONFIG_ARCH_R8A7794) += rcar-sysc.o r8a7794-sysc.o obj-$(CONFIG_ARCH_R8A7795) += rcar-sysc.o r8a7795-sysc.o obj-$(CONFIG_ARCH_R8A7796) += rcar-sysc.o r8a7796-sysc.o + obj-$(CONFIG_ARCH_R8A77965) += rcar-sysc.o r8a77965-sysc.o +obj-$(CONFIG_ARCH_R8A7797) += rcar-sysc.o r8a7797-sysc.o obj-$(CONFIG_ARCH_R8A7795) += rcar-avs.o obj-$(CONFIG_ARCH_R8A7796) += rcar-avs.o + obj-$(CONFIG_ARCH_R8A77965) += rcar-avs.o +obj-$(CONFIG_ARCH_R8A7797) += rcar-avs.o # EMS for R-Car Gen3 obj-$(CONFIG_ARCH_R8A7795) += rcar_ems_ctrl.o obj-$(CONFIG_ARCH_R8A7796) += rcar_ems_ctrl.o + obj-$(CONFIG_ARCH_R8A77965) += rcar_ems_ctrl.o +obj-$(CONFIG_ARCH_R8A7797) += rcar_ems_ctrl.o obj-$(CONFIG_RCAR_DDR_BACKUP) += s2ram_ddr_backup.o @@ -4893,24 +4868,24 @@ index 0000000..b71bdedb + .num_areas = ARRAY_SIZE(r8a7797_areas), +}; diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c -index a6d1c26..2e87293 100644 +index 61c2f2c..bc3632b 100644 --- a/drivers/soc/renesas/rcar-rst.c +++ b/drivers/soc/renesas/rcar-rst.c -@@ -41,6 +41,7 @@ struct rst_config { - /* R-Car Gen3 is handled like R-Car Gen2 */ +@@ -42,6 +42,7 @@ struct rst_config { { .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen2 }, { .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen2 }, + { .compatible = "renesas,r8a77965-rst", .data = &rcar_rst_gen2 }, + { .compatible = "renesas,r8a7797-rst", .data = &rcar_rst_gen2 }, { /* sentinel */ } }; diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c -index 072f94c..7e59c72 100644 +index b25c5cf..1d5d440 100644 --- a/drivers/soc/renesas/rcar-sysc.c +++ b/drivers/soc/renesas/rcar-sysc.c -@@ -321,6 +321,9 @@ static void __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd) - #ifdef CONFIG_ARCH_R8A7796 - { .compatible = "renesas,r8a7796-sysc", .data = &r8a7796_sysc_info }, +@@ -324,6 +324,9 @@ static void __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd) + #ifdef CONFIG_ARCH_R8A77965 + { .compatible = "renesas,r8a77965-sysc", .data = &r8a77965_sysc_info }, #endif +#ifdef CONFIG_ARCH_R8A7797 + { .compatible = "renesas,r8a7797-sysc", .data = &r8a7797_sysc_info }, @@ -4919,13 +4894,13 @@ index 072f94c..7e59c72 100644 }; diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h -index cd8bc52..e367715 100644 +index 04b5d01..1eb4e6d 100644 --- a/drivers/soc/renesas/rcar-sysc.h +++ b/drivers/soc/renesas/rcar-sysc.h -@@ -60,4 +60,5 @@ struct rcar_sysc_info { - extern const struct rcar_sysc_info r8a7794_sysc_info; +@@ -61,4 +61,5 @@ struct rcar_sysc_info { extern const struct rcar_sysc_info r8a7795_sysc_info; extern const struct rcar_sysc_info r8a7796_sysc_info; + extern const struct rcar_sysc_info r8a77965_sysc_info; +extern const struct rcar_sysc_info r8a7797_sysc_info; #endif /* __SOC_RENESAS_RCAR_SYSC_H__ */ diff --git a/drivers/soc/renesas/rcar_ems_ctrl.c b/drivers/soc/renesas/rcar_ems_ctrl.c @@ -4962,11 +4937,11 @@ index ca9af73..388c570 100644 continue; for (i = 0; i < total_target_cpu; i++) { diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c -index 5cab1b5..9d6fdb0 100644 +index 1b33c50..63f943d 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c -@@ -134,6 +134,11 @@ struct renesas_soc { - .id = 0x52, +@@ -139,6 +139,11 @@ struct renesas_soc { + .id = 0x55, }; +static const struct renesas_soc soc_rcar_v3m __initconst __maybe_unused = { @@ -4977,9 +4952,9 @@ index 5cab1b5..9d6fdb0 100644 static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = { .family = &fam_shmobile, .id = 0x37, -@@ -183,6 +188,9 @@ struct renesas_soc { - #ifdef CONFIG_ARCH_R8A7796 - { .compatible = "renesas,r8a7796", .data = &soc_rcar_m3_w }, +@@ -191,6 +196,9 @@ struct renesas_soc { + #ifdef CONFIG_ARCH_R8A77965 + { .compatible = "renesas,r8a77965", .data = &soc_rcar_m3_n }, #endif +#ifdef CONFIG_ARCH_R8A7797 + { .compatible = "renesas,r8a7797", .data = &soc_rcar_v3m }, @@ -4988,29 +4963,29 @@ index 5cab1b5..9d6fdb0 100644 { .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 }, #endif diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c -index 996869e..3281dc7 100644 +index 36e70db..a2606fe 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c -@@ -215,7 +215,8 @@ static int msiof_rcar_is_gen3(struct device *dev) - struct device_node *node = dev->of_node; +@@ -216,7 +216,8 @@ static int msiof_rcar_is_gen3(struct device *dev) return of_device_is_compatible(node, "renesas,msiof-r8a7795") || -- of_device_is_compatible(node, "renesas,msiof-r8a7796"); -+ of_device_is_compatible(node, "renesas,msiof-r8a7796") || + of_device_is_compatible(node, "renesas,msiof-r8a7796") || +- of_device_is_compatible(node, "renesas,msiof-r8a77965"); ++ of_device_is_compatible(node, "renesas,msiof-r8a77965") || + of_device_is_compatible(node, "renesas,msiof-r8a7797"); } static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) -@@ -1188,6 +1189,7 @@ static int sh_msiof_transfer_one(struct spi_master *master, - { .compatible = "renesas,msiof-r8a7794", .data = &r8a779x_data }, +@@ -1190,6 +1191,7 @@ static int sh_msiof_transfer_one(struct spi_master *master, { .compatible = "renesas,msiof-r8a7795", .data = &r8a779x_data }, { .compatible = "renesas,msiof-r8a7796", .data = &r8a779x_data }, + { .compatible = "renesas,msiof-r8a77965", .data = &r8a779x_data }, + { .compatible = "renesas,msiof-r8a7797", .data = &r8a779x_data }, {}, }; MODULE_DEVICE_TABLE(of, sh_msiof_match); diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c -index 6700dda..a9f4d96 100644 +index 6eb7395..a23dd44 100644 --- a/drivers/thermal/rcar_gen3_thermal.c +++ b/drivers/thermal/rcar_gen3_thermal.c @@ -391,6 +391,30 @@ static int rcar_gen3_r8a7795_thermal_init(struct rcar_thermal_priv *priv) @@ -5044,7 +5019,7 @@ index 6700dda..a9f4d96 100644 /* * Interrupt */ -@@ -472,9 +496,14 @@ static int rcar_gen3_thermal_remove(struct platform_device *pdev) +@@ -472,10 +496,15 @@ static int rcar_gen3_thermal_remove(struct platform_device *pdev) .thermal_init = rcar_gen3_r8a7796_thermal_init, }; @@ -5055,6 +5030,7 @@ index 6700dda..a9f4d96 100644 static const struct of_device_id rcar_thermal_dt_ids[] = { { .compatible = "renesas,thermal-r8a7795", .data = &r8a7795_data}, { .compatible = "renesas,thermal-r8a7796", .data = &r8a7796_data}, + { .compatible = "renesas,thermal-r8a77965", .data = &r8a7796_data}, + { .compatible = "renesas,thermal-r8a7797", .data = &r8a7797_data}, {}, }; diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch index 20adbaf..c193eb3 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch @@ -115,9 +115,9 @@ diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/ index 32fb4d9..1321e4f 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile -@@ -4,5 +4,24 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb - dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb - dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb +@@ -6,5 +6,24 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb + dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb + dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-xs.dtb +# ADAS boards +dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x-view.dtb diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0079-ASoC-fix-pcm-creation-regression.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0079-ASoC-fix-pcm-creation-regression.patch deleted file mode 100644 index ab0048c..0000000 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0079-ASoC-fix-pcm-creation-regression.patch +++ /dev/null @@ -1,173 +0,0 @@ -From c641e5b207ed7dfaa692820aeb5b6dde3de3e9b0 Mon Sep 17 00:00:00 2001 -From: Johan Hovold -Date: Wed, 12 Jul 2017 17:55:29 +0200 -Subject: [PATCH] ASoC: fix pcm-creation regression - -This reverts commit 99b04f4c4051 ("ASoC: add Component level -pcm_new/pcm_free"), which started calling the pcm_new callback for every -component in a *card* when creating a new pcm, something which does not -seem to make any sense. - -This specifically led to memory leaks in systems with more than one -platform component and where DMA memory is allocated in the -platform-driver callback. For example, when both mcasp devices are being -used on an am335x board, DMA memory would be allocated twice for every -DAI link during probe. - -When CONFIG_SND_VERBOSE_PROCFS was set this fortunately also led to -warnings such as: - -WARNING: CPU: 0 PID: 565 at ../fs/proc/generic.c:346 proc_register+0x110/0x154 -proc_dir_entry 'sub0/prealloc' already registered - -Since there seems to be no users of the new component callbacks, and the -current implementation introduced a regression, let's revert the -offending commit for now. - -Fixes: 99b04f4c4051 ("ASoC: add Component level pcm_new/pcm_free") -Signed-off-by: Johan Hovold -Reviewed-by: Linus Walleij -Tested-by: Linus Walleij -Signed-off-by: Mark Brown -Cc: stable # 4.10 ---- - include/sound/soc.h | 6 ------ - sound/soc/soc-core.c | 25 ------------------------- - sound/soc/soc-pcm.c | 32 +++++++++----------------------- - 3 files changed, 9 insertions(+), 54 deletions(-) - -diff --git a/include/sound/soc.h b/include/sound/soc.h -index 9c94b97..c4a8b19 100644 ---- a/include/sound/soc.h -+++ b/include/sound/soc.h -@@ -795,10 +795,6 @@ struct snd_soc_component_driver { - int (*suspend)(struct snd_soc_component *); - int (*resume)(struct snd_soc_component *); - -- /* pcm creation and destruction */ -- int (*pcm_new)(struct snd_soc_pcm_runtime *); -- void (*pcm_free)(struct snd_pcm *); -- - /* DT */ - int (*of_xlate_dai_name)(struct snd_soc_component *component, - struct of_phandle_args *args, -@@ -874,8 +870,6 @@ struct snd_soc_component { - void (*remove)(struct snd_soc_component *); - int (*suspend)(struct snd_soc_component *); - int (*resume)(struct snd_soc_component *); -- int (*pcm_new)(struct snd_soc_pcm_runtime *); -- void (*pcm_free)(struct snd_pcm *); - - /* machine specific init */ - int (*init)(struct snd_soc_component *component); -diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c -index 921622a..c240e13 100644 ---- a/sound/soc/soc-core.c -+++ b/sound/soc/soc-core.c -@@ -3171,8 +3171,6 @@ static int snd_soc_component_initialize(struct snd_soc_component *component, - component->remove = component->driver->remove; - component->suspend = component->driver->suspend; - component->resume = component->driver->resume; -- component->pcm_new = component->driver->pcm_new; -- component->pcm_free = component->driver->pcm_free; - - dapm = &component->dapm; - dapm->dev = dev; -@@ -3360,25 +3358,6 @@ static void snd_soc_platform_drv_remove(struct snd_soc_component *component) - platform->driver->remove(platform); - } - --static int snd_soc_platform_drv_pcm_new(struct snd_soc_pcm_runtime *rtd) --{ -- struct snd_soc_platform *platform = rtd->platform; -- -- if (platform->driver->pcm_new) -- return platform->driver->pcm_new(rtd); -- else -- return 0; --} -- --static void snd_soc_platform_drv_pcm_free(struct snd_pcm *pcm) --{ -- struct snd_soc_pcm_runtime *rtd = pcm->private_data; -- struct snd_soc_platform *platform = rtd->platform; -- -- if (platform->driver->pcm_free) -- platform->driver->pcm_free(pcm); --} -- - /** - * snd_soc_add_platform - Add a platform to the ASoC core - * @dev: The parent device for the platform -@@ -3402,10 +3381,6 @@ int snd_soc_add_platform(struct device *dev, struct snd_soc_platform *platform, - platform->component.probe = snd_soc_platform_drv_probe; - if (platform_drv->remove) - platform->component.remove = snd_soc_platform_drv_remove; -- if (platform_drv->pcm_new) -- platform->component.pcm_new = snd_soc_platform_drv_pcm_new; -- if (platform_drv->pcm_free) -- platform->component.pcm_free = snd_soc_platform_drv_pcm_free; - - #ifdef CONFIG_DEBUG_FS - platform->component.debugfs_prefix = "platform"; -diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c -index dcc5ece..553f7a7 100644 ---- a/sound/soc/soc-pcm.c -+++ b/sound/soc/soc-pcm.c -@@ -2628,25 +2628,12 @@ static int dpcm_fe_dai_close(struct snd_pcm_substream *fe_substream) - return ret; - } - --static void soc_pcm_free(struct snd_pcm *pcm) --{ -- struct snd_soc_pcm_runtime *rtd = pcm->private_data; -- struct snd_soc_component *component; -- -- list_for_each_entry(component, &rtd->card->component_dev_list, -- card_list) { -- if (component->pcm_free) -- component->pcm_free(pcm); -- } --} -- - /* create a new pcm */ - int soc_new_pcm(struct snd_soc_pcm_runtime *rtd, int num) - { - struct snd_soc_platform *platform = rtd->platform; - struct snd_soc_dai *codec_dai; - struct snd_soc_dai *cpu_dai = rtd->cpu_dai; -- struct snd_soc_component *component; - struct snd_pcm *pcm; - char new_name[64]; - int ret = 0, playback = 0, capture = 0; -@@ -2756,18 +2743,17 @@ int soc_new_pcm(struct snd_soc_pcm_runtime *rtd, int num) - if (capture) - snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &rtd->ops); - -- list_for_each_entry(component, &rtd->card->component_dev_list, card_list) { -- if (component->pcm_new) { -- ret = component->pcm_new(rtd); -- if (ret < 0) { -- dev_err(component->dev, -- "ASoC: pcm constructor failed: %d\n", -- ret); -- return ret; -- } -+ if (platform->driver->pcm_new) { -+ ret = platform->driver->pcm_new(rtd); -+ if (ret < 0) { -+ dev_err(platform->dev, -+ "ASoC: pcm constructor failed: %d\n", -+ ret); -+ return ret; - } - } -- pcm->private_free = soc_pcm_free; -+ -+ pcm->private_free = platform->driver->pcm_free; - out: - dev_info(rtd->card->dev, "%s <-> %s mapping ok\n", - (rtd->num_codecs > 1) ? "multicodec" : rtd->codec_dai->name, --- -1.9.1 - diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0079-Revert-dmaengine-rcar-dmac-use-TCRB-instead-of-TCR-f.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0079-Revert-dmaengine-rcar-dmac-use-TCRB-instead-of-TCR-f.patch new file mode 100644 index 0000000..97409fa --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0079-Revert-dmaengine-rcar-dmac-use-TCRB-instead-of-TCR-f.patch @@ -0,0 +1,29 @@ +From b3026b3a8ddcd9801583aa5e653ef432fbe60bf0 Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov +Date: Mon, 4 Dec 2017 17:49:47 +0300 +Subject: [PATCH] Revert "dmaengine: rcar-dmac: use TCRB instead of TCR for + residue" + +The patch breaks SCIF DMA support + +This reverts commit 936abcc1d0b13ff4a112b153e56c0e60bbdc0f5f. +--- + drivers/dma/sh/rcar-dmac.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c +index 9120ff4..0ae7131 100644 +--- a/drivers/dma/sh/rcar-dmac.c ++++ b/drivers/dma/sh/rcar-dmac.c +@@ -1298,7 +1298,7 @@ static unsigned int rcar_dmac_chan_get_residue(struct rcar_dmac_chan *chan, + } + + /* Add the residue for the current chunk. */ +- residue += rcar_dmac_chan_read(chan, RCAR_DMATCRB) << desc->xfer_shift; ++ residue += rcar_dmac_chan_read(chan, RCAR_DMATCR) << desc->xfer_shift; + + return residue; + } +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0100-LVDS-ar0132-use-raw12.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0100-LVDS-ar0132-use-raw12.patch index abf2624..7822b35 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0100-LVDS-ar0132-use-raw12.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0100-LVDS-ar0132-use-raw12.patch @@ -141,7 +141,7 @@ index 8dd0f99..caa3f74 100644 } reg8_write(client, 0x70, (idx << 6) | 0x1e); /* CSI data type: yuv422 8-bit, assign VC */ - reg8_write(client, 0x7c, 0x81); /* BIT(7) - magic to Use RAW10 as 8-bit mode */ -+ reg8_write(client, 0x71, (idx << 6) | 0x2a); /* CSI data type: RAW12, assign VC */ ++ reg8_write(client, 0x71, (idx << 6) | 0x2a); /* CSI data type: RAW8 (for RAW12 and bits reodering), assign VC */ + reg8_write(client, 0x7c, 0x00); /* RAW12 mode */ + reg8_write(client, 0xbc, 0x00); /* Setup minimal time between FV and LV to 3 PCLKs */ reg8_write(client, 0x6e, 0x88); /* Sensor reset: backchannel GPIO0/GPIO1 set low */ diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend index 0b4d393..d996b6a 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend @@ -69,7 +69,7 @@ SRC_URI_append = " \ file://0076-MOST-dim2-Renesas-R-Car3-variant.patch \ file://0077-MOST-dim2-add-timeouts.patch \ file://0078-MOST-aim-fix-null-pointer-crash.patch \ - file://0079-ASoC-fix-pcm-creation-regression.patch \ + file://0079-Revert-dmaengine-rcar-dmac-use-TCRB-instead-of-TCR-f.patch \ " SRC_URI_append_r8a7797 = " \ -- cgit 1.2.3-korg From 465a65cfdc9009860286222004f8ea1eb6c7b103 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Sun, 10 Dec 2017 23:54:04 +0300 Subject: KF: release GP6_08 - Release GP6_08 and input pins used on gpio expander U11, since this pin is used by IPL for access CPLD during gpio bitbang i/f to implement reset - fix typo in i2cswitch node name --- .../0040-arm64-dts-renesas-add-ADAS-boards.patch | 31 +++++++--------------- 1 file changed, 9 insertions(+), 22 deletions(-) (limited to 'meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch') diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch index c193eb3..9db9056 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch @@ -64,11 +64,11 @@ Signed-off-by: Vladimir Barinov arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi | 545 ++++++ arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi | 30 + arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi | 46 + - arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 1554 ++++++++++++++++++ + arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 1541 +++++++++++++++++ arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi | 515 ++++++ arch/arm64/boot/dts/renesas/ulcb-vb.dtsi | 1726 ++++++++++++++++++++ arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi | 578 +++++++ - 42 files changed, 17184 insertions(+) + 42 files changed, 17171 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/legacy/Makefile create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts @@ -112,10 +112,10 @@ Signed-off-by: Vladimir Barinov create mode 100644 arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile -index 32fb4d9..1321e4f 100644 +index f9c71df..af88350 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile -@@ -6,5 +6,24 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb +@@ -6,5 +6,24 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-xs.dtb @@ -13156,10 +13156,10 @@ index 0000000..b854216 +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi new file mode 100644 -index 0000000..917dbab +index 0000000..5958450 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi -@@ -0,0 +1,1554 @@ +@@ -0,0 +1,1541 @@ +/* + * Device Tree Source for the ULCB Kingfisher board + * @@ -13637,10 +13637,11 @@ index 0000000..917dbab + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; ++/* + interrupt-controller; + interrupt-parent = <&gpio6>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; -+ ++*/ + hub_pwen { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; @@ -13665,18 +13666,6 @@ index 0000000..917dbab + output-high; + line-name = "OTG EXTLPn"; + }; -+ otg_stat1 { -+ gpio-hog; -+ gpios = <10 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "OTG Stat1"; -+ }; -+ otg_stat2 { -+ gpio-hog; -+ gpios = <11 GPIO_ACTIVE_HIGH>; -+ input; -+ line-name = "OTG Stat2"; -+ }; + }; + + gpio_ext_75: pca9539@75 { @@ -13951,7 +13940,7 @@ index 0000000..917dbab + }; + }; + -+ i2cswitch4: pca9548@74 { ++ i2cswitch4: pca9548@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; @@ -14712,8 +14701,6 @@ index 0000000..917dbab + pcie1v8-supply = <&mpcie_1v8>; +}; + -+ -+ diff --git a/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi b/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi new file mode 100644 index 0000000..92ed4a4 -- cgit 1.2.3-korg