This setting is only applicable to data pins used for Generic Streaming including any linked pins to Streaming Port B. All data pins share the same FSY / SCK signals, hence this setting applies to all data pins.
- Enumerator:
UCS_STREAM_PORT_CLK_DLY_NONE |
Data is not delayed by a single SCK clock delay.
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UCS_STREAM_PORT_CLK_DLY_DELAYED |
There is a single SCK clock delay between the start of frame (falling edge of FSY) and the start of the frame data on the data pins.
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UCS_STREAM_PORT_CLK_DLY_WILD |
Wildcard.
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