From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001 From: Angelos Mouzakitis Date: Tue, 10 Oct 2023 14:33:42 +0000 Subject: Add submodule dependency files Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec --- .../synctools/tablegen/X86/back/X86InstrFMA.td | 636 +++++++++++++++++++++ 1 file changed, 636 insertions(+) create mode 100644 capstone/suite/synctools/tablegen/X86/back/X86InstrFMA.td (limited to 'capstone/suite/synctools/tablegen/X86/back/X86InstrFMA.td') diff --git a/capstone/suite/synctools/tablegen/X86/back/X86InstrFMA.td b/capstone/suite/synctools/tablegen/X86/back/X86InstrFMA.td new file mode 100644 index 000000000..a559f62c8 --- /dev/null +++ b/capstone/suite/synctools/tablegen/X86/back/X86InstrFMA.td @@ -0,0 +1,636 @@ +//===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes FMA (Fused Multiply-Add) instructions. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// FMA3 - Intel 3 operand Fused Multiply-Add instructions +//===----------------------------------------------------------------------===// + +// For all FMA opcodes declared in fma3p_rm_* and fma3s_rm_* multiclasses +// defined below, both the register and memory variants are commutable. +// For the register form the commutable operands are 1, 2 and 3. +// For the memory variant the folded operand must be in 3. Thus, +// in that case, only the operands 1 and 2 can be swapped. +// Commuting some of operands may require the opcode change. +// FMA*213*: +// operands 1 and 2 (memory & register forms): *213* --> *213*(no changes); +// operands 1 and 3 (register forms only): *213* --> *231*; +// operands 2 and 3 (register forms only): *213* --> *132*. +// FMA*132*: +// operands 1 and 2 (memory & register forms): *132* --> *231*; +// operands 1 and 3 (register forms only): *132* --> *132*(no changes); +// operands 2 and 3 (register forms only): *132* --> *213*. +// FMA*231*: +// operands 1 and 2 (memory & register forms): *231* --> *132*; +// operands 1 and 3 (register forms only): *231* --> *213*; +// operands 2 and 3 (register forms only): *231* --> *231*(no changes). + +multiclass fma3p_rm_213 opc, string OpcodeStr, RegisterClass RC, + ValueType VT, X86MemOperand x86memop, PatFrag MemFrag, + SDNode Op, X86FoldableSchedWrite sched> { + def r : FMA3, + Sched<[sched]>; + + let mayLoad = 1 in + def m : FMA3, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +multiclass fma3p_rm_231 opc, string OpcodeStr, RegisterClass RC, + ValueType VT, X86MemOperand x86memop, PatFrag MemFrag, + SDNode Op, X86FoldableSchedWrite sched> { + let hasSideEffects = 0 in + def r : FMA3, Sched<[sched]>; + + let mayLoad = 1 in + def m : FMA3, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +multiclass fma3p_rm_132 opc, string OpcodeStr, RegisterClass RC, + ValueType VT, X86MemOperand x86memop, PatFrag MemFrag, + SDNode Op, X86FoldableSchedWrite sched> { + let hasSideEffects = 0 in + def r : FMA3, Sched<[sched]>; + + // Pattern is 312 order so that the load is in a different place from the + // 213 and 231 patterns this helps tablegen's duplicate pattern detection. + let mayLoad = 1 in + def m : FMA3, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +let Constraints = "$src1 = $dst", hasSideEffects = 0, isCommutable = 1 in +multiclass fma3p_forms opc132, bits<8> opc213, bits<8> opc231, + string OpcodeStr, string PackTy, string Suff, + PatFrag MemFrag128, PatFrag MemFrag256, + SDNode Op, ValueType OpTy128, ValueType OpTy256, + X86SchedWriteWidths sched> { + defm NAME#213#Suff : fma3p_rm_213; + defm NAME#231#Suff : fma3p_rm_231; + defm NAME#132#Suff : fma3p_rm_132; + + defm NAME#213#Suff#Y : fma3p_rm_213, + VEX_L; + defm NAME#231#Suff#Y : fma3p_rm_231, + VEX_L; + defm NAME#132#Suff#Y : fma3p_rm_132, + VEX_L; +} + +// Fused Multiply-Add +let ExeDomain = SSEPackedSingle in { + defm VFMADD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", "PS", + loadv4f32, loadv8f32, X86Fmadd, v4f32, v8f32, + SchedWriteFMA>; + defm VFMSUB : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", "PS", + loadv4f32, loadv8f32, X86Fmsub, v4f32, v8f32, + SchedWriteFMA>; + defm VFMADDSUB : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps", "PS", + loadv4f32, loadv8f32, X86Fmaddsub, v4f32, v8f32, + SchedWriteFMA>; + defm VFMSUBADD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps", "PS", + loadv4f32, loadv8f32, X86Fmsubadd, v4f32, v8f32, + SchedWriteFMA>; +} + +let ExeDomain = SSEPackedDouble in { + defm VFMADD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", "PD", + loadv2f64, loadv4f64, X86Fmadd, v2f64, + v4f64, SchedWriteFMA>, VEX_W; + defm VFMSUB : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", "PD", + loadv2f64, loadv4f64, X86Fmsub, v2f64, + v4f64, SchedWriteFMA>, VEX_W; + defm VFMADDSUB : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd", "PD", + loadv2f64, loadv4f64, X86Fmaddsub, + v2f64, v4f64, SchedWriteFMA>, VEX_W; + defm VFMSUBADD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd", "PD", + loadv2f64, loadv4f64, X86Fmsubadd, + v2f64, v4f64, SchedWriteFMA>, VEX_W; +} + +// Fused Negative Multiply-Add +let ExeDomain = SSEPackedSingle in { + defm VFNMADD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", "PS", loadv4f32, + loadv8f32, X86Fnmadd, v4f32, v8f32, SchedWriteFMA>; + defm VFNMSUB : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", "PS", loadv4f32, + loadv8f32, X86Fnmsub, v4f32, v8f32, SchedWriteFMA>; +} +let ExeDomain = SSEPackedDouble in { + defm VFNMADD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", "PD", loadv2f64, + loadv4f64, X86Fnmadd, v2f64, v4f64, SchedWriteFMA>, VEX_W; + defm VFNMSUB : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd", "PD", loadv2f64, + loadv4f64, X86Fnmsub, v2f64, v4f64, SchedWriteFMA>, VEX_W; +} + +// All source register operands of FMA opcodes defined in fma3s_rm multiclass +// can be commuted. In many cases such commute transformation requres an opcode +// adjustment, for example, commuting the operands 1 and 2 in FMA*132 form +// would require an opcode change to FMA*231: +// FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2; +// --> +// FMA*231* reg2, reg1, reg3; // reg1 * reg3 + reg2; +// Please see more detailed comment at the very beginning of the section +// defining FMA3 opcodes above. +multiclass fma3s_rm_213 opc, string OpcodeStr, + X86MemOperand x86memop, RegisterClass RC, + SDPatternOperator OpNode, + X86FoldableSchedWrite sched> { + def r : FMA3S, + Sched<[sched]>; + + let mayLoad = 1 in + def m : FMA3S, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +multiclass fma3s_rm_231 opc, string OpcodeStr, + X86MemOperand x86memop, RegisterClass RC, + SDPatternOperator OpNode, X86FoldableSchedWrite sched> { + let hasSideEffects = 0 in + def r : FMA3S, Sched<[sched]>; + + let mayLoad = 1 in + def m : FMA3S, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +multiclass fma3s_rm_132 opc, string OpcodeStr, + X86MemOperand x86memop, RegisterClass RC, + SDPatternOperator OpNode, X86FoldableSchedWrite sched> { + let hasSideEffects = 0 in + def r : FMA3S, Sched<[sched]>; + + // Pattern is 312 order so that the load is in a different place from the + // 213 and 231 patterns this helps tablegen's duplicate pattern detection. + let mayLoad = 1 in + def m : FMA3S, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +let Constraints = "$src1 = $dst", isCommutable = 1, hasSideEffects = 0 in +multiclass fma3s_forms opc132, bits<8> opc213, bits<8> opc231, + string OpStr, string PackTy, string Suff, + SDNode OpNode, RegisterClass RC, + X86MemOperand x86memop, X86FoldableSchedWrite sched> { + defm NAME#213#Suff : fma3s_rm_213; + defm NAME#231#Suff : fma3s_rm_231; + defm NAME#132#Suff : fma3s_rm_132; +} + +// These FMA*_Int instructions are defined specially for being used when +// the scalar FMA intrinsics are lowered to machine instructions, and in that +// sense, they are similar to existing ADD*_Int, SUB*_Int, MUL*_Int, etc. +// instructions. +// +// All of the FMA*_Int opcodes are defined as commutable here. +// Commuting the 2nd and 3rd source register operands of FMAs is quite trivial +// and the corresponding optimizations have been developed. +// Commuting the 1st operand of FMA*_Int requires some additional analysis, +// the commute optimization is legal only if all users of FMA*_Int use only +// the lowest element of the FMA*_Int instruction. Even though such analysis +// may be not implemented yet we allow the routines doing the actual commute +// transformation to decide if one or another instruction is commutable or not. +let Constraints = "$src1 = $dst", isCommutable = 1, isCodeGenOnly = 1, + hasSideEffects = 0 in +multiclass fma3s_rm_int opc, string OpcodeStr, + Operand memopr, RegisterClass RC, + X86FoldableSchedWrite sched> { + def r_Int : FMA3S_Int, Sched<[sched]>; + + let mayLoad = 1 in + def m_Int : FMA3S_Int, Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +// The FMA 213 form is created for lowering of scalar FMA intrinscis +// to machine instructions. +// The FMA 132 form can trivially be get by commuting the 2nd and 3rd operands +// of FMA 213 form. +// The FMA 231 form can be get only by commuting the 1st operand of 213 or 132 +// forms and is possible only after special analysis of all uses of the initial +// instruction. Such analysis do not exist yet and thus introducing the 231 +// form of FMA*_Int instructions is done using an optimistic assumption that +// such analysis will be implemented eventually. +multiclass fma3s_int_forms opc132, bits<8> opc213, bits<8> opc231, + string OpStr, string PackTy, string Suff, + RegisterClass RC, Operand memop, + X86FoldableSchedWrite sched> { + defm NAME#132#Suff : fma3s_rm_int; + defm NAME#213#Suff : fma3s_rm_int; + defm NAME#231#Suff : fma3s_rm_int; +} + +multiclass fma3s opc132, bits<8> opc213, bits<8> opc231, + string OpStr, SDNode OpNode, X86FoldableSchedWrite sched> { + let ExeDomain = SSEPackedSingle in + defm NAME : fma3s_forms, + fma3s_int_forms; + + let ExeDomain = SSEPackedDouble in + defm NAME : fma3s_forms, + fma3s_int_forms, VEX_W; +} + +defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", X86Fmadd, + SchedWriteFMA.Scl>, VEX_LIG; +defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", X86Fmsub, + SchedWriteFMA.Scl>, VEX_LIG; + +defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", X86Fnmadd, + SchedWriteFMA.Scl>, VEX_LIG; +defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", X86Fnmsub, + SchedWriteFMA.Scl>, VEX_LIG; + +multiclass scalar_fma_patterns { + let Predicates = [HasFMA, NoAVX512] in { + def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector + (Op RC:$src2, + (EltVT (extractelt (VT VR128:$src1), (iPTR 0))), + RC:$src3))))), + (!cast(Prefix#"213"#Suffix#"r_Int") + VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), + (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>; + + def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector + (Op RC:$src2, RC:$src3, + (EltVT (extractelt (VT VR128:$src1), (iPTR 0)))))))), + (!cast(Prefix#"231"#Suffix#"r_Int") + VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), + (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>; + + def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector + (Op RC:$src2, + (EltVT (extractelt (VT VR128:$src1), (iPTR 0))), + (mem_frag addr:$src3)))))), + (!cast(Prefix#"213"#Suffix#"m_Int") + VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), + addr:$src3)>; + + def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector + (Op (EltVT (extractelt (VT VR128:$src1), (iPTR 0))), + (mem_frag addr:$src3), RC:$src2))))), + (!cast(Prefix#"132"#Suffix#"m_Int") + VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), + addr:$src3)>; + + def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector + (Op RC:$src2, (mem_frag addr:$src3), + (EltVT (extractelt (VT VR128:$src1), (iPTR 0)))))))), + (!cast(Prefix#"231"#Suffix#"m_Int") + VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), + addr:$src3)>; + } +} + +defm : scalar_fma_patterns; +defm : scalar_fma_patterns; +defm : scalar_fma_patterns; +defm : scalar_fma_patterns; + +defm : scalar_fma_patterns; +defm : scalar_fma_patterns; +defm : scalar_fma_patterns; +defm : scalar_fma_patterns; + +//===----------------------------------------------------------------------===// +// FMA4 - AMD 4 operand Fused Multiply-Add instructions +//===----------------------------------------------------------------------===// + +multiclass fma4s opc, string OpcodeStr, RegisterClass RC, + X86MemOperand x86memop, ValueType OpVT, SDNode OpNode, + PatFrag mem_frag, X86FoldableSchedWrite sched> { + let isCommutable = 1 in + def rr : FMA4S, VEX_W, VEX_LIG, + Sched<[sched]>; + def rm : FMA4S, VEX_W, VEX_LIG, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; + def mr : FMA4S, VEX_LIG, + Sched<[sched.Folded, ReadAfterLd, + // x86memop:$src2 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC:$src3 + ReadAfterLd]>; +// For disassembler +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in + def rr_REV : FMA4S, + VEX_LIG, FoldGenData, Sched<[sched]>; +} + +multiclass fma4s_int opc, string OpcodeStr, Operand memop, + ValueType VT, X86FoldableSchedWrite sched> { +let isCodeGenOnly = 1, hasSideEffects = 0 in { + def rr_Int : FMA4S_Int, VEX_W, VEX_LIG, Sched<[sched]>; + let mayLoad = 1 in + def rm_Int : FMA4S_Int, VEX_W, VEX_LIG, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; + let mayLoad = 1 in + def mr_Int : FMA4S_Int, + VEX_LIG, Sched<[sched.Folded, ReadAfterLd, + // memop:$src2 + ReadDefault, ReadDefault, ReadDefault, + ReadDefault, ReadDefault, + // VR128::$src3 + ReadAfterLd]>; + def rr_Int_REV : FMA4S_Int, VEX_LIG, FoldGenData, Sched<[sched]>; +} // isCodeGenOnly = 1 +} + +multiclass fma4p opc, string OpcodeStr, SDNode OpNode, + ValueType OpVT128, ValueType OpVT256, + PatFrag ld_frag128, PatFrag ld_frag256, + X86SchedWriteWidths sched> { + let isCommutable = 1 in + def rr : FMA4, + VEX_W, Sched<[sched.XMM]>; + def rm : FMA4, VEX_W, + Sched<[sched.XMM.Folded, ReadAfterLd, ReadAfterLd]>; + def mr : FMA4, + Sched<[sched.XMM.Folded, ReadAfterLd, + // f128mem:$src2 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // VR128::$src3 + ReadAfterLd]>; + let isCommutable = 1 in + def Yrr : FMA4, + VEX_W, VEX_L, Sched<[sched.YMM]>; + def Yrm : FMA4, VEX_W, VEX_L, + Sched<[sched.YMM.Folded, ReadAfterLd, ReadAfterLd]>; + def Ymr : FMA4, VEX_L, + Sched<[sched.YMM.Folded, ReadAfterLd, + // f256mem:$src2 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // VR256::$src3 + ReadAfterLd]>; +// For disassembler +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { + def rr_REV : FMA4, + Sched<[sched.XMM]>, FoldGenData; + def Yrr_REV : FMA4, + VEX_L, Sched<[sched.YMM]>, FoldGenData; +} // isCodeGenOnly = 1 +} + +let ExeDomain = SSEPackedSingle in { + // Scalar Instructions + defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, X86Fmadd, loadf32, + SchedWriteFMA.Scl>, + fma4s_int<0x6A, "vfmaddss", ssmem, v4f32, + SchedWriteFMA.Scl>; + defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", FR32, f32mem, f32, X86Fmsub, loadf32, + SchedWriteFMA.Scl>, + fma4s_int<0x6E, "vfmsubss", ssmem, v4f32, + SchedWriteFMA.Scl>; + defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", FR32, f32mem, f32, + X86Fnmadd, loadf32, SchedWriteFMA.Scl>, + fma4s_int<0x7A, "vfnmaddss", ssmem, v4f32, + SchedWriteFMA.Scl>; + defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", FR32, f32mem, f32, + X86Fnmsub, loadf32, SchedWriteFMA.Scl>, + fma4s_int<0x7E, "vfnmsubss", ssmem, v4f32, + SchedWriteFMA.Scl>; + // Packed Instructions + defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86Fmadd, v4f32, v8f32, + loadv4f32, loadv8f32, SchedWriteFMA>; + defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86Fmsub, v4f32, v8f32, + loadv4f32, loadv8f32, SchedWriteFMA>; + defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86Fnmadd, v4f32, v8f32, + loadv4f32, loadv8f32, SchedWriteFMA>; + defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86Fnmsub, v4f32, v8f32, + loadv4f32, loadv8f32, SchedWriteFMA>; + defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", X86Fmaddsub, v4f32, v8f32, + loadv4f32, loadv8f32, SchedWriteFMA>; + defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", X86Fmsubadd, v4f32, v8f32, + loadv4f32, loadv8f32, SchedWriteFMA>; +} + +let ExeDomain = SSEPackedDouble in { + // Scalar Instructions + defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", FR64, f64mem, f64, X86Fmadd, loadf64, + SchedWriteFMA.Scl>, + fma4s_int<0x6B, "vfmaddsd", sdmem, v2f64, + SchedWriteFMA.Scl>; + defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", FR64, f64mem, f64, X86Fmsub, loadf64, + SchedWriteFMA.Scl>, + fma4s_int<0x6F, "vfmsubsd", sdmem, v2f64, + SchedWriteFMA.Scl>; + defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", FR64, f64mem, f64, + X86Fnmadd, loadf64, SchedWriteFMA.Scl>, + fma4s_int<0x7B, "vfnmaddsd", sdmem, v2f64, + SchedWriteFMA.Scl>; + defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", FR64, f64mem, f64, + X86Fnmsub, loadf64, SchedWriteFMA.Scl>, + fma4s_int<0x7F, "vfnmsubsd", sdmem, v2f64, + SchedWriteFMA.Scl>; + // Packed Instructions + defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", X86Fmadd, v2f64, v4f64, + loadv2f64, loadv4f64, SchedWriteFMA>; + defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86Fmsub, v2f64, v4f64, + loadv2f64, loadv4f64, SchedWriteFMA>; + defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86Fnmadd, v2f64, v4f64, + loadv2f64, loadv4f64, SchedWriteFMA>; + defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86Fnmsub, v2f64, v4f64, + loadv2f64, loadv4f64, SchedWriteFMA>; + defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", X86Fmaddsub, v2f64, v4f64, + loadv2f64, loadv4f64, SchedWriteFMA>; + defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", X86Fmsubadd, v2f64, v4f64, + loadv2f64, loadv4f64, SchedWriteFMA>; +} + +multiclass scalar_fma4_patterns { + let Predicates = [HasFMA4] in { + def : Pat<(VT (X86vzmovl (VT (scalar_to_vector + (Op RC:$src1, RC:$src2, RC:$src3))))), + (!cast(Name#"rr_Int") + (VT (COPY_TO_REGCLASS RC:$src1, VR128)), + (VT (COPY_TO_REGCLASS RC:$src2, VR128)), + (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>; + + def : Pat<(VT (X86vzmovl (VT (scalar_to_vector + (Op RC:$src1, RC:$src2, + (mem_frag addr:$src3)))))), + (!cast(Name#"rm_Int") + (VT (COPY_TO_REGCLASS RC:$src1, VR128)), + (VT (COPY_TO_REGCLASS RC:$src2, VR128)), addr:$src3)>; + + def : Pat<(VT (X86vzmovl (VT (scalar_to_vector + (Op RC:$src1, (mem_frag addr:$src2), + RC:$src3))))), + (!cast(Name#"mr_Int") + (VT (COPY_TO_REGCLASS RC:$src1, VR128)), addr:$src2, + (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>; + } +} + +defm : scalar_fma4_patterns; +defm : scalar_fma4_patterns; +defm : scalar_fma4_patterns; +defm : scalar_fma4_patterns; + +defm : scalar_fma4_patterns; +defm : scalar_fma4_patterns; +defm : scalar_fma4_patterns; +defm : scalar_fma4_patterns; -- cgit