From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001
From: Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com>
Date: Tue, 10 Oct 2023 14:33:42 +0000
Subject: Add submodule dependency files

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
---
 .../MdePkg/Library/BaseLib/Ia32/EnableCache.nasm   | 36 ++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.nasm

(limited to 'roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.nasm')

diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.nasm
new file mode 100644
index 000000000..02ed72921
--- /dev/null
+++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.nasm
@@ -0,0 +1,36 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+;   EnableCache.Asm
+;
+; Abstract:
+;
+;  Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear
+;  the NW bit of CR0 to 0
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+    SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmEnableCache (
+;   VOID
+;   );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmEnableCache)
+ASM_PFX(AsmEnableCache):
+    wbinvd
+    mov     eax, cr0
+    btr     eax, 29
+    btr     eax, 30
+    mov     cr0, eax
+    ret
+
-- 
cgit