From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001 From: Angelos Mouzakitis Date: Tue, 10 Oct 2023 14:33:42 +0000 Subject: Add submodule dependency files Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec --- roms/edk2/MdePkg/Library/BaseLib/Ia32/ARShiftU64.c | 45 + .../MdePkg/Library/BaseLib/Ia32/ARShiftU64.nasm | 39 + .../MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.c | 35 + .../MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.nasm | 30 + roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuId.c | 68 ++ roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuId.nasm | 59 + roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuIdEx.c | 76 ++ roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuIdEx.nasm | 61 + roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuPause.c | 29 + .../edk2/MdePkg/Library/BaseLib/Ia32/CpuPause.nasm | 30 + .../MdePkg/Library/BaseLib/Ia32/DisableCache.c | 30 + .../MdePkg/Library/BaseLib/Ia32/DisableCache.nasm | 36 + .../Library/BaseLib/Ia32/DisableInterrupts.c | 26 + .../Library/BaseLib/Ia32/DisableInterrupts.nasm | 31 + .../MdePkg/Library/BaseLib/Ia32/DisablePaging32.c | 71 ++ .../Library/BaseLib/Ia32/DisablePaging32.nasm | 48 + .../Library/BaseLib/Ia32/DivS64x64Remainder.c | 47 + roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32.c | 44 + .../MdePkg/Library/BaseLib/Ia32/DivU64x32.nasm | 37 + .../Library/BaseLib/Ia32/DivU64x32Remainder.c | 49 + .../Library/BaseLib/Ia32/DivU64x32Remainder.nasm | 42 + .../Library/BaseLib/Ia32/DivU64x64Remainder.nasm | 88 ++ .../edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.c | 30 + .../MdePkg/Library/BaseLib/Ia32/EnableCache.nasm | 36 + .../Library/BaseLib/Ia32/EnableDisableInterrupts.c | 30 + .../BaseLib/Ia32/EnableDisableInterrupts.nasm | 32 + .../MdePkg/Library/BaseLib/Ia32/EnableInterrupts.c | 26 + .../Library/BaseLib/Ia32/EnableInterrupts.nasm | 31 + .../MdePkg/Library/BaseLib/Ia32/EnablePaging32.c | 75 ++ .../Library/BaseLib/Ia32/EnablePaging32.nasm | 48 + .../Library/BaseLib/Ia32/EnablePaging64.nasm | 59 + .../MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c | 52 + .../Library/BaseLib/Ia32/FlushCacheLine.nasm | 45 + roms/edk2/MdePkg/Library/BaseLib/Ia32/FxRestore.c | 34 + .../MdePkg/Library/BaseLib/Ia32/FxRestore.nasm | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/FxSave.c | 34 + roms/edk2/MdePkg/Library/BaseLib/Ia32/FxSave.nasm | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/GccInline.c | 586 ++++++++++ .../MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c | 1170 ++++++++++++++++++++ .../Library/BaseLib/Ia32/InternalSwitchStack.c | 54 + .../Library/BaseLib/Ia32/InternalSwitchStack.nasm | 41 + roms/edk2/MdePkg/Library/BaseLib/Ia32/Invd.c | 29 + roms/edk2/MdePkg/Library/BaseLib/Ia32/Invd.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/LRotU64.c | 49 + roms/edk2/MdePkg/Library/BaseLib/Ia32/LRotU64.nasm | 44 + roms/edk2/MdePkg/Library/BaseLib/Ia32/LShiftU64.c | 45 + .../MdePkg/Library/BaseLib/Ia32/LShiftU64.nasm | 39 + roms/edk2/MdePkg/Library/BaseLib/Ia32/Lfence.nasm | 30 + .../edk2/MdePkg/Library/BaseLib/Ia32/LongJump.nasm | 60 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ModU64x32.c | 42 + .../MdePkg/Library/BaseLib/Ia32/ModU64x32.nasm | 36 + roms/edk2/MdePkg/Library/BaseLib/Ia32/Monitor.c | 42 + roms/edk2/MdePkg/Library/BaseLib/Ia32/Monitor.nasm | 36 + roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x32.c | 41 + .../MdePkg/Library/BaseLib/Ia32/MultU64x32.nasm | 34 + roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x64.c | 45 + .../MdePkg/Library/BaseLib/Ia32/MultU64x64.nasm | 40 + roms/edk2/MdePkg/Library/BaseLib/Ia32/Mwait.c | 38 + roms/edk2/MdePkg/Library/BaseLib/Ia32/Mwait.nasm | 34 + .../MdePkg/Library/BaseLib/Ia32/Non-existing.c | 51 + roms/edk2/MdePkg/Library/BaseLib/Ia32/RRotU64.c | 49 + roms/edk2/MdePkg/Library/BaseLib/Ia32/RRotU64.nasm | 44 + roms/edk2/MdePkg/Library/BaseLib/Ia32/RShiftU64.c | 45 + .../MdePkg/Library/BaseLib/Ia32/RShiftU64.nasm | 39 + roms/edk2/MdePkg/Library/BaseLib/Ia32/RdRand.nasm | 84 ++ roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr0.c | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr0.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr2.c | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr2.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr3.c | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr3.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr4.c | 34 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr4.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCs.c | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCs.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr0.c | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr0.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr1.c | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr1.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr2.c | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr2.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr3.c | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr3.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr4.c | 34 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm | 38 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr5.c | 34 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm | 38 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr6.c | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr6.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr7.c | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr7.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDs.c | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDs.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEflags.c | 33 + .../MdePkg/Library/BaseLib/Ia32/ReadEflags.nasm | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEs.c | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEs.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadFs.c | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadFs.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGdtr.c | 33 + .../edk2/MdePkg/Library/BaseLib/Ia32/ReadGdtr.nasm | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGs.c | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGs.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadIdtr.c | 32 + .../edk2/MdePkg/Library/BaseLib/Ia32/ReadIdtr.nasm | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadLdtr.c | 31 + .../edk2/MdePkg/Library/BaseLib/Ia32/ReadLdtr.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm0.c | 36 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm0.nasm | 35 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm1.c | 36 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm1.nasm | 35 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm2.c | 36 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm2.nasm | 35 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm3.c | 36 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm3.nasm | 35 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm4.c | 36 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm4.nasm | 35 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm5.c | 36 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm5.nasm | 35 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm6.c | 36 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm6.nasm | 35 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm7.c | 36 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm7.nasm | 35 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c | 37 + .../MdePkg/Library/BaseLib/Ia32/ReadMsr64.nasm | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadPmc.c | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadPmc.nasm | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadSs.c | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadSs.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTr.c | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTr.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTsc.c | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTsc.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/SetJump.nasm | 63 ++ .../edk2/MdePkg/Library/BaseLib/Ia32/SwapBytes64.c | 37 + .../MdePkg/Library/BaseLib/Ia32/SwapBytes64.nasm | 34 + roms/edk2/MdePkg/Library/BaseLib/Ia32/Thunk16.nasm | 257 +++++ roms/edk2/MdePkg/Library/BaseLib/Ia32/VmgExit.nasm | 38 + roms/edk2/MdePkg/Library/BaseLib/Ia32/Wbinvd.c | 29 + roms/edk2/MdePkg/Library/BaseLib/Ia32/Wbinvd.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr0.c | 31 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteCr0.nasm | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr2.c | 31 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteCr2.nasm | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr3.c | 31 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteCr3.nasm | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr4.c | 33 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteCr4.nasm | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr0.c | 31 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteDr0.nasm | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr1.c | 31 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteDr1.nasm | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr2.c | 31 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteDr2.nasm | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr3.c | 31 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteDr3.nasm | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr4.c | 33 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm | 39 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr5.c | 33 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm | 39 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr6.c | 31 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteDr6.nasm | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr7.c | 31 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteDr7.nasm | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteGdtr.c | 33 + .../MdePkg/Library/BaseLib/Ia32/WriteGdtr.nasm | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteIdtr.c | 35 + .../MdePkg/Library/BaseLib/Ia32/WriteIdtr.nasm | 35 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteLdtr.c | 33 + .../MdePkg/Library/BaseLib/Ia32/WriteLdtr.nasm | 32 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm0.c | 32 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteMm0.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm1.c | 32 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteMm1.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm2.c | 32 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteMm2.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm3.c | 32 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteMm3.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm4.c | 31 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteMm4.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm5.c | 31 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteMm5.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm6.c | 32 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteMm6.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm7.c | 32 + .../edk2/MdePkg/Library/BaseLib/Ia32/WriteMm7.nasm | 31 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMsr64.c | 43 + .../MdePkg/Library/BaseLib/Ia32/WriteMsr64.nasm | 35 + roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteTr.nasm | 30 + roms/edk2/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm | 31 + 190 files changed, 8834 insertions(+) create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ARShiftU64.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ARShiftU64.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuId.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuId.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuIdEx.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuIdEx.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuPause.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuPause.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableCache.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableCache.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableInterrupts.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableInterrupts.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/DisablePaging32.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/DisablePaging32.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/DivS64x64Remainder.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x64Remainder.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableInterrupts.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableInterrupts.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging32.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging32.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/FxRestore.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/FxRestore.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/FxSave.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/FxSave.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/GccInline.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/Invd.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/Invd.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/LRotU64.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/LRotU64.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/LShiftU64.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/LShiftU64.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/Lfence.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/LongJump.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ModU64x32.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ModU64x32.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/Monitor.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/Monitor.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x32.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x32.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x64.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x64.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/Mwait.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/Mwait.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/Non-existing.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/RRotU64.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/RRotU64.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/RShiftU64.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/RShiftU64.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/RdRand.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr0.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr0.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr2.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr2.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr3.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr3.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr4.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr4.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCs.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCs.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr0.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr0.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr1.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr1.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr2.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr2.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr3.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr3.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr4.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr5.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr6.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr6.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr7.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr7.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDs.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDs.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEflags.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEflags.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEs.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEs.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadFs.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadFs.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGdtr.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGdtr.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGs.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGs.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadIdtr.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadIdtr.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadLdtr.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadLdtr.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm0.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm0.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm1.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm1.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm2.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm2.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm3.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm3.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm4.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm4.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm5.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm5.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm6.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm6.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm7.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm7.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMsr64.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadPmc.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadPmc.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadSs.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadSs.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTr.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTr.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTsc.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTsc.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/SetJump.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/SwapBytes64.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/SwapBytes64.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/Thunk16.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/VmgExit.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/Wbinvd.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/Wbinvd.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr0.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr0.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr2.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr2.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr3.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr3.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr4.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr4.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr0.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr0.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr1.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr1.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr2.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr2.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr3.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr3.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr4.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr5.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr6.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr6.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr7.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr7.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteGdtr.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteGdtr.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteIdtr.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteIdtr.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteLdtr.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteLdtr.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm0.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm0.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm1.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm1.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm2.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm2.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm3.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm3.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm4.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm4.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm5.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm5.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm6.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm6.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm7.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm7.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMsr64.c create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMsr64.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteTr.nasm create mode 100644 roms/edk2/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm (limited to 'roms/edk2/MdePkg/Library/BaseLib/Ia32') diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ARShiftU64.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ARShiftU64.c new file mode 100644 index 000000000..836108364 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ARShiftU64.c @@ -0,0 +1,45 @@ +/** @file + 64-bit arithmetic right shift function for IA-32. + + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Shifts a 64-bit integer right between 0 and 63 bits. The high bits + are filled with original integer's bit 63. The shifted value is returned. + + This function shifts the 64-bit value Operand to the right by Count bits. The + high Count bits are set to bit 63 of Operand. The shifted value is returned. + + @param Operand The 64-bit operand to shift right. + @param Count The number of bits to shift right. + + @return Operand arithmetically shifted right by Count. + +**/ +UINT64 +EFIAPI +InternalMathARShiftU64 ( + IN UINT64 Operand, + IN UINTN Count + ) +{ + _asm { + mov cl, byte ptr [Count] + mov eax, dword ptr [Operand + 4] + cdq + test cl, 32 + jnz L0 + mov edx, eax + mov eax, dword ptr [Operand + 0] +L0: + shrd eax, edx, cl + sar edx, cl + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ARShiftU64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ARShiftU64.nasm new file mode 100644 index 000000000..94aa88229 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ARShiftU64.nasm @@ -0,0 +1,39 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ARShiftU64.nasm +; +; Abstract: +; +; 64-bit arithmetic right shift function for IA-32 +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; InternalMathARShiftU64 ( +; IN UINT64 Operand, +; IN UINTN Count +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalMathARShiftU64) +ASM_PFX(InternalMathARShiftU64): + mov cl, [esp + 12] + mov eax, [esp + 8] + cdq + test cl, 32 + jnz .0 + mov edx, eax + mov eax, [esp + 4] +.0: + shrd eax, edx, cl + sar edx, cl + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.c new file mode 100644 index 000000000..a59da0cee --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.c @@ -0,0 +1,35 @@ +/** @file + CpuBreakpoint function. + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics. +**/ + +void __debugbreak (VOID); + +#pragma intrinsic(__debugbreak) + +/** + Generates a breakpoint on the CPU. + + Generates a breakpoint on the CPU. The breakpoint must be implemented such + that code can resume normal execution after the breakpoint. + +**/ +VOID +EFIAPI +CpuBreakpoint ( + VOID + ) +{ + __debugbreak (); +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.nasm new file mode 100644 index 000000000..a62e4f5c3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.nasm @@ -0,0 +1,30 @@ +;------------------------------------------------------------------------------ ; +; Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; CpuBreakpoint.Asm +; +; Abstract: +; +; CpuBreakpoint function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; CpuBreakpoint ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(CpuBreakpoint) +ASM_PFX(CpuBreakpoint): + int 3 + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuId.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuId.c new file mode 100644 index 000000000..bcb0fa78f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuId.c @@ -0,0 +1,68 @@ +/** @file + AsmCpuid function. + + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Retrieves CPUID information. + + Executes the CPUID instruction with EAX set to the value specified by Index. + This function always returns Index. + If Eax is not NULL, then the value of EAX after CPUID is returned in Eax. + If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx. + If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx. + If Edx is not NULL, then the value of EDX after CPUID is returned in Edx. + This function is only available on IA-32 and x64. + + @param Index The 32-bit value to load into EAX prior to invoking the CPUID + instruction. + @param RegisterEax A pointer to the 32-bit EAX value returned by the CPUID + instruction. This is an optional parameter that may be NULL. + @param RegisterEbx A pointer to the 32-bit EBX value returned by the CPUID + instruction. This is an optional parameter that may be NULL. + @param RegisterEcx A pointer to the 32-bit ECX value returned by the CPUID + instruction. This is an optional parameter that may be NULL. + @param RegisterEdx A pointer to the 32-bit EDX value returned by the CPUID + instruction. This is an optional parameter that may be NULL. + + @return Index. + +**/ +UINT32 +EFIAPI +AsmCpuid ( + IN UINT32 Index, + OUT UINT32 *RegisterEax, OPTIONAL + OUT UINT32 *RegisterEbx, OPTIONAL + OUT UINT32 *RegisterEcx, OPTIONAL + OUT UINT32 *RegisterEdx OPTIONAL + ) +{ + _asm { + mov eax, Index + cpuid + push ecx + mov ecx, RegisterEax + jecxz SkipEax + mov [ecx], eax +SkipEax: + mov ecx, RegisterEbx + jecxz SkipEbx + mov [ecx], ebx +SkipEbx: + pop eax + mov ecx, RegisterEcx + jecxz SkipEcx + mov [ecx], eax +SkipEcx: + mov ecx, RegisterEdx + jecxz SkipEdx + mov [ecx], edx +SkipEdx: + mov eax, Index + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuId.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuId.nasm new file mode 100644 index 000000000..d38135fcd --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuId.nasm @@ -0,0 +1,59 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; CpuId.Asm +; +; Abstract: +; +; AsmCpuid function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmCpuid ( +; IN UINT32 RegisterInEax, +; OUT UINT32 *RegisterOutEax OPTIONAL, +; OUT UINT32 *RegisterOutEbx OPTIONAL, +; OUT UINT32 *RegisterOutEcx OPTIONAL, +; OUT UINT32 *RegisterOutEdx OPTIONAL +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmCpuid) +ASM_PFX(AsmCpuid): + push ebx + push ebp + mov ebp, esp + mov eax, [ebp + 12] + cpuid + push ecx + mov ecx, [ebp + 16] + jecxz .0 + mov [ecx], eax +.0: + mov ecx, [ebp + 20] + jecxz .1 + mov [ecx], ebx +.1: + mov ecx, [ebp + 24] + jecxz .2 + pop DWORD [ecx] +.2: + mov ecx, [ebp + 28] + jecxz .3 + mov [ecx], edx +.3: + mov eax, [ebp + 12] + leave + pop ebx + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuIdEx.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuIdEx.c new file mode 100644 index 000000000..b537182a6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuIdEx.c @@ -0,0 +1,76 @@ +/** @file + AsmCpuidEx function. + + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Retrieves CPUID information using an extended leaf identifier. + + Executes the CPUID instruction with EAX set to the value specified by Index + and ECX set to the value specified by SubIndex. This function always returns + Index. This function is only available on IA-32 and x64. + + If Eax is not NULL, then the value of EAX after CPUID is returned in Eax. + If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx. + If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx. + If Edx is not NULL, then the value of EDX after CPUID is returned in Edx. + + @param Index The 32-bit value to load into EAX prior to invoking the + CPUID instruction. + @param SubIndex The 32-bit value to load into ECX prior to invoking the + CPUID instruction. + @param RegisterEax A pointer to the 32-bit EAX value returned by the CPUID + instruction. This is an optional parameter that may be + NULL. + @param RegisterEbx A pointer to the 32-bit EBX value returned by the CPUID + instruction. This is an optional parameter that may be + NULL. + @param RegisterEcx A pointer to the 32-bit ECX value returned by the CPUID + instruction. This is an optional parameter that may be + NULL. + @param RegisterEdx A pointer to the 32-bit EDX value returned by the CPUID + instruction. This is an optional parameter that may be + NULL. + + @return Index. + +**/ +UINT32 +EFIAPI +AsmCpuidEx ( + IN UINT32 Index, + IN UINT32 SubIndex, + OUT UINT32 *RegisterEax, OPTIONAL + OUT UINT32 *RegisterEbx, OPTIONAL + OUT UINT32 *RegisterEcx, OPTIONAL + OUT UINT32 *RegisterEdx OPTIONAL + ) +{ + _asm { + mov eax, Index + mov ecx, SubIndex + cpuid + push ecx + mov ecx, RegisterEax + jecxz SkipEax + mov [ecx], eax +SkipEax: + mov ecx, RegisterEbx + jecxz SkipEbx + mov [ecx], ebx +SkipEbx: + pop eax + mov ecx, RegisterEcx + jecxz SkipEcx + mov [ecx], eax +SkipEcx: + mov ecx, RegisterEdx + jecxz SkipEdx + mov [ecx], edx +SkipEdx: + mov eax, Index + } +} diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuIdEx.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuIdEx.nasm new file mode 100644 index 000000000..f381069c6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuIdEx.nasm @@ -0,0 +1,61 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; CpuIdEx.Asm +; +; Abstract: +; +; AsmCpuidEx function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT32 +; EFIAPI +; AsmCpuidEx ( +; IN UINT32 RegisterInEax, +; IN UINT32 RegisterInEcx, +; OUT UINT32 *RegisterOutEax OPTIONAL, +; OUT UINT32 *RegisterOutEbx OPTIONAL, +; OUT UINT32 *RegisterOutEcx OPTIONAL, +; OUT UINT32 *RegisterOutEdx OPTIONAL +; ) +;------------------------------------------------------------------------------ +global ASM_PFX(AsmCpuidEx) +ASM_PFX(AsmCpuidEx): + push ebx + push ebp + mov ebp, esp + mov eax, [ebp + 12] + mov ecx, [ebp + 16] + cpuid + push ecx + mov ecx, [ebp + 20] + jecxz .0 + mov [ecx], eax +.0: + mov ecx, [ebp + 24] + jecxz .1 + mov [ecx], ebx +.1: + mov ecx, [ebp + 32] + jecxz .2 + mov [ecx], edx +.2: + mov ecx, [ebp + 28] + jecxz .3 + pop DWORD [ecx] +.3: + mov eax, [ebp + 12] + leave + pop ebx + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuPause.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuPause.c new file mode 100644 index 000000000..12dc896fe --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuPause.c @@ -0,0 +1,29 @@ +/** @file + CpuPause function. + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Requests CPU to pause for a short period of time. + + Requests CPU to pause for a short period of time. Typically used in MP + systems to prevent memory starvation while waiting for a spin lock. + +**/ +VOID +EFIAPI +CpuPause ( + VOID + ) +{ + _asm { + pause + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuPause.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuPause.nasm new file mode 100644 index 000000000..8fac8c518 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuPause.nasm @@ -0,0 +1,30 @@ +;------------------------------------------------------------------------------ ; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; CpuPause.Asm +; +; Abstract: +; +; CpuPause function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; CpuPause ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(CpuPause) +ASM_PFX(CpuPause): + pause + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableCache.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableCache.c new file mode 100644 index 000000000..6a8be4ef2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableCache.c @@ -0,0 +1,30 @@ +/** @file + AsmDisableCache function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Set CD bit and clear NW bit of CR0 followed by a WBINVD. + + Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0, + and executing a WBINVD instruction. This function is only available on IA-32 and x64. + +**/ +VOID +EFIAPI +AsmDisableCache ( + VOID + ) +{ + _asm { + mov eax, cr0 + bts eax, 30 + btr eax, 29 + mov cr0, eax + wbinvd + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableCache.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableCache.nasm new file mode 100644 index 000000000..c379e4a6b --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableCache.nasm @@ -0,0 +1,36 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; DisableCache.Asm +; +; Abstract: +; +; Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a +; WBINVD instruction. +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmDisableCache ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmDisableCache) +ASM_PFX(AsmDisableCache): + mov eax, cr0 + bts eax, 30 + btr eax, 29 + mov cr0, eax + wbinvd + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableInterrupts.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableInterrupts.c new file mode 100644 index 000000000..4141ef751 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableInterrupts.c @@ -0,0 +1,26 @@ +/** @file + DisableInterrupts function. + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Disables CPU interrupts. + +**/ +VOID +EFIAPI +DisableInterrupts ( + VOID + ) +{ + _asm { + cli + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableInterrupts.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableInterrupts.nasm new file mode 100644 index 000000000..ed73f66be --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableInterrupts.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; DisableInterrupts.Asm +; +; Abstract: +; +; DisableInterrupts function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; DisableInterrupts ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(DisableInterrupts) +ASM_PFX(DisableInterrupts): + cli + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisablePaging32.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisablePaging32.c new file mode 100644 index 000000000..12ee87413 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisablePaging32.c @@ -0,0 +1,71 @@ +/** @file + AsmDisablePaging32 function. + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "BaseLibInternals.h" + +/** + Disables the 32-bit paging mode on the CPU. + + Disables the 32-bit paging mode on the CPU and returns to 32-bit protected + mode. This function assumes the current execution mode is 32-paged protected + mode. This function is only available on IA-32. After the 32-bit paging mode + is disabled, control is transferred to the function specified by EntryPoint + using the new stack specified by NewStack and passing in the parameters + specified by Context1 and Context2. Context1 and Context2 are optional and + may be NULL. The function EntryPoint must never return. + + There are a number of constraints that must be followed before calling this + function: + 1) Interrupts must be disabled. + 2) The caller must be in 32-bit paged mode. + 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode. + 4) CR3 must point to valid page tables that guarantee that the pages for + this function and the stack are identity mapped. + + @param EntryPoint A pointer to function to call with the new stack after + paging is disabled. + @param Context1 A pointer to the context to pass into the EntryPoint + function as the first parameter after paging is disabled. + @param Context2 A pointer to the context to pass into the EntryPoint + function as the second parameter after paging is + disabled. + @param NewStack A pointer to the new stack to use for the EntryPoint + function after paging is disabled. + +**/ +__declspec (naked) +VOID +EFIAPI +InternalX86DisablePaging32 ( + IN SWITCH_STACK_ENTRY_POINT EntryPoint, + IN VOID *Context1, OPTIONAL + IN VOID *Context2, OPTIONAL + IN VOID *NewStack + ) +{ + _asm { + push ebp + mov ebp, esp + mov ebx, EntryPoint + mov ecx, Context1 + mov edx, Context2 + pushfd + pop edi // save EFLAGS to edi + cli + mov eax, cr0 + btr eax, 31 + mov esp, NewStack + mov cr0, eax + push edi + popfd // restore EFLAGS from edi + push edx + push ecx + call ebx + jmp $ // EntryPoint() should not return + } +} diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisablePaging32.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisablePaging32.nasm new file mode 100644 index 000000000..0cab3304a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisablePaging32.nasm @@ -0,0 +1,48 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; DisablePaging32.Asm +; +; Abstract: +; +; AsmDisablePaging32 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; InternalX86DisablePaging32 ( +; IN SWITCH_STACK_ENTRY_POINT EntryPoint, +; IN VOID *Context1, OPTIONAL +; IN VOID *Context2, OPTIONAL +; IN VOID *NewStack +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalX86DisablePaging32) +ASM_PFX(InternalX86DisablePaging32): + mov ebx, [esp + 4] + mov ecx, [esp + 8] + mov edx, [esp + 12] + pushfd + pop edi ; save EFLAGS to edi + cli + mov eax, cr0 + btr eax, 31 + mov esp, [esp + 16] + mov cr0, eax + push edi + popfd ; restore EFLAGS from edi + push edx + push ecx + call ebx + jmp $ ; EntryPoint() should not return + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivS64x64Remainder.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivS64x64Remainder.c new file mode 100644 index 000000000..4e6496404 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivS64x64Remainder.c @@ -0,0 +1,47 @@ +/** @file + Integer division worker functions for Ia32. + + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "BaseLibInternals.h" + +/** + Worker function that Divides a 64-bit signed integer by a 64-bit signed integer and + generates a 64-bit signed result and a optional 64-bit signed remainder. + + This function divides the 64-bit signed value Dividend by the 64-bit + signed value Divisor and generates a 64-bit signed quotient. If Remainder + is not NULL, then the 64-bit signed remainder is returned in Remainder. + This function returns the 64-bit signed quotient. + + @param Dividend A 64-bit signed value. + @param Divisor A 64-bit signed value. + @param Remainder A pointer to a 64-bit signed value. This parameter is + optional and may be NULL. + + @return Dividend / Divisor + +**/ +INT64 +EFIAPI +InternalMathDivRemS64x64 ( + IN INT64 Dividend, + IN INT64 Divisor, + OUT INT64 *Remainder OPTIONAL + ) +{ + INT64 Quot; + + Quot = InternalMathDivRemU64x64 ( + (UINT64) (Dividend >= 0 ? Dividend : -Dividend), + (UINT64) (Divisor >= 0 ? Divisor : -Divisor), + (UINT64 *) Remainder + ); + if (Remainder != NULL && Dividend < 0) { + *Remainder = -*Remainder; + } + return (Dividend ^ Divisor) >= 0 ? Quot : -Quot; +} diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32.c new file mode 100644 index 000000000..538f77a83 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32.c @@ -0,0 +1,44 @@ +/** @file + Calculate the quotient of a 64-bit integer by a 32-bit integer + + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Divides a 64-bit unsigned integer by a 32-bit unsigned integer and + generates a 64-bit unsigned result. + + This function divides the 64-bit unsigned value Dividend by the 32-bit + unsigned value Divisor and generates a 64-bit unsigned quotient. This + function returns the 64-bit unsigned quotient. + + @param Dividend A 64-bit unsigned value. + @param Divisor A 32-bit unsigned value. + + @return Dividend / Divisor + +**/ +UINT64 +EFIAPI +InternalMathDivU64x32 ( + IN UINT64 Dividend, + IN UINT32 Divisor + ) +{ + _asm { + mov eax, dword ptr [Dividend + 4] + mov ecx, Divisor + xor edx, edx + div ecx + push eax ; save quotient on stack + mov eax, dword ptr [Dividend] + div ecx + pop edx ; restore high-order dword of the quotient + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32.nasm new file mode 100644 index 000000000..d462119d4 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32.nasm @@ -0,0 +1,37 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; DivU64x32.nasm +; +; Abstract: +; +; Calculate the quotient of a 64-bit integer by a 32-bit integer +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; InternalMathDivU64x32 ( +; IN UINT64 Dividend, +; IN UINT32 Divisor +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalMathDivU64x32) +ASM_PFX(InternalMathDivU64x32): + mov eax, [esp + 8] + mov ecx, [esp + 12] + xor edx, edx + div ecx + push eax ; save quotient on stack + mov eax, [esp + 8] + div ecx + pop edx ; restore high-order dword of the quotient + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.c new file mode 100644 index 000000000..035d4340d --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.c @@ -0,0 +1,49 @@ +/** @file + Set error flag for all division functions + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Divides a 64-bit unsigned integer by a 32-bit unsigned integer and + generates a 64-bit unsigned result and an optional 32-bit unsigned remainder. + + This function divides the 64-bit unsigned value Dividend by the 32-bit + unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder + is not NULL, then the 32-bit unsigned remainder is returned in Remainder. + This function returns the 64-bit unsigned quotient. + + @param Dividend A 64-bit unsigned value. + @param Divisor A 32-bit unsigned value. + @param Remainder A pointer to a 32-bit unsigned value. This parameter is + optional and may be NULL. + + @return Dividend / Divisor + +**/ +UINT64 +EFIAPI +InternalMathDivRemU64x32 ( + IN UINT64 Dividend, + IN UINT32 Divisor, + OUT UINT32 *Remainder + ) +{ + _asm { + mov ecx, Divisor + mov eax, dword ptr [Dividend + 4] + xor edx, edx + div ecx + push eax + mov eax, dword ptr [Dividend + 0] + div ecx + mov ecx, Remainder + jecxz RemainderNull // abandon remainder if Remainder == NULL + mov [ecx], edx +RemainderNull: + pop edx + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.nasm new file mode 100644 index 000000000..944ba73f1 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.nasm @@ -0,0 +1,42 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; DivError.asm +; +; Abstract: +; +; Set error flag for all division functions +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; InternalMathDivRemU64x32 ( +; IN UINT64 Dividend, +; IN UINT32 Divisor, +; OUT UINT32 *Remainder +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalMathDivRemU64x32) +ASM_PFX(InternalMathDivRemU64x32): + mov ecx, [esp + 12] ; ecx <- divisor + mov eax, [esp + 8] ; eax <- dividend[32..63] + xor edx, edx + div ecx ; eax <- quotient[32..63], edx <- remainder + push eax + mov eax, [esp + 8] ; eax <- dividend[0..31] + div ecx ; eax <- quotient[0..31] + mov ecx, [esp + 20] ; ecx <- Remainder + jecxz .0 ; abandon remainder if Remainder == NULL + mov [ecx], edx +.0: + pop edx ; edx <- quotient[32..63] + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x64Remainder.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x64Remainder.nasm new file mode 100644 index 000000000..0adb07f73 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x64Remainder.nasm @@ -0,0 +1,88 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; DivU64x64Remainder.nasm +; +; Abstract: +; +; Calculate the quotient of a 64-bit integer by a 64-bit integer and returns +; both the quotient and the remainder +; +;------------------------------------------------------------------------------ + + SECTION .text + +extern ASM_PFX(InternalMathDivRemU64x32) + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; InternalMathDivRemU64x64 ( +; IN UINT64 Dividend, +; IN UINT64 Divisor, +; OUT UINT64 *Remainder OPTIONAL +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalMathDivRemU64x64) +ASM_PFX(InternalMathDivRemU64x64): + mov ecx, [esp + 16] ; ecx <- divisor[32..63] + test ecx, ecx + jnz _@DivRemU64x64 ; call _@DivRemU64x64 if Divisor > 2^32 + mov ecx, [esp + 20] + jecxz .0 + and dword [ecx + 4], 0 ; zero high dword of remainder + mov [esp + 16], ecx ; set up stack frame to match DivRemU64x32 +.0: + jmp ASM_PFX(InternalMathDivRemU64x32) + +_@DivRemU64x64: + push ebx + push esi + push edi + mov edx, dword [esp + 20] + mov eax, dword [esp + 16] ; edx:eax <- dividend + mov edi, edx + mov esi, eax ; edi:esi <- dividend + mov ebx, dword [esp + 24] ; ecx:ebx <- divisor +.1: + shr edx, 1 + rcr eax, 1 + shrd ebx, ecx, 1 + shr ecx, 1 + jnz .1 + div ebx + mov ebx, eax ; ebx <- quotient + mov ecx, [esp + 28] ; ecx <- high dword of divisor + mul dword [esp + 24] ; edx:eax <- quotient * divisor[0..31] + imul ecx, ebx ; ecx <- quotient * divisor[32..63] + add edx, ecx ; edx <- (quotient * divisor)[32..63] + mov ecx, dword [esp + 32] ; ecx <- addr for Remainder + jc @TooLarge ; product > 2^64 + cmp edi, edx ; compare high 32 bits + ja @Correct + jb @TooLarge ; product > dividend + cmp esi, eax + jae @Correct ; product <= dividend +@TooLarge: + dec ebx ; adjust quotient by -1 + jecxz @Return ; return if Remainder == NULL + sub eax, dword [esp + 24] + sbb edx, dword [esp + 28] ; edx:eax <- (quotient - 1) * divisor +@Correct: + jecxz @Return + sub esi, eax + sbb edi, edx ; edi:esi <- remainder + mov [ecx], esi + mov [ecx + 4], edi +@Return: + mov eax, ebx ; eax <- quotient + xor edx, edx ; quotient is 32 bits long + pop edi + pop esi + pop ebx + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.c new file mode 100644 index 000000000..4f5c6e9ab --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.c @@ -0,0 +1,30 @@ +/** @file + AsmEnableCache function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Perform a WBINVD and clear both the CD and NW bits of CR0. + + Enables the caches by executing a WBINVD instruction and then clear both the CD and NW + bits of CR0 to 0. This function is only available on IA-32 and x64. + +**/ +VOID +EFIAPI +AsmEnableCache ( + VOID + ) +{ + _asm { + wbinvd + mov eax, cr0 + btr eax, 30 + btr eax, 29 + mov cr0, eax + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.nasm new file mode 100644 index 000000000..02ed72921 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.nasm @@ -0,0 +1,36 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; EnableCache.Asm +; +; Abstract: +; +; Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear +; the NW bit of CR0 to 0 +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmEnableCache ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmEnableCache) +ASM_PFX(AsmEnableCache): + wbinvd + mov eax, cr0 + btr eax, 29 + btr eax, 30 + mov cr0, eax + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.c new file mode 100644 index 000000000..7ec62147f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.c @@ -0,0 +1,30 @@ +/** @file + EnableDisableInterrupts function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Enables CPU interrupts for the smallest window required to capture any + pending interrupts. + +**/ +VOID +EFIAPI +EnableDisableInterrupts ( + VOID + ) +{ + _asm { + sti + nop + nop + cli + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.nasm new file mode 100644 index 000000000..2da094f0d --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; EnableDisableInterrupts.Asm +; +; Abstract: +; +; EnableDisableInterrupts function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; EnableDisableInterrupts ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(EnableDisableInterrupts) +ASM_PFX(EnableDisableInterrupts): + sti + cli + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableInterrupts.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableInterrupts.c new file mode 100644 index 000000000..bc03144c4 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableInterrupts.c @@ -0,0 +1,26 @@ +/** @file + EnableInterrupts function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Enables CPU interrupts. + +**/ +VOID +EFIAPI +EnableInterrupts ( + VOID + ) +{ + _asm { + sti + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableInterrupts.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableInterrupts.nasm new file mode 100644 index 000000000..979e70820 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableInterrupts.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; EnableInterrupts.Asm +; +; Abstract: +; +; EnableInterrupts function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; EnableInterrupts ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(EnableInterrupts) +ASM_PFX(EnableInterrupts): + sti + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging32.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging32.c new file mode 100644 index 000000000..ce0c71067 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging32.c @@ -0,0 +1,75 @@ +/** @file + AsmEnablePaging32 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "BaseLibInternals.h" + +/** + Enables the 32-bit paging mode on the CPU. + + Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables + must be properly initialized prior to calling this service. This function + assumes the current execution mode is 32-bit protected mode. This function is + only available on IA-32. After the 32-bit paging mode is enabled, control is + transferred to the function specified by EntryPoint using the new stack + specified by NewStack and passing in the parameters specified by Context1 and + Context2. Context1 and Context2 are optional and may be NULL. The function + EntryPoint must never return. + + There are a number of constraints that must be followed before calling this + function: + 1) Interrupts must be disabled. + 2) The caller must be in 32-bit protected mode with flat descriptors. This + means all descriptors must have a base of 0 and a limit of 4GB. + 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat + descriptors. + 4) CR3 must point to valid page tables that will be used once the transition + is complete, and those page tables must guarantee that the pages for this + function and the stack are identity mapped. + + @param EntryPoint A pointer to function to call with the new stack after + paging is enabled. + @param Context1 A pointer to the context to pass into the EntryPoint + function as the first parameter after paging is enabled. + @param Context2 A pointer to the context to pass into the EntryPoint + function as the second parameter after paging is enabled. + @param NewStack A pointer to the new stack to use for the EntryPoint + function after paging is enabled. + +**/ +__declspec (naked) +VOID +EFIAPI +InternalX86EnablePaging32 ( + IN SWITCH_STACK_ENTRY_POINT EntryPoint, + IN VOID *Context1, OPTIONAL + IN VOID *Context2, OPTIONAL + IN VOID *NewStack + ) +{ + _asm { + push ebp + mov ebp, esp + mov ebx, EntryPoint + mov ecx, Context1 + mov edx, Context2 + pushfd + pop edi + cli + mov eax, cr0 + bts eax, 31 + mov esp, NewStack + mov cr0, eax + push edi + popfd + push edx + push ecx + call ebx + jmp $ + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging32.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging32.nasm new file mode 100644 index 000000000..3f00167b3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging32.nasm @@ -0,0 +1,48 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; EnablePaging32.Asm +; +; Abstract: +; +; AsmEnablePaging32 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; InternalX86EnablePaging32 ( +; IN SWITCH_STACK_ENTRY_POINT EntryPoint, +; IN VOID *Context1, OPTIONAL +; IN VOID *Context2, OPTIONAL +; IN VOID *NewStack +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalX86EnablePaging32) +ASM_PFX(InternalX86EnablePaging32): + mov ebx, [esp + 4] + mov ecx, [esp + 8] + mov edx, [esp + 12] + pushfd + pop edi ; save flags in edi + cli + mov eax, cr0 + bts eax, 31 + mov esp, [esp + 16] + mov cr0, eax + push edi + popfd ; restore flags + push edx + push ecx + call ebx + jmp $ + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm new file mode 100644 index 000000000..544e3c389 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm @@ -0,0 +1,59 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; EnablePaging64.Asm +; +; Abstract: +; +; AsmEnablePaging64 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; InternalX86EnablePaging64 ( +; IN UINT16 Cs, +; IN UINT64 EntryPoint, +; IN UINT64 Context1, OPTIONAL +; IN UINT64 Context2, OPTIONAL +; IN UINT64 NewStack +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalX86EnablePaging64) +ASM_PFX(InternalX86EnablePaging64): + cli + mov DWORD [esp], .0 ; offset for far retf, seg is the 1st arg + mov eax, cr4 + or al, (1 << 5) + mov cr4, eax ; enable PAE + mov ecx, 0xc0000080 + rdmsr + or ah, 1 ; set LME + wrmsr + mov eax, cr0 + bts eax, 31 ; set PG + mov cr0, eax ; enable paging + retf ; topmost 2 dwords hold the address +.0: + DB 0x67, 0x48 ; 32-bit address size, 64-bit operand size + mov ebx, [esp] ; mov rbx, [esp] + DB 0x67, 0x48 + mov ecx, [esp + 8] ; mov rcx, [esp + 8] + DB 0x67, 0x48 + mov edx, [esp + 0x10] ; mov rdx, [esp + 10h] + DB 0x67, 0x48 + mov esp, [esp + 0x18] ; mov rsp, [esp + 18h] + DB 0x48 + add esp, -0x20 ; add rsp, -20h + call ebx ; call rbx + hlt ; no one should get here + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c new file mode 100644 index 000000000..8fbda0670 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c @@ -0,0 +1,52 @@ +/** @file + AsmFlushCacheLine function + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Flushes a cache line from all the instruction and data caches within the + coherency domain of the CPU. + + Flushed the cache line specified by LinearAddress, and returns LinearAddress. + This function is only available on IA-32 and x64. + + @param LinearAddress The address of the cache line to flush. If the CPU is + in a physical addressing mode, then LinearAddress is a + physical address. If the CPU is in a virtual + addressing mode, then LinearAddress is a virtual + address. + + @return LinearAddress +**/ +VOID * +EFIAPI +AsmFlushCacheLine ( + IN VOID *LinearAddress + ) +{ + // + // If the CPU does not support CLFLUSH instruction, + // then promote flush range to flush entire cache. + // + _asm { + mov eax, 1 + cpuid + test edx, BIT19 + jz NoClflush + mov eax, dword ptr [LinearAddress] + clflush [eax] + jmp Done +NoClflush: + wbinvd +Done: + } + + return LinearAddress; +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.nasm new file mode 100644 index 000000000..8afd4cbdc --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.nasm @@ -0,0 +1,45 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; FlushCacheLine.Asm +; +; Abstract: +; +; AsmFlushCacheLine function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID * +; EFIAPI +; AsmFlushCacheLine ( +; IN VOID *LinearAddress +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmFlushCacheLine) +ASM_PFX(AsmFlushCacheLine): + ; + ; If the CPU does not support CLFLUSH instruction, + ; then promote flush range to flush entire cache. + ; + mov eax, 1 + push ebx + cpuid + pop ebx + mov eax, [esp + 4] + test edx, BIT19 + jz .0 + clflush [eax] + ret +.0: + wbinvd + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxRestore.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxRestore.c new file mode 100644 index 000000000..ddd1e4903 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxRestore.c @@ -0,0 +1,34 @@ +/** @file + AsmFxRestore function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "BaseLibInternals.h" + + +/** + Restores the current floating point/SSE/SSE2 context from a buffer. + + Restores the current floating point/SSE/SSE2 state from the buffer specified + by Buffer. Buffer must be aligned on a 16-byte boundary. This function is + only available on IA-32 and x64. + + @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context. + +**/ +VOID +EFIAPI +InternalX86FxRestore ( + IN CONST IA32_FX_BUFFER *Buffer + ) +{ + _asm { + mov eax, Buffer + fxrstor [eax] + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxRestore.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxRestore.nasm new file mode 100644 index 000000000..c48746890 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxRestore.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; FxRestore.Asm +; +; Abstract: +; +; AsmFxRestore function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; InternalX86FxRestore ( +; IN CONST IA32_FX_BUFFER *Buffer +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalX86FxRestore) +ASM_PFX(InternalX86FxRestore): + mov eax, [esp + 4] ; Buffer must be 16-byte aligned + fxrstor [eax] + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxSave.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxSave.c new file mode 100644 index 000000000..a8c888217 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxSave.c @@ -0,0 +1,34 @@ +/** @file + AsmFxSave function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "BaseLibInternals.h" + + +/** + Save the current floating point/SSE/SSE2 context to a buffer. + + Saves the current floating point/SSE/SSE2 state to the buffer specified by + Buffer. Buffer must be aligned on a 16-byte boundary. This function is only + available on IA-32 and x64. + + @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context. + +**/ +VOID +EFIAPI +InternalX86FxSave ( + OUT IA32_FX_BUFFER *Buffer + ) +{ + _asm { + mov eax, Buffer + fxsave [eax] + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxSave.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxSave.nasm new file mode 100644 index 000000000..c1982c064 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxSave.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; FxSave.Asm +; +; Abstract: +; +; AsmFxSave function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; InternalX86FxSave ( +; OUT IA32_FX_BUFFER *Buffer +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalX86FxSave) +ASM_PFX(InternalX86FxSave): + mov eax, [esp + 4] ; Buffer must be 16-byte aligned + fxsave [eax] + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/GccInline.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/GccInline.c new file mode 100644 index 000000000..6ed938187 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/GccInline.c @@ -0,0 +1,586 @@ +/** @file + GCC inline implementation of BaseLib processor specific functions. + + Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "BaseLibInternals.h" + +/** + Used to serialize load and store operations. + + All loads and stores that proceed calls to this function are guaranteed to be + globally visible when this function returns. + +**/ +VOID +EFIAPI +MemoryFence ( + VOID + ) +{ + // This is a little bit of overkill and it is more about the compiler that it is + // actually processor synchronization. This is like the _ReadWriteBarrier + // Microsoft specific intrinsic + __asm__ __volatile__ ("":::"memory"); +} + +/** + Requests CPU to pause for a short period of time. + + Requests CPU to pause for a short period of time. Typically used in MP + systems to prevent memory starvation while waiting for a spin lock. + +**/ +VOID +EFIAPI +CpuPause ( + VOID + ) +{ + __asm__ __volatile__ ("pause"); +} + +/** + Generates a breakpoint on the CPU. + + Generates a breakpoint on the CPU. The breakpoint must be implemented such + that code can resume normal execution after the breakpoint. + +**/ +VOID +EFIAPI +CpuBreakpoint ( + VOID + ) +{ + __asm__ __volatile__ ("int $3"); +} + +/** + Reads the current value of the EFLAGS register. + + Reads and returns the current value of the EFLAGS register. This function is + only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a + 64-bit value on X64. + + @return EFLAGS on IA-32 or RFLAGS on X64. + +**/ +UINTN +EFIAPI +AsmReadEflags ( + VOID + ) +{ + UINTN Eflags; + + __asm__ __volatile__ ( + "pushfl \n\t" + "popl %0 " + : "=r" (Eflags) + ); + + return Eflags; +} + +/** + Save the current floating point/SSE/SSE2 context to a buffer. + + Saves the current floating point/SSE/SSE2 state to the buffer specified by + Buffer. Buffer must be aligned on a 16-byte boundary. This function is only + available on IA-32 and X64. + + @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context. + +**/ +VOID +EFIAPI +InternalX86FxSave ( + OUT IA32_FX_BUFFER *Buffer + ) +{ + __asm__ __volatile__ ( + "fxsave %0" + : + : "m" (*Buffer) // %0 + ); +} + + +/** + Restores the current floating point/SSE/SSE2 context from a buffer. + + Restores the current floating point/SSE/SSE2 state from the buffer specified + by Buffer. Buffer must be aligned on a 16-byte boundary. This function is + only available on IA-32 and X64. + + @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context. + +**/ +VOID +EFIAPI +InternalX86FxRestore ( + IN CONST IA32_FX_BUFFER *Buffer + ) +{ + __asm__ __volatile__ ( + "fxrstor %0" + : + : "m" (*Buffer) // %0 + ); +} + + +/** + Reads the current value of 64-bit MMX Register #0 (MM0). + + Reads and returns the current value of MM0. This function is only available + on IA-32 and X64. + + @return The current value of MM0. + +**/ +UINT64 +EFIAPI +AsmReadMm0 ( + VOID + ) +{ + UINT64 Data; + + __asm__ __volatile__ ( + "push %%eax \n\t" + "push %%eax \n\t" + "movq %%mm0, (%%esp)\n\t" + "pop %%eax \n\t" + "pop %%edx \n\t" + : "=A" (Data) // %0 + ); + + return Data; +} + + +/** + Reads the current value of 64-bit MMX Register #1 (MM1). + + Reads and returns the current value of MM1. This function is only available + on IA-32 and X64. + + @return The current value of MM1. + +**/ +UINT64 +EFIAPI +AsmReadMm1 ( + VOID + ) +{ + UINT64 Data; + + __asm__ __volatile__ ( + "push %%eax \n\t" + "push %%eax \n\t" + "movq %%mm1, (%%esp)\n\t" + "pop %%eax \n\t" + "pop %%edx \n\t" + : "=A" (Data) // %0 + ); + + return Data; +} + + +/** + Reads the current value of 64-bit MMX Register #2 (MM2). + + Reads and returns the current value of MM2. This function is only available + on IA-32 and X64. + + @return The current value of MM2. + +**/ +UINT64 +EFIAPI +AsmReadMm2 ( + VOID + ) +{ + UINT64 Data; + + __asm__ __volatile__ ( + "push %%eax \n\t" + "push %%eax \n\t" + "movq %%mm2, (%%esp)\n\t" + "pop %%eax \n\t" + "pop %%edx \n\t" + : "=A" (Data) // %0 + ); + + return Data; +} + + +/** + Reads the current value of 64-bit MMX Register #3 (MM3). + + Reads and returns the current value of MM3. This function is only available + on IA-32 and X64. + + @return The current value of MM3. + +**/ +UINT64 +EFIAPI +AsmReadMm3 ( + VOID + ) +{ + UINT64 Data; + + __asm__ __volatile__ ( + "push %%eax \n\t" + "push %%eax \n\t" + "movq %%mm3, (%%esp)\n\t" + "pop %%eax \n\t" + "pop %%edx \n\t" + : "=A" (Data) // %0 + ); + + return Data; +} + + +/** + Reads the current value of 64-bit MMX Register #4 (MM4). + + Reads and returns the current value of MM4. This function is only available + on IA-32 and X64. + + @return The current value of MM4. + +**/ +UINT64 +EFIAPI +AsmReadMm4 ( + VOID + ) +{ + UINT64 Data; + + __asm__ __volatile__ ( + "push %%eax \n\t" + "push %%eax \n\t" + "movq %%mm4, (%%esp)\n\t" + "pop %%eax \n\t" + "pop %%edx \n\t" + : "=A" (Data) // %0 + ); + + return Data; +} + + +/** + Reads the current value of 64-bit MMX Register #5 (MM5). + + Reads and returns the current value of MM5. This function is only available + on IA-32 and X64. + + @return The current value of MM5. + +**/ +UINT64 +EFIAPI +AsmReadMm5 ( + VOID + ) +{ + UINT64 Data; + + __asm__ __volatile__ ( + "push %%eax \n\t" + "push %%eax \n\t" + "movq %%mm5, (%%esp)\n\t" + "pop %%eax \n\t" + "pop %%edx \n\t" + : "=A" (Data) // %0 + ); + + return Data; +} + + +/** + Reads the current value of 64-bit MMX Register #6 (MM6). + + Reads and returns the current value of MM6. This function is only available + on IA-32 and X64. + + @return The current value of MM6. + +**/ +UINT64 +EFIAPI +AsmReadMm6 ( + VOID + ) +{ + UINT64 Data; + + __asm__ __volatile__ ( + "push %%eax \n\t" + "push %%eax \n\t" + "movq %%mm6, (%%esp)\n\t" + "pop %%eax \n\t" + "pop %%edx \n\t" + : "=A" (Data) // %0 + ); + + return Data; +} + + +/** + Reads the current value of 64-bit MMX Register #7 (MM7). + + Reads and returns the current value of MM7. This function is only available + on IA-32 and X64. + + @return The current value of MM7. + +**/ +UINT64 +EFIAPI +AsmReadMm7 ( + VOID + ) +{ + UINT64 Data; + + __asm__ __volatile__ ( + "push %%eax \n\t" + "push %%eax \n\t" + "movq %%mm7, (%%esp)\n\t" + "pop %%eax \n\t" + "pop %%edx \n\t" + : "=A" (Data) // %0 + ); + + return Data; +} + + +/** + Writes the current value of 64-bit MMX Register #0 (MM0). + + Writes the current value of MM0. This function is only available on IA32 and + X64. + + @param Value The 64-bit value to write to MM0. + +**/ +VOID +EFIAPI +AsmWriteMm0 ( + IN UINT64 Value + ) +{ + __asm__ __volatile__ ( + "movq %0, %%mm0" // %0 + : + : "m" (Value) + ); +} + + +/** + Writes the current value of 64-bit MMX Register #1 (MM1). + + Writes the current value of MM1. This function is only available on IA32 and + X64. + + @param Value The 64-bit value to write to MM1. + +**/ +VOID +EFIAPI +AsmWriteMm1 ( + IN UINT64 Value + ) +{ + __asm__ __volatile__ ( + "movq %0, %%mm1" // %0 + : + : "m" (Value) + ); +} + + +/** + Writes the current value of 64-bit MMX Register #2 (MM2). + + Writes the current value of MM2. This function is only available on IA32 and + X64. + + @param Value The 64-bit value to write to MM2. + +**/ +VOID +EFIAPI +AsmWriteMm2 ( + IN UINT64 Value + ) +{ + __asm__ __volatile__ ( + "movq %0, %%mm2" // %0 + : + : "m" (Value) + ); +} + + +/** + Writes the current value of 64-bit MMX Register #3 (MM3). + + Writes the current value of MM3. This function is only available on IA32 and + X64. + + @param Value The 64-bit value to write to MM3. + +**/ +VOID +EFIAPI +AsmWriteMm3 ( + IN UINT64 Value + ) +{ + __asm__ __volatile__ ( + "movq %0, %%mm3" // %0 + : + : "m" (Value) + ); +} + + +/** + Writes the current value of 64-bit MMX Register #4 (MM4). + + Writes the current value of MM4. This function is only available on IA32 and + X64. + + @param Value The 64-bit value to write to MM4. + +**/ +VOID +EFIAPI +AsmWriteMm4 ( + IN UINT64 Value + ) +{ + __asm__ __volatile__ ( + "movq %0, %%mm4" // %0 + : + : "m" (Value) + ); +} + + +/** + Writes the current value of 64-bit MMX Register #5 (MM5). + + Writes the current value of MM5. This function is only available on IA32 and + X64. + + @param Value The 64-bit value to write to MM5. + +**/ +VOID +EFIAPI +AsmWriteMm5 ( + IN UINT64 Value + ) +{ + __asm__ __volatile__ ( + "movq %0, %%mm5" // %0 + : + : "m" (Value) + ); +} + + +/** + Writes the current value of 64-bit MMX Register #6 (MM6). + + Writes the current value of MM6. This function is only available on IA32 and + X64. + + @param Value The 64-bit value to write to MM6. + +**/ +VOID +EFIAPI +AsmWriteMm6 ( + IN UINT64 Value + ) +{ + __asm__ __volatile__ ( + "movq %0, %%mm6" // %0 + : + : "m" (Value) + ); +} + + +/** + Writes the current value of 64-bit MMX Register #7 (MM7). + + Writes the current value of MM7. This function is only available on IA32 and + X64. + + @param Value The 64-bit value to write to MM7. + +**/ +VOID +EFIAPI +AsmWriteMm7 ( + IN UINT64 Value + ) +{ + __asm__ __volatile__ ( + "movq %0, %%mm7" // %0 + : + : "m" (Value) + ); +} + + +/** + Reads the current value of Time Stamp Counter (TSC). + + Reads and returns the current value of TSC. This function is only available + on IA-32 and X64. + + @return The current value of TSC + +**/ +UINT64 +EFIAPI +AsmReadTsc ( + VOID + ) +{ + UINT64 Data; + + __asm__ __volatile__ ( + "rdtsc" + : "=A" (Data) + ); + + return Data; +} diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c new file mode 100644 index 000000000..30aa63243 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c @@ -0,0 +1,1170 @@ +/** @file + GCC inline implementation of BaseLib processor specific functions that use + privlidged instructions. + + Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "BaseLibInternals.h" + +/** + Enables CPU interrupts. + + Enables CPU interrupts. + +**/ +VOID +EFIAPI +EnableInterrupts ( + VOID + ) +{ + __asm__ __volatile__ ("sti"::: "memory"); +} + + +/** + Disables CPU interrupts. + + Disables CPU interrupts. + +**/ +VOID +EFIAPI +DisableInterrupts ( + VOID + ) +{ + __asm__ __volatile__ ("cli"::: "memory"); +} + +/** + Returns a 64-bit Machine Specific Register(MSR). + + Reads and returns the 64-bit MSR specified by Index. No parameter checking is + performed on Index, and some Index values may cause CPU exceptions. The + caller must either guarantee that Index is valid, or the caller must set up + exception handlers to catch the exceptions. This function is only available + on IA-32 and X64. + + @param Index The 32-bit MSR index to read. + + @return The value of the MSR identified by Index. + +**/ +UINT64 +EFIAPI +AsmReadMsr64 ( + IN UINT32 Index + ) +{ + UINT64 Data; + + __asm__ __volatile__ ( + "rdmsr" + : "=A" (Data) // %0 + : "c" (Index) // %1 + ); + + return Data; +} + +/** + Writes a 64-bit value to a Machine Specific Register(MSR), and returns the + value. + + Writes the 64-bit value specified by Value to the MSR specified by Index. The + 64-bit value written to the MSR is returned. No parameter checking is + performed on Index or Value, and some of these may cause CPU exceptions. The + caller must either guarantee that Index and Value are valid, or the caller + must establish proper exception handlers. This function is only available on + IA-32 and X64. + + @param Index The 32-bit MSR index to write. + @param Value The 64-bit value to write to the MSR. + + @return Value + +**/ +UINT64 +EFIAPI +AsmWriteMsr64 ( + IN UINT32 Index, + IN UINT64 Value + ) +{ + __asm__ __volatile__ ( + "wrmsr" + : + : "c" (Index), + "A" (Value) + ); + + return Value; +} + +/** + Reads the current value of the Control Register 0 (CR0). + + Reads and returns the current value of CR0. This function is only available + on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on + X64. + + @return The value of the Control Register 0 (CR0). + +**/ +UINTN +EFIAPI +AsmReadCr0 ( + VOID + ) +{ + UINTN Data; + + __asm__ __volatile__ ( + "movl %%cr0,%0" + : "=a" (Data) + ); + + return Data; +} + + +/** + Reads the current value of the Control Register 2 (CR2). + + Reads and returns the current value of CR2. This function is only available + on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on + X64. + + @return The value of the Control Register 2 (CR2). + +**/ +UINTN +EFIAPI +AsmReadCr2 ( + VOID + ) +{ + UINTN Data; + + __asm__ __volatile__ ( + "movl %%cr2, %0" + : "=r" (Data) + ); + + return Data; +} + +/** + Reads the current value of the Control Register 3 (CR3). + + Reads and returns the current value of CR3. This function is only available + on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on + X64. + + @return The value of the Control Register 3 (CR3). + +**/ +UINTN +EFIAPI +AsmReadCr3 ( + VOID + ) +{ + UINTN Data; + + __asm__ __volatile__ ( + "movl %%cr3, %0" + : "=r" (Data) + ); + + return Data; +} + + +/** + Reads the current value of the Control Register 4 (CR4). + + Reads and returns the current value of CR4. This function is only available + on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on + X64. + + @return The value of the Control Register 4 (CR4). + +**/ +UINTN +EFIAPI +AsmReadCr4 ( + VOID + ) +{ + UINTN Data; + + __asm__ __volatile__ ( + "movl %%cr4, %0" + : "=a" (Data) + ); + + return Data; +} + + +/** + Writes a value to Control Register 0 (CR0). + + Writes and returns a new value to CR0. This function is only available on + IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + + @param Cr0 The value to write to CR0. + + @return The value written to CR0. + +**/ +UINTN +EFIAPI +AsmWriteCr0 ( + UINTN Cr0 + ) +{ + __asm__ __volatile__ ( + "movl %0, %%cr0" + : + : "r" (Cr0) + ); + return Cr0; +} + + +/** + Writes a value to Control Register 2 (CR2). + + Writes and returns a new value to CR2. This function is only available on + IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + + @param Cr2 The value to write to CR2. + + @return The value written to CR2. + +**/ +UINTN +EFIAPI +AsmWriteCr2 ( + UINTN Cr2 + ) +{ + __asm__ __volatile__ ( + "movl %0, %%cr2" + : + : "r" (Cr2) + ); + return Cr2; +} + + +/** + Writes a value to Control Register 3 (CR3). + + Writes and returns a new value to CR3. This function is only available on + IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + + @param Cr3 The value to write to CR3. + + @return The value written to CR3. + +**/ +UINTN +EFIAPI +AsmWriteCr3 ( + UINTN Cr3 + ) +{ + __asm__ __volatile__ ( + "movl %0, %%cr3" + : + : "r" (Cr3) + ); + return Cr3; +} + + +/** + Writes a value to Control Register 4 (CR4). + + Writes and returns a new value to CR4. This function is only available on + IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + + @param Cr4 The value to write to CR4. + + @return The value written to CR4. + +**/ +UINTN +EFIAPI +AsmWriteCr4 ( + UINTN Cr4 + ) +{ + __asm__ __volatile__ ( + "movl %0, %%cr4" + : + : "r" (Cr4) + ); + return Cr4; +} + + +/** + Reads the current value of Debug Register 0 (DR0). + + Reads and returns the current value of DR0. This function is only available + on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on + X64. + + @return The value of Debug Register 0 (DR0). + +**/ +UINTN +EFIAPI +AsmReadDr0 ( + VOID + ) +{ + UINTN Data; + + __asm__ __volatile__ ( + "movl %%dr0, %0" + : "=r" (Data) + ); + + return Data; +} + + +/** + Reads the current value of Debug Register 1 (DR1). + + Reads and returns the current value of DR1. This function is only available + on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on + X64. + + @return The value of Debug Register 1 (DR1). + +**/ +UINTN +EFIAPI +AsmReadDr1 ( + VOID + ) +{ + UINTN Data; + + __asm__ __volatile__ ( + "movl %%dr1, %0" + : "=r" (Data) + ); + + return Data; +} + + +/** + Reads the current value of Debug Register 2 (DR2). + + Reads and returns the current value of DR2. This function is only available + on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on + X64. + + @return The value of Debug Register 2 (DR2). + +**/ +UINTN +EFIAPI +AsmReadDr2 ( + VOID + ) +{ + UINTN Data; + + __asm__ __volatile__ ( + "movl %%dr2, %0" + : "=r" (Data) + ); + + return Data; +} + + +/** + Reads the current value of Debug Register 3 (DR3). + + Reads and returns the current value of DR3. This function is only available + on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on + X64. + + @return The value of Debug Register 3 (DR3). + +**/ +UINTN +EFIAPI +AsmReadDr3 ( + VOID + ) +{ + UINTN Data; + + __asm__ __volatile__ ( + "movl %%dr3, %0" + : "=r" (Data) + ); + + return Data; +} + + +/** + Reads the current value of Debug Register 4 (DR4). + + Reads and returns the current value of DR4. This function is only available + on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on + X64. + + @return The value of Debug Register 4 (DR4). + +**/ +UINTN +EFIAPI +AsmReadDr4 ( + VOID + ) +{ + UINTN Data; + + __asm__ __volatile__ ( + "movl %%dr4, %0" + : "=r" (Data) + ); + + return Data; +} + + +/** + Reads the current value of Debug Register 5 (DR5). + + Reads and returns the current value of DR5. This function is only available + on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on + X64. + + @return The value of Debug Register 5 (DR5). + +**/ +UINTN +EFIAPI +AsmReadDr5 ( + VOID + ) +{ + UINTN Data; + + __asm__ __volatile__ ( + "movl %%dr5, %0" + : "=r" (Data) + ); + + return Data; +} + + +/** + Reads the current value of Debug Register 6 (DR6). + + Reads and returns the current value of DR6. This function is only available + on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on + X64. + + @return The value of Debug Register 6 (DR6). + +**/ +UINTN +EFIAPI +AsmReadDr6 ( + VOID + ) +{ + UINTN Data; + + __asm__ __volatile__ ( + "movl %%dr6, %0" + : "=r" (Data) + ); + + return Data; +} + + +/** + Reads the current value of Debug Register 7 (DR7). + + Reads and returns the current value of DR7. This function is only available + on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on + X64. + + @return The value of Debug Register 7 (DR7). + +**/ +UINTN +EFIAPI +AsmReadDr7 ( + VOID + ) +{ + UINTN Data; + + __asm__ __volatile__ ( + "movl %%dr7, %0" + : "=r" (Data) + ); + + return Data; +} + + +/** + Writes a value to Debug Register 0 (DR0). + + Writes and returns a new value to DR0. This function is only available on + IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + + @param Dr0 The value to write to Dr0. + + @return The value written to Debug Register 0 (DR0). + +**/ +UINTN +EFIAPI +AsmWriteDr0 ( + UINTN Dr0 + ) +{ + __asm__ __volatile__ ( + "movl %0, %%dr0" + : + : "r" (Dr0) + ); + return Dr0; +} + + +/** + Writes a value to Debug Register 1 (DR1). + + Writes and returns a new value to DR1. This function is only available on + IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + + @param Dr1 The value to write to Dr1. + + @return The value written to Debug Register 1 (DR1). + +**/ +UINTN +EFIAPI +AsmWriteDr1 ( + UINTN Dr1 + ) +{ + __asm__ __volatile__ ( + "movl %0, %%dr1" + : + : "r" (Dr1) + ); + return Dr1; +} + + +/** + Writes a value to Debug Register 2 (DR2). + + Writes and returns a new value to DR2. This function is only available on + IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + + @param Dr2 The value to write to Dr2. + + @return The value written to Debug Register 2 (DR2). + +**/ +UINTN +EFIAPI +AsmWriteDr2 ( + UINTN Dr2 + ) +{ + __asm__ __volatile__ ( + "movl %0, %%dr2" + : + : "r" (Dr2) + ); + return Dr2; +} + + +/** + Writes a value to Debug Register 3 (DR3). + + Writes and returns a new value to DR3. This function is only available on + IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + + @param Dr3 The value to write to Dr3. + + @return The value written to Debug Register 3 (DR3). + +**/ +UINTN +EFIAPI +AsmWriteDr3 ( + UINTN Dr3 + ) +{ + __asm__ __volatile__ ( + "movl %0, %%dr3" + : + : "r" (Dr3) + ); + return Dr3; +} + + +/** + Writes a value to Debug Register 4 (DR4). + + Writes and returns a new value to DR4. This function is only available on + IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + + @param Dr4 The value to write to Dr4. + + @return The value written to Debug Register 4 (DR4). + +**/ +UINTN +EFIAPI +AsmWriteDr4 ( + UINTN Dr4 + ) +{ + __asm__ __volatile__ ( + "movl %0, %%dr4" + : + : "r" (Dr4) + ); + return Dr4; +} + + +/** + Writes a value to Debug Register 5 (DR5). + + Writes and returns a new value to DR5. This function is only available on + IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + + @param Dr5 The value to write to Dr5. + + @return The value written to Debug Register 5 (DR5). + +**/ +UINTN +EFIAPI +AsmWriteDr5 ( + UINTN Dr5 + ) +{ + __asm__ __volatile__ ( + "movl %0, %%dr5" + : + : "r" (Dr5) + ); + return Dr5; +} + + +/** + Writes a value to Debug Register 6 (DR6). + + Writes and returns a new value to DR6. This function is only available on + IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + + @param Dr6 The value to write to Dr6. + + @return The value written to Debug Register 6 (DR6). + +**/ +UINTN +EFIAPI +AsmWriteDr6 ( + UINTN Dr6 + ) +{ + __asm__ __volatile__ ( + "movl %0, %%dr6" + : + : "r" (Dr6) + ); + return Dr6; +} + + +/** + Writes a value to Debug Register 7 (DR7). + + Writes and returns a new value to DR7. This function is only available on + IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + + @param Dr7 The value to write to Dr7. + + @return The value written to Debug Register 7 (DR7). + +**/ +UINTN +EFIAPI +AsmWriteDr7 ( + UINTN Dr7 + ) +{ + __asm__ __volatile__ ( + "movl %0, %%dr7" + : + : "r" (Dr7) + ); + return Dr7; +} + + +/** + Reads the current value of Code Segment Register (CS). + + Reads and returns the current value of CS. This function is only available on + IA-32 and X64. + + @return The current value of CS. + +**/ +UINT16 +EFIAPI +AsmReadCs ( + VOID + ) +{ + UINT16 Data; + + __asm__ __volatile__ ( + "mov %%cs, %0" + :"=a" (Data) + ); + + return Data; +} + + +/** + Reads the current value of Data Segment Register (DS). + + Reads and returns the current value of DS. This function is only available on + IA-32 and X64. + + @return The current value of DS. + +**/ +UINT16 +EFIAPI +AsmReadDs ( + VOID + ) +{ + UINT16 Data; + + __asm__ __volatile__ ( + "mov %%ds, %0" + :"=a" (Data) + ); + + return Data; +} + + +/** + Reads the current value of Extra Segment Register (ES). + + Reads and returns the current value of ES. This function is only available on + IA-32 and X64. + + @return The current value of ES. + +**/ +UINT16 +EFIAPI +AsmReadEs ( + VOID + ) +{ + UINT16 Data; + + __asm__ __volatile__ ( + "mov %%es, %0" + :"=a" (Data) + ); + + return Data; +} + + +/** + Reads the current value of FS Data Segment Register (FS). + + Reads and returns the current value of FS. This function is only available on + IA-32 and X64. + + @return The current value of FS. + +**/ +UINT16 +EFIAPI +AsmReadFs ( + VOID + ) +{ + UINT16 Data; + + __asm__ __volatile__ ( + "mov %%fs, %0" + :"=a" (Data) + ); + + return Data; +} + + +/** + Reads the current value of GS Data Segment Register (GS). + + Reads and returns the current value of GS. This function is only available on + IA-32 and X64. + + @return The current value of GS. + +**/ +UINT16 +EFIAPI +AsmReadGs ( + VOID + ) +{ + UINT16 Data; + + __asm__ __volatile__ ( + "mov %%gs, %0" + :"=a" (Data) + ); + + return Data; +} + + +/** + Reads the current value of Stack Segment Register (SS). + + Reads and returns the current value of SS. This function is only available on + IA-32 and X64. + + @return The current value of SS. + +**/ +UINT16 +EFIAPI +AsmReadSs ( + VOID + ) +{ + UINT16 Data; + + __asm__ __volatile__ ( + "mov %%ds, %0" + :"=a" (Data) + ); + + return Data; +} + + +/** + Reads the current value of Task Register (TR). + + Reads and returns the current value of TR. This function is only available on + IA-32 and X64. + + @return The current value of TR. + +**/ +UINT16 +EFIAPI +AsmReadTr ( + VOID + ) +{ + UINT16 Data; + + __asm__ __volatile__ ( + "str %0" + : "=a" (Data) + ); + + return Data; +} + + +/** + Reads the current Global Descriptor Table Register(GDTR) descriptor. + + Reads and returns the current GDTR descriptor and returns it in Gdtr. This + function is only available on IA-32 and X64. + + @param Gdtr The pointer to a GDTR descriptor. + +**/ +VOID +EFIAPI +InternalX86ReadGdtr ( + OUT IA32_DESCRIPTOR *Gdtr + ) +{ + __asm__ __volatile__ ( + "sgdt %0" + : "=m" (*Gdtr) + ); +} + + +/** + Writes the current Global Descriptor Table Register (GDTR) descriptor. + + Writes and the current GDTR descriptor specified by Gdtr. This function is + only available on IA-32 and X64. + + @param Gdtr The pointer to a GDTR descriptor. + +**/ +VOID +EFIAPI +InternalX86WriteGdtr ( + IN CONST IA32_DESCRIPTOR *Gdtr + ) +{ + __asm__ __volatile__ ( + "lgdt %0" + : + : "m" (*Gdtr) + ); + +} + + +/** + Reads the current Interrupt Descriptor Table Register(GDTR) descriptor. + + Reads and returns the current IDTR descriptor and returns it in Idtr. This + function is only available on IA-32 and X64. + + @param Idtr The pointer to a IDTR descriptor. + +**/ +VOID +EFIAPI +InternalX86ReadIdtr ( + OUT IA32_DESCRIPTOR *Idtr + ) +{ + __asm__ __volatile__ ( + "sidt %0" + : "=m" (*Idtr) + ); +} + + +/** + Writes the current Interrupt Descriptor Table Register(GDTR) descriptor. + + Writes the current IDTR descriptor and returns it in Idtr. This function is + only available on IA-32 and X64. + + @param Idtr The pointer to a IDTR descriptor. + +**/ +VOID +EFIAPI +InternalX86WriteIdtr ( + IN CONST IA32_DESCRIPTOR *Idtr + ) +{ + __asm__ __volatile__ ( + "lidt %0" + : + : "m" (*Idtr) + ); +} + + +/** + Reads the current Local Descriptor Table Register(LDTR) selector. + + Reads and returns the current 16-bit LDTR descriptor value. This function is + only available on IA-32 and X64. + + @return The current selector of LDT. + +**/ +UINT16 +EFIAPI +AsmReadLdtr ( + VOID + ) +{ + UINT16 Data; + + __asm__ __volatile__ ( + "sldt %0" + : "=g" (Data) // %0 + ); + + return Data; +} + + +/** + Writes the current Local Descriptor Table Register (GDTR) selector. + + Writes and the current LDTR descriptor specified by Ldtr. This function is + only available on IA-32 and X64. + + @param Ldtr 16-bit LDTR selector value. + +**/ +VOID +EFIAPI +AsmWriteLdtr ( + IN UINT16 Ldtr + ) +{ + __asm__ __volatile__ ( + "lldtw %0" + : + : "g" (Ldtr) // %0 + ); +} + +/** + Reads the current value of a Performance Counter (PMC). + + Reads and returns the current value of performance counter specified by + Index. This function is only available on IA-32 and X64. + + @param Index The 32-bit Performance Counter index to read. + + @return The value of the PMC specified by Index. + +**/ +UINT64 +EFIAPI +AsmReadPmc ( + IN UINT32 Index + ) +{ + UINT64 Data; + + __asm__ __volatile__ ( + "rdpmc" + : "=A" (Data) + : "c" (Index) + ); + + return Data; +} + +/** + Executes a WBINVD instruction. + + Executes a WBINVD instruction. This function is only available on IA-32 and + X64. + +**/ +VOID +EFIAPI +AsmWbinvd ( + VOID + ) +{ + __asm__ __volatile__ ("wbinvd":::"memory"); +} + +/** + Executes a INVD instruction. + + Executes a INVD instruction. This function is only available on IA-32 and + X64. + +**/ +VOID +EFIAPI +AsmInvd ( + VOID + ) +{ + __asm__ __volatile__ ("invd":::"memory"); + +} + + +/** + Flushes a cache line from all the instruction and data caches within the + coherency domain of the CPU. + + Flushed the cache line specified by LinearAddress, and returns LinearAddress. + This function is only available on IA-32 and X64. + + @param LinearAddress The address of the cache line to flush. If the CPU is + in a physical addressing mode, then LinearAddress is a + physical address. If the CPU is in a virtual + addressing mode, then LinearAddress is a virtual + address. + + @return LinearAddress +**/ +VOID * +EFIAPI +AsmFlushCacheLine ( + IN VOID *LinearAddress + ) +{ + UINT32 RegEdx; + + // + // If the CPU does not support CLFLUSH instruction, + // then promote flush range to flush entire cache. + // + AsmCpuid (0x01, NULL, NULL, NULL, &RegEdx); + if ((RegEdx & BIT19) == 0) { + __asm__ __volatile__ ("wbinvd":::"memory"); + return LinearAddress; + } + + + __asm__ __volatile__ ( + "clflush (%0)" + : "+a" (LinearAddress) + : + : "memory" + ); + + return LinearAddress; +} diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.c new file mode 100644 index 000000000..6f4cf79e6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.c @@ -0,0 +1,54 @@ +/** @file + SwitchStack() function for IA-32. + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "BaseLibInternals.h" + +/** + Transfers control to a function starting with a new stack. + + Transfers control to the function specified by EntryPoint using the + new stack specified by NewStack and passing in the parameters specified + by Context1 and Context2. Context1 and Context2 are optional and may + be NULL. The function EntryPoint must never return. + Marker will be ignored on IA-32, x64, and EBC. + IPF CPUs expect one additional parameter of type VOID * that specifies + the new backing store pointer. + + If EntryPoint is NULL, then ASSERT(). + If NewStack is NULL, then ASSERT(). + + @param EntryPoint A pointer to function to call with the new stack. + @param Context1 A pointer to the context to pass into the EntryPoint + function. + @param Context2 A pointer to the context to pass into the EntryPoint + function. + @param NewStack A pointer to the new stack to use for the EntryPoint + function. + @param Marker VA_LIST marker for the variable argument list. + +**/ +VOID +EFIAPI +InternalSwitchStack ( + IN SWITCH_STACK_ENTRY_POINT EntryPoint, + IN VOID *Context1, OPTIONAL + IN VOID *Context2, OPTIONAL + IN VOID *NewStack, + IN VA_LIST Marker + ) +{ + BASE_LIBRARY_JUMP_BUFFER JumpBuffer; + + JumpBuffer.Eip = (UINTN)EntryPoint; + JumpBuffer.Esp = (UINTN)NewStack - sizeof (VOID*); + JumpBuffer.Esp -= sizeof (Context1) + sizeof (Context2); + ((VOID**)JumpBuffer.Esp)[1] = Context1; + ((VOID**)JumpBuffer.Esp)[2] = Context2; + + LongJump (&JumpBuffer, (UINTN)-1); +} diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.nasm new file mode 100644 index 000000000..adfcdf779 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.nasm @@ -0,0 +1,41 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Portions copyright (c) 2011, Apple Inc. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; InternalSwitchStack.nasm +; +; Abstract: +; +; Implementation of a stack switch on IA-32. +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; InternalSwitchStack ( +; IN SWITCH_STACK_ENTRY_POINT EntryPoint, +; IN VOID *Context1, OPTIONAL +; IN VOID *Context2, OPTIONAL +; IN VOID *NewStack +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalSwitchStack) +ASM_PFX(InternalSwitchStack): + push ebp + mov ebp, esp + + mov esp, [ebp + 20] ; switch stack + sub esp, 8 + mov eax, [ebp + 16] + mov [esp + 4], eax + mov eax, [ebp + 12] + mov [esp], eax + push 0 ; keeps gdb from unwinding stack + jmp dword [ebp + 8] ; call and never return diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Invd.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Invd.c new file mode 100644 index 000000000..9870cf9c6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Invd.c @@ -0,0 +1,29 @@ +/** @file + AsmInvd function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Executes a INVD instruction. + + Executes a INVD instruction. This function is only available on IA-32 and + x64. + +**/ +VOID +EFIAPI +AsmInvd ( + VOID + ) +{ + _asm { + invd + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Invd.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Invd.nasm new file mode 100644 index 000000000..f6d1beb1b --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Invd.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; Invd.Asm +; +; Abstract: +; +; AsmInvd function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmInvd ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmInvd) +ASM_PFX(AsmInvd): + invd + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/LRotU64.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LRotU64.c new file mode 100644 index 000000000..87d370c6f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LRotU64.c @@ -0,0 +1,49 @@ +/** @file + 64-bit left rotation for Ia32 + + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Rotates a 64-bit integer left between 0 and 63 bits, filling + the low bits with the high bits that were rotated. + + This function rotates the 64-bit value Operand to the left by Count bits. The + low Count bits are fill with the high Count bits of Operand. The rotated + value is returned. + + @param Operand The 64-bit operand to rotate left. + @param Count The number of bits to rotate left. + + @return Operand <<< Count + +**/ +UINT64 +EFIAPI +InternalMathLRotU64 ( + IN UINT64 Operand, + IN UINTN Count + ) +{ + _asm { + mov cl, byte ptr [Count] + mov edx, dword ptr [Operand + 4] + mov eax, dword ptr [Operand + 0] + shld ebx, edx, cl + shld edx, eax, cl + ror ebx, cl + shld eax, ebx, cl + test cl, 32 ; Count >= 32? + jz L0 + mov ecx, eax + mov eax, edx + mov edx, ecx +L0: + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/LRotU64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LRotU64.nasm new file mode 100644 index 000000000..3922ae229 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LRotU64.nasm @@ -0,0 +1,44 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; LRotU64.nasm +; +; Abstract: +; +; 64-bit left rotation for Ia32 +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; InternalMathLRotU64 ( +; IN UINT64 Operand, +; IN UINTN Count +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalMathLRotU64) +ASM_PFX(InternalMathLRotU64): + push ebx + mov cl, [esp + 16] + mov edx, [esp + 12] + mov eax, [esp + 8] + shld ebx, edx, cl + shld edx, eax, cl + ror ebx, cl + shld eax, ebx, cl + test cl, 32 ; Count >= 32? + jz .0 + mov ecx, eax + mov eax, edx + mov edx, ecx +.0: + pop ebx + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/LShiftU64.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LShiftU64.c new file mode 100644 index 000000000..1604e7e2f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LShiftU64.c @@ -0,0 +1,45 @@ +/** @file + 64-bit left shift function for IA-32. + + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Shifts a 64-bit integer left between 0 and 63 bits. The low bits + are filled with zeros. The shifted value is returned. + + This function shifts the 64-bit value Operand to the left by Count bits. The + low Count bits are set to zero. The shifted value is returned. + + @param Operand The 64-bit operand to shift left. + @param Count The number of bits to shift left. + + @return Operand << Count + +**/ +UINT64 +EFIAPI +InternalMathLShiftU64 ( + IN UINT64 Operand, + IN UINTN Count + ) +{ + _asm { + mov cl, byte ptr [Count] + xor eax, eax + mov edx, dword ptr [Operand + 0] + test cl, 32 // Count >= 32? + jnz L0 + mov eax, edx + mov edx, dword ptr [Operand + 4] +L0: + shld edx, eax, cl + shl eax, cl + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/LShiftU64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LShiftU64.nasm new file mode 100644 index 000000000..26c38a122 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LShiftU64.nasm @@ -0,0 +1,39 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; LShiftU64.nasm +; +; Abstract: +; +; 64-bit left shift function for IA-32 +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; InternalMathLShiftU64 ( +; IN UINT64 Operand, +; IN UINTN Count +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalMathLShiftU64) +ASM_PFX(InternalMathLShiftU64): + mov cl, [esp + 12] + xor eax, eax + mov edx, [esp + 4] + test cl, 32 ; Count >= 32? + jnz .0 + mov eax, edx + mov edx, [esp + 8] +.0: + shld edx, eax, cl + shl eax, cl + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Lfence.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Lfence.nasm new file mode 100644 index 000000000..44478be35 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Lfence.nasm @@ -0,0 +1,30 @@ +;------------------------------------------------------------------------------ ; +; Copyright (c) 2018, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; Lfence.nasm +; +; Abstract: +; +; Performs a serializing operation on all load-from-memory instructions that +; were issued prior to the call of this function. +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmLfence ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmLfence) +ASM_PFX(AsmLfence): + lfence + ret diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/LongJump.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LongJump.nasm new file mode 100644 index 000000000..f94d10f80 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LongJump.nasm @@ -0,0 +1,60 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; LongJump.Asm +; +; Abstract: +; +; Implementation of _LongJump() on IA-32. +; +;------------------------------------------------------------------------------ + +%include "Nasm.inc" + + SECTION .text + +extern ASM_PFX(PcdGet32 (PcdControlFlowEnforcementPropertyMask)) + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; InternalLongJump ( +; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, +; IN UINTN Value +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalLongJump) +ASM_PFX(InternalLongJump): + + mov eax, [ASM_PFX(PcdGet32 (PcdControlFlowEnforcementPropertyMask))] + test eax, eax + jz CetDone + mov eax, cr4 + bt eax, 23 ; check if CET is enabled + jnc CetDone + + mov edx, [esp + 4] ; edx = JumpBuffer + mov edx, [edx + 24] ; edx = target SSP + READSSP_EAX + sub edx, eax ; edx = delta + mov eax, edx ; eax = delta + + shr eax, 2 ; eax = delta/sizeof(UINT32) + INCSSP_EAX + +CetDone: + + pop eax ; skip return address + pop edx ; edx <- JumpBuffer + pop eax ; eax <- Value + mov ebx, [edx] + mov esi, [edx + 4] + mov edi, [edx + 8] + mov ebp, [edx + 12] + mov esp, [edx + 16] + jmp dword [edx + 20] ; restore "eip" + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ModU64x32.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ModU64x32.c new file mode 100644 index 000000000..26a19cbd9 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ModU64x32.c @@ -0,0 +1,42 @@ +/** @file + Calculate the remainder of a 64-bit integer by a 32-bit integer + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Divides a 64-bit unsigned integer by a 32-bit unsigned integer and + generates a 32-bit unsigned remainder. + + This function divides the 64-bit unsigned value Dividend by the 32-bit + unsigned value Divisor and generates a 32-bit remainder. This function + returns the 32-bit unsigned remainder. + + @param Dividend A 64-bit unsigned value. + @param Divisor A 32-bit unsigned value. + + @return Dividend % Divisor + +**/ +UINT32 +EFIAPI +InternalMathModU64x32 ( + IN UINT64 Dividend, + IN UINT32 Divisor + ) +{ + _asm { + mov eax, dword ptr [Dividend + 4] + mov ecx, Divisor + xor edx, edx + div ecx + mov eax, dword ptr [Dividend + 0] + div ecx + mov eax, edx + } +} diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ModU64x32.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ModU64x32.nasm new file mode 100644 index 000000000..9f05fded3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ModU64x32.nasm @@ -0,0 +1,36 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; DivU64x32.asm +; +; Abstract: +; +; Calculate the remainder of a 64-bit integer by a 32-bit integer +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT32 +; EFIAPI +; InternalMathModU64x32 ( +; IN UINT64 Dividend, +; IN UINT32 Divisor +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalMathModU64x32) +ASM_PFX(InternalMathModU64x32): + mov eax, [esp + 8] + mov ecx, [esp + 12] + xor edx, edx + div ecx + mov eax, [esp + 4] + div ecx + mov eax, edx + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Monitor.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Monitor.c new file mode 100644 index 000000000..966b128a3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Monitor.c @@ -0,0 +1,42 @@ +/** @file + AsmMonitor function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Sets up a monitor buffer that is used by AsmMwait(). + + Executes a MONITOR instruction with the register state specified by Eax, Ecx + and Edx. Returns Eax. This function is only available on IA-32 and x64. + + @param RegisterEax The value to load into EAX or RAX before executing the MONITOR + instruction. + @param RegisterEcx The value to load into ECX or RCX before executing the MONITOR + instruction. + @param RegisterEdx The value to load into EDX or RDX before executing the MONITOR + instruction. + + @return RegisterEax + +**/ +UINTN +EFIAPI +AsmMonitor ( + IN UINTN RegisterEax, + IN UINTN RegisterEcx, + IN UINTN RegisterEdx + ) +{ + _asm { + mov eax, RegisterEax + mov ecx, RegisterEcx + mov edx, RegisterEdx + _emit 0x0f // monitor + _emit 0x01 + _emit 0xc8 + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Monitor.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Monitor.nasm new file mode 100644 index 000000000..28dc0ba70 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Monitor.nasm @@ -0,0 +1,36 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; Monitor.Asm +; +; Abstract: +; +; AsmMonitor function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmMonitor ( +; IN UINTN Eax, +; IN UINTN Ecx, +; IN UINTN Edx +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmMonitor) +ASM_PFX(AsmMonitor): + mov eax, [esp + 4] + mov ecx, [esp + 8] + mov edx, [esp + 12] + DB 0xf, 1, 0xc8 ; monitor + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x32.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x32.c new file mode 100644 index 000000000..a72868464 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x32.c @@ -0,0 +1,41 @@ +/** @file + Calculate the product of a 64-bit integer and a 32-bit integer + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Multiples a 64-bit unsigned integer by a 32-bit unsigned integer + and generates a 64-bit unsigned result. + + This function multiples the 64-bit unsigned value Multiplicand by the 32-bit + unsigned value Multiplier and generates a 64-bit unsigned result. This 64- + bit unsigned result is returned. + + @param Multiplicand A 64-bit unsigned value. + @param Multiplier A 32-bit unsigned value. + + @return Multiplicand * Multiplier + +**/ +UINT64 +EFIAPI +InternalMathMultU64x32 ( + IN UINT64 Multiplicand, + IN UINT32 Multiplier + ) +{ + _asm { + mov ecx, Multiplier + mov eax, ecx + imul ecx, dword ptr [Multiplicand + 4] // overflow not detectable + mul dword ptr [Multiplicand + 0] + add edx, ecx + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x32.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x32.nasm new file mode 100644 index 000000000..f7591b120 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x32.nasm @@ -0,0 +1,34 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; MultU64x32.nasm +; +; Abstract: +; +; Calculate the product of a 64-bit integer and a 32-bit integer +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; InternalMathMultU64x32 ( +; IN UINT64 Multiplicand, +; IN UINT32 Multiplier +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalMathMultU64x32) +ASM_PFX(InternalMathMultU64x32): + mov ecx, [esp + 12] + mov eax, ecx + imul ecx, [esp + 8] ; overflow not detectable + mul dword [esp + 4] + add edx, ecx + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x64.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x64.c new file mode 100644 index 000000000..806cbd565 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x64.c @@ -0,0 +1,45 @@ +/** @file + Calculate the product of a 64-bit integer and another 64-bit integer + + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Multiplies a 64-bit unsigned integer by a 64-bit unsigned integer + and generates a 64-bit unsigned result. + + This function multiplies the 64-bit unsigned value Multiplicand by the 64-bit + unsigned value Multiplier and generates a 64-bit unsigned result. This 64- + bit unsigned result is returned. + + @param Multiplicand A 64-bit unsigned value. + @param Multiplier A 64-bit unsigned value. + + @return Multiplicand * Multiplier + +**/ +UINT64 +EFIAPI +InternalMathMultU64x64 ( + IN UINT64 Multiplicand, + IN UINT64 Multiplier + ) +{ + _asm { + mov ebx, dword ptr [Multiplicand + 0] + mov edx, dword ptr [Multiplier + 0] + mov ecx, ebx + mov eax, edx + imul ebx, dword ptr [Multiplier + 4] + imul edx, dword ptr [Multiplicand + 4] + add ebx, edx + mul ecx + add edx, ebx + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x64.nasm new file mode 100644 index 000000000..c128022f9 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x64.nasm @@ -0,0 +1,40 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; MultU64x64.nasm +; +; Abstract: +; +; Calculate the product of a 64-bit integer and another 64-bit integer +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; InternalMathMultU64x64 ( +; IN UINT64 Multiplicand, +; IN UINT64 Multiplier +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalMathMultU64x64) +ASM_PFX(InternalMathMultU64x64): + push ebx + mov ebx, [esp + 8] ; ebx <- M1[0..31] + mov edx, [esp + 16] ; edx <- M2[0..31] + mov ecx, ebx + mov eax, edx + imul ebx, [esp + 20] ; ebx <- M1[0..31] * M2[32..63] + imul edx, [esp + 12] ; edx <- M1[32..63] * M2[0..31] + add ebx, edx ; carries are abandoned + mul ecx ; edx:eax <- M1[0..31] * M2[0..31] + add edx, ebx ; carries are abandoned + pop ebx + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Mwait.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Mwait.c new file mode 100644 index 000000000..08c666f79 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Mwait.c @@ -0,0 +1,38 @@ +/** @file + AsmMwait function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Executes an MWAIT instruction. + + Executes an MWAIT instruction with the register state specified by Eax and + Ecx. Returns Eax. This function is only available on IA-32 and x64. + + @param RegisterEax The value to load into EAX or RAX before executing the MONITOR + instruction. + @param RegisterEcx The value to load into ECX or RCX before executing the MONITOR + instruction. + + @return RegisterEax + +**/ +UINTN +EFIAPI +AsmMwait ( + IN UINTN RegisterEax, + IN UINTN RegisterEcx + ) +{ + _asm { + mov eax, RegisterEax + mov ecx, RegisterEcx + _emit 0x0f // mwait + _emit 0x01 + _emit 0xC9 + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Mwait.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Mwait.nasm new file mode 100644 index 000000000..3956940ca --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Mwait.nasm @@ -0,0 +1,34 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; Mwait.Asm +; +; Abstract: +; +; AsmMwait function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmMwait ( +; IN UINTN Eax, +; IN UINTN Ecx +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmMwait) +ASM_PFX(AsmMwait): + mov eax, [esp + 4] + mov ecx, [esp + 8] + DB 0xf, 1, 0xc9 ; mwait + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Non-existing.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Non-existing.c new file mode 100644 index 000000000..889ece463 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Non-existing.c @@ -0,0 +1,51 @@ +/** @file + Non-existing BaseLib functions on Ia32 + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +/** + Disables the 64-bit paging mode on the CPU. + + Disables the 64-bit paging mode on the CPU and returns to 32-bit protected + mode. This function assumes the current execution mode is 64-paging mode. + This function is only available on x64. After the 64-bit paging mode is + disabled, control is transferred to the function specified by EntryPoint + using the new stack specified by NewStack and passing in the parameters + specified by Context1 and Context2. Context1 and Context2 are optional and + may be 0. The function EntryPoint must never return. + + @param CodeSelector The 16-bit selector to load in the CS before EntryPoint + is called. The descriptor in the GDT that this selector + references must be setup for 32-bit protected mode. + @param EntryPoint The 64-bit virtual address of the function to call with + the new stack after paging is disabled. + @param Context1 The 64-bit virtual address of the context to pass into + the EntryPoint function as the first parameter after + paging is disabled. + @param Context2 The 64-bit virtual address of the context to pass into + the EntryPoint function as the second parameter after + paging is disabled. + @param NewStack The 64-bit virtual address of the new stack to use for + the EntryPoint function after paging is disabled. + +**/ +VOID +EFIAPI +InternalX86DisablePaging64 ( + IN UINT16 CodeSelector, + IN UINT32 EntryPoint, + IN UINT32 Context1, OPTIONAL + IN UINT32 Context2, OPTIONAL + IN UINT32 NewStack + ) +{ + // + // This function cannot work on IA32 platform + // + ASSERT (FALSE); +} diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/RRotU64.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RRotU64.c new file mode 100644 index 000000000..82711a5f8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RRotU64.c @@ -0,0 +1,49 @@ +/** @file + 64-bit right rotation for Ia32 + + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Rotates a 64-bit integer right between 0 and 63 bits, filling + the high bits with the high low bits that were rotated. + + This function rotates the 64-bit value Operand to the right by Count bits. + The high Count bits are fill with the low Count bits of Operand. The rotated + value is returned. + + @param Operand The 64-bit operand to rotate right. + @param Count The number of bits to rotate right. + + @return Operand >>> Count + +**/ +UINT64 +EFIAPI +InternalMathRRotU64 ( + IN UINT64 Operand, + IN UINTN Count + ) +{ + _asm { + mov cl, byte ptr [Count] + mov eax, dword ptr [Operand + 0] + mov edx, dword ptr [Operand + 4] + shrd ebx, eax, cl + shrd eax, edx, cl + rol ebx, cl + shrd edx, ebx, cl + test cl, 32 // Count >= 32? + jz L0 + mov ecx, eax + mov eax, edx + mov edx, ecx +L0: + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/RRotU64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RRotU64.nasm new file mode 100644 index 000000000..7e4646e1e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RRotU64.nasm @@ -0,0 +1,44 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; RRotU64.nasm +; +; Abstract: +; +; 64-bit right rotation for Ia32 +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; InternalMathRRotU64 ( +; IN UINT64 Operand, +; IN UINTN Count +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalMathRRotU64) +ASM_PFX(InternalMathRRotU64): + push ebx + mov cl, [esp + 16] + mov eax, [esp + 8] + mov edx, [esp + 12] + shrd ebx, eax, cl + shrd eax, edx, cl + rol ebx, cl + shrd edx, ebx, cl + test cl, 32 ; Count >= 32? + jz .0 + mov ecx, eax ; switch eax & edx if Count >= 32 + mov eax, edx + mov edx, ecx +.0: + pop ebx + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/RShiftU64.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RShiftU64.c new file mode 100644 index 000000000..35d843705 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RShiftU64.c @@ -0,0 +1,45 @@ +/** @file + 64-bit logical right shift function for IA-32 + + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Shifts a 64-bit integer right between 0 and 63 bits. This high bits + are filled with zeros. The shifted value is returned. + + This function shifts the 64-bit value Operand to the right by Count bits. The + high Count bits are set to zero. The shifted value is returned. + + @param Operand The 64-bit operand to shift right. + @param Count The number of bits to shift right. + + @return Operand >> Count + +**/ +UINT64 +EFIAPI +InternalMathRShiftU64 ( + IN UINT64 Operand, + IN UINTN Count + ) +{ + _asm { + mov cl, byte ptr [Count] + xor edx, edx + mov eax, dword ptr [Operand + 4] + test cl, 32 + jnz L0 + mov edx, eax + mov eax, dword ptr [Operand + 0] +L0: + shrd eax, edx, cl + shr edx, cl + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/RShiftU64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RShiftU64.nasm new file mode 100644 index 000000000..ef30e7f33 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RShiftU64.nasm @@ -0,0 +1,39 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; RShiftU64.nasm +; +; Abstract: +; +; 64-bit logical right shift function for IA-32 +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; InternalMathRShiftU64 ( +; IN UINT64 Operand, +; IN UINTN Count +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalMathRShiftU64) +ASM_PFX(InternalMathRShiftU64): + mov cl, [esp + 12] ; cl <- Count + xor edx, edx + mov eax, [esp + 8] + test cl, 32 ; Count >= 32? + jnz .0 + mov edx, eax + mov eax, [esp + 4] +.0: + shrd eax, edx, cl + shr edx, cl + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/RdRand.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RdRand.nasm new file mode 100644 index 000000000..e12b8e961 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RdRand.nasm @@ -0,0 +1,84 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; RdRand.nasm +; +; Abstract: +; +; Generates random number through CPU RdRand instruction under 32-bit platform. +; +; Notes: +; +;------------------------------------------------------------------------------ + +SECTION .text + +;------------------------------------------------------------------------------ +; Generates a 16 bit random number through RDRAND instruction. +; Return TRUE if Rand generated successfully, or FALSE if not. +; +; BOOLEAN EFIAPI InternalX86RdRand16 (UINT16 *Rand); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalX86RdRand16) +ASM_PFX(InternalX86RdRand16): + ; rdrand ax ; generate a 16 bit RN into ax + ; CF=1 if RN generated ok, otherwise CF=0 + db 0xf, 0xc7, 0xf0 ; rdrand r16: "0f c7 /6 ModRM:r/m(w)" + jc rn16_ok ; jmp if CF=1 + xor eax, eax ; reg=0 if CF=0 + ret ; return with failure status +rn16_ok: + mov edx, dword [esp + 4] + mov [edx], ax + mov eax, 1 + ret + +;------------------------------------------------------------------------------ +; Generates a 32 bit random number through RDRAND instruction. +; Return TRUE if Rand generated successfully, or FALSE if not. +; +; BOOLEAN EFIAPI InternalX86RdRand32 (UINT32 *Rand); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalX86RdRand32) +ASM_PFX(InternalX86RdRand32): + ; rdrand eax ; generate a 32 bit RN into eax + ; CF=1 if RN generated ok, otherwise CF=0 + db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 ModRM:r/m(w)" + jc rn32_ok ; jmp if CF=1 + xor eax, eax ; reg=0 if CF=0 + ret ; return with failure status +rn32_ok: + mov edx, dword [esp + 4] + mov [edx], eax + mov eax, 1 + ret + +;------------------------------------------------------------------------------ +; Generates a 64 bit random number through RDRAND instruction. +; Return TRUE if Rand generated successfully, or FALSE if not. +; +; BOOLEAN EFIAPI InternalX86RdRand64 (UINT64 *Rand); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalX86RdRand64) +ASM_PFX(InternalX86RdRand64): + ; rdrand eax ; generate a 32 bit RN into eax + ; CF=1 if RN generated ok, otherwise CF=0 + db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 ModRM:r/m(w)" + jnc rn64_ret ; jmp if CF=0 + mov edx, dword [esp + 4] + mov [edx], eax + + db 0xf, 0xc7, 0xf0 ; generate another 32 bit RN + jnc rn64_ret ; jmp if CF=0 + mov [edx + 4], eax + + mov eax, 1 + ret +rn64_ret: + xor eax, eax + ret ; return with failure status + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr0.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr0.c new file mode 100644 index 000000000..4a37c7b02 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr0.c @@ -0,0 +1,31 @@ +/** @file + AsmReadCr0 function + + Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of the Control Register 0 (CR0). + + Reads and returns the current value of CR0. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of the Control Register 0 (CR0). + +**/ +UINTN +EFIAPI +AsmReadCr0 ( + VOID + ) +{ + __asm { + mov eax, cr0 + } +} diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr0.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr0.nasm new file mode 100644 index 000000000..8303313f2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr0.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadCr0.Asm +; +; Abstract: +; +; AsmReadCr0 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmReadCr0 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadCr0) +ASM_PFX(AsmReadCr0): + mov eax, cr0 + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr2.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr2.c new file mode 100644 index 000000000..feab38055 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr2.c @@ -0,0 +1,32 @@ +/** @file + AsmReadCr2 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of the Control Register 2 (CR2). + + Reads and returns the current value of CR2. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of the Control Register 2 (CR2). + +**/ +UINTN +EFIAPI +AsmReadCr2 ( + VOID + ) +{ + __asm { + mov eax, cr2 + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr2.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr2.nasm new file mode 100644 index 000000000..202fb53ee --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr2.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadCr2.Asm +; +; Abstract: +; +; AsmReadCr2 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmReadCr2 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadCr2) +ASM_PFX(AsmReadCr2): + mov eax, cr2 + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr3.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr3.c new file mode 100644 index 000000000..b00e32491 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr3.c @@ -0,0 +1,32 @@ +/** @file + AsmReadCr3 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of the Control Register 3 (CR3). + + Reads and returns the current value of CR3. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of the Control Register 3 (CR3). + +**/ +UINTN +EFIAPI +AsmReadCr3 ( + VOID + ) +{ + __asm { + mov eax, cr3 + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr3.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr3.nasm new file mode 100644 index 000000000..67b80ea9a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr3.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadCr3.Asm +; +; Abstract: +; +; AsmReadCr3 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmReadCr3 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadCr3) +ASM_PFX(AsmReadCr3): + mov eax, cr3 + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr4.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr4.c new file mode 100644 index 000000000..f948f82b7 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr4.c @@ -0,0 +1,34 @@ +/** @file + AsmReadCr4 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of the Control Register 4 (CR4). + + Reads and returns the current value of CR4. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of the Control Register 4 (CR4). + +**/ +UINTN +EFIAPI +AsmReadCr4 ( + VOID + ) +{ + __asm { + _emit 0x0f // mov eax, cr4 + _emit 0x20 + _emit 0xE0 + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr4.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr4.nasm new file mode 100644 index 000000000..8202da7c6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr4.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadCr4.Asm +; +; Abstract: +; +; AsmReadCr4 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmReadCr4 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadCr4) +ASM_PFX(AsmReadCr4): + mov eax, cr4 + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCs.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCs.c new file mode 100644 index 000000000..02f23f5f1 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCs.c @@ -0,0 +1,32 @@ +/** @file + AsmReadCs function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of Code Segment Register (CS). + + Reads and returns the current value of CS. This function is only available on + IA-32 and x64. + + @return The current value of CS. + +**/ +UINT16 +EFIAPI +AsmReadCs ( + VOID + ) +{ + __asm { + xor eax, eax + mov ax, cs + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCs.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCs.nasm new file mode 100644 index 000000000..8c2a3f08b --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCs.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadCs.Asm +; +; Abstract: +; +; AsmReadCs function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT16 +; EFIAPI +; AsmReadCs ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadCs) +ASM_PFX(AsmReadCs): + mov eax, cs + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr0.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr0.c new file mode 100644 index 000000000..5418f92a3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr0.c @@ -0,0 +1,32 @@ +/** @file + AsmReadDr0 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of Debug Register 0 (DR0). + + Reads and returns the current value of DR0. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of Debug Register 0 (DR0). + +**/ +UINTN +EFIAPI +AsmReadDr0 ( + VOID + ) +{ + __asm { + mov eax, dr0 + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr0.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr0.nasm new file mode 100644 index 000000000..ab700fc41 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr0.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadDr0.Asm +; +; Abstract: +; +; AsmReadDr0 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmReadDr0 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadDr0) +ASM_PFX(AsmReadDr0): + mov eax, dr0 + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr1.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr1.c new file mode 100644 index 000000000..d72adaadb --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr1.c @@ -0,0 +1,32 @@ +/** @file + AsmReadDr1 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of Debug Register 1 (DR1). + + Reads and returns the current value of DR1. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of Debug Register 1 (DR1). + +**/ +UINTN +EFIAPI +AsmReadDr1 ( + VOID + ) +{ + __asm { + mov eax, dr1 + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr1.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr1.nasm new file mode 100644 index 000000000..594aa73a2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr1.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadDr1.Asm +; +; Abstract: +; +; AsmReadDr1 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmReadDr1 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadDr1) +ASM_PFX(AsmReadDr1): + mov eax, dr1 + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr2.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr2.c new file mode 100644 index 000000000..fde799728 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr2.c @@ -0,0 +1,32 @@ +/** @file + AsmReadDr2 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of Debug Register 2 (DR2). + + Reads and returns the current value of DR2. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of Debug Register 2 (DR2). + +**/ +UINTN +EFIAPI +AsmReadDr2 ( + VOID + ) +{ + __asm { + mov eax, dr2 + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr2.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr2.nasm new file mode 100644 index 000000000..ec7eb5d47 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr2.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadDr2.Asm +; +; Abstract: +; +; AsmReadDr2 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmReadDr2 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadDr2) +ASM_PFX(AsmReadDr2): + mov eax, dr2 + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr3.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr3.c new file mode 100644 index 000000000..9b899e79c --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr3.c @@ -0,0 +1,32 @@ +/** @file + AsmReadDr3 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of Debug Register 3 (DR3). + + Reads and returns the current value of DR3. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of Debug Register 3 (DR3). + +**/ +UINTN +EFIAPI +AsmReadDr3 ( + VOID + ) +{ + __asm { + mov eax, dr3 + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr3.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr3.nasm new file mode 100644 index 000000000..9e79ef6e1 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr3.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadDr3.Asm +; +; Abstract: +; +; AsmReadDr3 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmReadDr3 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadDr3) +ASM_PFX(AsmReadDr3): + mov eax, dr3 + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr4.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr4.c new file mode 100644 index 000000000..52293d335 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr4.c @@ -0,0 +1,34 @@ +/** @file + AsmReadDr4 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of Debug Register 4 (DR4). + + Reads and returns the current value of DR4. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of Debug Register 4 (DR4). + +**/ +UINTN +EFIAPI +AsmReadDr4 ( + VOID + ) +{ + __asm { + _emit 0x0f + _emit 0x21 + _emit 0xe0 + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm new file mode 100644 index 000000000..81c681de3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm @@ -0,0 +1,38 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadDr4.Asm +; +; Abstract: +; +; AsmReadDr4 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmReadDr4 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadDr4) +ASM_PFX(AsmReadDr4): + ; + ; DR4 is alias to DR6 only if DE (in CR4) is cleared. Otherwise, reading + ; this register will cause a #UD exception. + ; + ; MS assembler doesn't support this instruction since no one would use it + ; under normal circustances. Here opcode is used. + ; + DB 0xf, 0x21, 0xe0 + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr5.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr5.c new file mode 100644 index 000000000..ecf6dc2d2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr5.c @@ -0,0 +1,34 @@ +/** @file + AsmReadDr5 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of Debug Register 5 (DR5). + + Reads and returns the current value of DR5. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of Debug Register 5 (DR5). + +**/ +UINTN +EFIAPI +AsmReadDr5 ( + VOID + ) +{ + __asm { + _emit 0x0f + _emit 0x21 + _emit 0xe8 + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm new file mode 100644 index 000000000..e2deacb83 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm @@ -0,0 +1,38 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadDr5.Asm +; +; Abstract: +; +; AsmReadDr5 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmReadDr5 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadDr5) +ASM_PFX(AsmReadDr5): + ; + ; DR5 is alias to DR7 only if DE (in CR4) is cleared. Otherwise, reading + ; this register will cause a #UD exception. + ; + ; MS assembler doesn't support this instruction since no one would use it + ; under normal circustances. Here opcode is used. + ; + DB 0xf, 0x21, 0xe8 + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr6.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr6.c new file mode 100644 index 000000000..2b082970f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr6.c @@ -0,0 +1,32 @@ +/** @file + AsmReadDr6 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of Debug Register 6 (DR6). + + Reads and returns the current value of DR6. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of Debug Register 6 (DR6). + +**/ +UINTN +EFIAPI +AsmReadDr6 ( + VOID + ) +{ + __asm { + mov eax, dr6 + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr6.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr6.nasm new file mode 100644 index 000000000..a3e38aa11 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr6.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadDr6.Asm +; +; Abstract: +; +; AsmReadDr6 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmReadDr6 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadDr6) +ASM_PFX(AsmReadDr6): + mov eax, dr6 + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr7.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr7.c new file mode 100644 index 000000000..8be80482f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr7.c @@ -0,0 +1,32 @@ +/** @file + AsmReadDr7 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of Debug Register 7 (DR7). + + Reads and returns the current value of DR7. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of Debug Register 7 (DR7). + +**/ +UINTN +EFIAPI +AsmReadDr7 ( + VOID + ) +{ + __asm { + mov eax, dr7 + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr7.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr7.nasm new file mode 100644 index 000000000..6cbbb484e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr7.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadDr7.Asm +; +; Abstract: +; +; AsmReadDr7 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmReadDr7 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadDr7) +ASM_PFX(AsmReadDr7): + mov eax, dr7 + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDs.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDs.c new file mode 100644 index 000000000..3cdada3ac --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDs.c @@ -0,0 +1,32 @@ +/** @file + AsmReadDs function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of Data Segment Register (DS). + + Reads and returns the current value of DS. This function is only available on + IA-32 and x64. + + @return The current value of DS. + +**/ +UINT16 +EFIAPI +AsmReadDs ( + VOID + ) +{ + __asm { + xor eax, eax + mov ax, ds + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDs.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDs.nasm new file mode 100644 index 000000000..e2d3a05ec --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDs.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadDs.Asm +; +; Abstract: +; +; AsmReadDs function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT16 +; EFIAPI +; AsmReadDs ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadDs) +ASM_PFX(AsmReadDs): + mov eax, ds + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEflags.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEflags.c new file mode 100644 index 000000000..1cea323c5 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEflags.c @@ -0,0 +1,33 @@ +/** @file + AsmReadEflags function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of the EFLAGS register. + + Reads and returns the current value of the EFLAGS register. This function is + only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a + 64-bit value on x64. + + @return EFLAGS on IA-32 or RFLAGS on x64. + +**/ +UINTN +EFIAPI +AsmReadEflags ( + VOID + ) +{ + __asm { + pushfd + pop eax + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEflags.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEflags.nasm new file mode 100644 index 000000000..05dca3fa6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEflags.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadEflags.Asm +; +; Abstract: +; +; AsmReadEflags function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmReadEflags ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadEflags) +ASM_PFX(AsmReadEflags): + pushfd + pop eax + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEs.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEs.c new file mode 100644 index 000000000..30953fdf3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEs.c @@ -0,0 +1,32 @@ +/** @file + AsmReadEs function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of ES Data Segment Register (ES). + + Reads and returns the current value of ES. This function is only available on + IA-32 and x64. + + @return The current value of ES. + +**/ +UINT16 +EFIAPI +AsmReadEs ( + VOID + ) +{ + __asm { + xor eax, eax + mov ax, es + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEs.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEs.nasm new file mode 100644 index 000000000..5228298cf --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEs.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadEs.Asm +; +; Abstract: +; +; AsmReadEs function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT16 +; EFIAPI +; AsmReadEs ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadEs) +ASM_PFX(AsmReadEs): + mov eax, es + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadFs.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadFs.c new file mode 100644 index 000000000..51fb020b1 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadFs.c @@ -0,0 +1,32 @@ +/** @file + AsmReadFs function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of FS Data Segment Register (FS). + + Reads and returns the current value of FS. This function is only available on + IA-32 and x64. + + @return The current value of FS. + +**/ +UINT16 +EFIAPI +AsmReadFs ( + VOID + ) +{ + __asm { + xor eax, eax + mov ax, fs + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadFs.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadFs.nasm new file mode 100644 index 000000000..fa7fbc351 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadFs.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadFs.Asm +; +; Abstract: +; +; AsmReadFs function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT16 +; EFIAPI +; AsmReadFs ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadFs) +ASM_PFX(AsmReadFs): + mov eax, fs + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGdtr.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGdtr.c new file mode 100644 index 000000000..5b01300b4 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGdtr.c @@ -0,0 +1,33 @@ +/** @file + AsmReadGdtr function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "BaseLibInternals.h" + + +/** + Reads the current Global Descriptor Table Register(GDTR) descriptor. + + Reads and returns the current GDTR descriptor and returns it in Gdtr. This + function is only available on IA-32 and x64. + + @param Gdtr The pointer to a GDTR descriptor. + +**/ +VOID +EFIAPI +InternalX86ReadGdtr ( + OUT IA32_DESCRIPTOR *Gdtr + ) +{ + _asm { + mov eax, Gdtr + sgdt fword ptr [eax] + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGdtr.nasm new file mode 100644 index 000000000..03b03a89b --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGdtr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadGdtr.Asm +; +; Abstract: +; +; AsmReadGdtr function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; InternalX86ReadGdtr ( +; OUT IA32_DESCRIPTOR *Gdtr +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalX86ReadGdtr) +ASM_PFX(InternalX86ReadGdtr): + mov eax, [esp + 4] + sgdt [eax] + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGs.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGs.c new file mode 100644 index 000000000..6209a31ae --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGs.c @@ -0,0 +1,32 @@ +/** @file + AsmReadGs function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of GS Data Segment Register (GS). + + Reads and returns the current value of GS. This function is only available on + IA-32 and x64. + + @return The current value of GS. + +**/ +UINT16 +EFIAPI +AsmReadGs ( + VOID + ) +{ + __asm { + xor eax, eax + mov ax, gs + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGs.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGs.nasm new file mode 100644 index 000000000..b1e46deef --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGs.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadGs.Asm +; +; Abstract: +; +; AsmReadGs function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT16 +; EFIAPI +; AsmReadGs ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadGs) +ASM_PFX(AsmReadGs): + mov eax, gs + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadIdtr.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadIdtr.c new file mode 100644 index 000000000..93f44535d --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadIdtr.c @@ -0,0 +1,32 @@ +/** @file + AsmReadIdtr function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "BaseLibInternals.h" + + +/** + Reads the current Interrupt Descriptor Table Register(GDTR) descriptor. + + Reads and returns the current IDTR descriptor and returns it in Idtr. This + function is only available on IA-32 and x64. + + @param Idtr The pointer to a IDTR descriptor. + +**/ +VOID +EFIAPI +InternalX86ReadIdtr ( + OUT IA32_DESCRIPTOR *Idtr + ) +{ + _asm { + mov eax, Idtr + sidt fword ptr [eax] + } +} diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadIdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadIdtr.nasm new file mode 100644 index 000000000..9fa1c62e3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadIdtr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadIdtr.Asm +; +; Abstract: +; +; AsmReadIdtr function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; InternalX86ReadIdtr ( +; OUT IA32_DESCRIPTOR *Idtr +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalX86ReadIdtr) +ASM_PFX(InternalX86ReadIdtr): + mov eax, [esp + 4] + sidt [eax] + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadLdtr.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadLdtr.c new file mode 100644 index 000000000..407676a46 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadLdtr.c @@ -0,0 +1,31 @@ +/** @file + AsmReadLdtr function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current Local Descriptor Table Register(LDTR) selector. + + Reads and returns the current 16-bit LDTR descriptor value. This function is + only available on IA-32 and x64. + + @return The current selector of LDT. + +**/ +UINT16 +EFIAPI +AsmReadLdtr ( + VOID + ) +{ + _asm { + sldt ax + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadLdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadLdtr.nasm new file mode 100644 index 000000000..c1e169b65 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadLdtr.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadLdtr.Asm +; +; Abstract: +; +; AsmReadLdtr function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT16 +; EFIAPI +; AsmReadLdtr ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadLdtr) +ASM_PFX(AsmReadLdtr): + sldt ax + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm0.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm0.c new file mode 100644 index 000000000..00dfe0589 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm0.c @@ -0,0 +1,36 @@ +/** @file + AsmReadMm0 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of 64-bit MMX Register #0 (MM0). + + Reads and returns the current value of MM0. This function is only available + on IA-32 and x64. + + @return The current value of MM0. + +**/ +UINT64 +EFIAPI +AsmReadMm0 ( + VOID + ) +{ + _asm { + push eax + push eax + movq [esp], mm0 + pop eax + pop edx + emms + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm0.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm0.nasm new file mode 100644 index 000000000..36da46f43 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm0.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadMm0.Asm +; +; Abstract: +; +; AsmReadMm0 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; AsmReadMm0 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadMm0) +ASM_PFX(AsmReadMm0): + push eax + push eax + movq [esp], mm0 + pop eax + pop edx + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm1.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm1.c new file mode 100644 index 000000000..0ed311e41 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm1.c @@ -0,0 +1,36 @@ +/** @file + AsmReadMm1 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of 64-bit MMX Register #1 (MM1). + + Reads and returns the current value of MM1. This function is only available + on IA-32 and x64. + + @return The current value of MM1. + +**/ +UINT64 +EFIAPI +AsmReadMm1 ( + VOID + ) +{ + _asm { + push eax + push eax + movq [esp], mm1 + pop eax + pop edx + emms + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm1.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm1.nasm new file mode 100644 index 000000000..49ae74264 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm1.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadMm1.Asm +; +; Abstract: +; +; AsmReadMm1 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; AsmReadMm1 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadMm1) +ASM_PFX(AsmReadMm1): + push eax + push eax + movq [esp], mm1 + pop eax + pop edx + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm2.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm2.c new file mode 100644 index 000000000..bd830c557 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm2.c @@ -0,0 +1,36 @@ +/** @file + AsmReadMm2 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of 64-bit MMX Register #2 (MM2). + + Reads and returns the current value of MM2. This function is only available + on IA-32 and x64. + + @return The current value of MM2. + +**/ +UINT64 +EFIAPI +AsmReadMm2 ( + VOID + ) +{ + _asm { + push eax + push eax + movq [esp], mm2 + pop eax + pop edx + emms + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm2.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm2.nasm new file mode 100644 index 000000000..3023592a6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm2.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadMm2.Asm +; +; Abstract: +; +; AsmReadMm2 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; AsmReadMm2 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadMm2) +ASM_PFX(AsmReadMm2): + push eax + push eax + movq [esp], mm2 + pop eax + pop edx + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm3.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm3.c new file mode 100644 index 000000000..c8967083b --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm3.c @@ -0,0 +1,36 @@ +/** @file + AsmReadMm3 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of 64-bit MMX Register #3 (MM3). + + Reads and returns the current value of MM3. This function is only available + on IA-32 and x64. + + @return The current value of MM3. + +**/ +UINT64 +EFIAPI +AsmReadMm3 ( + VOID + ) +{ + _asm { + push eax + push eax + movq [esp], mm3 + pop eax + pop edx + emms + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm3.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm3.nasm new file mode 100644 index 000000000..339468cc0 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm3.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadMm3.Asm +; +; Abstract: +; +; AsmReadMm3 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; AsmReadMm3 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadMm3) +ASM_PFX(AsmReadMm3): + push eax + push eax + movq [esp], mm3 + pop eax + pop edx + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm4.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm4.c new file mode 100644 index 000000000..9e2794cd4 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm4.c @@ -0,0 +1,36 @@ +/** @file + AsmReadMm4 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of 64-bit MMX Register #4 (MM4). + + Reads and returns the current value of MM4. This function is only available + on IA-32 and x64. + + @return The current value of MM4. + +**/ +UINT64 +EFIAPI +AsmReadMm4 ( + VOID + ) +{ + _asm { + push eax + push eax + movq [esp], mm4 + pop eax + pop edx + emms + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm4.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm4.nasm new file mode 100644 index 000000000..53da33a3f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm4.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadMm4.Asm +; +; Abstract: +; +; AsmReadMm4 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; AsmReadMm4 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadMm4) +ASM_PFX(AsmReadMm4): + push eax + push eax + movq [esp], mm4 + pop eax + pop edx + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm5.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm5.c new file mode 100644 index 000000000..93cad05a4 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm5.c @@ -0,0 +1,36 @@ +/** @file + AsmReadMm5 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of 64-bit MMX Register #5 (MM5). + + Reads and returns the current value of MM5. This function is only available + on IA-32 and x64. + + @return The current value of MM5. + +**/ +UINT64 +EFIAPI +AsmReadMm5 ( + VOID + ) +{ + _asm { + push eax + push eax + movq [esp], mm5 + pop eax + pop edx + emms + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm5.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm5.nasm new file mode 100644 index 000000000..dd1e87cf8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm5.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadMm5.Asm +; +; Abstract: +; +; AsmReadMm5 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; AsmReadMm5 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadMm5) +ASM_PFX(AsmReadMm5): + push eax + push eax + movq [esp], mm5 + pop eax + pop edx + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm6.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm6.c new file mode 100644 index 000000000..d2c559163 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm6.c @@ -0,0 +1,36 @@ +/** @file + AsmReadMm6 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of 64-bit MMX Register #6 (MM6). + + Reads and returns the current value of MM6. This function is only available + on IA-32 and x64. + + @return The current value of MM6. + +**/ +UINT64 +EFIAPI +AsmReadMm6 ( + VOID + ) +{ + _asm { + push eax + push eax + movq [esp], mm6 + pop eax + pop edx + emms + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm6.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm6.nasm new file mode 100644 index 000000000..1b43d056e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm6.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadMm6.Asm +; +; Abstract: +; +; AsmReadMm6 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; AsmReadMm6 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadMm6) +ASM_PFX(AsmReadMm6): + push eax + push eax + movq [esp], mm6 + pop eax + pop edx + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm7.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm7.c new file mode 100644 index 000000000..68cf03928 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm7.c @@ -0,0 +1,36 @@ +/** @file + AsmReadMm7 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of 64-bit MMX Register #7 (MM7). + + Reads and returns the current value of MM7. This function is only available + on IA-32 and x64. + + @return The current value of MM7. + +**/ +UINT64 +EFIAPI +AsmReadMm7 ( + VOID + ) +{ + _asm { + push eax + push eax + movq [esp], mm7 + pop eax + pop edx + emms + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm7.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm7.nasm new file mode 100644 index 000000000..3df4c9fc8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm7.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadMm7.Asm +; +; Abstract: +; +; AsmReadMm7 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; AsmReadMm7 ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadMm7) +ASM_PFX(AsmReadMm7): + push eax + push eax + movq [esp], mm7 + pop eax + pop edx + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c new file mode 100644 index 000000000..6d2394b1a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c @@ -0,0 +1,37 @@ +/** @file + AsmReadMsr64 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Returns a 64-bit Machine Specific Register(MSR). + + Reads and returns the 64-bit MSR specified by Index. No parameter checking is + performed on Index, and some Index values may cause CPU exceptions. The + caller must either guarantee that Index is valid, or the caller must set up + exception handlers to catch the exceptions. This function is only available + on IA-32 and x64. + + @param Index The 32-bit MSR index to read. + + @return The value of the MSR identified by Index. + +**/ +UINT64 +EFIAPI +AsmReadMsr64 ( + IN UINT32 Index + ) +{ + _asm { + mov ecx, Index + rdmsr + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMsr64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMsr64.nasm new file mode 100644 index 000000000..97b853a3a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMsr64.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadMsr64.Asm +; +; Abstract: +; +; AsmReadMsr64 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; AsmReadMsr64 ( +; IN UINT64 Index +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadMsr64) +ASM_PFX(AsmReadMsr64): + mov ecx, [esp + 4] + rdmsr + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadPmc.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadPmc.c new file mode 100644 index 000000000..cc09ed700 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadPmc.c @@ -0,0 +1,31 @@ +/** @file + AsmReadPmc function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Reads the current value of a Performance Counter (PMC). + + Reads and returns the current value of performance counter specified by + Index. This function is only available on IA-32 and x64. + + @param Index The 32-bit Performance Counter index to read. + + @return The value of the PMC specified by Index. + +**/ +UINT64 +EFIAPI +AsmReadPmc ( + IN UINT32 Index + ) +{ + _asm { + mov ecx, Index + rdpmc + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadPmc.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadPmc.nasm new file mode 100644 index 000000000..53142e33f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadPmc.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadPmc.Asm +; +; Abstract: +; +; AsmReadPmc function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; AsmReadPmc ( +; IN UINT32 PmcIndex +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadPmc) +ASM_PFX(AsmReadPmc): + mov ecx, [esp + 4] + rdpmc + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadSs.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadSs.c new file mode 100644 index 000000000..9d7a6411a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadSs.c @@ -0,0 +1,32 @@ +/** @file + AsmReadSs function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of Stack Segment Register (SS). + + Reads and returns the current value of SS. This function is only available on + IA-32 and x64. + + @return The current value of SS. + +**/ +UINT16 +EFIAPI +AsmReadSs ( + VOID + ) +{ + __asm { + xor eax, eax + mov ax, ss + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadSs.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadSs.nasm new file mode 100644 index 000000000..61628dec3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadSs.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadSs.Asm +; +; Abstract: +; +; AsmReadSs function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT16 +; EFIAPI +; AsmReadSs ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadSs) +ASM_PFX(AsmReadSs): + mov eax, ss + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTr.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTr.c new file mode 100644 index 000000000..b52f8f31d --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTr.c @@ -0,0 +1,31 @@ +/** @file + AsmReadTr function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of Task Register (TR). + + Reads and returns the current value of TR. This function is only available on + IA-32 and x64. + + @return The current value of TR. + +**/ +UINT16 +EFIAPI +AsmReadTr ( + VOID + ) +{ + _asm { + str ax + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTr.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTr.nasm new file mode 100644 index 000000000..9f238e2ae --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTr.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadTr.Asm +; +; Abstract: +; +; AsmReadTr function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT16 +; EFIAPI +; AsmReadTr ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadTr) +ASM_PFX(AsmReadTr): + str ax + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTsc.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTsc.c new file mode 100644 index 000000000..a67b57a77 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTsc.c @@ -0,0 +1,31 @@ +/** @file + AsmReadTsc function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Reads the current value of Time Stamp Counter (TSC). + + Reads and returns the current value of TSC. This function is only available + on IA-32 and x64. + + @return The current value of TSC + +**/ +UINT64 +EFIAPI +AsmReadTsc ( + VOID + ) +{ + _asm { + rdtsc + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTsc.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTsc.nasm new file mode 100644 index 000000000..1bc875bd3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTsc.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadTsc.Asm +; +; Abstract: +; +; AsmReadTsc function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; AsmReadTsc ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadTsc) +ASM_PFX(AsmReadTsc): + rdtsc + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/SetJump.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/SetJump.nasm new file mode 100644 index 000000000..364613b5f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/SetJump.nasm @@ -0,0 +1,63 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; SetJump.Asm +; +; Abstract: +; +; Implementation of SetJump() on IA-32. +; +;------------------------------------------------------------------------------ + +%include "Nasm.inc" + + SECTION .text + +extern ASM_PFX(InternalAssertJumpBuffer) +extern ASM_PFX(PcdGet32 (PcdControlFlowEnforcementPropertyMask)) + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; SetJump ( +; OUT BASE_LIBRARY_JUMP_BUFFER *JumpBuffer +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(SetJump) +ASM_PFX(SetJump): + push DWORD [esp + 4] + call ASM_PFX(InternalAssertJumpBuffer) ; To validate JumpBuffer + pop ecx + pop ecx ; ecx <- return address + mov edx, [esp] + + xor eax, eax + mov [edx + 24], eax ; save 0 to SSP + + mov eax, [ASM_PFX(PcdGet32 (PcdControlFlowEnforcementPropertyMask))] + test eax, eax + jz CetDone + mov eax, cr4 + bt eax, 23 ; check if CET is enabled + jnc CetDone + + mov eax, 1 + INCSSP_EAX ; to read original SSP + READSSP_EAX + mov [edx + 0x24], eax ; save SSP + +CetDone: + + mov [edx], ebx + mov [edx + 4], esi + mov [edx + 8], edi + mov [edx + 12], ebp + mov [edx + 16], esp + mov [edx + 20], ecx ; eip value to restore in LongJump + xor eax, eax + jmp ecx + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/SwapBytes64.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/SwapBytes64.c new file mode 100644 index 000000000..67587f1d2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/SwapBytes64.c @@ -0,0 +1,37 @@ +/** @file + Implementation of 64-bit swap bytes + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Switches the endianess of a 64-bit integer. + + This function swaps the bytes in a 64-bit unsigned value to switch the value + from little endian to big endian or vice versa. The byte swapped value is + returned. + + @param Operand A 64-bit unsigned value. + + @return The byte swaped Operand. + +**/ +UINT64 +EFIAPI +InternalMathSwapBytes64 ( + IN UINT64 Operand + ) +{ + _asm { + mov eax, dword ptr [Operand + 4] + mov edx, dword ptr [Operand + 0] + bswap eax + bswap edx + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/SwapBytes64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/SwapBytes64.nasm new file mode 100644 index 000000000..73a109415 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/SwapBytes64.nasm @@ -0,0 +1,34 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; CpuId.Asm +; +; Abstract: +; +; AsmCpuid function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; InternalMathSwapBytes64 ( +; IN UINT64 Operand +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalMathSwapBytes64) +ASM_PFX(InternalMathSwapBytes64): + mov eax, [esp + 8] ; eax <- upper 32 bits + mov edx, [esp + 4] ; edx <- lower 32 bits + bswap eax + bswap edx + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Thunk16.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Thunk16.nasm new file mode 100644 index 000000000..03a300dc6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Thunk16.nasm @@ -0,0 +1,257 @@ + +#include "BaseLibInternals.h" + +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; Thunk.asm +; +; Abstract: +; +; Real mode thunk +; +;------------------------------------------------------------------------------ + +global ASM_PFX(m16Size) +global ASM_PFX(mThunk16Attr) +global ASM_PFX(m16Gdt) +global ASM_PFX(m16GdtrBase) +global ASM_PFX(mTransition) +global ASM_PFX(m16Start) + +struc IA32_REGS + + ._EDI: resd 1 + ._ESI: resd 1 + ._EBP: resd 1 + ._ESP: resd 1 + ._EBX: resd 1 + ._EDX: resd 1 + ._ECX: resd 1 + ._EAX: resd 1 + ._DS: resw 1 + ._ES: resw 1 + ._FS: resw 1 + ._GS: resw 1 + ._EFLAGS: resd 1 + ._EIP: resd 1 + ._CS: resw 1 + ._SS: resw 1 + .size: + +endstruc + +;; .const + +SECTION .data + +; +; These are global constant to convey information to C code. +; +ASM_PFX(m16Size) DW ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start) +ASM_PFX(mThunk16Attr) DW _BackFromUserCode.ThunkAttrEnd - 4 - ASM_PFX(m16Start) +ASM_PFX(m16Gdt) DW _NullSegDesc - ASM_PFX(m16Start) +ASM_PFX(m16GdtrBase) DW _16GdtrBase - ASM_PFX(m16Start) +ASM_PFX(mTransition) DW _EntryPoint - ASM_PFX(m16Start) + +SECTION .text + +ASM_PFX(m16Start): + +SavedGdt: + dw 0 + dd 0 + +;------------------------------------------------------------------------------ +; _BackFromUserCode() takes control in real mode after 'retf' has been executed +; by user code. It will be shadowed to somewhere in memory below 1MB. +;------------------------------------------------------------------------------ +_BackFromUserCode: + ; + ; The order of saved registers on the stack matches the order they appears + ; in IA32_REGS structure. This facilitates wrapper function to extract them + ; into that structure. + ; +BITS 16 + push ss + push cs + ; + ; Note: We can't use o32 on the next instruction because of a bug + ; in NASM 2.09.04 through 2.10rc1. + ; + call dword .Base ; push eip +.Base: + pushfd + cli ; disable interrupts + push gs + push fs + push es + push ds + pushad + mov edx, strict dword 0 +.ThunkAttrEnd: + test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 + jz .1 + mov ax, 2401h + int 15h + cli ; disable interrupts + jnc .2 +.1: + test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL + jz .2 + in al, 92h + or al, 2 + out 92h, al ; deactivate A20M# +.2: + xor eax, eax + mov ax, ss + lea ebp, [esp + IA32_REGS.size] + mov [bp - IA32_REGS.size + IA32_REGS._ESP], ebp + mov bx, [bp - IA32_REGS.size + IA32_REGS._EIP] + shl eax, 4 ; shl eax, 4 + add ebp, eax ; add ebp, eax + mov eax, strict dword 0 +.SavedCr4End: + mov cr4, eax +o32 lgdt [cs:bx + (SavedGdt - .Base)] + mov eax, strict dword 0 +.SavedCr0End: + mov cr0, eax + mov ax, strict word 0 +.SavedSsEnd: + mov ss, eax + mov esp, strict dword 0 +.SavedEspEnd: +o32 retf ; return to protected mode + +_EntryPoint: + DD _ToUserCode - ASM_PFX(m16Start) + DW 8h +_16Idtr: + DW (1 << 10) - 1 + DD 0 +_16Gdtr: + DW GdtEnd - _NullSegDesc - 1 +_16GdtrBase: + DD 0 + +;------------------------------------------------------------------------------ +; _ToUserCode() takes control in real mode before passing control to user code. +; It will be shadowed to somewhere in memory below 1MB. +;------------------------------------------------------------------------------ +_ToUserCode: +BITS 16 + mov dx, ss + mov ss, cx ; set new segment selectors + mov ds, cx + mov es, cx + mov fs, cx + mov gs, cx + mov cr0, eax ; real mode starts at next instruction + ; which (per SDM) *must* be a far JMP. + jmp 0:strict word 0 +.RealAddrEnd: + mov cr4, ebp + mov ss, si ; set up 16-bit stack segment + xchg esp, ebx ; set up 16-bit stack pointer + mov bp, [esp + IA32_REGS.size] + mov [cs:bp + (_BackFromUserCode.SavedSsEnd - 2 - _BackFromUserCode)], dx + mov [cs:bp + (_BackFromUserCode.SavedEspEnd - 4 - _BackFromUserCode)], ebx + lidt [cs:bp + (_16Idtr - _BackFromUserCode)] + + popad + pop ds + pop es + pop fs + pop gs + popfd + +o32 retf ; transfer control to user code + +ALIGN 16 +_NullSegDesc DQ 0 +_16CsDesc: + DW -1 + DW 0 + DB 0 + DB 9bh + DB 8fh ; 16-bit segment, 4GB limit + DB 0 +_16DsDesc: + DW -1 + DW 0 + DB 0 + DB 93h + DB 8fh ; 16-bit segment, 4GB limit + DB 0 +GdtEnd: + +;------------------------------------------------------------------------------ +; IA32_REGISTER_SET * +; EFIAPI +; InternalAsmThunk16 ( +; IN IA32_REGISTER_SET *RegisterSet, +; IN OUT VOID *Transition +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalAsmThunk16) +ASM_PFX(InternalAsmThunk16): +BITS 32 + push ebp + push ebx + push esi + push edi + push ds + push es + push fs + push gs + mov esi, [esp + 36] ; esi <- RegSet, the 1st parameter + movzx edx, word [esi + IA32_REGS._SS] + mov edi, [esi + IA32_REGS._ESP] + add edi, - (IA32_REGS.size + 4) ; reserve stack space + mov ebx, edi ; ebx <- stack offset + imul eax, edx, 16 ; eax <- edx * 16 + push IA32_REGS.size / 4 + add edi, eax ; edi <- linear address of 16-bit stack + pop ecx + rep movsd ; copy RegSet + mov eax, [esp + 40] ; eax <- address of transition code + mov esi, edx ; esi <- 16-bit stack segment + lea edx, [eax + (_BackFromUserCode.SavedCr0End - ASM_PFX(m16Start))] + mov ecx, eax + and ecx, 0fh + shl eax, 12 + lea ecx, [ecx + (_BackFromUserCode - ASM_PFX(m16Start))] + mov ax, cx + stosd ; [edi] <- return address of user code + add eax, _ToUserCode.RealAddrEnd - _BackFromUserCode + mov [edx + (_ToUserCode.RealAddrEnd - 4 - _BackFromUserCode.SavedCr0End)], eax + sgdt [edx + (SavedGdt - _BackFromUserCode.SavedCr0End)] + sidt [esp + 36] ; save IDT stack in argument space + mov eax, cr0 + mov [edx - 4], eax ; save CR0 in _BackFromUserCode.SavedCr0End - 4 + and eax, 7ffffffeh ; clear PE, PG bits + mov ebp, cr4 + mov [edx + (_BackFromUserCode.SavedCr4End - 4 - _BackFromUserCode.SavedCr0End)], ebp + and ebp, ~30h ; clear PAE, PSE bits + push 10h + pop ecx ; ecx <- selector for data segments + lgdt [edx + (_16Gdtr - _BackFromUserCode.SavedCr0End)] + pushfd ; Save df/if indeed + call dword far [edx + (_EntryPoint - _BackFromUserCode.SavedCr0End)] + popfd + lidt [esp + 36] ; restore protected mode IDTR + lea eax, [ebp - IA32_REGS.size] ; eax <- the address of IA32_REGS + pop gs + pop fs + pop es + pop ds + pop edi + pop esi + pop ebx + pop ebp + ret diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/VmgExit.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/VmgExit.nasm new file mode 100644 index 000000000..69f7fbf35 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/VmgExit.nasm @@ -0,0 +1,38 @@ +;------------------------------------------------------------------------------ +; +; Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; VmgExit.Asm +; +; Abstract: +; +; AsmVmgExit function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmVmgExit ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmVmgExit) +ASM_PFX(AsmVmgExit): +; +; NASM doesn't support the vmmcall instruction in 32-bit mode and NASM versions +; before 2.12 cannot translate the 64-bit "rep vmmcall" instruction into elf32 +; format. Given that VMGEXIT does not make sense on IA32, provide a stub +; implementation that is identical to CpuBreakpoint(). In practice, AsmVmgExit() +; should never be called on IA32. +; + int 3 + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Wbinvd.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Wbinvd.c new file mode 100644 index 000000000..87bd71f05 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Wbinvd.c @@ -0,0 +1,29 @@ +/** @file + AsmWbinvd function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Executes a WBINVD instruction. + + Executes a WBINVD instruction. This function is only available on IA-32 and + x64. + +**/ +VOID +EFIAPI +AsmWbinvd ( + VOID + ) +{ + _asm { + wbinvd + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Wbinvd.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Wbinvd.nasm new file mode 100644 index 000000000..714e42789 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Wbinvd.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; Wbinvd.Asm +; +; Abstract: +; +; AsmWbinvd function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmWbinvd ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWbinvd) +ASM_PFX(AsmWbinvd): + wbinvd + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr0.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr0.c new file mode 100644 index 000000000..46e49a678 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr0.c @@ -0,0 +1,31 @@ +/** @file + AsmWriteCr0 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Writes a value to Control Register 0 (CR0). + + Writes and returns a new value to CR0. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Value The value to write to CR0. + + @return The value written to CR0. + +**/ +UINTN +EFIAPI +AsmWriteCr0 ( + UINTN Value + ) +{ + _asm { + mov eax, Value + mov cr0, eax + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr0.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr0.nasm new file mode 100644 index 000000000..6730fbe37 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr0.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteCr0.Asm +; +; Abstract: +; +; AsmWriteCr0 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmWriteCr0 ( +; UINTN Cr0 +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteCr0) +ASM_PFX(AsmWriteCr0): + mov eax, [esp + 4] + mov cr0, eax + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr2.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr2.c new file mode 100644 index 000000000..f437bfc8c --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr2.c @@ -0,0 +1,31 @@ +/** @file + AsmWriteCr2 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Writes a value to Control Register 2 (CR2). + + Writes and returns a new value to CR2. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Value The value to write to CR2. + + @return The value written to CR2. + +**/ +UINTN +EFIAPI +AsmWriteCr2 ( + UINTN Value + ) +{ + _asm { + mov eax, Value + mov cr2, eax + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr2.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr2.nasm new file mode 100644 index 000000000..989639066 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr2.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteCr2.Asm +; +; Abstract: +; +; AsmWriteCr2 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmWriteCr2 ( +; UINTN Cr2 +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteCr2) +ASM_PFX(AsmWriteCr2): + mov eax, [esp + 4] + mov cr2, eax + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr3.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr3.c new file mode 100644 index 000000000..48cb8ad16 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr3.c @@ -0,0 +1,31 @@ +/** @file + AsmWriteCr3 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Writes a value to Control Register 3 (CR3). + + Writes and returns a new value to CR3. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Value The value to write to CR3. + + @return The value written to CR3. + +**/ +UINTN +EFIAPI +AsmWriteCr3 ( + UINTN Value + ) +{ + _asm { + mov eax, Value + mov cr3, eax + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr3.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr3.nasm new file mode 100644 index 000000000..21114f35c --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr3.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteCr3.Asm +; +; Abstract: +; +; AsmWriteCr3 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmWriteCr3 ( +; UINTN Cr3 +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteCr3) +ASM_PFX(AsmWriteCr3): + mov eax, [esp + 4] + mov cr3, eax + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr4.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr4.c new file mode 100644 index 000000000..01f059ffa --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr4.c @@ -0,0 +1,33 @@ +/** @file + AsmWriteCr4 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Writes a value to Control Register 4 (CR4). + + Writes and returns a new value to CR4. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Value The value to write to CR4. + + @return The value written to CR4. + +**/ +UINTN +EFIAPI +AsmWriteCr4 ( + UINTN Value + ) +{ + _asm { + mov eax, Value + _emit 0x0f // mov cr4, eax + _emit 0x22 + _emit 0xE0 + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr4.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr4.nasm new file mode 100644 index 000000000..b090606b1 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr4.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteCr4.Asm +; +; Abstract: +; +; AsmWriteCr4 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmWriteCr4 ( +; UINTN Cr4 +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteCr4) +ASM_PFX(AsmWriteCr4): + mov eax, [esp + 4] + mov cr4, eax + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr0.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr0.c new file mode 100644 index 000000000..80bb23818 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr0.c @@ -0,0 +1,31 @@ +/** @file + AsmWriteDr0 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Writes a value to Debug Register 0 (DR0). + + Writes and returns a new value to DR0. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Value The value to write to Dr0. + + @return The value written to Debug Register 0 (DR0). + +**/ +UINTN +EFIAPI +AsmWriteDr0 ( + IN UINTN Value + ) +{ + _asm { + mov eax, Value + mov dr0, eax + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr0.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr0.nasm new file mode 100644 index 000000000..24cd2c2e8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr0.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteDr0.Asm +; +; Abstract: +; +; AsmWriteDr0 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmWriteDr0 ( +; IN UINTN Value +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteDr0) +ASM_PFX(AsmWriteDr0): + mov eax, [esp + 4] + mov dr0, eax + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr1.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr1.c new file mode 100644 index 000000000..f1c8f325e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr1.c @@ -0,0 +1,31 @@ +/** @file + AsmWriteDr1 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Writes a value to Debug Register 1 (DR1). + + Writes and returns a new value to DR1. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Value The value to write to Dr1. + + @return The value written to Debug Register 1 (DR1). + +**/ +UINTN +EFIAPI +AsmWriteDr1 ( + IN UINTN Value + ) +{ + _asm { + mov eax, Value + mov dr1, eax + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr1.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr1.nasm new file mode 100644 index 000000000..57afac4f1 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr1.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteDr1.Asm +; +; Abstract: +; +; AsmWriteDr1 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmWriteDr1 ( +; IN UINTN Value +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteDr1) +ASM_PFX(AsmWriteDr1): + mov eax, [esp + 4] + mov dr1, eax + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr2.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr2.c new file mode 100644 index 000000000..6e1e7f240 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr2.c @@ -0,0 +1,31 @@ +/** @file + AsmWriteDr2 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Writes a value to Debug Register 2 (DR2). + + Writes and returns a new value to DR2. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Value The value to write to Dr2. + + @return The value written to Debug Register 2 (DR2). + +**/ +UINTN +EFIAPI +AsmWriteDr2 ( + IN UINTN Value + ) +{ + _asm { + mov eax, Value + mov dr2, eax + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr2.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr2.nasm new file mode 100644 index 000000000..3fd32a772 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr2.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteDr2.Asm +; +; Abstract: +; +; AsmWriteDr2 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmWriteDr2 ( +; IN UINTN Value +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteDr2) +ASM_PFX(AsmWriteDr2): + mov eax, [esp + 4] + mov dr2, eax + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr3.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr3.c new file mode 100644 index 000000000..7cb1d3724 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr3.c @@ -0,0 +1,31 @@ +/** @file + AsmWriteDr3 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Writes a value to Debug Register 3 (DR3). + + Writes and returns a new value to DR3. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Value The value to write to Dr3. + + @return The value written to Debug Register 3 (DR3). + +**/ +UINTN +EFIAPI +AsmWriteDr3 ( + IN UINTN Value + ) +{ + _asm { + mov eax, Value + mov dr3, eax + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr3.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr3.nasm new file mode 100644 index 000000000..73ad24a8c --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr3.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteDr3.Asm +; +; Abstract: +; +; AsmWriteDr3 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmWriteDr3 ( +; IN UINTN Value +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteDr3) +ASM_PFX(AsmWriteDr3): + mov eax, [esp + 4] + mov dr3, eax + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr4.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr4.c new file mode 100644 index 000000000..778017f33 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr4.c @@ -0,0 +1,33 @@ +/** @file + AsmWriteDr4 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Writes a value to Debug Register 4 (DR4). + + Writes and returns a new value to DR4. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Value The value to write to Dr4. + + @return The value written to Debug Register 4 (DR4). + +**/ +UINTN +EFIAPI +AsmWriteDr4 ( + IN UINTN Value + ) +{ + _asm { + mov eax, Value + _emit 0x0f // mov dr4, eax + _emit 0x23 + _emit 0xe0 + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm new file mode 100644 index 000000000..0d23fca11 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm @@ -0,0 +1,39 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteDr4.Asm +; +; Abstract: +; +; AsmWriteDr4 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmWriteDr4 ( +; IN UINTN Value +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteDr4) +ASM_PFX(AsmWriteDr4): + mov eax, [esp + 4] + ; + ; DR4 is alias to DR6 only if DE (in CR4) is cleared. Otherwise, writing to + ; this register will cause a #UD exception. + ; + ; MS assembler doesn't support this instruction since no one would use it + ; under normal circustances. Here opcode is used. + ; + DB 0xf, 0x23, 0xe0 + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr5.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr5.c new file mode 100644 index 000000000..2159813a3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr5.c @@ -0,0 +1,33 @@ +/** @file + AsmWriteDr5 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Writes a value to Debug Register 5 (DR5). + + Writes and returns a new value to DR5. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Value The value to write to Dr5. + + @return The value written to Debug Register 5 (DR5). + +**/ +UINTN +EFIAPI +AsmWriteDr5 ( + IN UINTN Value + ) +{ + _asm { + mov eax, Value + _emit 0x0f // mov dr5, eax + _emit 0x23 + _emit 0xe8 + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm new file mode 100644 index 000000000..bc5f424b8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm @@ -0,0 +1,39 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteDr5.Asm +; +; Abstract: +; +; AsmWriteDr5 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmWriteDr5 ( +; IN UINTN Value +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteDr5) +ASM_PFX(AsmWriteDr5): + mov eax, [esp + 4] + ; + ; DR5 is alias to DR7 only if DE (in CR4) is cleared. Otherwise, writing to + ; this register will cause a #UD exception. + ; + ; MS assembler doesn't support this instruction since no one would use it + ; under normal circustances. Here opcode is used. + ; + DB 0xf, 0x23, 0xe8 + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr6.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr6.c new file mode 100644 index 000000000..c03d71643 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr6.c @@ -0,0 +1,31 @@ +/** @file + AsmWriteDr6 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Writes a value to Debug Register 6 (DR6). + + Writes and returns a new value to DR6. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Value The value to write to Dr6. + + @return The value written to Debug Register 6 (DR6). + +**/ +UINTN +EFIAPI +AsmWriteDr6 ( + IN UINTN Value + ) +{ + _asm { + mov eax, Value + mov dr6, eax + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr6.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr6.nasm new file mode 100644 index 000000000..9089c52c9 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr6.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteDr6.Asm +; +; Abstract: +; +; AsmWriteDr6 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmWriteDr6 ( +; IN UINTN Value +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteDr6) +ASM_PFX(AsmWriteDr6): + mov eax, [esp + 4] + mov dr6, eax + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr7.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr7.c new file mode 100644 index 000000000..c4821e4cd --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr7.c @@ -0,0 +1,31 @@ +/** @file + AsmWriteDr7 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Writes a value to Debug Register 7 (DR7). + + Writes and returns a new value to DR7. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Value The value to write to Dr7. + + @return The value written to Debug Register 7 (DR7). + +**/ +UINTN +EFIAPI +AsmWriteDr7 ( + IN UINTN Value + ) +{ + _asm { + mov eax, Value + mov dr7, eax + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr7.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr7.nasm new file mode 100644 index 000000000..5dc22b695 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr7.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteDr7.Asm +; +; Abstract: +; +; AsmWriteDr7 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINTN +; EFIAPI +; AsmWriteDr7 ( +; IN UINTN Value +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteDr7) +ASM_PFX(AsmWriteDr7): + mov eax, [esp + 4] + mov dr7, eax + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteGdtr.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteGdtr.c new file mode 100644 index 000000000..37ceae73f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteGdtr.c @@ -0,0 +1,33 @@ +/** @file + AsmWriteGdtr function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "BaseLibInternals.h" + + +/** + Writes the current Global Descriptor Table Register (GDTR) descriptor. + + Writes and the current GDTR descriptor specified by Gdtr. This function is + only available on IA-32 and x64. + + @param Gdtr The pointer to a GDTR descriptor. + +**/ +VOID +EFIAPI +InternalX86WriteGdtr ( + IN CONST IA32_DESCRIPTOR *Gdtr + ) +{ + _asm { + mov eax, Gdtr + lgdt fword ptr [eax] + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteGdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteGdtr.nasm new file mode 100644 index 000000000..cc1a08a53 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteGdtr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteGdtr.Asm +; +; Abstract: +; +; AsmWriteGdtr function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; InternalX86WriteGdtr ( +; IN CONST IA32_DESCRIPTOR *Idtr +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalX86WriteGdtr) +ASM_PFX(InternalX86WriteGdtr): + mov eax, [esp + 4] + lgdt [eax] + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteIdtr.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteIdtr.c new file mode 100644 index 000000000..49ef22b99 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteIdtr.c @@ -0,0 +1,35 @@ +/** @file + AsmWriteIdtr function + + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "BaseLibInternals.h" + +/** + Writes the current Interrupt Descriptor Table Register(GDTR) descriptor. + + Writes the current IDTR descriptor and returns it in Idtr. This function is + only available on IA-32 and x64. + + @param Idtr The pointer to a IDTR descriptor. + +**/ +VOID +EFIAPI +InternalX86WriteIdtr ( + IN CONST IA32_DESCRIPTOR *Idtr + ) +{ + _asm { + mov eax, Idtr + pushfd + cli + lidt fword ptr [eax] + popfd + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteIdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteIdtr.nasm new file mode 100644 index 000000000..074dc1846 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteIdtr.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteIdtr.Asm +; +; Abstract: +; +; AsmWriteIdtr function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; InternalX86WriteIdtr ( +; IN CONST IA32_DESCRIPTOR *Idtr +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalX86WriteIdtr) +ASM_PFX(InternalX86WriteIdtr): + mov eax, [esp + 4] + pushfd + cli + lidt [eax] + popfd + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteLdtr.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteLdtr.c new file mode 100644 index 000000000..8e12f7840 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteLdtr.c @@ -0,0 +1,33 @@ +/** @file + AsmWriteLdtr function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Writes the current Local Descriptor Table Register (GDTR) selector. + + Writes and the current LDTR descriptor specified by Ldtr. This function is + only available on IA-32 and x64. + + @param Ldtr 16-bit LDTR selector value. + +**/ +VOID +EFIAPI +AsmWriteLdtr ( + IN UINT16 Ldtr + ) +{ + _asm { + xor eax, eax + mov ax, Ldtr + lldt ax + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteLdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteLdtr.nasm new file mode 100644 index 000000000..870ea18d7 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteLdtr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteLdtr.Asm +; +; Abstract: +; +; AsmWriteLdtr function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmWriteLdtr ( +; IN UINT16 Ldtr +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteLdtr) +ASM_PFX(AsmWriteLdtr): + mov eax, [esp + 4] + lldt ax + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm0.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm0.c new file mode 100644 index 000000000..ea26009a6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm0.c @@ -0,0 +1,32 @@ +/** @file + AsmWriteMm0 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Writes the current value of 64-bit MMX Register #0 (MM0). + + Writes the current value of MM0. This function is only available on IA32 and + x64. + + @param Value The 64-bit value to write to MM0. + +**/ +VOID +EFIAPI +AsmWriteMm0 ( + IN UINT64 Value + ) +{ + _asm { + movq mm0, qword ptr [Value] + emms + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm0.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm0.nasm new file mode 100644 index 000000000..4fcf9da85 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm0.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteMm0.Asm +; +; Abstract: +; +; AsmWriteMm0 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmWriteMm0 ( +; IN UINT64 Value +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteMm0) +ASM_PFX(AsmWriteMm0): + movq mm0, [esp + 4] + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm1.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm1.c new file mode 100644 index 000000000..b8da47329 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm1.c @@ -0,0 +1,32 @@ +/** @file + AsmWriteMm1 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Writes the current value of 64-bit MMX Register #1 (MM1). + + Writes the current value of MM1. This function is only available on IA32 and + x64. + + @param Value The 64-bit value to write to MM1. + +**/ +VOID +EFIAPI +AsmWriteMm1 ( + IN UINT64 Value + ) +{ + _asm { + movq mm1, qword ptr [Value] + emms + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm1.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm1.nasm new file mode 100644 index 000000000..00e2d10b9 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm1.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteMm1.Asm +; +; Abstract: +; +; AsmWriteMm1 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmWriteMm1 ( +; IN UINT64 Value +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteMm1) +ASM_PFX(AsmWriteMm1): + movq mm1, [esp + 4] + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm2.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm2.c new file mode 100644 index 000000000..6b77aed7a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm2.c @@ -0,0 +1,32 @@ +/** @file + AsmWriteMm2 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Writes the current value of 64-bit MMX Register #2 (MM2). + + Writes the current value of MM2. This function is only available on IA32 and + x64. + + @param Value The 64-bit value to write to MM2. + +**/ +VOID +EFIAPI +AsmWriteMm2 ( + IN UINT64 Value + ) +{ + _asm { + movq mm2, qword ptr [Value] + emms + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm2.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm2.nasm new file mode 100644 index 000000000..ec9d2b299 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm2.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteMm2.Asm +; +; Abstract: +; +; AsmWriteMm2 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmWriteMm2 ( +; IN UINT64 Value +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteMm2) +ASM_PFX(AsmWriteMm2): + movq mm2, [esp + 4] + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm3.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm3.c new file mode 100644 index 000000000..4fc7d7042 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm3.c @@ -0,0 +1,32 @@ +/** @file + AsmWriteMm3 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Writes the current value of 64-bit MMX Register #3 (MM3). + + Writes the current value of MM3. This function is only available on IA32 and + x64. + + @param Value The 64-bit value to write to MM3. + +**/ +VOID +EFIAPI +AsmWriteMm3 ( + IN UINT64 Value + ) +{ + _asm { + movq mm3, qword ptr [Value] + emms + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm3.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm3.nasm new file mode 100644 index 000000000..01d29c49a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm3.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteMm3.Asm +; +; Abstract: +; +; AsmWriteMm3 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmWriteMm3 ( +; IN UINT64 Value +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteMm3) +ASM_PFX(AsmWriteMm3): + movq mm3, [esp + 4] + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm4.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm4.c new file mode 100644 index 000000000..2fce55497 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm4.c @@ -0,0 +1,31 @@ +/** @file + AsmWriteMm4 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Writes the current value of 64-bit MMX Register #4 (MM4). + + Writes the current value of MM4. This function is only available on IA32 and + x64. + + @param Value The 64-bit value to write to MM4. + +**/ +VOID +EFIAPI +AsmWriteMm4 ( + IN UINT64 Value + ) +{ + _asm { + movq mm4, qword ptr [Value] + emms + } +} diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm4.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm4.nasm new file mode 100644 index 000000000..0b2255655 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm4.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteMm4.Asm +; +; Abstract: +; +; AsmWriteMm4 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmWriteMm4 ( +; IN UINT64 Value +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteMm4) +ASM_PFX(AsmWriteMm4): + movq mm4, [esp + 4] + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm5.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm5.c new file mode 100644 index 000000000..a0ec714e3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm5.c @@ -0,0 +1,31 @@ +/** @file + AsmWriteMm5 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Writes the current value of 64-bit MMX Register #5 (MM5). + + Writes the current value of MM5. This function is only available on IA32 and + x64. + + @param Value The 64-bit value to write to MM5. + +**/ +VOID +EFIAPI +AsmWriteMm5 ( + IN UINT64 Value + ) +{ + _asm { + movq mm5, qword ptr [Value] + emms + } +} diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm5.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm5.nasm new file mode 100644 index 000000000..4a3c0df48 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm5.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteMm5.Asm +; +; Abstract: +; +; AsmWriteMm5 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmWriteMm5 ( +; IN UINT64 Value +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteMm5) +ASM_PFX(AsmWriteMm5): + movq mm5, [esp + 4] + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm6.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm6.c new file mode 100644 index 000000000..c3b57b4b5 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm6.c @@ -0,0 +1,32 @@ +/** @file + AsmWriteMm6 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Writes the current value of 64-bit MMX Register #6 (MM6). + + Writes the current value of MM6. This function is only available on IA32 and + x64. + + @param Value The 64-bit value to write to MM6. + +**/ +VOID +EFIAPI +AsmWriteMm6 ( + IN UINT64 Value + ) +{ + _asm { + movq mm6, qword ptr [Value] + emms + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm6.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm6.nasm new file mode 100644 index 000000000..397ccfbc2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm6.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteMm6.Asm +; +; Abstract: +; +; AsmWriteMm6 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmWriteMm6 ( +; IN UINT64 Value +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteMm6) +ASM_PFX(AsmWriteMm6): + movq mm6, [esp + 4] + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm7.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm7.c new file mode 100644 index 000000000..e1e893245 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm7.c @@ -0,0 +1,32 @@ +/** @file + AsmWriteMm7 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Writes the current value of 64-bit MMX Register #7 (MM7). + + Writes the current value of MM7. This function is only available on IA32 and + x64. + + @param Value The 64-bit value to write to MM7. + +**/ +VOID +EFIAPI +AsmWriteMm7 ( + IN UINT64 Value + ) +{ + _asm { + movq mm7, qword ptr [Value] + emms + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm7.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm7.nasm new file mode 100644 index 000000000..ee3c7f1d1 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm7.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteMm7.Asm +; +; Abstract: +; +; AsmWriteMm7 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmWriteMm7 ( +; IN UINT64 Value +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteMm7) +ASM_PFX(AsmWriteMm7): + movq mm7, [esp + 4] + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMsr64.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMsr64.c new file mode 100644 index 000000000..badf1d8e5 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMsr64.c @@ -0,0 +1,43 @@ +/** @file + AsmWriteMsr64 function + + Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + + +/** + Writes a 64-bit value to a Machine Specific Register(MSR), and returns the + value. + + Writes the 64-bit value specified by Value to the MSR specified by Index. The + 64-bit value written to the MSR is returned. No parameter checking is + performed on Index or Value, and some of these may cause CPU exceptions. The + caller must either guarantee that Index and Value are valid, or the caller + must establish proper exception handlers. This function is only available on + IA-32 and x64. + + @param Index The 32-bit MSR index to write. + @param Value The 64-bit value to write to the MSR. + + @return Value + +**/ +UINT64 +EFIAPI +AsmWriteMsr64 ( + IN UINT32 Index, + IN UINT64 Value + ) +{ + _asm { + mov edx, dword ptr [Value + 4] + mov eax, dword ptr [Value + 0] + mov ecx, Index + wrmsr + } +} + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMsr64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMsr64.nasm new file mode 100644 index 000000000..f9e3b0561 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMsr64.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteMsr64.Asm +; +; Abstract: +; +; AsmWriteMsr64 function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; AsmWriteMsr64 ( +; IN UINT32 Index, +; IN UINT64 Value +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteMsr64) +ASM_PFX(AsmWriteMsr64): + mov edx, [esp + 12] + mov eax, [esp + 8] + mov ecx, [esp + 4] + wrmsr + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteTr.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteTr.nasm new file mode 100644 index 000000000..e36c63863 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteTr.nasm @@ -0,0 +1,30 @@ +;------------------------------------------------------------------------------ ; +; Copyright (c) 2017, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteTr.nasm +; +; Abstract: +; +; Write TR register +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; AsmWriteTr ( +; UINT16 Selector +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteTr) +ASM_PFX(AsmWriteTr): + mov eax, [esp+4] + ltr ax + ret + diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm new file mode 100644 index 000000000..9f7b03bbf --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; XGetBv.Asm +; +; Abstract: +; +; AsmXgetBv function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; AsmXGetBv ( +; IN UINT32 Index +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmXGetBv) +ASM_PFX(AsmXGetBv): + mov ecx, [esp + 4] + xgetbv + ret -- cgit 1.2.3-korg