From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001 From: Angelos Mouzakitis Date: Tue, 10 Oct 2023 14:33:42 +0000 Subject: Add submodule dependency files Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec --- roms/opensbi/platform/kendryte/k210/config.mk | 19 +++ roms/opensbi/platform/kendryte/k210/k210.dts | 70 +++++++++++ roms/opensbi/platform/kendryte/k210/objects.mk | 14 +++ roms/opensbi/platform/kendryte/k210/platform.c | 159 +++++++++++++++++++++++++ roms/opensbi/platform/kendryte/k210/platform.h | 36 ++++++ 5 files changed, 298 insertions(+) create mode 100644 roms/opensbi/platform/kendryte/k210/config.mk create mode 100644 roms/opensbi/platform/kendryte/k210/k210.dts create mode 100644 roms/opensbi/platform/kendryte/k210/objects.mk create mode 100644 roms/opensbi/platform/kendryte/k210/platform.c create mode 100644 roms/opensbi/platform/kendryte/k210/platform.h (limited to 'roms/opensbi/platform/kendryte') diff --git a/roms/opensbi/platform/kendryte/k210/config.mk b/roms/opensbi/platform/kendryte/k210/config.mk new file mode 100644 index 000000000..8a9b81418 --- /dev/null +++ b/roms/opensbi/platform/kendryte/k210/config.mk @@ -0,0 +1,19 @@ +# +# SPDX-License-Identifier: BSD-2-Clause +# +# Copyright (c) 2019 Western Digital Corporation or its affiliates. +# +# Authors: +# Damien Le Moal +# + +# Compiler flags +platform-cppflags-y = +platform-cflags-y = +platform-asflags-y = +platform-ldflags-y = + +# Blobs to build +FW_TEXT_START=0x80000000 +FW_PAYLOAD=y +FW_PAYLOAD_ALIGN=0x1000 diff --git a/roms/opensbi/platform/kendryte/k210/k210.dts b/roms/opensbi/platform/kendryte/k210/k210.dts new file mode 100644 index 000000000..bcd075bf5 --- /dev/null +++ b/roms/opensbi/platform/kendryte/k210/k210.dts @@ -0,0 +1,70 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Damien Le Moal + */ + +/dts-v1/; +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "kendryte,k210"; + + chosen { + bootargs = "console=hvc0 earlycon=sbi"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + clock-frequency = <390000000>; + i-cache-size = <32768>; + d-cache-size = <32768>; + mmu-type = "none"; + reg = <0>; + riscv,isa = "rv64imafdc"; + status = "okay"; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + device_type = "cpu"; + clock-frequency = <390000000>; + d-cache-size = <32768>; + i-cache-size = <32768>; + mmu-type = "none"; + reg = <1>; + riscv,isa = "rv64imafdc"; + status = "okay"; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + memory@80000000 { + /* Bank 0: 4 MB, Bank 1: 2 MB, AI chip SRAM: 2MB */ + device_type = "memory"; + reg = <0x00000000 0x80000000 0x00000000 0x00800000>; + }; + + plic0: interrupt-controller@C000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = + <&cpu0_intc 11 &cpu0_intc 9 + &cpu1_intc 11 &cpu1_intc 9>; + reg = <0x0 0xc000000 0x0 0x4000000>; + }; +}; diff --git a/roms/opensbi/platform/kendryte/k210/objects.mk b/roms/opensbi/platform/kendryte/k210/objects.mk new file mode 100644 index 000000000..b74da7407 --- /dev/null +++ b/roms/opensbi/platform/kendryte/k210/objects.mk @@ -0,0 +1,14 @@ +# +# SPDX-License-Identifier: BSD-2-Clause +# +# Copyright (c) 2019 Western Digital Corporation or its affiliates. +# +# Authors: +# Damien Le Moal +# + +platform-objs-y += platform.o + +platform-objs-y += k210.o +platform-varprefix-k210.o = dt_k210 +platform-padding-k210.o = 2048 diff --git a/roms/opensbi/platform/kendryte/k210/platform.c b/roms/opensbi/platform/kendryte/k210/platform.c new file mode 100644 index 000000000..944b38885 --- /dev/null +++ b/roms/opensbi/platform/kendryte/k210/platform.c @@ -0,0 +1,159 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Damien Le Moal + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "platform.h" + +extern const char dt_k210_start[]; + +unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4) +{ + return (unsigned long)&dt_k210_start[0]; +} + +static struct plic_data plic = { + .addr = K210_PLIC_BASE_ADDR, + .num_src = K210_PLIC_NUM_SOURCES, +}; + +static struct clint_data clint = { + .addr = K210_CLINT_BASE_ADDR, + .first_hartid = 0, + .hart_count = K210_HART_COUNT, + .has_64bit_mmio = TRUE, +}; + +static u32 k210_get_clk_freq(void) +{ + u32 clksel0, pll0; + u64 pll0_freq, clkr0, clkf0, clkod0, div; + + /* + * If the clock selector is not set, use the base frequency. + * Otherwise, use PLL0 frequency with a frequency divisor. + */ + clksel0 = k210_read_sysreg(K210_CLKSEL0); + if (!(clksel0 & 0x1)) + return K210_CLK0_FREQ; + + /* + * Get PLL0 frequency: + * freq = base frequency * clkf0 / (clkr0 * clkod0) + */ + pll0 = k210_read_sysreg(K210_PLL0); + clkr0 = 1 + (pll0 & 0x0000000f); + clkf0 = 1 + ((pll0 & 0x000003f0) >> 4); + clkod0 = 1 + ((pll0 & 0x00003c00) >> 10); + pll0_freq = clkf0 * K210_CLK0_FREQ / (clkr0 * clkod0); + + /* Get the frequency divisor from the clock selector */ + div = 2ULL << ((clksel0 & 0x00000006) >> 1); + + return pll0_freq / div; +} + +static int k210_final_init(bool cold_boot) +{ + void *fdt; + + if (!cold_boot) + return 0; + + fdt = sbi_scratch_thishart_arg1_ptr(); + + fdt_cpu_fixup(fdt); + fdt_fixups(fdt); + + return 0; +} + +static int k210_console_init(void) +{ + return sifive_uart_init(K210_UART_BASE_ADDR, k210_get_clk_freq(), + K210_UART_BAUDRATE); +} + +static int k210_irqchip_init(bool cold_boot) +{ + int rc; + u32 hartid = current_hartid(); + + if (cold_boot) { + rc = plic_cold_irqchip_init(&plic); + if (rc) + return rc; + } + + return plic_warm_irqchip_init(&plic, hartid * 2, hartid * 2 + 1); +} + +static int k210_ipi_init(bool cold_boot) +{ + int rc; + + if (cold_boot) { + rc = clint_cold_ipi_init(&clint); + if (rc) + return rc; + } + + return clint_warm_ipi_init(); +} + +static int k210_timer_init(bool cold_boot) +{ + int rc; + + if (cold_boot) { + rc = clint_cold_timer_init(&clint, NULL); + if (rc) + return rc; + } + + return clint_warm_timer_init(); +} + +const struct sbi_platform_operations platform_ops = { + .final_init = k210_final_init, + + .console_init = k210_console_init, + .console_putc = sifive_uart_putc, + .console_getc = sifive_uart_getc, + + .irqchip_init = k210_irqchip_init, + + .ipi_init = k210_ipi_init, + .ipi_send = clint_ipi_send, + .ipi_clear = clint_ipi_clear, + + .timer_init = k210_timer_init, + .timer_value = clint_timer_value, + .timer_event_stop = clint_timer_event_stop, + .timer_event_start = clint_timer_event_start, +}; + +const struct sbi_platform platform = { + .opensbi_version = OPENSBI_VERSION, + .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01), + .name = "Kendryte K210", + .features = SBI_PLATFORM_HAS_TIMER_VALUE, + .hart_count = K210_HART_COUNT, + .hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE, + .platform_ops_addr = (unsigned long)&platform_ops +}; diff --git a/roms/opensbi/platform/kendryte/k210/platform.h b/roms/opensbi/platform/kendryte/k210/platform.h new file mode 100644 index 000000000..5269bc4fd --- /dev/null +++ b/roms/opensbi/platform/kendryte/k210/platform.h @@ -0,0 +1,36 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Damien Le Moal + */ +#ifndef _K210_PLATFORM_H_ +#define _K210_PLATFORM_H_ + +#include + +#define K210_HART_COUNT 2 + +#define K210_UART_BAUDRATE 115200 + +#define K210_CLK0_FREQ 26000000UL +#define K210_PLIC_NUM_SOURCES 65 + +/* Registers base address */ +#define K210_SYSCTL_BASE_ADDR 0x50440000ULL +#define K210_UART_BASE_ADDR 0x38000000ULL +#define K210_CLINT_BASE_ADDR 0x02000000ULL +#define K210_PLIC_BASE_ADDR 0x0C000000ULL + +/* Registers */ +#define K210_PLL0 0x08 +#define K210_CLKSEL0 0x20 + +static inline u32 k210_read_sysreg(u32 reg) +{ + return readl((volatile void *)(K210_SYSCTL_BASE_ADDR + reg)); +} + +#endif /* _K210_PLATFORM_H_ */ -- cgit 1.2.3-korg