From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001
From: Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com>
Date: Tue, 10 Oct 2023 14:33:42 +0000
Subject: Add submodule dependency files

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
---
 roms/skiboot/doc/device-tree/memory-hierarchy.rst | 26 +++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 roms/skiboot/doc/device-tree/memory-hierarchy.rst

(limited to 'roms/skiboot/doc/device-tree/memory-hierarchy.rst')

diff --git a/roms/skiboot/doc/device-tree/memory-hierarchy.rst b/roms/skiboot/doc/device-tree/memory-hierarchy.rst
new file mode 100644
index 000000000..c3c1d0349
--- /dev/null
+++ b/roms/skiboot/doc/device-tree/memory-hierarchy.rst
@@ -0,0 +1,26 @@
+P9 memory hierarchy
+-------------------
+P9 Nimbus supports direct attached DDR memory through 4 DDR ports per side
+of the processor. Device tree contains memory hierarchy so that one can
+traverse from chip to DIMM like below:
+
+  xscom@<addr>/mcbist@<mcbist_id>/mcs@<mcs_id>/mca@<mca_id>/dimm@<resource_id>
+
+Example of dimm node:
+
+.. code-block:: dts
+
+    dimm@d00e {
+            memory-id = <0xc>; /* DRAM Device Type. 0xc = DDR4 */
+            product-version = <0x32>; /* Module Revision Code */
+            device_type = "memory-dimm-ddr4";
+            serial-number = <0x15d9ad1c>;
+            status = "okay";
+            size = <0x4000>;
+            phandle = <0xd2>;
+            ibm,loc-code = "UOPWR.0000000-Node0-DIMM14";
+            part-number = "36ASF2G72PZ-2G6B2   ";
+            reg = <0xd00e>;
+            manufacturer-id = <0x802c>; /* Vendor ID, we can get vendor name from this ID */
+    };
+
-- 
cgit 1.2.3-korg