From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001
From: Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com>
Date: Tue, 10 Oct 2023 14:33:42 +0000
Subject: Add submodule dependency files

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
---
 roms/u-boot/arch/arm/dts/zynqmp-r5.dts | 73 ++++++++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)
 create mode 100644 roms/u-boot/arch/arm/dts/zynqmp-r5.dts

(limited to 'roms/u-boot/arch/arm/dts/zynqmp-r5.dts')

diff --git a/roms/u-boot/arch/arm/dts/zynqmp-r5.dts b/roms/u-boot/arch/arm/dts/zynqmp-r5.dts
new file mode 100644
index 000000000..a72172ef2
--- /dev/null
+++ b/roms/u-boot/arch/arm/dts/zynqmp-r5.dts
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP R5
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "xlnx,zynqmp-r5";
+	model = "Xilinx ZynqMP R5";
+
+	cpus {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-r5";
+			device_type = "cpu";
+			reg = <0>;
+		};
+	};
+
+	aliases {
+		serial0 = &uart1;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>;
+	};
+
+	chosen {
+		bootargs = "";
+		stdout-path = "serial0:115200n8";
+	};
+
+	clk100: clk100 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		u-boot,dm-pre-reloc;
+	};
+
+	amba {
+		u-boot,dm-pre-reloc;
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		ttc0: timer@ff110000 {
+			compatible = "cdns,ttc";
+			status = "okay";
+			reg = <0xff110000 0x1000>;
+			timer-width = <32>;
+			clocks = <&clk100>;
+		};
+
+		uart1: serial@ff010000 {
+			u-boot,dm-pre-reloc;
+			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
+			reg = <0xff010000 0x1000>;
+			clock-names = "uart_clk", "pclk";
+			clocks = <&clk100 &clk100>;
+		};
+	};
+};
-- 
cgit 1.2.3-korg