From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001 From: Angelos Mouzakitis Date: Tue, 10 Oct 2023 14:33:42 +0000 Subject: Add submodule dependency files Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec --- roms/u-boot/arch/arm/include/asm/arch-meson/axg.h | 34 ++++++ roms/u-boot/arch/arm/include/asm/arch-meson/boot.h | 24 +++++ .../arch/arm/include/asm/arch-meson/clock-axg.h | 104 ++++++++++++++++++ .../arch/arm/include/asm/arch-meson/clock-g12a.h | 104 ++++++++++++++++++ .../arch/arm/include/asm/arch-meson/clock-gx.h | 117 +++++++++++++++++++++ roms/u-boot/arch/arm/include/asm/arch-meson/eth.h | 13 +++ roms/u-boot/arch/arm/include/asm/arch-meson/g12a.h | 35 ++++++ roms/u-boot/arch/arm/include/asm/arch-meson/gpio.h | 10 ++ roms/u-boot/arch/arm/include/asm/arch-meson/gx.h | 44 ++++++++ roms/u-boot/arch/arm/include/asm/arch-meson/i2c.h | 10 ++ roms/u-boot/arch/arm/include/asm/arch-meson/mem.h | 16 +++ .../arch/arm/include/asm/arch-meson/meson-vpu.h | 13 +++ roms/u-boot/arch/arm/include/asm/arch-meson/sm.h | 33 ++++++ .../arch/arm/include/asm/arch-meson/usb-gx.h | 17 +++ roms/u-boot/arch/arm/include/asm/arch-meson/usb.h | 12 +++ 15 files changed, 586 insertions(+) create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/axg.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/boot.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/clock-axg.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/clock-g12a.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/clock-gx.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/eth.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/g12a.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/gx.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/i2c.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/mem.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/meson-vpu.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/sm.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/usb-gx.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/usb.h (limited to 'roms/u-boot/arch/arm/include/asm/arch-meson') diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/axg.h b/roms/u-boot/arch/arm/include/asm/arch-meson/axg.h new file mode 100644 index 000000000..12042de93 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/axg.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef __AXG_H__ +#define __AXG_H__ + +#ifndef __ASSEMBLY__ +#include +#endif + +#define AXG_AOBUS_BASE 0xff800000 +#define AXG_PERIPHS_BASE 0xff634400 +#define AXG_HIU_BASE 0xff63c000 +#define AXG_ETH_BASE 0xff3f0000 + +/* Always-On Peripherals registers */ +#define AXG_AO_ADDR(off) (AXG_AOBUS_BASE + ((off) << 2)) + +#define AXG_AO_SEC_GP_CFG0 AXG_AO_ADDR(0x90) +#define AXG_AO_SEC_GP_CFG3 AXG_AO_ADDR(0x93) +#define AXG_AO_SEC_GP_CFG4 AXG_AO_ADDR(0x94) +#define AXG_AO_SEC_GP_CFG5 AXG_AO_ADDR(0x95) + +#define AXG_AO_BOOT_DEVICE 0xF +#define AXG_AO_MEM_SIZE_MASK 0xFFFF0000 +#define AXG_AO_MEM_SIZE_SHIFT 16 +#define AXG_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 +#define AXG_AO_BL31_RSVMEM_SIZE_SHIFT 16 +#define AXG_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF + +#endif /* __AXG_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/boot.h b/roms/u-boot/arch/arm/include/asm/arch-meson/boot.h new file mode 100644 index 000000000..c67d12d06 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/boot.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef __MESON_BOOT_H__ +#define __MESON_BOOT_H__ + +#include + +/* Boot device */ +#define BOOT_DEVICE_RESERVED 0 +#define BOOT_DEVICE_EMMC 1 +#define BOOT_DEVICE_NAND 2 +#define BOOT_DEVICE_SPI 3 +#define BOOT_DEVICE_SD 4 +#define BOOT_DEVICE_USB 5 + +int meson_get_boot_device(void); + +int meson_get_soc_rev(char *buff, size_t buff_len); + +#endif /* __MESON_BOOT_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/clock-axg.h b/roms/u-boot/arch/arm/include/asm/arch-meson/clock-axg.h new file mode 100644 index 000000000..1ef88e4fa --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/clock-axg.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 - AmLogic, Inc. + * Copyright 2018 - Beniamino Galvani + * Copyright 2018 - BayLibre, SAS + * Author: Neil Armstrong + */ +#ifndef _ARCH_MESON_CLOCK_AXG_H_ +#define _ARCH_MESON_CLOCK_AXG_H_ + +/* + * Clock controller register offsets + * + * Register offsets from the data sheet are listed in comment blocks below. + * Those offsets must be multiplied by 4 before adding them to the base address + * to get the right value + */ +#define HHI_GP0_PLL_CNTL 0x40 +#define HHI_GP0_PLL_CNTL2 0x44 +#define HHI_GP0_PLL_CNTL3 0x48 +#define HHI_GP0_PLL_CNTL4 0x4c +#define HHI_GP0_PLL_CNTL5 0x50 +#define HHI_GP0_PLL_STS 0x54 +#define HHI_GP0_PLL_CNTL1 0x58 +#define HHI_HIFI_PLL_CNTL 0x80 +#define HHI_HIFI_PLL_CNTL2 0x84 +#define HHI_HIFI_PLL_CNTL3 0x88 +#define HHI_HIFI_PLL_CNTL4 0x8C +#define HHI_HIFI_PLL_CNTL5 0x90 +#define HHI_HIFI_PLL_STS 0x94 +#define HHI_HIFI_PLL_CNTL1 0x98 + +#define HHI_XTAL_DIVN_CNTL 0xbc +#define HHI_GCLK2_MPEG0 0xc0 +#define HHI_GCLK2_MPEG1 0xc4 +#define HHI_GCLK2_MPEG2 0xc8 +#define HHI_GCLK2_OTHER 0xd0 +#define HHI_GCLK2_AO 0xd4 +#define HHI_PCIE_PLL_CNTL 0xd8 +#define HHI_PCIE_PLL_CNTL1 0xdC +#define HHI_PCIE_PLL_CNTL2 0xe0 +#define HHI_PCIE_PLL_CNTL3 0xe4 +#define HHI_PCIE_PLL_CNTL4 0xe8 +#define HHI_PCIE_PLL_CNTL5 0xec +#define HHI_PCIE_PLL_CNTL6 0xf0 +#define HHI_PCIE_PLL_STS 0xf4 + +#define HHI_MEM_PD_REG0 0x100 +#define HHI_VPU_MEM_PD_REG0 0x104 +#define HHI_VIID_CLK_DIV 0x128 +#define HHI_VIID_CLK_CNTL 0x12c + +#define HHI_GCLK_MPEG0 0x140 +#define HHI_GCLK_MPEG1 0x144 +#define HHI_GCLK_MPEG2 0x148 +#define HHI_GCLK_OTHER 0x150 +#define HHI_GCLK_AO 0x154 +#define HHI_SYS_CPU_CLK_CNTL1 0x15c +#define HHI_SYS_CPU_RESET_CNTL 0x160 +#define HHI_VID_CLK_DIV 0x164 +#define HHI_SPICC_HCLK_CNTL 0x168 + +#define HHI_MPEG_CLK_CNTL 0x174 +#define HHI_VID_CLK_CNTL 0x17c +#define HHI_TS_CLK_CNTL 0x190 +#define HHI_VID_CLK_CNTL2 0x194 +#define HHI_SYS_CPU_CLK_CNTL0 0x19c +#define HHI_VID_PLL_CLK_DIV 0x1a0 +#define HHI_VPU_CLK_CNTL 0x1bC + +#define HHI_VAPBCLK_CNTL 0x1F4 + +#define HHI_GEN_CLK_CNTL 0x228 + +#define HHI_VDIN_MEAS_CLK_CNTL 0x250 +#define HHI_NAND_CLK_CNTL 0x25C +#define HHI_SD_EMMC_CLK_CNTL 0x264 + +#define HHI_MPLL_CNTL 0x280 +#define HHI_MPLL_CNTL2 0x284 +#define HHI_MPLL_CNTL3 0x288 +#define HHI_MPLL_CNTL4 0x28C +#define HHI_MPLL_CNTL5 0x290 +#define HHI_MPLL_CNTL6 0x294 +#define HHI_MPLL_CNTL7 0x298 +#define HHI_MPLL_CNTL8 0x29C +#define HHI_MPLL_CNTL9 0x2A0 +#define HHI_MPLL_CNTL10 0x2A4 + +#define HHI_MPLL3_CNTL0 0x2E0 +#define HHI_MPLL3_CNTL1 0x2E4 +#define HHI_PLL_TOP_MISC 0x2E8 + +#define HHI_SYS_PLL_CNTL1 0x2FC +#define HHI_SYS_PLL_CNTL 0x300 +#define HHI_SYS_PLL_CNTL2 0x304 +#define HHI_SYS_PLL_CNTL3 0x308 +#define HHI_SYS_PLL_CNTL4 0x30c +#define HHI_SYS_PLL_CNTL5 0x310 +#define HHI_SYS_PLL_STS 0x314 +#define HHI_DPLL_TOP_I 0x318 +#define HHI_DPLL_TOP2_I 0x31C + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/clock-g12a.h b/roms/u-boot/arch/arm/include/asm/arch-meson/clock-g12a.h new file mode 100644 index 000000000..d52e27e00 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/clock-g12a.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 - AmLogic, Inc. + * Copyright 2018 - Beniamino Galvani + * Copyright 2018 - BayLibre, SAS + * Author: Neil Armstrong + */ +#ifndef _ARCH_MESON_CLOCK_G12A_H_ +#define _ARCH_MESON_CLOCK_G12A_H_ + +/* + * Clock controller register offsets + * + * Register offsets from the data sheet are listed in comment blocks below. + * Those offsets must be multiplied by 4 before adding them to the base address + * to get the right value + */ + +#define HHI_MIPI_CNTL0 0x000 +#define HHI_MIPI_CNTL1 0x004 +#define HHI_MIPI_CNTL2 0x008 +#define HHI_MIPI_STS 0x00C +#define HHI_GP0_PLL_CNTL0 0x040 +#define HHI_GP0_PLL_CNTL1 0x044 +#define HHI_GP0_PLL_CNTL2 0x048 +#define HHI_GP0_PLL_CNTL3 0x04C +#define HHI_GP0_PLL_CNTL4 0x050 +#define HHI_GP0_PLL_CNTL5 0x054 +#define HHI_GP0_PLL_CNTL6 0x058 +#define HHI_GP0_PLL_STS 0x05C +#define HHI_PCIE_PLL_CNTL0 0x098 +#define HHI_PCIE_PLL_CNTL1 0x09C +#define HHI_PCIE_PLL_CNTL2 0x0A0 +#define HHI_PCIE_PLL_CNTL3 0x0A4 +#define HHI_PCIE_PLL_CNTL4 0x0A8 +#define HHI_PCIE_PLL_CNTL5 0x0AC +#define HHI_PCIE_PLL_STS 0x0B8 +#define HHI_HIFI_PLL_CNTL0 0x0D8 +#define HHI_HIFI_PLL_CNTL1 0x0DC +#define HHI_HIFI_PLL_CNTL2 0x0E0 +#define HHI_HIFI_PLL_CNTL3 0x0E4 +#define HHI_HIFI_PLL_CNTL4 0x0E8 +#define HHI_HIFI_PLL_CNTL5 0x0EC +#define HHI_HIFI_PLL_CNTL6 0x0F0 +#define HHI_VIID_CLK_DIV 0x128 +#define HHI_VIID_CLK_CNTL 0x12C +#define HHI_GCLK_MPEG0 0x140 +#define HHI_GCLK_MPEG1 0x144 +#define HHI_GCLK_MPEG2 0x148 +#define HHI_GCLK_OTHER 0x150 +#define HHI_GCLK_OTHER2 0x154 +#define HHI_VID_CLK_DIV 0x164 +#define HHI_MPEG_CLK_CNTL 0x174 +#define HHI_AUD_CLK_CNTL 0x178 +#define HHI_VID_CLK_CNTL 0x17c +#define HHI_TS_CLK_CNTL 0x190 +#define HHI_VID_CLK_CNTL2 0x194 +#define HHI_SYS_CPU_CLK_CNTL0 0x19c +#define HHI_VID_PLL_CLK_DIV 0x1A0 +#define HHI_MALI_CLK_CNTL 0x1b0 +#define HHI_VPU_CLKC_CNTL 0x1b4 +#define HHI_VPU_CLK_CNTL 0x1bC +#define HHI_HDMI_CLK_CNTL 0x1CC +#define HHI_VDEC_CLK_CNTL 0x1E0 +#define HHI_VDEC2_CLK_CNTL 0x1E4 +#define HHI_VDEC3_CLK_CNTL 0x1E8 +#define HHI_VDEC4_CLK_CNTL 0x1EC +#define HHI_HDCP22_CLK_CNTL 0x1F0 +#define HHI_VAPBCLK_CNTL 0x1F4 +#define HHI_VPU_CLKB_CNTL 0x20C +#define HHI_GEN_CLK_CNTL 0x228 +#define HHI_VDIN_MEAS_CLK_CNTL 0x250 +#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254 +#define HHI_NAND_CLK_CNTL 0x25C +#define HHI_SD_EMMC_CLK_CNTL 0x264 +#define HHI_MPLL_CNTL0 0x278 +#define HHI_MPLL_CNTL1 0x27C +#define HHI_MPLL_CNTL2 0x280 +#define HHI_MPLL_CNTL3 0x284 +#define HHI_MPLL_CNTL4 0x288 +#define HHI_MPLL_CNTL5 0x28c +#define HHI_MPLL_CNTL6 0x290 +#define HHI_MPLL_CNTL7 0x294 +#define HHI_MPLL_CNTL8 0x298 +#define HHI_FIX_PLL_CNTL0 0x2A0 +#define HHI_FIX_PLL_CNTL1 0x2A4 +#define HHI_FIX_PLL_CNTL3 0x2AC +#define HHI_SYS_PLL_CNTL0 0x2f4 +#define HHI_SYS_PLL_CNTL1 0x2f8 +#define HHI_SYS_PLL_CNTL2 0x2fc +#define HHI_SYS_PLL_CNTL3 0x300 +#define HHI_SYS_PLL_CNTL4 0x304 +#define HHI_SYS_PLL_CNTL5 0x308 +#define HHI_SYS_PLL_CNTL6 0x30c +#define HHI_HDMI_PLL_CNTL0 0x320 +#define HHI_HDMI_PLL_CNTL1 0x324 +#define HHI_HDMI_PLL_CNTL2 0x328 +#define HHI_HDMI_PLL_CNTL3 0x32c +#define HHI_HDMI_PLL_CNTL4 0x330 +#define HHI_HDMI_PLL_CNTL5 0x334 +#define HHI_HDMI_PLL_CNTL6 0x338 +#define HHI_SPICC_CLK_CNTL 0x3dc + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/clock-gx.h b/roms/u-boot/arch/arm/include/asm/arch-meson/clock-gx.h new file mode 100644 index 000000000..13a2e7688 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/clock-gx.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 - AmLogic, Inc. + * Copyright 2018 - Beniamino Galvani + */ +#ifndef _ARCH_MESON_CLOCK_GX_H_ +#define _ARCH_MESON_CLOCK_GX_H_ + +/* + * Clock controller register offsets + * + * Register offsets from the data sheet are listed in comment blocks below. + * Those offsets must be multiplied by 4 before adding them to the base address + * to get the right value + */ +#define SCR 0x2C /* 0x0b offset in data sheet */ +#define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */ + +#define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */ +#define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ +#define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ +#define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */ +#define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */ +#define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */ + +#define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */ +#define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */ + +#define HHI_MEM_PD_REG0 0x100 /* 0x40 offset in data sheet */ +#define HHI_MEM_PD_REG1 0x104 /* 0x41 offset in data sheet */ +#define HHI_VPU_MEM_PD_REG1 0x108 /* 0x42 offset in data sheet */ +#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ +#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ + +#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ +#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ +#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ +#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ +#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ +#define HHI_SYS_OSCIN_CNTL 0x158 /* 0x56 offset in data sheet */ +#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ +#define HHI_SYS_CPU_RESET_CNTL 0x160 /* 0x58 offset in data sheet */ +#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ + +#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ +#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ +#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ +#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */ +#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ +#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ +#define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ +#define HHI_AUD_CLK_CNTL3 0x1a4 /* 0x69 offset in data sheet */ +#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */ +#define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */ + +#define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */ +#define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */ +#define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */ +#define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */ +#define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */ +#define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */ +#define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */ + +#define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */ +#define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */ +#define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */ +#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ +#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ + +#define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */ +#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */ +#define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */ + +#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ +#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ +#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ +#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ +#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ +#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ +#define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */ +#define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */ +#define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ +#define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */ + +#define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */ +#define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */ +#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ +#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ + +#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ +#define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */ +#define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */ +#define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */ +#define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */ +#define HHI_DPLL_TOP_I 0x318 /* 0xc6 offset in data sheet */ +#define HHI_DPLL_TOP2_I 0x31C /* 0xc7 offset in data sheet */ +#define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ +#define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ +#define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ +#define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ +#define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ +#define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */ +#define HHI_HDMI_PLL_CNTL_I 0x338 /* 0xce offset in data sheet */ +#define HHI_HDMI_PLL_CNTL7 0x33C /* 0xcf offset in data sheet */ + +#define HHI_HDMI_PHY_CNTL0 0x3A0 /* 0xe8 offset in data sheet */ +#define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */ +#define HHI_HDMI_PHY_CNTL2 0x3A8 /* 0xea offset in data sheet */ +#define HHI_HDMI_PHY_CNTL3 0x3AC /* 0xeb offset in data sheet */ + +#define HHI_VID_LOCK_CLK_CNTL 0x3C8 /* 0xf2 offset in data sheet */ +#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */ +#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */ + +ulong meson_measure_clk_rate(unsigned int clk); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/eth.h b/roms/u-boot/arch/arm/include/asm/arch-meson/eth.h new file mode 100644 index 000000000..c0070615c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/eth.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef __MESON_ETH_H__ +#define __MESON_ETH_H__ + +/* Generate an unique MAC address based on the HW serial */ +int meson_generate_serial_ethaddr(void); + +#endif /* __MESON_ETH_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/g12a.h b/roms/u-boot/arch/arm/include/asm/arch-meson/g12a.h new file mode 100644 index 000000000..ef4f301f7 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/g12a.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef __G12A_H__ +#define __G12A_H__ + +#ifndef __ASSEMBLY__ +#include +#endif + +#define G12A_AOBUS_BASE 0xff800000 +#define G12A_PERIPHS_BASE 0xff634400 +#define G12A_HIU_BASE 0xff63c000 +#define G12A_ETH_PHY_BASE 0xff64c000 +#define G12A_ETH_BASE 0xff3f0000 + +/* Always-On Peripherals registers */ +#define G12A_AO_ADDR(off) (G12A_AOBUS_BASE + ((off) << 2)) + +#define G12A_AO_SEC_GP_CFG0 G12A_AO_ADDR(0x90) +#define G12A_AO_SEC_GP_CFG3 G12A_AO_ADDR(0x93) +#define G12A_AO_SEC_GP_CFG4 G12A_AO_ADDR(0x94) +#define G12A_AO_SEC_GP_CFG5 G12A_AO_ADDR(0x95) + +#define G12A_AO_BOOT_DEVICE 0xF +#define G12A_AO_MEM_SIZE_MASK 0xFFFF0000 +#define G12A_AO_MEM_SIZE_SHIFT 16 +#define G12A_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 +#define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16 +#define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF + +#endif /* __G12A_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-meson/gpio.h new file mode 100644 index 000000000..d0142f16e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/gpio.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 - Beniamino Galvani + */ + +#ifndef __ASM_ARCH_MESON_GPIO_H +#define __ASM_ARCH_MESON_GPIO_H + + +#endif /* __ASM_ARCH_MESON_GPIO_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/gx.h b/roms/u-boot/arch/arm/include/asm/arch-meson/gx.h new file mode 100644 index 000000000..26ec5d0bc --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/gx.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 - Beniamino Galvani + */ + +#ifndef __GX_H__ +#define __GX_H__ + +#ifndef __ASSEMBLY__ +#include +#endif + +#define GX_FIRMWARE_MEM_SIZE 0x1000000 + +#define GX_AOBUS_BASE 0xc8100000 +#define GX_PERIPHS_BASE 0xc8834400 +#define GX_HIU_BASE 0xc883c000 +#define GX_ETH_BASE 0xc9410000 + +/* Always-On Peripherals registers */ +#define GX_AO_ADDR(off) (GX_AOBUS_BASE + ((off) << 2)) + +#define GX_AO_SEC_GP_CFG0 GX_AO_ADDR(0x90) +#define GX_AO_SEC_GP_CFG3 GX_AO_ADDR(0x93) +#define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94) +#define GX_AO_SEC_GP_CFG5 GX_AO_ADDR(0x95) + +#define GX_AO_BOOT_DEVICE 0xF +#define GX_AO_MEM_SIZE_MASK 0xFFFF0000 +#define GX_AO_MEM_SIZE_SHIFT 16 +#define GX_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 +#define GX_AO_BL31_RSVMEM_SIZE_SHIFT 16 +#define GX_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF + +/* Peripherals registers */ +#define GX_PERIPHS_ADDR(off) (GX_PERIPHS_BASE + ((off) << 2)) + +/* GPIO registers 0 to 6 */ +#define _GX_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n)) +#define GX_GPIO_EN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 0) +#define GX_GPIO_IN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1) +#define GX_GPIO_OUT(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2) + +#endif /* __GX_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/i2c.h b/roms/u-boot/arch/arm/include/asm/arch-meson/i2c.h new file mode 100644 index 000000000..aa474a05b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/i2c.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 - Beniamino Galvani + */ +#ifndef _MESON_I2C_H_ +#define _MESON_I2C_H_ + +#define MESON_I2C_CLK_RATE 167000000 + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/mem.h b/roms/u-boot/arch/arm/include/asm/arch-meson/mem.h new file mode 100644 index 000000000..a65100aeb --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/mem.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef __MESON_MEM_H__ +#define __MESON_MEM_H__ + +/* Configure the reserved memory zones exported by the secure registers + * into EFI and DTB reserved memory entries. + */ +void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size); +void meson_init_reserved_memory(void *fdt); + +#endif /* __MESON_MEM_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/meson-vpu.h b/roms/u-boot/arch/arm/include/asm/arch-meson/meson-vpu.h new file mode 100644 index 000000000..f31dfa6ad --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/meson-vpu.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Maxime Jourdan + */ + +#ifndef __MESON_VPU_H__ +#define __MESON_VPU_H__ + +/* Allow reserving the framebuffer memory region */ +void meson_vpu_rsv_fb(void *fdt); + +#endif /* __MESON_VPU_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/sm.h b/roms/u-boot/arch/arm/include/asm/arch-meson/sm.h new file mode 100644 index 000000000..f3ae46a6d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/sm.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 - Beniamino Galvani + */ + +#ifndef __MESON_SM_H__ +#define __MESON_SM_H__ + +ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size); + +#define SM_SERIAL_SIZE 12 + +int meson_sm_get_serial(void *buffer, size_t size); + +enum { + REBOOT_REASON_COLD = 0, + REBOOT_REASON_NORMAL = 1, + REBOOT_REASON_RECOVERY = 2, + REBOOT_REASON_UPDATE = 3, + REBOOT_REASON_FASTBOOT = 4, + REBOOT_REASON_SUSPEND_OFF = 5, + REBOOT_REASON_HIBERNATE = 6, + REBOOT_REASON_BOOTLOADER = 7, + REBOOT_REASON_SHUTDOWN_REBOOT = 8, + REBOOT_REASON_RPMBP = 9, + REBOOT_REASON_CRASH_DUMP = 11, + REBOOT_REASON_KERNEL_PANIC = 12, + REBOOT_REASON_WATCHDOG_REBOOT = 13, +}; + +int meson_sm_get_reboot_reason(void); + +#endif /* __MESON_SM_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/usb-gx.h b/roms/u-boot/arch/arm/include/asm/arch-meson/usb-gx.h new file mode 100644 index 000000000..61f1809df --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/usb-gx.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 BayLibre SAS + * Author: Neil Armstrong + */ +#ifndef _ARCH_MESON_USB_GX_H_ +#define _ARCH_MESON_USB_GX_H_ + +#include +#include + +/* TOFIX add set_mode to struct phy_ops */ +void phy_meson_gxl_usb2_set_mode(struct phy *phy, enum usb_dr_mode mode); + +int dwc3_meson_gxl_force_mode(struct udevice *dev, enum usb_dr_mode mode); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/usb.h b/roms/u-boot/arch/arm/include/asm/arch-meson/usb.h new file mode 100644 index 000000000..b794b5ce7 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/usb.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef __MESON_USB_H__ +#define __MESON_USB_H__ + +int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode); + +#endif /* __MESON_USB_H__ */ -- cgit 1.2.3-korg