From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001 From: Angelos Mouzakitis Date: Tue, 10 Oct 2023 14:33:42 +0000 Subject: Add submodule dependency files Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec --- roms/u-boot/arch/arm/include/asm/acpi_table.h | 0 .../arch/arm/include/asm/arch-am33xx/chilisom.h | 14 + .../arm/include/asm/arch-am33xx/clk_synthesizer.h | 40 + .../arch/arm/include/asm/arch-am33xx/clock.h | 135 + .../arm/include/asm/arch-am33xx/clock_ti81xx.h | 142 + .../arm/include/asm/arch-am33xx/clocks_am33xx.h | 35 + roms/u-boot/arch/arm/include/asm/arch-am33xx/cpu.h | 612 ++ .../arch/arm/include/asm/arch-am33xx/ddr_defs.h | 383 + .../arch/arm/include/asm/arch-am33xx/emac_defs.h | 37 + .../u-boot/arch/arm/include/asm/arch-am33xx/gpio.h | 30 + .../arch/arm/include/asm/arch-am33xx/hardware.h | 89 + .../arm/include/asm/arch-am33xx/hardware_am33xx.h | 76 + .../arm/include/asm/arch-am33xx/hardware_am43xx.h | 94 + .../arm/include/asm/arch-am33xx/hardware_ti814x.h | 60 + .../arm/include/asm/arch-am33xx/hardware_ti816x.h | 62 + roms/u-boot/arch/arm/include/asm/arch-am33xx/i2c.h | 20 + roms/u-boot/arch/arm/include/asm/arch-am33xx/mem.h | 63 + .../arm/include/asm/arch-am33xx/mmc_host_def.h | 35 + roms/u-boot/arch/arm/include/asm/arch-am33xx/mux.h | 46 + .../arch/arm/include/asm/arch-am33xx/mux_am33xx.h | 246 + .../arch/arm/include/asm/arch-am33xx/mux_am43xx.h | 210 + .../arch/arm/include/asm/arch-am33xx/mux_ti814x.h | 311 + .../arch/arm/include/asm/arch-am33xx/mux_ti816x.h | 362 + .../u-boot/arch/arm/include/asm/arch-am33xx/omap.h | 48 + roms/u-boot/arch/arm/include/asm/arch-am33xx/spl.h | 72 + .../arch/arm/include/asm/arch-am33xx/sys_proto.h | 49 + .../arm/include/asm/arch-armada100/armada100.h | 59 + .../arch/arm/include/asm/arch-armada100/config.h | 27 + .../arch/arm/include/asm/arch-armada100/cpu.h | 161 + .../arch/arm/include/asm/arch-armada100/gpio.h | 31 + .../arch/arm/include/asm/arch-armada100/mfp.h | 79 + .../arch/arm/include/asm/arch-armada100/spi.h | 78 + .../include/asm/arch-armada100/utmi-armada100.h | 62 + .../arch/arm/include/asm/arch-armada8k/cache_llc.h | 20 + .../arch/arm/include/asm/arch-armada8k/soc-info.h | 16 + .../arch/arm/include/asm/arch-armv7/generictimer.h | 50 + .../arch/arm/include/asm/arch-armv7/globaltimer.h | 19 + .../arch/arm/include/asm/arch-armv7/sysctrl.h | 53 + .../arch/arm/include/asm/arch-armv7/systimer.h | 35 + roms/u-boot/arch/arm/include/asm/arch-armv7/wdt.h | 38 + .../arch/arm/include/asm/arch-aspeed/boot0.h | 23 + .../arch/arm/include/asm/arch-aspeed/pinctrl.h | 51 + .../arch/arm/include/asm/arch-aspeed/platform.h | 25 + .../arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 247 + .../arch/arm/include/asm/arch-aspeed/scu_ast2600.h | 338 + .../arm/include/asm/arch-aspeed/sdram_ast2500.h | 137 + .../arm/include/asm/arch-aspeed/sdram_ast2600.h | 163 + .../arch/arm/include/asm/arch-aspeed/timer.h | 53 + roms/u-boot/arch/arm/include/asm/arch-aspeed/wdt.h | 113 + .../arch/arm/include/asm/arch-aspeed/wdt_ast2600.h | 129 + .../arch/arm/include/asm/arch-bcm235xx/boot0.h | 10 + .../arch/arm/include/asm/arch-bcm235xx/gpio.h | 14 + .../arch/arm/include/asm/arch-bcm235xx/sysmap.h | 30 + .../arch/arm/include/asm/arch-bcm281xx/boot0.h | 10 + .../arch/arm/include/asm/arch-bcm281xx/gpio.h | 14 + .../arch/arm/include/asm/arch-bcm281xx/sysmap.h | 36 + .../arch/arm/include/asm/arch-bcmcygnus/configs.h | 26 + .../arch/arm/include/asm/arch-bcmns3/bl33_info.h | 26 + .../arch/arm/include/asm/arch-bcmnsp/configs.h | 20 + .../arch/arm/include/asm/arch-ep93xx/ep93xx.h | 666 ++ .../arm/include/asm/arch-fsl-layerscape/clock.h | 23 + .../arm/include/asm/arch-fsl-layerscape/config.h | 409 + .../arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 96 + .../arch/arm/include/asm/arch-fsl-layerscape/fdt.h | 10 + .../arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 193 + .../include/asm/arch-fsl-layerscape/fsl_portals.h | 24 + .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 218 + .../arm/include/asm/arch-fsl-layerscape/gpio.h | 22 + .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 712 ++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 603 ++ .../arm/include/asm/arch-fsl-layerscape/imx-regs.h | 12 + .../arch/arm/include/asm/arch-fsl-layerscape/mmu.h | 9 + .../arch/arm/include/asm/arch-fsl-layerscape/mp.h | 49 + .../include/asm/arch-fsl-layerscape/ns_access.h | 91 + .../arch/arm/include/asm/arch-fsl-layerscape/ppa.h | 12 + .../arch/arm/include/asm/arch-fsl-layerscape/soc.h | 142 + .../arm/include/asm/arch-fsl-layerscape/speed.h | 12 + .../asm/arch-fsl-layerscape/stream_id_lsch2.h | 63 + .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 137 + .../arch/arm/include/asm/arch-fsl-layerscape/svr.h | 42 + .../arch/arm/include/asm/arch-hi3660/hi3660.h | 56 + .../arm/include/asm/arch-hi3798cv200/hi3798cv200.h | 53 + .../arch/arm/include/asm/arch-hi6220/dwmmc.h | 7 + .../u-boot/arch/arm/include/asm/arch-hi6220/gpio.h | 26 + .../arch/arm/include/asm/arch-hi6220/hi6220.h | 389 + .../include/asm/arch-hi6220/hi6220_regs_alwayson.h | 419 + .../arch/arm/include/asm/arch-hi6220/periph.h | 29 + .../arch/arm/include/asm/arch-hi6220/pinmux.h | 81 + roms/u-boot/arch/arm/include/asm/arch-imx/cpu.h | 96 + roms/u-boot/arch/arm/include/asm/arch-imx8/boot0.h | 21 + roms/u-boot/arch/arm/include/asm/arch-imx8/clock.h | 27 + roms/u-boot/arch/arm/include/asm/arch-imx8/gpio.h | 21 + roms/u-boot/arch/arm/include/asm/arch-imx8/image.h | 67 + .../arch/arm/include/asm/arch-imx8/imx-regs.h | 50 + .../arch/arm/include/asm/arch-imx8/imx8-pins.h | 17 + roms/u-boot/arch/arm/include/asm/arch-imx8/iomux.h | 44 + .../arch/arm/include/asm/arch-imx8/power-domain.h | 15 + .../arch/arm/include/asm/arch-imx8/sci/rpc.h | 230 + .../arch/arm/include/asm/arch-imx8/sci/sci.h | 138 + .../arm/include/asm/arch-imx8/sci/svc/misc/api.h | 31 + .../arm/include/asm/arch-imx8/sci/svc/pad/api.h | 60 + .../arm/include/asm/arch-imx8/sci/svc/pm/api.h | 44 + .../arm/include/asm/arch-imx8/sci/svc/rm/api.h | 69 + .../arm/include/asm/arch-imx8/sci/svc/seco/api.h | 37 + .../arch/arm/include/asm/arch-imx8/sci/types.h | 226 + .../arm/include/asm/arch-imx8/snvs_security_sc.h | 11 + .../arch/arm/include/asm/arch-imx8/sys_proto.h | 32 + .../u-boot/arch/arm/include/asm/arch-imx8m/clock.h | 278 + .../arch/arm/include/asm/arch-imx8m/clock_imx8mm.h | 580 ++ .../arch/arm/include/asm/arch-imx8m/clock_imx8mq.h | 431 + .../arch/arm/include/asm/arch-imx8m/crm_regs.h | 9 + roms/u-boot/arch/arm/include/asm/arch-imx8m/ddr.h | 750 ++ roms/u-boot/arch/arm/include/asm/arch-imx8m/gpio.h | 11 + .../arch/arm/include/asm/arch-imx8m/imx-regs.h | 517 + .../arch/arm/include/asm/arch-imx8m/imx8mm_pins.h | 691 ++ .../arch/arm/include/asm/arch-imx8m/imx8mn_pins.h | 763 ++ .../arch/arm/include/asm/arch-imx8m/imx8mp_pins.h | 1080 ++ .../arch/arm/include/asm/arch-imx8m/imx8mq_pins.h | 622 ++ .../arm/include/asm/arch-imx8m/lpddr4_define.h | 97 + .../arch/arm/include/asm/arch-imx8m/power-domain.h | 15 + .../arch/arm/include/asm/arch-imx8m/sys_proto.h | 17 + .../u-boot/arch/arm/include/asm/arch-imxrt/clock.h | 10 + roms/u-boot/arch/arm/include/asm/arch-imxrt/gpio.h | 19 + .../arch/arm/include/asm/arch-imxrt/imx-regs.h | 30 + .../u-boot/arch/arm/include/asm/arch-imxrt/imxrt.h | 11 + .../arch/arm/include/asm/arch-imxrt/sys_proto.h | 11 + .../u-boot/arch/arm/include/asm/arch-lpc32xx/clk.h | 186 + .../arch/arm/include/asm/arch-lpc32xx/config.h | 72 + .../u-boot/arch/arm/include/asm/arch-lpc32xx/cpu.h | 53 + .../u-boot/arch/arm/include/asm/arch-lpc32xx/dma.h | 64 + .../u-boot/arch/arm/include/asm/arch-lpc32xx/emc.h | 99 + .../arch/arm/include/asm/arch-lpc32xx/gpio.h | 42 + .../arch/arm/include/asm/arch-lpc32xx/gpio_grp.h | 39 + .../u-boot/arch/arm/include/asm/arch-lpc32xx/i2c.h | 36 + .../u-boot/arch/arm/include/asm/arch-lpc32xx/mux.h | 34 + .../arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 22 + .../arch/arm/include/asm/arch-lpc32xx/timer.h | 60 + .../arch/arm/include/asm/arch-lpc32xx/uart.h | 100 + .../u-boot/arch/arm/include/asm/arch-lpc32xx/wdt.h | 37 + .../arch/arm/include/asm/arch-ls102xa/clock.h | 21 + .../arch/arm/include/asm/arch-ls102xa/config.h | 116 + .../arch/arm/include/asm/arch-ls102xa/fsl_serdes.h | 36 + .../arch/arm/include/asm/arch-ls102xa/gpio.h | 32 + .../arm/include/asm/arch-ls102xa/immap_ls102xa.h | 432 + .../arch/arm/include/asm/arch-ls102xa/imx-regs.h | 12 + .../arm/include/asm/arch-ls102xa/ls102xa_devdis.h | 51 + .../arm/include/asm/arch-ls102xa/ls102xa_soc.h | 19 + .../include/asm/arch-ls102xa/ls102xa_stream_id.h | 73 + .../arch/arm/include/asm/arch-ls102xa/ns_access.h | 94 + .../u-boot/arch/arm/include/asm/arch-ls102xa/soc.h | 0 .../u-boot/arch/arm/include/asm/arch-ls102xa/spl.h | 19 + .../u-boot/arch/arm/include/asm/arch-ls102xa/svr.h | 13 + .../arch/arm/include/asm/arch-mediatek/gpio.h | 9 + .../arch/arm/include/asm/arch-mediatek/misc.h | 17 + .../arch/arm/include/asm/arch-mediatek/reset.h | 13 + roms/u-boot/arch/arm/include/asm/arch-meson/axg.h | 34 + roms/u-boot/arch/arm/include/asm/arch-meson/boot.h | 24 + .../arch/arm/include/asm/arch-meson/clock-axg.h | 104 + .../arch/arm/include/asm/arch-meson/clock-g12a.h | 104 + .../arch/arm/include/asm/arch-meson/clock-gx.h | 117 + roms/u-boot/arch/arm/include/asm/arch-meson/eth.h | 13 + roms/u-boot/arch/arm/include/asm/arch-meson/g12a.h | 35 + roms/u-boot/arch/arm/include/asm/arch-meson/gpio.h | 10 + roms/u-boot/arch/arm/include/asm/arch-meson/gx.h | 44 + roms/u-boot/arch/arm/include/asm/arch-meson/i2c.h | 10 + roms/u-boot/arch/arm/include/asm/arch-meson/mem.h | 16 + .../arch/arm/include/asm/arch-meson/meson-vpu.h | 13 + roms/u-boot/arch/arm/include/asm/arch-meson/sm.h | 33 + .../arch/arm/include/asm/arch-meson/usb-gx.h | 17 + roms/u-boot/arch/arm/include/asm/arch-meson/usb.h | 12 + roms/u-boot/arch/arm/include/asm/arch-mvebu/spi.h | 60 + roms/u-boot/arch/arm/include/asm/arch-mx25/clock.h | 57 + roms/u-boot/arch/arm/include/asm/arch-mx25/gpio.h | 13 + .../arch/arm/include/asm/arch-mx25/imx-regs.h | 504 + .../arch/arm/include/asm/arch-mx25/iomux-mx25.h | 537 + roms/u-boot/arch/arm/include/asm/arch-mx25/macro.h | 90 + roms/u-boot/arch/arm/include/asm/arch-mx27/clock.h | 22 + roms/u-boot/arch/arm/include/asm/arch-mx27/gpio.h | 58 + .../arch/arm/include/asm/arch-mx27/imx-regs.h | 480 + .../u-boot/arch/arm/include/asm/arch-mx27/mxcmmc.h | 11 + .../arch/arm/include/asm/arch-mx27/regs-rtc.h | 26 + roms/u-boot/arch/arm/include/asm/arch-mx31/clock.h | 35 + roms/u-boot/arch/arm/include/asm/arch-mx31/gpio.h | 13 + .../arch/arm/include/asm/arch-mx31/imx-regs.h | 895 ++ .../arch/arm/include/asm/arch-mx31/sys_proto.h | 20 + roms/u-boot/arch/arm/include/asm/arch-mx35/clock.h | 67 + .../arch/arm/include/asm/arch-mx35/crm_regs.h | 243 + roms/u-boot/arch/arm/include/asm/arch-mx35/gpio.h | 13 + .../arch/arm/include/asm/arch-mx35/imx-regs.h | 356 + .../arch/arm/include/asm/arch-mx35/iomux-mx35.h | 1259 +++ .../arm/include/asm/arch-mx35/lowlevel_macro.S | 125 + .../arch/arm/include/asm/arch-mx35/mmc_host_def.h | 14 + .../arch/arm/include/asm/arch-mx35/sys_proto.h | 15 + roms/u-boot/arch/arm/include/asm/arch-mx5/clock.h | 56 + .../arch/arm/include/asm/arch-mx5/crm_regs.h | 616 ++ roms/u-boot/arch/arm/include/asm/arch-mx5/gpio.h | 13 + .../arch/arm/include/asm/arch-mx5/imx-regs.h | 526 + .../arch/arm/include/asm/arch-mx5/iomux-mx51.h | 241 + .../arch/arm/include/asm/arch-mx5/iomux-mx53.h | 1215 +++ .../arch/arm/include/asm/arch-mx5/sys_proto.h | 11 + roms/u-boot/arch/arm/include/asm/arch-mx6/clock.h | 87 + .../arch/arm/include/asm/arch-mx6/crm_regs.h | 1309 +++ roms/u-boot/arch/arm/include/asm/arch-mx6/gpio.h | 13 + .../u-boot/arch/arm/include/asm/arch-mx6/imx-rdc.h | 15 + .../arch/arm/include/asm/arch-mx6/imx-regs.h | 972 ++ roms/u-boot/arch/arm/include/asm/arch-mx6/iomux.h | 192 + .../u-boot/arch/arm/include/asm/arch-mx6/litesom.h | 15 + .../u-boot/arch/arm/include/asm/arch-mx6/mx6-ddr.h | 549 + .../arch/arm/include/asm/arch-mx6/mx6-pins.h | 49 + .../arch/arm/include/asm/arch-mx6/mx6_plugin.S | 158 + .../arch/arm/include/asm/arch-mx6/mx6dl-ddr.h | 58 + .../arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 1079 ++ .../arch/arm/include/asm/arch-mx6/mx6q-ddr.h | 56 + .../arch/arm/include/asm/arch-mx6/mx6q_pins.h | 1035 ++ .../arch/arm/include/asm/arch-mx6/mx6sl-ddr.h | 44 + .../arch/arm/include/asm/arch-mx6/mx6sl_pins.h | 72 + .../arch/arm/include/asm/arch-mx6/mx6sll_pins.h | 1018 ++ .../arch/arm/include/asm/arch-mx6/mx6sx-ddr.h | 44 + .../arch/arm/include/asm/arch-mx6/mx6sx_pins.h | 1674 +++ .../arch/arm/include/asm/arch-mx6/mx6sx_rdc.h | 154 + .../arch/arm/include/asm/arch-mx6/mx6ul-ddr.h | 44 + .../arch/arm/include/asm/arch-mx6/mx6ul_pins.h | 1064 ++ .../arch/arm/include/asm/arch-mx6/mx6ull_pins.h | 1064 ++ .../arch/arm/include/asm/arch-mx6/mxc_hdmi.h | 1057 ++ .../u-boot/arch/arm/include/asm/arch-mx6/opos6ul.h | 11 + .../arch/arm/include/asm/arch-mx6/sys_proto.h | 41 + roms/u-boot/arch/arm/include/asm/arch-mx7/clock.h | 364 + .../arch/arm/include/asm/arch-mx7/clock_slice.h | 115 + .../arch/arm/include/asm/arch-mx7/crm_regs.h | 2817 +++++ roms/u-boot/arch/arm/include/asm/arch-mx7/gpio.h | 11 + .../u-boot/arch/arm/include/asm/arch-mx7/imx-rdc.h | 15 + .../arch/arm/include/asm/arch-mx7/imx-regs.h | 1192 +++ .../u-boot/arch/arm/include/asm/arch-mx7/mx7-ddr.h | 170 + .../arch/arm/include/asm/arch-mx7/mx7-pins.h | 18 + .../arch/arm/include/asm/arch-mx7/mx7_plugin.S | 110 + .../arch/arm/include/asm/arch-mx7/mx7d_pins.h | 1307 +++ .../arch/arm/include/asm/arch-mx7/mx7d_rdc.h | 162 + .../arch/arm/include/asm/arch-mx7/sys_proto.h | 13 + .../arch/arm/include/asm/arch-mx7ulp/clock.h | 41 + .../u-boot/arch/arm/include/asm/arch-mx7ulp/gpio.h | 21 + .../arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 1157 +++ .../arch/arm/include/asm/arch-mx7ulp/iomux.h | 94 + .../arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h | 909 ++ .../arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S | 93 + roms/u-boot/arch/arm/include/asm/arch-mx7ulp/pcc.h | 371 + roms/u-boot/arch/arm/include/asm/arch-mx7ulp/scg.h | 339 + .../arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 21 + roms/u-boot/arch/arm/include/asm/arch-mxs/clock.h | 53 + roms/u-boot/arch/arm/include/asm/arch-mxs/gpio.h | 18 + .../arch/arm/include/asm/arch-mxs/imx-regs.h | 38 + .../arch/arm/include/asm/arch-mxs/iomux-mx23.h | 349 + .../arch/arm/include/asm/arch-mxs/iomux-mx28.h | 531 + roms/u-boot/arch/arm/include/asm/arch-mxs/iomux.h | 164 + .../arch/arm/include/asm/arch-mxs/regs-base.h | 120 + .../arm/include/asm/arch-mxs/regs-clkctrl-mx23.h | 209 + .../arm/include/asm/arch-mxs/regs-clkctrl-mx28.h | 287 + .../arch/arm/include/asm/arch-mxs/regs-digctl.h | 146 + .../arch/arm/include/asm/arch-mxs/regs-i2c.h | 193 + .../arch/arm/include/asm/arch-mxs/regs-lradc.h | 386 + .../arch/arm/include/asm/arch-mxs/regs-ocotp.h | 159 + .../arch/arm/include/asm/arch-mxs/regs-pinctrl.h | 1270 +++ .../arm/include/asm/arch-mxs/regs-power-mx23.h | 344 + .../arm/include/asm/arch-mxs/regs-power-mx28.h | 399 + .../arch/arm/include/asm/arch-mxs/regs-rtc.h | 133 + .../arch/arm/include/asm/arch-mxs/regs-ssp.h | 415 + .../arch/arm/include/asm/arch-mxs/regs-timrot.h | 258 + .../arch/arm/include/asm/arch-mxs/regs-uartapp.h | 219 + .../arch/arm/include/asm/arch-mxs/regs-usb.h | 164 + .../arch/arm/include/asm/arch-mxs/regs-usbphy.h | 137 + .../arch/arm/include/asm/arch-mxs/sys_proto.h | 97 + .../arch/arm/include/asm/arch-octeontx/board.h | 123 + .../arch/arm/include/asm/arch-octeontx/clock.h | 25 + .../include/asm/arch-octeontx/csrs/csrs-mio_emm.h | 1193 +++ .../arm/include/asm/arch-octeontx/csrs/csrs-xcv.h | 428 + .../arch/arm/include/asm/arch-octeontx/gpio.h | 6 + .../arch/arm/include/asm/arch-octeontx/smc.h | 20 + .../arch/arm/include/asm/arch-octeontx/soc.h | 33 + .../arch/arm/include/asm/arch-octeontx2/board.h | 128 + .../arch/arm/include/asm/arch-octeontx2/clock.h | 24 + .../arm/include/asm/arch-octeontx2/csrs/csrs-cgx.h | 7851 ++++++++++++++ .../arm/include/asm/arch-octeontx2/csrs/csrs-lmt.h | 60 + .../include/asm/arch-octeontx2/csrs/csrs-mio_emm.h | 1193 +++ .../arm/include/asm/arch-octeontx2/csrs/csrs-nix.h | 10404 +++++++++++++++++++ .../arm/include/asm/arch-octeontx2/csrs/csrs-npa.h | 2294 ++++ .../arm/include/asm/arch-octeontx2/csrs/csrs-npc.h | 1629 +++ .../arm/include/asm/arch-octeontx2/csrs/csrs-rvu.h | 2276 ++++ .../arch/arm/include/asm/arch-octeontx2/gpio.h | 6 + .../arch/arm/include/asm/arch-octeontx2/smc-id.h | 32 + .../arch/arm/include/asm/arch-octeontx2/smc.h | 18 + .../arch/arm/include/asm/arch-octeontx2/soc.h | 33 + .../arch/arm/include/asm/arch-omap3/am35x_def.h | 69 + .../u-boot/arch/arm/include/asm/arch-omap3/clock.h | 63 + .../arch/arm/include/asm/arch-omap3/clocks_omap3.h | 347 + roms/u-boot/arch/arm/include/asm/arch-omap3/cpu.h | 504 + roms/u-boot/arch/arm/include/asm/arch-omap3/dma.h | 63 + roms/u-boot/arch/arm/include/asm/arch-omap3/dss.h | 233 + roms/u-boot/arch/arm/include/asm/arch-omap3/ehci.h | 38 + .../arch/arm/include/asm/arch-omap3/emac_defs.h | 41 + .../u-boot/arch/arm/include/asm/arch-omap3/emif4.h | 65 + roms/u-boot/arch/arm/include/asm/arch-omap3/gpio.h | 34 + roms/u-boot/arch/arm/include/asm/arch-omap3/i2c.h | 11 + roms/u-boot/arch/arm/include/asm/arch-omap3/mem.h | 488 + .../arch/arm/include/asm/arch-omap3/mmc_host_def.h | 67 + roms/u-boot/arch/arm/include/asm/arch-omap3/musb.h | 12 + roms/u-boot/arch/arm/include/asm/arch-omap3/mux.h | 497 + roms/u-boot/arch/arm/include/asm/arch-omap3/omap.h | 284 + .../arch/arm/include/asm/arch-omap3/omap3-regs.h | 78 + roms/u-boot/arch/arm/include/asm/arch-omap3/spl.h | 22 + .../arch/arm/include/asm/arch-omap3/sys_proto.h | 77 + .../u-boot/arch/arm/include/asm/arch-omap4/clock.h | 251 + roms/u-boot/arch/arm/include/asm/arch-omap4/cpu.h | 109 + roms/u-boot/arch/arm/include/asm/arch-omap4/ehci.h | 38 + roms/u-boot/arch/arm/include/asm/arch-omap4/gpio.h | 34 + .../arch/arm/include/asm/arch-omap4/hardware.h | 25 + roms/u-boot/arch/arm/include/asm/arch-omap4/i2c.h | 11 + roms/u-boot/arch/arm/include/asm/arch-omap4/mem.h | 61 + .../arch/arm/include/asm/arch-omap4/mmc_host_def.h | 38 + .../arch/arm/include/asm/arch-omap4/mux_omap4.h | 328 + roms/u-boot/arch/arm/include/asm/arch-omap4/omap.h | 143 + roms/u-boot/arch/arm/include/asm/arch-omap4/spl.h | 22 + .../arch/arm/include/asm/arch-omap4/sys_proto.h | 71 + .../u-boot/arch/arm/include/asm/arch-omap5/clock.h | 416 + roms/u-boot/arch/arm/include/asm/arch-omap5/cpu.h | 133 + .../arm/include/asm/arch-omap5/dra7xx_iodelay.h | 92 + roms/u-boot/arch/arm/include/asm/arch-omap5/ehci.h | 29 + roms/u-boot/arch/arm/include/asm/arch-omap5/gpio.h | 40 + .../arch/arm/include/asm/arch-omap5/hardware.h | 30 + roms/u-boot/arch/arm/include/asm/arch-omap5/i2c.h | 11 + roms/u-boot/arch/arm/include/asm/arch-omap5/mem.h | 61 + .../arch/arm/include/asm/arch-omap5/mmc_host_def.h | 38 + .../arch/arm/include/asm/arch-omap5/mux_dra7xx.h | 356 + .../arch/arm/include/asm/arch-omap5/mux_omap5.h | 317 + roms/u-boot/arch/arm/include/asm/arch-omap5/omap.h | 271 + roms/u-boot/arch/arm/include/asm/arch-omap5/sata.h | 38 + roms/u-boot/arch/arm/include/asm/arch-omap5/spl.h | 26 + .../arch/arm/include/asm/arch-omap5/sys_proto.h | 92 + .../u-boot/arch/arm/include/asm/arch-orion5x/spl.h | 9 + .../arch/arm/include/asm/arch-owl/regs_s700.h | 64 + .../arch/arm/include/asm/arch-owl/regs_s900.h | 68 + roms/u-boot/arch/arm/include/asm/arch-px30/boot0.h | 11 + roms/u-boot/arch/arm/include/asm/arch-px30/gpio.h | 11 + .../arch/arm/include/asm/arch-pxa/bitfield.h | 112 + roms/u-boot/arch/arm/include/asm/arch-pxa/config.h | 24 + .../arch/arm/include/asm/arch-pxa/hardware.h | 82 + .../arch/arm/include/asm/arch-pxa/pxa-regs.h | 2635 +++++ roms/u-boot/arch/arm/include/asm/arch-pxa/pxa.h | 28 + .../arch/arm/include/asm/arch-pxa/regs-mmc.h | 140 + .../arch/arm/include/asm/arch-pxa/regs-uart.h | 95 + .../arch/arm/include/asm/arch-pxa/regs-usb.h | 146 + .../arch/arm/include/asm/arch-rk3036/boot0.h | 11 + .../u-boot/arch/arm/include/asm/arch-rk3036/gpio.h | 11 + .../arch/arm/include/asm/arch-rk3128/boot0.h | 11 + .../u-boot/arch/arm/include/asm/arch-rk3128/gpio.h | 11 + .../arch/arm/include/asm/arch-rk3188/boot0.h | 11 + .../u-boot/arch/arm/include/asm/arch-rk3188/gpio.h | 11 + .../arch/arm/include/asm/arch-rk322x/boot0.h | 11 + .../u-boot/arch/arm/include/asm/arch-rk322x/gpio.h | 11 + .../arch/arm/include/asm/arch-rk3288/boot0.h | 11 + .../u-boot/arch/arm/include/asm/arch-rk3288/gpio.h | 11 + .../arch/arm/include/asm/arch-rk3308/boot0.h | 11 + .../arch/arm/include/asm/arch-rk3308/cru_rk3308.h | 288 + .../u-boot/arch/arm/include/asm/arch-rk3308/gpio.h | 11 + .../arch/arm/include/asm/arch-rk3308/grf_rk3308.h | 195 + .../arch/arm/include/asm/arch-rk3328/boot0.h | 11 + .../u-boot/arch/arm/include/asm/arch-rk3328/gpio.h | 11 + .../arch/arm/include/asm/arch-rk3368/boot0.h | 11 + .../u-boot/arch/arm/include/asm/arch-rk3368/gpio.h | 11 + .../arch/arm/include/asm/arch-rk3399/boot0.h | 11 + .../u-boot/arch/arm/include/asm/arch-rk3399/gpio.h | 11 + .../arch/arm/include/asm/arch-rockchip/boot0.h | 60 + .../arch/arm/include/asm/arch-rockchip/boot_mode.h | 25 + .../arch/arm/include/asm/arch-rockchip/bootrom.h | 62 + .../arch/arm/include/asm/arch-rockchip/clock.h | 175 + .../arm/include/asm/arch-rockchip/cpu_rk3288.h | 49 + .../arch/arm/include/asm/arch-rockchip/cru.h | 35 + .../arch/arm/include/asm/arch-rockchip/cru_px30.h | 449 + .../arm/include/asm/arch-rockchip/cru_rk3036.h | 171 + .../arm/include/asm/arch-rockchip/cru_rk3128.h | 213 + .../arm/include/asm/arch-rockchip/cru_rk3188.h | 191 + .../arm/include/asm/arch-rockchip/cru_rk322x.h | 209 + .../arm/include/asm/arch-rockchip/cru_rk3288.h | 230 + .../arm/include/asm/arch-rockchip/cru_rk3328.h | 70 + .../arm/include/asm/arch-rockchip/cru_rk3368.h | 142 + .../arm/include/asm/arch-rockchip/cru_rk3399.h | 112 + .../arm/include/asm/arch-rockchip/cru_rv1108.h | 260 + .../arm/include/asm/arch-rockchip/ddr_rk3188.h | 24 + .../arm/include/asm/arch-rockchip/ddr_rk3288.h | 443 + .../arm/include/asm/arch-rockchip/ddr_rk3368.h | 190 + .../arm/include/asm/arch-rockchip/edp_rk3288.h | 638 ++ .../arch/arm/include/asm/arch-rockchip/f_rockusb.h | 136 + .../arch/arm/include/asm/arch-rockchip/gpio.h | 57 + .../arch/arm/include/asm/arch-rockchip/grf_px30.h | 142 + .../arm/include/asm/arch-rockchip/grf_rk3036.h | 80 + .../arm/include/asm/arch-rockchip/grf_rk3128.h | 548 + .../arm/include/asm/arch-rockchip/grf_rk3188.h | 250 + .../arm/include/asm/arch-rockchip/grf_rk322x.h | 93 + .../arm/include/asm/arch-rockchip/grf_rk3288.h | 1155 ++ .../arm/include/asm/arch-rockchip/grf_rk3328.h | 133 + .../arm/include/asm/arch-rockchip/grf_rk3368.h | 137 + .../arm/include/asm/arch-rockchip/grf_rk3399.h | 672 ++ .../arm/include/asm/arch-rockchip/grf_rv1108.h | 111 + .../arch/arm/include/asm/arch-rockchip/hardware.h | 18 + .../arch/arm/include/asm/arch-rockchip/i2c.h | 69 + .../arm/include/asm/arch-rockchip/lvds_rk3288.h | 100 + .../arch/arm/include/asm/arch-rockchip/misc.h | 13 + .../arch/arm/include/asm/arch-rockchip/periph.h | 62 + .../arm/include/asm/arch-rockchip/pmu_rk3188.h | 35 + .../arm/include/asm/arch-rockchip/pmu_rk3288.h | 92 + .../arm/include/asm/arch-rockchip/pmu_rk3399.h | 72 + .../arch/arm/include/asm/arch-rockchip/pwm.h | 47 + .../arm/include/asm/arch-rockchip/qos_rk3288.h | 19 + .../include/asm/arch-rockchip/rockchip_mipi_dsi.h | 194 + .../arch/arm/include/asm/arch-rockchip/sdram.h | 86 + .../arm/include/asm/arch-rockchip/sdram_common.h | 144 + .../arm/include/asm/arch-rockchip/sdram_msch.h | 85 + .../include/asm/arch-rockchip/sdram_pctl_px30.h | 143 + .../arm/include/asm/arch-rockchip/sdram_phy_px30.h | 66 + .../asm/arch-rockchip/sdram_phy_ron_rtt_px30.h | 59 + .../arm/include/asm/arch-rockchip/sdram_px30.h | 134 + .../arm/include/asm/arch-rockchip/sdram_rk3036.h | 338 + .../arm/include/asm/arch-rockchip/sdram_rk322x.h | 575 + .../arm/include/asm/arch-rockchip/sdram_rk3288.h | 102 + .../arm/include/asm/arch-rockchip/sdram_rk3328.h | 265 + .../arm/include/asm/arch-rockchip/sdram_rk3399.h | 100 + .../arch/arm/include/asm/arch-rockchip/sys_proto.h | 9 + .../arch/arm/include/asm/arch-rockchip/timer.h | 18 + .../arch/arm/include/asm/arch-rockchip/uart.h | 43 + .../arm/include/asm/arch-rockchip/vop_rk3288.h | 359 + .../arch/arm/include/asm/arch-rv1108/boot0.h | 11 + .../u-boot/arch/arm/include/asm/arch-rv1108/gpio.h | 11 + .../arch/arm/include/asm/arch-sa1100/bitfield.h | 112 + roms/u-boot/arch/arm/include/asm/arch-spear/clk.h | 10 + roms/u-boot/arch/arm/include/asm/arch-spear/gpio.h | 23 + .../arch/arm/include/asm/arch-spear/hardware.h | 72 + .../arch/arm/include/asm/arch-spear/spr_defs.h | 50 + .../arch/arm/include/asm/arch-spear/spr_emi.h | 37 + .../arch/arm/include/asm/arch-spear/spr_gpt.h | 68 + .../arch/arm/include/asm/arch-spear/spr_misc.h | 260 + .../arch/arm/include/asm/arch-spear/spr_ssp.h | 28 + .../arch/arm/include/asm/arch-spear/spr_syscntl.h | 35 + .../arch/arm/include/asm/arch-stih410/sdhci.h | 72 + .../arch/arm/include/asm/arch-stih410/sys_proto.h | 10 + roms/u-boot/arch/arm/include/asm/arch-stm32/gpio.h | 86 + .../arch/arm/include/asm/arch-stm32/stm32f.h | 21 + .../arch/arm/include/asm/arch-stm32f4/gpio.h | 15 + .../arch/arm/include/asm/arch-stm32f4/stm32.h | 40 + .../arch/arm/include/asm/arch-stm32f4/stm32_pwr.h | 27 + .../arch/arm/include/asm/arch-stm32f7/gpio.h | 12 + .../arch/arm/include/asm/arch-stm32f7/stm32.h | 18 + .../arch/arm/include/asm/arch-stm32f7/stm32_pwr.h | 29 + .../arch/arm/include/asm/arch-stm32f7/syscfg.h | 32 + .../arch/arm/include/asm/arch-stm32h7/gpio.h | 12 + .../arch/arm/include/asm/arch-stm32h7/stm32.h | 20 + .../arch/arm/include/asm/arch-stv0991/gpio.h | 21 + .../arch/arm/include/asm/arch-stv0991/hardware.h | 72 + .../arm/include/asm/arch-stv0991/stv0991_cgu.h | 130 + .../arm/include/asm/arch-stv0991/stv0991_creg.h | 103 + .../arm/include/asm/arch-stv0991/stv0991_defs.h | 15 + .../arm/include/asm/arch-stv0991/stv0991_gpt.h | 42 + .../arm/include/asm/arch-stv0991/stv0991_periph.h | 45 + .../arm/include/asm/arch-stv0991/stv0991_wdru.h | 27 + .../u-boot/arch/arm/include/asm/arch-sunxi/boot0.h | 56 + roms/u-boot/arch/arm/include/asm/arch-sunxi/ccu.h | 100 + .../u-boot/arch/arm/include/asm/arch-sunxi/clock.h | 39 + .../arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 362 + .../arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 341 + .../arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 533 + .../arm/include/asm/arch-sunxi/clock_sun8i_a83t.h | 305 + .../arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 230 + roms/u-boot/arch/arm/include/asm/arch-sunxi/cpu.h | 23 + .../arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 220 + .../arm/include/asm/arch-sunxi/cpu_sun50i_h6.h | 81 + .../arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 118 + .../arch/arm/include/asm/arch-sunxi/cpucfg.h | 67 + .../arch/arm/include/asm/arch-sunxi/display.h | 352 + .../arch/arm/include/asm/arch-sunxi/display2.h | 140 + roms/u-boot/arch/arm/include/asm/arch-sunxi/dma.h | 15 + .../arch/arm/include/asm/arch-sunxi/dma_sun4i.h | 67 + roms/u-boot/arch/arm/include/asm/arch-sunxi/dram.h | 42 + .../arch/arm/include/asm/arch-sunxi/dram_sun4i.h | 180 + .../arm/include/asm/arch-sunxi/dram_sun50i_h6.h | 336 + .../arm/include/asm/arch-sunxi/dram_sun50i_h616.h | 159 + .../arch/arm/include/asm/arch-sunxi/dram_sun6i.h | 362 + .../arm/include/asm/arch-sunxi/dram_sun8i_a23.h | 266 + .../arm/include/asm/arch-sunxi/dram_sun8i_a33.h | 182 + .../arm/include/asm/arch-sunxi/dram_sun8i_a83t.h | 211 + .../arch/arm/include/asm/arch-sunxi/dram_sun9i.h | 281 + .../arm/include/asm/arch-sunxi/dram_sunxi_dw.h | 243 + roms/u-boot/arch/arm/include/asm/arch-sunxi/gpio.h | 255 + .../u-boot/arch/arm/include/asm/arch-sunxi/gtbus.h | 20 + .../arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h | 91 + roms/u-boot/arch/arm/include/asm/arch-sunxi/i2c.h | 32 + roms/u-boot/arch/arm/include/asm/arch-sunxi/lcdc.h | 130 + roms/u-boot/arch/arm/include/asm/arch-sunxi/mmc.h | 138 + roms/u-boot/arch/arm/include/asm/arch-sunxi/p2wi.h | 139 + .../arch/arm/include/asm/arch-sunxi/pmic_bus.h | 17 + roms/u-boot/arch/arm/include/asm/arch-sunxi/prcm.h | 18 + .../arch/arm/include/asm/arch-sunxi/prcm_sun50i.h | 47 + .../arch/arm/include/asm/arch-sunxi/prcm_sun6i.h | 247 + roms/u-boot/arch/arm/include/asm/arch-sunxi/pwm.h | 49 + roms/u-boot/arch/arm/include/asm/arch-sunxi/rsb.h | 53 + roms/u-boot/arch/arm/include/asm/arch-sunxi/spl.h | 26 + .../arch/arm/include/asm/arch-sunxi/sys_proto.h | 32 + .../u-boot/arch/arm/include/asm/arch-sunxi/timer.h | 87 + roms/u-boot/arch/arm/include/asm/arch-sunxi/tve.h | 130 + roms/u-boot/arch/arm/include/asm/arch-sunxi/tzpc.h | 33 + .../arch/arm/include/asm/arch-sunxi/watchdog.h | 46 + roms/u-boot/arch/arm/include/asm/arch-tegra/ap.h | 68 + .../arch/arm/include/asm/arch-tegra/apb_misc.h | 21 + .../u-boot/arch/arm/include/asm/arch-tegra/board.h | 33 + .../arch/arm/include/asm/arch-tegra/bpmp_abi.h | 1590 +++ .../u-boot/arch/arm/include/asm/arch-tegra/cboot.h | 48 + .../arch/arm/include/asm/arch-tegra/clk_rst.h | 451 + .../u-boot/arch/arm/include/asm/arch-tegra/clock.h | 423 + roms/u-boot/arch/arm/include/asm/arch-tegra/dc.h | 572 + .../arch/arm/include/asm/arch-tegra/funcmux.h | 28 + roms/u-boot/arch/arm/include/asm/arch-tegra/fuse.h | 22 + .../arch/arm/include/asm/arch-tegra/gp_padctrl.h | 25 + roms/u-boot/arch/arm/include/asm/arch-tegra/gpio.h | 40 + roms/u-boot/arch/arm/include/asm/arch-tegra/gpu.h | 35 + roms/u-boot/arch/arm/include/asm/arch-tegra/ivc.h | 176 + .../arch/arm/include/asm/arch-tegra/pinmux.h | 249 + roms/u-boot/arch/arm/include/asm/arch-tegra/pmc.h | 413 + roms/u-boot/arch/arm/include/asm/arch-tegra/pmu.h | 13 + .../arch/arm/include/asm/arch-tegra/powergate.h | 39 + roms/u-boot/arch/arm/include/asm/arch-tegra/pwm.h | 29 + roms/u-boot/arch/arm/include/asm/arch-tegra/scu.h | 26 + .../arch/arm/include/asm/arch-tegra/sys_proto.h | 34 + .../u-boot/arch/arm/include/asm/arch-tegra/tegra.h | 114 + .../arch/arm/include/asm/arch-tegra/tegra_ahub.h | 475 + .../arch/arm/include/asm/arch-tegra/tegra_i2c.h | 157 + .../arch/arm/include/asm/arch-tegra/tegra_i2s.h | 206 + .../arch/arm/include/asm/arch-tegra/tegra_mmc.h | 148 + .../u-boot/arch/arm/include/asm/arch-tegra/timer.h | 14 + roms/u-boot/arch/arm/include/asm/arch-tegra/uart.h | 30 + roms/u-boot/arch/arm/include/asm/arch-tegra/usb.h | 360 + .../arch/arm/include/asm/arch-tegra/warmboot.h | 133 + .../arch/arm/include/asm/arch-tegra/xusb-padctl.h | 25 + .../arm/include/asm/arch-tegra114/clock-tables.h | 392 + .../arch/arm/include/asm/arch-tegra114/clock.h | 20 + .../arch/arm/include/asm/arch-tegra114/flow.h | 24 + .../arch/arm/include/asm/arch-tegra114/funcmux.h | 20 + .../arm/include/asm/arch-tegra114/gp_padctrl.h | 72 + .../arch/arm/include/asm/arch-tegra114/gpio.h | 19 + .../u-boot/arch/arm/include/asm/arch-tegra114/mc.h | 36 + .../arch/arm/include/asm/arch-tegra114/pinmux.h | 328 + .../arch/arm/include/asm/arch-tegra114/powergate.h | 6 + .../arch/arm/include/asm/arch-tegra114/sysctr.h | 24 + .../arch/arm/include/asm/arch-tegra114/tegra.h | 24 + .../arch/arm/include/asm/arch-tegra124/ahb.h | 90 + .../arm/include/asm/arch-tegra124/clock-tables.h | 497 + .../arch/arm/include/asm/arch-tegra124/clock.h | 44 + .../arch/arm/include/asm/arch-tegra124/display.h | 57 + .../arch/arm/include/asm/arch-tegra124/flow.h | 59 + .../arch/arm/include/asm/arch-tegra124/funcmux.h | 22 + .../arm/include/asm/arch-tegra124/gp_padctrl.h | 73 + .../arch/arm/include/asm/arch-tegra124/gpio.h | 43 + .../u-boot/arch/arm/include/asm/arch-tegra124/mc.h | 71 + .../arch/arm/include/asm/arch-tegra124/pinmux.h | 359 + .../arch/arm/include/asm/arch-tegra124/powergate.h | 6 + .../arch/arm/include/asm/arch-tegra124/pwm.h | 13 + .../arch/arm/include/asm/arch-tegra124/sysctr.h | 25 + .../arch/arm/include/asm/arch-tegra124/tegra.h | 29 + .../arch/arm/include/asm/arch-tegra186/gpio.h | 9 + .../arch/arm/include/asm/arch-tegra186/tegra.h | 15 + .../arm/include/asm/arch-tegra20/clock-tables.h | 185 + .../arch/arm/include/asm/arch-tegra20/clock.h | 19 + .../arch/arm/include/asm/arch-tegra20/display.h | 28 + .../u-boot/arch/arm/include/asm/arch-tegra20/emc.h | 96 + .../arch/arm/include/asm/arch-tegra20/flow.h | 19 + .../arch/arm/include/asm/arch-tegra20/funcmux.h | 51 + .../arch/arm/include/asm/arch-tegra20/gp_padctrl.h | 49 + .../arch/arm/include/asm/arch-tegra20/gpio.h | 35 + roms/u-boot/arch/arm/include/asm/arch-tegra20/mc.h | 35 + .../arch/arm/include/asm/arch-tegra20/pinmux.h | 238 + .../arch/arm/include/asm/arch-tegra20/powergate.h | 6 + .../u-boot/arch/arm/include/asm/arch-tegra20/pwm.h | 13 + .../arm/include/asm/arch-tegra20/sdram_param.h | 131 + .../arch/arm/include/asm/arch-tegra20/tegra.h | 21 + .../arch/arm/include/asm/arch-tegra210/ahb.h | 90 + .../arm/include/asm/arch-tegra210/clock-tables.h | 567 + .../arch/arm/include/asm/arch-tegra210/clock.h | 26 + .../arch/arm/include/asm/arch-tegra210/flow.h | 44 + .../arch/arm/include/asm/arch-tegra210/funcmux.h | 22 + .../arm/include/asm/arch-tegra210/gp_padctrl.h | 73 + .../arch/arm/include/asm/arch-tegra210/gpio.h | 43 + .../u-boot/arch/arm/include/asm/arch-tegra210/mc.h | 71 + .../arch/arm/include/asm/arch-tegra210/pinmux.h | 415 + .../arch/arm/include/asm/arch-tegra210/powergate.h | 11 + .../arch/arm/include/asm/arch-tegra210/sysctr.h | 25 + .../arch/arm/include/asm/arch-tegra210/tegra.h | 31 + .../arm/include/asm/arch-tegra30/clock-tables.h | 372 + .../arch/arm/include/asm/arch-tegra30/clock.h | 19 + .../arch/arm/include/asm/arch-tegra30/flow.h | 24 + .../arch/arm/include/asm/arch-tegra30/funcmux.h | 20 + .../arch/arm/include/asm/arch-tegra30/gp_padctrl.h | 54 + .../arch/arm/include/asm/arch-tegra30/gpio.h | 42 + roms/u-boot/arch/arm/include/asm/arch-tegra30/mc.h | 37 + .../arch/arm/include/asm/arch-tegra30/pinmux.h | 404 + .../arch/arm/include/asm/arch-tegra30/powergate.h | 6 + .../arch/arm/include/asm/arch-tegra30/tegra.h | 20 + .../u-boot/arch/arm/include/asm/arch-vf610/clock.h | 29 + .../arch/arm/include/asm/arch-vf610/crm_regs.h | 275 + .../arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 83 + roms/u-boot/arch/arm/include/asm/arch-vf610/gpio.h | 28 + .../arch/arm/include/asm/arch-vf610/imx-regs.h | 480 + .../arch/arm/include/asm/arch-vf610/iomux-vf610.h | 255 + roms/u-boot/arch/arm/include/asm/armv7.h | 161 + roms/u-boot/arch/arm/include/asm/armv7_mpu.h | 134 + roms/u-boot/arch/arm/include/asm/armv7m.h | 68 + roms/u-boot/arch/arm/include/asm/armv8/cpu.h | 26 + roms/u-boot/arch/arm/include/asm/armv8/mmu.h | 140 + .../arch/arm/include/asm/armv8/sec_firmware.h | 35 + roms/u-boot/arch/arm/include/asm/assembler.h | 84 + roms/u-boot/arch/arm/include/asm/atomic.h | 32 + roms/u-boot/arch/arm/include/asm/barriers.h | 50 + roms/u-boot/arch/arm/include/asm/bitops.h | 185 + .../arm/include/asm/boot0-linux-kernel-header.h | 48 + roms/u-boot/arch/arm/include/asm/bootm.h | 63 + roms/u-boot/arch/arm/include/asm/byteorder.h | 32 + roms/u-boot/arch/arm/include/asm/cache.h | 62 + roms/u-boot/arch/arm/include/asm/config.h | 19 + roms/u-boot/arch/arm/include/asm/davinci_rtc.h | 51 + roms/u-boot/arch/arm/include/asm/dma-mapping.h | 28 + roms/u-boot/arch/arm/include/asm/ehci-omap.h | 139 + roms/u-boot/arch/arm/include/asm/emif.h | 1303 +++ roms/u-boot/arch/arm/include/asm/fsl_secure_boot.h | 135 + roms/u-boot/arch/arm/include/asm/gic-v3.h | 138 + roms/u-boot/arch/arm/include/asm/gic.h | 110 + roms/u-boot/arch/arm/include/asm/global_data.h | 136 + roms/u-boot/arch/arm/include/asm/gpio.h | 10 + roms/u-boot/arch/arm/include/asm/handoff.h | 21 + roms/u-boot/arch/arm/include/asm/hardware.h | 18 + roms/u-boot/arch/arm/include/asm/io.h | 498 + .../arch/arm/include/asm/iproc-common/armpll.h | 13 + .../arch/arm/include/asm/iproc-common/configs.h | 17 + .../arm/include/asm/iproc-common/iproc_sdhci.h | 12 + .../arch/arm/include/asm/iproc-common/sysmap.h | 46 + .../arch/arm/include/asm/iproc-common/timer.h | 36 + roms/u-boot/arch/arm/include/asm/kona-common/clk.h | 29 + .../arch/arm/include/asm/kona-common/kona_sdhci.h | 11 + roms/u-boot/arch/arm/include/asm/linkage.h | 7 + .../arch/arm/include/asm/mach-imx/boot_mode.h | 53 + roms/u-boot/arch/arm/include/asm/mach-imx/dma.h | 162 + roms/u-boot/arch/arm/include/asm/mach-imx/gpio.h | 22 + roms/u-boot/arch/arm/include/asm/mach-imx/hab.h | 239 + .../arch/arm/include/asm/mach-imx/imx-nandbcb.h | 125 + .../arch/arm/include/asm/mach-imx/imximage.cfg | 23 + .../arch/arm/include/asm/mach-imx/iomux-v3.h | 301 + .../arch/arm/include/asm/mach-imx/module_fuse.h | 127 + .../arch/arm/include/asm/mach-imx/mx5_video.h | 17 + .../u-boot/arch/arm/include/asm/mach-imx/mxc_i2c.h | 105 + .../arch/arm/include/asm/mach-imx/rdc-sema.h | 99 + .../arch/arm/include/asm/mach-imx/regs-apbh.h | 587 ++ .../arch/arm/include/asm/mach-imx/regs-bch.h | 234 + .../arch/arm/include/asm/mach-imx/regs-common.h | 70 + .../arch/arm/include/asm/mach-imx/regs-gpmi.h | 213 + .../arch/arm/include/asm/mach-imx/regs-lcdif.h | 240 + .../arch/arm/include/asm/mach-imx/regs-usbphy.h | 25 + roms/u-boot/arch/arm/include/asm/mach-imx/sata.h | 15 + roms/u-boot/arch/arm/include/asm/mach-imx/spi.h | 16 + .../arch/arm/include/asm/mach-imx/sys_proto.h | 228 + .../arch/arm/include/asm/mach-imx/syscounter.h | 28 + roms/u-boot/arch/arm/include/asm/mach-imx/video.h | 30 + roms/u-boot/arch/arm/include/asm/mach-types.h | 5054 +++++++++ roms/u-boot/arch/arm/include/asm/macro.h | 337 + roms/u-boot/arch/arm/include/asm/memory.h | 136 + roms/u-boot/arch/arm/include/asm/mmu.h | 8 + roms/u-boot/arch/arm/include/asm/omap_common.h | 838 ++ roms/u-boot/arch/arm/include/asm/omap_gpio.h | 51 + roms/u-boot/arch/arm/include/asm/omap_i2c.h | 22 + roms/u-boot/arch/arm/include/asm/omap_mmc.h | 240 + roms/u-boot/arch/arm/include/asm/omap_musb.h | 32 + roms/u-boot/arch/arm/include/asm/omap_sec_common.h | 63 + roms/u-boot/arch/arm/include/asm/opcodes-sec.h | 16 + roms/u-boot/arch/arm/include/asm/opcodes-virt.h | 26 + roms/u-boot/arch/arm/include/asm/opcodes.h | 228 + roms/u-boot/arch/arm/include/asm/pl310.h | 89 + roms/u-boot/arch/arm/include/asm/posix_types.h | 87 + .../u-boot/arch/arm/include/asm/proc-armv/domain.h | 50 + .../arch/arm/include/asm/proc-armv/processor.h | 74 + .../u-boot/arch/arm/include/asm/proc-armv/ptrace.h | 131 + .../u-boot/arch/arm/include/asm/proc-armv/system.h | 224 + roms/u-boot/arch/arm/include/asm/processor.h | 134 + roms/u-boot/arch/arm/include/asm/psci.h | 121 + roms/u-boot/arch/arm/include/asm/ptrace.h | 33 + roms/u-boot/arch/arm/include/asm/sections.h | 11 + roms/u-boot/arch/arm/include/asm/secure.h | 61 + roms/u-boot/arch/arm/include/asm/setjmp.h | 27 + roms/u-boot/arch/arm/include/asm/setup.h | 274 + roms/u-boot/arch/arm/include/asm/spin_table.h | 12 + roms/u-boot/arch/arm/include/asm/spl.h | 44 + roms/u-boot/arch/arm/include/asm/string.h | 53 + roms/u-boot/arch/arm/include/asm/system.h | 634 ++ .../arch/arm/include/asm/ti-common/davinci_nand.h | 98 + .../arch/arm/include/asm/ti-common/keystone_nav.h | 190 + .../arch/arm/include/asm/ti-common/keystone_net.h | 235 + .../arm/include/asm/ti-common/keystone_serdes.h | 54 + .../arch/arm/include/asm/ti-common/omap_wdt.h | 68 + .../arch/arm/include/asm/ti-common/sys_proto.h | 73 + .../arch/arm/include/asm/ti-common/ti-aemif.h | 38 + .../arch/arm/include/asm/ti-common/ti-edma3.h | 127 + roms/u-boot/arch/arm/include/asm/types.h | 45 + roms/u-boot/arch/arm/include/asm/u-boot-arm.h | 61 + roms/u-boot/arch/arm/include/asm/u-boot.h | 33 + roms/u-boot/arch/arm/include/asm/unaligned.h | 19 + roms/u-boot/arch/arm/include/asm/unified.h | 128 + roms/u-boot/arch/arm/include/asm/utils.h | 39 + roms/u-boot/arch/arm/include/asm/xen.h | 7 + roms/u-boot/arch/arm/include/asm/xen/hypercall.h | 22 + roms/u-boot/arch/arm/include/asm/xen/system.h | 88 + roms/u-boot/arch/arm/include/debug/8250.S | 51 + 712 files changed, 141668 insertions(+) create mode 100644 roms/u-boot/arch/arm/include/asm/acpi_table.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/chilisom.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/clock.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/cpu.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/ddr_defs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/emac_defs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/i2c.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/mem.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/mmc_host_def.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/mux.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am33xx.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am43xx.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti814x.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti816x.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/omap.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/spl.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-am33xx/sys_proto.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-armada100/armada100.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-armada100/config.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-armada100/cpu.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-armada100/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-armada100/mfp.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-armada100/spi.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-armada100/utmi-armada100.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-armada8k/cache_llc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-armada8k/soc-info.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-armv7/generictimer.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-armv7/globaltimer.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-armv7/sysctrl.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-armv7/systimer.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-armv7/wdt.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-aspeed/boot0.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-aspeed/pinctrl.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-aspeed/platform.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-aspeed/scu_ast2500.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-aspeed/scu_ast2600.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-aspeed/sdram_ast2500.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-aspeed/timer.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-aspeed/wdt.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-aspeed/wdt_ast2600.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-bcm235xx/boot0.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-bcm235xx/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-bcm235xx/sysmap.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-bcm281xx/boot0.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-bcm281xx/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-bcm281xx/sysmap.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-bcmcygnus/configs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-bcmns3/bl33_info.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-bcmnsp/configs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-ep93xx/ep93xx.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/clock.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/config.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/cpu.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/fdt.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/mmu.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/mp.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/ppa.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/soc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/speed.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/svr.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-hi3660/hi3660.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-hi6220/dwmmc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-hi6220/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-hi6220/hi6220.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-hi6220/periph.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-hi6220/pinmux.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx/cpu.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8/boot0.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8/clock.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8/image.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8/imx-regs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8/imx8-pins.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8/iomux.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8/power-domain.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8/sci/rpc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8/sci/sci.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8/sci/types.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8/snvs_security_sc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8/sys_proto.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8m/clock.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h create 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create mode 100644 roms/u-boot/arch/arm/include/asm/arch-lpc32xx/timer.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-lpc32xx/uart.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-lpc32xx/wdt.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-ls102xa/clock.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-ls102xa/config.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-ls102xa/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-ls102xa/imx-regs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-ls102xa/ns_access.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-ls102xa/soc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-ls102xa/spl.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-ls102xa/svr.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mediatek/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mediatek/misc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mediatek/reset.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/axg.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/boot.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/clock-axg.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/clock-g12a.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/clock-gx.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/eth.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/g12a.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/gx.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/i2c.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/mem.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/meson-vpu.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/sm.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/usb-gx.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-meson/usb.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mvebu/spi.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx25/clock.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx25/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx25/imx-regs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx25/iomux-mx25.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx25/macro.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx27/clock.h create mode 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create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx35/mmc_host_def.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx35/sys_proto.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx5/clock.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx5/crm_regs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx5/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx5/imx-regs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx51.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx53.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx5/sys_proto.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/clock.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/crm_regs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/imx-rdc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/imx-regs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/iomux.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/litesom.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/mx6-ddr.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/mx6-pins.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/mx6_plugin.S create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl_pins.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q-ddr.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q_pins.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sl_pins.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sll_pins.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sx_pins.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/mx6ul_pins.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/mx6ull_pins.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/mxc_hdmi.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/opos6ul.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx6/sys_proto.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7/clock.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7/clock_slice.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7/crm_regs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7/imx-rdc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7/imx-regs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7/mx7-ddr.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7/mx7-pins.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7/mx7_plugin.S create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7/mx7d_pins.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7/mx7d_rdc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7/sys_proto.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7ulp/clock.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7ulp/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7ulp/imx-regs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7ulp/iomux.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7ulp/pcc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7ulp/scg.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mx7ulp/sys_proto.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/clock.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/imx-regs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx23.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx28.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/iomux.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/regs-base.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/regs-digctl.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/regs-i2c.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/regs-lradc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ocotp.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/regs-pinctrl.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx23.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx28.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/regs-rtc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ssp.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/regs-timrot.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/regs-uartapp.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usb.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usbphy.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-mxs/sys_proto.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx/board.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx/clock.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx/csrs/csrs-mio_emm.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx/csrs/csrs-xcv.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx/smc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx/soc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx2/board.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx2/clock.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-cgx.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-lmt.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-mio_emm.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-nix.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-npa.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-npc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-rvu.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx2/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx2/smc-id.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx2/smc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-octeontx2/soc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap3/am35x_def.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap3/clock.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap3/clocks_omap3.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap3/cpu.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap3/dma.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap3/dss.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap3/ehci.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap3/emac_defs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap3/emif4.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap3/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap3/i2c.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap3/mem.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap3/mmc_host_def.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap3/musb.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap3/mux.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap3/omap.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap3/omap3-regs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap3/spl.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap3/sys_proto.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap4/clock.h create mode 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create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap5/ehci.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap5/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap5/hardware.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap5/i2c.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap5/mem.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap5/mmc_host_def.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap5/mux_dra7xx.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap5/mux_omap5.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap5/omap.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap5/sata.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap5/spl.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-omap5/sys_proto.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-orion5x/spl.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-owl/regs_s700.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-owl/regs_s900.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-px30/boot0.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-px30/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-pxa/bitfield.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-pxa/config.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-pxa/hardware.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-pxa/pxa-regs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-pxa/pxa.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-pxa/regs-mmc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-pxa/regs-uart.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-pxa/regs-usb.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk3036/boot0.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk3036/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk3128/boot0.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk3128/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk3188/boot0.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk3188/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk322x/boot0.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk322x/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk3288/boot0.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk3288/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk3308/boot0.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk3308/cru_rk3308.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk3308/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk3308/grf_rk3308.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk3328/boot0.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk3328/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk3368/boot0.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk3368/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk3399/boot0.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rk3399/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/boot0.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/boot_mode.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/bootrom.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/clock.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/cpu_rk3288.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/cru.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_px30.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3036.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3128.h create mode 100644 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create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_px30.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3036.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3128.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3188.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk322x.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3288.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3328.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3368.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3399.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rv1108.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/hardware.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rockchip/i2c.h create mode 100644 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roms/u-boot/arch/arm/include/asm/arch-rv1108/boot0.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-rv1108/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-sa1100/bitfield.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-spear/clk.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-spear/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-spear/hardware.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-spear/spr_defs.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-spear/spr_emi.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-spear/spr_gpt.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-spear/spr_misc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-spear/spr_ssp.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-spear/spr_syscntl.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-stih410/sdhci.h create mode 100644 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roms/u-boot/arch/arm/include/asm/arch-sunxi/mmc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-sunxi/p2wi.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-sunxi/pmic_bus.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-sunxi/prcm.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-sunxi/prcm_sun6i.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-sunxi/pwm.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-sunxi/rsb.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-sunxi/spl.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-sunxi/sys_proto.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-sunxi/timer.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-sunxi/tve.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-sunxi/tzpc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-sunxi/watchdog.h create mode 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create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra/usb.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra/warmboot.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra/xusb-padctl.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra114/clock-tables.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra114/clock.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra114/flow.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra114/funcmux.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra114/gp_padctrl.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra114/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra114/mc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra114/pinmux.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra114/powergate.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra114/sysctr.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra114/tegra.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra124/ahb.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra124/clock-tables.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra124/clock.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra124/display.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra124/flow.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra124/funcmux.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra124/gp_padctrl.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra124/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra124/mc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra124/pinmux.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra124/powergate.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra124/pwm.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra124/sysctr.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra124/tegra.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra186/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra186/tegra.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra20/clock-tables.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra20/clock.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra20/display.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra20/emc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra20/flow.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra20/funcmux.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra20/gp_padctrl.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra20/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra20/mc.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra20/pinmux.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra20/powergate.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra20/pwm.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra20/sdram_param.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra210/ahb.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra210/clock-tables.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra210/clock.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra210/flow.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra210/funcmux.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra210/gp_padctrl.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra210/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/arch-tegra210/mc.h create mode 100644 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roms/u-boot/arch/arm/include/asm/atomic.h create mode 100644 roms/u-boot/arch/arm/include/asm/barriers.h create mode 100644 roms/u-boot/arch/arm/include/asm/bitops.h create mode 100644 roms/u-boot/arch/arm/include/asm/boot0-linux-kernel-header.h create mode 100644 roms/u-boot/arch/arm/include/asm/bootm.h create mode 100644 roms/u-boot/arch/arm/include/asm/byteorder.h create mode 100644 roms/u-boot/arch/arm/include/asm/cache.h create mode 100644 roms/u-boot/arch/arm/include/asm/config.h create mode 100644 roms/u-boot/arch/arm/include/asm/davinci_rtc.h create mode 100644 roms/u-boot/arch/arm/include/asm/dma-mapping.h create mode 100644 roms/u-boot/arch/arm/include/asm/ehci-omap.h create mode 100644 roms/u-boot/arch/arm/include/asm/emif.h create mode 100644 roms/u-boot/arch/arm/include/asm/fsl_secure_boot.h create mode 100644 roms/u-boot/arch/arm/include/asm/gic-v3.h create mode 100644 roms/u-boot/arch/arm/include/asm/gic.h create mode 100644 roms/u-boot/arch/arm/include/asm/global_data.h create mode 100644 roms/u-boot/arch/arm/include/asm/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/handoff.h create mode 100644 roms/u-boot/arch/arm/include/asm/hardware.h create mode 100644 roms/u-boot/arch/arm/include/asm/io.h create mode 100644 roms/u-boot/arch/arm/include/asm/iproc-common/armpll.h create mode 100644 roms/u-boot/arch/arm/include/asm/iproc-common/configs.h create mode 100644 roms/u-boot/arch/arm/include/asm/iproc-common/iproc_sdhci.h create mode 100644 roms/u-boot/arch/arm/include/asm/iproc-common/sysmap.h create mode 100644 roms/u-boot/arch/arm/include/asm/iproc-common/timer.h create mode 100644 roms/u-boot/arch/arm/include/asm/kona-common/clk.h create mode 100644 roms/u-boot/arch/arm/include/asm/kona-common/kona_sdhci.h create mode 100644 roms/u-boot/arch/arm/include/asm/linkage.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/boot_mode.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/dma.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/hab.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/imx-nandbcb.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/imximage.cfg create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/iomux-v3.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/module_fuse.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/mx5_video.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/mxc_i2c.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/rdc-sema.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/regs-apbh.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/regs-bch.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/regs-common.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/regs-gpmi.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/regs-lcdif.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/regs-usbphy.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/sata.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/spi.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/sys_proto.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/syscounter.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-imx/video.h create mode 100644 roms/u-boot/arch/arm/include/asm/mach-types.h create mode 100644 roms/u-boot/arch/arm/include/asm/macro.h create mode 100644 roms/u-boot/arch/arm/include/asm/memory.h create mode 100644 roms/u-boot/arch/arm/include/asm/mmu.h create mode 100644 roms/u-boot/arch/arm/include/asm/omap_common.h create mode 100644 roms/u-boot/arch/arm/include/asm/omap_gpio.h create mode 100644 roms/u-boot/arch/arm/include/asm/omap_i2c.h create mode 100644 roms/u-boot/arch/arm/include/asm/omap_mmc.h create mode 100644 roms/u-boot/arch/arm/include/asm/omap_musb.h create mode 100644 roms/u-boot/arch/arm/include/asm/omap_sec_common.h create mode 100644 roms/u-boot/arch/arm/include/asm/opcodes-sec.h create mode 100644 roms/u-boot/arch/arm/include/asm/opcodes-virt.h create mode 100644 roms/u-boot/arch/arm/include/asm/opcodes.h create mode 100644 roms/u-boot/arch/arm/include/asm/pl310.h create mode 100644 roms/u-boot/arch/arm/include/asm/posix_types.h create mode 100644 roms/u-boot/arch/arm/include/asm/proc-armv/domain.h create mode 100644 roms/u-boot/arch/arm/include/asm/proc-armv/processor.h create mode 100644 roms/u-boot/arch/arm/include/asm/proc-armv/ptrace.h create mode 100644 roms/u-boot/arch/arm/include/asm/proc-armv/system.h create mode 100644 roms/u-boot/arch/arm/include/asm/processor.h create mode 100644 roms/u-boot/arch/arm/include/asm/psci.h create mode 100644 roms/u-boot/arch/arm/include/asm/ptrace.h create mode 100644 roms/u-boot/arch/arm/include/asm/sections.h create mode 100644 roms/u-boot/arch/arm/include/asm/secure.h create mode 100644 roms/u-boot/arch/arm/include/asm/setjmp.h create mode 100644 roms/u-boot/arch/arm/include/asm/setup.h create mode 100644 roms/u-boot/arch/arm/include/asm/spin_table.h create mode 100644 roms/u-boot/arch/arm/include/asm/spl.h create mode 100644 roms/u-boot/arch/arm/include/asm/string.h create mode 100644 roms/u-boot/arch/arm/include/asm/system.h create mode 100644 roms/u-boot/arch/arm/include/asm/ti-common/davinci_nand.h create mode 100644 roms/u-boot/arch/arm/include/asm/ti-common/keystone_nav.h create mode 100644 roms/u-boot/arch/arm/include/asm/ti-common/keystone_net.h create mode 100644 roms/u-boot/arch/arm/include/asm/ti-common/keystone_serdes.h create mode 100644 roms/u-boot/arch/arm/include/asm/ti-common/omap_wdt.h create mode 100644 roms/u-boot/arch/arm/include/asm/ti-common/sys_proto.h create mode 100644 roms/u-boot/arch/arm/include/asm/ti-common/ti-aemif.h create mode 100644 roms/u-boot/arch/arm/include/asm/ti-common/ti-edma3.h create mode 100644 roms/u-boot/arch/arm/include/asm/types.h create mode 100644 roms/u-boot/arch/arm/include/asm/u-boot-arm.h create mode 100644 roms/u-boot/arch/arm/include/asm/u-boot.h create mode 100644 roms/u-boot/arch/arm/include/asm/unaligned.h create mode 100644 roms/u-boot/arch/arm/include/asm/unified.h create mode 100644 roms/u-boot/arch/arm/include/asm/utils.h create mode 100644 roms/u-boot/arch/arm/include/asm/xen.h create mode 100644 roms/u-boot/arch/arm/include/asm/xen/hypercall.h create mode 100644 roms/u-boot/arch/arm/include/asm/xen/system.h create mode 100644 roms/u-boot/arch/arm/include/debug/8250.S (limited to 'roms/u-boot/arch/arm/include') diff --git a/roms/u-boot/arch/arm/include/asm/acpi_table.h b/roms/u-boot/arch/arm/include/asm/acpi_table.h new file mode 100644 index 000000000..e69de29bb diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/chilisom.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/chilisom.h new file mode 100644 index 000000000..493be6431 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/chilisom.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Grinn + */ + +#ifndef __ARCH_ARM_MACH_CHILISOM_SOM_H__ +#define __ARCH_ARM_MACH_CHILISOM_SOM_H__ + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +void chilisom_enable_pin_mux(void); +void chilisom_spl_board_init(void); +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h new file mode 100644 index 000000000..7bcafba6f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * clk-synthesizer.h + * + * Clock synthesizer header + * + * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef __CLK_SYNTHESIZER_H +#define __CLK_SYNTHESIZER_H + +#define CLK_SYNTHESIZER_ID_REG 0x0 +#define CLK_SYNTHESIZER_XCSEL 0x05 +#define CLK_SYNTHESIZER_MUX_REG 0x14 +#define CLK_SYNTHESIZER_PDIV2_REG 0x16 +#define CLK_SYNTHESIZER_PDIV3_REG 0x17 + +#define CLK_SYNTHESIZER_BYTE_MODE 0x80 + +/** + * struct clk_synth: This structure holds data neeed for configuring + * for clock synthesizer. + * @id: The id of synthesizer + * @capacitor: value of the capacitor attached + * @mux: mux settings. + * @pdiv2: Div to be applied to second output + * @pdiv3: Div to be applied to third output + */ +struct clk_synth { + u32 id; + u32 capacitor; + u32 mux; + u32 pdiv2; + u32 pdiv3; +}; + +int setup_clock_synthesizer(struct clk_synth *data); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/clock.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/clock.h new file mode 100644 index 000000000..5d775902b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/clock.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * clock.h + * + * clock header + * + * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef _CLOCKS_H_ +#define _CLOCKS_H_ + +#include +#include + +#if defined(CONFIG_TI816X) || defined(CONFIG_TI814X) +#include +#endif + +#define LDELAY 1000000 + +/*CM___CLKCTRL */ +#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 +#define CD_CLKCTRL_CLKTRCTRL_MASK 3 + +#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 +#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 +#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 + +/* CM___CLKCTRL */ +#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 +#define MODULE_CLKCTRL_MODULEMODE_MASK 3 +#define MODULE_CLKCTRL_IDLEST_SHIFT 16 +#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) + +#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 +#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 + +#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 +#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 +#define MODULE_CLKCTRL_IDLEST_IDLE 2 +#define MODULE_CLKCTRL_IDLEST_DISABLED 3 + +/* CM_CLKMODE_DPLL */ +#define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12 +#define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12) +#define CM_CLKMODE_DPLL_SSC_ACK_MASK (1 << 13) +#define CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) +#define CM_CLKMODE_DPLL_SSC_TYPE_MASK (1 << 15) +#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 +#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) +#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 +#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) +#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 +#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) +#define CM_CLKMODE_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) + +#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 + +#define DPLL_EN_STOP 1 +#define DPLL_EN_MN_BYPASS 4 +#define DPLL_EN_LOW_POWER_BYPASS 5 +#define DPLL_EN_FAST_RELOCK_BYPASS 6 +#define DPLL_EN_LOCK 7 + +/* CM_IDLEST_DPLL fields */ +#define ST_DPLL_CLK_MASK 1 + +/* CM_CLKSEL_DPLL */ +#define CM_CLKSEL_DPLL_M_SHIFT 8 +#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) +#define CM_CLKSEL_DPLL_N_SHIFT 0 +#define CM_CLKSEL_DPLL_N_MASK 0x7F + +struct dpll_params { + u32 m; + u32 n; + s8 m2; + s8 m3; + s8 m4; + s8 m5; + s8 m6; +}; + +struct dpll_regs { + u32 cm_clkmode_dpll; + u32 cm_idlest_dpll; + u32 cm_autoidle_dpll; + u32 cm_clksel_dpll; + u32 cm_div_m2_dpll; + u32 cm_div_m3_dpll; + u32 cm_div_m4_dpll; + u32 cm_div_m5_dpll; + u32 cm_div_m6_dpll; +}; + +extern const struct dpll_regs dpll_mpu_regs; +extern const struct dpll_regs dpll_core_regs; +extern const struct dpll_regs dpll_per_regs; +extern const struct dpll_regs dpll_ddr_regs; +extern const struct dpll_regs dpll_disp_regs; +extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS]; +extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ]; +extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ]; +extern const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ]; +extern const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ]; +extern const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ]; + +extern struct cm_wkuppll *const cmwkup; + +const struct dpll_params *get_dpll_mpu_params(void); +const struct dpll_params *get_dpll_core_params(void); +const struct dpll_params *get_dpll_per_params(void); +const struct dpll_params *get_dpll_ddr_params(void); +void scale_vcores(void); +void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); +void prcm_init(void); +void enable_basic_clocks(void); + +void rtc_only_update_board_type(u32 btype); +u32 rtc_only_get_board_type(void); +void rtc_only_prcm_init(void); +void rtc_only_enable_basic_clocks(void); + +void do_enable_clocks(u32 *const *, u32 *const *, u8); +void do_disable_clocks(u32 *const *, u32 *const *, u8); + +void set_mpu_spreadspectrum(int permille); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h new file mode 100644 index 000000000..f0699229a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h @@ -0,0 +1,142 @@ +/* + * ti81xx.h + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#ifndef _CLOCK_TI81XX_H_ +#define _CLOCK_TI81XX_H_ + +#define PRCM_MOD_EN 0x2 + +#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) +#define CM_ALWON_BASE (PRCM_BASE + 0x1400) + +struct cm_def { + unsigned int resv0[2]; + unsigned int l3fastclkstctrl; + unsigned int resv1[1]; + unsigned int pciclkstctrl; + unsigned int resv2[1]; + unsigned int ducaticlkstctrl; + unsigned int resv3[1]; + unsigned int emif0clkctrl; + unsigned int emif1clkctrl; + unsigned int dmmclkctrl; + unsigned int fwclkctrl; + unsigned int resv4[10]; + unsigned int usbclkctrl; + unsigned int resv5[1]; + unsigned int sataclkctrl; + unsigned int resv6[4]; + unsigned int ducaticlkctrl; + unsigned int pciclkctrl; +}; + +struct cm_alwon { + unsigned int l3slowclkstctrl; + unsigned int ethclkstctrl; + unsigned int l3medclkstctrl; + unsigned int mmu_clkstctrl; + unsigned int mmucfg_clkstctrl; + unsigned int ocmc0clkstctrl; +#if defined(CONFIG_TI814X) + unsigned int vcpclkstctrl; +#elif defined(CONFIG_TI816X) + unsigned int ocmc1clkstctrl; +#endif + unsigned int mpuclkstctrl; + unsigned int sysclk4clkstctrl; + unsigned int sysclk5clkstctrl; + unsigned int sysclk6clkstctrl; + unsigned int rtcclkstctrl; + unsigned int l3fastclkstctrl; + unsigned int resv0[67]; + unsigned int mcasp0clkctrl; + unsigned int mcasp1clkctrl; + unsigned int mcasp2clkctrl; + unsigned int mcbspclkctrl; + unsigned int uart0clkctrl; + unsigned int uart1clkctrl; + unsigned int uart2clkctrl; + unsigned int gpio0clkctrl; + unsigned int gpio1clkctrl; + unsigned int i2c0clkctrl; + unsigned int i2c1clkctrl; +#if defined(CONFIG_TI814X) + unsigned int mcasp345clkctrl; + unsigned int atlclkctrl; + unsigned int mlbclkctrl; + unsigned int pataclkctrl; + unsigned int resv1[1]; + unsigned int uart3clkctrl; + unsigned int uart4clkctrl; + unsigned int uart5clkctrl; +#elif defined(CONFIG_TI816X) + unsigned int resv1[1]; + unsigned int timer1clkctrl; + unsigned int timer2clkctrl; + unsigned int timer3clkctrl; + unsigned int timer4clkctrl; + unsigned int timer5clkctrl; + unsigned int timer6clkctrl; + unsigned int timer7clkctrl; +#endif + unsigned int wdtimerclkctrl; + unsigned int spiclkctrl; + unsigned int mailboxclkctrl; + unsigned int spinboxclkctrl; + unsigned int mmudataclkctrl; + unsigned int resv2[2]; + unsigned int mmucfgclkctrl; +#if defined(CONFIG_TI814X) + unsigned int resv3[2]; +#elif defined(CONFIG_TI816X) + unsigned int resv3[1]; + unsigned int sdioclkctrl; +#endif + unsigned int ocmc0clkctrl; +#if defined(CONFIG_TI814X) + unsigned int vcpclkctrl; +#elif defined(CONFIG_TI816X) + unsigned int ocmc1clkctrl; +#endif + unsigned int resv4[2]; + unsigned int controlclkctrl; + unsigned int resv5[2]; + unsigned int gpmcclkctrl; + unsigned int ethernet0clkctrl; + unsigned int ethernet1clkctrl; + unsigned int mpuclkctrl; +#if defined(CONFIG_TI814X) + unsigned int debugssclkctrl; +#elif defined(CONFIG_TI816X) + unsigned int resv6[1]; +#endif + unsigned int l3clkctrl; + unsigned int l4hsclkctrl; + unsigned int l4lsclkctrl; + unsigned int rtcclkctrl; + unsigned int tpccclkctrl; + unsigned int tptc0clkctrl; + unsigned int tptc1clkctrl; + unsigned int tptc2clkctrl; + unsigned int tptc3clkctrl; +#if defined(CONFIG_TI814X) + unsigned int resv6[4]; + unsigned int dcan01clkctrl; + unsigned int mmchs0clkctrl; + unsigned int mmchs1clkctrl; + unsigned int mmchs2clkctrl; + unsigned int custefuseclkctrl; +#elif defined(CONFIG_TI816X) + unsigned int sr0clkctrl; + unsigned int sr1clkctrl; +#endif +}; + +#endif /* _CLOCK_TI81XX_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h new file mode 100644 index 000000000..e5ad50754 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * clocks_am33xx.h + * + * AM33xx clock define + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef _CLOCKS_AM33XX_H_ +#define _CLOCKS_AM33XX_H_ + +/* MAIN PLL Fdll supported frequencies */ +#define MPUPLL_M_1000 1000 +#define MPUPLL_M_800 800 +#define MPUPLL_M_720 720 +#define MPUPLL_M_600 600 +#define MPUPLL_M_500 500 +#define MPUPLL_M_300 300 + +#define UART_RESET (0x1 << 1) +#define UART_CLK_RUNNING_MASK 0x1 +#define UART_SMART_IDLE_EN (0x1 << 0x3) + +#define CM_DLL_CTRL_NO_OVERRIDE 0x0 +#define CM_DLL_READYST 0x4 + +#define NUM_OPPS 6 + +extern void enable_dmm_clocks(void); +extern void enable_emif_clocks(void); +extern const struct dpll_params dpll_core_opp100; +extern struct dpll_params dpll_mpu_opp100; + +#endif /* endif _CLOCKS_AM33XX_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/cpu.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/cpu.h new file mode 100644 index 000000000..79081de70 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/cpu.h @@ -0,0 +1,612 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * cpu.h + * + * AM33xx specific header file + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef _AM33XX_CPU_H +#define _AM33XX_CPU_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include +#include +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +#include + +#define CL_BIT(x) (0 << x) + +/* Timer register bits */ +#define TCLR_ST BIT(0) /* Start=1 Stop=0 */ +#define TCLR_AR BIT(1) /* Auto reload */ +#define TCLR_PRE BIT(5) /* Pre-scaler enable */ +#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */ +#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */ +#define TCLR_CE BIT(6) /* compare mode enable */ +#define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */ +#define TCLR_TCM BIT(8) /* edge detection of input pin*/ +#define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */ +#define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/ +#define TCLR_CAPTMODE BIT(13) /* capture mode */ +#define TCLR_GPOCFG BIT(14) /* 0=output,1=input */ + +#define TCFG_RESET BIT(0) /* software reset */ +#define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */ +#define TCFG_IDLEMOD_SHIFT (2) /* power management */ + +/* cpu-id for AM43XX AM33XX and TI81XX family */ +#define AM437X 0xB98C +#define AM335X 0xB944 +#define TI81XX 0xB81E +#define DEVICE_ID (CTRL_BASE + 0x0600) +#define DEVICE_ID_MASK 0x1FFF +#define PACKAGE_TYPE_SHIFT 16 +#define PACKAGE_TYPE_MASK (3 << 16) + +/* Package Type */ +#define PACKAGE_TYPE_UNDEFINED 0x0 +#define PACKAGE_TYPE_ZCZ 0x1 +#define PACKAGE_TYPE_ZCE 0x2 +#define PACKAGE_TYPE_RESERVED 0x3 + +/* MPU max frequencies */ +#define AM335X_ZCZ_300 0x1FEF +#define AM335X_ZCZ_600 0x1FAF +#define AM335X_ZCZ_720 0x1F2F +#define AM335X_ZCZ_800 0x1E2F +#define AM335X_ZCZ_1000 0x1C2F +#define AM335X_ZCE_300 0x1FDF +#define AM335X_ZCE_600 0x1F9F + +/* This gives the status of the boot mode pins on the evm */ +#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ + | BIT(3) | BIT(4)) + +#define PRM_RSTCTRL_RESET 0x01 +#define PRM_RSTST_WARM_RESET_MASK 0x232 + +/* EMIF Control register bits */ +#define EMIF_CTRL_DEVOFF BIT(0) + +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +#include + +#ifndef CONFIG_AM43XX +/* Encapsulating core pll registers */ +struct cm_wkuppll { + unsigned int wkclkstctrl; /* offset 0x00 */ + unsigned int wkctrlclkctrl; /* offset 0x04 */ + unsigned int wkgpio0clkctrl; /* offset 0x08 */ + unsigned int wkl4wkclkctrl; /* offset 0x0c */ + unsigned int timer0clkctrl; /* offset 0x10 */ + unsigned int resv2[3]; + unsigned int idlestdpllmpu; /* offset 0x20 */ + unsigned int sscdeltamstepdllmpu; /* off 0x24 */ + unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */ + unsigned int clkseldpllmpu; /* offset 0x2c */ + unsigned int resv4[1]; + unsigned int idlestdpllddr; /* offset 0x34 */ + unsigned int resv5[2]; + unsigned int clkseldpllddr; /* offset 0x40 */ + unsigned int resv6[4]; + unsigned int clkseldplldisp; /* offset 0x54 */ + unsigned int resv7[1]; + unsigned int idlestdpllcore; /* offset 0x5c */ + unsigned int resv8[2]; + unsigned int clkseldpllcore; /* offset 0x68 */ + unsigned int resv9[1]; + unsigned int idlestdpllper; /* offset 0x70 */ + unsigned int resv10[2]; + unsigned int clkdcoldodpllper; /* offset 0x7c */ + unsigned int divm4dpllcore; /* offset 0x80 */ + unsigned int divm5dpllcore; /* offset 0x84 */ + unsigned int clkmoddpllmpu; /* offset 0x88 */ + unsigned int clkmoddpllper; /* offset 0x8c */ + unsigned int clkmoddpllcore; /* offset 0x90 */ + unsigned int clkmoddpllddr; /* offset 0x94 */ + unsigned int clkmoddplldisp; /* offset 0x98 */ + unsigned int clkseldpllper; /* offset 0x9c */ + unsigned int divm2dpllddr; /* offset 0xA0 */ + unsigned int divm2dplldisp; /* offset 0xA4 */ + unsigned int divm2dpllmpu; /* offset 0xA8 */ + unsigned int divm2dpllper; /* offset 0xAC */ + unsigned int resv11[1]; + unsigned int wkup_uart0ctrl; /* offset 0xB4 */ + unsigned int wkup_i2c0ctrl; /* offset 0xB8 */ + unsigned int wkup_adctscctrl; /* offset 0xBC */ + unsigned int resv12; + unsigned int timer1clkctrl; /* offset 0xC4 */ + unsigned int resv13[4]; + unsigned int divm6dpllcore; /* offset 0xD8 */ +}; + +/** + * Encapsulating peripheral functional clocks + * pll registers + */ +struct cm_perpll { + unsigned int l4lsclkstctrl; /* offset 0x00 */ + unsigned int l3sclkstctrl; /* offset 0x04 */ + unsigned int l4fwclkstctrl; /* offset 0x08 */ + unsigned int l3clkstctrl; /* offset 0x0c */ + unsigned int resv1; + unsigned int cpgmac0clkctrl; /* offset 0x14 */ + unsigned int lcdclkctrl; /* offset 0x18 */ + unsigned int usb0clkctrl; /* offset 0x1C */ + unsigned int resv2; + unsigned int tptc0clkctrl; /* offset 0x24 */ + unsigned int emifclkctrl; /* offset 0x28 */ + unsigned int ocmcramclkctrl; /* offset 0x2c */ + unsigned int gpmcclkctrl; /* offset 0x30 */ + unsigned int mcasp0clkctrl; /* offset 0x34 */ + unsigned int uart5clkctrl; /* offset 0x38 */ + unsigned int mmc0clkctrl; /* offset 0x3C */ + unsigned int elmclkctrl; /* offset 0x40 */ + unsigned int i2c2clkctrl; /* offset 0x44 */ + unsigned int i2c1clkctrl; /* offset 0x48 */ + unsigned int spi0clkctrl; /* offset 0x4C */ + unsigned int spi1clkctrl; /* offset 0x50 */ + unsigned int resv3[3]; + unsigned int l4lsclkctrl; /* offset 0x60 */ + unsigned int l4fwclkctrl; /* offset 0x64 */ + unsigned int mcasp1clkctrl; /* offset 0x68 */ + unsigned int uart1clkctrl; /* offset 0x6C */ + unsigned int uart2clkctrl; /* offset 0x70 */ + unsigned int uart3clkctrl; /* offset 0x74 */ + unsigned int uart4clkctrl; /* offset 0x78 */ + unsigned int timer7clkctrl; /* offset 0x7C */ + unsigned int timer2clkctrl; /* offset 0x80 */ + unsigned int timer3clkctrl; /* offset 0x84 */ + unsigned int timer4clkctrl; /* offset 0x88 */ + unsigned int resv4[8]; + unsigned int gpio1clkctrl; /* offset 0xAC */ + unsigned int gpio2clkctrl; /* offset 0xB0 */ + unsigned int gpio3clkctrl; /* offset 0xB4 */ + unsigned int resv5; + unsigned int tpccclkctrl; /* offset 0xBC */ + unsigned int dcan0clkctrl; /* offset 0xC0 */ + unsigned int dcan1clkctrl; /* offset 0xC4 */ + unsigned int resv6; + unsigned int epwmss1clkctrl; /* offset 0xCC */ + unsigned int emiffwclkctrl; /* offset 0xD0 */ + unsigned int epwmss0clkctrl; /* offset 0xD4 */ + unsigned int epwmss2clkctrl; /* offset 0xD8 */ + unsigned int l3instrclkctrl; /* offset 0xDC */ + unsigned int l3clkctrl; /* Offset 0xE0 */ + unsigned int resv8[2]; + unsigned int timer5clkctrl; /* offset 0xEC */ + unsigned int timer6clkctrl; /* offset 0xF0 */ + unsigned int mmc1clkctrl; /* offset 0xF4 */ + unsigned int mmc2clkctrl; /* offset 0xF8 */ + unsigned int resv9[8]; + unsigned int l4hsclkstctrl; /* offset 0x11C */ + unsigned int l4hsclkctrl; /* offset 0x120 */ + unsigned int resv10[8]; + unsigned int cpswclkstctrl; /* offset 0x144 */ + unsigned int lcdcclkstctrl; /* offset 0x148 */ +}; + +/* Encapsulating Display pll registers */ +struct cm_dpll { + unsigned int resv1; + unsigned int clktimer7clk; /* offset 0x04 */ + unsigned int clktimer2clk; /* offset 0x08 */ + unsigned int clktimer3clk; /* offset 0x0C */ + unsigned int clktimer4clk; /* offset 0x10 */ + unsigned int resv2; + unsigned int clktimer5clk; /* offset 0x18 */ + unsigned int clktimer6clk; /* offset 0x1C */ + unsigned int resv3[2]; + unsigned int clktimer1clk; /* offset 0x28 */ + unsigned int resv4[2]; + unsigned int clklcdcpixelclk; /* offset 0x34 */ +}; + +struct prm_device_inst { + unsigned int prm_rstctrl; + unsigned int prm_rsttime; + unsigned int prm_rstst; +}; +#else +/* Encapsulating core pll registers */ +struct cm_wkuppll { + unsigned int resv0[136]; + unsigned int wkl4wkclkctrl; /* offset 0x220 */ + unsigned int resv1[7]; + unsigned int usbphy0clkctrl; /* offset 0x240 */ + unsigned int resv112; + unsigned int usbphy1clkctrl; /* offset 0x248 */ + unsigned int resv113[45]; + unsigned int wkclkstctrl; /* offset 0x300 */ + unsigned int resv2[15]; + unsigned int wkup_i2c0ctrl; /* offset 0x340 */ + unsigned int resv3; + unsigned int wkup_uart0ctrl; /* offset 0x348 */ + unsigned int resv4[5]; + unsigned int wkctrlclkctrl; /* offset 0x360 */ + unsigned int resv5; + unsigned int wkgpio0clkctrl; /* offset 0x368 */ + + unsigned int resv6[109]; + unsigned int clkmoddpllcore; /* offset 0x520 */ + unsigned int idlestdpllcore; /* offset 0x524 */ + unsigned int resv61; + unsigned int clkseldpllcore; /* offset 0x52C */ + unsigned int resv7[2]; + unsigned int divm4dpllcore; /* offset 0x538 */ + unsigned int divm5dpllcore; /* offset 0x53C */ + unsigned int divm6dpllcore; /* offset 0x540 */ + + unsigned int resv8[7]; + unsigned int clkmoddpllmpu; /* offset 0x560 */ + unsigned int idlestdpllmpu; /* offset 0x564 */ + unsigned int resv9; + unsigned int clkseldpllmpu; /* offset 0x56c */ + unsigned int divm2dpllmpu; /* offset 0x570 */ + + unsigned int resv10[11]; + unsigned int clkmoddpllddr; /* offset 0x5A0 */ + unsigned int idlestdpllddr; /* offset 0x5A4 */ + unsigned int resv11; + unsigned int clkseldpllddr; /* offset 0x5AC */ + unsigned int divm2dpllddr; /* offset 0x5B0 */ + + unsigned int resv12[11]; + unsigned int clkmoddpllper; /* offset 0x5E0 */ + unsigned int idlestdpllper; /* offset 0x5E4 */ + unsigned int resv13; + unsigned int clkseldpllper; /* offset 0x5EC */ + unsigned int divm2dpllper; /* offset 0x5F0 */ + unsigned int resv14[8]; + unsigned int clkdcoldodpllper; /* offset 0x614 */ + + unsigned int resv15[2]; + unsigned int clkmoddplldisp; /* offset 0x620 */ + unsigned int resv16[2]; + unsigned int clkseldplldisp; /* offset 0x62C */ + unsigned int divm2dplldisp; /* offset 0x630 */ +}; + +/* + * Encapsulating peripheral functional clocks + * pll registers + */ +struct cm_perpll { + unsigned int l3clkstctrl; /* offset 0x00 */ + unsigned int resv0[7]; + unsigned int l3clkctrl; /* Offset 0x20 */ + unsigned int resv112[7]; + unsigned int l3instrclkctrl; /* offset 0x40 */ + unsigned int resv2[3]; + unsigned int ocmcramclkctrl; /* offset 0x50 */ + unsigned int resv3[9]; + unsigned int tpccclkctrl; /* offset 0x78 */ + unsigned int resv4; + unsigned int tptc0clkctrl; /* offset 0x80 */ + + unsigned int resv5[7]; + unsigned int l4hsclkctrl; /* offset 0x0A0 */ + unsigned int resv6; + unsigned int l4fwclkctrl; /* offset 0x0A8 */ + unsigned int resv7[85]; + unsigned int l3sclkstctrl; /* offset 0x200 */ + unsigned int resv8[7]; + unsigned int gpmcclkctrl; /* offset 0x220 */ + unsigned int resv9[5]; + unsigned int mcasp0clkctrl; /* offset 0x238 */ + unsigned int resv10; + unsigned int mcasp1clkctrl; /* offset 0x240 */ + unsigned int resv11; + unsigned int mmc2clkctrl; /* offset 0x248 */ + unsigned int resv12[3]; + unsigned int qspiclkctrl; /* offset 0x258 */ + unsigned int resv121; + unsigned int usb0clkctrl; /* offset 0x260 */ + unsigned int resv122; + unsigned int usb1clkctrl; /* offset 0x268 */ + unsigned int resv13[101]; + unsigned int l4lsclkstctrl; /* offset 0x400 */ + unsigned int resv14[7]; + unsigned int l4lsclkctrl; /* offset 0x420 */ + unsigned int resv15; + unsigned int dcan0clkctrl; /* offset 0x428 */ + unsigned int resv16; + unsigned int dcan1clkctrl; /* offset 0x430 */ + unsigned int resv17[13]; + unsigned int elmclkctrl; /* offset 0x468 */ + + unsigned int resv18[3]; + unsigned int gpio1clkctrl; /* offset 0x478 */ + unsigned int resv19; + unsigned int gpio2clkctrl; /* offset 0x480 */ + unsigned int resv20; + unsigned int gpio3clkctrl; /* offset 0x488 */ + unsigned int resv41; + unsigned int gpio4clkctrl; /* offset 0x490 */ + unsigned int resv42; + unsigned int gpio5clkctrl; /* offset 0x498 */ + unsigned int resv21[3]; + + unsigned int i2c1clkctrl; /* offset 0x4A8 */ + unsigned int resv22; + unsigned int i2c2clkctrl; /* offset 0x4B0 */ + unsigned int resv23[3]; + unsigned int mmc0clkctrl; /* offset 0x4C0 */ + unsigned int resv24; + unsigned int mmc1clkctrl; /* offset 0x4C8 */ + + unsigned int resv25[13]; + unsigned int spi0clkctrl; /* offset 0x500 */ + unsigned int resv26; + unsigned int spi1clkctrl; /* offset 0x508 */ + unsigned int resv27[9]; + unsigned int timer2clkctrl; /* offset 0x530 */ + unsigned int resv28; + unsigned int timer3clkctrl; /* offset 0x538 */ + unsigned int resv29; + unsigned int timer4clkctrl; /* offset 0x540 */ + unsigned int resv30[5]; + unsigned int timer7clkctrl; /* offset 0x558 */ + + unsigned int resv31[9]; + unsigned int uart1clkctrl; /* offset 0x580 */ + unsigned int resv32; + unsigned int uart2clkctrl; /* offset 0x588 */ + unsigned int resv33; + unsigned int uart3clkctrl; /* offset 0x590 */ + unsigned int resv34; + unsigned int uart4clkctrl; /* offset 0x598 */ + unsigned int resv35; + unsigned int uart5clkctrl; /* offset 0x5A0 */ + unsigned int resv36[5]; + unsigned int usbphyocp2scp0clkctrl; /* offset 0x5B8 */ + unsigned int resv361; + unsigned int usbphyocp2scp1clkctrl; /* offset 0x5C0 */ + unsigned int resv3611[79]; + + unsigned int emifclkstctrl; /* offset 0x700 */ + unsigned int resv362[7]; + unsigned int emifclkctrl; /* offset 0x720 */ + unsigned int resv37[3]; + unsigned int emiffwclkctrl; /* offset 0x730 */ + unsigned int resv371; + unsigned int otfaemifclkctrl; /* offset 0x738 */ + unsigned int resv38[57]; + unsigned int lcdclkctrl; /* offset 0x820 */ + unsigned int resv39[183]; + unsigned int cpswclkstctrl; /* offset 0xB00 */ + unsigned int resv40[7]; + unsigned int cpgmac0clkctrl; /* offset 0xB20 */ +}; + +struct cm_device_inst { + unsigned int cm_clkout1_ctrl; + unsigned int cm_dll_ctrl; +}; + +struct prm_device_inst { + unsigned int rstctrl; + unsigned int rstst; + unsigned int rsttime; + unsigned int sram_count; + unsigned int ldo_sram_core_set; /* offset 0x10 */ + unsigned int ldo_sram_core_ctr; + unsigned int ldo_sram_mpu_setu; + unsigned int ldo_sram_mpu_ctrl; + unsigned int io_count; /* offset 0x20 */ + unsigned int io_pmctrl; + unsigned int vc_val_bypass; + unsigned int resv1; + unsigned int emif_ctrl; /* offset 0x30 */ +}; + +struct cm_dpll { + unsigned int resv1; + unsigned int clktimer2clk; /* offset 0x04 */ + unsigned int resv2[11]; + unsigned int clkselmacclk; /* offset 0x34 */ +}; +#endif /* CONFIG_AM43XX */ + +/* Control Module RTC registers */ +struct cm_rtc { + unsigned int rtcclkctrl; /* offset 0x0 */ + unsigned int clkstctrl; /* offset 0x4 */ +}; + +/* Timer 32 bit registers */ +struct gptimer { + unsigned int tidr; /* offset 0x00 */ + unsigned char res1[12]; + unsigned int tiocp_cfg; /* offset 0x10 */ + unsigned char res2[12]; + unsigned int tier; /* offset 0x20 */ + unsigned int tistatr; /* offset 0x24 */ + unsigned int tistat; /* offset 0x28 */ + unsigned int tisr; /* offset 0x2c */ + unsigned int tcicr; /* offset 0x30 */ + unsigned int twer; /* offset 0x34 */ + unsigned int tclr; /* offset 0x38 */ + unsigned int tcrr; /* offset 0x3c */ + unsigned int tldr; /* offset 0x40 */ + unsigned int ttgr; /* offset 0x44 */ + unsigned int twpc; /* offset 0x48 */ + unsigned int tmar; /* offset 0x4c */ + unsigned int tcar1; /* offset 0x50 */ + unsigned int tscir; /* offset 0x54 */ + unsigned int tcar2; /* offset 0x58 */ +}; + +/* UART Registers */ +struct uart_sys { + unsigned int resv1[21]; + unsigned int uartsyscfg; /* offset 0x54 */ + unsigned int uartsyssts; /* offset 0x58 */ +}; + +/* VTP Registers */ +struct vtp_reg { + unsigned int vtp0ctrlreg; +}; + +/* Control Status Register */ +struct ctrl_stat { + unsigned int resv1[16]; + unsigned int statusreg; /* ofset 0x40 */ + unsigned int resv2[51]; + unsigned int secure_emif_sdram_config; /* offset 0x0110 */ + unsigned int resv3[319]; + unsigned int dev_attr; +}; + +/* AM33XX GPIO registers */ +#define OMAP_GPIO_REVISION 0x0000 +#define OMAP_GPIO_SYSCONFIG 0x0010 +#define OMAP_GPIO_SYSSTATUS 0x0114 +#define OMAP_GPIO_IRQSTATUS1 0x002c +#define OMAP_GPIO_IRQSTATUS2 0x0030 +#define OMAP_GPIO_IRQSTATUS_SET_0 0x0034 +#define OMAP_GPIO_IRQSTATUS_SET_1 0x0038 +#define OMAP_GPIO_CTRL 0x0130 +#define OMAP_GPIO_OE 0x0134 +#define OMAP_GPIO_DATAIN 0x0138 +#define OMAP_GPIO_DATAOUT 0x013c +#define OMAP_GPIO_LEVELDETECT0 0x0140 +#define OMAP_GPIO_LEVELDETECT1 0x0144 +#define OMAP_GPIO_RISINGDETECT 0x0148 +#define OMAP_GPIO_FALLINGDETECT 0x014c +#define OMAP_GPIO_DEBOUNCE_EN 0x0150 +#define OMAP_GPIO_DEBOUNCE_VAL 0x0154 +#define OMAP_GPIO_CLEARDATAOUT 0x0190 +#define OMAP_GPIO_SETDATAOUT 0x0194 + +/* Control Device Register */ + + /* Control Device Register */ +#define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F +#define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8 +#define MREQPRIO_1_DSS_MASK 0xFFFFFF8F + +struct ctrl_dev { + unsigned int deviceid; /* offset 0x00 */ + unsigned int resv1[7]; + unsigned int usb_ctrl0; /* offset 0x20 */ + unsigned int resv2; + unsigned int usb_ctrl1; /* offset 0x28 */ + unsigned int resv3; + unsigned int macid0l; /* offset 0x30 */ + unsigned int macid0h; /* offset 0x34 */ + unsigned int macid1l; /* offset 0x38 */ + unsigned int macid1h; /* offset 0x3c */ + unsigned int resv4[4]; + unsigned int miisel; /* offset 0x50 */ + unsigned int resv5[7]; + unsigned int mreqprio_0; /* offset 0x70 */ + unsigned int mreqprio_1; /* offset 0x74 */ + unsigned int resv6[97]; + unsigned int efuse_sma; /* offset 0x1FC */ +}; + +/* Bandwidth Limiter Portion of the L3Fast Configuration Register */ +#define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0 +#define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0 +#define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800 + +struct l3f_cfg_bwlimiter { + u32 padding0[2]; + u32 modena_init0_bw_fractional; + u32 modena_init0_bw_integer; + u32 modena_init0_watermark_0; +}; + +/* gmii_sel register defines */ +#define GMII1_SEL_MII 0x0 +#define GMII1_SEL_RMII 0x1 +#define GMII1_SEL_RGMII 0x2 +#define GMII2_SEL_MII 0x0 +#define GMII2_SEL_RMII 0x4 +#define GMII2_SEL_RGMII 0x8 +#define RGMII1_IDMODE BIT(4) +#define RGMII2_IDMODE BIT(5) +#define RMII1_IO_CLK_EN BIT(6) +#define RMII2_IO_CLK_EN BIT(7) + +#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII) +#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII) +#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII) +#define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE) +#define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN) + +/* PWMSS */ +struct pwmss_regs { + unsigned int idver; + unsigned int sysconfig; + unsigned int clkconfig; + unsigned int clkstatus; +}; +#define ECAP_CLK_EN BIT(0) +#define ECAP_CLK_STOP_REQ BIT(1) +#define EPWM_CLK_EN BIT(8) +#define EPWM_CLK_STOP_REQ BIT(9) + +struct pwmss_ecap_regs { + unsigned int tsctr; + unsigned int ctrphs; + unsigned int cap1; + unsigned int cap2; + unsigned int cap3; + unsigned int cap4; + unsigned int resv1[4]; + unsigned short ecctl1; + unsigned short ecctl2; +}; + +struct pwmss_epwm_regs { + unsigned short tbctl; + unsigned short tbsts; + unsigned short tbphshr; + unsigned short tbphs; + unsigned short tbcnt; + unsigned short tbprd; + unsigned short res1; + unsigned short cmpctl; + unsigned short cmpahr; + unsigned short cmpa; + unsigned short cmpb; + unsigned short aqctla; + unsigned short aqctlb; + unsigned short aqsfrc; + unsigned short aqcsfrc; + unsigned short dbctl; + unsigned short dbred; + unsigned short dbfed; + unsigned short tzsel; + unsigned short tzctl; + unsigned short tzflg; + unsigned short tzclr; + unsigned short tzfrc; + unsigned short etsel; + unsigned short etps; + unsigned short etflg; + unsigned short etclr; + unsigned short etfrc; + unsigned short pcctl; + unsigned int res2[66]; + unsigned short hrcnfg; +}; + +/* Capture Control register 2 */ +#define ECTRL2_SYNCOSEL_MASK (0x03 << 6) +#define ECTRL2_MDSL_ECAP BIT(9) +#define ECTRL2_CTRSTP_FREERUN BIT(4) +#define ECTRL2_PLSL_LOW BIT(10) +#define ECTRL2_SYNC_EN BIT(5) + +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +#endif /* _AM33XX_CPU_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/ddr_defs.h new file mode 100644 index 000000000..15a5b641f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -0,0 +1,383 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * ddr_defs.h + * + * ddr specific header + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef _DDR_DEFS_H +#define _DDR_DEFS_H + +#include +#include + +/* AM335X EMIF Register values */ +#define VTP_CTRL_READY (0x1 << 5) +#define VTP_CTRL_ENABLE (0x1 << 6) +#define VTP_CTRL_START_EN (0x1) +#ifdef CONFIG_AM43XX +#define DDR_CKE_CTRL_NORMAL 0x3 +#else +#define DDR_CKE_CTRL_NORMAL 0x1 +#endif +#define PHY_EN_DYN_PWRDN (0x1 << 20) + +/* Micron MT47H128M16RT-25E */ +#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005 +#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9 +#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA +#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F +#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 +#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a +#define MT47H128M16RT25E_RATIO 0x80 +#define MT47H128M16RT25E_RD_DQS 0x12 +#define MT47H128M16RT25E_PHY_WR_DATA 0x40 +#define MT47H128M16RT25E_PHY_FIFO_WE 0x80 +#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B + +/* Micron MT41J128M16JT-125 */ +#define MT41J128MJT125_EMIF_READ_LATENCY 0x100006 +#define MT41J128MJT125_EMIF_TIM1 0x0888A39B +#define MT41J128MJT125_EMIF_TIM2 0x26337FDA +#define MT41J128MJT125_EMIF_TIM3 0x501F830F +#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2 +#define MT41J128MJT125_EMIF_SDREF 0x0000093B +#define MT41J128MJT125_ZQ_CFG 0x50074BE4 +#define MT41J128MJT125_RATIO 0x40 +#define MT41J128MJT125_INVERT_CLKOUT 0x1 +#define MT41J128MJT125_RD_DQS 0x3B +#define MT41J128MJT125_WR_DQS 0x85 +#define MT41J128MJT125_PHY_WR_DATA 0xC1 +#define MT41J128MJT125_PHY_FIFO_WE 0x100 +#define MT41J128MJT125_IOCTRL_VALUE 0x18B + +/* Micron MT41J128M16JT-125 at 400MHz*/ +#define MT41J128MJT125_EMIF_READ_LATENCY_400MHz 0x100007 +#define MT41J128MJT125_EMIF_TIM1_400MHz 0x0AAAD4DB +#define MT41J128MJT125_EMIF_TIM2_400MHz 0x26437FDA +#define MT41J128MJT125_EMIF_TIM3_400MHz 0x501F83FF +#define MT41J128MJT125_EMIF_SDCFG_400MHz 0x61C052B2 +#define MT41J128MJT125_EMIF_SDREF_400MHz 0x00000C30 +#define MT41J128MJT125_ZQ_CFG_400MHz 0x50074BE4 +#define MT41J128MJT125_RATIO_400MHz 0x80 +#define MT41J128MJT125_INVERT_CLKOUT_400MHz 0x0 +#define MT41J128MJT125_RD_DQS_400MHz 0x3A +#define MT41J128MJT125_WR_DQS_400MHz 0x3B +#define MT41J128MJT125_PHY_WR_DATA_400MHz 0x76 +#define MT41J128MJT125_PHY_FIFO_WE_400MHz 0x96 + +/* Micron MT41K128M16JT-187E */ +#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06 +#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB +#define MT41K128MJT187E_EMIF_TIM2 0x36337FDA +#define MT41K128MJT187E_EMIF_TIM3 0x501F830F +#define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2 +#define MT41K128MJT187E_EMIF_SDREF 0x0000093B +#define MT41K128MJT187E_ZQ_CFG 0x50074BE4 +#define MT41K128MJT187E_RATIO 0x40 +#define MT41K128MJT187E_INVERT_CLKOUT 0x1 +#define MT41K128MJT187E_RD_DQS 0x3B +#define MT41K128MJT187E_WR_DQS 0x85 +#define MT41K128MJT187E_PHY_WR_DATA 0xC1 +#define MT41K128MJT187E_PHY_FIFO_WE 0x100 +#define MT41K128MJT187E_IOCTRL_VALUE 0x18B + +/* Micron MT41K128M16JT-125 IT:K (256 MB) at 400MHz */ +#define MT41K128M16JT125K_EMIF_READ_LATENCY 0x07 +#define MT41K128M16JT125K_EMIF_TIM1 0x0AAAD4DB +#define MT41K128M16JT125K_EMIF_TIM2 0x2A437FDA +#define MT41K128M16JT125K_EMIF_TIM3 0x501F83FF +#define MT41K128M16JT125K_EMIF_SDCFG 0x61A052B2 +#define MT41K128M16JT125K_EMIF_SDREF 0x00000C30 +#define MT41K128M16JT125K_ZQ_CFG 0x50074BE4 +#define MT41K128M16JT125K_RATIO 0x80 +#define MT41K128M16JT125K_INVERT_CLKOUT 0x0 +#define MT41K128M16JT125K_RD_DQS 0x38 +#define MT41K128M16JT125K_WR_DQS 0x46 +#define MT41K128M16JT125K_PHY_WR_DATA 0x7D +#define MT41K128M16JT125K_PHY_FIFO_WE 0x9B +#define MT41K128M16JT125K_IOCTRL_VALUE 0x18B + +/* Micron MT41J64M16JT-125 */ +#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32 + +/* Micron MT41J256M16JT-125 */ +#define MT41J256MJT125_EMIF_SDCFG 0x61C04B32 + +/* Micron MT41J256M8HX-15E */ +#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006 +#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B +#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA +#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F +#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32 +#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B +#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4 +#define MT41J256M8HX15E_RATIO 0x40 +#define MT41J256M8HX15E_INVERT_CLKOUT 0x1 +#define MT41J256M8HX15E_RD_DQS 0x3B +#define MT41J256M8HX15E_WR_DQS 0x85 +#define MT41J256M8HX15E_PHY_WR_DATA 0xC1 +#define MT41J256M8HX15E_PHY_FIFO_WE 0x100 +#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B + +/* Micron MT41K256M16HA-125E */ +#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007 +#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB +#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA +#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F +#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332 +#define MT41K256M16HA125E_EMIF_SDREF 0xC30 +#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4 +#define MT41K256M16HA125E_RATIO 0x80 +#define MT41K256M16HA125E_INVERT_CLKOUT 0x0 +#define MT41K256M16HA125E_RD_DQS 0x38 +#define MT41K256M16HA125E_WR_DQS 0x44 +#define MT41K256M16HA125E_PHY_WR_DATA 0x7D +#define MT41K256M16HA125E_PHY_FIFO_WE 0x94 +#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B + +/* Micron MT41J512M8RH-125 on EVM v1.5 */ +#define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006 +#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B +#define MT41J512M8RH125_EMIF_TIM2 0x26517FDA +#define MT41J512M8RH125_EMIF_TIM3 0x501F84EF +#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2 +#define MT41J512M8RH125_EMIF_SDREF 0x0000093B +#define MT41J512M8RH125_ZQ_CFG 0x50074BE4 +#define MT41J512M8RH125_RATIO 0x80 +#define MT41J512M8RH125_INVERT_CLKOUT 0x0 +#define MT41J512M8RH125_RD_DQS 0x3B +#define MT41J512M8RH125_WR_DQS 0x3C +#define MT41J512M8RH125_PHY_FIFO_WE 0xA5 +#define MT41J512M8RH125_PHY_WR_DATA 0x74 +#define MT41J512M8RH125_IOCTRL_VALUE 0x18B + +/* Samsung K4B2G1646E-BIH9 */ +#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007 +#define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B +#define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA +#define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF +#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2 +#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30 +#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4 +#define K4B2G1646EBIH9_RATIO 0x80 +#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0 +#define K4B2G1646EBIH9_RD_DQS 0x35 +#define K4B2G1646EBIH9_WR_DQS 0x3A +#define K4B2G1646EBIH9_PHY_FIFO_WE 0x97 +#define K4B2G1646EBIH9_PHY_WR_DATA 0x76 +#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B + +#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294 +#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 +#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 +#define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294 + +#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84 +#define DDR3_DATA0_IOCTRL_VALUE 0x84 +#define DDR3_DATA1_IOCTRL_VALUE 0x84 +#define DDR3_DATA2_IOCTRL_VALUE 0x84 +#define DDR3_DATA3_IOCTRL_VALUE 0x84 + +/** + * Configure DMM + */ +void config_dmm(const struct dmm_lisa_map_regs *regs); + +/** + * Configure SDRAM + */ +void config_sdram(const struct emif_regs *regs, int nr); +void config_sdram_emif4d5(const struct emif_regs *regs, int nr); + +/** + * Set SDRAM timings + */ +void set_sdram_timings(const struct emif_regs *regs, int nr); + +/** + * Configure DDR PHY + */ +void config_ddr_phy(const struct emif_regs *regs, int nr); + +struct ddr_cmd_regs { + unsigned int resv0[7]; + unsigned int cm0csratio; /* offset 0x01C */ + unsigned int resv1[3]; + unsigned int cm0iclkout; /* offset 0x02C */ + unsigned int resv2[8]; + unsigned int cm1csratio; /* offset 0x050 */ + unsigned int resv3[3]; + unsigned int cm1iclkout; /* offset 0x060 */ + unsigned int resv4[8]; + unsigned int cm2csratio; /* offset 0x084 */ + unsigned int resv5[3]; + unsigned int cm2iclkout; /* offset 0x094 */ + unsigned int resv6[3]; +}; + +struct ddr_data_regs { + unsigned int dt0rdsratio0; /* offset 0x0C8 */ + unsigned int resv1[4]; + unsigned int dt0wdsratio0; /* offset 0x0DC */ + unsigned int resv2[4]; + unsigned int dt0wiratio0; /* offset 0x0F0 */ + unsigned int resv3; + unsigned int dt0wimode0; /* offset 0x0F8 */ + unsigned int dt0giratio0; /* offset 0x0FC */ + unsigned int resv4; + unsigned int dt0gimode0; /* offset 0x104 */ + unsigned int dt0fwsratio0; /* offset 0x108 */ + unsigned int resv5[4]; + unsigned int dt0dqoffset; /* offset 0x11C */ + unsigned int dt0wrsratio0; /* offset 0x120 */ + unsigned int resv6[4]; + unsigned int dt0rdelays0; /* offset 0x134 */ + unsigned int dt0dldiff0; /* offset 0x138 */ + unsigned int resv7[12]; +}; + +/** + * This structure represents the DDR registers on AM33XX devices. + * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that + * correspond to DATA1 registers defined here. + */ +struct ddr_regs { + unsigned int resv0[3]; + unsigned int cm0config; /* offset 0x00C */ + unsigned int cm0configclk; /* offset 0x010 */ + unsigned int resv1[2]; + unsigned int cm0csratio; /* offset 0x01C */ + unsigned int resv2[3]; + unsigned int cm0iclkout; /* offset 0x02C */ + unsigned int resv3[4]; + unsigned int cm1config; /* offset 0x040 */ + unsigned int cm1configclk; /* offset 0x044 */ + unsigned int resv4[2]; + unsigned int cm1csratio; /* offset 0x050 */ + unsigned int resv5[3]; + unsigned int cm1iclkout; /* offset 0x060 */ + unsigned int resv6[4]; + unsigned int cm2config; /* offset 0x074 */ + unsigned int cm2configclk; /* offset 0x078 */ + unsigned int resv7[2]; + unsigned int cm2csratio; /* offset 0x084 */ + unsigned int resv8[3]; + unsigned int cm2iclkout; /* offset 0x094 */ + unsigned int resv9[12]; + unsigned int dt0rdsratio0; /* offset 0x0C8 */ + unsigned int resv10[4]; + unsigned int dt0wdsratio0; /* offset 0x0DC */ + unsigned int resv11[4]; + unsigned int dt0wiratio0; /* offset 0x0F0 */ + unsigned int resv12; + unsigned int dt0wimode0; /* offset 0x0F8 */ + unsigned int dt0giratio0; /* offset 0x0FC */ + unsigned int resv13; + unsigned int dt0gimode0; /* offset 0x104 */ + unsigned int dt0fwsratio0; /* offset 0x108 */ + unsigned int resv14[4]; + unsigned int dt0dqoffset; /* offset 0x11C */ + unsigned int dt0wrsratio0; /* offset 0x120 */ + unsigned int resv15[4]; + unsigned int dt0rdelays0; /* offset 0x134 */ + unsigned int dt0dldiff0; /* offset 0x138 */ +}; + +/** + * Encapsulates DDR CMD control registers. + */ +struct cmd_control { + unsigned long cmd0csratio; + unsigned long cmd0csforce; + unsigned long cmd0csdelay; + unsigned long cmd0iclkout; + unsigned long cmd1csratio; + unsigned long cmd1csforce; + unsigned long cmd1csdelay; + unsigned long cmd1iclkout; + unsigned long cmd2csratio; + unsigned long cmd2csforce; + unsigned long cmd2csdelay; + unsigned long cmd2iclkout; +}; + +/** + * Encapsulates DDR DATA registers. + */ +struct ddr_data { + unsigned long datardsratio0; + unsigned long datawdsratio0; + unsigned long datawiratio0; + unsigned long datagiratio0; + unsigned long datafwsratio0; + unsigned long datawrsratio0; +}; + +/** + * Configure DDR CMD control registers + */ +void config_cmd_ctrl(const struct cmd_control *cmd, int nr); + +/** + * Configure DDR DATA registers + */ +void config_ddr_data(const struct ddr_data *data, int nr); + +/** + * This structure represents the DDR io control on AM33XX devices. + */ +struct ddr_cmdtctrl { + unsigned int cm0ioctl; + unsigned int cm1ioctl; + unsigned int cm2ioctl; + unsigned int resv2[12]; + unsigned int dt0ioctl; + unsigned int dt1ioctl; + unsigned int dt2ioctrl; + unsigned int dt3ioctrl; + unsigned int resv3[4]; + unsigned int emif_sdram_config_ext; +}; + +struct ctrl_ioregs { + unsigned int cm0ioctl; + unsigned int cm1ioctl; + unsigned int cm2ioctl; + unsigned int dt0ioctl; + unsigned int dt1ioctl; + unsigned int dt2ioctrl; + unsigned int dt3ioctrl; + unsigned int emif_sdram_config_ext; +}; + +/** + * Configure DDR io control registers + */ +void config_io_ctrl(const struct ctrl_ioregs *ioregs); + +struct ddr_ctrl { + unsigned int ddrioctrl; + unsigned int resv1[325]; + unsigned int ddrckectrl; +}; + +#ifdef CONFIG_TI816X +void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl, + const struct emif_regs *regs, + const struct dmm_lisa_map_regs *lisa_regs, int nrs); +#else +void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, + const struct ddr_data *data, const struct cmd_control *ctrl, + const struct emif_regs *regs, int nr); +#endif +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size); + +#endif /* _DDR_DEFS_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/emac_defs.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/emac_defs.h new file mode 100644 index 000000000..eb6516da9 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/emac_defs.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2010 Texas Instruments + * + * Based on: + * + * ---------------------------------------------------------------------------- + * + * dm644x_emac.h + * + * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM + * + * Copyright (C) 2005 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + */ + +#ifndef _EMAC_DEFS_H_ +#define _EMAC_DEFS_H_ + +#ifdef CONFIG_TI816X +#define EMAC_BASE_ADDR (0x4A100000) +#define EMAC_WRAPPER_BASE_ADDR (0x4A100900) +#define EMAC_WRAPPER_RAM_ADDR (0x4A102000) +#define EMAC_MDIO_BASE_ADDR (0x4A100800) +#define EMAC_MDIO_BUS_FREQ (250000000UL) +#define EMAC_MDIO_CLOCK_FREQ (2000000UL) + +typedef volatile unsigned int dv_reg; +typedef volatile unsigned int *dv_reg_p; + +#define DAVINCI_EMAC_VERSION2 +#define DAVINCI_EMAC_GIG_ENABLE +#endif + +#endif /* _EMAC_DEFS_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/gpio.h new file mode 100644 index 000000000..24dc4bb1d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/gpio.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _GPIO_AM33xx_H +#define _GPIO_AM33xx_H + +#include + +#ifdef CONFIG_AM43XX +#define OMAP_MAX_GPIO 192 +#else +#define OMAP_MAX_GPIO 128 +#endif + +#define AM33XX_GPIO0_BASE 0x44E07000 +#define AM33XX_GPIO1_BASE 0x4804C000 +#define AM33XX_GPIO2_BASE 0x481AC000 +#define AM33XX_GPIO3_BASE 0x481AE000 +#define AM33XX_GPIO4_BASE 0x48320000 +#define AM33XX_GPIO5_BASE 0x48322000 + +/* GPIO CTRL register */ +#define GPIO_CTRL_DISABLEMODULE_SHIFT 0 +#define GPIO_CTRL_DISABLEMODULE_MASK (1 << 0) +#define GPIO_CTRL_ENABLEMODULE GPIO_CTRL_DISABLEMODULE_MASK + +/* GPIO OUTPUT ENABLE register */ +#define GPIO_OE_ENABLE(x) (1 << x) + +/* GPIO SETDATAOUT register */ +#define GPIO_SETDATAOUT(x) (1 << x) +#endif /* _GPIO_AM33xx_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware.h new file mode 100644 index 000000000..0508b8c91 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * hardware.h + * + * hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef __AM33XX_HARDWARE_H +#define __AM33XX_HARDWARE_H + +#include +#include +#ifdef CONFIG_AM33XX +#include +#elif defined(CONFIG_TI816X) +#include +#elif defined(CONFIG_TI814X) +#include +#elif defined(CONFIG_AM43XX) +#include +#endif + +/* + * Common hardware definitions + */ + +/* DM Timer base addresses */ +#define DM_TIMER0_BASE 0x4802C000 +#define DM_TIMER1_BASE 0x4802E000 +#define DM_TIMER2_BASE 0x48040000 +#define DM_TIMER3_BASE 0x48042000 +#define DM_TIMER4_BASE 0x48044000 +#define DM_TIMER5_BASE 0x48046000 +#define DM_TIMER6_BASE 0x48048000 +#define DM_TIMER7_BASE 0x4804A000 + +/* GPIO Base address */ +#define GPIO0_BASE 0x48032000 +#define GPIO1_BASE 0x4804C000 + +/* BCH Error Location Module */ +#define ELM_BASE 0x48080000 + +/* EMIF Base address */ +#define EMIF4_0_CFG_BASE 0x4C000000 +#define EMIF4_1_CFG_BASE 0x4D000000 + +/* DDR Base address */ +#define DDR_CTRL_ADDR 0x44E10E04 +#define DDR_CONTROL_BASE_ADDR 0x44E11404 + +/* UART */ +#if CONFIG_CONS_INDEX == 1 +# define DEFAULT_UART_BASE UART0_BASE +#elif CONFIG_CONS_INDEX == 2 +# define DEFAULT_UART_BASE UART1_BASE +#elif CONFIG_CONS_INDEX == 3 +# define DEFAULT_UART_BASE UART2_BASE +#elif CONFIG_CONS_INDEX == 4 +# define DEFAULT_UART_BASE UART3_BASE +#elif CONFIG_CONS_INDEX == 5 +# define DEFAULT_UART_BASE UART4_BASE +#elif CONFIG_CONS_INDEX == 6 +# define DEFAULT_UART_BASE UART5_BASE +#endif + +/* GPMC Base address */ +#define GPMC_BASE 0x50000000 + +/* CPSW Config space */ +#define CPSW_BASE 0x4A100000 + +/* Control status register */ +#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) +#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31 +#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29) +#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29 +#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22) +#define CTRL_SYSBOOT_15_14_SHIFT 22 + +#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0 +#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1 + +#define NUM_CRYSTAL_FREQ 0x4 + +int clk_get(int clk); +#endif /* __AM33XX_HARDWARE_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h new file mode 100644 index 000000000..878ef3e5d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * hardware_am33xx.h + * + * AM33xx hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef __AM33XX_HARDWARE_AM33XX_H +#define __AM33XX_HARDWARE_AM33XX_H + +/* Module base addresses */ + +/* UART Base Address */ +#define UART0_BASE 0x44E09000 +#define UART1_BASE 0x48022000 +#define UART2_BASE 0x48024000 +#define UART3_BASE 0x481A6000 +#define UART4_BASE 0x481A8000 +#define UART5_BASE 0x481AA000 + +/* GPIO Base address */ +#define GPIO2_BASE 0x481AC000 + +/* Watchdog Timer */ +#define WDT_BASE 0x44E35000 + +/* Control Module Base Address */ +#define CTRL_BASE 0x44E10000 +#define CTRL_DEVICE_BASE 0x44E10600 + +/* PRCM Base Address */ +#define PRCM_BASE 0x44E00000 +#define CM_PER 0x44E00000 +#define CM_WKUP 0x44E00400 +#define CM_DPLL 0x44E00500 +#define CM_RTC 0x44E00800 + +#define PRM_RSTCTRL (PRCM_BASE + 0x0F00) +#define PRM_RSTST (PRM_RSTCTRL + 8) + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x44E10E0C +#define VTP1_CTRL_ADDR 0x48140E10 +#define PRM_DEVICE_INST 0x44E00F00 + +/* DDR Base address */ +#define DDR_PHY_CMD_ADDR 0x44E12000 +#define DDR_PHY_DATA_ADDR 0x44E120C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 +#define DDR_DATA_REGS_NR 2 + +#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) +#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE + +/* CPSW Config space */ +#define CPSW_MDIO_BASE 0x4A101000 + +/* RTC base address */ +#define RTC_BASE 0x44E3E000 + +/* OTG */ +#define USB0_OTG_BASE 0x47401000 +#define USB1_OTG_BASE 0x47401800 + +/* LCD Controller */ +#define LCD_CNTL_BASE 0x4830E000 + +/* PWMSS */ +#define PWMSS0_BASE 0x48300000 +#define AM33XX_ECAP0_BASE 0x48300100 +#define AM33XX_EPWM_BASE 0x48300200 + +#endif /* __AM33XX_HARDWARE_AM33XX_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h new file mode 100644 index 000000000..0b73ebdbb --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * hardware_am43xx.h + * + * AM43xx hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef __AM43XX_HARDWARE_AM43XX_H +#define __AM43XX_HARDWARE_AM43XX_H + +#ifndef __ASSEMBLY__ +#include +#endif + +/* Module base addresses */ + +/* L3 Fast Configuration Bandwidth Limiter Base Address */ +#define L3F_CFG_BWLIMITER 0x44005200 + +/* UART Base Address */ +#define UART0_BASE 0x44E09000 + +/* GPIO Base address */ +#define GPIO2_BASE 0x481AC000 + +/* Watchdog Timer */ +#define WDT_BASE 0x44E35000 + +/* Control Module Base Address */ +#define CTRL_BASE 0x44E10000 +#define CTRL_DEVICE_BASE 0x44E10600 + +/* PRCM Base Address */ +#define PRCM_BASE 0x44DF0000 +#define CM_WKUP 0x44DF2800 +#define CM_PER 0x44DF8800 +#define CM_DPLL 0x44DF4200 +#define CM_RTC 0x44DF8500 + +#define PRM_RSTCTRL (PRCM_BASE + 0x4000) +#define PRM_RSTST (PRM_RSTCTRL + 4) + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x44E10E0C +#define VTP1_CTRL_ADDR 0x48140E10 + +/* USB CTRL Base Address */ +#define USB1_CTRL 0x44e10628 +#define USB1_CTRL_CM_PWRDN BIT(0) +#define USB1_CTRL_OTG_PWRDN BIT(1) + +/* DDR Base address */ +#define DDR_PHY_CMD_ADDR 0x44E12000 +#define DDR_PHY_DATA_ADDR 0x44E120C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 +#define DDR_DATA_REGS_NR 2 + +/* CPSW Config space */ +#define CPSW_MDIO_BASE 0x4A101000 + +/* RTC base address */ +#define RTC_BASE 0x44E3E000 + +/* USB OTG */ +#define USB_OTG_SS1_BASE 0x48390000 +#define USB_OTG_SS1_GLUE_BASE 0x48380000 +#define USB2_PHY1_POWER 0x44E10620 + +#define USB_OTG_SS2_BASE 0x483D0000 +#define USB_OTG_SS2_GLUE_BASE 0x483C0000 +#define USB2_PHY2_POWER 0x44E10628 + +/* USB Clock Control */ +#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260) +#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268) +#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1) +#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) + +#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8) +#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) +#define USBPHYOCPSCP_MODULE_EN (1 << 1) +#define CM_DEVICE_INST 0x44df4100 +#define PRM_DEVICE_INST 0x44df4000 + +#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) +#define USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) + +/* EDMA3 Base Address */ +#define EDMA3_BASE 0x49000000 + +#endif /* __AM43XX_HARDWARE_AM43XX_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h new file mode 100644 index 000000000..b00d592bc --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * hardware_ti814x.h + * + * TI814x hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef __AM33XX_HARDWARE_TI814X_H +#define __AM33XX_HARDWARE_TI814X_H + +/* Module base addresses */ + +/* UART Base Address */ +#define UART0_BASE 0x48020000 + +/* Watchdog Timer */ +#define WDT_BASE 0x481C7000 + +/* Control Module Base Address */ +#define CTRL_BASE 0x48140000 +#define CTRL_DEVICE_BASE 0x48140600 + +/* PRCM Base Address */ +#define PRCM_BASE 0x48180000 +#define CM_PER 0x44E00000 +#define CM_WKUP 0x44E00400 + +#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) +#define PRM_RSTST (PRM_RSTCTRL + 8) + +/* PLL Subsystem Base Address */ +#define PLL_SUBSYS_BASE 0x481C5000 + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x48140E0C +#define VTP1_CTRL_ADDR 0x48140E10 + +/* DDR Base address */ +#define DDR_PHY_CMD_ADDR 0x47C0C400 +#define DDR_PHY_DATA_ADDR 0x47C0C4C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 +#define DDR_DATA_REGS_NR 4 + +#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) +#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE + +/* CPSW Config space */ +#define CPSW_MDIO_BASE 0x4A100800 + +/* RTC base address */ +#define RTC_BASE 0x480C0000 + +/* OTG */ +#define USB0_OTG_BASE 0x47401000 +#define USB1_OTG_BASE 0x47401800 + +#endif /* __AM33XX_HARDWARE_TI814X_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h new file mode 100644 index 000000000..78b79486e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h @@ -0,0 +1,62 @@ +/* + * hardware_ti816x.h + * + * TI816x hardware specific header + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * Based on TI-PSP-04.00.02.14 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AM33XX_HARDWARE_TI816X_H +#define __AM33XX_HARDWARE_TI816X_H + +/* UART */ +#define UART0_BASE 0x48020000 +#define UART1_BASE 0x48022000 +#define UART2_BASE 0x48024000 + +/* Watchdog Timer */ +#define WDT_BASE 0x480C2000 + +/* Control Module Base Address */ +#define CTRL_BASE 0x48140000 +#define CTRL_DEVICE_BASE 0x48140600 + +/* PRCM Base Address */ +#define PRCM_BASE 0x48180000 + +#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) +#define PRM_RSTST (PRM_RSTCTRL + 8) + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x48198358 +#define VTP1_CTRL_ADDR 0x4819A358 + +/* DDR Base address */ +#define DDR_PHY_CMD_ADDR 0x48198000 +#define DDR_PHY_DATA_ADDR 0x481980C8 +#define DDR_PHY_CMD_ADDR2 0x4819A000 +#define DDR_PHY_DATA_ADDR2 0x4819A0C8 +#define DDR_DATA_REGS_NR 4 + + +#define DDRPHY_0_CONFIG_BASE 0x48198000 +#define DDRPHY_1_CONFIG_BASE 0x4819A000 +#define DDRPHY_CONFIG_BASE ((emif == 0) ? \ + DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE) + +/* RTC base address */ +#define RTC_BASE 0x480C0000 + +#endif /* __AM33XX_HARDWARE_TI816X_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/i2c.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/i2c.h new file mode 100644 index 000000000..c2a98500d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/i2c.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Texas Instruments, + */ +#ifndef _I2C_AM33XX_H_ +#define _I2C_AM33XX_H_ + +#include + +#define I2C_BASE1 0x44E0B000 +#define I2C_BASE2 0x4802A000 +#define I2C_BASE3 0x4819C000 + +#define I2C_DEFAULT_BASE I2C_BASE1 + +#define I2C_IP_CLK 48000000 +#define I2C_INTERNAL_SAMPLING_CLK 12000000 + +#endif /* _I2C_AM33XX_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/mem.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/mem.h new file mode 100644 index 000000000..0fd52f82f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/mem.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, + * + * Author + * Mansoor Ahamed + * + * Initial Code from: + * Richard Woodruff + */ + +#ifndef _MEM_H_ +#define _MEM_H_ + +/* + * GPMC settings - + * Definitions is as per the following format + * #define _GPMC_CONFIG + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should + * go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * M_NAND - Micron NAND + * STNOR - STMicrolelctronics M29W128GL + */ +#define GPMC_SIZE_256M 0x0 +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#define M_NAND_GPMC_CONFIG1 0x00000800 +#define M_NAND_GPMC_CONFIG2 0x001e1e00 +#define M_NAND_GPMC_CONFIG3 0x001e1e00 +#define M_NAND_GPMC_CONFIG4 0x16051807 +#define M_NAND_GPMC_CONFIG5 0x00151e1e +#define M_NAND_GPMC_CONFIG6 0x16000f80 +#define M_NAND_GPMC_CONFIG7 0x00000008 + +#define STNOR_GPMC_CONFIG1 0x00001200 +#define STNOR_GPMC_CONFIG2 0x00101000 +#define STNOR_GPMC_CONFIG3 0x00030301 +#define STNOR_GPMC_CONFIG4 0x10041004 +#define STNOR_GPMC_CONFIG5 0x000C1010 +#define STNOR_GPMC_CONFIG6 0x08070280 +#define STNOR_GPMC_CONFIG7 0x00000F48 + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#define DBG_MPDB 6 + +#endif /* endif _MEM_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/mmc_host_def.h new file mode 100644 index 000000000..5a2ea8fae --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -0,0 +1,35 @@ +/* + * mmc_host_def.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MMC_HOST_DEF_H +#define MMC_HOST_DEF_H + +#include + +/* + * OMAP HSMMC register definitions + */ +#define OMAP_HSMMC1_BASE 0x48060000 +#define OMAP_HSMMC2_BASE 0x481D8000 + +#if defined(CONFIG_TI814X) +#undef MMC_CLOCK_REFERENCE +#define MMC_CLOCK_REFERENCE 192 /* MHz */ +#elif defined(CONFIG_TI816X) +#undef MMC_CLOCK_REFERENCE +#define MMC_CLOCK_REFERENCE 48 /* MHz */ +#endif + +#endif /* MMC_HOST_DEF_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux.h new file mode 100644 index 000000000..b16b18473 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux.h @@ -0,0 +1,46 @@ +/* + * mux.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MUX_H_ +#define _MUX_H_ + +#include + +#ifdef CONFIG_AM33XX +#include +#elif defined(CONFIG_TI814X) +#include +#elif defined(CONFIG_TI816X) +#include +#elif defined(CONFIG_AM43XX) +#include +#endif + +struct module_pin_mux { + short reg_offset; + unsigned int val; +}; + +/* Pad control register offset */ +#define PAD_CTRL_BASE 0x800 +#define OFFSET(x) (unsigned int) (&((struct pad_signals *)\ + (PAD_CTRL_BASE))->x) + +/* + * Configure the pin mux for the module + */ +void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux); + +#endif /* endif _MUX_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am33xx.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am33xx.h new file mode 100644 index 000000000..26bd4b46f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am33xx.h @@ -0,0 +1,246 @@ +/* + * mux_am33xx.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MUX_AM33XX_H_ +#define _MUX_AM33XX_H_ + +#include + +#define MUX_CFG(value, offset) \ + __raw_writel(value, (CTRL_BASE + offset)); + +/* PAD Control Fields */ +#define SLEWCTRL (0x1 << 6) +#define RXACTIVE (0x1 << 5) +#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */ +#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */ +#define PULLUDEN (0x0 << 3) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ +#define MODE(val) val /* used for Readability */ + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int gpmc_ad0; + int gpmc_ad1; + int gpmc_ad2; + int gpmc_ad3; + int gpmc_ad4; + int gpmc_ad5; + int gpmc_ad6; + int gpmc_ad7; + int gpmc_ad8; + int gpmc_ad9; + int gpmc_ad10; + int gpmc_ad11; + int gpmc_ad12; + int gpmc_ad13; + int gpmc_ad14; + int gpmc_ad15; + int gpmc_a0; + int gpmc_a1; + int gpmc_a2; + int gpmc_a3; + int gpmc_a4; + int gpmc_a5; + int gpmc_a6; + int gpmc_a7; + int gpmc_a8; + int gpmc_a9; + int gpmc_a10; + int gpmc_a11; + int gpmc_wait0; + int gpmc_wpn; + int gpmc_be1n; + int gpmc_csn0; + int gpmc_csn1; + int gpmc_csn2; + int gpmc_csn3; + int gpmc_clk; + int gpmc_advn_ale; + int gpmc_oen_ren; + int gpmc_wen; + int gpmc_be0n_cle; + int lcd_data0; + int lcd_data1; + int lcd_data2; + int lcd_data3; + int lcd_data4; + int lcd_data5; + int lcd_data6; + int lcd_data7; + int lcd_data8; + int lcd_data9; + int lcd_data10; + int lcd_data11; + int lcd_data12; + int lcd_data13; + int lcd_data14; + int lcd_data15; + int lcd_vsync; + int lcd_hsync; + int lcd_pclk; + int lcd_ac_bias_en; + int mmc0_dat3; + int mmc0_dat2; + int mmc0_dat1; + int mmc0_dat0; + int mmc0_clk; + int mmc0_cmd; + int mii1_col; + int mii1_crs; + int mii1_rxerr; + int mii1_txen; + int mii1_rxdv; + int mii1_txd3; + int mii1_txd2; + int mii1_txd1; + int mii1_txd0; + int mii1_txclk; + int mii1_rxclk; + int mii1_rxd3; + int mii1_rxd2; + int mii1_rxd1; + int mii1_rxd0; + int rmii1_refclk; + int mdio_data; + int mdio_clk; + int spi0_sclk; + int spi0_d0; + int spi0_d1; + int spi0_cs0; + int spi0_cs1; + int ecap0_in_pwm0_out; + int uart0_ctsn; + int uart0_rtsn; + int uart0_rxd; + int uart0_txd; + int uart1_ctsn; + int uart1_rtsn; + int uart1_rxd; + int uart1_txd; + int i2c0_sda; + int i2c0_scl; + int mcasp0_aclkx; + int mcasp0_fsx; + int mcasp0_axr0; + int mcasp0_ahclkr; + int mcasp0_aclkr; + int mcasp0_fsr; + int mcasp0_axr1; + int mcasp0_ahclkx; + int xdma_event_intr0; + int xdma_event_intr1; + int nresetin_out; + int porz; + int nnmi; + int osc0_in; + int osc0_out; + int rsvd1; + int tms; + int tdi; + int tdo; + int tck; + int ntrst; + int emu0; + int emu1; + int osc1_in; + int osc1_out; + int pmic_power_en; + int rtc_porz; + int rsvd2; + int ext_wakeup; + int enz_kaldo_1p8v; + int usb0_dm; + int usb0_dp; + int usb0_ce; + int usb0_id; + int usb0_vbus; + int usb0_drvvbus; + int usb1_dm; + int usb1_dp; + int usb1_ce; + int usb1_id; + int usb1_vbus; + int usb1_drvvbus; + int ddr_resetn; + int ddr_csn0; + int ddr_cke; + int ddr_ck; + int ddr_nck; + int ddr_casn; + int ddr_rasn; + int ddr_wen; + int ddr_ba0; + int ddr_ba1; + int ddr_ba2; + int ddr_a0; + int ddr_a1; + int ddr_a2; + int ddr_a3; + int ddr_a4; + int ddr_a5; + int ddr_a6; + int ddr_a7; + int ddr_a8; + int ddr_a9; + int ddr_a10; + int ddr_a11; + int ddr_a12; + int ddr_a13; + int ddr_a14; + int ddr_a15; + int ddr_odt; + int ddr_d0; + int ddr_d1; + int ddr_d2; + int ddr_d3; + int ddr_d4; + int ddr_d5; + int ddr_d6; + int ddr_d7; + int ddr_d8; + int ddr_d9; + int ddr_d10; + int ddr_d11; + int ddr_d12; + int ddr_d13; + int ddr_d14; + int ddr_d15; + int ddr_dqm0; + int ddr_dqm1; + int ddr_dqs0; + int ddr_dqsn0; + int ddr_dqs1; + int ddr_dqsn1; + int ddr_vref; + int ddr_vtp; + int ddr_strben0; + int ddr_strben1; + int ain7; + int ain6; + int ain5; + int ain4; + int ain3; + int ain2; + int ain1; + int ain0; + int vrefp; + int vrefn; +}; + +#endif /* endif _MUX_AM33XX_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am43xx.h new file mode 100644 index 000000000..f74ae74ff --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am43xx.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * mux_am43xx.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef _MUX_AM43XX_H_ +#define _MUX_AM43XX_H_ + +#include + +#define MUX_CFG(value, offset) \ + __raw_writel(value, (CTRL_BASE + offset)); + +/* PAD Control Fields */ +#define SLEWCTRL (0x1 << 19) +#define RXACTIVE (0x1 << 18) +#define PULLDOWN_EN (0x0 << 17) /* Pull Down Selection */ +#define PULLUP_EN (0x1 << 17) /* Pull Up Selection */ +#define PULLUDEN (0x0 << 16) /* Pull up/down enable */ +#define PULLUDDIS (0x1 << 16) /* Pull up/down disable */ +#define MODE(val) val /* used for Readability */ + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int gpmc_ad0; + int gpmc_ad1; + int gpmc_ad2; + int gpmc_ad3; + int gpmc_ad4; + int gpmc_ad5; + int gpmc_ad6; + int gpmc_ad7; + int gpmc_ad8; + int gpmc_ad9; + int gpmc_ad10; + int gpmc_ad11; + int gpmc_ad12; + int gpmc_ad13; + int gpmc_ad14; + int gpmc_ad15; + int gpmc_a0; + int gpmc_a1; + int gpmc_a2; + int gpmc_a3; + int gpmc_a4; + int gpmc_a5; + int gpmc_a6; + int gpmc_a7; + int gpmc_a8; + int gpmc_a9; + int gpmc_a10; + int gpmc_a11; + int gpmc_wait0; + int gpmc_wpn; + int gpmc_be1n; + int gpmc_csn0; + int gpmc_csn1; + int gpmc_csn2; + int gpmc_csn3; + int gpmc_clk; + int gpmc_advn_ale; + int gpmc_oen_ren; + int gpmc_wen; + int gpmc_be0n_cle; + int lcd_data0; + int lcd_data1; + int lcd_data2; + int lcd_data3; + int lcd_data4; + int lcd_data5; + int lcd_data6; + int lcd_data7; + int lcd_data8; + int lcd_data9; + int lcd_data10; + int lcd_data11; + int lcd_data12; + int lcd_data13; + int lcd_data14; + int lcd_data15; + int lcd_vsync; + int lcd_hsync; + int lcd_pclk; + int lcd_ac_bias_en; + int mmc0_dat3; + int mmc0_dat2; + int mmc0_dat1; + int mmc0_dat0; + int mmc0_clk; + int mmc0_cmd; + int mii1_col; + int mii1_crs; + int mii1_rxerr; + int mii1_txen; + int mii1_rxdv; + int mii1_txd3; + int mii1_txd2; + int mii1_txd1; + int mii1_txd0; + int mii1_txclk; + int mii1_rxclk; + int mii1_rxd3; + int mii1_rxd2; + int mii1_rxd1; + int mii1_rxd0; + int rmii1_refclk; + int mdio_data; + int mdio_clk; + int spi0_sclk; + int spi0_d0; + int spi0_d1; + int spi0_cs0; + int spi0_cs1; + int ecap0_in_pwm0_out; + int uart0_ctsn; + int uart0_rtsn; + int uart0_rxd; + int uart0_txd; + int uart1_ctsn; + int uart1_rtsn; + int uart1_rxd; + int uart1_txd; + int i2c0_sda; + int i2c0_scl; + int mcasp0_aclkx; + int mcasp0_fsx; + int mcasp0_axr0; + int mcasp0_ahclkr; + int mcasp0_aclkr; + int mcasp0_fsr; + int mcasp0_axr1; + int mcasp0_ahclkx; + int cam0_hd; + int cam0_vd; + int cam0_field; + int cam0_wen; + int cam0_pclk; + int cam0_data8; + int cam0_data9; + int cam1_data9; + int cam1_data8; + int cam1_hd; + int cam1_vd; + int cam1_pclk; + int cam1_field; + int cam1_wen; + int cam1_data0; + int cam1_data1; + int cam1_data2; + int cam1_data3; + int cam1_data4; + int cam1_data5; + int cam1_data6; + int cam1_data7; + int cam0_data0; + int cam0_data1; + int cam0_data2; + int cam0_data3; + int cam0_data4; + int cam0_data5; + int cam0_data6; + int cam0_data7; + int uart3_rxd; + int uart3_txd; + int uart3_ctsn; + int uart3_rtsn; + int gpio5_8; + int gpio5_9; + int gpio5_10; + int gpio5_11; + int gpio5_12; + int gpio5_13; + int spi4_sclk; + int spi4_d0; + int spi4_d1; + int spi4_cs0; + int spi2_sclk; + int spi2_d0; + int spi2_d1; + int spi2_cs0; + int xdma_evt_intr0; + int xdma_evt_intr1; + int clkreq; + int nresetin_out; + int rsvd1; + int nnmi; + int rsvd2; + int rsvd3; + int tms; + int tdi; + int tdo; + int tck; + int ntrst; + int emu0; + int emu1; + int osc1_in; + int osc1_out; + int rtc_porz; + int ext_wakeup0; + int pmic_power_en0; + int usb0_drvvbus; + int usb1_drvvbus; +}; + +#endif /* _MUX_AM43XX_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti814x.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti814x.h new file mode 100644 index 000000000..a26e5038f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti814x.h @@ -0,0 +1,311 @@ +/* + * mux_ti814x.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MUX_TI814X_H_ +#define _MUX_TI814X_H_ + +/* PAD Control Fields */ +#define PINCNTL_RSV_MSK (0x3 << 18) /* Reserved bitmask */ +#define PULLUP_EN (0x1 << 17) /* Pull UP Selection */ +#define PULLUDEN (0x0 << 16) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 16) /* Pull up disabled */ +#define MODE(val) val /* used for Readability */ + +#define MUX_CFG(value, offset) \ +{ \ + int tmp; \ + tmp = __raw_readl(CTRL_BASE + offset); \ + tmp &= PINCNTL_RSV_MSK; \ + __raw_writel(tmp | value, (CTRL_BASE + offset));\ +} + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int pincntl1; + int pincntl2; + int pincntl3; + int pincntl4; + int pincntl5; + int pincntl6; + int pincntl7; + int pincntl8; + int pincntl9; + int pincntl10; + int pincntl11; + int pincntl12; + int pincntl13; + int pincntl14; + int pincntl15; + int pincntl16; + int pincntl17; + int pincntl18; + int pincntl19; + int pincntl20; + int pincntl21; + int pincntl22; + int pincntl23; + int pincntl24; + int pincntl25; + int pincntl26; + int pincntl27; + int pincntl28; + int pincntl29; + int pincntl30; + int pincntl31; + int pincntl32; + int pincntl33; + int pincntl34; + int pincntl35; + int pincntl36; + int pincntl37; + int pincntl38; + int pincntl39; + int pincntl40; + int pincntl41; + int pincntl42; + int pincntl43; + int pincntl44; + int pincntl45; + int pincntl46; + int pincntl47; + int pincntl48; + int pincntl49; + int pincntl50; + int pincntl51; + int pincntl52; + int pincntl53; + int pincntl54; + int pincntl55; + int pincntl56; + int pincntl57; + int pincntl58; + int pincntl59; + int pincntl60; + int pincntl61; + int pincntl62; + int pincntl63; + int pincntl64; + int pincntl65; + int pincntl66; + int pincntl67; + int pincntl68; + int pincntl69; + int pincntl70; + int pincntl71; + int pincntl72; + int pincntl73; + int pincntl74; + int pincntl75; + int pincntl76; + int pincntl77; + int pincntl78; + int pincntl79; + int pincntl80; + int pincntl81; + int pincntl82; + int pincntl83; + int pincntl84; + int pincntl85; + int pincntl86; + int pincntl87; + int pincntl88; + int pincntl89; + int pincntl90; + int pincntl91; + int pincntl92; + int pincntl93; + int pincntl94; + int pincntl95; + int pincntl96; + int pincntl97; + int pincntl98; + int pincntl99; + int pincntl100; + int pincntl101; + int pincntl102; + int pincntl103; + int pincntl104; + int pincntl105; + int pincntl106; + int pincntl107; + int pincntl108; + int pincntl109; + int pincntl110; + int pincntl111; + int pincntl112; + int pincntl113; + int pincntl114; + int pincntl115; + int pincntl116; + int pincntl117; + int pincntl118; + int pincntl119; + int pincntl120; + int pincntl121; + int pincntl122; + int pincntl123; + int pincntl124; + int pincntl125; + int pincntl126; + int pincntl127; + int pincntl128; + int pincntl129; + int pincntl130; + int pincntl131; + int pincntl132; + int pincntl133; + int pincntl134; + int pincntl135; + int pincntl136; + int pincntl137; + int pincntl138; + int pincntl139; + int pincntl140; + int pincntl141; + int pincntl142; + int pincntl143; + int pincntl144; + int pincntl145; + int pincntl146; + int pincntl147; + int pincntl148; + int pincntl149; + int pincntl150; + int pincntl151; + int pincntl152; + int pincntl153; + int pincntl154; + int pincntl155; + int pincntl156; + int pincntl157; + int pincntl158; + int pincntl159; + int pincntl160; + int pincntl161; + int pincntl162; + int pincntl163; + int pincntl164; + int pincntl165; + int pincntl166; + int pincntl167; + int pincntl168; + int pincntl169; + int pincntl170; + int pincntl171; + int pincntl172; + int pincntl173; + int pincntl174; + int pincntl175; + int pincntl176; + int pincntl177; + int pincntl178; + int pincntl179; + int pincntl180; + int pincntl181; + int pincntl182; + int pincntl183; + int pincntl184; + int pincntl185; + int pincntl186; + int pincntl187; + int pincntl188; + int pincntl189; + int pincntl190; + int pincntl191; + int pincntl192; + int pincntl193; + int pincntl194; + int pincntl195; + int pincntl196; + int pincntl197; + int pincntl198; + int pincntl199; + int pincntl200; + int pincntl201; + int pincntl202; + int pincntl203; + int pincntl204; + int pincntl205; + int pincntl206; + int pincntl207; + int pincntl208; + int pincntl209; + int pincntl210; + int pincntl211; + int pincntl212; + int pincntl213; + int pincntl214; + int pincntl215; + int pincntl216; + int pincntl217; + int pincntl218; + int pincntl219; + int pincntl220; + int pincntl221; + int pincntl222; + int pincntl223; + int pincntl224; + int pincntl225; + int pincntl226; + int pincntl227; + int pincntl228; + int pincntl229; + int pincntl230; + int pincntl231; + int pincntl232; + int pincntl233; + int pincntl234; + int pincntl235; + int pincntl236; + int pincntl237; + int pincntl238; + int pincntl239; + int pincntl240; + int pincntl241; + int pincntl242; + int pincntl243; + int pincntl244; + int pincntl245; + int pincntl246; + int pincntl247; + int pincntl248; + int pincntl249; + int pincntl250; + int pincntl251; + int pincntl252; + int pincntl253; + int pincntl254; + int pincntl255; + int pincntl256; + int pincntl257; + int pincntl258; + int pincntl259; + int pincntl260; + int pincntl261; + int pincntl262; + int pincntl263; + int pincntl264; + int pincntl265; + int pincntl266; + int pincntl267; + int pincntl268; + int pincntl269; + int pincntl270; +}; + +#endif /* endif _MUX_TI814X_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti816x.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti816x.h new file mode 100644 index 000000000..a6a8a988a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti816x.h @@ -0,0 +1,362 @@ +/* + * mux_ti816x.h + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MUX_TI816X_H_ +#define _MUX_TI816X_H_ + +#include + +#define MUX_CFG(value, offset) \ + __raw_writel(value, (CTRL_BASE + offset)); + +#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */ +#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */ +#define PULLUDEN (0x0 << 3) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ +#define MODE(val) (val) /* used for Readability */ + + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int pincntl1; + int pincntl2; + int pincntl3; + int pincntl4; + int pincntl5; + int pincntl6; + int pincntl7; + int pincntl8; + int pincntl9; + int pincntl10; + int pincntl11; + int pincntl12; + int pincntl13; + int pincntl14; + int pincntl15; + int pincntl16; + int pincntl17; + int pincntl18; + int pincntl19; + int pincntl20; + int pincntl21; + int pincntl22; + int pincntl23; + int pincntl24; + int pincntl25; + int pincntl26; + int pincntl27; + int pincntl28; + int pincntl29; + int pincntl30; + int pincntl31; + int pincntl32; + int pincntl33; + int pincntl34; + int pincntl35; + int pincntl36; + int pincntl37; + int pincntl38; + int pincntl39; + int pincntl40; + int pincntl41; + int pincntl42; + int pincntl43; + int pincntl44; + int pincntl45; + int pincntl46; + int pincntl47; + int pincntl48; + int pincntl49; + int pincntl50; + int pincntl51; + int pincntl52; + int pincntl53; + int pincntl54; + int pincntl55; + int pincntl56; + int pincntl57; + int pincntl58; + int pincntl59; + int pincntl60; + int pincntl61; + int pincntl62; + int pincntl63; + int pincntl64; + int pincntl65; + int pincntl66; + int pincntl67; + int pincntl68; + int pincntl69; + int pincntl70; + int pincntl71; + int pincntl72; + int pincntl73; + int pincntl74; + int pincntl75; + int pincntl76; + int pincntl77; + int pincntl78; + int pincntl79; + int pincntl80; + int pincntl81; + int pincntl82; + int pincntl83; + int pincntl84; + int pincntl85; + int pincntl86; + int pincntl87; + int pincntl88; + int pincntl89; + int pincntl90; + int pincntl91; + int pincntl92; + int pincntl93; + int pincntl94; + int pincntl95; + int pincntl96; + int pincntl97; + int pincntl98; + int pincntl99; + int pincntl100; + int pincntl101; + int pincntl102; + int pincntl103; + int pincntl104; + int pincntl105; + int pincntl106; + int pincntl107; + int pincntl108; + int pincntl109; + int pincntl110; + int pincntl111; + int pincntl112; + int pincntl113; + int pincntl114; + int pincntl115; + int pincntl116; + int pincntl117; + int pincntl118; + int pincntl119; + int pincntl120; + int pincntl121; + int pincntl122; + int pincntl123; + int pincntl124; + int pincntl125; + int pincntl126; + int pincntl127; + int pincntl128; + int pincntl129; + int pincntl130; + int pincntl131; + int pincntl132; + int pincntl133; + int pincntl134; + int pincntl135; + int pincntl136; + int pincntl137; + int pincntl138; + int pincntl139; + int pincntl140; + int pincntl141; + int pincntl142; + int pincntl143; + int pincntl144; + int pincntl145; + int pincntl146; + int pincntl147; + int pincntl148; + int pincntl149; + int pincntl150; + int pincntl151; + int pincntl152; + int pincntl153; + int pincntl154; + int pincntl155; + int pincntl156; + int pincntl157; + int pincntl158; + int pincntl159; + int pincntl160; + int pincntl161; + int pincntl162; + int pincntl163; + int pincntl164; + int pincntl165; + int pincntl166; + int pincntl167; + int pincntl168; + int pincntl169; + int pincntl170; + int pincntl171; + int pincntl172; + int pincntl173; + int pincntl174; + int pincntl175; + int pincntl176; + int pincntl177; + int pincntl178; + int pincntl179; + int pincntl180; + int pincntl181; + int pincntl182; + int pincntl183; + int pincntl184; + int pincntl185; + int pincntl186; + int pincntl187; + int pincntl188; + int pincntl189; + int pincntl190; + int pincntl191; + int pincntl192; + int pincntl193; + int pincntl194; + int pincntl195; + int pincntl196; + int pincntl197; + int pincntl198; + int pincntl199; + int pincntl200; + int pincntl201; + int pincntl202; + int pincntl203; + int pincntl204; + int pincntl205; + int pincntl206; + int pincntl207; + int pincntl208; + int pincntl209; + int pincntl210; + int pincntl211; + int pincntl212; + int pincntl213; + int pincntl214; + int pincntl215; + int pincntl216; + int pincntl217; + int pincntl218; + int pincntl219; + int pincntl220; + int pincntl221; + int pincntl222; + int pincntl223; + int pincntl224; + int pincntl225; + int pincntl226; + int pincntl227; + int pincntl228; + int pincntl229; + int pincntl230; + int pincntl231; + int pincntl232; + int pincntl233; + int pincntl234; + int pincntl235; + int pincntl236; + int pincntl237; + int pincntl238; + int pincntl239; + int pincntl240; + int pincntl241; + int pincntl242; + int pincntl243; + int pincntl244; + int pincntl245; + int pincntl246; + int pincntl247; + int pincntl248; + int pincntl249; + int pincntl250; + int pincntl251; + int pincntl252; + int pincntl253; + int pincntl254; + int pincntl255; + int pincntl256; + int pincntl257; + int pincntl258; + int pincntl259; + int pincntl260; + int pincntl261; + int pincntl262; + int pincntl263; + int pincntl264; + int pincntl265; + int pincntl266; + int pincntl267; + int pincntl268; + int pincntl269; + int pincntl270; + int pincntl271; + int pincntl272; + int pincntl273; + int pincntl274; + int pincntl275; + int pincntl276; + int pincntl277; + int pincntl278; + int pincntl279; + int pincntl280; + int pincntl281; + int pincntl282; + int pincntl283; + int pincntl284; + int pincntl285; + int pincntl286; + int pincntl287; + int pincntl288; + int pincntl289; + int pincntl290; + int pincntl291; + int pincntl292; + int pincntl293; + int pincntl294; + int pincntl295; + int pincntl296; + int pincntl297; + int pincntl298; + int pincntl299; + int pincntl300; + int pincntl301; + int pincntl302; + int pincntl303; + int pincntl304; + int pincntl305; + int pincntl306; + int pincntl307; + int pincntl308; + int pincntl309; + int pincntl310; + int pincntl311; + int pincntl312; + int pincntl313; + int pincntl314; + int pincntl315; + int pincntl316; + int pincntl317; + int pincntl318; + int pincntl319; + int pincntl320; + int pincntl321; + int pincntl322; + int pincntl323; +}; + +#endif /* endif _MUX_TI816X_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/omap.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/omap.h new file mode 100644 index 000000000..bc9f0a114 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/omap.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * omap.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * Author: + * Chandan Nath + * + * Derived from OMAP4 work by + * Aneesh V + */ + +#ifndef _OMAP_H_ +#define _OMAP_H_ + +#include + +#ifdef CONFIG_AM33XX +#define NON_SECURE_SRAM_START 0x402F0400 +#define NON_SECURE_SRAM_END 0x40310000 +#define NON_SECURE_SRAM_IMG_END 0x4030B800 +#elif defined(CONFIG_TI816X) || defined(CONFIG_TI814X) +#define NON_SECURE_SRAM_START 0x40300000 +#define NON_SECURE_SRAM_END 0x40320000 +#define NON_SECURE_SRAM_IMG_END 0x4031B800 +#elif defined(CONFIG_AM43XX) +#define NON_SECURE_SRAM_START 0x402F0400 +#define NON_SECURE_SRAM_END 0x40340000 +#define NON_SECURE_SRAM_IMG_END 0x40337DE0 +#define QSPI_BASE 0x47900000 +#endif +#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K) + +/* Boot parameters */ +#ifndef __ASSEMBLY__ +struct omap_boot_parameters { + unsigned int reserved; + unsigned int boot_device_descriptor; + unsigned char boot_device; + unsigned char reset_reason; +}; + +#define DEVICE_TYPE_SHIFT 0x8 +#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/spl.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/spl.h new file mode 100644 index 000000000..f3910c212 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/spl.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Texas Instruments, + */ +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_ARCH_SPL_H_ + +#define BOOT_DEVICE_NONE 0x00 +#define BOOT_DEVICE_MMC2_2 0xFF + +#if defined(CONFIG_TI814X) +#define BOOT_DEVICE_XIP 0x01 +#define BOOT_DEVICE_XIPWAIT 0x02 +#define BOOT_DEVICE_NAND 0x05 +#define BOOT_DEVICE_NAND_I2C 0x06 +#define BOOT_DEVICE_MMC2 0x08 /* ROM only supports 2nd instance. */ +#define BOOT_DEVICE_MMC1 0x09 +#define BOOT_DEVICE_SPI 0x15 +#define BOOT_DEVICE_UART 0x41 +#define BOOT_DEVICE_USBETH 0x44 +#define BOOT_DEVICE_CPGMAC 0x46 + +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 +#elif defined(CONFIG_TI816X) +#define BOOT_DEVICE_XIP 0x01 +#define BOOT_DEVICE_XIPWAIT 0x02 +#define BOOT_DEVICE_NAND 0x03 +#define BOOT_DEVICE_ONENAND 0x04 +#define BOOT_DEVICE_MMC2 0x05 /* ROM only supports 2nd instance. */ +#define BOOT_DEVICE_MMC1 0x06 +#define BOOT_DEVICE_UART 0x43 +#define BOOT_DEVICE_USB 0x45 + +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 +#elif defined(CONFIG_AM33XX) +#define BOOT_DEVICE_XIP 0x01 +#define BOOT_DEVICE_XIPWAIT 0x02 +#define BOOT_DEVICE_NAND 0x05 +#define BOOT_DEVICE_NAND_I2C 0x06 +#define BOOT_DEVICE_MMC1 0x08 +#define BOOT_DEVICE_MMC2 0x09 +#define BOOT_DEVICE_SPI 0x0B +#define BOOT_DEVICE_UART 0x41 +#define BOOT_DEVICE_USBETH 0x44 +#define BOOT_DEVICE_CPGMAC 0x46 +#define BOOT_DEVICE_ONENAND 0xFF /* ROM does not support OneNAND. */ + +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 +#elif defined(CONFIG_AM43XX) +#define BOOT_DEVICE_NOR 0x01 +#define BOOT_DEVICE_NAND 0x05 +#define BOOT_DEVICE_MMC1 0x07 +#define BOOT_DEVICE_MMC2 0x08 +#define BOOT_DEVICE_SPI 0x0A +#define BOOT_DEVICE_USB 0x0D +#define BOOT_DEVICE_UART 0x41 +#define BOOT_DEVICE_USBETH 0x45 +#define BOOT_DEVICE_CPGMAC 0x47 + +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 +#ifdef CONFIG_SPL_USB_STORAGE +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_USB +#else +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 +#endif +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-am33xx/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-am33xx/sys_proto.h new file mode 100644 index 000000000..be17aad29 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * sys_proto.h + * + * System information header + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ +#include +#include + +u32 get_cpu_rev(void); +u32 get_sysboot_value(void); + +extern struct ctrl_stat *cstat; +u32 get_device_type(void); +void save_omap_boot_params(void); +void setup_early_clocks(void); +void setup_clocks_for_console(void); +void mpu_pll_config_val(int mpull_m); +void ddr_pll_config(unsigned int ddrpll_M); + +void sdelay(unsigned long); + +void gpmc_init(void); +void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, u32 base, + u32 size); +int omap_nand_switch_ecc(uint32_t, uint32_t); + +void set_uart_mux_conf(void); +void set_mux_conf_regs(void); +void sdram_init(void); +u32 wait_on_value(u32, u32, void *, u32); +#ifdef CONFIG_NOR_BOOT +void enable_norboot_pin_mux(void); +#endif +void am33xx_spl_board_init(void); +int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev); +int am335x_get_mpu_vdd(int sil_rev, int frequency); +int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency); +#endif + +void enable_usb_clocks(int index); +void disable_usb_clocks(int index); +void do_board_detect(void); +u32 get_sys_clk_index(void); diff --git a/roms/u-boot/arch/arm/include/asm/arch-armada100/armada100.h b/roms/u-boot/arch/arm/include/asm/arch-armada100/armada100.h new file mode 100644 index 000000000..dd21ad3c6 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-armada100/armada100.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * Contributor: Mahavir Jain + */ + +#ifndef _ASM_ARCH_ARMADA100_H +#define _ASM_ARCH_ARMADA100_H + +#if defined (CONFIG_ARMADA100) + +/* Common APB clock register bit definitions */ +#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */ +#define APBC_FNCLK (1<<1) /* Functional Clock Enable */ +#define APBC_RST (1<<2) /* Reset Generation */ +/* Functional Clock Selection Mask */ +#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) + +/* Fast Ethernet Controller Clock register definition */ +#define FE_CLK_RST 0x1 +#define FE_CLK_ENA 0x8 + +/* SSP2 Clock Control */ +#define SSP2_APBCLK 0x01 +#define SSP2_FNCLK 0x02 + +/* USB Clock/reset control bits */ +#define USB_SPH_AXICLK_EN 0x10 +#define USB_SPH_AXI_RST 0x02 + +/* MPMU Clocks */ +#define APB2_26M_EN (1 << 20) +#define AP_26M (1 << 4) + +/* Register Base Addresses */ +#define ARMD1_DRAM_BASE 0xB0000000 +#define ARMD1_FEC_BASE 0xC0800000 +#define ARMD1_TIMER_BASE 0xD4014000 +#define ARMD1_APBC1_BASE 0xD4015000 +#define ARMD1_APBC2_BASE 0xD4015800 +#define ARMD1_UART1_BASE 0xD4017000 +#define ARMD1_UART2_BASE 0xD4018000 +#define ARMD1_GPIO_BASE 0xD4019000 +#define ARMD1_SSP1_BASE 0xD401B000 +#define ARMD1_SSP2_BASE 0xD401C000 +#define ARMD1_MFPR_BASE 0xD401E000 +#define ARMD1_SSP3_BASE 0xD401F000 +#define ARMD1_SSP4_BASE 0xD4020000 +#define ARMD1_SSP5_BASE 0xD4021000 +#define ARMD1_UART3_BASE 0xD4026000 +#define ARMD1_MPMU_BASE 0xD4050000 +#define ARMD1_USB_HOST_BASE 0xD4209000 +#define ARMD1_APMU_BASE 0xD4282800 +#define ARMD1_CPU_BASE 0xD4282C00 + +#endif /* CONFIG_ARMADA100 */ +#endif /* _ASM_ARCH_ARMADA100_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-armada100/config.h b/roms/u-boot/arch/arm/include/asm/arch-armada100/config.h new file mode 100644 index 000000000..2862dd072 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-armada100/config.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 + * Marvell Semiconductor + * Written-by: Lei Wen + */ + +/* + * This file should be included in board config header file. + * + * It supports common definitions for Armada100 platform + */ + +#ifndef _ARMD1_CONFIG_H +#define _ARMD1_CONFIG_H + +#include + +#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ +#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ +#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */ +#define MV_MFPR_BASE ARMD1_MFPR_BASE +#define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE +#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register + represents UART Unit Enable */ + +#endif /* _ARMD1_CONFIG_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-armada100/cpu.h b/roms/u-boot/arch/arm/include/asm/arch-armada100/cpu.h new file mode 100644 index 000000000..cd5e5051d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-armada100/cpu.h @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar , Contributor: Mahavir Jain + */ + +#ifndef _ARMADA100CPU_H +#define _ARMADA100CPU_H + +#include +#include + +/* + * Main Power Management (MPMU) Registers + * Refer Datasheet Appendix A.8 + */ +struct armd1mpmu_registers { + u8 pad0[0x08 - 0x00]; + u32 fccr; /*0x0008*/ + u32 pocr; /*0x000c*/ + u32 posr; /*0x0010*/ + u32 succr; /*0x0014*/ + u8 pad1[0x030 - 0x014 - 4]; + u32 gpcr; /*0x0030*/ + u8 pad2[0x200 - 0x030 - 4]; + u32 wdtpcr; /*0x0200*/ + u8 pad3[0x1000 - 0x200 - 4]; + u32 apcr; /*0x1000*/ + u32 apsr; /*0x1004*/ + u8 pad4[0x1020 - 0x1004 - 4]; + u32 aprr; /*0x1020*/ + u32 acgr; /*0x1024*/ + u32 arsr; /*0x1028*/ +}; + +/* + * Application Subsystem Power Management + * Refer Datasheet Appendix A.9 + */ +struct armd1apmu_registers { + u32 pcr; /* 0x000 */ + u32 ccr; /* 0x004 */ + u32 pad1; + u32 ccsr; /* 0x00C */ + u32 fc_timer; /* 0x010 */ + u32 pad2; + u32 ideal_cfg; /* 0x018 */ + u8 pad3[0x04C - 0x018 - 4]; + u32 lcdcrc; /* 0x04C */ + u32 cciccrc; /* 0x050 */ + u32 sd1crc; /* 0x054 */ + u32 sd2crc; /* 0x058 */ + u32 usbcrc; /* 0x05C */ + u32 nfccrc; /* 0x060 */ + u32 dmacrc; /* 0x064 */ + u32 pad4; + u32 buscrc; /* 0x06C */ + u8 pad5[0x07C - 0x06C - 4]; + u32 wake_clr; /* 0x07C */ + u8 pad6[0x090 - 0x07C - 4]; + u32 core_status; /* 0x090 */ + u32 rfsc; /* 0x094 */ + u32 imr; /* 0x098 */ + u32 irwc; /* 0x09C */ + u32 isr; /* 0x0A0 */ + u8 pad7[0x0B0 - 0x0A0 - 4]; + u32 mhst; /* 0x0B0 */ + u32 msr; /* 0x0B4 */ + u8 pad8[0x0C0 - 0x0B4 - 4]; + u32 msst; /* 0x0C0 */ + u32 pllss; /* 0x0C4 */ + u32 smb; /* 0x0C8 */ + u32 gccrc; /* 0x0CC */ + u8 pad9[0x0D4 - 0x0CC - 4]; + u32 smccrc; /* 0x0D4 */ + u32 pad10; + u32 xdcrc; /* 0x0DC */ + u32 sd3crc; /* 0x0E0 */ + u32 sd4crc; /* 0x0E4 */ + u8 pad11[0x0F0 - 0x0E4 - 4]; + u32 cfcrc; /* 0x0F0 */ + u32 mspcrc; /* 0x0F4 */ + u32 cmucrc; /* 0x0F8 */ + u32 fecrc; /* 0x0FC */ + u32 pciecrc; /* 0x100 */ + u32 epdcrc; /* 0x104 */ +}; + +/* + * APB1 Clock Reset/Control Registers + * Refer Datasheet Appendix A.10 + */ +struct armd1apb1_registers { + u32 uart1; /*0x000*/ + u32 uart2; /*0x004*/ + u32 gpio; /*0x008*/ + u32 pwm1; /*0x00c*/ + u32 pwm2; /*0x010*/ + u32 pwm3; /*0x014*/ + u32 pwm4; /*0x018*/ + u8 pad0[0x028 - 0x018 - 4]; + u32 rtc; /*0x028*/ + u32 twsi0; /*0x02c*/ + u32 kpc; /*0x030*/ + u32 timers; /*0x034*/ + u8 pad1[0x03c - 0x034 - 4]; + u32 aib; /*0x03c*/ + u32 sw_jtag; /*0x040*/ + u32 timer1; /*0x044*/ + u32 onewire; /*0x048*/ + u8 pad2[0x050 - 0x048 - 4]; + u32 asfar; /*0x050 AIB Secure First Access Reg*/ + u32 assar; /*0x054 AIB Secure Second Access Reg*/ + u8 pad3[0x06c - 0x054 - 4]; + u32 twsi1; /*0x06c*/ + u32 uart3; /*0x070*/ + u8 pad4[0x07c - 0x070 - 4]; + u32 timer2; /*0x07C*/ + u8 pad5[0x084 - 0x07c - 4]; + u32 ac97; /*0x084*/ +}; + +/* +* APB2 Clock Reset/Control Registers +* Refer Datasheet Appendix A.11 +*/ +struct armd1apb2_registers { + u32 pad1[0x01C - 0x000]; + u32 ssp1_clkrst; /* 0x01C */ + u32 ssp2_clkrst; /* 0x020 */ + u32 pad2[0x04C - 0x020 - 4]; + u32 ssp3_clkrst; /* 0x04C */ + u32 pad3[0x058 - 0x04C - 4]; + u32 ssp4_clkrst; /* 0x058 */ + u32 ssp5_clkrst; /* 0x05C */ +}; + +/* + * CPU Interface Registers + * Refer Datasheet Appendix A.2 + */ +struct armd1cpu_registers { + u32 chip_id; /* Chip Id Reg */ + u32 pad; + u32 cpu_conf; /* CPU Conf Reg */ + u32 pad1; + u32 cpu_sram_spd; /* CPU SRAM Speed Reg */ + u32 pad2; + u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */ + u32 mcb_conf; /* MCB Conf Reg */ + u32 sys_boot_ctl; /* Sytem Boot Control */ +}; + +/* + * Functions + */ +u32 armd1_sdram_base(int); +u32 armd1_sdram_size(int); + +#endif /* _ARMADA100CPU_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-armada100/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-armada100/gpio.h new file mode 100644 index 000000000..b85f6a53d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-armada100/gpio.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 + * eInfochips Ltd. + * Written-by: Ajay Bhargav + * + * (C) Copyright 2010 + * Marvell Semiconductor + */ + +#ifndef _ASM_ARCH_GPIO_H +#define _ASM_ARCH_GPIO_H + +#include +#include + +#define GPIO_HIGH 1 +#define GPIO_LOW 0 + +#define GPIO_TO_REG(gp) (gp >> 5) +#define GPIO_TO_BIT(gp) (1 << (gp & 0x1F)) +#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01) + +static inline void *get_gpio_base(int bank) +{ + const unsigned int offset[4] = {0, 4, 8, 0x100}; + /* gpio register bank offset - refer Appendix A.36 */ + return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]); +} + +#endif /* _ASM_ARCH_GPIO_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-armada100/mfp.h b/roms/u-boot/arch/arm/include/asm/arch-armada100/mfp.h new file mode 100644 index 000000000..a808ee857 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-armada100/mfp.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h + * (C) Copyright 2007 + * Marvell Semiconductor + * 2007-08-21: eric miao + * + * (C) Copyright 2010 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * Contributor: Mahavir Jain + */ + +#ifndef __ARMADA100_MFP_H +#define __ARMADA100_MFP_H + +/* + * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs + * + * offset, pull,pF, drv,dF, edge,eF ,afn,aF + */ +/* UART1 */ +#define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST) +#define MFP107_UART1_RXD (MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST) +#define MFP108_UART1_RXD (MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST) +#define MFP108_UART1_TXD (MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST) +#define MFP109_UART1_CTS (MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM) +#define MFP109_UART1_RTS (MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM) +#define MFP110_UART1_RTS (MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM) +#define MFP110_UART1_CTS (MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM) +#define MFP111_UART1_RI (MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM) +#define MFP111_UART1_DSR (MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM) +#define MFP112_UART1_DTR (MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM) +#define MFP112_UART1_DCD (MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM) + +/* UART2 */ +#define MFP47_UART2_RXD (MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM) +#define MFP48_UART2_TXD (MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM) +#define MFP88_UART2_RXD (MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM) +#define MFP89_UART2_TXD (MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM) + +/* UART3 */ +#define MFPO8_UART3_TXD (MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM) +#define MFPO9_UART3_RXD (MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM) + +/* I2c */ +#define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM) +#define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM) + +/* Fast Ethernet */ +#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP087_ETH_TXEN (MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP095_ETH_RXER (MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM) + +/* SPI */ +#define MFP107_SSP2_RXD (MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM) +#define MFP108_SSP2_TXD (MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM) +#define MFP110_SSP2_CS (MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM) +#define MFP111_SSP2_CLK (MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM) + +/* More macros can be defined here... */ + +#define MFP_PIN_MAX 117 + +#endif /* __ARMADA100_MFP_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-armada100/spi.h b/roms/u-boot/arch/arm/include/asm/arch-armada100/spi.h new file mode 100644 index 000000000..873ba6e91 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-armada100/spi.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 + * eInfochips Ltd. + * Written-by: Ajay Bhargav + * + * (C) Copyright 2010 + * Marvell Semiconductor + */ + +#ifndef __ARMADA100_SPI_H_ +#define __ARMADA100_SPI_H_ + +#include + +#define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE +#define SSP_REG_BASE(x) CAT_BASE_ADDR(x) + +/* + * SSP Serial Port Registers + * refer Appendix A.26 + */ +struct ssp_reg { + u32 sscr0; /* SSP Control Register 0 - 0x000 */ + u32 sscr1; /* SSP Control Register 1 - 0x004 */ + u32 sssr; /* SSP Status Register - 0x008 */ + u32 ssitr; /* SSP Interrupt Test Register - 0x00C */ + u32 ssdr; /* SSP Data Register - 0x010 */ + u32 pad1[5]; + u32 ssto; /* SSP Timeout Register - 0x028 */ + u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */ + u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */ + u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */ + u32 sstss; /* SSP Timeslot Status Register - 0x038 */ +}; + +#define DEFAULT_WORD_LEN 8 +#define SSP_FLUSH_NUM 0x2000 +#define RX_THRESH_DEF 8 +#define TX_THRESH_DEF 8 +#define TIMEOUT_DEF 1000 + +#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ +#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ +#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ +#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity + setting */ +#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ +#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ +#define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */ +#define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */ + +#define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */ +#define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */ +#define SSCR1_TINTE (1 << 19) /* Receiver Time-out + Interrupt enable */ + +#define SSCR0_DSS 0x0f /* Data Size Select (mask) */ +#define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */ +#define SSCR0_FRF 0x30 /* FRame Format (mask) */ +#define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial + Peripheral Interface */ +#define SSCR0_TI (0x1 << 4) /* TI's Synchronous + Serial Protocol (SSP) */ +#define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */ +#define SSCR0_ECS (1 << 6) /* External clock select */ +#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port + Enable */ + +#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ +#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ +#define SSSR_BSY (1 << 4) /* SSP Busy */ +#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ +#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ +#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ +#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ + +#endif /* __ARMADA100_SPI_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-armada100/utmi-armada100.h b/roms/u-boot/arch/arm/include/asm/arch-armada100/utmi-armada100.h new file mode 100644 index 000000000..28147f42a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-armada100/utmi-armada100.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * eInfochips Ltd. + * Written-by: Ajay Bhargav + * + * (C) Copyright 2009 + * Marvell Semiconductor + */ + +#ifndef __UTMI_ARMADA100__ +#define __UTMI_ARMADA100__ + +#define UTMI_PHY_BASE 0xD4206000 + +/* utmi_ctrl - bits */ +#define INPKT_DELAY_SOF (1 << 28) +#define PLL_PWR_UP 2 +#define PHY_PWR_UP 1 + +/* utmi_pll - bits */ +#define PLL_FBDIV_MASK 0x00000FF0 +#define PLL_FBDIV 4 +#define PLL_REFDIV_MASK 0x0000000F +#define PLL_REFDIV 0 +#define PLL_READY 0x800000 +#define VCOCAL_START (1 << 21) + +#define N_DIVIDER 0xEE +#define M_DIVIDER 0x0B + +/* utmi_tx - bits */ +#define CK60_PHSEL 17 +#define PHSEL_VAL 0x4 +#define RCAL_START (1 << 12) + +/* + * USB PHY registers + * Refer Datasheet Appendix A.21 + */ +struct armd1usb_phy_reg { + u32 utmi_rev; /* USB PHY Revision */ + u32 utmi_ctrl; /* USB PHY Control register */ + u32 utmi_pll; /* PLL register */ + u32 utmi_tx; /* Tx register */ + u32 utmi_rx; /* Rx register */ + u32 utmi_ivref; /* IVREF register */ + u32 utmi_tst_g0; /* Test group 0 register */ + u32 utmi_tst_g1; /* Test group 1 register */ + u32 utmi_tst_g2; /* Test group 2 register */ + u32 utmi_tst_g3; /* Test group 3 register */ + u32 utmi_tst_g4; /* Test group 4 register */ + u32 utmi_tst_g5; /* Test group 5 register */ + u32 utmi_reserve; /* Reserve Register */ + u32 utmi_usb_int; /* USB interuppt register */ + u32 utmi_dbg_ctl; /* Debug control register */ + u32 utmi_otg_addon; /* OTG addon register */ +}; + +int utmi_init(void); + +#endif /* __UTMI_ARMADA100__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-armada8k/cache_llc.h b/roms/u-boot/arch/arm/include/asm/arch-armada8k/cache_llc.h new file mode 100644 index 000000000..8cb114496 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-armada8k/cache_llc.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Marvell International Ltd. + * https://spdx.org/licenses + */ + +#ifndef _CACHE_LLC_H_ +#define _CACHE_LLC_H_ + +/* Armada-7K/8K last level cache */ + +#define MVEBU_A8K_REGS_BASE_MSB 0xf000 +#define LLC_BASE_ADDR 0x8000 +#define LLC_CACHE_SYNC 0x700 +#define LLC_CACHE_SYNC_COMPLETE 0x730 +#define LLC_FLUSH_BY_WAY 0x7fc +#define LLC_WAY_MASK 0xffffffff +#define LLC_CACHE_SYNC_MASK 0x1 + +#endif /* _CACHE_LLC_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-armada8k/soc-info.h b/roms/u-boot/arch/arm/include/asm/arch-armada8k/soc-info.h new file mode 100644 index 000000000..64606efff --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-armada8k/soc-info.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Marvell International Ltd. + * https://spdx.org/licenses + */ + +#ifndef _SOC_INFO_H_ +#define _SOC_INFO_H_ + +/* Pin Ctrl driver definitions */ +#define BITS_PER_PIN 4 +#define PIN_FUNC_MASK ((1 << BITS_PER_PIN) - 1) +#define PIN_REG_SHIFT 3 +#define PIN_FIELD_MASK ((1 << PIN_REG_SHIFT) - 1) + +#endif /* _SOC_INFO_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-armv7/generictimer.h b/roms/u-boot/arch/arm/include/asm/arch-armv7/generictimer.h new file mode 100644 index 000000000..f40268609 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-armv7/generictimer.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2013 - ARM Ltd + * Author: Marc Zyngier + * + * Based on code by Carl van Schaik . + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef _GENERICTIMER_H_ +#define _GENERICTIMER_H_ + +#ifdef __ASSEMBLY__ + +/* + * This macro provide a physical timer that can be used for delay in the code. + * The macro is moved from sunxi/psci_sun7i.S + * + * reg: is used in this macro. + * ticks: The freq is based on generic timer. + */ +.macro timer_wait reg, ticks + movw \reg, #(\ticks & 0xffff) + movt \reg, #(\ticks >> 16) + mcr p15, 0, \reg, c14, c2, 0 + isb + mov \reg, #3 + mcr p15, 0, \reg, c14, c2, 1 +1 : isb + mrc p15, 0, \reg, c14, c2, 1 + ands \reg, \reg, #4 + bne 1b + mov \reg, #0 + mcr p15, 0, \reg, c14, c2, 1 + isb +.endm + +#endif /* __ASSEMBLY__ */ + +#endif /* _GENERICTIMER_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-armv7/globaltimer.h b/roms/u-boot/arch/arm/include/asm/arch-armv7/globaltimer.h new file mode 100644 index 000000000..2d9cf7798 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-armv7/globaltimer.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 Nobuhiro Iwamatsu + * (C) Copyright 2012 Renesas Solutions Corp. + */ +#ifndef _GLOBALTIMER_H_ +#define _GLOBALTIMER_H_ + +struct globaltimer { + u32 cnt_l; /* 0x00 */ + u32 cnt_h; + u32 ctl; + u32 stat; + u32 cmp_l; /* 0x10 */ + u32 cmp_h; + u32 inc; +}; + +#endif /* _GLOBALTIMER_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-armv7/sysctrl.h b/roms/u-boot/arch/arm/include/asm/arch-armv7/sysctrl.h new file mode 100644 index 000000000..fc72fac8d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-armv7/sysctrl.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 Linaro + * Matt Waddel, + */ +#ifndef _SYSCTRL_H_ +#define _SYSCTRL_H_ + +/* System controller (SP810) register definitions */ +#define SP810_TIMER0_ENSEL (1 << 15) +#define SP810_TIMER1_ENSEL (1 << 17) +#define SP810_TIMER2_ENSEL (1 << 19) +#define SP810_TIMER3_ENSEL (1 << 21) + +struct sysctrl { + u32 scctrl; /* 0x000 */ + u32 scsysstat; + u32 scimctrl; + u32 scimstat; + u32 scxtalctrl; + u32 scpllctrl; + u32 scpllfctrl; + u32 scperctrl0; + u32 scperctrl1; + u32 scperen; + u32 scperdis; + u32 scperclken; + u32 scperstat; + u32 res1[0x006]; + u32 scflashctrl; /* 0x04c */ + u32 res2[0x3a4]; + u32 scsysid0; /* 0xee0 */ + u32 scsysid1; + u32 scsysid2; + u32 scsysid3; + u32 scitcr; + u32 scitir0; + u32 scitir1; + u32 scitor; + u32 sccntctrl; + u32 sccntdata; + u32 sccntstep; + u32 res3[0x32]; + u32 scperiphid0; /* 0xfe0 */ + u32 scperiphid1; + u32 scperiphid2; + u32 scperiphid3; + u32 scpcellid0; + u32 scpcellid1; + u32 scpcellid2; + u32 scpcellid3; +}; +#endif /* _SYSCTRL_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-armv7/systimer.h b/roms/u-boot/arch/arm/include/asm/arch-armv7/systimer.h new file mode 100644 index 000000000..04c413045 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-armv7/systimer.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 Linaro + * Matt Waddel, + */ +#ifndef _SYSTIMER_H_ +#define _SYSTIMER_H_ + +/* AMBA timer register base address */ +#define SYSTIMER_BASE 0x10011000 + +#define SYSHZ_CLOCK 1000000 /* Timers -> 1Mhz */ +#define SYSTIMER_RELOAD 0xFFFFFFFF +#define SYSTIMER_EN (1 << 7) +#define SYSTIMER_32BIT (1 << 1) +#define SYSTIMER_PRESC_16 (1 << 2) +#define SYSTIMER_PRESC_256 (1 << 3) + +struct systimer { + u32 timer0load; /* 0x00 */ + u32 timer0value; + u32 timer0control; + u32 timer0intclr; + u32 timer0ris; + u32 timer0mis; + u32 timer0bgload; + u32 timer1load; /* 0x20 */ + u32 timer1value; + u32 timer1control; + u32 timer1intclr; + u32 timer1ris; + u32 timer1mis; + u32 timer1bgload; +}; +#endif /* _SYSTIMER_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-armv7/wdt.h b/roms/u-boot/arch/arm/include/asm/arch-armv7/wdt.h new file mode 100644 index 000000000..e3fa16ffa --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-armv7/wdt.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Matt Waddel, + */ +#ifndef _WDT_H_ +#define _WDT_H_ + +/* Watchdog timer (SP805) register base address */ +#define WDT_BASE 0x100E5000 + +#define WDT_EN 0x2 +#define WDT_RESET_LOAD 0x0 + +struct wdt { + u32 wdogload; /* 0x000 */ + u32 wdogvalue; + u32 wdogcontrol; + u32 wdogintclr; + u32 wdogris; + u32 wdogmis; + u32 res1[0x2F9]; + u32 wdoglock; /* 0xC00 */ + u32 res2[0xBE]; + u32 wdogitcr; /* 0xF00 */ + u32 wdogitop; + u32 res3[0x35]; + u32 wdogperiphid0; /* 0xFE0 */ + u32 wdogperiphid1; + u32 wdogperiphid2; + u32 wdogperiphid3; + u32 wdogpcellid0; + u32 wdogpcellid1; + u32 wdogpcellid2; + u32 wdogpcellid3; +}; + +#endif /* _WDT_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/boot0.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/boot0.h new file mode 100644 index 000000000..368becc87 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/boot0.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ + +#ifndef _ASM_ARCH_BOOT0_H +#define _ASM_ARCH_BOOT0_H + +_start: + ARM_VECTORS + + .word 0x0 /* key location */ + .word 0x0 /* start address of image */ + .word 0xfc00 /* maximum image size: 63KB */ + .word 0x0 /* signature address */ + .word 0x0 /* header revision ID low */ + .word 0x0 /* header revision ID high */ + .word 0x0 /* reserved */ + .word 0x0 /* checksum */ + .word 0x0 /* BL2 secure header */ + .word 0x0 /* public key or digest offset for BL2 */ + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/pinctrl.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/pinctrl.h new file mode 100644 index 000000000..dd85464dd --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/pinctrl.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2017 Google, Inc + */ +#ifndef _ASM_ARCH_PERIPH_H +#define _ASM_ARCH_PERIPH_H + +/* + * Peripherals supported by the hardware. + * These are used to specify pinctrl settings. + */ + +enum periph_id { + PERIPH_ID_UART1, + PERIPH_ID_UART2, + PERIPH_ID_UART3, + PERIPH_ID_UART4, + PERIPH_ID_LPC, + PERIPH_ID_PWM0, + PERIPH_ID_PWM1, + PERIPH_ID_PWM2, + PERIPH_ID_PWM3, + PERIPH_ID_PWM4, + PERIPH_ID_PWM5, + PERIPH_ID_PWM6, + PERIPH_ID_PWM7, + PERIPH_ID_PWM8, + PERIPH_ID_MAC1, + PERIPH_ID_MAC2, + PERIPH_ID_VIDEO, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, + PERIPH_ID_I2C8, + PERIPH_ID_I2C9, + PERIPH_ID_I2C10, + PERIPH_ID_I2C11, + PERIPH_ID_I2C12, + PERIPH_ID_I2C13, + PERIPH_ID_I2C14, + PERIPH_ID_SD1, + PERIPH_ID_SD2, +}; + +#endif /* _ASM_ARCH_SCU_AST2500_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/platform.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/platform.h new file mode 100644 index 000000000..d50ec5f8a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/platform.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) ASPEED Technology Inc. + * Ryan Chen + * + */ + +#ifndef _ASM_ARCH_PLATFORM_H +#define _ASM_ARCH_PLATFORM_H + +#if defined(CONFIG_ASPEED_AST2500) +#define ASPEED_MAC_COUNT 2 +#define ASPEED_DRAM_BASE 0x80000000 +#define ASPEED_SRAM_BASE 0x1e720000 +#define ASPEED_SRAM_SIZE 0x9000 +#elif defined(CONFIG_ASPEED_AST2600) +#define ASPEED_MAC_COUNT 4 +#define ASPEED_DRAM_BASE 0x80000000 +#define ASPEED_SRAM_BASE 0x10000000 +#define ASPEED_SRAM_SIZE 0x10000 +#else +#err "Unrecognized Aspeed platform." +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/scu_ast2500.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/scu_ast2500.h new file mode 100644 index 000000000..8db4901cc --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/scu_ast2500.h @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2016 Google, Inc + */ +#ifndef _ASM_ARCH_SCU_AST2500_H +#define _ASM_ARCH_SCU_AST2500_H + +#define SCU_UNLOCK_VALUE 0x1688a8a8 + +#define SCU_HWSTRAP_VGAMEM_SHIFT 2 +#define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT) +#define SCU_HWSTRAP_MAC1_RGMII (1 << 6) +#define SCU_HWSTRAP_MAC2_RGMII (1 << 7) +#define SCU_HWSTRAP_DDR4 (1 << 24) +#define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23) + +#define SCU_MPLL_DENUM_SHIFT 0 +#define SCU_MPLL_DENUM_MASK 0x1f +#define SCU_MPLL_NUM_SHIFT 5 +#define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT) +#define SCU_MPLL_POST_SHIFT 13 +#define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT) +#define SCU_PCLK_DIV_SHIFT 23 +#define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT) +#define SCU_SDCLK_DIV_SHIFT 12 +#define SCU_SDCLK_DIV_MASK (7 << SCU_SDCLK_DIV_SHIFT) +#define SCU_HPLL_DENUM_SHIFT 0 +#define SCU_HPLL_DENUM_MASK 0x1f +#define SCU_HPLL_NUM_SHIFT 5 +#define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT) +#define SCU_HPLL_POST_SHIFT 13 +#define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT) + +#define SCU_MACCLK_SHIFT 16 +#define SCU_MACCLK_MASK (7 << SCU_MACCLK_SHIFT) + +#define SCU_MISC2_RGMII_HPLL (1 << 23) +#define SCU_MISC2_RGMII_CLKDIV_SHIFT 20 +#define SCU_MISC2_RGMII_CLKDIV_MASK (3 << SCU_MISC2_RGMII_CLKDIV_SHIFT) +#define SCU_MISC2_RMII_MPLL (1 << 19) +#define SCU_MISC2_RMII_CLKDIV_SHIFT 16 +#define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT) +#define SCU_MISC2_UARTCLK_SHIFT 24 + +#define SCU_MISC_D2PLL_OFF (1 << 4) +#define SCU_MISC_UARTCLK_DIV13 (1 << 12) +#define SCU_MISC_GCRT_USB20CLK (1 << 21) + +#define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT 0 +#define SCU_MICDS_MAC1RGMII_TXDLY_MASK (0x3f\ + << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT) +#define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT 6 +#define SCU_MICDS_MAC2RGMII_TXDLY_MASK (0x3f\ + << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT) +#define SCU_MICDS_MAC1RMII_RDLY_SHIFT 12 +#define SCU_MICDS_MAC1RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT) +#define SCU_MICDS_MAC2RMII_RDLY_SHIFT 18 +#define SCU_MICDS_MAC2RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT) +#define SCU_MICDS_MAC1RMII_TXFALL (1 << 24) +#define SCU_MICDS_MAC2RMII_TXFALL (1 << 25) +#define SCU_MICDS_RMII1_RCLKEN (1 << 29) +#define SCU_MICDS_RMII2_RCLKEN (1 << 30) +#define SCU_MICDS_RGMIIPLL (1 << 31) + +/* + * SYSRESET is actually more like a Power register, + * except that corresponding bit set to 1 means that + * the peripheral is off. + */ +#define SCU_SYSRESET_XDMA (1 << 25) +#define SCU_SYSRESET_MCTP (1 << 24) +#define SCU_SYSRESET_ADC (1 << 23) +#define SCU_SYSRESET_JTAG (1 << 22) +#define SCU_SYSRESET_MIC (1 << 18) +#define SCU_SYSRESET_SDIO (1 << 16) +#define SCU_SYSRESET_USB11HOST (1 << 15) +#define SCU_SYSRESET_USBHUB (1 << 14) +#define SCU_SYSRESET_CRT (1 << 13) +#define SCU_SYSRESET_MAC2 (1 << 12) +#define SCU_SYSRESET_MAC1 (1 << 11) +#define SCU_SYSRESET_PECI (1 << 10) +#define SCU_SYSRESET_PWM (1 << 9) +#define SCU_SYSRESET_PCI_VGA (1 << 8) +#define SCU_SYSRESET_2D (1 << 7) +#define SCU_SYSRESET_VIDEO (1 << 6) +#define SCU_SYSRESET_LPC (1 << 5) +#define SCU_SYSRESET_HAC (1 << 4) +#define SCU_SYSRESET_USBHID (1 << 3) +#define SCU_SYSRESET_I2C (1 << 2) +#define SCU_SYSRESET_AHB (1 << 1) +#define SCU_SYSRESET_SDRAM_WDT (1 << 0) + +/* Bits 16-27 in the register control pin functions for I2C devices 3-14 */ +#define SCU_PINMUX_CTRL5_I2C (1 << 16) + +/* + * The values are grouped by function, not by register. + * They are actually scattered across multiple loosely related registers. + */ +#define SCU_PIN_FUN_MAC1_MDC (1 << 30) +#define SCU_PIN_FUN_MAC1_MDIO (1 << 31) +#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0) +#define SCU_PIN_FUN_MAC2_MDIO (1 << 2) +#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1) +#define SCU_PIN_FUN_SCL1 (1 << 12) +#define SCU_PIN_FUN_SCL2 (1 << 14) +#define SCU_PIN_FUN_SDA1 (1 << 13) +#define SCU_PIN_FUN_SDA2 (1 << 15) + +#define SCU_CLKSTOP_MAC1 (1 << 20) +#define SCU_CLKSTOP_MAC2 (1 << 21) +#define SCU_CLKSTOP_SDCLK (1 << 27) + +#define SCU_D2PLL_EXT1_OFF (1 << 0) +#define SCU_D2PLL_EXT1_BYPASS (1 << 1) +#define SCU_D2PLL_EXT1_RESET (1 << 2) +#define SCU_D2PLL_EXT1_MODE_SHIFT 3 +#define SCU_D2PLL_EXT1_MODE_MASK (3 << SCU_D2PLL_EXT1_MODE_SHIFT) +#define SCU_D2PLL_EXT1_PARAM_SHIFT 5 +#define SCU_D2PLL_EXT1_PARAM_MASK (0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT) + +#define SCU_D2PLL_NUM_SHIFT 0 +#define SCU_D2PLL_NUM_MASK (0xff << SCU_D2PLL_NUM_SHIFT) +#define SCU_D2PLL_DENUM_SHIFT 8 +#define SCU_D2PLL_DENUM_MASK (0x1f << SCU_D2PLL_DENUM_SHIFT) +#define SCU_D2PLL_POST_SHIFT 13 +#define SCU_D2PLL_POST_MASK (0x3f << SCU_D2PLL_POST_SHIFT) +#define SCU_D2PLL_ODIV_SHIFT 19 +#define SCU_D2PLL_ODIV_MASK (7 << SCU_D2PLL_ODIV_SHIFT) +#define SCU_D2PLL_SIC_SHIFT 22 +#define SCU_D2PLL_SIC_MASK (0x1f << SCU_D2PLL_SIC_SHIFT) +#define SCU_D2PLL_SIP_SHIFT 27 +#define SCU_D2PLL_SIP_MASK (0x1f << SCU_D2PLL_SIP_SHIFT) + +#define SCU_CLKDUTY_DCLK_SHIFT 0 +#define SCU_CLKDUTY_DCLK_MASK (0x3f << SCU_CLKDUTY_DCLK_SHIFT) +#define SCU_CLKDUTY_RGMII1TXCK_SHIFT 8 +#define SCU_CLKDUTY_RGMII1TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII1TXCK_SHIFT) +#define SCU_CLKDUTY_RGMII2TXCK_SHIFT 16 +#define SCU_CLKDUTY_RGMII2TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII2TXCK_SHIFT) + +#ifndef __ASSEMBLY__ + +struct ast2500_clk_priv { + struct ast2500_scu *scu; +}; + +struct ast2500_scu { + u32 protection_key; + u32 sysreset_ctrl1; + u32 clk_sel1; + u32 clk_stop_ctrl1; + u32 freq_counter_ctrl; + u32 freq_counter_cmp; + u32 intr_ctrl; + u32 d2_pll_param; + u32 m_pll_param; + u32 h_pll_param; + u32 d_pll_param; + u32 misc_ctrl1; + u32 pci_config[3]; + u32 sysreset_status; + u32 vga_handshake[2]; + u32 mac_clk_delay; + u32 misc_ctrl2; + u32 vga_scratch[8]; + u32 hwstrap; + u32 rng_ctrl; + u32 rng_data; + u32 rev_id; + u32 pinmux_ctrl[6]; + u32 reserved0; + u32 extrst_sel; + u32 pinmux_ctrl1[4]; + u32 reserved1[2]; + u32 mac_clk_delay_100M; + u32 mac_clk_delay_10M; + u32 wakeup_enable; + u32 wakeup_control; + u32 reserved2[3]; + u32 sysreset_ctrl2; + u32 clk_sel2; + u32 clk_stop_ctrl2; + u32 freerun_counter; + u32 freerun_counter_ext; + u32 clk_duty_meas_ctrl; + u32 clk_duty_meas_res; + u32 reserved3[4]; + /* The next registers are not key-protected */ + struct ast2500_cpu2 { + u32 ctrl; + u32 base_addr[9]; + u32 cache_ctrl; + } cpu2; + u32 reserved4; + u32 d_pll_ext_param[3]; + u32 d2_pll_ext_param[3]; + u32 mh_pll_ext_param; + u32 reserved5; + u32 chip_id[2]; + u32 reserved6[2]; + u32 uart_clk_ctrl; + u32 reserved7[7]; + u32 pcie_config; + u32 mmio_decode; + u32 reloc_ctrl_decode[2]; + u32 mailbox_addr; + u32 shared_sram_decode[2]; + u32 bmc_rev_id; + u32 reserved8; + u32 bmc_device_id; + u32 reserved9[13]; + u32 clk_duty_sel; +}; + +/** + * ast_get_clk() - get a pointer to Clock Driver + * + * @devp, OUT - pointer to Clock Driver + * @return zero on success, error code (< 0) otherwise. + */ +int ast_get_clk(struct udevice **devp); + +/** + * ast_get_scu() - get a pointer to SCU registers + * + * @return pointer to struct ast2500_scu on success, ERR_PTR otherwise + */ +void *ast_get_scu(void); + +/** + * ast_scu_unlock() - unlock protected registers + * + * @scu, pointer to ast2500_scu + */ +void ast_scu_unlock(struct ast2500_scu *scu); + +/** + * ast_scu_lock() - lock protected registers + * + * @scu, pointer to ast2500_scu + */ +void ast_scu_lock(struct ast2500_scu *scu); + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_ARCH_SCU_AST2500_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/scu_ast2600.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/scu_ast2600.h new file mode 100644 index 000000000..a205fb1f7 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/scu_ast2600.h @@ -0,0 +1,338 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#ifndef _ASM_ARCH_SCU_AST2600_H +#define _ASM_ARCH_SCU_AST2600_H + +#define SCU_UNLOCK_KEY 0x1688a8a8 + +#define SCU_CLKGATE1_EMMC BIT(27) +#define SCU_CLKGATE1_MAC2 BIT(21) +#define SCU_CLKGATE1_MAC1 BIT(20) +#define SCU_CLKGATE1_USB_HUB BIT(14) +#define SCU_CLKGATE1_USB_HOST2 BIT(7) + +#define SCU_CLKGATE2_FSI BIT(30) +#define SCU_CLKGATE2_MAC4 BIT(21) +#define SCU_CLKGATE2_MAC3 BIT(20) +#define SCU_CLKGATE2_SDIO BIT(4) + +#define SCU_DRAM_HDSHK_SOC_INIT BIT(7) +#define SCU_DRAM_HDSHK_RDY BIT(6) + +#define SCU_CLKSRC1_ECC_RSA_DIV_MASK GENMASK(27, 26) +#define SCU_CLKSRC1_ECC_RSA_DIV_SHIFT 26 +#define SCU_CLKSRC1_PCLK_DIV_MASK GENMASK(25, 23) +#define SCU_CLKSRC1_PCLK_DIV_SHIFT 23 +#define SCU_CLKSRC1_BCLK_DIV_MASK GENMASK(22, 20) +#define SCU_CLKSRC1_BCLK_DIV_SHIFT 20 +#define SCU_CLKSRC1_ECC_RSA BIT(19) +#define SCU_CLKSRC1_MAC_DIV_MASK GENMASK(18, 16) +#define SCU_CLKSRC1_MAC_DIV_SHIFT 16 +#define SCU_CLKSRC1_EMMC_EN BIT(15) +#define SCU_CLKSRC1_EMMC_DIV_MASK GENMASK(14, 12) +#define SCU_CLKSRC1_EMMC_DIV_SHIFT 12 +#define SCU_CLKSRC1_EMMC BIT(11) + +#define SCU_CLKSRC2_RMII12 BIT(19) +#define SCU_CLKSRC2_RMII12_DIV_MASK GENMASK(18, 16) +#define SCU_CLKSRC2_RMII12_DIV_SHIFT 16 +#define SCU_CLKSRC2_UART5 BIT(14) + +#define SCU_CLKSRC4_SDIO_EN BIT(31) +#define SCU_CLKSRC4_SDIO_DIV_MASK GENMASK(30, 28) +#define SCU_CLKSRC4_SDIO_DIV_SHIFT 28 +#define SCU_CLKSRC4_MAC_DIV_MASK GENMASK(26, 24) +#define SCU_CLKSRC4_MAC_DIV_SHIFT 24 +#define SCU_CLKSRC4_RMII34_DIV_MASK GENMASK(18, 16) +#define SCU_CLKSRC4_RMII34_DIV_SHIFT 16 +#define SCU_CLKSRC4_PCLK_DIV_MASK GENMASK(11, 9) +#define SCU_CLKSRC4_PCLK_DIV_SHIFT 9 +#define SCU_CLKSRC4_SDIO BIT(8) +#define SCU_CLKSRC4_UART6 BIT(5) +#define SCU_CLKSRC4_UART4 BIT(3) +#define SCU_CLKSRC4_UART3 BIT(2) +#define SCU_CLKSRC4_UART2 BIT(1) +#define SCU_CLKSRC4_UART1 BIT(0) + +#define SCU_CLKSRC5_UART13 BIT(12) +#define SCU_CLKSRC5_UART12 BIT(11) +#define SCU_CLKSRC5_UART11 BIT(10) +#define SCU_CLKSRC5_UART10 BIT(9) +#define SCU_CLKSRC5_UART9 BIT(8) +#define SCU_CLKSRC5_UART8 BIT(7) +#define SCU_CLKSRC5_UART7 BIT(6) +#define SCU_CLKSRC5_HUXCLK_MASK GENMASK(5, 3) +#define SCU_CLKSRC5_HUXCLK_SHIFT 3 +#define SCU_CLKSRC5_UXCLK_MASK GENMASK(2, 0) +#define SCU_CLKSRC5_UXCLK_SHIFT 0 + +#define SCU_PINCTRL1_EMMC_MASK GENMASK(31, 24) +#define SCU_PINCTRL1_EMMC_SHIFT 24 + +#define SCU_PINCTRL16_MAC4_DRIVING_MASK GENMASK(3, 2) +#define SCU_PINCTRL16_MAC4_DRIVING_SHIFT 2 +#define SCU_PINCTRL16_MAC3_DRIVING_MASK GENMASK(1, 0) +#define SCU_PINCTRL16_MAC3_DRIVING_SHIFT 0 + +#define SCU_HWSTRAP1_CPU_AXI_CLK_RATIO BIT(16) +#define SCU_HWSTRAP1_VGA_MEM_MASK GENMASK(14, 13) +#define SCU_HWSTRAP1_VGA_MEM_SHIFT 13 +#define SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_MASK GENMASK(12, 11) +#define SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_SHIFT 11 +#define SCU_HWSTRAP1_CPU_FREQ_MASK GENMASK(10, 8) +#define SCU_HWSTRAP1_CPU_FREQ_SHIFT 8 +#define SCU_HWSTRAP1_MAC2_INTF BIT(7) +#define SCU_HWSTRAP1_MAC1_INTF BIT(6) + +#define SCU_EFUSE_DIS_DP BIT(17) +#define SCU_EFUSE_DIS_VGA BIT(14) +#define SCU_EFUSE_DIS_PCIE_EP BIT(13) +#define SCU_EFUSE_DIS_USB BIT(12) +#define SCU_EFUSE_DIS_RVAS BIT(10) +#define SCU_EFUSE_DIS_VIDEO_DEC BIT(9) +#define SCU_EFUSE_DIS_VIDEO BIT(8) +#define SCU_EFUSE_DIS_PCIE_RC BIT(7) +#define SCU_EFUSE_DIS_CM3 BIT(6) +#define SCU_EFUSE_DIS_CA7 BIT(5) + +#define SCU_PLL_RST BIT(25) +#define SCU_PLL_BYPASS BIT(24) +#define SCU_PLL_OFF BIT(23) +#define SCU_PLL_DIV_MASK GENMASK(22, 19) +#define SCU_PLL_DIV_SHIFT 19 +#define SCU_PLL_DENUM_MASK GENMASK(18, 13) +#define SCU_PLL_DENUM_SHIFT 13 +#define SCU_PLL_NUM_MASK GENMASK(12, 0) +#define SCU_PLL_NUM_SHIFT 0 + +#define SCU_UART_CLKGEN_N_MASK GENMASK(17, 8) +#define SCU_UART_CLKGEN_N_SHIFT 8 +#define SCU_UART_CLKGEN_R_MASK GENMASK(7, 0) +#define SCU_UART_CLKGEN_R_SHIFT 0 + +#define SCU_HUART_CLKGEN_N_MASK GENMASK(17, 8) +#define SCU_HUART_CLKGEN_N_SHIFT 8 +#define SCU_HUART_CLKGEN_R_MASK GENMASK(7, 0) +#define SCU_HUART_CLKGEN_R_SHIFT 0 + +#define SCU_MISC_CTRL1_UART5_DIV BIT(12) + +#ifndef __ASSEMBLY__ +struct ast2600_scu { + uint32_t prot_key1; /* 0x000 */ + uint32_t chip_id1; /* 0x004 */ + uint32_t rsv_0x08; /* 0x008 */ + uint32_t rsv_0x0c; /* 0x00C */ + uint32_t prot_key2; /* 0x010 */ + uint32_t chip_id2; /* 0x014 */ + uint32_t rsv_0x18[10]; /* 0x018 ~ 0x03C */ + uint32_t modrst_ctrl1; /* 0x040 */ + uint32_t modrst_clr1; /* 0x044 */ + uint32_t rsv_0x48; /* 0x048 */ + uint32_t rsv_0x4C; /* 0x04C */ + uint32_t modrst_ctrl2; /* 0x050 */ + uint32_t modrst_clr2; /* 0x054 */ + uint32_t rsv_0x58; /* 0x058 */ + uint32_t rsv_0x5C; /* 0x05C */ + uint32_t extrst_sel1; /* 0x060 */ + uint32_t sysrst_sts1_1; /* 0x064 */ + uint32_t sysrst_sts1_2; /* 0x068 */ + uint32_t sysrst_sts1_3; /* 0x06C */ + uint32_t extrst_sel2; /* 0x070 */ + uint32_t sysrst_sts2_1; /* 0x074 */ + uint32_t sysrst_sts2_2; /* 0x078 */ + uint32_t stsrst_sts3_2; /* 0x07C */ + uint32_t clkgate_ctrl1; /* 0x080 */ + uint32_t clkgate_clr1; /* 0x084 */ + uint32_t rsv_0x88; /* 0x088 */ + uint32_t rsv_0x8C; /* 0x08C */ + uint32_t clkgate_ctrl2; /* 0x090 */ + uint32_t clkgate_clr2; /* 0x094 */ + uint32_t rsv_0x98[10]; /* 0x098 ~ 0x0BC */ + uint32_t misc_ctrl1; /* 0x0C0 */ + uint32_t misc_ctrl2; /* 0x0C4 */ + uint32_t debug_ctrl1; /* 0x0C8 */ + uint32_t rsv_0xCC; /* 0x0CC */ + uint32_t misc_ctrl3; /* 0x0D0 */ + uint32_t misc_ctrl4; /* 0x0D4 */ + uint32_t debug_ctrl2; /* 0x0D8 */ + uint32_t rsv_0xdc[9]; /* 0x0DC ~ 0x0FC */ + uint32_t dram_hdshk; /* 0x100 */ + uint32_t soc_scratch[3]; /* 0x104 ~ 0x10C */ + uint32_t rsv_0x110[4]; /* 0x110 ~ 0x11C*/ + uint32_t cpu_scratch_wp; /* 0x120 */ + uint32_t rsv_0x124[23]; /* 0x124 */ + uint32_t smp_boot[12]; /* 0x180 */ + uint32_t cpu_scratch[20]; /* 0x1b0 */ + uint32_t hpll; /* 0x200 */ + uint32_t hpll_ext; /* 0x204 */ + uint32_t rsv_0x208[2]; /* 0x208 ~ 0x20C */ + uint32_t apll; /* 0x210 */ + uint32_t apll_ext; /* 0x214 */ + uint32_t rsv_0x218[2]; /* 0x218 ~ 0x21C */ + uint32_t mpll; /* 0x220 */ + uint32_t mpll_ext; /* 0x224 */ + uint32_t rsv_0x228[6]; /* 0x228 ~ 0x23C */ + uint32_t epll; /* 0x240 */ + uint32_t epll_ext; /* 0x244 */ + uint32_t rsv_0x248[6]; /* 0x248 ~ 0x25C */ + uint32_t dpll; /* 0x260 */ + uint32_t dpll_ext; /* 0x264 */ + uint32_t rsv_0x268[38]; /* 0x268 ~ 0x2FC */ + uint32_t clksrc1; /* 0x300 */ + uint32_t clksrc2; /* 0x304 */ + uint32_t clksrc3; /* 0x308 */ + uint32_t rsv_0x30c; /* 0x30C */ + uint32_t clksrc4; /* 0x310 */ + uint32_t clksrc5; /* 0x314 */ + uint32_t rsv_0x318[2]; /* 0x318 ~ 0x31C */ + uint32_t freq_counter_ctrl1; /* 0x320 */ + uint32_t freq_counter_cmp1; /* 0x324 */ + uint32_t rsv_0x328[2]; /* 0x328 ~ 0x32C */ + uint32_t freq_counter_ctrl2; /* 0x330 */ + uint32_t freq_counter_cmp2; /* 0x334 */ + uint32_t uart_clkgen; /* 0x338 */ + uint32_t huart_clkgen; /* 0x33C */ + uint32_t mac12_clk_delay; /* 0x340 */ + uint32_t rsv_0x344; /* 0x344 */ + uint32_t mac12_clk_delay_100M; /* 0x348 */ + uint32_t mac12_clk_delay_10M; /* 0x34C */ + uint32_t mac34_clk_delay; /* 0x350 */ + uint32_t rsv_0x354; /* 0x354 */ + uint32_t mac34_clk_delay_100M; /* 0x358 */ + uint32_t mac34_clk_delay_10M; /* 0x35C */ + uint32_t clkduty_meas_ctrl; /* 0x360 */ + uint32_t clkduty1; /* 0x364 */ + uint32_t clkduty2; /* 0x368 */ + uint32_t clkduty_meas_res; /* 0x36C */ + uint32_t clkduty_meas_ctrl2; /* 0x370 */ + uint32_t clkduty3; /* 0x374 */ + uint32_t rsv_0x378[34]; /* 0x378 ~ 0x3FC */ + uint32_t pinmux1; /* 0x400 */ + uint32_t pinmux2; /* 0x404 */ + uint32_t rsv_0x408; /* 0x408 */ + uint32_t pinmux3; /* 0x40C */ + uint32_t pinmux4; /* 0x410 */ + uint32_t pinmux5; /* 0x414 */ + uint32_t pinmux6; /* 0x418 */ + uint32_t pinmux7; /* 0x41C */ + uint32_t rsv_0x420[4]; /* 0x420 ~ 0x42C */ + uint32_t pinmux8; /* 0x430 */ + uint32_t pinmux9; /* 0x434 */ + uint32_t pinmux10; /* 0x438 */ + uint32_t rsv_0x43c; /* 0x43C */ + uint32_t pinmux12; /* 0x440 */ + uint32_t pinmux13; /* 0x444 */ + uint32_t rsv_0x448[2]; /* 0x448 ~ 0x44C */ + uint32_t pinmux14; /* 0x450 */ + uint32_t pinmux15; /* 0x454 */ + uint32_t pinmux16; /* 0x458 */ + uint32_t rsv_0x45c[21]; /* 0x45C ~ 0x4AC */ + uint32_t pinmux17; /* 0x4B0 */ + uint32_t pinmux18; /* 0x4B4 */ + uint32_t pinmux19; /* 0x4B8 */ + uint32_t pinmux20; /* 0x4BC */ + uint32_t rsv_0x4c0[5]; /* 0x4C0 ~ 0x4D0 */ + uint32_t pinmux22; /* 0x4D4 */ + uint32_t pinmux23; /* 0x4D8 */ + uint32_t rsv_0x4dc[9]; /* 0x4DC ~ 0x4FC */ + uint32_t hwstrap1; /* 0x500 */ + uint32_t hwstrap_clr1; /* 0x504 */ + uint32_t hwstrap_prot1; /* 0x508 */ + uint32_t rsv_0x50c; /* 0x50C */ + uint32_t hwstrap2; /* 0x510 */ + uint32_t hwstrap_clr2; /* 0x514 */ + uint32_t hwstrap_prot2; /* 0x518 */ + uint32_t rsv_0x51c; /* 0x51C */ + uint32_t rng_ctrl; /* 0x520 */ + uint32_t rng_data; /* 0x524 */ + uint32_t rsv_0x528[6]; /* 0x528 ~ 0x53C */ + uint32_t pwr_save_wakeup_en1; /* 0x540 */ + uint32_t pwr_save_wakeup_ctrl1; /* 0x544 */ + uint32_t rsv_0x548[2]; /* 0x548 */ + uint32_t pwr_save_wakeup_en2; /* 0x550 */ + uint32_t pwr_save_wakeup_ctrl2; /* 0x554 */ + uint32_t rsv_0x558[2]; /* 0x558 */ + uint32_t intr1_ctrl_sts; /* 0x560 */ + uint32_t rsv_0x564[3]; /* 0x564 */ + uint32_t intr2_ctrl_sts; /* 0x570 */ + uint32_t rsv_0x574[7]; /* 0x574 ~ 0x58C */ + uint32_t otp_ctrl; /* 0x590 */ + uint32_t efuse; /* 0x594 */ + uint32_t rsv_0x598[6]; /* 0x598 */ + uint32_t chip_unique_id[8]; /* 0x5B0 */ + uint32_t rsv_0x5e0[8]; /* 0x5E0 ~ 0x5FC */ + uint32_t disgpio_in_pull_down0; /* 0x610 */ + uint32_t disgpio_in_pull_down1; /* 0x614 */ + uint32_t disgpio_in_pull_down2; /* 0x618 */ + uint32_t disgpio_in_pull_down3; /* 0x61C */ + uint32_t rsv_0x620[4]; /* 0x620 ~ 0x62C */ + uint32_t disgpio_in_pull_down4; /* 0x630 */ + uint32_t disgpio_in_pull_down5; /* 0x634 */ + uint32_t disgpio_in_pull_down6; /* 0x638 */ + uint32_t rsv_0x63c[5]; /* 0x63C ~ 0x64C */ + uint32_t sli_driving_strength; /* 0x650 */ + uint32_t rsv_0x654[107]; /* 0x654 ~ 0x7FC */ + uint32_t ca7_ctrl1; /* 0x800 */ + uint32_t ca7_ctrl2; /* 0x804 */ + uint32_t ca7_ctrl3; /* 0x808 */ + uint32_t ca7_ctrl4; /* 0x80C */ + uint32_t rsv_0x810[4]; /* 0x810 ~ 0x81C */ + uint32_t ca7_parity_chk; /* 0x820 */ + uint32_t ca7_parity_clr; /* 0x824 */ + uint32_t rsv_0x828[118]; /* 0x828 ~ 0x9FC */ + uint32_t cm3_ctrl; /* 0xA00 */ + uint32_t cm3_base; /* 0xA04 */ + uint32_t cm3_imem_addr; /* 0xA08 */ + uint32_t cm3_dmem_addr; /* 0xA0C */ + uint32_t rsv_0xa10[12]; /* 0xA10 ~ 0xA3C */ + uint32_t cm3_cache_area; /* 0xA40 */ + uint32_t cm3_cache_invd_ctrl; /* 0xA44 */ + uint32_t cm3_cache_func_ctrl; /* 0xA48 */ + uint32_t rsv_0xa4c[108]; /* 0xA4C ~ 0xBFC */ + uint32_t pci_cfg[3]; /* 0xC00 */ + uint32_t rsv_0xc0c[5]; /* 0xC0C ~ 0xC1C */ + uint32_t pcie_cfg; /* 0xC20 */ + uint32_t mmio_decode; /* 0xC24 */ + uint32_t reloc_ctrl_decode[2]; /* 0xC28 */ + uint32_t rsv_0xc30[4]; /* 0xC30 ~ 0xC3C */ + uint32_t mbox_decode; /* 0xC40 */ + uint32_t shared_sram_decode[2]; /* 0xC44 */ + uint32_t bmc_rev_id; /* 0xC4C */ + uint32_t rsv_0xc50[5]; /* 0xC50 ~ 0xC60 */ + uint32_t bmc_device_id; /* 0xC64 */ + uint32_t rsv_0xc68[102]; /* 0xC68 ~ 0xDFC */ + uint32_t vga_scratch1; /* 0xE00 */ + uint32_t vga_scratch2; /* 0xE04 */ + uint32_t vga_scratch3; /* 0xE08 */ + uint32_t vga_scratch4; /* 0xE0C */ + uint32_t rsv_0xe10[4]; /* 0xE10 ~ 0xE1C */ + uint32_t vga_scratch5; /* 0xE20 */ + uint32_t vga_scratch6; /* 0xE24 */ + uint32_t vga_scratch7; /* 0xE28 */ + uint32_t vga_scratch8; /* 0xE2C */ + uint32_t rsv_0xe30[52]; /* 0xE30 ~ 0xEFC */ + uint32_t wr_prot1; /* 0xF00 */ + uint32_t wr_prot2; /* 0xF04 */ + uint32_t wr_prot3; /* 0xF08 */ + uint32_t wr_prot4; /* 0xF0C */ + uint32_t wr_prot5; /* 0xF10 */ + uint32_t wr_prot6; /* 0xF18 */ + uint32_t wr_prot7; /* 0xF1C */ + uint32_t wr_prot8; /* 0xF20 */ + uint32_t wr_prot9; /* 0xF24 */ + uint32_t rsv_0xf28[2]; /* 0xF28 ~ 0xF2C */ + uint32_t wr_prot10; /* 0xF30 */ + uint32_t wr_prot11; /* 0xF34 */ + uint32_t wr_prot12; /* 0xF38 */ + uint32_t wr_prot13; /* 0xF3C */ + uint32_t wr_prot14; /* 0xF40 */ + uint32_t rsv_0xf44; /* 0xF44 */ + uint32_t wr_prot15; /* 0xF48 */ + uint32_t rsv_0xf4c[5]; /* 0xF4C ~ 0xF5C */ + uint32_t wr_prot16; /* 0xF60 */ +}; +#endif +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/sdram_ast2500.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/sdram_ast2500.h new file mode 100644 index 000000000..0bc551fbe --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/sdram_ast2500.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2016 Google, Inc + */ +#ifndef _ASM_ARCH_SDRAM_AST2500_H +#define _ASM_ARCH_SDRAM_AST2500_H + +#define SDRAM_UNLOCK_KEY 0xfc600309 +#define SDRAM_VIDEO_UNLOCK_KEY 0x2003000f + +#define SDRAM_PCR_CKE_EN (1 << 0) +#define SDRAM_PCR_AUTOPWRDN_EN (1 << 1) +#define SDRAM_PCR_CKE_DELAY_SHIFT 4 +#define SDRAM_PCR_CKE_DELAY_MASK 7 +#define SDRAM_PCR_RESETN_DIS (1 << 7) +#define SDRAM_PCR_ODT_EN (1 << 8) +#define SDRAM_PCR_ODT_AUTO_ON (1 << 10) +#define SDRAM_PCR_ODT_EXT_EN (1 << 11) +#define SDRAM_PCR_TCKE_PW_SHIFT 12 +#define SDRAM_PCR_TCKE_PW_MASK 7 +#define SDRAM_PCR_RGAP_CTRL_EN (1 << 15) +#define SDRAM_PCR_MREQI_DIS (1 << 17) + +/* Fixed priority DRAM Requests mask */ +#define SDRAM_REQ_VGA_HW_CURSOR (1 << 0) +#define SDRAM_REQ_VGA_TEXT_CG_FONT (1 << 1) +#define SDRAM_REQ_VGA_TEXT_ASCII (1 << 2) +#define SDRAM_REQ_VGA_CRT (1 << 3) +#define SDRAM_REQ_SOC_DC_CURSOR (1 << 4) +#define SDRAM_REQ_SOC_DC_OCD (1 << 5) +#define SDRAM_REQ_SOC_DC_CRT (1 << 6) +#define SDRAM_REQ_VIDEO_HIPRI_WRITE (1 << 7) +#define SDRAM_REQ_USB20_EHCI1 (1 << 8) +#define SDRAM_REQ_USB20_EHCI2 (1 << 9) +#define SDRAM_REQ_CPU (1 << 10) +#define SDRAM_REQ_AHB2 (1 << 11) +#define SDRAM_REQ_AHB (1 << 12) +#define SDRAM_REQ_MAC0 (1 << 13) +#define SDRAM_REQ_MAC1 (1 << 14) +#define SDRAM_REQ_PCIE (1 << 16) +#define SDRAM_REQ_XDMA (1 << 17) +#define SDRAM_REQ_ENCRYPTION (1 << 18) +#define SDRAM_REQ_VIDEO_FLAG (1 << 21) +#define SDRAM_REQ_VIDEO_LOW_PRI_WRITE (1 << 28) +#define SDRAM_REQ_2D_RW (1 << 29) +#define SDRAM_REQ_MEMCHECK (1 << 30) + +#define SDRAM_ICR_RESET_ALL (1 << 31) + +#define SDRAM_CONF_CAP_SHIFT 0 +#define SDRAM_CONF_CAP_MASK 3 +#define SDRAM_CONF_DDR4 (1 << 4) +#define SDRAM_CONF_SCRAMBLE (1 << 8) +#define SDRAM_CONF_SCRAMBLE_PAT2 (1 << 9) +#define SDRAM_CONF_CACHE_EN (1 << 10) +#define SDRAM_CONF_CACHE_INIT_EN (1 << 12) +#define SDRAM_CONF_DUALX8 (1 << 13) +#define SDRAM_CONF_CACHE_INIT_DONE (1 << 19) + +#define SDRAM_CONF_CAP_128M 0 +#define SDRAM_CONF_CAP_256M 1 +#define SDRAM_CONF_CAP_512M 2 +#define SDRAM_CONF_CAP_1024M 3 + +#define SDRAM_MISC_DDR4_TREFRESH (1 << 3) + +#define SDRAM_PHYCTRL0_INIT (1 << 0) +#define SDRAM_PHYCTRL0_AUTO_UPDATE (1 << 1) +#define SDRAM_PHYCTRL0_NRST (1 << 2) + +#define SDRAM_REFRESH_CYCLES_SHIFT 0 +#define SDRAM_REFRESH_CYCLES_MASK 0xf +#define SDRAM_REFRESH_ZQCS_EN (1 << 7) +#define SDRAM_REFRESH_PERIOD_SHIFT 8 +#define SDRAM_REFRESH_PERIOD_MASK 0xf + +#define SDRAM_TEST_LEN_SHIFT 4 +#define SDRAM_TEST_LEN_MASK 0xfffff +#define SDRAM_TEST_START_ADDR_SHIFT 24 +#define SDRAM_TEST_START_ADDR_MASK 0x3f + +#define SDRAM_TEST_EN (1 << 0) +#define SDRAM_TEST_MODE_SHIFT 1 +#define SDRAM_TEST_MODE_MASK 3 +#define SDRAM_TEST_MODE_WO 0 +#define SDRAM_TEST_MODE_RB 1 +#define SDRAM_TEST_MODE_RW 2 +#define SDRAM_TEST_GEN_MODE_SHIFT 3 +#define SDRAM_TEST_GEN_MODE_MASK 7 +#define SDRAM_TEST_TWO_MODES (1 << 6) +#define SDRAM_TEST_ERRSTOP (1 << 7) +#define SDRAM_TEST_DONE (1 << 12) +#define SDRAM_TEST_FAIL (1 << 13) + +#define SDRAM_AC_TRFC_SHIFT 0 +#define SDRAM_AC_TRFC_MASK 0xff + +#ifndef __ASSEMBLY__ + +struct ast2500_sdrammc_regs { + u32 protection_key; + u32 config; + u32 gm_protection_key; + u32 refresh_timing; + u32 ac_timing[3]; + u32 misc_control; + u32 mr46_mode_setting; + u32 mr5_mode_setting; + u32 mode_setting_control; + u32 mr02_mode_setting; + u32 mr13_mode_setting; + u32 power_control; + u32 req_limit_mask; + u32 pri_group_setting; + u32 max_grant_len[4]; + u32 intr_ctrl; + u32 ecc_range_ctrl; + u32 first_ecc_err_addr; + u32 last_ecc_err_addr; + u32 phy_ctrl[4]; + u32 ecc_test_ctrl; + u32 test_addr; + u32 test_fail_dq_bit; + u32 test_init_val; + u32 phy_debug_ctrl; + u32 phy_debug_data; + u32 reserved1[30]; + u32 scu_passwd; + u32 reserved2[7]; + u32 scu_mpll; + u32 reserved3[19]; + u32 scu_hwstrap; +}; + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_ARCH_SDRAM_AST2500_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h new file mode 100644 index 000000000..d2408c002 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#ifndef _ASM_ARCH_SDRAM_AST2600_H +#define _ASM_ARCH_SDRAM_AST2600_H + +/* keys for unlocking HW */ +#define SDRAM_UNLOCK_KEY 0xFC600309 +#define SDRAM_VIDEO_UNLOCK_KEY 0x00440003 + +/* Fixed priority DRAM Requests mask */ +#define REQ_PRI_VGA_HW_CURSOR_R 0 +#define REQ_PRI_VGA_CRT_R 1 +#define REQ_PRI_SOC_DISPLAY_CTRL_R 2 +#define REQ_PRI_PCIE_BUS1_RW 3 +#define REQ_PRI_VIDEO_HIGH_PRI_W 4 +#define REQ_PRI_CPU_RW 5 +#define REQ_PRI_SLI_RW 6 +#define REQ_PRI_PCIE_BUS2_RW 7 +#define REQ_PRI_USB2_0_HUB_EHCI1_DMA_RW 8 +#define REQ_PRI_USB2_0_DEV_EHCI2_DMA_RW 9 +#define REQ_PRI_USB1_1_UHCI_HOST_RW 10 +#define REQ_PRI_AHB_BUS_RW 11 +#define REQ_PRI_CM3_DATA_RW 12 +#define REQ_PRI_CM3_INST_R 13 +#define REQ_PRI_MAC0_DMA_RW 14 +#define REQ_PRI_MAC1_DMA_RW 15 +#define REQ_PRI_SDIO_DMA_RW 16 +#define REQ_PRI_PILOT_ENGINE_RW 17 +#define REQ_PRI_XDMA1_RW 18 +#define REQ_PRI_MCTP1_RW 19 +#define REQ_PRI_VIDEO_FLAG_RW 20 +#define REQ_PRI_VIDEO_LOW_PRI_W 21 +#define REQ_PRI_2D_ENGINE_DATA_RW 22 +#define REQ_PRI_ENC_ENGINE_RW 23 +#define REQ_PRI_MCTP2_RW 24 +#define REQ_PRI_XDMA2_RW 25 +#define REQ_PRI_ECC_RSA_RW 26 + +#define MCR30_RESET_DLL_DELAY_EN BIT(4) +#define MCR30_MODE_REG_SEL_SHIFT 1 +#define MCR30_MODE_REG_SEL_MASK GENMASK(3, 1) +#define MCR30_SET_MODE_REG BIT(0) + +#define MCR30_SET_MR(mr) ((mr << MCR30_MODE_REG_SEL_SHIFT) | MCR30_SET_MODE_REG) + +#define MCR34_SELF_REFRESH_STATUS_MASK GENMASK(30, 28) + +#define MCR34_ODT_DELAY_SHIFT 12 +#define MCR34_ODT_DELAY_MASK GENMASK(15, 12) +#define MCR34_ODT_EXT_SHIFT 10 +#define MCR34_ODT_EXT_MASK GENMASK(11, 10) +#define MCR34_ODT_AUTO_ON BIT(9) +#define MCR34_ODT_EN BIT(8) +#define MCR34_RESETN_DIS BIT(7) +#define MCR34_MREQI_DIS BIT(6) +#define MCR34_MREQ_BYPASS_DIS BIT(5) +#define MCR34_RGAP_CTRL_EN BIT(4) +#define MCR34_CKE_OUT_IN_SELF_REF_DIS BIT(3) +#define MCR34_FOURCE_SELF_REF_EN BIT(2) +#define MCR34_AUTOPWRDN_EN BIT(1) +#define MCR34_CKE_EN BIT(0) + +#define MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT 16 +#define MCR38_RW_MAX_GRANT_CNT_RQ_MASK GENMASK(20, 16) + +/* default request queued limitation mask (0xFFBBFFF4) */ +#define MCR3C_DEFAULT_MASK \ + ~(REQ_PRI_VGA_HW_CURSOR_R | REQ_PRI_VGA_CRT_R | REQ_PRI_PCIE_BUS1_RW | \ + REQ_PRI_XDMA1_RW | REQ_PRI_2D_ENGINE_DATA_RW) + +#define MCR50_RESET_ALL_INTR BIT(31) +#define SDRAM_CONF_ECC_AUTO_SCRUBBING BIT(9) +#define SDRAM_CONF_SCRAMBLE BIT(8) +#define SDRAM_CONF_ECC_EN BIT(7) +#define SDRAM_CONF_DUALX8 BIT(5) +#define SDRAM_CONF_DDR4 BIT(4) +#define SDRAM_CONF_VGA_SIZE_SHIFT 2 +#define SDRAM_CONF_VGA_SIZE_MASK GENMASK(3, 2) +#define SDRAM_CONF_CAP_SHIFT 0 +#define SDRAM_CONF_CAP_MASK GENMASK(1, 0) + +#define SDRAM_CONF_CAP_256M 0 +#define SDRAM_CONF_CAP_512M 1 +#define SDRAM_CONF_CAP_1024M 2 +#define SDRAM_CONF_CAP_2048M 3 +#define SDRAM_CONF_ECC_SETUP (SDRAM_CONF_ECC_AUTO_SCRUBBING | SDRAM_CONF_ECC_EN) + +#define SDRAM_MISC_DDR4_TREFRESH (1 << 3) + +#define SDRAM_PHYCTRL0_PLL_LOCKED BIT(4) +#define SDRAM_PHYCTRL0_NRST BIT(2) +#define SDRAM_PHYCTRL0_INIT BIT(0) + +/* MCR0C */ +#define SDRAM_REFRESH_PERIOD_ZQCS_SHIFT 16 +#define SDRAM_REFRESH_PERIOD_ZQCS_MASK GENMASK(31, 16) +#define SDRAM_REFRESH_PERIOD_SHIFT 8 +#define SDRAM_REFRESH_PERIOD_MASK GENMASK(15, 8) +#define SDRAM_REFRESH_ZQCS_EN BIT(7) +#define SDRAM_RESET_DLL_ZQCL_EN BIT(6) +#define SDRAM_LOW_PRI_REFRESH_EN BIT(5) +#define SDRAM_FORCE_PRECHARGE_EN BIT(4) +#define SDRAM_REFRESH_EN BIT(0) + +#define SDRAM_TEST_LEN_SHIFT 4 +#define SDRAM_TEST_LEN_MASK 0xfffff +#define SDRAM_TEST_START_ADDR_SHIFT 24 +#define SDRAM_TEST_START_ADDR_MASK 0x3f + +#define SDRAM_TEST_EN (1 << 0) +#define SDRAM_TEST_MODE_SHIFT 1 +#define SDRAM_TEST_MODE_MASK (0x3 << SDRAM_TEST_MODE_SHIFT) +#define SDRAM_TEST_MODE_WO (0x0 << SDRAM_TEST_MODE_SHIFT) +#define SDRAM_TEST_MODE_RB (0x1 << SDRAM_TEST_MODE_SHIFT) +#define SDRAM_TEST_MODE_RW (0x2 << SDRAM_TEST_MODE_SHIFT) + +#define SDRAM_TEST_GEN_MODE_SHIFT 3 +#define SDRAM_TEST_GEN_MODE_MASK (7 << SDRAM_TEST_GEN_MODE_SHIFT) +#define SDRAM_TEST_TWO_MODES (1 << 6) +#define SDRAM_TEST_ERRSTOP (1 << 7) +#define SDRAM_TEST_DONE (1 << 12) +#define SDRAM_TEST_FAIL (1 << 13) + +#define SDRAM_AC_TRFC_SHIFT 0 +#define SDRAM_AC_TRFC_MASK 0xff + +#define SDRAM_ECC_RANGE_ADDR_MASK GENMASK(30, 20) +#define SDRAM_ECC_RANGE_ADDR_SHIFT 20 + +#ifndef __ASSEMBLY__ +struct ast2600_sdrammc_regs { + u32 protection_key; /* offset 0x00 */ + u32 config; /* offset 0x04 */ + u32 gm_protection_key; /* offset 0x08 */ + u32 refresh_timing; /* offset 0x0C */ + u32 ac_timing[4]; /* offset 0x10 ~ 0x1C */ + u32 mr01_mode_setting; /* offset 0x20 */ + u32 mr23_mode_setting; /* offset 0x24 */ + u32 mr45_mode_setting; /* offset 0x28 */ + u32 mr6_mode_setting; /* offset 0x2C */ + u32 mode_setting_control; /* offset 0x30 */ + u32 power_ctrl; /* offset 0x34 */ + u32 arbitration_ctrl; /* offset 0x38 */ + u32 req_limit_mask; /* offset 0x3C */ + u32 max_grant_len[4]; /* offset 0x40 ~ 0x4C */ + u32 intr_ctrl; /* offset 0x50 */ + u32 ecc_range_ctrl; /* offset 0x54 */ + u32 first_ecc_err_addr; /* offset 0x58 */ + u32 last_ecc_err_addr; /* offset 0x5C */ + u32 phy_ctrl[4]; /* offset 0x60 ~ 0x6C */ + u32 ecc_test_ctrl; /* offset 0x70 */ + u32 test_addr; /* offset 0x74 */ + u32 test_fail_dq_bit; /* offset 0x78 */ + u32 test_init_val; /* offset 0x7C */ + u32 req_input_ctrl; /* offset 0x80 */ + u32 req_high_pri_ctrl; /* offset 0x84 */ + u32 reserved0[6]; /* offset 0x88 ~ 0x9C */ +}; +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_ARCH_SDRAM_AST2600_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/timer.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/timer.h new file mode 100644 index 000000000..ff24e2f86 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/timer.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2016 Google, Inc + */ +#ifndef _ASM_ARCH_TIMER_H +#define _ASM_ARCH_TIMER_H + +/* Each timer has 4 control bits in ctrl1 register. + * Timer1 uses bits 0:3, Timer2 uses bits 4:7 and so on, + * such that timer X uses bits (4 * X - 4):(4 * X - 1) + * If the timer does not support PWM, bit 4 is reserved. + */ +#define AST_TMC_EN (1 << 0) +#define AST_TMC_1MHZ (1 << 1) +#define AST_TMC_OVFINTR (1 << 2) +#define AST_TMC_PWM (1 << 3) + +/* Timers are counted from 1 in the datasheet. */ +#define AST_TMC_CTRL1_SHIFT(n) (4 * ((n) - 1)) + +#define AST_TMC_RATE (1000*1000) + +#ifndef __ASSEMBLY__ + +/* + * All timers share control registers, which makes it harder to make them + * separate devices. Since only one timer is needed at the moment, making + * it this just one device. + */ + +struct ast_timer_counter { + u32 status; + u32 reload_val; + u32 match1; + u32 match2; +}; + +struct ast_timer { + struct ast_timer_counter timers1[3]; + u32 ctrl1; + u32 ctrl2; +#ifdef CONFIG_ASPEED_AST2500 + u32 ctrl3; + u32 ctrl1_clr; +#else + u32 reserved[2]; +#endif + struct ast_timer_counter timers2[5]; +}; + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_ARCH_TIMER_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/wdt.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/wdt.h new file mode 100644 index 000000000..fb04d41d3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/wdt.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Google, Inc + */ + +#ifndef _ASM_ARCH_WDT_H +#define _ASM_ARCH_WDT_H + +#define WDT_BASE 0x1e785000 + +/* + * Special value that needs to be written to counter_restart register to + * (re)start the timer + */ +#define WDT_COUNTER_RESTART_VAL 0x4755 + +/* Control register */ +#define WDT_CTRL_RESET_MODE_SHIFT 5 +#define WDT_CTRL_RESET_MODE_MASK 3 + +#define WDT_CTRL_EN (1 << 0) +#define WDT_CTRL_RESET (1 << 1) +#define WDT_CTRL_CLK1MHZ (1 << 4) +#define WDT_CTRL_2ND_BOOT (1 << 7) + +/* Values for Reset Mode */ +#define WDT_CTRL_RESET_SOC 0 +#define WDT_CTRL_RESET_CHIP 1 +#define WDT_CTRL_RESET_CPU 2 +#define WDT_CTRL_RESET_MASK 3 + +/* Reset Mask register */ +#define WDT_RESET_ARM (1 << 0) +#define WDT_RESET_COPROC (1 << 1) +#define WDT_RESET_SDRAM (1 << 2) +#define WDT_RESET_AHB (1 << 3) +#define WDT_RESET_I2C (1 << 4) +#define WDT_RESET_MAC1 (1 << 5) +#define WDT_RESET_MAC2 (1 << 6) +#define WDT_RESET_GCRT (1 << 7) +#define WDT_RESET_USB20 (1 << 8) +#define WDT_RESET_USB11_HOST (1 << 9) +#define WDT_RESET_USB11_EHCI2 (1 << 10) +#define WDT_RESET_VIDEO (1 << 11) +#define WDT_RESET_HAC (1 << 12) +#define WDT_RESET_LPC (1 << 13) +#define WDT_RESET_SDSDIO (1 << 14) +#define WDT_RESET_MIC (1 << 15) +#define WDT_RESET_CRT2C (1 << 16) +#define WDT_RESET_PWM (1 << 17) +#define WDT_RESET_PECI (1 << 18) +#define WDT_RESET_JTAG (1 << 19) +#define WDT_RESET_ADC (1 << 20) +#define WDT_RESET_GPIO (1 << 21) +#define WDT_RESET_MCTP (1 << 22) +#define WDT_RESET_XDMA (1 << 23) +#define WDT_RESET_SPI (1 << 24) +#define WDT_RESET_MISC (1 << 25) + +#define WDT_RESET_DEFAULT \ + (WDT_RESET_ARM | WDT_RESET_COPROC | WDT_RESET_I2C | \ + WDT_RESET_MAC1 | WDT_RESET_MAC2 | WDT_RESET_GCRT | \ + WDT_RESET_USB20 | WDT_RESET_USB11_HOST | WDT_RESET_USB11_EHCI2 | \ + WDT_RESET_VIDEO | WDT_RESET_HAC | WDT_RESET_LPC | \ + WDT_RESET_SDSDIO | WDT_RESET_MIC | WDT_RESET_CRT2C | \ + WDT_RESET_PWM | WDT_RESET_PECI | WDT_RESET_JTAG | \ + WDT_RESET_ADC | WDT_RESET_GPIO | WDT_RESET_MISC) + +#ifndef __ASSEMBLY__ +struct ast_wdt { + u32 counter_status; + u32 counter_reload_val; + u32 counter_restart; + u32 ctrl; + u32 timeout_status; + u32 clr_timeout_status; + u32 reset_width; + /* On pre-ast2500 SoCs this register is reserved. */ + u32 reset_mask; +}; + +/** + * Given flags parameter passed to wdt_reset or wdt_start uclass functions, + * gets Reset Mode value from it. + * + * @flags: flags parameter passed into wdt_reset or wdt_start + * @return Reset Mode value + */ +u32 ast_reset_mode_from_flags(ulong flags); + +/** + * Given flags parameter passed to wdt_reset or wdt_start uclass functions, + * gets Reset Mask value from it. Reset Mask is only supported on ast2500 + * + * @flags: flags parameter passed into wdt_reset or wdt_start + * @return Reset Mask value + */ +u32 ast_reset_mask_from_flags(ulong flags); + +/** + * Given Reset Mask and Reset Mode values, converts them to flags, + * suitable for passing into wdt_start or wdt_reset uclass functions. + * + * On ast2500 Reset Mask is 25 bits wide and Reset Mode is 2 bits wide, so they + * can both be packed into single 32 bits wide value. + * + * @reset_mode: Reset Mode + * @reset_mask: Reset Mask + */ +ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask); +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_ARCH_WDT_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/wdt_ast2600.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/wdt_ast2600.h new file mode 100644 index 000000000..96e8ca07e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/wdt_ast2600.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2020 Aspeed Technology Inc. + */ + +#ifndef _ASM_ARCH_WDT_AST2600_H +#define _ASM_ARCH_WDT_AST2600_H + +#define WDT_BASE 0x1e785000 + +/* + * Special value that needs to be written to counter_restart register to + * (re)start the timer + */ +#define WDT_COUNTER_RESTART_VAL 0x4755 + +/* reset mode */ +#define WDT_RESET_MODE_SOC 0 +#define WDT_RESET_MODE_CHIP 1 +#define WDT_RESET_MODE_CPU 2 + +/* bit-fields of WDT control register */ +#define WDT_CTRL_2ND_BOOT BIT(7) +#define WDT_CTRL_RESET_MODE_MASK GENMASK(6, 5) +#define WDT_CTRL_RESET_MODE_SHIFT 5 +#define WDT_CTRL_CLK1MHZ BIT(4) +#define WDT_CTRL_RESET BIT(1) +#define WDT_CTRL_EN BIT(0) + +/* bit-fields of WDT reset mask1 register */ +#define WDT_RESET_MASK1_RVAS BIT(25) +#define WDT_RESET_MASK1_GPIO1 BIT(24) +#define WDT_RESET_MASK1_XDMA2 BIT(23) +#define WDT_RESET_MASK1_XDMA1 BIT(22) +#define WDT_RESET_MASK1_MCTP2 BIT(21) +#define WDT_RESET_MASK1_MCTP1 BIT(20) +#define WDT_RESET_MASK1_JTAG1 BIT(19) +#define WDT_RESET_MASK1_SD_SDIO1 BIT(18) +#define WDT_RESET_MASK1_MAC2 BIT(17) +#define WDT_RESET_MASK1_MAC1 BIT(16) +#define WDT_RESET_MASK1_GPMCU BIT(15) +#define WDT_RESET_MASK1_DPMCU BIT(14) +#define WDT_RESET_MASK1_DP BIT(13) +#define WDT_RESET_MASK1_HAC BIT(12) +#define WDT_RESET_MASK1_VIDEO BIT(11) +#define WDT_RESET_MASK1_CRT BIT(10) +#define WDT_RESET_MASK1_GCRT BIT(9) +#define WDT_RESET_MASK1_USB11_UHCI BIT(8) +#define WDT_RESET_MASK1_USB_PORTA BIT(7) +#define WDT_RESET_MASK1_USB_PORTB BIT(6) +#define WDT_RESET_MASK1_COPROC BIT(5) +#define WDT_RESET_MASK1_SOC BIT(4) +#define WDT_RESET_MASK1_SLI BIT(3) +#define WDT_RESET_MASK1_AHB BIT(2) +#define WDT_RESET_MASK1_SDRAM BIT(1) +#define WDT_RESET_MASK1_ARM BIT(0) + +/* bit-fields of WDT reset mask2 register */ +#define WDT_RESET_MASK2_ESPI BIT(26) +#define WDT_RESET_MASK2_I3C_BUS8 BIT(25) +#define WDT_RESET_MASK2_I3C_BUS7 BIT(24) +#define WDT_RESET_MASK2_I3C_BUS6 BIT(23) +#define WDT_RESET_MASK2_I3C_BUS5 BIT(22) +#define WDT_RESET_MASK2_I3C_BUS4 BIT(21) +#define WDT_RESET_MASK2_I3C_BUS3 BIT(20) +#define WDT_RESET_MASK2_I3C_BUS2 BIT(19) +#define WDT_RESET_MASK2_I3C_BUS1 BIT(18) +#define WDT_RESET_MASK2_I3C_GLOBAL BIT(17) +#define WDT_RESET_MASK2_I2C BIT(16) +#define WDT_RESET_MASK2_FSI BIT(15) +#define WDT_RESET_MASK2_ADC BIT(14) +#define WDT_RESET_MASK2_PWM BIT(13) +#define WDT_RESET_MASK2_PECI BIT(12) +#define WDT_RESET_MASK2_LPC BIT(11) +#define WDT_RESET_MASK2_MDC_MDIO BIT(10) +#define WDT_RESET_MASK2_GPIO2 BIT(9) +#define WDT_RESET_MASK2_JTAG2 BIT(8) +#define WDT_RESET_MASK2_SD_SDIO2 BIT(7) +#define WDT_RESET_MASK2_MAC4 BIT(6) +#define WDT_RESET_MASK2_MAC3 BIT(5) +#define WDT_RESET_MASK2_SOC BIT(4) +#define WDT_RESET_MASK2_SLI2 BIT(3) +#define WDT_RESET_MASK2_AHB2 BIT(2) +#define WDT_RESET_MASK2_SPI1_SPI2 BIT(1) +#define WDT_RESET_MASK2_ARM BIT(0) + +#define WDT_RESET_MASK1_DEFAULT \ + (WDT_RESET_MASK1_RVAS | WDT_RESET_MASK1_GPIO1 | \ + WDT_RESET_MASK1_JTAG1 | WDT_RESET_MASK1_SD_SDIO1 | \ + WDT_RESET_MASK1_MAC2 | WDT_RESET_MASK1_MAC1 | \ + WDT_RESET_MASK1_HAC | WDT_RESET_MASK1_VIDEO | \ + WDT_RESET_MASK1_CRT | WDT_RESET_MASK1_GCRT | \ + WDT_RESET_MASK1_USB11_UHCI | WDT_RESET_MASK1_USB_PORTA | \ + WDT_RESET_MASK1_USB_PORTB | WDT_RESET_MASK1_COPROC | \ + WDT_RESET_MASK1_SOC | WDT_RESET_MASK1_ARM) + +#define WDT_RESET_MASK2_DEFAULT \ + (WDT_RESET_MASK2_I3C_BUS8 | WDT_RESET_MASK2_I3C_BUS7 | \ + WDT_RESET_MASK2_I3C_BUS6 | WDT_RESET_MASK2_I3C_BUS5 | \ + WDT_RESET_MASK2_I3C_BUS4 | WDT_RESET_MASK2_I3C_BUS3 | \ + WDT_RESET_MASK2_I3C_BUS2 | WDT_RESET_MASK2_I3C_BUS1 | \ + WDT_RESET_MASK2_I3C_GLOBAL | WDT_RESET_MASK2_I2C | \ + WDT_RESET_MASK2_FSI | WDT_RESET_MASK2_ADC | \ + WDT_RESET_MASK2_PWM | WDT_RESET_MASK2_PECI | \ + WDT_RESET_MASK2_LPC | WDT_RESET_MASK2_MDC_MDIO | \ + WDT_RESET_MASK2_GPIO2 | WDT_RESET_MASK2_JTAG2 | \ + WDT_RESET_MASK2_SD_SDIO2 | WDT_RESET_MASK2_MAC4 | \ + WDT_RESET_MASK2_MAC3 | WDT_RESET_MASK2_SOC | \ + WDT_RESET_MASK2_ARM) + +#ifndef __ASSEMBLY__ +struct ast2600_wdt { + u32 counter_status; + u32 counter_reload_val; + u32 counter_restart; + u32 ctrl; + u32 timeout_status; + u32 clr_timeout_status; + u32 reset_width; + u32 reset_mask1; + u32 reset_mask2; + u32 sw_reset_ctrl; + u32 sw_reset_mask1; + u32 sw_reset_mask2; + u32 sw_reset_disable; +}; +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_ARCH_WDT_AST2600_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-bcm235xx/boot0.h b/roms/u-boot/arch/arm/include/asm/arch-bcm235xx/boot0.h new file mode 100644 index 000000000..8cde42b89 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-bcm235xx/boot0.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Broadcom Corporation. + */ + +/* BOOT0 header information */ +_start: + ARM_VECTORS + .word 0xbabeface + .word _end - _start diff --git a/roms/u-boot/arch/arm/include/asm/arch-bcm235xx/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-bcm235xx/gpio.h new file mode 100644 index 000000000..82c12bb70 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-bcm235xx/gpio.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013 Broadcom Corporation. + */ + +#ifndef __ARCH_BCM235XX_GPIO_H +#define __ARCH_BCM235XX_GPIO_H + +/* + * Empty file - cmd_gpio.c requires this. The implementation + * is in drivers/gpio/kona_gpio.c instead of inlined here. + */ + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-bcm235xx/sysmap.h b/roms/u-boot/arch/arm/include/asm/arch-bcm235xx/sysmap.h new file mode 100644 index 000000000..ff6debc67 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-bcm235xx/sysmap.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013 Broadcom Corporation. + */ + +#ifndef __ARCH_BCM235XX_SYSMAP_H + +#define BSC1_BASE_ADDR 0x3e016000 +#define BSC2_BASE_ADDR 0x3e017000 +#define BSC3_BASE_ADDR 0x3e018000 +#define GPIO2_BASE_ADDR 0x35003000 +#define HSOTG_BASE_ADDR 0x3f120000 +#define HSOTG_CTRL_BASE_ADDR 0x3f130000 +#define KONA_MST_CLK_BASE_ADDR 0x3f001000 +#define KONA_SLV_CLK_BASE_ADDR 0x3e011000 +#define PMU_BSC_BASE_ADDR 0x3500d000 +#define SDIO1_BASE_ADDR 0x3f180000 +#define SDIO2_BASE_ADDR 0x3f190000 +#define SDIO3_BASE_ADDR 0x3f1a0000 +#define SDIO4_BASE_ADDR 0x3f1b0000 +#define TIMER_BASE_ADDR 0x3e00d000 + +#define HSOTG_DCTL_OFFSET 0x00000804 +#define HSOTG_DCTL_SFTDISCON_MASK 0x00000002 + +#define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008 +#define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002 +#define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001 + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/boot0.h b/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/boot0.h new file mode 100644 index 000000000..8cde42b89 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/boot0.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Broadcom Corporation. + */ + +/* BOOT0 header information */ +_start: + ARM_VECTORS + .word 0xbabeface + .word _end - _start diff --git a/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/gpio.h new file mode 100644 index 000000000..6716e1a15 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/gpio.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013 Broadcom Corporation. + */ + +#ifndef __ARCH_BCM281XX_GPIO_H +#define __ARCH_BCM281XX_GPIO_H + +/* + * Empty file - cmd_gpio.c requires this. The implementation + * is in drivers/gpio/kona_gpio.c instead of inlined here. + */ + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/sysmap.h b/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/sysmap.h new file mode 100644 index 000000000..477b69388 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/sysmap.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013 Broadcom Corporation. + */ + +#ifndef __ARCH_BCM281XX_SYSMAP_H + +#define BSC1_BASE_ADDR 0x3e016000 +#define BSC2_BASE_ADDR 0x3e017000 +#define BSC3_BASE_ADDR 0x3e018000 +#define DWDMA_AHB_BASE_ADDR 0x38100000 +#define ESUB_CLK_BASE_ADDR 0x38000000 +#define ESW_CONTRL_BASE_ADDR 0x38200000 +#define GPIO2_BASE_ADDR 0x35003000 +#define HSOTG_BASE_ADDR 0x3f120000 +#define HSOTG_CTRL_BASE_ADDR 0x3f130000 +#define KONA_MST_CLK_BASE_ADDR 0x3f001000 +#define KONA_SLV_CLK_BASE_ADDR 0x3e011000 +#define PMU_BSC_BASE_ADDR 0x3500d000 +#define PWRMGR_BASE_ADDR 0x35010000 +#define SDIO1_BASE_ADDR 0x3f180000 +#define SDIO2_BASE_ADDR 0x3f190000 +#define SDIO3_BASE_ADDR 0x3f1a0000 +#define SDIO4_BASE_ADDR 0x3f1b0000 +#define SECWD_BASE_ADDR 0x3500c000 +#define SECWD2_BASE_ADDR 0x35002f40 +#define TIMER_BASE_ADDR 0x3e00d000 + +#define HSOTG_DCTL_OFFSET 0x00000804 +#define HSOTG_DCTL_SFTDISCON_MASK 0x00000002 + +#define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008 +#define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002 +#define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001 + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-bcmcygnus/configs.h b/roms/u-boot/arch/arm/include/asm/arch-bcmcygnus/configs.h new file mode 100644 index 000000000..bf05cb3a7 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-bcmcygnus/configs.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014-2017 Broadcom. + */ + +#ifndef __ARCH_CONFIGS_H +#define __ARCH_CONFIGS_H + +#include + +/* uArchitecture specifics */ + +/* Serial Info */ +/* Post pad 3 bytes after each reg addr */ +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_NS16550_CLK 100000000 +#define CONFIG_SYS_NS16550_CLK_DIV 54 +#define CONFIG_SERIAL_MULTI +#define CONFIG_SYS_NS16550_COM3 0x18023000 + +/* Ethernet */ +#define CONFIG_PHY_RESET_DELAY 10000 /* PHY reset delay in us*/ + +#endif /* __ARCH_CONFIGS_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-bcmns3/bl33_info.h b/roms/u-boot/arch/arm/include/asm/arch-bcmns3/bl33_info.h new file mode 100644 index 000000000..bbc95b018 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-bcmns3/bl33_info.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Broadcom. + * + */ + +#ifndef BL33_INFO_H +#define BL33_INFO_H +#include + +/* Increase version number each time this file is modified */ +#define BL33_INFO_VERSION 1 + +struct chip_info { + unsigned int chip_id; + unsigned int rev_id; +}; + +struct bl33_info { + unsigned int version; + struct chip_info chip; +}; + +extern struct bl33_info *bl33_info; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-bcmnsp/configs.h b/roms/u-boot/arch/arm/include/asm/arch-bcmnsp/configs.h new file mode 100644 index 000000000..05fa9b961 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-bcmnsp/configs.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Broadcom Corporation. + */ + +#ifndef __ARCH_CONFIGS_H +#define __ARCH_CONFIGS_H + +#include + +/* uArchitecture specifics */ + +/* Serial Info */ +/* no padding */ +#define CONFIG_SYS_NS16550_REG_SIZE 1 + +#define CONFIG_SYS_NS16550_CLK 0x03b9aca0 +#define CONFIG_SYS_NS16550_COM1 0x18000300 + +#endif /* __ARCH_CONFIGS_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-ep93xx/ep93xx.h b/roms/u-boot/arch/arm/include/asm/arch-ep93xx/ep93xx.h new file mode 100644 index 000000000..272b64480 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-ep93xx/ep93xx.h @@ -0,0 +1,666 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Cirrus Logic EP93xx register definitions. + * + * Copyright (C) 2013 + * Sergey Kostanbaev fairwaves.ru> + * + * Copyright (C) 2009 + * Matthias Kaehlcke + * + * Copyright (C) 2006 + * Dominic Rath + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., + * + * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is + * + * Copyright (C) 2004 Ray Lehtiniemi + * Copyright (C) 2003 Cirrus Logic, Inc + * Copyright (C) 1999 ARM Limited. + */ + +#define EP93XX_AHB_BASE 0x80000000 +#define EP93XX_APB_BASE 0x80800000 + +/* + * 0x80000000 - 0x8000FFFF: DMA + */ +#define DMA_OFFSET 0x000000 +#define DMA_BASE (EP93XX_AHB_BASE | DMA_OFFSET) + +#ifndef __ASSEMBLY__ +struct dma_channel { + uint32_t control; + uint32_t interrupt; + uint32_t ppalloc; + uint32_t status; + uint32_t reserved0; + uint32_t remain; + uint32_t reserved1[2]; + uint32_t maxcnt0; + uint32_t base0; + uint32_t current0; + uint32_t reserved2; + uint32_t maxcnt1; + uint32_t base1; + uint32_t current1; + uint32_t reserved3; +}; + +struct dma_regs { + struct dma_channel m2p_channel_0; + struct dma_channel m2p_channel_1; + struct dma_channel m2p_channel_2; + struct dma_channel m2p_channel_3; + struct dma_channel m2m_channel_0; + struct dma_channel m2m_channel_1; + struct dma_channel reserved0[2]; + struct dma_channel m2p_channel_5; + struct dma_channel m2p_channel_4; + struct dma_channel m2p_channel_7; + struct dma_channel m2p_channel_6; + struct dma_channel m2p_channel_9; + struct dma_channel m2p_channel_8; + uint32_t channel_arbitration; + uint32_t reserved[15]; + uint32_t global_interrupt; +}; +#endif + +/* + * 0x80010000 - 0x8001FFFF: Ethernet MAC + */ +#define MAC_OFFSET 0x010000 +#define MAC_BASE (EP93XX_AHB_BASE | MAC_OFFSET) + +#ifndef __ASSEMBLY__ +struct mac_queue { + uint32_t badd; + union { /* deal with half-word aligned registers */ + uint32_t blen; + union { + uint16_t filler; + uint16_t curlen; + }; + }; + uint32_t curadd; +}; + +struct mac_regs { + uint32_t rxctl; + uint32_t txctl; + uint32_t testctl; + uint32_t reserved0; + uint32_t miicmd; + uint32_t miidata; + uint32_t miists; + uint32_t reserved1; + uint32_t selfctl; + uint32_t inten; + uint32_t intstsp; + uint32_t intstsc; + uint32_t reserved2[2]; + uint32_t diagad; + uint32_t diagdata; + uint32_t gt; + uint32_t fct; + uint32_t fcf; + uint32_t afp; + union { + struct { + uint32_t indad; + uint32_t indad_upper; + }; + uint32_t hashtbl; + }; + uint32_t reserved3[2]; + uint32_t giintsts; + uint32_t giintmsk; + uint32_t giintrosts; + uint32_t giintfrc; + uint32_t txcollcnt; + uint32_t rxmissnct; + uint32_t rxruntcnt; + uint32_t reserved4; + uint32_t bmctl; + uint32_t bmsts; + uint32_t rxbca; + uint32_t reserved5; + struct mac_queue rxdq; + uint32_t rxdqenq; + struct mac_queue rxstsq; + uint32_t rxstsqenq; + struct mac_queue txdq; + uint32_t txdqenq; + struct mac_queue txstsq; + uint32_t reserved6; + uint32_t rxbufthrshld; + uint32_t txbufthrshld; + uint32_t rxststhrshld; + uint32_t txststhrshld; + uint32_t rxdthrshld; + uint32_t txdthrshld; + uint32_t maxfrmlen; + uint32_t maxhdrlen; +}; +#endif + +#define SELFCTL_RWP (1 << 7) +#define SELFCTL_GPO0 (1 << 5) +#define SELFCTL_PUWE (1 << 4) +#define SELFCTL_PDWE (1 << 3) +#define SELFCTL_MIIL (1 << 2) +#define SELFCTL_RESET (1 << 0) + +#define INTSTS_RWI (1 << 30) +#define INTSTS_RXMI (1 << 29) +#define INTSTS_RXBI (1 << 28) +#define INTSTS_RXSQI (1 << 27) +#define INTSTS_TXLEI (1 << 26) +#define INTSTS_ECIE (1 << 25) +#define INTSTS_TXUHI (1 << 24) +#define INTSTS_MOI (1 << 18) +#define INTSTS_TXCOI (1 << 17) +#define INTSTS_RXROI (1 << 16) +#define INTSTS_MIII (1 << 12) +#define INTSTS_PHYI (1 << 11) +#define INTSTS_TI (1 << 10) +#define INTSTS_AHBE (1 << 8) +#define INTSTS_OTHER (1 << 4) +#define INTSTS_TXSQ (1 << 3) +#define INTSTS_RXSQ (1 << 2) + +#define BMCTL_MT (1 << 13) +#define BMCTL_TT (1 << 12) +#define BMCTL_UNH (1 << 11) +#define BMCTL_TXCHR (1 << 10) +#define BMCTL_TXDIS (1 << 9) +#define BMCTL_TXEN (1 << 8) +#define BMCTL_EH2 (1 << 6) +#define BMCTL_EH1 (1 << 5) +#define BMCTL_EEOB (1 << 4) +#define BMCTL_RXCHR (1 << 2) +#define BMCTL_RXDIS (1 << 1) +#define BMCTL_RXEN (1 << 0) + +#define BMSTS_TXACT (1 << 7) +#define BMSTS_TP (1 << 4) +#define BMSTS_RXACT (1 << 3) +#define BMSTS_QID_MASK 0x07 +#define BMSTS_QID_RXDATA 0x00 +#define BMSTS_QID_TXDATA 0x01 +#define BMSTS_QID_RXSTS 0x02 +#define BMSTS_QID_TXSTS 0x03 +#define BMSTS_QID_RXDESC 0x04 +#define BMSTS_QID_TXDESC 0x05 + +#define AFP_MASK 0x07 +#define AFP_IAPRIMARY 0x00 +#define AFP_IASECONDARY1 0x01 +#define AFP_IASECONDARY2 0x02 +#define AFP_IASECONDARY3 0x03 +#define AFP_TX 0x06 +#define AFP_HASH 0x07 + +#define RXCTL_PAUSEA (1 << 20) +#define RXCTL_RXFCE1 (1 << 19) +#define RXCTL_RXFCE0 (1 << 18) +#define RXCTL_BCRC (1 << 17) +#define RXCTL_SRXON (1 << 16) +#define RXCTL_RCRCA (1 << 13) +#define RXCTL_RA (1 << 12) +#define RXCTL_PA (1 << 11) +#define RXCTL_BA (1 << 10) +#define RXCTL_MA (1 << 9) +#define RXCTL_IAHA (1 << 8) +#define RXCTL_IA3 (1 << 3) +#define RXCTL_IA2 (1 << 2) +#define RXCTL_IA1 (1 << 1) +#define RXCTL_IA0 (1 << 0) + +#define TXCTL_DEFDIS (1 << 7) +#define TXCTL_MBE (1 << 6) +#define TXCTL_ICRC (1 << 5) +#define TXCTL_TPD (1 << 4) +#define TXCTL_OCOLL (1 << 3) +#define TXCTL_SP (1 << 2) +#define TXCTL_PB (1 << 1) +#define TXCTL_STXON (1 << 0) + +#define MIICMD_REGAD_MASK (0x001F) +#define MIICMD_PHYAD_MASK (0x03E0) +#define MIICMD_OPCODE_MASK (0xC000) +#define MIICMD_PHYAD_8950 (0x0000) +#define MIICMD_OPCODE_READ (0x8000) +#define MIICMD_OPCODE_WRITE (0x4000) + +#define MIISTS_BUSY (1 << 0) + +/* + * 0x80020000 - 0x8002FFFF: USB OHCI + */ +#define USB_OFFSET 0x020000 +#define USB_BASE (EP93XX_AHB_BASE | USB_OFFSET) + +/* + * 0x80030000 - 0x8003FFFF: Raster engine + */ +#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315)) +#define RASTER_OFFSET 0x030000 +#define RASTER_BASE (EP93XX_AHB_BASE | RASTER_OFFSET) +#endif + +/* + * 0x80040000 - 0x8004FFFF: Graphics accelerator + */ +#if defined(CONFIG_EP9315) +#define GFX_OFFSET 0x040000 +#define GFX_BASE (EP93XX_AHB_BASE | GFX_OFFSET) +#endif + +/* + * 0x80050000 - 0x8005FFFF: Reserved + */ + +/* + * 0x80060000 - 0x8006FFFF: SDRAM controller + */ +#define SDRAM_OFFSET 0x060000 +#define SDRAM_BASE (EP93XX_AHB_BASE | SDRAM_OFFSET) + +#ifndef __ASSEMBLY__ +struct sdram_regs { + uint32_t reserved; + uint32_t glconfig; + uint32_t refrshtimr; + uint32_t bootsts; + uint32_t devcfg0; + uint32_t devcfg1; + uint32_t devcfg2; + uint32_t devcfg3; +}; +#endif + +#define SDRAM_DEVCFG_EXTBUSWIDTH (1 << 2) +#define SDRAM_DEVCFG_BANKCOUNT (1 << 3) +#define SDRAM_DEVCFG_SROMLL (1 << 5) +#define SDRAM_DEVCFG_CASLAT_2 0x00010000 +#define SDRAM_DEVCFG_RASTOCAS_2 0x00200000 + +#define SDRAM_OFF_GLCONFIG 0x0004 +#define SDRAM_OFF_REFRSHTIMR 0x0008 + +#define SDRAM_OFF_DEVCFG0 0x0010 +#define SDRAM_OFF_DEVCFG1 0x0014 +#define SDRAM_OFF_DEVCFG2 0x0018 +#define SDRAM_OFF_DEVCFG3 0x001C + +#define SDRAM_DEVCFG0_BASE 0xC0000000 +#define SDRAM_DEVCFG1_BASE 0xD0000000 +#define SDRAM_DEVCFG2_BASE 0xE0000000 +#define SDRAM_DEVCFG3_ASD0_BASE 0xF0000000 +#define SDRAM_DEVCFG3_ASD1_BASE 0x00000000 + +#define GLCONFIG_INIT (1 << 0) +#define GLCONFIG_MRS (1 << 1) +#define GLCONFIG_SMEMBUSY (1 << 5) +#define GLCONFIG_LCR (1 << 6) +#define GLCONFIG_REARBEN (1 << 7) +#define GLCONFIG_CLKSHUTDOWN (1 << 30) +#define GLCONFIG_CKE (1 << 31) + +#define EP93XX_SDRAMCTRL 0x80060000 +#define EP93XX_SDRAMCTRL_GLOBALCFG_INIT 0x00000001 +#define EP93XX_SDRAMCTRL_GLOBALCFG_MRS 0x00000002 +#define EP93XX_SDRAMCTRL_GLOBALCFG_SMEMBUSY 0x00000020 +#define EP93XX_SDRAMCTRL_GLOBALCFG_LCR 0x00000040 +#define EP93XX_SDRAMCTRL_GLOBALCFG_REARBEN 0x00000080 +#define EP93XX_SDRAMCTRL_GLOBALCFG_CLKSHUTDOWN 0x40000000 +#define EP93XX_SDRAMCTRL_GLOBALCFG_CKE 0x80000000 + +#define EP93XX_SDRAMCTRL_REFRESH_MASK 0x0000FFFF + +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_32 0x00000002 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_16 0x00000001 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_8 0x00000000 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_MASK 0x00000003 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_MEDIA 0x00000004 + +#define EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH 0x00000004 +#define EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT 0x00000008 +#define EP93XX_SDRAMCTRL_DEVCFG_SROM512 0x00000010 +#define EP93XX_SDRAMCTRL_DEVCFG_SROMLL 0x00000020 +#define EP93XX_SDRAMCTRL_DEVCFG_2KPAGE 0x00000040 +#define EP93XX_SDRAMCTRL_DEVCFG_SFCONFIGADDR 0x00000080 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_MASK 0x00070000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 0x00010000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_3 0x00020000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_4 0x00030000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_5 0x00040000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_6 0x00050000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_7 0x00060000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_8 0x00070000 +#define EP93XX_SDRAMCTRL_DEVCFG_WBL 0x00080000 +#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_MASK 0x00300000 +#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 0x00200000 +#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_3 0x00300000 +#define EP93XX_SDRAMCTRL_DEVCFG_AUTOPRECHARGE 0x01000000 + +/* + * 0x80070000 - 0x8007FFFF: Reserved + */ + +/* + * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA + */ +#define SMC_OFFSET 0x080000 +#define SMC_BASE (EP93XX_AHB_BASE | SMC_OFFSET) + +#ifndef __ASSEMBLY__ +struct smc_regs { + uint32_t bcr0; + uint32_t bcr1; + uint32_t bcr2; + uint32_t bcr3; + uint32_t reserved0[2]; + uint32_t bcr6; + uint32_t bcr7; +#if defined(CONFIG_EP9315) + uint32_t pcattribute; + uint32_t pccommon; + uint32_t pcio; + uint32_t reserved1[5]; + uint32_t pcmciactrl; +#endif +}; +#endif + +#define EP93XX_OFF_SMCBCR0 0x00 +#define EP93XX_OFF_SMCBCR1 0x04 +#define EP93XX_OFF_SMCBCR2 0x08 +#define EP93XX_OFF_SMCBCR3 0x0C +#define EP93XX_OFF_SMCBCR6 0x18 +#define EP93XX_OFF_SMCBCR7 0x1C + +#define SMC_BCR_IDCY_SHIFT 0 +#define SMC_BCR_WST1_SHIFT 5 +#define SMC_BCR_BLE (1 << 10) +#define SMC_BCR_WST2_SHIFT 11 +#define SMC_BCR_MW_SHIFT 28 + +/* + * 0x80090000 - 0x8009FFFF: Boot ROM + */ + +/* + * 0x800A0000 - 0x800AFFFF: IDE interface + */ + +/* + * 0x800B0000 - 0x800BFFFF: VIC1 + */ + +/* + * 0x800C0000 - 0x800CFFFF: VIC2 + */ + +/* + * 0x800D0000 - 0x800FFFFF: Reserved + */ + +/* + * 0x80800000 - 0x8080FFFF: Reserved + */ + +/* + * 0x80810000 - 0x8081FFFF: Timers + */ +#define TIMER_OFFSET 0x010000 +#define TIMER_BASE (EP93XX_APB_BASE | TIMER_OFFSET) + +#ifndef __ASSEMBLY__ +struct timer { + uint32_t load; + uint32_t value; + uint32_t control; + uint32_t clear; +}; + +struct timer4 { + uint32_t value_low; + uint32_t value_high; +}; + +struct timer_regs { + struct timer timer1; + uint32_t reserved0[4]; + struct timer timer2; + uint32_t reserved1[12]; + struct timer4 timer4; + uint32_t reserved2[6]; + struct timer timer3; +}; +#endif + +/* + * 0x80820000 - 0x8082FFFF: I2S + */ +#define I2S_OFFSET 0x020000 +#define I2S_BASE (EP93XX_APB_BASE | I2S_OFFSET) + +/* + * 0x80830000 - 0x8083FFFF: Security + */ +#define SECURITY_OFFSET 0x030000 +#define SECURITY_BASE (EP93XX_APB_BASE | SECURITY_OFFSET) + +#define EXTENSIONID (SECURITY_BASE + 0x2714) + +/* + * 0x80840000 - 0x8084FFFF: GPIO + */ +#define GPIO_OFFSET 0x040000 +#define GPIO_BASE (EP93XX_APB_BASE | GPIO_OFFSET) + +#ifndef __ASSEMBLY__ +struct gpio_int { + uint32_t inttype1; + uint32_t inttype2; + uint32_t eoi; + uint32_t inten; + uint32_t intsts; + uint32_t rawintsts; + uint32_t db; +}; + +struct gpio_regs { + uint32_t padr; + uint32_t pbdr; + uint32_t pcdr; + uint32_t pddr; + uint32_t paddr; + uint32_t pbddr; + uint32_t pcddr; + uint32_t pdddr; + uint32_t pedr; + uint32_t peddr; + uint32_t reserved0[2]; + uint32_t pfdr; + uint32_t pfddr; + uint32_t pgdr; + uint32_t pgddr; + uint32_t phdr; + uint32_t phddr; + uint32_t reserved1; + uint32_t finttype1; + uint32_t finttype2; + uint32_t reserved2; + struct gpio_int pfint; + uint32_t reserved3[10]; + struct gpio_int paint; + struct gpio_int pbint; + uint32_t eedrive; +}; +#endif + +#define EP93XX_LED_DATA 0x80840020 +#define EP93XX_LED_GREEN_ON 0x0001 +#define EP93XX_LED_RED_ON 0x0002 + +#define EP93XX_LED_DDR 0x80840024 +#define EP93XX_LED_GREEN_ENABLE 0x0001 +#define EP93XX_LED_RED_ENABLE 0x00020000 + +/* + * 0x80850000 - 0x8087FFFF: Reserved + */ + +/* + * 0x80880000 - 0x8088FFFF: AAC + */ +#define AAC_OFFSET 0x080000 +#define AAC_BASE (EP93XX_APB_BASE | AAC_OFFSET) + +/* + * 0x80890000 - 0x8089FFFF: Reserved + */ + +/* + * 0x808A0000 - 0x808AFFFF: SPI + */ +#define SPI_OFFSET 0x0A0000 +#define SPI_BASE (EP93XX_APB_BASE | SPI_OFFSET) + +/* + * 0x808B0000 - 0x808BFFFF: IrDA + */ +#define IRDA_OFFSET 0x0B0000 +#define IRDA_BASE (EP93XX_APB_BASE | IRDA_OFFSET) + +/* + * 0x808C0000 - 0x808CFFFF: UART1 + */ +#define UART1_OFFSET 0x0C0000 +#define UART1_BASE (EP93XX_APB_BASE | UART1_OFFSET) + +/* + * 0x808D0000 - 0x808DFFFF: UART2 + */ +#define UART2_OFFSET 0x0D0000 +#define UART2_BASE (EP93XX_APB_BASE | UART2_OFFSET) + +/* + * 0x808E0000 - 0x808EFFFF: UART3 + */ +#define UART3_OFFSET 0x0E0000 +#define UART3_BASE (EP93XX_APB_BASE | UART3_OFFSET) + +/* + * 0x808F0000 - 0x808FFFFF: Key Matrix + */ +#define KEY_OFFSET 0x0F0000 +#define KEY_BASE (EP93XX_APB_BASE | KEY_OFFSET) + +/* + * 0x80900000 - 0x8090FFFF: Touchscreen + */ +#define TOUCH_OFFSET 0x900000 +#define TOUCH_BASE (EP93XX_APB_BASE | TOUCH_OFFSET) + +/* + * 0x80910000 - 0x8091FFFF: Pulse Width Modulation + */ +#define PWM_OFFSET 0x910000 +#define PWM_BASE (EP93XX_APB_BASE | PWM_OFFSET) + +/* + * 0x80920000 - 0x8092FFFF: Real time clock + */ +#define RTC_OFFSET 0x920000 +#define RTC_BASE (EP93XX_APB_BASE | RTC_OFFSET) + +/* + * 0x80930000 - 0x8093FFFF: Syscon + */ +#define SYSCON_OFFSET 0x930000 +#define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET) + +/* Security */ +#define SECURITY_EXTENSIONID 0x80832714 + +#ifndef __ASSEMBLY__ +struct syscon_regs { + uint32_t pwrsts; + uint32_t pwrcnt; + uint32_t halt; + uint32_t stby; + uint32_t reserved0[2]; + uint32_t teoi; + uint32_t stfclr; + uint32_t clkset1; + uint32_t clkset2; + uint32_t reserved1[6]; + uint32_t scratch0; + uint32_t scratch1; + uint32_t reserved2[2]; + uint32_t apbwait; + uint32_t bustmstrarb; + uint32_t bootmodeclr; + uint32_t reserved3[9]; + uint32_t devicecfg; + uint32_t vidclkdiv; + uint32_t mirclkdiv; + uint32_t i2sclkdiv; + uint32_t keytchclkdiv; + uint32_t chipid; + uint32_t reserved4; + uint32_t syscfg; + uint32_t reserved5[8]; + uint32_t sysswlock; +}; +#else +#define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040) +#endif + +#define SYSCON_OFF_CLKSET1 0x0020 +#define SYSCON_OFF_SYSCFG 0x009c + +#define SYSCON_PWRCNT_UART_BAUD (1 << 29) +#define SYSCON_PWRCNT_USH_EN (1 << 28) + +#define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0 +#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5 +#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT 11 +#define SYSCON_CLKSET_PLL_PS_SHIFT 16 +#define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18 +#define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20 +#define SYSCON_CLKSET1_NBYP1 (1 << 23) +#define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25 + +#define SYSCON_CLKSET2_PLL2_EN (1 << 18) +#define SYSCON_CLKSET2_NBYP2 (1 << 19) +#define SYSCON_CLKSET2_USB_DIV_SHIFT 28 + +#define SYSCON_CHIPID_REV_MASK 0xF0000000 +#define SYSCON_DEVICECFG_SWRST (1 << 31) + +#define SYSCON_SYSCFG_LASDO 0x00000020 + +/* + * 0x80930000 - 0x8093FFFF: Watchdog Timer + */ +#define WATCHDOG_OFFSET 0x940000 +#define WATCHDOG_BASE (EP93XX_APB_BASE | WATCHDOG_OFFSET) + +/* + * 0x80950000 - 0x9000FFFF: Reserved + */ + +/* + * During low_level init we store memory layout in memory at specific location + */ +#define UBOOT_MEMORYCNF_BANK_SIZE 0x2000 +#define UBOOT_MEMORYCNF_BANK_MASK 0x2004 +#define UBOOT_MEMORYCNF_BANK_COUNT 0x2008 diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/clock.h new file mode 100644 index 000000000..d56169143 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/clock.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP Semiconductors + * + */ + +#ifndef __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ +#define __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_BUS_CLK, + MXC_UART_CLK, + MXC_I2C_CLK, + MXC_DSPI_CLK, +}; + +unsigned int mxc_get_clock(enum mxc_clock clk); +ulong get_ddr_freq(ulong); +uint get_svr(void); + +#endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/config.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/config.h new file mode 100644 index 000000000..da7ca0587 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -0,0 +1,409 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016-2018, 2020 NXP + * Copyright 2015, Freescale Semiconductor + */ + +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ +#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ + +#include +#include + +#ifndef __ASSEMBLY__ +#include +#endif + +#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 + +/* + * Reserve secure memory + * To be aligned with MMU block size + */ +#define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */ +#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */ + +#ifdef CONFIG_ARCH_LS2080A +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } +#define SRDS_MAX_LANES 8 +#define CONFIG_SYS_PAGE_SIZE 0x10000 +#ifndef L1_CACHE_BYTES +#define L1_CACHE_SHIFT 6 +#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) +#endif + +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ + +/* DDR */ +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE + +#define CONFIG_SYS_FSL_CCSR_GUR_LE +#define CONFIG_SYS_FSL_CCSR_SCFG_LE +#define CONFIG_SYS_FSL_ESDHC_LE +#define CONFIG_SYS_FSL_IFC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE + +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06100000 + +/* SMMU Defintions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */ + +/* SFP */ +#define CONFIG_SYS_FSL_SFP_VER_3_4 +#define CONFIG_SYS_FSL_SFP_LE +#define CONFIG_SYS_FSL_SRK_LE + +/* Security Monitor */ +#define CONFIG_SYS_FSL_SEC_MON_LE + +/* Secure Boot */ +#define CONFIG_ESBC_HDR_LS + +/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE + +/* Cache Coherent Interconnect */ +#define CCI_MN_BASE 0x04000000 +#define CCI_MN_RNF_NODEID_LIST 0x180 +#define CCI_MN_DVM_DOMAIN_CTL 0x200 +#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 + +#define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) +#define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) +#define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ +#define CCN_HN_F_SAM_NODEID_MASK 0x7f +#define CCN_HN_F_SAM_NODEID_DDR0 0x4 +#define CCN_HN_F_SAM_NODEID_DDR1 0xe + +#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) +#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) +#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) +#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) +#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) +#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) + +#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) +#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) +#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) + +#define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500) + +/* TZ Protection Controller Definitions */ +#define TZPC_BASE 0x02200000 +#define TZPCR0SIZE_BASE (TZPC_BASE) +#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) +#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) +#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) +#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) +#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) +#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) +#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) + +#define DCSR_CGACRE5 0x700070914ULL +#define EPU_EPCMPR5 0x700060914ULL +#define EPU_EPCCR5 0x700060814ULL +#define EPU_EPSMCR5 0x700060228ULL +#define EPU_EPECR5 0x700060314ULL +#define EPU_EPCTR5 0x700060a14ULL +#define EPU_EPGCR 0x700060000ULL + +#define CONFIG_SYS_FSL_ERRATUM_A008751 + +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + +#elif defined(CONFIG_ARCH_LS1088A) +#define CONFIG_SYS_FSL_NUM_CC_PLLS 3 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } +#define CONFIG_GICV3 +#define CONFIG_SYS_PAGE_SIZE 0x10000 + +#define SRDS_MAX_LANES 4 +#define SRDS_BITS_PER_LANE 4 + +/* TZ Protection Controller Definitions */ +#define TZPC_BASE 0x02200000 +#define TZPCR0SIZE_BASE (TZPC_BASE) +#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) +#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) +#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) +#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) +#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) +#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) +#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06100000 + +/* SMMU Defintions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */ + +/* DDR */ +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE + +#define CONFIG_SYS_FSL_CCSR_GUR_LE +#define CONFIG_SYS_FSL_CCSR_SCFG_LE +#define CONFIG_SYS_FSL_ESDHC_LE +#define CONFIG_SYS_FSL_IFC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE + +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN + +/* SFP */ +#define CONFIG_SYS_FSL_SFP_VER_3_4 +#define CONFIG_SYS_FSL_SFP_LE +#define CONFIG_SYS_FSL_SRK_LE + +/* Security Monitor */ +#define CONFIG_SYS_FSL_SEC_MON_LE + +/* Secure Boot */ +#define CONFIG_ESBC_HDR_LS + +/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ + +/* LX2160A/LX2162A Soc Support */ +#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) +#define TZPC_BASE 0x02200000 +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_EARLY_INIT +#endif +#define SRDS_MAX_LANES 8 +#ifndef L1_CACHE_BYTES +#define L1_CACHE_SHIFT 6 +#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) +#endif +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 } +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 + +#define CONFIG_SYS_PAGE_SIZE 0x10000 + +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ + +/* DDR */ +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE + +#define CONFIG_SYS_FSL_CCSR_GUR_LE +#define CONFIG_SYS_FSL_CCSR_SCFG_LE +#define CONFIG_SYS_FSL_ESDHC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE + +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06200000 + +/* SMMU Definitions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */ + +/* SFP */ +#define CONFIG_SYS_FSL_SFP_VER_3_4 +#define CONFIG_SYS_FSL_SFP_LE +#define CONFIG_SYS_FSL_SRK_LE + +/* Security Monitor */ +#define CONFIG_SYS_FSL_SEC_MON_LE + +/* Secure Boot */ +#define CONFIG_ESBC_HDR_LS + +/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE + +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + +#elif defined(CONFIG_ARCH_LS1028A) +#define CONFIG_SYS_FSL_NUM_CC_PLLS 3 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } +#define CONFIG_GICV3 +#define CONFIG_FSL_TZPC_BP147 +#define CONFIG_FSL_TZASC_400 + +/* TZ Protection Controller Definitions */ +#define TZPC_BASE 0x02200000 +#define TZPCR0SIZE_BASE (TZPC_BASE) +#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) +#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) +#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) +#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) +#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) +#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) +#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) + +#define SRDS_MAX_LANES 4 +#define SRDS_BITS_PER_LANE 4 + +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06040000 + +/* SMMU Definitions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */ + +/* DDR */ +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE + +#define CONFIG_SYS_FSL_CCSR_GUR_LE +#define CONFIG_SYS_FSL_CCSR_SCFG_LE +#define CONFIG_SYS_FSL_ESDHC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE + +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN + +/* SFP */ +#define CONFIG_SYS_FSL_SFP_VER_3_4 +#define CONFIG_SYS_FSL_SFP_LE +#define CONFIG_SYS_FSL_SRK_LE + +/* SEC */ +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + +/* Security Monitor */ +#define CONFIG_SYS_FSL_SEC_MON_LE + +/* Secure Boot */ +#define CONFIG_ESBC_HDR_LS + +/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE + +#elif defined(CONFIG_FSL_LSCH2) +#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ +#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ + +#define DCSR_DCFG_SBEESR2 0x20140534 +#define DCSR_DCFG_MBEESR2 0x20140544 + +#define CONFIG_SYS_FSL_CCSR_SCFG_BE +#define CONFIG_SYS_FSL_ESDHC_BE +#define CONFIG_SYS_FSL_WDOG_BE +#define CONFIG_SYS_FSL_DSPI_BE +#define CONFIG_SYS_FSL_CCSR_GUR_BE +#define CONFIG_SYS_FSL_PEX_LUT_BE + +/* SoC related */ +#ifdef CONFIG_ARCH_LS1043A +#define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FSL_QMAN_V3 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 7 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE + +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 + +#define CONFIG_SYS_FSL_IFC_BE +#define CONFIG_SYS_FSL_SFP_VER_3_2 +#define CONFIG_SYS_FSL_SEC_MON_BE +#define CONFIG_SYS_FSL_SFP_BE +#define CONFIG_SYS_FSL_SRK_LE +#define CONFIG_KEY_REVOCATION + +/* SMMU Defintions */ +#define SMMU_BASE 0x09000000 + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x01401000 +#define GICC_BASE 0x01402000 +#define GICH_BASE 0x01404000 +#define GICV_BASE 0x01406000 +#define GICD_SIZE 0x1000 +#define GICC_SIZE 0x2000 +#define GICH_SIZE 0x2000 +#define GICV_SIZE 0x2000 +#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN +#define GICD_BASE_64K 0x01410000 +#define GICC_BASE_64K 0x01420000 +#define GICH_BASE_64K 0x01440000 +#define GICV_BASE_64K 0x01460000 +#define GICD_SIZE_64K 0x10000 +#define GICC_SIZE_64K 0x20000 +#define GICH_SIZE_64K 0x20000 +#define GICV_SIZE_64K 0x20000 +#endif + +#define DCFG_CCSR_SVR 0x1ee00a4 +#define REV1_0 0x10 +#define REV1_1 0x11 +#define GIC_ADDR_BIT 31 +#define SCFG_GIC400_ALIGN 0x1570188 + +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + +#elif defined(CONFIG_ARCH_LS1012A) +#define GICD_BASE 0x01401000 +#define GICC_BASE 0x01402000 +#define CONFIG_SYS_FSL_SFP_VER_3_2 +#define CONFIG_SYS_FSL_SEC_MON_BE +#define CONFIG_SYS_FSL_SFP_BE +#define CONFIG_SYS_FSL_SRK_LE +#define CONFIG_KEY_REVOCATION +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE + +#elif defined(CONFIG_ARCH_LS1046A) +#define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FSL_QMAN_V3 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 8 +#define CONFIG_SYS_NUM_FM1_10GEC 2 +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE + +#define CONFIG_SYS_FSL_IFC_BE +#define CONFIG_SYS_FSL_SFP_VER_3_2 +#define CONFIG_SYS_FSL_SEC_MON_BE +#define CONFIG_SYS_FSL_SFP_BE +#define CONFIG_SYS_FSL_SRK_LE +#define CONFIG_KEY_REVOCATION + +/* SMMU Defintions */ +#define SMMU_BASE 0x09000000 + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x01410000 +#define GICC_BASE 0x01420000 + +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 +#else +#error SoC not defined +#endif +#endif + +#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/cpu.h new file mode 100644 index 000000000..c51b65ea3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017-2018, 2020 NXP + * Copyright 2014-2015, Freescale Semiconductor + */ + +#ifndef _FSL_LAYERSCAPE_CPU_H +#define _FSL_LAYERSCAPE_CPU_H + +#ifdef CONFIG_FSL_LSCH3 +#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 +#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 +#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 +#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 +#ifndef CONFIG_NXP_LSCH3_2 +#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 +#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 +#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 +#endif +#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 +#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 +#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 +#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 +#ifndef CONFIG_NXP_LSCH3_2 +#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 +#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 +#endif +#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 +#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 +#define CONFIG_SYS_FSL_MC_BASE 0x80c000000 +#define CONFIG_SYS_FSL_MC_SIZE 0x4000000 +#define CONFIG_SYS_FSL_NI_BASE 0x810000000 +#define CONFIG_SYS_FSL_NI_SIZE 0x8000000 +#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000 +#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 +#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 +#ifdef CONFIG_ARCH_LS2080A +#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 +#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 +#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 +#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 +#else +#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 +#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 +#ifndef CONFIG_SYS_PCIE3_PHYS_SIZE +#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 +#endif +#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 +#define SYS_PCIE5_PHYS_SIZE 0x800000000 +#define SYS_PCIE6_PHYS_SIZE 0x800000000 +#endif +#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000 +#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 +#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 +#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 +#if !defined(CONFIG_ARCH_LX2160A) || !defined(CONFIG_ARCH_LX2162) +#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 +#else +#define CONFIG_SYS_FSL_PEBUF_BASE 0x1c00000000 +#endif +#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 +#ifdef CONFIG_NXP_LSCH3_2 +#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000 +#define CONFIG_SYS_FSL_DRAM_SIZE2 0x1F80000000 +#define CONFIG_SYS_FSL_DRAM_BASE3 0x6000000000 +#define CONFIG_SYS_FSL_DRAM_SIZE3 0x2000000000 +#else +#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 +#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 +#endif +#elif defined(CONFIG_FSL_LSCH2) +#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000 +#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000 +#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000 +#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000 +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000 +#define CONFIG_SYS_FSL_IFC_BASE 0x60000000 +#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000 +#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 +#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 +#define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000 +#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000 +#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000 +#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */ +#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 +#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 +#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 +#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000 +#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ +#endif + +int fsl_qoriq_core_to_cluster(unsigned int core); +u32 cpu_mask(void); + +#endif /* _FSL_LAYERSCAPE_CPU_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/fdt.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/fdt.h new file mode 100644 index 000000000..ebc999cd7 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/fdt.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor + */ + +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ +#define _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ + +void fdt_fixup_board_enet(void *fdt); +#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h new file mode 100644 index 000000000..3c06a55cb --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef _FSL_ICID_H_ +#define _FSL_ICID_H_ + +#include +#include +#include +#include + +struct icid_id_table { + const char *compat; + u32 id; + u32 reg; + phys_addr_t compat_addr; + phys_addr_t reg_addr; + bool le; +}; + +struct fman_icid_id_table { + u32 port_id; + u32 icid; +}; + +u32 get_ppid_icid(int ppid_tbl_idx, int ppid); +int fdt_get_smmu_phandle(void *blob); +int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids); +void set_icids(void); +void fdt_fixup_icid(void *blob); + +#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \ + { .compat = name, \ + .id = idA, \ + .reg = regA, \ + .compat_addr = compataddr, \ + .reg_addr = addr, \ + .le = _le \ + } + +#ifdef CONFIG_SYS_FSL_SEC_LE +#define SEC_IS_LE true +#elif defined(CONFIG_SYS_FSL_SEC_BE) +#define SEC_IS_LE false +#endif + +#ifdef CONFIG_FSL_LSCH2 + +#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE +#define SCFG_IS_LE true +#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE) +#define SCFG_IS_LE false +#endif + +#define QDMA_IS_LE false + +#define SET_SCFG_ICID(compat, streamid, name, compataddr) \ + SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \ + offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \ + compataddr, SCFG_IS_LE) + +#define SET_USB_ICID(usb_num, compat, streamid) \ + SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\ + CONFIG_SYS_XHCI_USB##usb_num##_ADDR) + +#define SET_SATA_ICID(compat, streamid) \ + SET_SCFG_ICID(compat, streamid, sata_icid,\ + AHCI_BASE_ADDR) + +#define SET_SDHC_ICID(streamid) \ + SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\ + CONFIG_SYS_FSL_ESDHC_ADDR) + +#define SET_EDMA_ICID(streamid) \ + SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\ + EDMA_BASE_ADDR) + +#define SET_ETR_ICID(streamid) \ + SET_SCFG_ICID(NULL, streamid, etr_icid, 0) + +#define SET_DEBUG_ICID(streamid) \ + SET_SCFG_ICID(NULL, streamid, debug_icid, 0) + +#define SET_QE_ICID(streamid) \ + SET_SCFG_ICID("fsl,qe", streamid, qe_icid,\ + QE_BASE_ADDR) + +#define SET_QMAN_ICID(streamid) \ + SET_ICID_ENTRY("fsl,qman", streamid, streamid, \ + offsetof(struct ccsr_qman, liodnr) + \ + CONFIG_SYS_FSL_QMAN_ADDR, \ + CONFIG_SYS_FSL_QMAN_ADDR, false) + +#define SET_BMAN_ICID(streamid) \ + SET_ICID_ENTRY("fsl,bman", streamid, streamid, \ + offsetof(struct ccsr_bman, liodnr) + \ + CONFIG_SYS_FSL_BMAN_ADDR, \ + CONFIG_SYS_FSL_BMAN_ADDR, false) + +#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \ + { .port_id = (_port_id), .icid = (streamid) } + +#define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid)) + +#define SET_SEC_QI_ICID(streamid) \ + SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \ + 0, offsetof(ccsr_sec_t, qilcr_ls) + \ + CONFIG_SYS_FSL_SEC_ADDR, \ + CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE) + +extern struct fman_icid_id_table fman_icid_tbl[]; +extern int fman_icid_tbl_sz; + +#else /* CONFIG_FSL_LSCH2 */ + +#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE +#define GUR_IS_LE true +#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE) +#define GUR_IS_LE false +#endif + +#define QDMA_IS_LE true + +#define SET_GUR_ICID(compat, streamid, name, compataddr) \ + SET_ICID_ENTRY(compat, streamid, streamid, \ + offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \ + compataddr, GUR_IS_LE) + +#define SET_USB_ICID(usb_num, compat, streamid) \ + SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\ + CONFIG_SYS_XHCI_USB##usb_num##_ADDR) + +#define SET_SATA_ICID(sata_num, compat, streamid) \ + SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \ + AHCI_BASE_ADDR##sata_num) + +#define SET_SDHC_ICID(sdhc_num, streamid) \ + SET_GUR_ICID("fsl,esdhc", streamid, sdmm##sdhc_num##_amqr,\ + FSL_ESDHC##sdhc_num##_BASE_ADDR) + +#define SET_EDMA_ICID(streamid) \ + SET_GUR_ICID("fsl,vf610-edma", streamid, spare3_amqr,\ + EDMA_BASE_ADDR) + +#define SET_GPU_ICID(compat, streamid) \ + SET_GUR_ICID(compat, streamid, misc1_amqr,\ + GPU_BASE_ADDR) + +#define SET_DISPLAY_ICID(streamid) \ + SET_GUR_ICID("arm,mali-dp500", streamid, spare2_amqr,\ + DISPLAY_BASE_ADDR) + +#define SEC_ICID_REG_VAL(streamid) (streamid) + +#endif /* CONFIG_FSL_LSCH2 */ + +#define SET_QDMA_ICID(compat, streamid) \ + SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \ + QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \ + QDMA_BASE_ADDR, QDMA_IS_LE), \ + SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \ + QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \ + QDMA_BASE_ADDR, QDMA_IS_LE) + +#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ + SET_ICID_ENTRY( \ + (CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \ + (FSL_SEC_JR##jr_num##_OFFSET == \ + SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \ + ? NULL \ + : "fsl,sec-v4.0-job-ring"), \ + streamid, \ + SEC_ICID_REG_VAL(streamid), \ + offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \ + CONFIG_SYS_FSL_SEC_ADDR, \ + FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE) + +#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \ + SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \ + offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \ + CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE) + +#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \ + SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \ + offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \ + CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE) + +extern struct icid_id_table icid_tbl[]; +extern int icid_tbl_sz; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h new file mode 100644 index 000000000..1577e935a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef _FSL_PORTALS_H_ +#define _FSL_PORTALS_H_ + +struct qportal_info { + u16 dicid; /* DQRR ICID */ + u16 ficid; /* frame data ICID */ + u16 icid; + u8 sdest; +}; + +#define SET_QP_INFO(streamid, dest) \ + { .dicid = (streamid), .ficid = (streamid), .icid = (streamid), \ + .sdest = (dest) } + +extern struct qportal_info qp_info[]; +void fdt_portal(void *blob, const char *compat, const char *container, + u64 addr, u32 size); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h new file mode 100644 index 000000000..8f4365175 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __FSL_SERDES_H__ +#define __FSL_SERDES_H__ + +#include + +#ifdef CONFIG_FSL_LSCH3 +enum srds_prtcl { + /* + * Nobody will check whether the device 'NONE' has been configured, + * So use it to indicate if the serdes_prtcl_map has been initialized. + */ + NONE = 0, + PCIE1, + PCIE2, + PCIE3, + PCIE4, + PCIE5, + PCIE6, + SATA1, + SATA2, + SATA3, + SATA4, + XAUI1, + XAUI2, + XFI1, + XFI2, + XFI3, + XFI4, + XFI5, + XFI6, + XFI7, + XFI8, + XFI9, + XFI10, + XFI11, + XFI12, + XFI13, + XFI14, + SGMII1, + SGMII2, + SGMII3, + SGMII4, + SGMII5, + SGMII6, + SGMII7, + SGMII8, + SGMII9, + SGMII10, + SGMII11, + SGMII12, + SGMII13, + SGMII14, + SGMII15, + SGMII16, + SGMII17, + SGMII18, + QSGMII_A, + QSGMII_B, + QSGMII_C, + QSGMII_D, + SGMII_T1, + SGMII_T2, + SGMII_T3, + SGMII_T4, + SXGMII1, + SXGMII2, + SXGMII3, + SXGMII4, + QXGMII1, + QXGMII2, + QXGMII3, + QXGMII4, + _25GE1, + _25GE2, + _25GE3, + _25GE4, + _25GE5, + _25GE6, + _25GE7, + _25GE8, + _25GE9, + _25GE10, + _40GE1, + _40GE2, + _50GE1, + _50GE2, + _100GE1, + _100GE2, + SERDES_PRCTL_COUNT +}; + +enum srds { + FSL_SRDS_1 = 0, + FSL_SRDS_2 = 1, + NXP_SRDS_3 = 2, +}; +#elif defined(CONFIG_FSL_LSCH2) +enum srds_prtcl { + /* + * Nobody will check whether the device 'NONE' has been configured, + * So use it to indicate if the serdes_prtcl_map has been initialized. + */ + NONE = 0, + PCIE1, + PCIE2, + PCIE3, + PCIE4, + SATA1, + SATA2, + SRIO1, + SRIO2, + SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC10, + SGMII_FM2_DTSEC1, + SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, + SGMII_FM2_DTSEC4, + SGMII_FM2_DTSEC5, + SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC10, + SGMII_TSEC1, + SGMII_TSEC2, + SGMII_TSEC3, + SGMII_TSEC4, + XAUI_FM1, + XAUI_FM2, + AURORA, + CPRI1, + CPRI2, + CPRI3, + CPRI4, + CPRI5, + CPRI6, + CPRI7, + CPRI8, + XAUI_FM1_MAC9, + XAUI_FM1_MAC10, + XAUI_FM2_MAC9, + XAUI_FM2_MAC10, + HIGIG_FM1_MAC9, + HIGIG_FM1_MAC10, + HIGIG_FM2_MAC9, + HIGIG_FM2_MAC10, + QSGMII_FM1_A, /* A indicates MACs 1,2,5,6 */ + QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */ + QSGMII_FM2_A, + QSGMII_FM2_B, + XFI_FM1_MAC1, + XFI_FM1_MAC2, + XFI_FM1_MAC9, + XFI_FM1_MAC10, + XFI_FM2_MAC9, + XFI_FM2_MAC10, + INTERLAKEN, + QSGMII_SW1_A, /* Indicates ports on L2 Switch */ + QSGMII_SW1_B, + SGMII_2500_FM1_DTSEC1, + SGMII_2500_FM1_DTSEC2, + SGMII_2500_FM1_DTSEC3, + SGMII_2500_FM1_DTSEC4, + SGMII_2500_FM1_DTSEC5, + SGMII_2500_FM1_DTSEC6, + SGMII_2500_FM1_DTSEC9, + SGMII_2500_FM1_DTSEC10, + SGMII_2500_FM2_DTSEC1, + SGMII_2500_FM2_DTSEC2, + SGMII_2500_FM2_DTSEC3, + SGMII_2500_FM2_DTSEC4, + SGMII_2500_FM2_DTSEC5, + SGMII_2500_FM2_DTSEC6, + SGMII_2500_FM2_DTSEC9, + SGMII_2500_FM2_DTSEC10, + TX_CLK, + SERDES_PRCTL_COUNT +}; + +enum srds { + FSL_SRDS_1 = 0, + FSL_SRDS_2 = 1, +}; + +#endif + +int is_serdes_configured(enum srds_prtcl device); +void fsl_serdes_init(void); +int serdes_get_first_lane(u32 sd, enum srds_prtcl device); +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); +int is_serdes_prtcl_valid(int serdes, u32 prtcl); +int serdes_get_number(int serdes, int cfg); +void fsl_rgmii_init(void); + +#ifdef CONFIG_FSL_LSCH2 +const char *serdes_clock_to_string(u32 clock); +int get_serdes_protocol(void); +#endif +#ifdef CONFIG_SYS_HAS_SERDES +/* Get the volt of SVDD in unit mV */ +int get_serdes_volt(void); +/* Set the volt of SVDD in unit mV */ +int set_serdes_volt(int svdd); +/* The target volt of SVDD in unit mV */ +int setup_serdes_volt(u32 svdd); +#endif + +#endif /* __FSL_SERDES_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/gpio.h new file mode 100644 index 000000000..7ae5eee8b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/gpio.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +/* + * Dummy header file to enable CONFIG_OF_CONTROL. + * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. + * It includes via , so those SoCs that enable + * OF_CONTROL must have arch/gpio.h. + */ + +#ifndef __ASM_ARCH_MX85XX_GPIO_H +#define __ASM_ARCH_MX85XX_GPIO_H + +struct mpc8xxx_gpio_plat { + ulong addr; + ulong size; + uint ngpios; +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h new file mode 100644 index 000000000..c9be0768e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -0,0 +1,712 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013-2015 Freescale Semiconductor, Inc. + */ + +#ifndef __ARCH_FSL_LSCH2_IMMAP_H__ +#define __ARCH_FSL_LSCH2_IMMAP_H__ + +#include +#ifndef __ASSEMBLY__ +#include +#endif + +#define CONFIG_SYS_IMMR 0x01000000 +#define CONFIG_SYS_DCSRBAR 0x20000000 +#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) +#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040) + +#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) +#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000) +#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) +#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000) +#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) +#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) +#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) +#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0) +#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) +#define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000) +#define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) +#define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000) +#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) +#define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) +#define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) +#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) +#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) +#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) +#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) +#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) + +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0x508000000 +#define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \ + CONFIG_SYS_BMAN_MEM_BASE) +#define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0x500000000 +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680 + +#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000 + +#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) +#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) +#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) +#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000) + +#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) + +#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) +#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) + +#define GPIO1_BASE_ADDR (CONFIG_SYS_IMMR + 0x1300000) +#define GPIO2_BASE_ADDR (CONFIG_SYS_IMMR + 0x1310000) +#define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000) +#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000) + +#define QE_BASE_ADDR (CONFIG_SYS_IMMR + 0x1400000) + +#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) + +#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c00000) + +#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) + +#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) +#define QMAN_CQSIDR_REG 0x20a80 + +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL +#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL +/* LUT registers */ +#ifdef CONFIG_ARCH_LS1012A +#define PCIE_LUT_BASE 0xC0000 +#else +#define PCIE_LUT_BASE 0x10000 +#endif +#define PCIE_LUT_LCTRL0 0x7F8 +#define PCIE_LUT_DBG 0x7FC + +/* TZ Address Space Controller Definitions */ +#define TZASC1_BASE 0x01100000 /* as per CCSR map. */ +#define TZASC2_BASE 0x01110000 /* as per CCSR map. */ +#define TZASC3_BASE 0x01120000 /* as per CCSR map. */ +#define TZASC4_BASE 0x01130000 /* as per CCSR map. */ +#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) +#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) +#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) +#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) +#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) +#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) +#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) +#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) +#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) + +#define TP_ITYP_AV 0x00000001 /* Initiator available */ +#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ +#define TP_ITYP_TYPE_ARM 0x0 +#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ +#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ +#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ +#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ +#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ +#define TY_ITYP_VER_A7 0x1 +#define TY_ITYP_VER_A53 0x2 +#define TY_ITYP_VER_A57 0x3 +#define TY_ITYP_VER_A72 0x4 + +#define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */ +#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ +#define TP_INIT_PER_CLUSTER 4 + +/* + * Define default values for some CCSR macros to make header files cleaner* + * + * To completely disable CCSR relocation in a board header file, define + * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS + * to a value that is the same as CONFIG_SYS_CCSRBAR. + */ + +#ifdef CONFIG_SYS_CCSRBAR_PHYS +#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ +CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." +#endif + +#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#undef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif + +#ifndef CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR 0x01000000 +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000 +#endif + +#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CONFIG_SYS_CCSRBAR_PHYS_LOW) + +struct sys_info { + unsigned long freq_processor[CONFIG_MAX_CPUS]; + /* frequency of platform PLL */ + unsigned long freq_systembus; + unsigned long freq_ddrbus; + unsigned long freq_localbus; + unsigned long freq_cga_m2; +#ifdef CONFIG_SYS_DPAA_FMAN + unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; +#endif + unsigned long freq_qman; +}; + +#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000 +#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000 +#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000 +#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000 +#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000 +#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000 +#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000 + +#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000 +#define CONFIG_SYS_FSL_FM1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) +#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) + +#define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull +#define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull +#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET +#define FSL_SEC_JR1_OFFSET 0x720000ull +#define FSL_SEC_JR2_OFFSET 0x730000ull +#define FSL_SEC_JR3_OFFSET 0x740000ull +#define CONFIG_SYS_FSL_SEC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) +#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) +#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) +#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) +#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET) + +/* Device Configuration and Pin Control */ +#define DCFG_DCSR_PORCR1 0x0 +#define DCFG_DCSR_ECCCR2 0x524 +#define DISABLE_PFE_ECC BIT(13) + +struct ccsr_gur { + u32 porsr1; /* POR status 1 */ +#define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 + u32 porsr2; /* POR status 2 */ + u8 res_008[0x20-0x8]; + u32 gpporcr1; /* General-purpose POR configuration */ + u32 gpporcr2; +#define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25 +#define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F +#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20 +#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F + u32 dcfg_fusesr; /* Fuse status register */ + u8 res_02c[0x70-0x2c]; + u32 devdisr; /* Device disable control */ +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000 +#define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000 +#define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000 +#define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000 +#define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000 + u32 devdisr2; /* Device disable control 2 */ + u32 devdisr3; /* Device disable control 3 */ + u32 devdisr4; /* Device disable control 4 */ + u32 devdisr5; /* Device disable control 5 */ + u32 devdisr6; /* Device disable control 6 */ + u32 devdisr7; /* Device disable control 7 */ + u8 res_08c[0x94-0x8c]; + u32 coredisru; /* uppper portion for support of 64 cores */ + u32 coredisrl; /* lower portion for support of 64 cores */ + u8 res_09c[0xa0-0x9c]; + u32 pvr; /* Processor version */ + u32 svr; /* System version */ + u32 mvr; /* Manufacturing version */ + u8 res_0ac[0xb0-0xac]; + u32 rstcr; /* Reset control */ + u32 rstrqpblsr; /* Reset request preboot loader status */ + u8 res_0b8[0xc0-0xb8]; + u32 rstrqmr1; /* Reset request mask */ + u8 res_0c4[0xc8-0xc4]; + u32 rstrqsr1; /* Reset request status */ + u8 res_0cc[0xd4-0xcc]; + u32 rstrqwdtmrl; /* Reset request WDT mask */ + u8 res_0d8[0xdc-0xd8]; + u32 rstrqwdtsrl; /* Reset request WDT status */ + u8 res_0e0[0xe4-0xe0]; + u32 brrl; /* Boot release */ + u8 res_0e8[0x100-0xe8]; + u32 rcwsr[16]; /* Reset control word status */ +#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 +#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f +#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 +#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f +#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 +#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff +#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0 +#define RCW_SB_EN_REG_INDEX 7 +#define RCW_SB_EN_MASK 0x00200000 + + u8 res_140[0x200-0x140]; + u32 scratchrw[4]; /* Scratch Read/Write */ + u8 res_210[0x300-0x210]; + u32 scratchw1r[4]; /* Scratch Read (Write once) */ + u8 res_310[0x400-0x310]; + u32 crstsr[12]; + u8 res_430[0x500-0x430]; + + /* PCI Express n Logical I/O Device Number register */ + u32 dcfg_ccsr_pex1liodnr; + u32 dcfg_ccsr_pex2liodnr; + u32 dcfg_ccsr_pex3liodnr; + u32 dcfg_ccsr_pex4liodnr; + /* RIO n Logical I/O Device Number register */ + u32 dcfg_ccsr_rio1liodnr; + u32 dcfg_ccsr_rio2liodnr; + u32 dcfg_ccsr_rio3liodnr; + u32 dcfg_ccsr_rio4liodnr; + /* USB Logical I/O Device Number register */ + u32 dcfg_ccsr_usb1liodnr; + u32 dcfg_ccsr_usb2liodnr; + u32 dcfg_ccsr_usb3liodnr; + u32 dcfg_ccsr_usb4liodnr; + /* SD/MMC Logical I/O Device Number register */ + u32 dcfg_ccsr_sdmmc1liodnr; + u32 dcfg_ccsr_sdmmc2liodnr; + u32 dcfg_ccsr_sdmmc3liodnr; + u32 dcfg_ccsr_sdmmc4liodnr; + /* RIO Message Unit Logical I/O Device Number register */ + u32 dcfg_ccsr_riomaintliodnr; + + u8 res_544[0x550-0x544]; + u32 sataliodnr[4]; + u8 res_560[0x570-0x560]; + + u32 dcfg_ccsr_misc1liodnr; + u32 dcfg_ccsr_misc2liodnr; + u32 dcfg_ccsr_misc3liodnr; + u32 dcfg_ccsr_misc4liodnr; + u32 dcfg_ccsr_dma1liodnr; + u32 dcfg_ccsr_dma2liodnr; + u32 dcfg_ccsr_dma3liodnr; + u32 dcfg_ccsr_dma4liodnr; + u32 dcfg_ccsr_spare1liodnr; + u32 dcfg_ccsr_spare2liodnr; + u32 dcfg_ccsr_spare3liodnr; + u32 dcfg_ccsr_spare4liodnr; + u8 res_5a0[0x600-0x5a0]; + u32 dcfg_ccsr_pblsr; + + u32 pamubypenr; + u32 dmacr1; + + u8 res_60c[0x610-0x60c]; + u32 dcfg_ccsr_gensr1; + u32 dcfg_ccsr_gensr2; + u32 dcfg_ccsr_gensr3; + u32 dcfg_ccsr_gensr4; + u32 dcfg_ccsr_gencr1; + u32 dcfg_ccsr_gencr2; + u32 dcfg_ccsr_gencr3; + u32 dcfg_ccsr_gencr4; + u32 dcfg_ccsr_gencr5; + u32 dcfg_ccsr_gencr6; + u32 dcfg_ccsr_gencr7; + u8 res_63c[0x658-0x63c]; + u32 dcfg_ccsr_cgensr1; + u32 dcfg_ccsr_cgensr0; + u8 res_660[0x678-0x660]; + u32 dcfg_ccsr_cgencr1; + + u32 dcfg_ccsr_cgencr0; + u8 res_680[0x700-0x680]; + u32 dcfg_ccsr_sriopstecr; + u32 dcfg_ccsr_dcsrcr; + + u8 res_708[0x740-0x708]; /* add more registers when needed */ + u32 tp_ityp[64]; /* Topology Initiator Type Register */ + struct { + u32 upper; + u32 lower; + } tp_cluster[16]; + u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */ + u32 dcfg_ccsr_qmbm_warmrst; + u8 res_a04[0xa20-0xa04]; /* add more registers when needed */ + u32 dcfg_ccsr_reserved0; + u32 dcfg_ccsr_reserved1; +}; + +#define SCFG_QSPI_CLKSEL 0x40100000 +#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 +#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 +#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002 +#define SCFG_USBPWRFAULT_INACTIVE 0x00000000 +#define SCFG_USBPWRFAULT_SHARED 0x00000001 +#define SCFG_USBPWRFAULT_DEDICATED 0x00000002 +#define SCFG_USBPWRFAULT_USB3_SHIFT 4 +#define SCFG_USBPWRFAULT_USB2_SHIFT 2 +#define SCFG_USBPWRFAULT_USB1_SHIFT 0 + +#define SCFG_BASE 0x01570000 +#define SCFG_USB3PRM1CR_USB1 0x070 +#define SCFG_USB3PRM2CR_USB1 0x074 +#define SCFG_USB3PRM1CR_USB2 0x07C +#define SCFG_USB3PRM2CR_USB2 0x080 +#define SCFG_USB3PRM1CR_USB3 0x088 +#define SCFG_USB3PRM2CR_USB3 0x08c +#define SCFG_USB_TXVREFTUNE 0x9 +#define SCFG_USB_SQRXTUNE_MASK 0x7 +#define SCFG_USB_PCSTXSWINGFULL 0x47 +#define SCFG_USB_PHY1 0x084F0000 +#define SCFG_USB_PHY2 0x08500000 +#define SCFG_USB_PHY3 0x08510000 +#define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c +#define USB_PHY_RX_EQ_VAL_1 0x0000 +#define USB_PHY_RX_EQ_VAL_2 0x0080 +#define USB_PHY_RX_EQ_VAL_3 0x0380 +#define USB_PHY_RX_EQ_VAL_4 0x0b80 + +#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 +#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 +#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 +#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 +#define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000 +#define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000 +#define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000 +#define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000 +#define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000 +#define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000 + +/* RGMIIPCR bit definitions*/ +#define SCFG_RGMIIPCR_EN_AUTO BIT(3) +#define SCFG_RGMIIPCR_SETSP_1000M BIT(2) +#define SCFG_RGMIIPCR_SETSP_100M 0 +#define SCFG_RGMIIPCR_SETSP_10M BIT(1) +#define SCFG_RGMIIPCR_SETFD BIT(0) + +/* PFEASBCR bit definitions */ +#define SCFG_PFEASBCR_ARCACHE0 BIT(31) +#define SCFG_PFEASBCR_AWCACHE0 BIT(30) +#define SCFG_PFEASBCR_ARCACHE1 BIT(29) +#define SCFG_PFEASBCR_AWCACHE1 BIT(28) +#define SCFG_PFEASBCR_ARSNP BIT(27) +#define SCFG_PFEASBCR_AWSNP BIT(26) + +/* WR_QoS1 PFE bit definitions */ +#define SCFG_WR_QOS1_PFE1_QOS GENMASK(27, 24) +#define SCFG_WR_QOS1_PFE2_QOS GENMASK(23, 20) + +/* RD_QoS1 PFE bit definitions */ +#define SCFG_RD_QOS1_PFE1_QOS GENMASK(27, 24) +#define SCFG_RD_QOS1_PFE2_QOS GENMASK(23, 20) + +/* Supplemental Configuration Unit */ +struct ccsr_scfg { + u8 res_000[0x100-0x000]; + u32 usb2_icid; + u32 usb3_icid; + u8 res_108[0x114-0x108]; + u32 dma_icid; + u32 sata_icid; + u32 usb1_icid; + u32 qe_icid; + u32 sdhc_icid; + u32 edma_icid; + u32 etr_icid; + u32 core_sft_rst[4]; + u8 res_140[0x158-0x140]; + u32 altcbar; + u32 qspi_cfg; + u8 res_160[0x164 - 0x160]; + u32 wr_qos1; + u32 wr_qos2; + u32 rd_qos1; + u32 rd_qos2; + u8 res_174[0x180 - 0x174]; + u32 dmamcr; + u8 res_184[0x188-0x184]; + u32 gic_align; + u32 debug_icid; + u8 res_190[0x1a4-0x190]; + u32 snpcnfgcr; + u8 res_1a8[0x1ac-0x1a8]; + u32 intpcr; + u8 res_1b0[0x204-0x1b0]; + u32 coresrencr; + u8 res_208[0x220-0x208]; + u32 rvbar0_0; + u32 rvbar0_1; + u32 rvbar1_0; + u32 rvbar1_1; + u32 rvbar2_0; + u32 rvbar2_1; + u32 rvbar3_0; + u32 rvbar3_1; + u32 lpmcsr; + u8 res_244[0x400-0x244]; + u32 qspidqscr; + u32 ecgtxcmcr; + u32 sdhciovselcr; + u32 rcwpmuxcr0; + u32 usbdrvvbus_selcr; + u32 usbpwrfault_selcr; + u32 usb_refclk_selcr1; + u32 usb_refclk_selcr2; + u32 usb_refclk_selcr3; + u8 res_424[0x434 - 0x424]; + u32 rgmiipcr; + u32 res_438; + u32 rgmiipsr; + u32 pfepfcssr1; + u32 pfeintencr1; + u32 pfepfcssr2; + u32 pfeintencr2; + u32 pfeerrcr; + u32 pfeeerrintencr; + u32 pfeasbcr; + u32 pfebsbcr; + u8 res_460[0x484 - 0x460]; + u32 mdioselcr; + u8 res_468[0x600 - 0x488]; + u32 scratchrw[4]; + u8 res_610[0x680-0x610]; + u32 corebcr; + u8 res_684[0x1000-0x684]; + u32 pex1msiir; + u32 pex1msir; + u8 res_1008[0x2000-0x1008]; + u32 pex2; + u32 pex2msir; + u8 res_2008[0x3000-0x2008]; + u32 pex3msiir; + u32 pex3msir; +}; + +/* Clocking */ +struct ccsr_clk { + struct { + u32 clkcncsr; /* core cluster n clock control status */ + u8 res_004[0x0c]; + u32 clkcghwacsr; /* Clock generator n hardware accelerator */ + u8 res_014[0x0c]; + } clkcsr[4]; + u8 res_040[0x780]; /* 0x100 */ + struct { + u32 pllcngsr; + u8 res_804[0x1c]; + } pllcgsr[2]; + u8 res_840[0x1c0]; + u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ + u8 res_a04[0x1fc]; + u32 pllpgsr; /* 0xc00 Platform PLL General Status */ + u8 res_c04[0x1c]; + u32 plldgsr; /* 0xc20 DDR PLL General Status */ + u8 res_c24[0x3dc]; +}; + +/* System Counter */ +struct sctr_regs { + u32 cntcr; + u32 cntsr; + u32 cntcv1; + u32 cntcv2; + u32 resv1[4]; + u32 cntfid0; + u32 cntfid1; + u32 resv2[1002]; + u32 counterid[12]; +}; + +#define SRDS_MAX_LANES 4 +struct ccsr_serdes { + struct { + u32 rstctl; /* Reset Control Register */ +#define SRDS_RSTCTL_RST 0x80000000 +#define SRDS_RSTCTL_RSTDONE 0x40000000 +#define SRDS_RSTCTL_RSTERR 0x20000000 +#define SRDS_RSTCTL_SWRST 0x10000000 +#define SRDS_RSTCTL_SDEN 0x00000020 +#define SRDS_RSTCTL_SDRST_B 0x00000040 +#define SRDS_RSTCTL_PLLRST_B 0x00000080 + u32 pllcr0; /* PLL Control Register 0 */ +#define SRDS_PLLCR0_POFF 0x80000000 +#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 +#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 +#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 +#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 +#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 +#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 +#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 +#define SRDS_PLLCR0_PLL_LCK 0x00800000 +#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 +#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 +#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 +#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 +#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 +#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 +#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 + u32 pllcr1; /* PLL Control Register 1 */ +#define SRDS_PLLCR1_PLL_BWSEL 0x08000000 + u32 res_0c; /* 0x00c */ + u32 pllcr3; + u32 pllcr4; + u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */ + u8 res_1c[0x20-0x1c]; + } bank[2]; + u8 res_40[0x90-0x40]; + u32 srdstcalcr; /* 0x90 TX Calibration Control */ + u8 res_94[0xa0-0x94]; + u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ + u8 res_a4[0xb0-0xa4]; + u32 srdsgr0; /* 0xb0 General Register 0 */ + u8 res_b4[0x100-0xb4]; + struct { + u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */ + u8 res_104[0x120-0x104]; + } lnpssr[4]; /* Lane A, B, C, D */ + u8 res_180[0x200-0x180]; + u32 srdspccr0; /* 0x200 Protocol Configuration 0 */ + u32 srdspccr1; /* 0x204 Protocol Configuration 1 */ + u32 srdspccr2; /* 0x208 Protocol Configuration 2 */ + u32 srdspccr3; /* 0x20c Protocol Configuration 3 */ + u32 srdspccr4; /* 0x210 Protocol Configuration 4 */ + u32 srdspccr5; /* 0x214 Protocol Configuration 5 */ + u32 srdspccr6; /* 0x218 Protocol Configuration 6 */ + u32 srdspccr7; /* 0x21c Protocol Configuration 7 */ + u32 srdspccr8; /* 0x220 Protocol Configuration 8 */ + u32 srdspccr9; /* 0x224 Protocol Configuration 9 */ + u32 srdspccra; /* 0x228 Protocol Configuration A */ + u32 srdspccrb; /* 0x22c Protocol Configuration B */ + u8 res_230[0x800-0x230]; + struct { + u32 gcr0; /* 0x800 General Control Register 0 */ + u32 gcr1; /* 0x804 General Control Register 1 */ + u32 gcr2; /* 0x808 General Control Register 2 */ + u32 sscr0; + u32 recr0; /* 0x810 Receive Equalization Control */ + u32 recr1; + u32 tecr0; /* 0x818 Transmit Equalization Control */ + u32 sscr1; + u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ + u8 res_824[0x83c-0x824]; + u32 tcsr3; + } lane[4]; /* Lane A, B, C, D */ + u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */ + struct { + u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */ + u8 res_1004[0x1040-0x1004]; + } pcie[3]; + u8 res_10c0[0x1800-0x10c0]; + struct { + u8 res_1800[0x1804-0x1800]; + u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */ + u8 res_1808[0x180c-0x1808]; + u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */ + } sgmii[4]; /* Lane A, B, C, D */ + u8 res_1840[0x1880-0x1840]; + struct { + u8 res_1880[0x1884-0x1880]; + u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */ + u8 res_1888[0x188c-0x1888]; + u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */ + } qsgmii[2]; /* Lane A, B */ + u8 res_18a0[0x1980-0x18a0]; + struct { + u8 res_1980[0x1984-0x1980]; + u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */ + u8 res_1988[0x198c-0x1988]; + u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */ + } xfi[2]; /* Lane A, B */ + u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ +}; + +struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; + u32 gpibe; +}; + +/* MMU 500 */ +#define SMMU_SCR0 (SMMU_BASE + 0x0) +#define SMMU_SCR1 (SMMU_BASE + 0x4) +#define SMMU_SCR2 (SMMU_BASE + 0x8) +#define SMMU_SACR (SMMU_BASE + 0x10) +#define SMMU_IDR0 (SMMU_BASE + 0x20) +#define SMMU_IDR1 (SMMU_BASE + 0x24) + +#define SMMU_NSCR0 (SMMU_BASE + 0x400) +#define SMMU_NSCR2 (SMMU_BASE + 0x408) +#define SMMU_NSACR (SMMU_BASE + 0x410) + +#define SCR0_CLIENTPD_MASK 0x00000001 +#define SCR0_USFCFG_MASK 0x00000400 + +#ifdef CONFIG_TFABOOT +#define RCW_SRC_MASK (0xFF800000) +#define RCW_SRC_BIT 23 + +/* RCW SRC NAND */ +#define RCW_SRC_NAND_MASK (0x100) +#define RCW_SRC_NAND_VAL (0x100) +#define NAND_RESERVED_MASK (0xFC) +#define NAND_RESERVED_1 (0x0) +#define NAND_RESERVED_2 (0x80) + +/* RCW SRC NOR */ +#define RCW_SRC_NOR_MASK (0x1F0) +#define NOR_8B_VAL (0x10) +#define NOR_16B_VAL (0x20) +#define SD_VAL (0x40) +#define QSPI_VAL1 (0x44) +#define QSPI_VAL2 (0x45) +#endif + +uint get_svr(void); + +#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h new file mode 100644 index 000000000..b64d7fbc1 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -0,0 +1,603 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * LayerScape Internal Memory Map + * + * Copyright 2017-2020 NXP + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __ARCH_FSL_LSCH3_IMMAP_H_ +#define __ARCH_FSL_LSCH3_IMMAP_H_ + +#define CONFIG_SYS_IMMR 0x01000000 +#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) +#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) +#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 +#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) +#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) +#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180) +#else +#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) +#endif +#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) +#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) +#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) +#ifndef CONFIG_NXP_LSCH3_2 +#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) +#else +#define SYS_NXP_FSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) +#define SYS_NXP_FSPI_LUTKEY_BASE_ADDR 0x18 +#define SYS_NXP_FSPI_LUT_BASE_ADDR 0x200 +#endif +#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) +#define FSL_ESDHC1_BASE_ADDR CONFIG_SYS_FSL_ESDHC_ADDR +#define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000) +#ifndef CONFIG_NXP_LSCH3_2 +#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) +#endif +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) +#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000 +#define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000 +#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ + 0x18A0) +#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0) +#define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4) + +#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000) +#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000) +#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000) +#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) + +#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL +#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL +#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL +#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL + +#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) +#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) +#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) +#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) +#ifdef CONFIG_NXP_LSCH3_2 +#define I2C5_BASE_ADDR (CONFIG_SYS_IMMR + 0x01040000) +#define I2C6_BASE_ADDR (CONFIG_SYS_IMMR + 0x01050000) +#define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000) +#define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000) +#endif +#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000) +#define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0) +#define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8) + +#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) + +/* TZ Address Space Controller Definitions */ +#define TZASC1_BASE 0x01100000 /* as per CCSR map. */ +#define TZASC2_BASE 0x01110000 /* as per CCSR map. */ +#define TZASC3_BASE 0x01120000 /* as per CCSR map. */ +#define TZASC4_BASE 0x01130000 /* as per CCSR map. */ +#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) +#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) +#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) +#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) +#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) +#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) +#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) +#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) +#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) + +/* EDMA */ +#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x012c0000) + +/* SATA */ +#define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) +#define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000) +#define AHCI_BASE_ADDR3 (CONFIG_SYS_IMMR + 0x02220000) +#define AHCI_BASE_ADDR4 (CONFIG_SYS_IMMR + 0x02230000) + +/* QDMA */ +#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) +#define QMAN_CQSIDR_REG 0x20a80 + +/* DISPLAY */ +#define DISPLAY_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e080000) + +/* GPU */ +#define GPU_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e0c0000) + +/* SFP */ +#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) + +/* SEC */ +#define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull +#define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull +#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET +#define FSL_SEC_JR1_OFFSET 0x07020000ull +#define FSL_SEC_JR2_OFFSET 0x07030000ull +#define FSL_SEC_JR3_OFFSET 0x07040000ull +#define CONFIG_SYS_FSL_SEC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) +#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) +#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) +#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) +#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET) + +#ifdef CONFIG_TFABOOT +#ifdef CONFIG_NXP_LSCH3_2 +/* RCW_SRC field in Power-On Reset Control Register 1 */ +#define RCW_SRC_MASK 0x07800000 +#define RCW_SRC_BIT 23 + +/* CFG_RCW_SRC[3:0] */ +#define RCW_SRC_TYPE_MASK 0x8 +#define RCW_SRC_ADDR_OFFSET_8MB 0x800000 + +/* RCW SRC HARDCODED */ +#define RCW_SRC_HARDCODED_VAL 0x0 /* 0x00 - 0x07 */ + +#define RCW_SRC_SDHC1_VAL 0x8 /* 0x8 */ +#define RCW_SRC_SDHC2_VAL 0x9 /* 0x9 */ +#define RCW_SRC_I2C1_VAL 0xa /* 0xa */ +#define RCW_SRC_RESERVED_UART_VAL 0xb /* 0xb */ +#define RCW_SRC_FLEXSPI_NAND2K_VAL 0xc /* 0xc */ +#define RCW_SRC_FLEXSPI_NAND4K_VAL 0xd /* 0xd */ +#define RCW_SRC_RESERVED_1_VAL 0xe /* 0xe */ +#define RCW_SRC_FLEXSPI_NOR_24B 0xf /* 0xf */ +#else +#define RCW_SRC_MASK (0xFF800000) +#define RCW_SRC_BIT 23 +/* CFG_RCW_SRC[6:0] */ +#define RCW_SRC_TYPE_MASK (0x70) + +/* RCW SRC HARDCODED */ +#define RCW_SRC_HARDCODED_VAL (0x10) /* 0x10 - 0x1f */ +/* Hardcoded will also have CFG_RCW_SRC[7] as 1. 0x90 - 0x9f */ + +/* RCW SRC NOR */ +#define RCW_SRC_NOR_VAL (0x20) +#define NOR_TYPE_MASK (0x10) +#define NOR_16B_VAL (0x0) /* 0x20 - 0x2f */ +#define NOR_32B_VAL (0x10) /* 0x30 - 0x3f */ + +/* RCW SRC Serial Flash + * 1. SERIAL NOR (QSPI) + * 2. OTHERS (SD/MMC, SPI, I2C1 + */ +#define RCW_SRC_SERIAL_MASK (0x7F) +#define RCW_SRC_QSPI_VAL (0x62) /* 0x62 */ +#define RCW_SRC_SD_CARD_VAL (0x40) /* 0x40 */ +#define RCW_SRC_EMMC_VAL (0x41) /* 0x41 */ +#define RCW_SRC_I2C1_VAL (0x49) /* 0x49 */ +#endif +#endif + +/* Security Monitor */ +#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) + +/* MMU 500 */ +#define SMMU_SCR0 (SMMU_BASE + 0x0) +#define SMMU_SCR1 (SMMU_BASE + 0x4) +#define SMMU_SCR2 (SMMU_BASE + 0x8) +#define SMMU_SACR (SMMU_BASE + 0x10) +#define SMMU_IDR0 (SMMU_BASE + 0x20) +#define SMMU_IDR1 (SMMU_BASE + 0x24) + +#define SMMU_NSCR0 (SMMU_BASE + 0x400) +#define SMMU_NSCR2 (SMMU_BASE + 0x408) +#define SMMU_NSACR (SMMU_BASE + 0x410) + +#define SCR0_CLIENTPD_MASK 0x00000001 +#define SCR0_USFCFG_MASK 0x00000400 + + +/* PCIe */ +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) +#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) +#define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000) +#define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000) +#endif + +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL +#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL +#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL +#define SYS_PCIE5_PHYS_ADDR 0xa000000000ULL +#define SYS_PCIE6_PHYS_ADDR 0xa800000000ULL +#elif CONFIG_ARCH_LS1088A +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL +#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL +#elif CONFIG_ARCH_LS1028A +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL +#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x01f0000000ULL +/* this is used by integrated PCI on LS1028, includes ECAM and register space */ +#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x0010000000ULL +#else +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL +#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL +#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL +#endif + +/* Device Configuration */ +#define DCFG_BASE 0x01e00000 +#define DCFG_PORSR1 0x000 +#define DCFG_PORSR1_RCW_SRC 0xff800000 +#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 +#define DCFG_RCWSR12 0x12c +#define DCFG_RCWSR12_SDHC_SHIFT 24 +#define DCFG_RCWSR12_SDHC_MASK 0x7 +#define DCFG_RCWSR13 0x130 +#define DCFG_RCWSR13_SDHC_SHIFT 3 +#define DCFG_RCWSR13_SDHC_MASK 0x7 +#define DCFG_RCWSR13_DSPI (0 << 8) +#define DCFG_RCWSR15 0x138 +#define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3 + +#define DCFG_DCSR_BASE 0X700100000ULL +#define DCFG_DCSR_PORCR1 0x000 + +/* Interrupt Sampling Control */ +#define ISC_BASE 0x01F70000 +#define IRQCR_OFFSET 0x14 + +/* Supplemental Configuration */ +#define SCFG_BASE 0x01fc0000 +#define SCFG_USB3PRM1CR 0x000 +#define SCFG_USB3PRM1CR_INIT 0x27672b2a +#define SCFG_USB_TXVREFTUNE 0x9 +#define SCFG_USB_SQRXTUNE_MASK 0x7 +#define SCFG_QSPICLKCTLR 0x10 + +#define DCSR_BASE 0x700000000ULL +#define DCSR_USB_PHY1 0x4600000 +#define DCSR_USB_PHY2 0x4610000 +#define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C +#define USB_PHY_RX_EQ_VAL_1 0x0000 +#define USB_PHY_RX_EQ_VAL_2 0x0080 +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ + defined(CONFIG_ARCH_LS1028A) +#define USB_PHY_RX_EQ_VAL_3 0x0380 +#define USB_PHY_RX_EQ_VAL_4 0x0b80 +#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) +#define USB_PHY_RX_EQ_VAL_3 0x0080 +#define USB_PHY_RX_EQ_VAL_4 0x0880 +#endif +#define DCSR_USB_IOCR1 0x108004 +#define DCSR_USB_PCSTXSWINGFULL 0x71 + +#define TP_ITYP_AV 0x00000001 /* Initiator available */ +#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ +#define TP_ITYP_TYPE_ARM 0x0 +#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ +#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ +#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ +#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ +#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ +#define TY_ITYP_VER_A7 0x1 +#define TY_ITYP_VER_A53 0x2 +#define TY_ITYP_VER_A57 0x3 +#define TY_ITYP_VER_A72 0x4 + +#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ +#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ +#define TP_INIT_PER_CLUSTER 4 +/* This is chassis generation 3 */ +#ifndef __ASSEMBLY__ +struct sys_info { + unsigned long freq_processor[CONFIG_MAX_CPUS]; + /* frequency of platform PLL */ + unsigned long freq_systembus; + unsigned long freq_ddrbus; + unsigned long freq_cga_m2; +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR + unsigned long freq_ddrbus2; +#endif + unsigned long freq_localbus; + unsigned long freq_qe; +#ifdef CONFIG_SYS_DPAA_FMAN + unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; +#endif +#ifdef CONFIG_SYS_DPAA_QBMAN + unsigned long freq_qman; +#endif +#ifdef CONFIG_SYS_DPAA_PME + unsigned long freq_pme; +#endif +}; + +/* Global Utilities Block */ +struct ccsr_gur { + u32 porsr1; /* POR status 1 */ + u32 porsr2; /* POR status 2 */ + u8 res_008[0x20-0x8]; + u32 gpporcr1; /* General-purpose POR configuration */ + u32 gpporcr2; /* General-purpose POR configuration 2 */ + u32 gpporcr3; + u32 gpporcr4; + u8 res_030[0x60-0x30]; +#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F +#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F +#if defined(CONFIG_ARCH_LS1088A) +#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25 +#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20 +#else +#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2 +#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7 +#endif + u32 dcfg_fusesr; /* Fuse status register */ + u8 res_064[0x70-0x64]; + u32 devdisr; /* Device disable control 1 */ + u32 devdisr2; /* Device disable control 2 */ + u32 devdisr3; /* Device disable control 3 */ + u32 devdisr4; /* Device disable control 4 */ + u32 devdisr5; /* Device disable control 5 */ + u32 devdisr6; /* Device disable control 6 */ + u8 res_088[0x94-0x88]; + u32 coredisr; /* Device disable control 7 */ +#define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001 +#define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002 +#define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004 +#define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008 +#define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010 +#define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020 +#define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040 +#define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080 +#define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100 +#define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200 +#define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400 +#define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800 +#define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000 + u8 res_098[0xa0-0x98]; + u32 pvr; /* Processor version */ + u32 svr; /* System version */ + u8 res_0a8[0x100-0xa8]; + u32 rcwsr[30]; /* Reset control word status */ + +#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2 +#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f +#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10 +#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f +#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 +#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f + +#if defined(CONFIG_ARCH_LS2080A) +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000 +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24 +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK +#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS1_REGSR 29 +#define FSL_CHASSIS3_SRDS2_REGSR 29 +#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) +#define FSL_CHASSIS3_EC1_REGSR 27 +#define FSL_CHASSIS3_EC2_REGSR 27 +#define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003 +#define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT 0 +#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x0000000C +#define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT 2 +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000 +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0x03E00000 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 21 +#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK 0x7C000000 +#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT 26 +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK +#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS3_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK +#define FSL_CHASSIS3_SRDS3_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS1_REGSR 29 +#define FSL_CHASSIS3_SRDS2_REGSR 29 +#define FSL_CHASSIS3_SRDS3_REGSR 29 +#define FSL_CHASSIS3_RCWSR12_REGSR 12 +#define FSL_CHASSIS3_RCWSR13_REGSR 13 +#define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK 0x07000000 +#define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24 +#define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK 0x00000038 +#define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3 +#define FSL_CHASSIS3_IIC5_PMUX_MASK 0x00000E00 +#define FSL_CHASSIS3_IIC5_PMUX_SHIFT 9 +#elif defined(CONFIG_ARCH_LS1088A) +#define FSL_CHASSIS3_EC1_REGSR 26 +#define FSL_CHASSIS3_EC2_REGSR 26 +#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007 +#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0 +#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038 +#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3 +#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000 +#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF +#define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT 0 +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK +#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS1_REGSR 29 +#define FSL_CHASSIS3_SRDS2_REGSR 30 +#elif defined(CONFIG_ARCH_LS1028A) +#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000 +#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS1_REGSR 29 +#endif +#define RCW_SB_EN_REG_INDEX 9 +#define RCW_SB_EN_MASK 0x00000400 + + u8 res_178[0x200-0x178]; + u32 scratchrw[16]; /* Scratch Read/Write */ + u8 res_240[0x300-0x240]; + u32 scratchw1r[4]; /* Scratch Read (Write once) */ + u8 res_310[0x400-0x310]; + u32 bootlocptrl; /* Boot location pointer low-order addr */ + u32 bootlocptrh; /* Boot location pointer high-order addr */ + u8 res_408[0x520-0x408]; + u32 usb1_amqr; + u32 usb2_amqr; + u8 res_528[0x530-0x528]; /* add more registers when needed */ + u32 sdmm1_amqr; + u32 sdmm2_amqr; + u8 res_538[0x550 - 0x538]; /* add more registers when needed */ + u32 sata1_amqr; + u32 sata2_amqr; + u32 sata3_amqr; + u32 sata4_amqr; + u8 res_560[0x570 - 0x560]; /* add more registers when needed */ + u32 misc1_amqr; + u8 res_574[0x590-0x574]; /* add more registers when needed */ + u32 spare1_amqr; + u32 spare2_amqr; + u32 spare3_amqr; + u8 res_59c[0x620 - 0x59c]; /* add more registers when needed */ + u32 gencr[7]; /* General Control Registers */ + u8 res_63c[0x640-0x63c]; /* add more registers when needed */ + u32 cgensr1; /* Core General Status Register */ + u8 res_644[0x660-0x644]; /* add more registers when needed */ + u32 cgencr1; /* Core General Control Register */ + u8 res_664[0x740-0x664]; /* add more registers when needed */ + u32 tp_ityp[64]; /* Topology Initiator Type Register */ + struct { + u32 upper; + u32 lower; + } tp_cluster[4]; /* Core cluster n Topology Register */ + u8 res_864[0x920-0x864]; /* add more registers when needed */ + u32 ioqoscr[8]; /*I/O Quality of Services Register */ + u32 uccr; + u8 res_944[0x960-0x944]; /* add more registers when needed */ + u32 ftmcr; + u8 res_964[0x990-0x964]; /* add more registers when needed */ + u32 coredisablesr; + u8 res_994[0xa00-0x994]; /* add more registers when needed */ + u32 sdbgcr; /*Secure Debug Confifuration Register */ + u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */ + u32 ipbrr1; + u32 ipbrr2; + u8 res_858[0x1000-0xc00]; +}; + +struct ccsr_clk_cluster_group { + struct { + u8 res_00[0x10]; + u32 csr; + u8 res_14[0x20-0x14]; + } hwncsr[3]; + u8 res_60[0x80-0x60]; + struct { + u32 gsr; + u8 res_84[0xa0-0x84]; + } pllngsr[3]; + u8 res_e0[0x100-0xe0]; +}; + +struct ccsr_clk_ctrl { + struct { + u32 csr; /* core cluster n clock control status */ + u8 res_04[0x20-0x04]; + } clkcncsr[8]; +}; + +struct ccsr_reset { + u32 rstcr; /* 0x000 */ + u32 rstcrsp; /* 0x004 */ + u8 res_008[0x10-0x08]; /* 0x008 */ + u32 rstrqmr1; /* 0x010 */ + u32 rstrqmr2; /* 0x014 */ + u32 rstrqsr1; /* 0x018 */ + u32 rstrqsr2; /* 0x01c */ + u32 rstrqwdtmrl; /* 0x020 */ + u32 rstrqwdtmru; /* 0x024 */ + u8 res_028[0x30-0x28]; /* 0x028 */ + u32 rstrqwdtsrl; /* 0x030 */ + u32 rstrqwdtsru; /* 0x034 */ + u8 res_038[0x60-0x38]; /* 0x038 */ + u32 brrl; /* 0x060 */ + u32 brru; /* 0x064 */ + u8 res_068[0x80-0x68]; /* 0x068 */ + u32 pirset; /* 0x080 */ + u32 pirclr; /* 0x084 */ + u8 res_088[0x90-0x88]; /* 0x088 */ + u32 brcorenbr; /* 0x090 */ + u8 res_094[0x100-0x94]; /* 0x094 */ + u32 rcw_reqr; /* 0x100 */ + u32 rcw_completion; /* 0x104 */ + u8 res_108[0x110-0x108]; /* 0x108 */ + u32 pbi_reqr; /* 0x110 */ + u32 pbi_completion; /* 0x114 */ + u8 res_118[0xa00-0x118]; /* 0x118 */ + u32 qmbm_warmrst; /* 0xa00 */ + u32 soc_warmrst; /* 0xa04 */ + u8 res_a08[0xbf8-0xa08]; /* 0xa08 */ + u32 ip_rev1; /* 0xbf8 */ + u32 ip_rev2; /* 0xbfc */ +}; + +struct ccsr_serdes { + struct { + u32 rstctl; /* Reset Control Register */ + u32 pllcr0; /* PLL Control Register 0 */ + u32 pllcr1; /* PLL Control Register 1 */ + u32 pllcr2; /* PLL Control Register 2 */ + u32 pllcr3; /* PLL Control Register 3 */ + u32 pllcr4; /* PLL Control Register 4 */ + u32 pllcr5; /* PLL Control Register 5 */ + u8 res[0x20 - 0x1c]; + } bank[2]; + u8 res1[0x90 - 0x40]; + u32 srdstcalcr; /* TX Calibration Control */ + u32 srdstcalcr1; /* TX Calibration Control1 */ + u8 res2[0xa0 - 0x98]; + u32 srdsrcalcr; /* RX Calibration Control */ + u32 srdsrcalcr1; /* RX Calibration Control1 */ + u8 res3[0xb0 - 0xa8]; + u32 srdsgr0; /* General Register 0 */ + u8 res4[0x800 - 0xb4]; + struct serdes_lane { + u32 gcr0; /* General Control Register 0 */ + u32 gcr1; /* General Control Register 1 */ + u32 gcr2; /* General Control Register 2 */ + u32 ssc0; /* Speed Switch Control 0 */ + u32 rec0; /* Receive Equalization Control 0 */ + u32 rec1; /* Receive Equalization Control 1 */ + u32 tec0; /* Transmit Equalization Control 0 */ + u32 ssc1; /* Speed Switch Control 1 */ + u8 res1[0x840 - 0x820]; + } lane[8]; + u8 res5[0x19fc - 0xa00]; +}; + +struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; + u32 gpibe; +}; + +#endif /*__ASSEMBLY__ */ +#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h new file mode 100644 index 000000000..d709af8f7 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + */ + +#ifndef __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ +#define __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ + +#define I2C_QUIRK_REG /* enable 8-bit driver */ + +#endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/mmu.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/mmu.h new file mode 100644 index 000000000..661cdeafd --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/mmu.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015, Freescale Semiconductor + */ + +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ +#define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ +void update_early_mmu_table(void); +#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/mp.h new file mode 100644 index 000000000..faac8f112 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014-2015, Freescale Semiconductor + */ + +#ifndef _FSL_LAYERSCAPE_MP_H +#define _FSL_LAYERSCAPE_MP_H + +/* +* Each spin table element is defined as +* struct { +* uint64_t entry_addr; +* uint64_t status; +* uint64_t lpid; +* uint64_t arch_comp; +* }; +* we pad this struct to 64 bytes so each entry is in its own cacheline +* the actual spin table is an array of these structures +*/ +#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0 +#define SPIN_TABLE_ELEM_STATUS_IDX 1 +#define SPIN_TABLE_ELEM_LPID_IDX 2 +/* compare os arch and cpu arch */ +#define SPIN_TABLE_ELEM_ARCH_COMP_IDX 3 +#define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */ +#define SPIN_TABLE_ELEM_SIZE 64 + +/* os arch is same as cpu arch */ +#define OS_ARCH_SAME 0 +/* os arch is different from cpu arch */ +#define OS_ARCH_DIFF 1 + +#define id_to_core(x) ((x & 3) | (x >> 6)) +#ifndef __ASSEMBLY__ +extern u64 __real_cntfrq; +extern void *secondary_boot_addr; +extern void *secondary_boot_code_start; +extern size_t secondary_boot_code_size; +#ifdef CONFIG_MP +int fsl_layerscape_wake_seconday_cores(void); +#else +static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; } +#endif +void *get_spin_tbl_addr(void); +int is_core_online(u64 cpu_id); +u32 cpu_pos_mask(void); +#endif + +#endif /* _FSL_LAYERSCAPE_MP_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h new file mode 100644 index 000000000..a26510668 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __FSL_NS_ACCESS_H_ +#define __FSL_NS_ACCESS_H_ +#include + +enum csu_cslx_ind { + CSU_CSLX_PCIE2_IO = 0, + CSU_CSLX_PCIE1_IO, + CSU_CSLX_MG2TPR_IP, + CSU_CSLX_IFC_MEM, + CSU_CSLX_OCRAM, + CSU_CSLX_GIC, + CSU_CSLX_PCIE1, + CSU_CSLX_OCRAM2, + CSU_CSLX_QSPI_MEM, + CSU_CSLX_PCIE2, + CSU_CSLX_SATA, + CSU_CSLX_USB1, + CSU_CSLX_QM_BM_SWPORTAL, + CSU_CSLX_PCIE3 = 16, + CSU_CSLX_PCIE3_IO, + CSU_CSLX_USB3 = 20, + CSU_CSLX_USB2, + CSU_CSLX_PFE = 23, + CSU_CSLX_SERDES = 32, + CSU_CSLX_QDMA, + CSU_CSLX_LPUART2, + CSU_CSLX_LPUART1, + CSU_CSLX_LPUART4, + CSU_CSLX_LPUART3, + CSU_CSLX_LPUART6, + CSU_CSLX_LPUART5, + CSU_CSLX_DSPI1 = 41, + CSU_CSLX_QSPI, + CSU_CSLX_ESDHC, + CSU_CSLX_IFC = 45, + CSU_CSLX_I2C1, + CSU_CSLX_USB_2, + CSU_CSLX_I2C3 = 48, + CSU_CSLX_I2C2, + CSU_CSLX_DUART2 = 50, + CSU_CSLX_DUART1, + CSU_CSLX_WDT2, + CSU_CSLX_WDT1, + CSU_CSLX_EDMA, + CSU_CSLX_SYS_CNT, + CSU_CSLX_DMA_MUX2, + CSU_CSLX_DMA_MUX1, + CSU_CSLX_DDR, + CSU_CSLX_QUICC, + CSU_CSLX_DCFG_CCU_RCPM = 60, + CSU_CSLX_SECURE_BOOTROM, + CSU_CSLX_SFP, + CSU_CSLX_TMU, + CSU_CSLX_SECURE_MONITOR, + CSU_CSLX_SCFG, + CSU_CSLX_FM = 66, + CSU_CSLX_SEC5_5, + CSU_CSLX_BM, + CSU_CSLX_QM, + CSU_CSLX_GPIO2 = 70, + CSU_CSLX_GPIO1, + CSU_CSLX_GPIO4, + CSU_CSLX_GPIO3, + CSU_CSLX_PLATFORM_CONT, + CSU_CSLX_CSU, + CSU_CSLX_IIC4 = 77, + CSU_CSLX_WDT4, + CSU_CSLX_WDT3, + CSU_CSLX_ESDHC2 = 80, + CSU_CSLX_WDT5 = 81, + CSU_CSLX_SAI2, + CSU_CSLX_SAI1, + CSU_CSLX_SAI4, + CSU_CSLX_SAI3, + CSU_CSLX_FTM2 = 86, + CSU_CSLX_FTM1, + CSU_CSLX_FTM4, + CSU_CSLX_FTM3, + CSU_CSLX_FTM6 = 90, + CSU_CSLX_FTM5, + CSU_CSLX_FTM8, + CSU_CSLX_FTM7, + CSU_CSLX_DSCR = 121, +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/ppa.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/ppa.h new file mode 100644 index 000000000..f0c4a84f7 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/ppa.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 NXP Semiconductor, Inc. + */ + +#ifndef __FSL_PPA_H_ +#define __FSL_PPA_H_ + +#ifdef CONFIG_FSL_LS_PPA +int ppa_init(void); +#endif +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/soc.h new file mode 100644 index 000000000..bd41df1be --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017-2021 NXP + * Copyright 2015 Freescale Semiconductor + */ + +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ +#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ + +#ifndef __ASSEMBLY__ +#include +#ifdef CONFIG_FSL_LSCH2 +#include +#endif +#ifdef CONFIG_FSL_LSCH3 +#include +#endif +#endif +#include + +#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE +#define gur_in32(a) in_le32(a) +#define gur_out32(a, v) out_le32(a, v) +#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE) +#define gur_in32(a) in_be32(a) +#define gur_out32(a, v) out_be32(a, v) +#endif + +#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE +#define scfg_in32(a) in_le32(a) +#define scfg_out32(a, v) out_le32(a, v) +#define scfg_clrbits32(addr, clear) clrbits_le32(addr, clear) +#define scfg_clrsetbits32(addr, clear, set) clrsetbits_le32(addr, clear, set) +#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE) +#define scfg_in32(a) in_be32(a) +#define scfg_out32(a, v) out_be32(a, v) +#define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear) +#define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set) +#endif + +#ifdef CONFIG_SYS_FSL_PEX_LUT_LE +#define pex_lut_in32(a) in_le32(a) +#define pex_lut_out32(a, v) out_le32(a, v) +#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE) +#define pex_lut_in32(a) in_be32(a) +#define pex_lut_out32(a, v) out_be32(a, v) +#endif +#ifndef __ASSEMBLY__ +struct cpu_type { + char name[15]; + u32 soc_ver; + u32 num_cores; +}; + +#define CPU_TYPE_ENTRY(n, v, nc) \ + { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} + +#ifdef CONFIG_TFABOOT +#define SMC_DRAM_BANK_INFO (0xC200FF12) +#define SIP_SVC_RCW 0xC200FF18 + +phys_size_t tfa_get_dram_size(void); + +enum boot_src { + BOOT_SOURCE_RESERVED = 0, + BOOT_SOURCE_IFC_NOR, + BOOT_SOURCE_IFC_NAND, + BOOT_SOURCE_QSPI_NOR, + BOOT_SOURCE_QSPI_NAND, + BOOT_SOURCE_XSPI_NOR, + BOOT_SOURCE_XSPI_NAND, + BOOT_SOURCE_SD_MMC, + BOOT_SOURCE_SD_MMC2, + BOOT_SOURCE_I2C1_EXTENDED, +}; + +enum boot_src get_boot_src(void); +#endif +#endif +#define SVR_WO_E 0xFFFFFE + +#define SVR_MAJ(svr) (((svr) >> 4) & 0xf) +#define SVR_MIN(svr) (((svr) >> 0) & 0xf) +#define SVR_REV(svr) (((svr) >> 0) & 0xff) +#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) +#define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1)) +#define SVR_WO_CE 0xFFFFEE +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_CE) +#else +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) +#endif +#ifdef CONFIG_ARCH_LS1028A +#define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1)) +#endif +#define IS_SVR_REV(svr, maj, min) \ + ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) +#define SVR_DEV(svr) ((svr) >> 8) +#define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev)) + +#ifndef __ASSEMBLY__ +#ifdef CONFIG_FSL_LSCH3 +void fsl_lsch3_early_init_f(void); +int get_core_volt_from_fuse(void); +#elif defined(CONFIG_FSL_LSCH2) +void fsl_lsch2_early_init_f(void); +int setup_chip_volt(void); +/* Setup core vdd in unit mV */ +int board_setup_core_volt(u32 vdd); +#ifdef CONFIG_FSL_PFE +void init_pfe_scfg_dcfg_regs(void); +#endif +#endif +#ifdef CONFIG_QSPI_AHB_INIT +int qspi_ahb_init(void); +#endif + +#ifdef CONFIG_FSPI_AHB_EN_4BYTE +#define SYS_NXP_FSPI_LUTCR_LOCK 0x00000001 +#define SYS_NXP_FSPI_LUTCR_UNLOCK 0x00000002 +#define SYS_NXP_FSPI_LUTKEY 0x5AF05AF0 +int fspi_ahb_init(void); +#endif + +void cpu_name(char *name); +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 +void erratum_a009635(void); +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 +void erratum_a010315(void); +#endif + +bool soc_has_dp_ddr(void); +bool soc_has_aiop(void); + +#ifdef CONFIG_GIC_V3_ITS +int ls_gic_rd_tables_init(void *blob); +#endif +#endif + +#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/speed.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/speed.h new file mode 100644 index 000000000..26721699c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/speed.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014-2015, Freescale Semiconductor, Inc. + */ + +#ifndef _FSL_LAYERSCAPE_SPEED_H +#define _FSL_LAYERSCAPE_SPEED_H +void get_sys_info(struct sys_info *sys_info); +#ifdef CONFIG_SYS_DPAA_QBMAN +unsigned long get_qman_freq(void); +#endif +#endif /* _FSL_LAYERSCAPE_SPEED_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h new file mode 100644 index 000000000..1b02d484d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP Semiconductor, Inc. + * + */ +#ifndef __FSL_STREAM_ID_H +#define __FSL_STREAM_ID_H + +/* + * Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices + * are not hardwired and are programmed by sw. There are a limited number + * of stream IDs available, and the partitioning of them is scenario + * dependent. This header defines the partitioning between legacy, PCI, + * and DPAA1 devices. + * + * This partitioning can be customized in this file depending + * on the specific hardware config: + * + * -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc) + * -all legacy devices get a unique stream ID assigned and programmed in + * their AMQR registers by u-boot + * + * -PCIe + * -there is a range of stream IDs set aside for PCI in this + * file. U-boot will scan the PCI bus and for each device discovered: + * -allocate a streamID + * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' + * -set a msi-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt + * for more info on the msi-map definition) + * -set a iommu-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt + * for more info on the iommu-map definition) + * + * -DPAA1 + * - Stream ids for DPAA1 use are reserved for future usecase. + * + */ + + +#define FSL_INVALID_STREAM_ID 0 + +/* legacy devices */ +#define FSL_USB1_STREAM_ID 1 +#define FSL_USB2_STREAM_ID 2 +#define FSL_USB3_STREAM_ID 3 +#define FSL_SDHC_STREAM_ID 4 +#define FSL_SATA_STREAM_ID 5 +#define FSL_QE_STREAM_ID 6 +#define FSL_QDMA_STREAM_ID 7 +#define FSL_EDMA_STREAM_ID 8 +#define FSL_ETR_STREAM_ID 9 +#define FSL_DEBUG_STREAM_ID 10 + +/* PCI - programmed in PEXn_LUT */ +#define FSL_PEX_STREAM_ID_START 11 +#define FSL_PEX_STREAM_ID_END 26 + +/* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */ +#define FSL_DPAA1_STREAM_ID_START 27 +#define FSL_DPAA1_STREAM_ID_END 63 + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h new file mode 100644 index 000000000..b36b6d388 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015-2021 NXP + * Copyright 2014 Freescale Semiconductor, Inc. + * + */ +#ifndef __FSL_STREAM_ID_H +#define __FSL_STREAM_ID_H + +/* + * Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a) + * devices are not hardwired and are programmed by sw. There are a limited + * number of stream IDs available, and the partitioning of them is scenario + * dependent. This header defines the partitioning between legacy, + * PCI, and DPAA2 devices. + * + * This partitioning can be customized in this file depending + * on the specific hardware config: + * + * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA) + * -all legacy devices get a unique stream ID assigned and programmed in + * their AMQR registers by u-boot + * + * -PCIe + * -there is a range of stream IDs set aside for PCI in this + * file. U-boot will scan the PCI bus and for each device discovered: + * -allocate a streamID + * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' + * -set a msi-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt + * for more info on the msi-map definition) + * -set a iommu-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt + * for more info on the iommu-map definition) + * + * -DPAA2 + * -u-boot will allocate a range of stream IDs to be used by the Management + * Complex for containers and will set these values in the MC DPC image. + * -u-boot will fixup the iommu-map property in the fsl-mc node in the + * device tree (see Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt + * for more info on the msi-map definition) + * -the MC is responsible for allocating and setting up 'isolation context + * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. + * + * - ECAM (integrated PCI) + * - U-Boot applies the value here to HW and does DT fix-up for both + * 'iommu-map' and 'msi-map' + * + * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for + * each of the different bus masters. The relationship between + * the AMQ registers and stream IDs is defined in the table below: + * AMQ bit streamID bit + * --------------------------- + * PL[18] 9 // privilege bit + * BMT[17] 8 // bypass translation + * VA[16] 7 // reserved + * [15] - // unused + * ICID[14:7] - // unused + * ICID[6:0] 6-0 // isolation context id + * ---------------------------- + * + */ + +#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */ +#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */ + +#define FSL_INVALID_STREAM_ID 0 + +#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK) + +/* legacy devices */ +#define FSL_USB1_STREAM_ID 1 +#define FSL_USB2_STREAM_ID 2 +#define FSL_SDMMC_STREAM_ID 3 +#define FSL_SATA1_STREAM_ID 4 + +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \ + defined(CONFIG_ARCH_LX2162A) +#define FSL_SATA2_STREAM_ID 5 +#endif + +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \ + defined(CONFIG_ARCH_LX2162A) +#define FSL_DMA_STREAM_ID 6 +#elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) +#define FSL_DMA_STREAM_ID 5 +#endif + +/* PCI - programmed in PEXn_LUT */ +#define FSL_PEX_STREAM_ID_START 7 + +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1028A) +#define FSL_PEX_STREAM_ID_END 22 +#elif defined(CONFIG_ARCH_LS1088A) +#define FSL_PEX_STREAM_ID_END 18 +#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) +#define FSL_PEX_STREAM_ID_END (0x100) +#endif + + +/* DPAA2 - set in MC DPC and alloced by MC */ +#define FSL_DPAA2_STREAM_ID_START 23 +#define FSL_DPAA2_STREAM_ID_END 63 + +/* PCI IEPs, this overlaps DPAA2 but these two are exclusive at least for now */ +#define FSL_ECAM_STREAM_ID_START 41 +#define FSL_ECAM_STREAM_ID_END 63 + +#define FSL_SEC_STREAM_ID 64 +#define FSL_SEC_JR1_STREAM_ID 65 +#define FSL_SEC_JR2_STREAM_ID 66 +#define FSL_SEC_JR3_STREAM_ID 67 +#define FSL_SEC_JR4_STREAM_ID 68 + +#define FSL_SDMMC2_STREAM_ID 69 + +/* + * Erratum A-050382 workaround + * + * Description: + * The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not + * correctly forwarded to the SMMU. + * Workaround: + * Program eDMA ICID in the eDMA_AMQR register in DCFG to 40. + */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A050382 +#define FSL_EDMA_STREAM_ID 40 +#else +#define FSL_EDMA_STREAM_ID 70 +#endif + +#define FSL_GPU_STREAM_ID 71 +#define FSL_DISPLAY_STREAM_ID 72 +#define FSL_SATA3_STREAM_ID 73 +#define FSL_SATA4_STREAM_ID 74 + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/svr.h b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/svr.h new file mode 100644 index 000000000..e37c4a88b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-fsl-layerscape/svr.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ +#define _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ + +#define SVR_LS1012A 0x870400 +#define SVR_LS1043A 0x879200 +#define SVR_LS1023A 0x879208 +/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ +#define SVR_LS1043A_P23 0x879202 +#define SVR_LS1023A_P23 0x87920A +#define SVR_LS1017A 0x870B24 +#define SVR_LS1018A 0x870B20 +#define SVR_LS1027A 0x870B04 +#define SVR_LS1028A 0x870B00 +#define SVR_LS1046A 0x870700 +#define SVR_LS1026A 0x870708 +#define SVR_LS1048A 0x870320 +#define SVR_LS1084A 0x870302 +#define SVR_LS1088A 0x870300 +#define SVR_LS1044A 0x870322 +#define SVR_LS2045A 0x870120 +#define SVR_LS2080A 0x870110 +#define SVR_LS2085A 0x870100 +#define SVR_LS2040A 0x870130 +#define SVR_LS2088A 0x870900 +#define SVR_LS2084A 0x870910 +#define SVR_LS2048A 0x870920 +#define SVR_LS2044A 0x870930 +#define SVR_LS2081A 0x870918 +#define SVR_LS2041A 0x870914 +#define SVR_LX2160A 0x873600 +#define SVR_LX2120A 0x873620 +#define SVR_LX2080A 0x873602 +#define SVR_LX2162A 0x873608 +#define SVR_LX2122A 0x873628 +#define SVR_LX2082A 0x87360A + +#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-hi3660/hi3660.h b/roms/u-boot/arch/arm/include/asm/arch-hi3660/hi3660.h new file mode 100644 index 000000000..882262d13 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-hi3660/hi3660.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Linaro + * Author: Manivannan Sadhasivam + */ + +#ifndef __HI3660_H__ +#define __HI3660_H__ + +#ifndef __ASSEMBLY__ +#include +#endif + +#define HI3660_UART6_BASE 0xfff32000 + +#define PMU_REG_BASE 0xfff34000 +#define PMIC_HARDWARE_CTRL0 (PMU_REG_BASE + (0x0C5 << 2)) + +#define SCTRL_REG_BASE 0xfff0a000 +#define SCTRL_SCFPLLCTRL0 (SCTRL_REG_BASE + 0x120) +#define SCTRL_SCFPLLCTRL0_FPLL0_EN BIT(0) + +#define CRG_REG_BASE 0xfff35000 +#define CRG_PEREN2 (CRG_REG_BASE + 0x020) +#define CRG_PERDIS2 (CRG_REG_BASE + 0x024) +#define CRG_PERCLKEN2 (CRG_REG_BASE + 0x028) +#define CRG_PERSTAT2 (CRG_REG_BASE + 0x02C) +#define CRG_PEREN4 (CRG_REG_BASE + 0x040) +#define CRG_PERDIS4 (CRG_REG_BASE + 0x044) +#define CRG_PERCLKEN4 (CRG_REG_BASE + 0x048) +#define CRG_PERSTAT4 (CRG_REG_BASE + 0x04C) +#define CRG_PERRSTEN2 (CRG_REG_BASE + 0x078) +#define CRG_PERRSTDIS2 (CRG_REG_BASE + 0x07C) +#define CRG_PERRSTSTAT2 (CRG_REG_BASE + 0x080) +#define CRG_PERRSTEN3 (CRG_REG_BASE + 0x084) +#define CRG_PERRSTDIS3 (CRG_REG_BASE + 0x088) +#define CRG_PERRSTSTAT3 (CRG_REG_BASE + 0x08C) +#define CRG_PERRSTEN4 (CRG_REG_BASE + 0x090) +#define CRG_PERRSTDIS4 (CRG_REG_BASE + 0x094) +#define CRG_PERRSTSTAT4 (CRG_REG_BASE + 0x098) +#define CRG_ISOEN (CRG_REG_BASE + 0x144) +#define CRG_ISODIS (CRG_REG_BASE + 0x148) +#define CRG_ISOSTAT (CRG_REG_BASE + 0x14C) + +#define PINMUX4_BASE 0xfff11000 +#define PINMUX4_SDDET (PINMUX4_BASE + 0x60) + +#define PINCONF3_BASE 0xff37e800 +#define PINCONF3_SDCLK (PINCONF3_BASE + 0x00) +#define PINCONF3_SDCMD (PINCONF3_BASE + 0x04) +#define PINCONF3_SDDATA0 (PINCONF3_BASE + 0x08) +#define PINCONF3_SDDATA1 (PINCONF3_BASE + 0x0c) +#define PINCONF3_SDDATA2 (PINCONF3_BASE + 0x10) +#define PINCONF3_SDDATA3 (PINCONF3_BASE + 0x14) + +#endif /*__HI3660_H__*/ diff --git a/roms/u-boot/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h b/roms/u-boot/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h new file mode 100644 index 000000000..b98b45cc8 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Linaro + * Jorge Ramirez-Ortiz + */ + +#ifndef __HI3798cv200_H__ +#define __HI3798cv200_H__ + +#define REG_BASE_PERI_CTRL 0xF8A20000 +#define REG_BASE_CRG 0xF8A22000 + +/* DEVICES */ +#define REG_BASE_UART0 0xF8B00000 +#define HIOTG_BASE_ADDR 0xF98C0000 + +/* PERI control registers (4KB) */ + /* USB2 PHY01 configuration register */ +#define PERI_CTRL_USB0 (REG_BASE_PERI_CTRL + 0x120) + + /* USB2 controller configuration register */ +#define PERI_CTRL_USB3 (REG_BASE_PERI_CTRL + 0x12c) +#define USB2_2P_CHIPID (1 << 28) + +/* PERI CRG registers (4KB) */ + /* USB2 CTRL0 clock and soft reset */ +#define PERI_CRG46 (REG_BASE_CRG + 0xb8) +#define USB2_BUS_CKEN (1<<0) +#define USB2_OHCI48M_CKEN (1<<1) +#define USB2_OHCI12M_CKEN (1<<2) +#define USB2_OTG_UTMI_CKEN (1<<3) +#define USB2_HST_PHY_CKEN (1<<4) +#define USB2_UTMI0_CKEN (1<<5) +#define USB2_BUS_SRST_REQ (1<<12) +#define USB2_UTMI0_SRST_REQ (1<<13) +#define USB2_HST_PHY_SYST_REQ (1<<16) +#define USB2_OTG_PHY_SYST_REQ (1<<17) +#define USB2_CLK48_SEL (1<<20) + + /* USB2 PHY clock and soft reset */ +#define PERI_CRG47 (REG_BASE_CRG + 0xbc) +#define USB2_PHY01_REF_CKEN (1 << 0) +#define USB2_PHY2_REF_CKEN (1 << 2) +#define USB2_PHY01_SRST_REQ (1 << 4) +#define USB2_PHY2_SRST_REQ (1 << 6) +#define USB2_PHY01_SRST_TREQ0 (1 << 8) +#define USB2_PHY01_SRST_TREQ1 (1 << 9) +#define USB2_PHY2_SRST_TREQ (1 << 10) +#define USB2_PHY01_REFCLK_SEL (1 << 12) +#define USB2_PHY2_REFCLK_SEL (1 << 14) + + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-hi6220/dwmmc.h b/roms/u-boot/arch/arm/include/asm/arch-hi6220/dwmmc.h new file mode 100644 index 000000000..cf51c178c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-hi6220/dwmmc.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Linaro + * Peter Griffin + */ + +int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width); diff --git a/roms/u-boot/arch/arm/include/asm/arch-hi6220/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-hi6220/gpio.h new file mode 100644 index 000000000..12717a96a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-hi6220/gpio.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Linaro + * Peter Griffin + */ + +#ifndef _HI6220_GPIO_H_ +#define _HI6220_GPIO_H_ + +#define HI6220_GPIO_BASE(bank) (((bank < 4) ? 0xf8011000 : \ + 0xf7020000 - 0x4000) + (0x1000 * bank)) + +#define HI6220_GPIO_PER_BANK 8 +#define HI6220_GPIO_DIR 0x400 + +struct gpio_bank { + u8 *base; /* address of registers in physical memory */ +}; + +/* Information about a GPIO bank */ +struct hikey_gpio_plat { + int bank_index; + ulong base; /* address of registers in physical memory */ +}; + +#endif /* _HI6220_GPIO_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-hi6220/hi6220.h b/roms/u-boot/arch/arm/include/asm/arch-hi6220/hi6220.h new file mode 100644 index 000000000..55729e306 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-hi6220/hi6220.h @@ -0,0 +1,389 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Linaro + * Peter Griffin + */ + +#ifndef __HI6220_H__ +#define __HI6220_H__ + +#include "hi6220_regs_alwayson.h" + +#define HI6220_MMC0_BASE 0xF723D000 +#define HI6220_MMC1_BASE 0xF723E000 + +#define HI6220_UART0_BASE 0xF8015000 +#define HI6220_UART3_BASE 0xF7113000 + +#define HI6220_PMUSSI_BASE 0xF8000000 + +#define HI6220_PERI_BASE 0xF7030000 + +struct peri_sc_periph_regs { + u32 ctrl1; /*0x0*/ + u32 ctrl2; + u32 ctrl3; + u32 ctrl4; + u32 ctrl5; + u32 ctrl6; + u32 ctrl8; + u32 ctrl9; + u32 ctrl10; + u32 ctrl12; + u32 ctrl13; + u32 ctrl14; + + u32 unknown_1[8]; + + u32 ddr_ctrl0; /*0x50*/ + + u32 unknown_2[16]; + + u32 stat1; /*0x94*/ + + u32 unknown_3[90]; + + u32 clk0_en; /*0x200*/ + u32 clk0_dis; + u32 clk0_stat; + + u32 unknown_4; + + u32 clk1_en; /*0x210*/ + u32 clk1_dis; + u32 clk1_stat; + + u32 unknown_5; + + u32 clk2_en; /*0x220*/ + u32 clk2_dis; + u32 clk2_stat; + + u32 unknown_6; + + u32 clk3_en; /*0x230*/ + u32 clk3_dis; + u32 clk3_stat; + + u32 unknown_7; + + u32 clk8_en; /*0x240*/ + u32 clk8_dis; + u32 clk8_stat; + + u32 unknown_8; + + u32 clk9_en; /*0x250*/ + u32 clk9_dis; + u32 clk9_stat; + + u32 unknown_9; + + u32 clk10_en; /*0x260*/ + u32 clk10_dis; + u32 clk10_stat; + + u32 unknown_10; + + u32 clk12_en; /*0x270*/ + u32 clk12_dis; + u32 clk12_stat; + + u32 unknown_11[33]; + + u32 rst0_en; /*0x300*/ + u32 rst0_dis; + u32 rst0_stat; + + u32 unknown_12; + + u32 rst1_en; /*0x310*/ + u32 rst1_dis; + u32 rst1_stat; + + u32 unknown_13; + + u32 rst2_en; /*0x320*/ + u32 rst2_dis; + u32 rst2_stat; + + u32 unknown_14; + + u32 rst3_en; /*0x330*/ + u32 rst3_dis; + u32 rst3_stat; + + u32 unknown_15; + + u32 rst8_en; /*0x340*/ + u32 rst8_dis; + u32 rst8_stat; + + u32 unknown_16[45]; + + u32 clk0_sel; /*0x400*/ + + u32 unknown_17[36]; + + u32 clkcfg8bit1; /*0x494*/ + u32 clkcfg8bit2; + + u32 unknown_18[538]; + + u32 reserved8_addr; /*0xd04*/ +}; + + +/* CTRL1 bit definitions */ + +#define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0) +#define PERI_CTRL1_HIFI_INT_MASK (1 << 1) +#define PERI_CTRL1_HIFI_ALL_INT_MASK (1 << 2) +#define PERI_CTRL1_ETR_AXI_CSYSREQ_N_MSK (1 << 16) +#define PERI_CTRL1_HIFI_INT_MASK_MSK (1 << 17) +#define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK (1 << 18) + + +/* CTRL2 bit definitions */ + +#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0 (1 << 0) +#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC1 (1 << 2) +#define PERI_CTRL2_NAND_SYS_MEM_SEL (1 << 6) +#define PERI_CTRL2_G3D_DDRT_AXI_SEL (1 << 7) +#define PERI_CTRL2_GU_MDM_BBP_TESTPIN_SEL (1 << 8) +#define PERI_CTRL2_CODEC_SSI_MASTER_CHECK (1 << 9) +#define PERI_CTRL2_FUNC_TEST_SOFT (1 << 12) +#define PERI_CTRL2_CSSYS_TS_ENABLE (1 << 15) +#define PERI_CTRL2_HIFI_RAMCTRL_S_EMA (1 << 16) +#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAW (1 << 20) +#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAS (1 << 22) +#define PERI_CTRL2_HIFI_RAMCTRL_S_RET1N (1 << 26) +#define PERI_CTRL2_HIFI_RAMCTRL_S_RET2N (1 << 27) +#define PERI_CTRL2_HIFI_RAMCTRL_S_PGEN (1 << 28) + +/* CTRL3 bit definitions */ + +#define PERI_CTRL3_HIFI_DDR_HARQMEM_ADDR (1 << 0) +#define PERI_CTRL3_HIFI_HARQMEMRMP_EN (1 << 12) +#define PERI_CTRL3_HARQMEM_SYS_MED_SEL (1 << 13) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP1 (1 << 14) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP2 (1 << 16) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP3 (1 << 18) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP4 (1 << 20) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP5 (1 << 22) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP6 (1 << 24) + +/* CTRL4 bit definitions */ + +#define PERI_CTRL4_PICO_FSELV (1 << 0) +#define PERI_CTRL4_FPGA_EXT_PHY_SEL (1 << 3) +#define PERI_CTRL4_PICO_REFCLKSEL (1 << 4) +#define PERI_CTRL4_PICO_SIDDQ (1 << 6) +#define PERI_CTRL4_PICO_SUSPENDM_SLEEPM (1 << 7) +#define PERI_CTRL4_PICO_OGDISABLE (1 << 8) +#define PERI_CTRL4_PICO_COMMONONN (1 << 9) +#define PERI_CTRL4_PICO_VBUSVLDEXT (1 << 10) +#define PERI_CTRL4_PICO_VBUSVLDEXTSEL (1 << 11) +#define PERI_CTRL4_PICO_VATESTENB (1 << 12) +#define PERI_CTRL4_PICO_SUSPENDM (1 << 14) +#define PERI_CTRL4_PICO_SLEEPM (1 << 15) +#define PERI_CTRL4_BC11_C (1 << 16) +#define PERI_CTRL4_BC11_B (1 << 17) +#define PERI_CTRL4_BC11_A (1 << 18) +#define PERI_CTRL4_BC11_GND (1 << 19) +#define PERI_CTRL4_BC11_FLOAT (1 << 20) +#define PERI_CTRL4_OTG_PHY_SEL (1 << 21) +#define PERI_CTRL4_USB_OTG_SS_SCALEDOWN_MODE (1 << 22) +#define PERI_CTRL4_OTG_DM_PULLDOWN (1 << 24) +#define PERI_CTRL4_OTG_DP_PULLDOWN (1 << 25) +#define PERI_CTRL4_OTG_IDPULLUP (1 << 26) +#define PERI_CTRL4_OTG_DRVBUS (1 << 27) +#define PERI_CTRL4_OTG_SESSEND (1 << 28) +#define PERI_CTRL4_OTG_BVALID (1 << 29) +#define PERI_CTRL4_OTG_AVALID (1 << 30) +#define PERI_CTRL4_OTG_VBUSVALID (1 << 31) + +/* CTRL5 bit definitions */ + +#define PERI_CTRL5_USBOTG_RES_SEL (1 << 3) +#define PERI_CTRL5_PICOPHY_ACAENB (1 << 4) +#define PERI_CTRL5_PICOPHY_BC_MODE (1 << 5) +#define PERI_CTRL5_PICOPHY_CHRGSEL (1 << 6) +#define PERI_CTRL5_PICOPHY_VDATSRCEND (1 << 7) +#define PERI_CTRL5_PICOPHY_VDATDETENB (1 << 8) +#define PERI_CTRL5_PICOPHY_DCDENB (1 << 9) +#define PERI_CTRL5_PICOPHY_IDDIG (1 << 10) +#define PERI_CTRL5_DBG_MUX (1 << 11) + +/* CTRL6 bit definitions */ + +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMA (1 << 0) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAW (1 << 4) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAS (1 << 6) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET1N (1 << 10) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET2N (1 << 11) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_PGEN (1 << 12) + +/* CTRL8 bit definitions */ + +#define PERI_CTRL8_PICOPHY_TXRISETUNE0 (1 << 0) +#define PERI_CTRL8_PICOPHY_TXPREEMPAMPTUNE0 (1 << 2) +#define PERI_CTRL8_PICOPHY_TXRESTUNE0 (1 << 4) +#define PERI_CTRL8_PICOPHY_TXHSSVTUNE0 (1 << 6) +#define PERI_CTRL8_PICOPHY_COMPDISTUNE0 (1 << 8) +#define PERI_CTRL8_PICOPHY_TXPREEMPPULSETUNE0 (1 << 11) +#define PERI_CTRL8_PICOPHY_OTGTUNE0 (1 << 12) +#define PERI_CTRL8_PICOPHY_SQRXTUNE0 (1 << 16) +#define PERI_CTRL8_PICOPHY_TXVREFTUNE0 (1 << 20) +#define PERI_CTRL8_PICOPHY_TXFSLSTUNE0 (1 << 28) + +/* CTRL9 bit definitions */ + +#define PERI_CTRL9_PICOPLY_TESTCLKEN (1 << 0) +#define PERI_CTRL9_PICOPLY_TESTDATAOUTSEL (1 << 1) +#define PERI_CTRL9_PICOPLY_TESTADDR (1 << 4) +#define PERI_CTRL9_PICOPLY_TESTDATAIN (1 << 8) + +/* CLK0 EN/DIS/STAT bit definitions */ + +#define PERI_CLK0_MMC0 (1 << 0) +#define PERI_CLK0_MMC1 (1 << 1) +#define PERI_CLK0_MMC2 (1 << 2) +#define PERI_CLK0_NANDC (1 << 3) +#define PERI_CLK0_USBOTG (1 << 4) +#define PERI_CLK0_PICOPHY (1 << 5) +#define PERI_CLK0_PLL (1 << 6) + +/* CLK1 EN/DIS/STAT bit definitions */ + +#define PERI_CLK1_HIFI (1 << 0) +#define PERI_CLK1_DIGACODEC (1 << 5) + +/* CLK2 EN/DIS/STAT bit definitions */ + +#define PERI_CLK2_IPF (1 << 0) +#define PERI_CLK2_SOCP (1 << 1) +#define PERI_CLK2_DMAC (1 << 2) +#define PERI_CLK2_SECENG (1 << 3) +#define PERI_CLK2_HPM0 (1 << 5) +#define PERI_CLK2_HPM1 (1 << 6) +#define PERI_CLK2_HPM2 (1 << 7) +#define PERI_CLK2_HPM3 (1 << 8) + +/* CLK8 EN/DIS/STAT bit definitions */ + +#define PERI_CLK8_RS0 (1 << 0) +#define PERI_CLK8_RS2 (1 << 1) +#define PERI_CLK8_RS3 (1 << 2) +#define PERI_CLK8_MS0 (1 << 3) +#define PERI_CLK8_MS2 (1 << 5) +#define PERI_CLK8_XG2RAM0 (1 << 6) +#define PERI_CLK8_X2SRAM (1 << 7) +#define PERI_CLK8_SRAM (1 << 8) +#define PERI_CLK8_ROM (1 << 9) +#define PERI_CLK8_HARQ (1 << 10) +#define PERI_CLK8_MMU (1 << 11) +#define PERI_CLK8_DDRC (1 << 12) +#define PERI_CLK8_DDRPHY (1 << 13) +#define PERI_CLK8_DDRPHY_REF (1 << 14) +#define PERI_CLK8_X2X_SYSNOC (1 << 15) +#define PERI_CLK8_X2X_CCPU (1 << 16) +#define PERI_CLK8_DDRT (1 << 17) +#define PERI_CLK8_DDRPACK_RS (1 << 18) + +/* CLK9 EN/DIS/STAT bit definitions */ + +#define PERI_CLK9_CARM_DAP (1 << 0) +#define PERI_CLK9_CARM_ATB (1 << 1) +#define PERI_CLK9_CARM_LBUS (1 << 2) +#define PERI_CLK9_CARM_KERNEL (1 << 3) + +/* CLK10 EN/DIS/STAT bit definitions */ + +#define PERI_CLK10_IPF_CCPU (1 << 0) +#define PERI_CLK10_SOCP_CCPU (1 << 1) +#define PERI_CLK10_SECENG_CCPU (1 << 2) +#define PERI_CLK10_HARQ_CCPU (1 << 3) +#define PERI_CLK10_IPF_MCU (1 << 16) +#define PERI_CLK10_SOCP_MCU (1 << 17) +#define PERI_CLK10_SECENG_MCU (1 << 18) +#define PERI_CLK10_HARQ_MCU (1 << 19) + +/* CLK12 EN/DIS/STAT bit definitions */ + +#define PERI_CLK12_HIFI_SRC (1 << 0) +#define PERI_CLK12_MMC0_SRC (1 << 1) +#define PERI_CLK12_MMC1_SRC (1 << 2) +#define PERI_CLK12_MMC2_SRC (1 << 3) +#define PERI_CLK12_SYSPLL_DIV (1 << 4) +#define PERI_CLK12_TPIU_SRC (1 << 5) +#define PERI_CLK12_MMC0_HF (1 << 6) +#define PERI_CLK12_MMC1_HF (1 << 7) +#define PERI_CLK12_PLL_TEST_SRC (1 << 8) +#define PERI_CLK12_CODEC_SOC (1 << 9) +#define PERI_CLK12_MEDIA (1 << 10) + +/* RST0 EN/DIS/STAT bit definitions */ + +#define PERI_RST0_MMC0 (1 << 0) +#define PERI_RST0_MMC1 (1 << 1) +#define PERI_RST0_MMC2 (1 << 2) +#define PERI_RST0_NANDC (1 << 3) +#define PERI_RST0_USBOTG_BUS (1 << 4) +#define PERI_RST0_POR_PICOPHY (1 << 5) +#define PERI_RST0_USBOTG (1 << 6) +#define PERI_RST0_USBOTG_32K (1 << 7) + +/* RST1 EN/DIS/STAT bit definitions */ + +#define PERI_RST1_HIFI (1 << 0) +#define PERI_RST1_DIGACODEC (1 << 5) + +/* RST2 EN/DIS/STAT bit definitions */ + +#define PERI_RST2_IPF (1 << 0) +#define PERI_RST2_SOCP (1 << 1) +#define PERI_RST2_DMAC (1 << 2) +#define PERI_RST2_SECENG (1 << 3) +#define PERI_RST2_ABB (1 << 4) +#define PERI_RST2_HPM0 (1 << 5) +#define PERI_RST2_HPM1 (1 << 6) +#define PERI_RST2_HPM2 (1 << 7) +#define PERI_RST2_HPM3 (1 << 8) + +/* RST3 EN/DIS/STAT bit definitions */ + +#define PERI_RST3_CSSYS (1 << 0) +#define PERI_RST3_I2C0 (1 << 1) +#define PERI_RST3_I2C1 (1 << 2) +#define PERI_RST3_I2C2 (1 << 3) +#define PERI_RST3_I2C3 (1 << 4) +#define PERI_RST3_UART1 (1 << 5) +#define PERI_RST3_UART2 (1 << 6) +#define PERI_RST3_UART3 (1 << 7) +#define PERI_RST3_UART4 (1 << 8) +#define PERI_RST3_SSP (1 << 9) +#define PERI_RST3_PWM (1 << 10) +#define PERI_RST3_BLPWM (1 << 11) +#define PERI_RST3_TSENSOR (1 << 12) +#define PERI_RST3_DAPB (1 << 18) +#define PERI_RST3_HKADC (1 << 19) +#define PERI_RST3_CODEC (1 << 20) + +/* RST8 EN/DIS/STAT bit definitions */ + +#define PERI_RST8_RS0 (1 << 0) +#define PERI_RST8_RS2 (1 << 1) +#define PERI_RST8_RS3 (1 << 2) +#define PERI_RST8_MS0 (1 << 3) +#define PERI_RST8_MS2 (1 << 5) +#define PERI_RST8_XG2RAM0 (1 << 6) +#define PERI_RST8_X2SRAM_TZMA (1 << 7) +#define PERI_RST8_SRAM (1 << 8) +#define PERI_RST8_HARQ (1 << 10) +#define PERI_RST8_DDRC (1 << 12) +#define PERI_RST8_DDRC_APB (1 << 13) +#define PERI_RST8_DDRPACK_APB (1 << 14) +#define PERI_RST8_DDRT (1 << 17) + +#endif /*__HI62220_H__*/ diff --git a/roms/u-boot/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h b/roms/u-boot/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h new file mode 100644 index 000000000..4b9a0d44a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h @@ -0,0 +1,419 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Linaro + * Peter Griffin + */ + +#ifndef __HI6220_ALWAYSON_H__ +#define __HI6220_ALWAYSON_H__ + +#define ALWAYSON_CTRL_BASE 0xF7800000 + +struct alwayson_sc_regs { + u32 ctrl0; /*0x0*/ + u32 ctrl1; + u32 ctrl2; + + u32 unknown; + + u32 stat0; /*0x10*/ + u32 stat1; + u32 mcu_imctrl; + u32 mcu_imstat; + + u32 unknown_1[9]; + + u32 secondary_int_en0; /*0x44*/ + u32 secondary_int_statr0; + u32 secondary_int_statm0; + + u32 unknown_2; + + u32 mcu_wkup_int_en6; /*0x54*/ + u32 mcu_wkup_int_statr6; + u32 mcu_wkup_int_statm6; + + u32 unknown_3; + + u32 mcu_wkup_int_en5; /*0x64*/ + u32 mcu_wkup_int_statr5; + u32 mcu_wkup_int_statm5; + + u32 unknown_4[9]; + + u32 mcu_wkup_int_en4; /*0x94*/ + u32 mcu_wkup_int_statr4; + u32 mcu_wkup_int_statm4; + + u32 unknown_5[2]; + + u32 mcu_wkup_int_en0; /*0xa8*/ + u32 mcu_wkup_int_statr0; + u32 mcu_wkup_int_statm0; + + u32 mcu_wkup_int_en1; /*0xb4*/ + u32 mcu_wkup_int_statr1; + u32 mcu_wkup_int_statm1; + + u32 unknown_6; + + u32 int_statr; /*0xc4*/ + u32 int_statm; + u32 int_clear; + + u32 int_en_set; /*0xd0*/ + u32 int_en_dis; + u32 int_en_stat; + + u32 unknown_7[2]; + + u32 int_statr1; /*0xc4*/ + u32 int_statm1; + u32 int_clear1; + + u32 int_en_set1; /*0xf0*/ + u32 int_en_dis1; + u32 int_en_stat1; + + u32 unknown_8[53]; + + u32 timer_en0; /*0x1d0*/ + u32 timer_en1; + + u32 unknown_9[6]; + + u32 timer_en4; /*0x1f0*/ + u32 timer_en5; + + u32 unknown_10[130]; + + u32 mcu_subsys_ctrl0; /*0x400*/ + u32 mcu_subsys_ctrl1; + u32 mcu_subsys_ctrl2; + u32 mcu_subsys_ctrl3; + u32 mcu_subsys_ctrl4; + u32 mcu_subsys_ctrl5; + u32 mcu_subsys_ctrl6; + u32 mcu_subsys_ctrl7; + + u32 unknown_10_1[8]; + + u32 mcu_subsys_stat0; /*0x440*/ + u32 mcu_subsys_stat1; + u32 mcu_subsys_stat2; + u32 mcu_subsys_stat3; + u32 mcu_subsys_stat4; + u32 mcu_subsys_stat5; + u32 mcu_subsys_stat6; + u32 mcu_subsys_stat7; + + u32 unknown_11[116]; + + u32 clk4_en; /*0x630*/ + u32 clk4_dis; + u32 clk4_stat; + + u32 clk5_en; /*0x63c*/ + u32 clk5_dis; + u32 clk5_stat; + + u32 unknown_12[42]; + + u32 rst4_en; /*0x6f0*/ + u32 rst4_dis; + u32 rst4_stat; + + u32 rst5_en; /*0x6fc*/ + u32 rst5_dis; + u32 rst5_stat; + + u32 unknown_13[62]; + + u32 pw_clk0_en; /*0x800*/ + u32 pw_clk0_dis; + u32 pw_clk0_stat; + + u32 unknown_13_1; + + u32 pw_rst0_en; /*0x810*/ + u32 pw_rst0_dis; + u32 pw_rst0_stat; + + u32 unknown_14; + + u32 pw_isoen0; /*0x820*/ + u32 pw_isodis0; + u32 pw_iso_stat0; + + u32 unknown_14_1; + + u32 pw_mtcmos_en0; /*0x830*/ + u32 pw_mtcmos_dis0; + u32 pw_mtcmos_stat0; + u32 pw_mtcmos_ack_stat0; + u32 pw_mtcmos_timeout_stat0; + + u32 unknown_14_2[3]; + + u32 pw_stat0; /*0x850*/ + u32 pw_stat1; + + u32 unknown_15[10]; + + u32 systest_stat; /*0x880*/ + + u32 unknown_16[3]; + + u32 systest_slicer_cnt0;/*0x890*/ + u32 systest_slicer_cnt1; + + u32 unknown_17[12]; + + u32 pw_ctrl1; /*0x8C8*/ + u32 pw_ctrl; + + u32 mcpu_voteen; + u32 mcpu_votedis; + u32 mcpu_votestat; + + u32 unknown_17_1; + + u32 mcpu_vote_msk0; /*0x8E0*/ + u32 mcpu_vote_msk1; + u32 mcpu_votestat0_msk; + u32 mcpu_votestat1_msk; + + u32 peri_voteen; /*0x8F0*/ + u32 peri_votedis; + u32 peri_votestat; + + u32 unknown_17_2; + + u32 peri_vote_msk0; /*0x900*/ + u32 peri_vote_msk1; + u32 peri_votestat0_msk; + u32 erpi_votestat1_msk; + u32 acpu_voteen; + u32 acpu_votedis; + u32 acpu_votestat; + + u32 unknown_18; + + u32 acpu_vote_msk0; /*0x920*/ + u32 acpu_vote_msk1; + u32 acpu_votestat0_msk; + u32 acpu_votestat1_msk; + u32 mcu_voteen; + u32 mcu_votedis; + u32 mcu_votestat; + + u32 unknown_18_1; + + u32 mcu_vote_msk0; /*0x940*/ + u32 mcu_vote_msk1; + u32 mcu_vote_votestat0_msk; + u32 mcu_vote_votestat1_msk; + + u32 unknown_18_1_2[4]; + + u32 mcu_vote_vote1en; /*0x960*/ + u32 mcu_vote_vote1dis; + u32 mcu_vote_vote1stat; + + u32 unknown_18_2; + + u32 mcu_vote_vote1_msk0;/*0x970*/ + u32 mcu_vote_vote1_msk1; + u32 mcu_vote_vote1stat0_msk; + u32 mcu_vote_vote1stat1_msk; + u32 mcu_vote_vote2en; + u32 mcu_vote_vote2dis; + u32 mcu_vote_vote2stat; + + u32 unknown_18_3; + + u32 mcu_vote2_msk0; /*0x990*/ + u32 mcu_vote2_msk1; + u32 mcu_vote2stat0_msk; + u32 mcu_vote2stat1_msk; + u32 vote_ctrl; + u32 vote_stat; /*0x9a4*/ + + u32 unknown_19[342]; + + u32 econum; /*0xf00*/ + + u32 unknown_20_1[3]; + + u32 scchipid; /*0xf10*/ + + u32 unknown_20_2[2]; + + u32 scsocid; /*0xf1c*/ + + u32 unknown_20[48]; + + u32 soc_fpga_rtl_def; /*0xfe0*/ + u32 soc_fpga_pr_def; + u32 soc_fpga_res_def0; + u32 soc_fpga_res_def1; /*0xfec*/ +}; + +/* ctrl0 bit definitions */ + +#define ALWAYSON_SC_SYS_CTRL0_MODE_NORMAL 0x004 +#define ALWAYSON_SC_SYS_CTRL0_MODE_MASK 0x007 + +/* ctrl1 bit definitions */ + +#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG (1 << 0) +#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM (1 << 1) +#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP (1 << 2) +#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL (1 << 3) +#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG (1 << 4) +#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG (1 << 6) +#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG (1 << 7) +#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG (1 << 8) +#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG (1 << 9) +#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG (1 << 10) +#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1 (1 << 11) +#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT (1 << 12) +#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT (1 << 13) +#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG (1 << 15) +#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG_MSK (1 << 16) +#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK (1 << 17) +#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP_MSK (1 << 18) +#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL_MSK (1 << 19) +#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG_MSK (1 << 20) +#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG_MSK (1 << 22) +#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG_MSK (1 << 23) +#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG_MSK (1 << 24) +#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG_MSK (1 << 25) +#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG_MSK (1 << 26) +#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK (1 << 27) +#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK (1 << 28) +#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK (1 << 29) +#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK (1 << 31) + +/* ctrl2 bit definitions */ + +#define ALWAYSON_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR (1 << 26) +#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR (1 << 27) +#define ALWAYSON_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR (1 << 28) +#define ALWAYSON_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR (1 << 29) +#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR (1 << 30) +#define ALWAYSON_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR (1 << 31) + +/* stat0 bit definitions */ + +#define ALWAYSON_SC_SYS_STAT0_MCU_RST_STAT (1 << 25) +#define ALWAYSON_SC_SYS_STAT0_MCU_SOFTRST_STAT (1 << 26) +#define ALWAYSON_SC_SYS_STAT0_MCU_WDGRST_STAT (1 << 27) +#define ALWAYSON_SC_SYS_STAT0_TSENSOR_HARDRST_STAT (1 << 28) +#define ALWAYSON_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT (1 << 29) +#define ALWAYSON_SC_SYS_STAT0_CM3_WDG1_RST_STAT (1 << 30) +#define ALWAYSON_SC_SYS_STAT0_GLB_SRST_STAT (1 << 31) + +/* stat1 bit definitions */ + +#define ALWAYSON_SC_SYS_STAT1_MODE_STATUS (1 << 0) +#define ALWAYSON_SC_SYS_STAT1_BOOT_SEL_LOCK (1 << 16) +#define ALWAYSON_SC_SYS_STAT1_FUNC_MODE_LOCK (1 << 17) +#define ALWAYSON_SC_SYS_STAT1_BOOT_MODE_LOCK (1 << 19) +#define ALWAYSON_SC_SYS_STAT1_FUN_JTAG_MODE_OUT (1 << 20) +#define ALWAYSON_SC_SYS_STAT1_SECURITY_BOOT_FLG (1 << 27) +#define ALWAYSON_SC_SYS_STAT1_EFUSE_NANDBOOT_MSK (1 << 28) +#define ALWAYSON_SC_SYS_STAT1_EFUSE_NAND_BITWIDE (1 << 29) + +/* ctrl3 bit definitions */ + +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3 0x003 +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK 0x007 +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_CSSYS_CTRL_PROT (1 << 3) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_TCXO_AFC_OEN_CRG (1 << 4) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM1 (1 << 8) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM0 (1 << 9) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_SD (1 << 10) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_MCU_SUBSYS_CTRL3_RESERVED (1 << 11) + +/* clk4_en bit definitions */ + +#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_MCU (1 << 0) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_MCU_DAP (1 << 3) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER0 (1 << 4) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER1 (1 << 5) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT0 (1 << 6) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT1 (1 << 7) +#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_S (1 << 8) +#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_NS (1 << 9) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_EFUSEC (1 << 10) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TZPC (1 << 11) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT0 (1 << 12) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT1 (1 << 13) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT2 (1 << 14) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER0 (1 << 15) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER1 (1 << 16) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER2 (1 << 17) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER3 (1 << 18) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER4 (1 << 19) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER5 (1 << 20) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER6 (1 << 21) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER7 (1 << 22) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER8 (1 << 23) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_UART0 (1 << 24) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC0 (1 << 25) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC1 (1 << 26) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_PMUSSI (1 << 27) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_JTAG_AUTH (1 << 28) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_CS_DAPB_ON (1 << 29) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_PDM (1 << 30) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_SSI_PAD (1 << 31) + +/* clk5_en bit definitions */ + +#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU (1 << 0) +#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_CCPU (1 << 1) +#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_CCPU (1 << 2) +#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_CCPU (1 << 3) +#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU (1 << 16) +#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_MCU (1 << 17) +#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_MCU (1 << 18) +#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_MCU (1 << 19) + +/* rst4_dis bit definitions */ + +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_ECTR_N (1 << 0) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_SYS_N (1 << 1) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_POR_N (1 << 2) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_DAP_N (1 << 3) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER0_N (1 << 4) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER1_N (1 << 5) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT0_N (1 << 6) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT1_N (1 << 7) +#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_S_N (1 << 8) +#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_NS_N (1 << 9) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_EFUSEC_N (1 << 10) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT0_N (1 << 12) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT1_N (1 << 13) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT2_N (1 << 14) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER0_N (1 << 15) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER1_N (1 << 16) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER2_N (1 << 17) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER3_N (1 << 18) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER4_N (1 << 19) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER5_N (1 << 20) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER6_N (1 << 21) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER7_N (1 << 22) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER8_N (1 << 23) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_UART0_N (1 << 24) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC0_N (1 << 25) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC1_N (1 << 26) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N (1 << 27) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_JTAG_AUTH_N (1 << 28) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_CS_DAPB_ON_N (1 << 29) +#define ALWAYSON_SC_PERIPH_RST4_DIS_MDM_SUBSYS_GLB (1 << 30) + +#define PCLK_TIMER1 (1 << 16) +#define PCLK_TIMER0 (1 << 15) + +#endif /* __HI6220_ALWAYSON_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-hi6220/periph.h b/roms/u-boot/arch/arm/include/asm/arch-hi6220/periph.h new file mode 100644 index 000000000..edec21388 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-hi6220/periph.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Linaro + * Peter Griffin + */ + +#ifndef __ASM_ARM_ARCH_PERIPH_H +#define __ASM_ARM_ARCH_PERIPH_H + +/* + * Peripherals required for pinmux configuration. List will + * grow with support for more devices getting added. + * Numbering based on interrupt table. + * + */ +enum periph_id { + PERIPH_ID_UART0 = 36, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + PERIPH_ID_UART3, + PERIPH_ID_UART4, + PERIPH_ID_UART5, + PERIPH_ID_SDMMC0 = 72, + PERIPH_ID_SDMMC1, + + PERIPH_ID_NONE = -1, +}; + +#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-hi6220/pinmux.h b/roms/u-boot/arch/arm/include/asm/arch-hi6220/pinmux.h new file mode 100644 index 000000000..b4a9957e8 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-hi6220/pinmux.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Linaro + * Peter Griffin + */ + +#ifndef __ASM_ARM_ARCH_PINMUX_H +#define __ASM_ARM_ARCH_PINMUX_H + +#include "periph.h" + + +/* iomg bit definition */ +#define MUX_M0 0 +#define MUX_M1 1 +#define MUX_M2 2 +#define MUX_M3 3 +#define MUX_M4 4 +#define MUX_M5 5 +#define MUX_M6 6 +#define MUX_M7 7 + +/* iocg bit definition */ +#define PULL_MASK (3) +#define PULL_DIS (0) +#define PULL_UP (1 << 0) +#define PULL_DOWN (1 << 1) + +/* drive strength definition */ +#define DRIVE_MASK (7 << 4) +#define DRIVE1_02MA (0 << 4) +#define DRIVE1_04MA (1 << 4) +#define DRIVE1_08MA (2 << 4) +#define DRIVE1_10MA (3 << 4) +#define DRIVE2_02MA (0 << 4) +#define DRIVE2_04MA (1 << 4) +#define DRIVE2_08MA (2 << 4) +#define DRIVE2_10MA (3 << 4) +#define DRIVE3_04MA (0 << 4) +#define DRIVE3_08MA (1 << 4) +#define DRIVE3_12MA (2 << 4) +#define DRIVE3_16MA (3 << 4) +#define DRIVE3_20MA (4 << 4) +#define DRIVE3_24MA (5 << 4) +#define DRIVE3_32MA (6 << 4) +#define DRIVE3_40MA (7 << 4) +#define DRIVE4_02MA (0 << 4) +#define DRIVE4_04MA (2 << 4) +#define DRIVE4_08MA (4 << 4) +#define DRIVE4_10MA (6 << 4) + +#define HI6220_PINMUX0_BASE 0xf7010000 +#define HI6220_PINMUX1_BASE 0xf7010800 + +#ifndef __ASSEMBLY__ + +/* maybe more registers, but highest used is 123 */ +#define REG_NUM 123 + +struct hi6220_pinmux0_regs { + uint32_t iomg[REG_NUM]; +}; + +struct hi6220_pinmux1_regs { + uint32_t iocfg[REG_NUM]; +}; + +#endif + +/** + * Configures the pinmux for a particular peripheral. + * + * This function will configure the peripheral pinmux along with + * pull-up/down and drive strength. + * + * @param peripheral peripheral to be configured + * @return 0 if ok, -1 on error (e.g. unsupported peripheral) + */ +int hi6220_pinmux_config(int peripheral); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx/cpu.h b/roms/u-boot/arch/arm/include/asm/arch-imx/cpu.h new file mode 100644 index 000000000..267a094e5 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx/cpu.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2014 Freescale Semiconductor, Inc. + */ + +#define MXC_CPU_MX23 0x23 +#define MXC_CPU_MX25 0x25 +#define MXC_CPU_MX27 0x27 +#define MXC_CPU_MX28 0x28 +#define MXC_CPU_MX31 0x31 +#define MXC_CPU_MX35 0x35 +#define MXC_CPU_MX51 0x51 +#define MXC_CPU_MX53 0x53 +#define MXC_CPU_MX6SL 0x60 +#define MXC_CPU_MX6DL 0x61 +#define MXC_CPU_MX6SX 0x62 +#define MXC_CPU_MX6Q 0x63 +#define MXC_CPU_MX6UL 0x64 +#define MXC_CPU_MX6ULL 0x65 +#define MXC_CPU_MX6ULZ 0x6B +#define MXC_CPU_MX6SOLO 0x66 /* dummy */ +#define MXC_CPU_MX6SLL 0x67 +#define MXC_CPU_MX6D 0x6A +#define MXC_CPU_MX6DP 0x68 +#define MXC_CPU_MX6QP 0x69 +#define MXC_CPU_MX7S 0x71 /* dummy ID */ +#define MXC_CPU_MX7D 0x72 +#define MXC_CPU_IMX8MQ 0x82 +#define MXC_CPU_IMX8MD 0x83 /* dummy ID */ +#define MXC_CPU_IMX8MQL 0x84 /* dummy ID */ +#define MXC_CPU_IMX8MM 0x85 /* dummy ID */ +#define MXC_CPU_IMX8MML 0x86 /* dummy ID */ +#define MXC_CPU_IMX8MMD 0x87 /* dummy ID */ +#define MXC_CPU_IMX8MMDL 0x88 /* dummy ID */ +#define MXC_CPU_IMX8MMS 0x89 /* dummy ID */ +#define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */ +#define MXC_CPU_IMX8MN 0x8b /* dummy ID */ +#define MXC_CPU_IMX8MND 0x8c /* dummy ID */ +#define MXC_CPU_IMX8MNS 0x8d /* dummy ID */ +#define MXC_CPU_IMX8MNL 0x8e /* dummy ID */ +#define MXC_CPU_IMX8MNDL 0x8f /* dummy ID */ +#define MXC_CPU_IMX8MNSL 0x181 /* dummy ID */ +#define MXC_CPU_IMX8MNUQ 0x182 /* dummy ID */ +#define MXC_CPU_IMX8MNUD 0x183 /* dummy ID */ +#define MXC_CPU_IMX8MNUS 0x184 /* dummy ID */ +#define MXC_CPU_IMX8MP 0x185/* dummy ID */ +#define MXC_CPU_IMX8MP6 0x186 /* dummy ID */ +#define MXC_CPU_IMX8MPL 0x187 /* dummy ID */ +#define MXC_CPU_IMX8MPD 0x188 /* dummy ID */ +#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ +#define MXC_CPU_IMX8QM 0x91 /* dummy ID */ +#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ +#define MXC_CPU_IMXRT1020 0xB4 /* dummy ID */ +#define MXC_CPU_IMXRT1050 0xB6 /* dummy ID */ +#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ +#define MXC_CPU_VF610 0xF6 /* dummy ID */ + +#define MXC_SOC_MX6 0x60 +#define MXC_SOC_MX7 0x70 +#define MXC_SOC_IMX8M 0x80 +#define MXC_SOC_IMX8 0x90 /* dummy */ +#define MXC_SOC_IMXRT 0xB0 /* dummy */ +#define MXC_SOC_MX7ULP 0xE0 /* dummy */ + +#define CHIP_REV_1_0 0x10 +#define CHIP_REV_1_1 0x11 +#define CHIP_REV_1_2 0x12 +#define CHIP_REV_1_3 0x13 +#define CHIP_REV_1_5 0x15 +#define CHIP_REV_2_0 0x20 +#define CHIP_REV_2_1 0x21 +#define CHIP_REV_2_2 0x22 +#define CHIP_REV_2_5 0x25 +#define CHIP_REV_3_0 0x30 + +#define CHIP_REV_A 0x0 +#define CHIP_REV_B 0x1 +#define CHIP_REV_C 0x2 + +#define BOARD_REV_1_0 0x0 +#define BOARD_REV_2_0 0x1 +#define BOARD_VER_OFFSET 0x8 + +#define CS0_128 0 +#define CS0_64M_CS1_64M 1 +#define CS0_64M_CS1_32M_CS2_32M 2 +#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 + +u32 get_imx_reset_cause(void); +ulong get_systemPLLCLK(void); +ulong get_FCLK(void); +ulong get_HCLK(void); +ulong get_BCLK(void); +ulong get_PERCLK1(void); +ulong get_PERCLK2(void); +ulong get_PERCLK3(void); diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8/boot0.h b/roms/u-boot/arch/arm/include/asm/arch-imx8/boot0.h new file mode 100644 index 000000000..5ce781adb --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8/boot0.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#if defined(CONFIG_SPL_BUILD) + /* + * We use absolute address not PC relative address to jump. + * When running SPL on iMX8, the A core starts at address 0, a alias to OCRAM 0x100000, + * our linker address for SPL is from 0x100000. So using absolute address can jump to + * the OCRAM address from the alias. + * The alias only map first 96KB of OCRAM, so this require the SPL size can't beyond 96KB. + * But when using SPL DM, the size increase significantly and may exceed 96KB. + * That's why we have to jump to OCRAM. + */ + + ldr x0, =reset + br x0 +#else + b reset +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8/clock.h b/roms/u-boot/arch/arm/include/asm/arch-imx8/clock.h new file mode 100644 index 000000000..bea157171 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8/clock.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __ASM_ARCH_IMX8_CLOCK_H__ +#define __ASM_ARCH_IMX8_CLOCK_H__ + +/* Mainly for compatible to imx common code. */ +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_UART_CLK, + MXC_CSPI_CLK, + MXC_AXI_CLK, + MXC_DDR_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, + MXC_I2C_CLK, + MXC_FEC_CLK, +}; + +u32 mxc_get_clock(enum mxc_clock clk); + +#endif /* __ASM_ARCH_IMX8_CLOCK_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-imx8/gpio.h new file mode 100644 index 000000000..24cfde3c2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8/gpio.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __ASM_ARCH_IMX8_GPIO_H +#define __ASM_ARCH_IMX8_GPIO_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +/* GPIO registers */ +struct gpio_regs { + u32 gpio_dr; /* data */ + u32 gpio_dir; /* direction */ + u32 gpio_psr; /* pad satus */ +}; +#endif + +/* IMX8 the GPIO index is from 0 not 1 */ +#define IMX_GPIO_NR(port, index) (((port) * 32) + ((index) & 31)) + +#endif /* __ASM_ARCH_IMX8_GPIO_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8/image.h b/roms/u-boot/arch/arm/include/asm/arch-imx8/image.h new file mode 100644 index 000000000..547beeb98 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8/image.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018-2019 NXP + */ + +#ifndef __CONTAINER_HEADER_H_ +#define __CONTAINER_HEADER_H_ + +#include +#include + +#define IV_MAX_LEN 32 +#define HASH_MAX_LEN 64 + +#define CONTAINER_HDR_ALIGNMENT 0x400 +#define CONTAINER_HDR_EMMC_OFFSET 0 +#define CONTAINER_HDR_MMCSD_OFFSET SZ_32K +#define CONTAINER_HDR_QSPI_OFFSET SZ_4K +#define CONTAINER_HDR_NAND_OFFSET SZ_128M + +struct container_hdr { + u8 version; + u8 length_lsb; + u8 length_msb; + u8 tag; + u32 flags; + u16 sw_version; + u8 fuse_version; + u8 num_images; + u16 sig_blk_offset; + u16 reserved; +} __packed; + +struct boot_img_t { + u32 offset; + u32 size; + u64 dst; + u64 entry; + u32 hab_flags; + u32 meta; + u8 hash[HASH_MAX_LEN]; + u8 iv[IV_MAX_LEN]; +} __packed; + +struct signature_block_hdr { + u8 version; + u8 length_lsb; + u8 length_msb; + u8 tag; + u16 srk_table_offset; + u16 cert_offset; + u16 blob_offset; + u16 signature_offset; + u32 reserved; +} __packed; + +struct generate_key_blob_hdr { + u8 version; + u8 length_lsb; + u8 length_msb; + u8 tag; + u8 flags; + u8 size; + u8 algorithm; + u8 mode; +} __packed; +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8/imx-regs.h b/roms/u-boot/arch/arm/include/asm/arch-imx8/imx-regs.h new file mode 100644 index 000000000..ed6e05e55 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8/imx-regs.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __ASM_ARCH_IMX8_REGS_H__ +#define __ASM_ARCH_IMX8_REGS_H__ + +#define ARCH_MXC + +#define LPUART_BASE 0x5A060000 + +#define GPT1_BASE_ADDR 0x5D140000 +#define SCU_LPUART_BASE 0x33220000 +#define GPIO1_BASE_ADDR 0x5D080000 +#define GPIO2_BASE_ADDR 0x5D090000 +#define GPIO3_BASE_ADDR 0x5D0A0000 +#define GPIO4_BASE_ADDR 0x5D0B0000 +#define GPIO5_BASE_ADDR 0x5D0C0000 +#define GPIO6_BASE_ADDR 0x5D0D0000 +#define GPIO7_BASE_ADDR 0x5D0E0000 +#define GPIO8_BASE_ADDR 0x5D0F0000 +#define LPI2C1_BASE_ADDR 0x5A800000 +#define LPI2C2_BASE_ADDR 0x5A810000 +#define LPI2C3_BASE_ADDR 0x5A820000 +#define LPI2C4_BASE_ADDR 0x5A830000 +#define LPI2C5_BASE_ADDR 0x5A840000 + +#define FEC_QUIRK_ENET_MAC + +#ifdef CONFIG_IMX8QXP +#define LVDS0_PHYCTRL_BASE 0x56221000 +#define LVDS1_PHYCTRL_BASE 0x56241000 +#define MIPI0_SS_BASE 0x56220000 +#define MIPI1_SS_BASE 0x56240000 +#endif + +#define APBH_DMA_ARB_BASE_ADDR 0x5B810000 +#define APBH_DMA_ARB_END_ADDR 0x5B81FFFF +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR + +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) + +#define PASS_OVER_INFO_ADDR 0x0010fe00 + +#define USB_BASE_ADDR 0x5b0d0000 +#define USB_PHY0_BASE_ADDR 0x5b100000 + +#endif /* __ASM_ARCH_IMX8_REGS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8/imx8-pins.h b/roms/u-boot/arch/arm/include/asm/arch-imx8/imx8-pins.h new file mode 100644 index 000000000..213029816 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8/imx8-pins.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __ASM_ARCH_IMX8_PINS_H__ +#define __ASM_ARCH_IMX8_PINS_H__ + +#if defined(CONFIG_IMX8QXP) +#include +#elif defined(CONFIG_IMX8QM) +#include +#else +#error "No pin header" +#endif + +#endif /* __ASM_ARCH_IMX8_PINS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8/iomux.h b/roms/u-boot/arch/arm/include/asm/arch-imx8/iomux.h new file mode 100644 index 000000000..3acef1ea6 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8/iomux.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __ASM_ARCH_IMX8_IOMUX_H__ +#define __ASM_ARCH_IMX8_IOMUX_H__ + +#ifndef __ASSEMBLY__ +#include +#endif + +/* + * We use 64bits value for iomux settings. + * High 32bits are used for padring register value, + * low 16bits are used for pin index. + */ +typedef u64 iomux_cfg_t; + +#define PADRING_IFMUX_EN_SHIFT 31 +#define PADRING_IFMUX_EN_MASK BIT(31) +#define PADRING_GP_EN_SHIFT 30 +#define PADRING_GP_EN_MASK BIT(30) +#define PADRING_IFMUX_SHIFT 27 +#define PADRING_IFMUX_MASK GENMASK(29, 27) +#define PADRING_CONFIG_SHIFT 25 +#define PADRING_LPCONFIG_SHIFT 23 +#define PADRING_PULL_SHIFT 5 +#define PADRING_DSE_SHIFT 0 + +#define MUX_PAD_CTRL_SHIFT 32 +#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0xFFFFFFFF << MUX_PAD_CTRL_SHIFT) +#define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) +#define MUX_MODE_SHIFT (PADRING_IFMUX_SHIFT + MUX_PAD_CTRL_SHIFT) +#define MUX_MODE_MASK ((iomux_cfg_t)0x7 << MUX_MODE_SHIFT) +#define PIN_ID_MASK ((iomux_cfg_t)0xFFFF) + +/* Valid mux alt0 to alt7 */ +#define MUX_MODE_ALT(x) (((iomux_cfg_t)(x) << MUX_MODE_SHIFT) & \ + MUX_MODE_MASK) + +void imx8_iomux_setup_pad(iomux_cfg_t pad); +void imx8_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, u32 count); +#endif /* __ASM_ARCH_IMX8_IOMUX_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8/power-domain.h b/roms/u-boot/arch/arm/include/asm/arch-imx8/power-domain.h new file mode 100644 index 000000000..1db86a120 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8/power-domain.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 NXP + */ + +#ifndef _ASM_ARCH_IMX8_POWER_DOMAIN_H +#define _ASM_ARCH_IMX8_POWER_DOMAIN_H + +#include + +struct imx8_power_domain_plat { + sc_rsrc_t resource_id; +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/rpc.h b/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/rpc.h new file mode 100644 index 000000000..9f55904f4 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/rpc.h @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017-2018 NXP + * + */ + +#ifndef SC_RPC_H +#define SC_RPC_H + +/* Note: Check SCFW API Released DOC before you want to modify something */ +/* Defines */ + +#define SCFW_API_VERSION_MAJOR 1U +#define SCFW_API_VERSION_MINOR 15U + +#define SC_RPC_VERSION 1U + +#define SC_RPC_MAX_MSG 8U + +#define RPC_VER(MSG) ((MSG)->version) +#define RPC_SIZE(MSG) ((MSG)->size) +#define RPC_SVC(MSG) ((MSG)->svc) +#define RPC_FUNC(MSG) ((MSG)->func) +#define RPC_R8(MSG) ((MSG)->func) +#define RPC_I64(MSG, IDX) ((s64)(RPC_U32((MSG), (IDX))) << 32ULL) | \ + (s64)(RPC_U32((MSG), (IDX) + 4U)) +#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U]) +#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U]) +#define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)]) +#define RPC_U64(MSG, IDX) ((u64)(RPC_U32((MSG), (IDX))) << 32ULL) | \ + (u64)(RPC_U32((MSG), (IDX) + 4U)) +#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U]) +#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U]) +#define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)]) + +#define SC_RPC_SVC_UNKNOWN 0U +#define SC_RPC_SVC_RETURN 1U +#define SC_RPC_SVC_PM 2U +#define SC_RPC_SVC_RM 3U +#define SC_RPC_SVC_TIMER 5U +#define SC_RPC_SVC_PAD 6U +#define SC_RPC_SVC_MISC 7U +#define SC_RPC_SVC_IRQ 8U +#define SC_RPC_SVC_SECO 9U +#define SC_RPC_SVC_ABORT 10U + + +/* Types */ + +struct sc_rpc_msg_s { + u8 version; + u8 size; + u8 svc; + u8 func; + union { + s32 i32[(SC_RPC_MAX_MSG - 1U)]; + s16 i16[(SC_RPC_MAX_MSG - 1U) * 2U]; + s8 i8[(SC_RPC_MAX_MSG - 1U) * 4U]; + u32 u32[(SC_RPC_MAX_MSG - 1U)]; + u16 u16[(SC_RPC_MAX_MSG - 1U) * 2U]; + u8 u8[(SC_RPC_MAX_MSG - 1U) * 4U]; + } DATA; +}; + +/* PM RPC */ +#define PM_FUNC_UNKNOWN 0 +#define PM_FUNC_SET_SYS_POWER_MODE 19U +#define PM_FUNC_SET_PARTITION_POWER_MODE 1U +#define PM_FUNC_GET_SYS_POWER_MODE 2U +#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U +#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U +#define PM_FUNC_REQ_LOW_POWER_MODE 16U +#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U +#define PM_FUNC_SET_CPU_RESUME_ADDR 17U +#define PM_FUNC_SET_CPU_RESUME 21U +#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U +#define PM_FUNC_SET_CLOCK_RATE 5U +#define PM_FUNC_GET_CLOCK_RATE 6U +#define PM_FUNC_CLOCK_ENABLE 7U +#define PM_FUNC_SET_CLOCK_PARENT 14U +#define PM_FUNC_GET_CLOCK_PARENT 15U +#define PM_FUNC_RESET 13U +#define PM_FUNC_RESET_REASON 10U +#define PM_FUNC_BOOT 8U +#define PM_FUNC_REBOOT 9U +#define PM_FUNC_REBOOT_PARTITION 12U +#define PM_FUNC_CPU_START 11U +#define PM_FUNC_CPU_RESET 23U +#define PM_FUNC_RESOURCE_RESET 29U +#define PM_FUNC_IS_PARTITION_STARTED 24U + +/* MISC RPC */ +#define MISC_FUNC_UNKNOWN 0 +#define MISC_FUNC_SET_CONTROL 1U +#define MISC_FUNC_GET_CONTROL 2U +#define MISC_FUNC_SET_MAX_DMA_GROUP 4U +#define MISC_FUNC_SET_DMA_GROUP 5U +#define MISC_FUNC_SECO_IMAGE_LOAD 8U +#define MISC_FUNC_SECO_AUTHENTICATE 9U +#define MISC_FUNC_SECO_FUSE_WRITE 20U +#define MISC_FUNC_SECO_ENABLE_DEBUG 21U +#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U +#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U +#define MISC_FUNC_SECO_BUILD_INFO 24U +#define MISC_FUNC_DEBUG_OUT 10U +#define MISC_FUNC_WAVEFORM_CAPTURE 6U +#define MISC_FUNC_BUILD_INFO 15U +#define MISC_FUNC_UNIQUE_ID 19U +#define MISC_FUNC_SET_ARI 3U +#define MISC_FUNC_BOOT_STATUS 7U +#define MISC_FUNC_BOOT_DONE 14U +#define MISC_FUNC_OTP_FUSE_READ 11U +#define MISC_FUNC_OTP_FUSE_WRITE 17U +#define MISC_FUNC_SET_TEMP 12U +#define MISC_FUNC_GET_TEMP 13U +#define MISC_FUNC_GET_BOOT_DEV 16U +#define MISC_FUNC_GET_BUTTON_STATUS 18U +#define MISC_FUNC_GET_BOOT_CONTAINER 36U + +/* PAD RPC */ +#define PAD_FUNC_UNKNOWN 0 +#define PAD_FUNC_SET_MUX 1U +#define PAD_FUNC_GET_MUX 6U +#define PAD_FUNC_SET_GP 2U +#define PAD_FUNC_GET_GP 7U +#define PAD_FUNC_SET_WAKEUP 4U +#define PAD_FUNC_GET_WAKEUP 9U +#define PAD_FUNC_SET_ALL 5U +#define PAD_FUNC_GET_ALL 10U +#define PAD_FUNC_SET 15U +#define PAD_FUNC_GET 16U +#define PAD_FUNC_SET_GP_28FDSOI 11U +#define PAD_FUNC_GET_GP_28FDSOI 12U +#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U +#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U +#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U +#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U + +/* RM RPC */ +#define RM_FUNC_UNKNOWN 0 +#define RM_FUNC_PARTITION_ALLOC 1U +#define RM_FUNC_SET_CONFIDENTIAL 31U +#define RM_FUNC_PARTITION_FREE 2U +#define RM_FUNC_GET_DID 26U +#define RM_FUNC_PARTITION_STATIC 3U +#define RM_FUNC_PARTITION_LOCK 4U +#define RM_FUNC_GET_PARTITION 5U +#define RM_FUNC_SET_PARENT 6U +#define RM_FUNC_MOVE_ALL 7U +#define RM_FUNC_ASSIGN_RESOURCE 8U +#define RM_FUNC_SET_RESOURCE_MOVABLE 9U +#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U +#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U +#define RM_FUNC_SET_MASTER_SID 11U +#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U +#define RM_FUNC_IS_RESOURCE_OWNED 13U +#define RM_FUNC_GET_RESOURCE_OWNER 33U +#define RM_FUNC_IS_RESOURCE_MASTER 14U +#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U +#define RM_FUNC_GET_RESOURCE_INFO 16U +#define RM_FUNC_MEMREG_ALLOC 17U +#define RM_FUNC_MEMREG_SPLIT 29U +#define RM_FUNC_MEMREG_FREE 18U +#define RM_FUNC_FIND_MEMREG 30U +#define RM_FUNC_ASSIGN_MEMREG 19U +#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U +#define RM_FUNC_IS_MEMREG_OWNED 21U +#define RM_FUNC_GET_MEMREG_INFO 22U +#define RM_FUNC_ASSIGN_PAD 23U +#define RM_FUNC_SET_PAD_MOVABLE 24U +#define RM_FUNC_IS_PAD_OWNED 25U +#define RM_FUNC_DUMP 27U + +/* SECO RPC */ +#define SECO_FUNC_UNKNOWN 0 /* Unknown function */ +#define SECO_FUNC_IMAGE_LOAD 1U /* Index for seco_image_load() RPC call */ +#define SECO_FUNC_AUTHENTICATE 2U /* Index for seco_authenticate() RPC call */ +#define SECO_FUNC_ENH_AUTHENTICATE 24U /* Index for sc_seco_enh_authenticate() RPC call */ +#define SECO_FUNC_FORWARD_LIFECYCLE 3U /* Index for seco_forward_lifecycle() RPC call */ +#define SECO_FUNC_RETURN_LIFECYCLE 4U /* Index for seco_return_lifecycle() RPC call */ +#define SECO_FUNC_COMMIT 5U /* Index for seco_commit() RPC call */ +#define SECO_FUNC_ATTEST_MODE 6U /* Index for seco_attest_mode() RPC call */ +#define SECO_FUNC_ATTEST 7U /* Index for seco_attest() RPC call */ +#define SECO_FUNC_GET_ATTEST_PKEY 8U /* Index for seco_get_attest_pkey() RPC call */ +#define SECO_FUNC_GET_ATTEST_SIGN 9U /* Index for seco_get_attest_sign() RPC call */ +#define SECO_FUNC_ATTEST_VERIFY 10U /* Index for seco_attest_verify() RPC call */ +#define SECO_FUNC_GEN_KEY_BLOB 11U /* Index for seco_gen_key_blob() RPC call */ +#define SECO_FUNC_LOAD_KEY 12U /* Index for seco_load_key() RPC call */ +#define SECO_FUNC_GET_MP_KEY 13U /* Index for seco_get_mp_key() RPC call */ +#define SECO_FUNC_UPDATE_MPMR 14U /* Index for seco_update_mpmr() RPC call */ +#define SECO_FUNC_GET_MP_SIGN 15U /* Index for seco_get_mp_sign() RPC call */ +#define SECO_FUNC_BUILD_INFO 16U /* Index for seco_build_info() RPC call */ +#define SECO_FUNC_CHIP_INFO 17U /* Index for seco_chip_info() RPC call */ +#define SECO_FUNC_ENABLE_DEBUG 18U /* Index for seco_enable_debug() RPC call */ +#define SECO_FUNC_GET_EVENT 19U /* Index for seco_get_event() RPC call */ +#define SECO_FUNC_FUSE_WRITE 20U /* Index for seco_fuse_write() RPC call */ +#define SECO_FUNC_PATCH 21U /* Index for sc_seco_patch() RPC call */ +#define SECO_FUNC_START_RNG 22U /* Index for sc_seco_start_rng() RPC call */ +#define SECO_FUNC_SAB_MSG 23U /* Index for sc_seco_sab_msg() RPC call */ +#define SECO_FUNC_SECVIO_ENABLE 25U /* Index for sc_seco_secvio_enable() RPC call */ +#define SECO_FUNC_SECVIO_CONFIG 26U /* Index for sc_seco_secvio_config() RPC call */ +#define SECO_FUNC_SECVIO_DGO_CONFIG 27U /* Index for sc_seco_secvio_dgo_config() RPC call */ + +/* IRQ RPC */ +#define IRQ_FUNC_UNKNOWN 0 /* Unknown function */ +#define IRQ_FUNC_ENABLE 1U /* Index for sc_irq_enable() RPC call */ +#define IRQ_FUNC_STATUS 2U /* Index for sc_irq_status() RPC call */ + +/* TIMER RPC */ +#define TIMER_FUNC_UNKNOWN 0 /* Unknown function */ +#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for sc_timer_set_wdog_timeout() RPC call */ +#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for sc_timer_set_wdog_pre_timeout() RPC call */ +#define TIMER_FUNC_START_WDOG 2U /* Index for sc_timer_start_wdog() RPC call */ +#define TIMER_FUNC_STOP_WDOG 3U /* Index for sc_timer_stop_wdog() RPC call */ +#define TIMER_FUNC_PING_WDOG 4U /* Index for sc_timer_ping_wdog() RPC call */ +#define TIMER_FUNC_GET_WDOG_STATUS 5U /* Index for sc_timer_get_wdog_status() RPC call */ +#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U /* Index for sc_timer_pt_get_wdog_status() RPC call */ +#define TIMER_FUNC_SET_WDOG_ACTION 10U /* Index for sc_timer_set_wdog_action() RPC call */ +#define TIMER_FUNC_SET_RTC_TIME 6U /* Index for sc_timer_set_rtc_time() RPC call */ +#define TIMER_FUNC_GET_RTC_TIME 7U /* Index for sc_timer_get_rtc_time() RPC call */ +#define TIMER_FUNC_GET_RTC_SEC1970 9U /* Index for sc_timer_get_rtc_sec1970() RPC call */ +#define TIMER_FUNC_SET_RTC_ALARM 8U /* Index for sc_timer_set_rtc_alarm() RPC call */ +#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U /* Index for sc_timer_set_rtc_periodic_alarm() RPC call */ +#define TIMER_FUNC_CANCEL_RTC_ALARM 15U /* Index for sc_timer_cancel_rtc_alarm() RPC call */ +#define TIMER_FUNC_SET_RTC_CALB 11U /* Index for sc_timer_set_rtc_calb() RPC call */ +#define TIMER_FUNC_SET_SYSCTR_ALARM 16U /* Index for sc_timer_set_sysctr_alarm() RPC call */ +#define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for sc_timer_set_sysctr_periodic_alarm() RPC call */ +#define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for sc_timer_cancel_sysctr_alarm() RPC call */ + +#endif /* SC_RPC_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/sci.h b/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/sci.h new file mode 100644 index 000000000..1c29209b3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/sci.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef _SC_SCI_H +#define _SC_SCI_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static inline int sc_err_to_linux(sc_err_t err) +{ + int ret; + + switch (err) { + case SC_ERR_NONE: + return 0; + case SC_ERR_VERSION: + case SC_ERR_CONFIG: + case SC_ERR_PARM: + ret = -EINVAL; + break; + case SC_ERR_NOACCESS: + case SC_ERR_LOCKED: + case SC_ERR_UNAVAILABLE: + ret = -EACCES; + break; + case SC_ERR_NOTFOUND: + case SC_ERR_NOPOWER: + ret = -ENODEV; + break; + case SC_ERR_IPC: + ret = -EIO; + break; + case SC_ERR_BUSY: + ret = -EBUSY; + break; + case SC_ERR_FAIL: + ret = -EIO; + break; + default: + ret = 0; + break; + } + + debug("%s %d %d\n", __func__, err, ret); + + return ret; +} + +/* PM API*/ +int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode); +int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t *mode); +int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_pm_clock_rate_t *rate); +int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_pm_clock_rate_t *rate); +int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_bool_t enable, sc_bool_t autog); +int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_pm_clk_parent_t parent); +int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, + sc_faddr_t address); +sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt); +int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource); + +/* MISC API */ +int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, + sc_ctrl_t ctrl, u32 val); +int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, + u32 *val); +void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev); +void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status); +int sc_misc_get_boot_container(sc_ipc_t ipc, u8 *idx); +void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit); +int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val); +int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, + s16 *celsius, s8 *tenths); + +/* RM API */ +sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); +int sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start, + sc_faddr_t addr_end); +int sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_rm_pt_t pt, sc_rm_perm_t perm); +int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start, + sc_faddr_t *addr_end); +sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource); +int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, + sc_bool_t isolated, sc_bool_t restricted, + sc_bool_t grant, sc_bool_t coherent); +int sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt); +int sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt); +int sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent); +int sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource); +int sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad); +sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad); +int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_pt_t *pt); + +/* PAD API */ +int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val); +int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val); + +/* SMMU API */ +int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid); + +/* SECO API */ +int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, + sc_faddr_t addr); +int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change); +int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l, + u32 *uid_h); +void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit); +int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event); +int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr, + sc_faddr_t export_addr, u16 max_size); +int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size); +int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock); +int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr, + u16 msg_size, sc_faddr_t dst_addr, u16 dst_size); +int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data); +int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access, + u32 *data0, u32 *data1, u32 *data2, u32 *data3, + u32 *data4, u8 size); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h b/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h new file mode 100644 index 000000000..3629eb68d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_MISC_API_H +#define SC_MISC_API_H + +/* Defines for sc_misc_boot_status_t */ +#define SC_MISC_BOOT_STATUS_SUCCESS 0U /* Success */ +#define SC_MISC_BOOT_STATUS_SECURITY 1U /* Security violation */ + +/* Defines for sc_misc_seco_auth_cmd_t */ +#define SC_MISC_SECO_AUTH_SECO_FW 0U /* SECO Firmware */ +#define SC_MISC_SECO_AUTH_HDMI_TX_FW 1U /* HDMI TX Firmware */ +#define SC_MISC_SECO_AUTH_HDMI_RX_FW 2U /* HDMI RX Firmware */ + +/* Defines for sc_misc_temp_t */ +#define SC_MISC_TEMP 0U /* Temp sensor */ +#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */ +#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */ + +/* Defines for sc_misc_seco_auth_cmd_t */ +#define SC_MISC_AUTH_CONTAINER 0U /* Authenticate container */ +#define SC_MISC_VERIFY_IMAGE 1U /* Verify image */ +#define SC_MISC_REL_CONTAINER 2U /* Release container */ + +typedef u8 sc_misc_boot_status_t; +typedef u8 sc_misc_temp_t; + +#endif /* SC_MISC_API_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h b/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h new file mode 100644 index 000000000..df368e8c8 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_PAD_API_H +#define SC_PAD_API_H + +/* Defines for type widths */ +#define SC_PAD_MUX_W 3U /* Width of mux parameter */ + +/* Defines for sc_pad_config_t */ +#define SC_PAD_CONFIG_NORMAL 0U /* Normal */ +#define SC_PAD_CONFIG_OD 1U /* Open Drain */ +#define SC_PAD_CONFIG_OD_IN 2U /* Open Drain and input */ +#define SC_PAD_CONFIG_OUT_IN 3U /* Output and input */ + +/* Defines for sc_pad_iso_t */ +#define SC_PAD_ISO_OFF 0U /* ISO latch is transparent */ +#define SC_PAD_ISO_EARLY 1U /* Follow EARLY_ISO */ +#define SC_PAD_ISO_LATE 2U /* Follow LATE_ISO */ +#define SC_PAD_ISO_ON 3U /* ISO latched data is held */ + +/* Defines for sc_pad_28fdsoi_dse_t */ +#define SC_PAD_28FDSOI_DSE_18V_1MA 0U /* Drive strength of 1mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_2MA 1U /* Drive strength of 2mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_4MA 2U /* Drive strength of 4mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_6MA 3U /* Drive strength of 6mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_8MA 4U /* Drive strength of 8mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_10MA 5U /* Drive strength of 10mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_12MA 6U /* Drive strength of 12mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_HS 7U /* High-speed for 1.8v */ +#define SC_PAD_28FDSOI_DSE_33V_2MA 0U /* Drive strength of 2mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_4MA 1U /* Drive strength of 4mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_8MA 2U /* Drive strength of 8mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_12MA 3U /* Drive strength of 12mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_DV_HIGH 0U /* High drive strength dual volt */ +#define SC_PAD_28FDSOI_DSE_DV_LOW 1U /* Low drive strength dual volt */ + +/* Defines for sc_pad_28fdsoi_ps_t */ +#define SC_PAD_28FDSOI_PS_KEEPER 0U /* Bus-keeper (only valid for 1.8v) */ +#define SC_PAD_28FDSOI_PS_PU 1U /* Pull-up */ +#define SC_PAD_28FDSOI_PS_PD 2U /* Pull-down */ +#define SC_PAD_28FDSOI_PS_NONE 3U /* No pull (disabled) */ + +/* Defines for sc_pad_28fdsoi_pus_t */ +#define SC_PAD_28FDSOI_PUS_30K_PD 0U /* 30K pull-down */ +#define SC_PAD_28FDSOI_PUS_100K_PU 1U /* 100K pull-up */ +#define SC_PAD_28FDSOI_PUS_3K_PU 2U /* 3K pull-up */ +#define SC_PAD_28FDSOI_PUS_30K_PU 3U /* 30K pull-up */ + +/* Defines for sc_pad_wakeup_t */ +#define SC_PAD_WAKEUP_OFF 0U /* Off */ +#define SC_PAD_WAKEUP_CLEAR 1U /* Clears pending flag */ +#define SC_PAD_WAKEUP_LOW_LVL 4U /* Low level */ +#define SC_PAD_WAKEUP_FALL_EDGE 5U /* Falling edge */ +#define SC_PAD_WAKEUP_RISE_EDGE 6U /* Rising edge */ +#define SC_PAD_WAKEUP_HIGH_LVL 7U /* High-level */ + +#endif /* SC_PAD_API_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h b/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h new file mode 100644 index 000000000..9008b85c6 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_PM_API_H +#define SC_PM_API_H + +/* Defines for sc_pm_power_mode_t */ +#define SC_PM_PW_MODE_OFF 0U /* Power off */ +#define SC_PM_PW_MODE_STBY 1U /* Power in standby */ +#define SC_PM_PW_MODE_LP 2U /* Power in low-power */ +#define SC_PM_PW_MODE_ON 3U /* Power on */ + +/* Defines for sc_pm_clk_t */ +#define SC_PM_CLK_SLV_BUS 0U /* Slave bus clock */ +#define SC_PM_CLK_MST_BUS 1U /* Master bus clock */ +#define SC_PM_CLK_PER 2U /* Peripheral clock */ +#define SC_PM_CLK_PHY 3U /* Phy clock */ +#define SC_PM_CLK_MISC 4U /* Misc clock */ +#define SC_PM_CLK_MISC0 0U /* Misc 0 clock */ +#define SC_PM_CLK_MISC1 1U /* Misc 1 clock */ +#define SC_PM_CLK_MISC2 2U /* Misc 2 clock */ +#define SC_PM_CLK_MISC3 3U /* Misc 3 clock */ +#define SC_PM_CLK_MISC4 4U /* Misc 4 clock */ +#define SC_PM_CLK_CPU 2U /* CPU clock */ +#define SC_PM_CLK_PLL 4U /* PLL */ +#define SC_PM_CLK_BYPASS 4U /* Bypass clock */ + +/* Defines for sc_pm_clk_mode_t */ +#define SC_PM_CLK_MODE_ROM_INIT 0U /* Clock is initialized by ROM. */ +#define SC_PM_CLK_MODE_OFF 1U /* Clock is disabled */ +#define SC_PM_CLK_MODE_ON 2U /* Clock is enabled. */ +#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /* Clock is in SW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */ + +typedef u8 sc_pm_power_mode_t; +typedef u8 sc_pm_clk_t; +typedef u8 sc_pm_clk_mode_t; +typedef u8 sc_pm_clk_parent_t; +typedef u32 sc_pm_clock_rate_t; + +#endif /* SC_PM_API_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h b/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h new file mode 100644 index 000000000..ed303881e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_RM_API_H +#define SC_RM_API_H + +#include + +/* Defines for type widths */ +#define SC_RM_PARTITION_W 5U /* Width of sc_rm_pt_t */ +#define SC_RM_MEMREG_W 6U /* Width of sc_rm_mr_t */ +#define SC_RM_DID_W 4U /* Width of sc_rm_did_t */ +#define SC_RM_SID_W 6U /* Width of sc_rm_sid_t */ +#define SC_RM_SPA_W 2U /* Width of sc_rm_spa_t */ +#define SC_RM_PERM_W 3U /* Width of sc_rm_perm_t */ + +/* Defines for ALL parameters */ +#define SC_RM_PT_ALL ((sc_rm_pt_t)UINT8_MAX) /* All partitions */ +#define SC_RM_MR_ALL ((sc_rm_mr_t)UINT8_MAX) /* All memory regions */ + +/* Defines for sc_rm_spa_t */ +#define SC_RM_SPA_PASSTHRU 0U /* Pass through (attribute driven by master) */ +#define SC_RM_SPA_PASSSID 1U /* Pass through and output on SID */ +#define SC_RM_SPA_ASSERT 2U /* Assert (force to be secure/privileged) */ +#define SC_RM_SPA_NEGATE 3U /* Negate (force to be non-secure/user) */ + +/* Defines for sc_rm_perm_t */ +#define SC_RM_PERM_NONE 0U /* No access */ +#define SC_RM_PERM_SEC_R 1U /* Secure RO */ +#define SC_RM_PERM_SECPRIV_RW 2U /* Secure privilege R/W */ +#define SC_RM_PERM_SEC_RW 3U /* Secure R/W */ +#define SC_RM_PERM_NSPRIV_R 4U /* Secure R/W, non-secure privilege RO */ +#define SC_RM_PERM_NS_R 5U /* Secure R/W, non-secure RO */ +#define SC_RM_PERM_NSPRIV_RW 6U /* Secure R/W, non-secure privilege R/W */ +#define SC_RM_PERM_FULL 7U /* Full access */ + +/* Types */ + +/*! + * This type is used to declare a resource partition. + */ +typedef u8 sc_rm_pt_t; + +/*! + * This type is used to declare a memory region. + */ +typedef u8 sc_rm_mr_t; + +/*! + * This type is used to declare a resource domain ID used by the + * isolation HW. + */ +typedef u8 sc_rm_did_t; + +/*! + * This type is used to declare an SMMU StreamID. + */ +typedef u16 sc_rm_sid_t; + +/*! + * This type is a used to declare master transaction attributes. + */ +typedef u8 sc_rm_spa_t; + +typedef u8 sc_rm_perm_t; + +#endif /* SC_RM_API_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h b/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h new file mode 100644 index 000000000..3ed05842d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef SC_SECO_API_H +#define SC_SECO_API_H + +/* Includes */ + +#include + +/* Defines */ +#define SC_SECO_AUTH_CONTAINER 0U /* Authenticate container */ +#define SC_SECO_VERIFY_IMAGE 1U /* Verify image */ +#define SC_SECO_REL_CONTAINER 2U /* Release container */ +#define SC_SECO_AUTH_SECO_FW 3U /* SECO Firmware */ +#define SC_SECO_AUTH_HDMI_TX_FW 4U /* HDMI TX Firmware */ +#define SC_SECO_AUTH_HDMI_RX_FW 5U /* HDMI RX Firmware */ + +#define SC_SECO_RNG_STAT_UNAVAILABLE 0U /* Unable to initialize the RNG */ +#define SC_SECO_RNG_STAT_INPROGRESS 1U /* Initialization is on-going */ +#define SC_SECO_RNG_STAT_READY 2U /* Initialized */ + +/* Types */ + +/*! + * This type is used to issue SECO authenticate commands. + */ +typedef u8 sc_seco_auth_cmd_t; + +/*! + * This type is used to return the RNG initialization status. + */ +typedef u32 sc_seco_rng_stat_t; + +#endif /* SC_SECO_API_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/types.h b/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/types.h new file mode 100644 index 000000000..adfed13e3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8/sci/types.h @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_TYPES_H +#define SC_TYPES_H + +/* Includes */ +#include + +/* Defines */ +/* + * This type is used to declare a handle for an IPC communication + * channel. Its meaning is specific to the IPC implementation. + */ +typedef u64 sc_ipc_t; + +/* Defines for common frequencies */ +#define SC_32KHZ 32768U /* 32KHz */ +#define SC_10MHZ 10000000U /* 10MHz */ +#define SC_20MHZ 20000000U /* 20MHz */ +#define SC_25MHZ 25000000U /* 25MHz */ +#define SC_27MHZ 27000000U /* 27MHz */ +#define SC_40MHZ 40000000U /* 40MHz */ +#define SC_45MHZ 45000000U /* 45MHz */ +#define SC_50MHZ 50000000U /* 50MHz */ +#define SC_60MHZ 60000000U /* 60MHz */ +#define SC_66MHZ 66666666U /* 66MHz */ +#define SC_74MHZ 74250000U /* 74.25MHz */ +#define SC_80MHZ 80000000U /* 80MHz */ +#define SC_83MHZ 83333333U /* 83MHz */ +#define SC_84MHZ 84375000U /* 84.37MHz */ +#define SC_100MHZ 100000000U /* 100MHz */ +#define SC_114MHZ 114000000U /* 114MHz */ +#define SC_125MHZ 125000000U /* 125MHz */ +#define SC_133MHZ 133333333U /* 133MHz */ +#define SC_135MHZ 135000000U /* 135MHz */ +#define SC_150MHZ 150000000U /* 150MHz */ +#define SC_160MHZ 160000000U /* 160MHz */ +#define SC_166MHZ 166666666U /* 166MHz */ +#define SC_175MHZ 175000000U /* 175MHz */ +#define SC_180MHZ 180000000U /* 180MHz */ +#define SC_200MHZ 200000000U /* 200MHz */ +#define SC_250MHZ 250000000U /* 250MHz */ +#define SC_266MHZ 266666666U /* 266MHz */ +#define SC_300MHZ 300000000U /* 300MHz */ +#define SC_312MHZ 312500000U /* 312.5MHZ */ +#define SC_320MHZ 320000000U /* 320MHz */ +#define SC_325MHZ 325000000U /* 325MHz */ +#define SC_333MHZ 333333333U /* 333MHz */ +#define SC_350MHZ 350000000U /* 350MHz */ +#define SC_372MHZ 372000000U /* 372MHz */ +#define SC_375MHZ 375000000U /* 375MHz */ +#define SC_400MHZ 400000000U /* 400MHz */ +#define SC_465MHZ 465000000U /* 465MHz */ +#define SC_500MHZ 500000000U /* 500MHz */ +#define SC_594MHZ 594000000U /* 594MHz */ +#define SC_625MHZ 625000000U /* 625MHz */ +#define SC_640MHZ 640000000U /* 640MHz */ +#define SC_650MHZ 650000000U /* 650MHz */ +#define SC_667MHZ 666666667U /* 667MHz */ +#define SC_675MHZ 675000000U /* 675MHz */ +#define SC_700MHZ 700000000U /* 700MHz */ +#define SC_720MHZ 720000000U /* 720MHz */ +#define SC_750MHZ 750000000U /* 750MHz */ +#define SC_800MHZ 800000000U /* 800MHz */ +#define SC_850MHZ 850000000U /* 850MHz */ +#define SC_900MHZ 900000000U /* 900MHz */ +#define SC_1000MHZ 1000000000U /* 1GHz */ +#define SC_1060MHZ 1060000000U /* 1.06GHz */ +#define SC_1188MHZ 1188000000U /* 1.188GHz */ +#define SC_1260MHZ 1260000000U /* 1.26GHz */ +#define SC_1280MHZ 1280000000U /* 1.28GHz */ +#define SC_1300MHZ 1300000000U /* 1.3GHz */ +#define SC_1400MHZ 1400000000U /* 1.4GHz */ +#define SC_1500MHZ 1500000000U /* 1.5GHz */ +#define SC_1600MHZ 1600000000U /* 1.6GHz */ +#define SC_1800MHZ 1800000000U /* 1.8GHz */ +#define SC_1860MHZ 1860000000U /* 1.86GHz */ +#define SC_2000MHZ 2000000000U /* 2.0GHz */ +#define SC_2112MHZ 2112000000U /* 2.12GHz */ + +/* Defines for 24M related frequencies */ +#define SC_8MHZ 8000000U /* 8MHz */ +#define SC_12MHZ 12000000U /* 12MHz */ +#define SC_19MHZ 19800000U /* 19.8MHz */ +#define SC_24MHZ 24000000U /* 24MHz */ +#define SC_48MHZ 48000000U /* 48MHz */ +#define SC_120MHZ 120000000U /* 120MHz */ +#define SC_132MHZ 132000000U /* 132MHz */ +#define SC_144MHZ 144000000U /* 144MHz */ +#define SC_192MHZ 192000000U /* 192MHz */ +#define SC_211MHZ 211200000U /* 211.2MHz */ +#define SC_228MHZ 228000000U /* 233MHz */ +#define SC_240MHZ 240000000U /* 240MHz */ +#define SC_264MHZ 264000000U /* 264MHz */ +#define SC_352MHZ 352000000U /* 352MHz */ +#define SC_360MHZ 360000000U /* 360MHz */ +#define SC_384MHZ 384000000U /* 384MHz */ +#define SC_396MHZ 396000000U /* 396MHz */ +#define SC_432MHZ 432000000U /* 432MHz */ +#define SC_456MHZ 456000000U /* 466MHz */ +#define SC_480MHZ 480000000U /* 480MHz */ +#define SC_600MHZ 600000000U /* 600MHz */ +#define SC_744MHZ 744000000U /* 744MHz */ +#define SC_792MHZ 792000000U /* 792MHz */ +#define SC_864MHZ 864000000U /* 864MHz */ +#define SC_912MHZ 912000000U /* 912MHz */ +#define SC_960MHZ 960000000U /* 960MHz */ +#define SC_1056MHZ 1056000000U /* 1056MHz */ +#define SC_1104MHZ 1104000000U /* 1104MHz */ +#define SC_1200MHZ 1200000000U /* 1.2GHz */ +#define SC_1464MHZ 1464000000U /* 1.464GHz */ +#define SC_2400MHZ 2400000000U /* 2.4GHz */ + +/* Defines for A/V related frequencies */ +#define SC_62MHZ 62937500U /* 62.9375MHz */ +#define SC_755MHZ 755250000U /* 755.25MHz */ + +/* Defines for type widths */ +#define SC_FADDR_W 36U /* Width of sc_faddr_t */ +#define SC_BOOL_W 1U /* Width of sc_bool_t */ +#define SC_ERR_W 4U /* Width of sc_err_t */ +#define SC_RSRC_W 10U /* Width of sc_rsrc_t */ +#define SC_CTRL_W 6U /* Width of sc_ctrl_t */ + +/* Defines for sc_bool_t */ +#define SC_FALSE ((sc_bool_t)0U) +#define SC_TRUE ((sc_bool_t)1U) + +/* Defines for sc_err_t */ +#define SC_ERR_NONE 0U /* Success */ +#define SC_ERR_VERSION 1U /* Incompatible API version */ +#define SC_ERR_CONFIG 2U /* Configuration error */ +#define SC_ERR_PARM 3U /* Bad parameter */ +#define SC_ERR_NOACCESS 4U /* Permission error (no access) */ +#define SC_ERR_LOCKED 5U /* Permission error (locked) */ +#define SC_ERR_UNAVAILABLE 6U /* Unavailable (out of resources) */ +#define SC_ERR_NOTFOUND 7U /* Not found */ +#define SC_ERR_NOPOWER 8U /* No power */ +#define SC_ERR_IPC 9U /* Generic IPC error */ +#define SC_ERR_BUSY 10U /* Resource is currently busy/active */ +#define SC_ERR_FAIL 11U /* General I/O failure */ +#define SC_ERR_LAST 12U + +/* Defines for sc_ctrl_t. */ +#define SC_C_TEMP 0U +#define SC_C_TEMP_HI 1U +#define SC_C_TEMP_LOW 2U +#define SC_C_PXL_LINK_MST1_ADDR 3U +#define SC_C_PXL_LINK_MST2_ADDR 4U +#define SC_C_PXL_LINK_MST_ENB 5U +#define SC_C_PXL_LINK_MST1_ENB 6U +#define SC_C_PXL_LINK_MST2_ENB 7U +#define SC_C_PXL_LINK_SLV1_ADDR 8U +#define SC_C_PXL_LINK_SLV2_ADDR 9U +#define SC_C_PXL_LINK_MST_VLD 10U +#define SC_C_PXL_LINK_MST1_VLD 11U +#define SC_C_PXL_LINK_MST2_VLD 12U +#define SC_C_SINGLE_MODE 13U +#define SC_C_ID 14U +#define SC_C_PXL_CLK_POLARITY 15U +#define SC_C_LINESTATE 16U +#define SC_C_PCIE_G_RST 17U +#define SC_C_PCIE_BUTTON_RST 18U +#define SC_C_PCIE_PERST 19U +#define SC_C_PHY_RESET 20U +#define SC_C_PXL_LINK_RATE_CORRECTION 21U +#define SC_C_PANIC 22U +#define SC_C_PRIORITY_GROUP 23U +#define SC_C_TXCLK 24U +#define SC_C_CLKDIV 25U +#define SC_C_DISABLE_50 26U +#define SC_C_DISABLE_125 27U +#define SC_C_SEL_125 28U +#define SC_C_MODE 29U +#define SC_C_SYNC_CTRL0 30U +#define SC_C_KACHUNK_CNT 31U +#define SC_C_KACHUNK_SEL 32U +#define SC_C_SYNC_CTRL1 33U +#define SC_C_DPI_RESET 34U +#define SC_C_MIPI_RESET 35U +#define SC_C_DUAL_MODE 36U +#define SC_C_VOLTAGE 37U +#define SC_C_PXL_LINK_SEL 38U +#define SC_C_OFS_SEL 39U +#define SC_C_OFS_AUDIO 40U +#define SC_C_OFS_PERIPH 41U +#define SC_C_OFS_IRQ 42U +#define SC_C_RST0 43U +#define SC_C_RST1 44U +#define SC_C_SEL0 45U +#define SC_C_LAST 46U + +#define SC_P_ALL ((sc_pad_t)UINT16_MAX) /* All pads */ + +/* Types */ + +/* This type is used to store a boolean */ +typedef u8 sc_bool_t; + +/* This type is used to store a system (full-size) address. */ +typedef u64 sc_faddr_t; + +/* This type is used to indicate error response for most functions. */ +typedef u8 sc_err_t; + +/* + * This type is used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to at the end of the list). + */ +typedef u16 sc_rsrc_t; + +/* This type is used to indicate a control. */ +typedef u8 sc_ctrl_t; + +/* + * This type is used to indicate a pad. Valid values are SoC specific. + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +typedef u16 sc_pad_t; + +#endif /* SC_TYPES_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8/snvs_security_sc.h b/roms/u-boot/arch/arm/include/asm/arch-imx8/snvs_security_sc.h new file mode 100644 index 000000000..0b7ded7ba --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8/snvs_security_sc.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef _SNVS_SECURITY_SC_H +#define _SNVS_SECURITY_SC_H + +int snvs_security_sc_init(void); + +#endif /* _SNVS_SECURITY_SC_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-imx8/sys_proto.h new file mode 100644 index 000000000..6f1fc8f99 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8/sys_proto.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct pass_over_info_t { + u16 barker; + u16 len; + u32 g_bt_cfg_shadow; + u32 card_address_mode; + u32 bad_block_count_met; + u32 g_ap_mu; +}; + +extern unsigned long boot_pointer[]; +void build_info(void); +enum boot_device get_boot_device(void); +int print_bootinfo(void); +int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate); +int imx8_power_domain_lookup_name(const char *name, + struct power_domain *power_domain); +void imx8_power_off_pd_devices(const char *permanent_on_devices[], int size); +bool m4_parts_booted(void); diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8m/clock.h b/roms/u-boot/arch/arm/include/asm/arch-imx8m/clock.h new file mode 100644 index 000000000..77d9428a1 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8m/clock.h @@ -0,0 +1,278 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + * + * Peng Fan + */ + +#include + +#ifdef CONFIG_IMX8MQ +#include +#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || \ + defined(CONFIG_IMX8MP) +#include +#else +#error "Error no clock.h" +#endif + +#define MHZ(X) ((X) * 1000000UL) + +/* Mainly for compatible to imx common code. */ +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_IPG_CLK, + MXC_CSPI_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, + MXC_I2C_CLK, + MXC_UART_CLK, + MXC_QSPI_CLK, +}; + +enum clk_slice_type { + CORE_CLOCK_SLICE, + BUS_CLOCK_SLICE, + IP_CLOCK_SLICE, + AHB_CLOCK_SLICE, + IPG_CLOCK_SLICE, + CORE_SEL_CLOCK_SLICE, + DRAM_SEL_CLOCK_SLICE, +}; + +enum root_pre_div { + CLK_ROOT_PRE_DIV1 = 0, + CLK_ROOT_PRE_DIV2, + CLK_ROOT_PRE_DIV3, + CLK_ROOT_PRE_DIV4, + CLK_ROOT_PRE_DIV5, + CLK_ROOT_PRE_DIV6, + CLK_ROOT_PRE_DIV7, + CLK_ROOT_PRE_DIV8, +}; + +enum root_post_div { + CLK_ROOT_POST_DIV1 = 0, + CLK_ROOT_POST_DIV2, + CLK_ROOT_POST_DIV3, + CLK_ROOT_POST_DIV4, + CLK_ROOT_POST_DIV5, + CLK_ROOT_POST_DIV6, + CLK_ROOT_POST_DIV7, + CLK_ROOT_POST_DIV8, + CLK_ROOT_POST_DIV9, + CLK_ROOT_POST_DIV10, + CLK_ROOT_POST_DIV11, + CLK_ROOT_POST_DIV12, + CLK_ROOT_POST_DIV13, + CLK_ROOT_POST_DIV14, + CLK_ROOT_POST_DIV15, + CLK_ROOT_POST_DIV16, + CLK_ROOT_POST_DIV17, + CLK_ROOT_POST_DIV18, + CLK_ROOT_POST_DIV19, + CLK_ROOT_POST_DIV20, + CLK_ROOT_POST_DIV21, + CLK_ROOT_POST_DIV22, + CLK_ROOT_POST_DIV23, + CLK_ROOT_POST_DIV24, + CLK_ROOT_POST_DIV25, + CLK_ROOT_POST_DIV26, + CLK_ROOT_POST_DIV27, + CLK_ROOT_POST_DIV28, + CLK_ROOT_POST_DIV29, + CLK_ROOT_POST_DIV30, + CLK_ROOT_POST_DIV31, + CLK_ROOT_POST_DIV32, + CLK_ROOT_POST_DIV33, + CLK_ROOT_POST_DIV34, + CLK_ROOT_POST_DIV35, + CLK_ROOT_POST_DIV36, + CLK_ROOT_POST_DIV37, + CLK_ROOT_POST_DIV38, + CLK_ROOT_POST_DIV39, + CLK_ROOT_POST_DIV40, + CLK_ROOT_POST_DIV41, + CLK_ROOT_POST_DIV42, + CLK_ROOT_POST_DIV43, + CLK_ROOT_POST_DIV44, + CLK_ROOT_POST_DIV45, + CLK_ROOT_POST_DIV46, + CLK_ROOT_POST_DIV47, + CLK_ROOT_POST_DIV48, + CLK_ROOT_POST_DIV49, + CLK_ROOT_POST_DIV50, + CLK_ROOT_POST_DIV51, + CLK_ROOT_POST_DIV52, + CLK_ROOT_POST_DIV53, + CLK_ROOT_POST_DIV54, + CLK_ROOT_POST_DIV55, + CLK_ROOT_POST_DIV56, + CLK_ROOT_POST_DIV57, + CLK_ROOT_POST_DIV58, + CLK_ROOT_POST_DIV59, + CLK_ROOT_POST_DIV60, + CLK_ROOT_POST_DIV61, + CLK_ROOT_POST_DIV62, + CLK_ROOT_POST_DIV63, + CLK_ROOT_POST_DIV64, +}; + +struct clk_root_map { + enum clk_root_index entry; + enum clk_slice_type slice_type; + u32 slice_index; + u8 src_mux[8]; +}; + +struct ccm_ccgr { + u32 ccgr; + u32 ccgr_set; + u32 ccgr_clr; + u32 ccgr_tog; +}; + +struct ccm_root { + u32 target_root; + u32 target_root_set; + u32 target_root_clr; + u32 target_root_tog; + u32 misc; + u32 misc_set; + u32 misc_clr; + u32 misc_tog; + u32 nm_post; + u32 nm_post_root_set; + u32 nm_post_root_clr; + u32 nm_post_root_tog; + u32 nm_pre; + u32 nm_pre_root_set; + u32 nm_pre_root_clr; + u32 nm_pre_root_tog; + u32 db_post; + u32 db_post_root_set; + u32 db_post_root_clr; + u32 db_post_root_tog; + u32 db_pre; + u32 db_pre_root_set; + u32 db_pre_root_clr; + u32 db_pre_root_tog; + u32 reserved[4]; + u32 access_ctrl; + u32 access_ctrl_root_set; + u32 access_ctrl_root_clr; + u32 access_ctrl_root_tog; +}; + +struct ccm_reg { + u32 reserved_0[4096]; + struct ccm_ccgr ccgr_array[192]; + u32 reserved_1[3328]; + struct ccm_root core_root[5]; + u32 reserved_2[352]; + struct ccm_root bus_root[12]; + u32 reserved_3[128]; + struct ccm_root ahb_ipg_root[4]; + u32 reserved_4[384]; + struct ccm_root dram_sel; + struct ccm_root core_sel; + u32 reserved_5[448]; + struct ccm_root ip_root[78]; +}; + +enum enet_freq { + ENET_25MHZ = 0, + ENET_50MHZ, + ENET_125MHZ, +}; + +#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \ + { \ + .clk = (_rate), \ + .alt_root_sel = (_m), \ + .alt_pre_div = (_p), \ + .apb_root_sel = (_s), \ + .apb_pre_div = (_k), \ + } + +struct dram_bypass_clk_setting { + ulong clk; + int alt_root_sel; + enum root_pre_div alt_pre_div; + int apb_root_sel; + enum root_pre_div apb_pre_div; +}; + +#define CCGR_CLK_ON_MASK 0x03 +#define CLK_SRC_ON_MASK 0x03 + +#define CLK_ROOT_ON BIT(28) +#define CLK_ROOT_OFF (0 << 28) +#define CLK_ROOT_ENABLE_MASK BIT(28) +#define CLK_ROOT_ENABLE_SHIFT 28 +#define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24) + +/* For SEL, only use 1 bit */ +#define CLK_ROOT_SRC_MUX_MASK 0x07000000 +#define CLK_ROOT_SRC_MUX_SHIFT 24 +#define CLK_ROOT_SRC_0 0x00000000 +#define CLK_ROOT_SRC_1 0x01000000 +#define CLK_ROOT_SRC_2 0x02000000 +#define CLK_ROOT_SRC_3 0x03000000 +#define CLK_ROOT_SRC_4 0x04000000 +#define CLK_ROOT_SRC_5 0x05000000 +#define CLK_ROOT_SRC_6 0x06000000 +#define CLK_ROOT_SRC_7 0x07000000 + +#define CLK_ROOT_PRE_DIV_MASK (0x00070000) +#define CLK_ROOT_PRE_DIV_SHIFT 16 +#define CLK_ROOT_PRE_DIV(n) (((n) << 16) & 0x00070000) + +#define CLK_ROOT_AUDO_SLOW_EN 0x1000 + +#define CLK_ROOT_AUDO_DIV_MASK 0x700 +#define CLK_ROOT_AUDO_DIV_SHIFT 0x8 +#define CLK_ROOT_AUDO_DIV(n) (((n) << 8) & 0x700) + +/* For CORE: mask is 0x7; For IPG: mask is 0x3 */ +#define CLK_ROOT_POST_DIV_MASK 0x3f +#define CLK_ROOT_CORE_POST_DIV_MASK 0x7 +#define CLK_ROOT_IPG_POST_DIV_MASK 0x3 +#define CLK_ROOT_POST_DIV_SHIFT 0 +#define CLK_ROOT_POST_DIV(n) ((n) & 0x3f) +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 +#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000 +#define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M 0x01000000 +#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000 + +void dram_pll_init(ulong pll_val); +void dram_enable_bypass(ulong clk_val); +void dram_disable_bypass(void); +u32 imx_get_fecclk(void); +u32 imx_get_uartclk(void); +int clock_init(void); +void init_clk_usdhc(u32 index); +void init_uart_clk(u32 index); +void init_wdog_clk(void); +unsigned int mxc_get_clock(enum mxc_clock clk); +int clock_enable(enum clk_ccgr_index index, bool enable); +int clock_root_enabled(enum clk_root_index clock_id); +int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div, + enum root_post_div post_div, enum clk_root_src clock_src); +int clock_set_target_val(enum clk_root_index clock_id, u32 val); +int clock_get_target_val(enum clk_root_index clock_id, u32 *val); +int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div); +int clock_get_postdiv(enum clk_root_index clock_id, + enum root_post_div *post_div); +int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src); +void mxs_set_lcdclk(u32 base_addr, u32 freq); +int set_clk_qspi(void); +void enable_ocotp_clk(unsigned char enable); +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); +int set_clk_enet(enum enet_freq type); +int set_clk_eqos(enum enet_freq type); +void hab_caam_clock_enable(unsigned char enable); diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/roms/u-boot/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h new file mode 100644 index 000000000..63b14b9ca --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h @@ -0,0 +1,580 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018-2019 NXP + * + * Peng Fan + */ + +#ifndef _ASM_ARCH_IMX8MM_CLOCK_H +#define _ASM_ARCH_IMX8MM_CLOCK_H + +#ifndef __ASSEMBLY__ +#include +#endif + +#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ + { \ + .rate = (_rate), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + .kdiv = (_k), \ + } + +#define LOCK_STATUS BIT(31) +#define LOCK_SEL_MASK BIT(29) +#define CLKE_MASK BIT(13) +#define RST_MASK BIT(9) +#define BYPASS_MASK BIT(4) +#define MDIV_SHIFT 12 +#define MDIV_MASK GENMASK(21, 12) +#define PDIV_SHIFT 4 +#define PDIV_MASK GENMASK(9, 4) +#define SDIV_SHIFT 0 +#define SDIV_MASK GENMASK(2, 0) +#define KDIV_SHIFT 0 +#define KDIV_MASK GENMASK(15, 0) + +struct imx_int_pll_rate_table { + u32 rate; + int mdiv; + int pdiv; + int sdiv; + int kdiv; +}; + +enum pll_clocks { + ANATOP_ARM_PLL, + ANATOP_VPU_PLL, + ANATOP_GPU_PLL, + ANATOP_SYSTEM_PLL1, + ANATOP_SYSTEM_PLL2, + ANATOP_SYSTEM_PLL3, + ANATOP_AUDIO_PLL1, + ANATOP_AUDIO_PLL2, + ANATOP_VIDEO_PLL, + ANATOP_DRAM_PLL, +}; + +#ifdef CONFIG_IMX8MP +enum clk_root_index { + ARM_A53_CLK_ROOT = 0, + ARM_M7_CLK_ROOT = 1, + ML_CLK_ROOT = 2, + GPU3D_CORE_CLK_ROOT = 3, + GPU3D_SHADER_CLK_ROOT = 4, + GPU2D_CLK_ROOT = 5, + AUDIO_AXI_CLK_ROOT = 6, + HSIO_AXI_CLK_ROOT = 7, + MEDIA_ISP_CLK_ROOT = 8, + MAIN_AXI_CLK_ROOT = 16, + ENET_AXI_CLK_ROOT = 17, + NAND_USDHC_BUS_CLK_ROOT = 18, + VPU_BUS_CLK_ROOT = 19, + MEDIA_AXI_CLK_ROOT = 20, + MEDIA_APB_CLK_ROOT = 21, + HDMI_APB_CLK_ROOT = 22, + HDMI_AXI_CLK_ROOT = 23, + GPU_AXI_CLK_ROOT = 24, + GPU_AHB_CLK_ROOT = 25, + NOC_CLK_ROOT = 26, + NOC_IO_CLK_ROOT = 27, + ML_AXI_CLK_ROOT = 28, + ML_AHB_CLK_ROOT = 29, + AHB_CLK_ROOT = 32, + IPG_CLK_ROOT = 33, + AUDIO_AHB_CLK_ROOT = 34, + MIPI_DSI_ESC_RX_CLK_ROOT = 36, + MEDIA_DISP2_CLK_ROOT = 38, + DRAM_SEL_CFG = 48, + CORE_SEL_CFG = 49, + DRAM_ALT_CLK_ROOT = 64, + DRAM_APB_CLK_ROOT = 65, + VPU_G1_CLK_ROOT = 66, + VPU_G2_CLK_ROOT = 67, + CAN1_CLK_ROOT = 68, + CAN2_CLK_ROOT = 69, + PCIE_PHY_CLK_ROOT = 71, + PCIE_AUX_CLK_ROOT = 72, + I2C5_CLK_ROOT = 73, + I2C6_CLK_ROOT = 74, + SAI1_CLK_ROOT = 75, + SAI2_CLK_ROOT = 76, + SAI3_CLK_ROOT = 77, + SAI4_CLK_ROOT = 78, + SAI5_CLK_ROOT = 79, + SAI6_CLK_ROOT = 80, + ENET_QOS_CLK_ROOT = 81, + ENET_QOS_TIMER_CLK_ROOT = 82, + ENET_REF_CLK_ROOT = 83, + ENET_TIMER_CLK_ROOT = 84, + ENET_PHY_REF_CLK_ROOT = 85, + NAND_CLK_ROOT = 86, + QSPI_CLK_ROOT = 87, + USDHC1_CLK_ROOT = 88, + USDHC2_CLK_ROOT = 89, + I2C1_CLK_ROOT = 90, + I2C2_CLK_ROOT = 91, + I2C3_CLK_ROOT = 92, + I2C4_CLK_ROOT = 93, + UART1_CLK_ROOT = 94, + UART2_CLK_ROOT = 95, + UART3_CLK_ROOT = 96, + UART4_CLK_ROOT = 97, + USB_CORE_REF_CLK_ROOT = 98, + USB_PHY_REF_CLK_ROOT = 99, + GIC_CLK_ROOT = 100, + ECSPI1_CLK_ROOT = 101, + ECSPI2_CLK_ROOT = 102, + PWM1_CLK_ROOT = 103, + PWM2_CLK_ROOT = 104, + PWM3_CLK_ROOT = 105, + PWM4_CLK_ROOT = 106, + GPT1_CLK_ROOT = 107, + GPT2_CLK_ROOT = 108, + GPT3_CLK_ROOT = 109, + GPT4_CLK_ROOT = 110, + GPT5_CLK_ROOT = 111, + GPT6_CLK_ROOT = 112, + TRACE_CLK_ROOT = 113, + WDOG_CLK_ROOT = 114, + WRCLK_CLK_ROOT = 115, + IPP_DO_CLKO1 = 116, + IPP_DO_CLKO2 = 117, + HDMI_FDCC_TST_CLK_ROOT = 118, + HDMI_27M_CLK_ROOT = 119, + HDMI_REF_266M_CLK_ROOT = 120, + USDHC3_CLK_ROOT = 121, + MEDIA_CAM1_PIX_CLK_ROOT = 122, + MEDIA_MIPI_PHY1_REF_CLK_ROOT = 123, + MEDIA_DISP1_PIX_CLK_ROOT = 124, + MEDIA_CAM2_PIX_CLK_ROOT = 125, + MEDIA_LDB_CLK_ROOT = 126, + MEMREPAIR_CLK_ROOT = 127, + MEDIA_MIPI_TEST_BYTE_CLK = 130, + ECSPI3_CLK_ROOT = 131, + PDM_CLK_ROOT = 132, + VPU_VC8000E_CLK_ROOT = 133, + SAI7_CLK_ROOT = 134, + CLK_ROOT_MAX, +}; +#elif defined(CONFIG_IMX8MN) +enum clk_root_index { + ARM_A53_CLK_ROOT = 0, + ARM_M7_CLK_ROOT = 1, + GPU_CORE_CLK_ROOT = 3, + GPU_SHADER_CLK_ROOT = 4, + MAIN_AXI_CLK_ROOT = 16, + ENET_AXI_CLK_ROOT = 17, + NAND_USDHC_BUS_CLK_ROOT = 18, + DISPLAY_AXI_CLK_ROOT = 20, + DISPLAY_APB_CLK_ROOT = 21, + USB_BUS_CLK_ROOT = 23, + GPU_AXI_CLK_ROOT = 24, + GPU_AHB_CLK_ROOT = 25, + NOC_CLK_ROOT = 26, + AHB_CLK_ROOT = 32, + IPG_CLK_ROOT = 33, + AUDIO_AHB_CLK_ROOT = 34, + DRAM_SEL_CFG = 48, + CORE_SEL_CFG = 49, + DRAM_ALT_CLK_ROOT = 64, + DRAM_APB_CLK_ROOT = 65, + DISPLAY_PIXEL_CLK_ROOT = 74, + SAI2_CLK_ROOT = 76, + SAI3_CLK_ROOT = 77, + SAI5_CLK_ROOT = 79, + SAI6_CLK_ROOT = 80, + SPDIF1_CLK_ROOT = 81, + ENET_REF_CLK_ROOT = 83, + ENET_TIMER_CLK_ROOT = 84, + ENET_PHY_REF_CLK_ROOT = 85, + NAND_CLK_ROOT = 86, + QSPI_CLK_ROOT = 87, + USDHC1_CLK_ROOT = 88, + USDHC2_CLK_ROOT = 89, + I2C1_CLK_ROOT = 90, + I2C2_CLK_ROOT = 91, + I2C3_CLK_ROOT = 92, + I2C4_CLK_ROOT = 93, + UART1_CLK_ROOT = 94, + UART2_CLK_ROOT = 95, + UART3_CLK_ROOT = 96, + UART4_CLK_ROOT = 97, + USB_CORE_REF_CLK_ROOT = 98, + USB_PHY_REF_CLK_ROOT = 99, + GIC_CLK_ROOT = 100, + ECSPI1_CLK_ROOT = 101, + ECSPI2_CLK_ROOT = 102, + PWM1_CLK_ROOT = 103, + PWM2_CLK_ROOT = 104, + PWM3_CLK_ROOT = 105, + PWM4_CLK_ROOT = 106, + GPT1_CLK_ROOT = 107, + GPT2_CLK_ROOT = 108, + GPT3_CLK_ROOT = 109, + GPT4_CLK_ROOT = 110, + GPT5_CLK_ROOT = 111, + GPT6_CLK_ROOT = 112, + TRACE_CLK_ROOT = 113, + WDOG_CLK_ROOT = 114, + WRCLK_CLK_ROOT = 115, + IPP_DO_CLKO1 = 116, + IPP_DO_CLKO2 = 117, + MIPI_DSI_CORE_CLK_ROOT = 118, + DISPLAY_DSI_PHY_REF_CLK_ROOT = 119, + MIPI_DSI_DBI_CLK_ROOT = 120, + USDHC3_CLK_ROOT = 121, + DISPLAY_CAMERA_PIXEL_CLK_ROOT = 122, + MIPI_CSI1_PHY_REF_CLK_ROOT = 123, + MIPI_CSI2_PHY_REF_CLK_ROOT = 126, + MIPI_CSI2_ESC_CLK_ROOT = 127, + ECSPI3_CLK_ROOT = 131, + PDM_CLK_ROOT = 132, + SAI7_CLK_ROOT = 134, + CLK_ROOT_MAX, +}; +#else +enum clk_root_index { + ARM_A53_CLK_ROOT = 0, + ARM_M4_CLK_ROOT = 1, + VPU_A53_CLK_ROOT = 2, + GPU3D_CLK_ROOT = 3, + GPU2D_CLK_ROOT = 4, + MAIN_AXI_CLK_ROOT = 16, + ENET_AXI_CLK_ROOT = 17, + NAND_USDHC_BUS_CLK_ROOT = 18, + VPU_BUS_CLK_ROOT = 19, + DISPLAY_AXI_CLK_ROOT = 20, + DISPLAY_APB_CLK_ROOT = 21, + DISPLAY_RTRM_CLK_ROOT = 22, + USB_BUS_CLK_ROOT = 23, + GPU_AXI_CLK_ROOT = 24, + GPU_AHB_CLK_ROOT = 25, + NOC_CLK_ROOT = 26, + NOC_APB_CLK_ROOT = 27, + AHB_CLK_ROOT = 32, + IPG_CLK_ROOT = 33, + AUDIO_AHB_CLK_ROOT = 34, + MIPI_DSI_ESC_RX_CLK_ROOT = 36, + DRAM_SEL_CFG = 48, + CORE_SEL_CFG = 49, + DRAM_ALT_CLK_ROOT = 64, + DRAM_APB_CLK_ROOT = 65, + VPU_G1_CLK_ROOT = 66, + VPU_G2_CLK_ROOT = 67, + DISPLAY_DTRC_CLK_ROOT = 68, + DISPLAY_DC8000_CLK_ROOT = 69, + PCIE_CTRL_CLK_ROOT = 70, + PCIE_PHY_CLK_ROOT = 71, + PCIE_AUX_CLK_ROOT = 72, + DC_PIXEL_CLK_ROOT = 73, + LCDIF_PIXEL_CLK_ROOT = 74, + SAI1_CLK_ROOT = 75, + SAI2_CLK_ROOT = 76, + SAI3_CLK_ROOT = 77, + SAI4_CLK_ROOT = 78, + SAI5_CLK_ROOT = 79, + SAI6_CLK_ROOT = 80, + SPDIF1_CLK_ROOT = 81, + SPDIF2_CLK_ROOT = 82, + ENET_REF_CLK_ROOT = 83, + ENET_TIMER_CLK_ROOT = 84, + ENET_PHY_REF_CLK_ROOT = 85, + NAND_CLK_ROOT = 86, + QSPI_CLK_ROOT = 87, + USDHC1_CLK_ROOT = 88, + USDHC2_CLK_ROOT = 89, + I2C1_CLK_ROOT = 90, + I2C2_CLK_ROOT = 91, + I2C3_CLK_ROOT = 92, + I2C4_CLK_ROOT = 93, + UART1_CLK_ROOT = 94, + UART2_CLK_ROOT = 95, + UART3_CLK_ROOT = 96, + UART4_CLK_ROOT = 97, + USB_CORE_REF_CLK_ROOT = 98, + USB_PHY_REF_CLK_ROOT = 99, + GIC_CLK_ROOT = 100, + ECSPI1_CLK_ROOT = 101, + ECSPI2_CLK_ROOT = 102, + PWM1_CLK_ROOT = 103, + PWM2_CLK_ROOT = 104, + PWM3_CLK_ROOT = 105, + PWM4_CLK_ROOT = 106, + GPT1_CLK_ROOT = 107, + GPT2_CLK_ROOT = 108, + GPT3_CLK_ROOT = 109, + GPT4_CLK_ROOT = 110, + GPT5_CLK_ROOT = 111, + GPT6_CLK_ROOT = 112, + TRACE_CLK_ROOT = 113, + WDOG_CLK_ROOT = 114, + WRCLK_CLK_ROOT = 115, + IPP_DO_CLKO1 = 116, + IPP_DO_CLKO2 = 117, + MIPI_DSI_CORE_CLK_ROOT = 118, + MIPI_DSI_PHY_REF_CLK_ROOT = 119, + MIPI_DSI_DBI_CLK_ROOT = 120, + USDHC3_CLK_ROOT = 121, + MIPI_CSI1_CORE_CLK_ROOT = 122, + MIPI_CSI1_PHY_REF_CLK_ROOT = 123, + MIPI_CSI1_ESC_CLK_ROOT = 124, + MIPI_CSI2_CORE_CLK_ROOT = 125, + MIPI_CSI2_PHY_REF_CLK_ROOT = 126, + MIPI_CSI2_ESC_CLK_ROOT = 127, + PCIE2_CTRL_CLK_ROOT = 128, + PCIE2_PHY_CLK_ROOT = 129, + PCIE2_AUX_CLK_ROOT = 130, + ECSPI3_CLK_ROOT = 131, + PDM_CLK_ROOT = 132, + VPU_H1_CLK_ROOT = 133, + CLK_ROOT_MAX, +}; +#endif + +enum clk_root_src { + OSC_24M_CLK, + ARM_PLL_CLK, + DRAM_PLL1_CLK, + VIDEO_PLL2_CLK, + VPU_PLL_CLK, + GPU_PLL_CLK, + SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_266M_CLK, + SYSTEM_PLL1_200M_CLK, + SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_133M_CLK, + SYSTEM_PLL1_100M_CLK, + SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL2_500M_CLK, + SYSTEM_PLL2_333M_CLK, + SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_166M_CLK, + SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, + AUDIO_PLL1_CLK, + AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, + OSC_32K_CLK, + EXT_CLK_1, + EXT_CLK_2, + EXT_CLK_3, + EXT_CLK_4, + OSC_HDMI_CLK, + ARM_A53_ALT_CLK, +}; + +enum clk_ccgr_index { + CCGR_DVFS = 0, + CCGR_ANAMIX = 1, + CCGR_CPU = 2, + CCGR_CSU = 3, + CCGR_DEBUG = 4, + CCGR_DDR1 = 5, + CCGR_ECSPI1 = 7, + CCGR_ECSPI2 = 8, + CCGR_ECSPI3 = 9, + CCGR_ENET1 = 10, + CCGR_GPIO1 = 11, + CCGR_GPIO2 = 12, + CCGR_GPIO3 = 13, + CCGR_GPIO4 = 14, + CCGR_GPIO5 = 15, + CCGR_GPT1 = 16, + CCGR_GPT2 = 17, + CCGR_GPT3 = 18, + CCGR_GPT4 = 19, + CCGR_AAM_8MP = 20, + CCGR_GPT5 = 20, + CCGR_GPT6 = 21, + CCGR_HS = 22, + CCGR_I2C1 = 23, + CCGR_I2C2 = 24, + CCGR_I2C3 = 25, + CCGR_I2C4 = 26, + CCGR_IOMUX = 27, + CCGR_IOMUX1 = 28, + CCGR_IOMUX2 = 29, + CCGR_IOMUX3 = 30, + CCGR_IOMUX4 = 31, + CCGR_SNVSMIX_IPG_CLK = 32, + CCGR_MU = 33, + CCGR_OCOTP = 34, + CCGR_OCRAM = 35, + CCGR_OCRAM_S = 36, + CCGR_PCIE = 37, + CCGR_PERFMON1 = 38, + CCGR_PERFMON2 = 39, + CCGR_PWM1 = 40, + CCGR_PWM2 = 41, + CCGR_PWM3 = 42, + CCGR_PWM4 = 43, + CCGR_QOS = 44, + CCGR_QOS_DISPMIX = 45, + CCGR_QOS_ETHENET = 46, + CCGR_QSPI = 47, + CCGR_RAWNAND = 48, + CCGR_RDC = 49, + CCGR_ROM = 50, + CCGR_I2C5_8MP = 51, + CCGR_SAI1 = 51, + CCGR_I2C6_8MP = 52, + CCGR_SAI2 = 52, + CCGR_SAI3 = 53, + CCGR_SAI4 = 54, + CCGR_SAI5 = 55, + CCGR_SAI6 = 56, + CCGR_SCTR = 57, + CCGR_SDMA1 = 58, + CCGR_SDMA2 = 59, + CCGR_SEC_DEBUG = 60, + CCGR_SEMA1 = 61, + CCGR_SEMA2 = 62, + CCGR_IRQ_STEER_8MP = 63, + CCGR_SIM_DISPLAY = 63, + CCGR_SIM_ENET = 64, + CCGR_SIM_M = 65, + CCGR_SIM_MAIN = 66, + CCGR_SIM_S = 67, + CCGR_SIM_WAKEUP = 68, + CCGR_GPU2D_8MP = 69, + CCGR_SIM_HSIO = 69, + CCGR_GPU3D_8MP = 70, + CCGR_SIM_VPU = 70, + CCGR_SNVS = 71, + CCGR_TRACE = 72, + CCGR_UART1 = 73, + CCGR_UART2 = 74, + CCGR_UART3 = 75, + CCGR_UART4 = 76, + CCGR_USB_MSCALE_PL301 = 77, + CCGR_USB_PHY_8MP = 79, + CCGR_GPU3D = 79, + CCGR_USDHC1 = 81, + CCGR_USDHC2 = 82, + CCGR_WDOG1 = 83, + CCGR_WDOG2 = 84, + CCGR_WDOG3 = 85, + CCGR_VPUG1 = 86, + CCGR_GPU_BUS = 87, + CCGR_VPUH1 = 89, + CCGR_VPUG2 = 90, + CCGR_PDM = 91, + CCGR_GIC = 92, + CCGR_DISPMIX = 93, + CCGR_USDHC3 = 94, + CCGR_SDMA3 = 95, + CCGR_XTAL = 96, + CCGR_PLL = 97, + CCGR_TEMP_SENSOR = 98, + CCGR_VPUMIX_BUS = 99, + CCGR_SAI7 = 101, + CCGR_GPU2D = 102, + CCGR_MAX +}; + +enum clk_src_index { + CLK_SRC_CKIL_SYNC_REQ = 0, + CLK_SRC_ARM_PLL_EN = 1, + CLK_SRC_GPU_PLL_EN = 2, + CLK_SRC_VPU_PLL_EN = 3, + CLK_SRC_DRAM_PLL_EN = 4, + CLK_SRC_SYSTEM_PLL1_EN = 5, + CLK_SRC_SYSTEM_PLL2_EN = 6, + CLK_SRC_SYSTEM_PLL3_EN = 7, + CLK_SRC_AUDIO_PLL1_EN = 8, + CLK_SRC_AUDIO_PLL2_EN = 9, + CLK_SRC_VIDEO_PLL1_EN = 10, + CLK_SRC_RESERVED = 11, + CLK_SRC_ARM_PLL = 12, + CLK_SRC_GPU_PLL = 13, + CLK_SRC_VPU_PLL = 14, + CLK_SRC_DRAM_PLL = 15, + CLK_SRC_SYSTEM_PLL1_800M = 16, + CLK_SRC_SYSTEM_PLL1_400M = 17, + CLK_SRC_SYSTEM_PLL1_266M = 18, + CLK_SRC_SYSTEM_PLL1_200M = 19, + CLK_SRC_SYSTEM_PLL1_160M = 20, + CLK_SRC_SYSTEM_PLL1_133M = 21, + CLK_SRC_SYSTEM_PLL1_100M = 22, + CLK_SRC_SYSTEM_PLL1_80M = 23, + CLK_SRC_SYSTEM_PLL1_40M = 24, + CLK_SRC_SYSTEM_PLL2_1000M = 25, + CLK_SRC_SYSTEM_PLL2_500M = 26, + CLK_SRC_SYSTEM_PLL2_333M = 27, + CLK_SRC_SYSTEM_PLL2_250M = 28, + CLK_SRC_SYSTEM_PLL2_200M = 29, + CLK_SRC_SYSTEM_PLL2_166M = 30, + CLK_SRC_SYSTEM_PLL2_125M = 31, + CLK_SRC_SYSTEM_PLL2_100M = 32, + CLK_SRC_SYSTEM_PLL2_50M = 33, + CLK_SRC_SYSTEM_PLL3 = 34, + CLK_SRC_AUDIO_PLL1 = 35, + CLK_SRC_AUDIO_PLL2 = 36, + CLK_SRC_VIDEO_PLL1 = 37, +}; + +#define INTPLL_LOCK_MASK BIT(31) +#define INTPLL_LOCK_SEL_MASK BIT(29) +#define INTPLL_EXT_BYPASS_MASK BIT(28) +#define INTPLL_DIV20_CLKE_MASK BIT(27) +#define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26) +#define INTPLL_DIV10_CLKE_MASK BIT(25) +#define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24) +#define INTPLL_DIV8_CLKE_MASK BIT(23) +#define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22) +#define INTPLL_DIV6_CLKE_MASK BIT(21) +#define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20) +#define INTPLL_DIV5_CLKE_MASK BIT(19) +#define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18) +#define INTPLL_DIV4_CLKE_MASK BIT(17) +#define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16) +#define INTPLL_DIV3_CLKE_MASK BIT(15) +#define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14) +#define INTPLL_DIV2_CLKE_MASK BIT(13) +#define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12) +#define INTPLL_CLKE_MASK BIT(11) +#define INTPLL_CLKE_OVERRIDE_MASK BIT(10) +#define INTPLL_RST_MASK BIT(9) +#define INTPLL_RST_OVERRIDE_MASK BIT(8) +#define INTPLL_BYPASS_MASK BIT(4) +#define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2) +#define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0) + +#define INTPLL_MAIN_DIV_MASK GENMASK(21, 12) +#define INTPLL_MAIN_DIV_VAL(n) ((n << 12) & GENMASK(21, 12)) +#define INTPLL_MAIN_DIV_SHIFT 12 +#define INTPLL_PRE_DIV_MASK GENMASK(9, 4) +#define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9, 4)) +#define INTPLL_PRE_DIV_SHIFT 4 +#define INTPLL_POST_DIV_MASK GENMASK(2, 0) +#define INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2, 0)) +#define INTPLL_POST_DIV_SHIFT 0 + +#define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4) +#define INTPLL_LOCK_CON_DLY_SHIFT 4 +#define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2) +#define INTPLL_LOCK_CON_OUT_SHIFT 2 +#define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0) +#define INTPLL_LOCK_CON_IN_SHIFT 0 + +#define INTPLL_LRD_EN_MASK BIT(21) +#define INTPLL_FOUT_MASK BIT(20) +#define INTPLL_AFC_SEL_MASK BIT(19) +#define INTPLL_PBIAS_CTRL_MASK BIT(18) +#define INTPLL_PBIAS_CTRL_EN_MASK BIT(17) +#define INTPLL_AFCINIT_SEL_MASK BIT(16) +#define INTPLL_FSEL_MASK BIT(14) +#define INTPLL_FEED_EN_MASK BIT(13) +#define INTPLL_EXTAFC_MASK GENMASK(7, 3) +#define INTPLL_AFC_EN_MASK BIT(2) +#define INTPLL_ICP_MASK GENMASK(1, 0) + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/roms/u-boot/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h new file mode 100644 index 000000000..340a61e55 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h @@ -0,0 +1,431 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + * + * Peng Fan + */ + +#ifndef _ASM_ARCH_IMX8M_CLOCK_H +#define _ASM_ARCH_IMX8M_CLOCK_H + +#ifndef __ASSEMBLY__ +#include +#endif + +enum pll_clocks { + ANATOP_ARM_PLL, + ANATOP_GPU_PLL, + ANATOP_SYSTEM_PLL1, + ANATOP_SYSTEM_PLL2, + ANATOP_SYSTEM_PLL3, + ANATOP_AUDIO_PLL1, + ANATOP_AUDIO_PLL2, + ANATOP_VIDEO_PLL1, + ANATOP_VIDEO_PLL2, + ANATOP_DRAM_PLL, +}; + +enum clk_root_index { + ARM_A53_CLK_ROOT = 0, + ARM_M4_CLK_ROOT = 1, + VPU_A53_CLK_ROOT = 2, + GPU_CORE_CLK_ROOT = 3, + GPU_SHADER_CLK_ROOT = 4, + MAIN_AXI_CLK_ROOT = 16, + ENET_AXI_CLK_ROOT = 17, + NAND_USDHC_BUS_CLK_ROOT = 18, + VPU_BUS_CLK_ROOT = 19, + DISPLAY_AXI_CLK_ROOT = 20, + DISPLAY_APB_CLK_ROOT = 21, + DISPLAY_RTRM_CLK_ROOT = 22, + USB_BUS_CLK_ROOT = 23, + GPU_AXI_CLK_ROOT = 24, + GPU_AHB_CLK_ROOT = 25, + NOC_CLK_ROOT = 26, + NOC_APB_CLK_ROOT = 27, + AHB_CLK_ROOT = 32, + IPG_CLK_ROOT = 33, + AUDIO_AHB_CLK_ROOT = 34, + MIPI_DSI_ESC_RX_CLK_ROOT = 36, + DRAM_SEL_CFG = 48, + CORE_SEL_CFG = 49, + DRAM_ALT_CLK_ROOT = 64, + DRAM_APB_CLK_ROOT = 65, + VPU_G1_CLK_ROOT = 66, + VPU_G2_CLK_ROOT = 67, + DISPLAY_DTRC_CLK_ROOT = 68, + DISPLAY_DC8000_CLK_ROOT = 69, + PCIE1_CTRL_CLK_ROOT = 70, + PCIE1_PHY_CLK_ROOT = 71, + PCIE1_AUX_CLK_ROOT = 72, + DC_PIXEL_CLK_ROOT = 73, + LCDIF_PIXEL_CLK_ROOT = 74, + SAI1_CLK_ROOT = 75, + SAI2_CLK_ROOT = 76, + SAI3_CLK_ROOT = 77, + SAI4_CLK_ROOT = 78, + SAI5_CLK_ROOT = 79, + SAI6_CLK_ROOT = 80, + SPDIF1_CLK_ROOT = 81, + SPDIF2_CLK_ROOT = 82, + ENET_REF_CLK_ROOT = 83, + ENET_TIMER_CLK_ROOT = 84, + ENET_PHY_REF_CLK_ROOT = 85, + NAND_CLK_ROOT = 86, + QSPI_CLK_ROOT = 87, + USDHC1_CLK_ROOT = 88, + USDHC2_CLK_ROOT = 89, + I2C1_CLK_ROOT = 90, + I2C2_CLK_ROOT = 91, + I2C3_CLK_ROOT = 92, + I2C4_CLK_ROOT = 93, + UART1_CLK_ROOT = 94, + UART2_CLK_ROOT = 95, + UART3_CLK_ROOT = 96, + UART4_CLK_ROOT = 97, + USB_CORE_REF_CLK_ROOT = 98, + USB_PHY_REF_CLK_ROOT = 99, + GIC_CLK_ROOT = 100, + ECSPI1_CLK_ROOT = 101, + ECSPI2_CLK_ROOT = 102, + PWM1_CLK_ROOT = 103, + PWM2_CLK_ROOT = 104, + PWM3_CLK_ROOT = 105, + PWM4_CLK_ROOT = 106, + GPT1_CLK_ROOT = 107, + GPT2_CLK_ROOT = 108, + GPT3_CLK_ROOT = 109, + GPT4_CLK_ROOT = 110, + GPT5_CLK_ROOT = 111, + GPT6_CLK_ROOT = 112, + TRACE_CLK_ROOT = 113, + WDOG_CLK_ROOT = 114, + WRCLK_CLK_ROOT = 115, + IPP_DO_CLKO1 = 116, + IPP_DO_CLKO2 = 117, + MIPI_DSI_CORE_CLK_ROOT = 118, + MIPI_DSI_PHY_REF_CLK_ROOT = 119, + MIPI_DSI_DBI_CLK_ROOT = 120, + OLD_MIPI_DSI_ESC_CLK_ROOT = 121, + MIPI_CSI1_CORE_CLK_ROOT = 122, + MIPI_CSI1_PHY_REF_CLK_ROOT = 123, + MIPI_CSI1_ESC_CLK_ROOT = 124, + MIPI_CSI2_CORE_CLK_ROOT = 125, + MIPI_CSI2_PHY_REF_CLK_ROOT = 126, + MIPI_CSI2_ESC_CLK_ROOT = 127, + PCIE2_CTRL_CLK_ROOT = 128, + PCIE2_PHY_CLK_ROOT = 129, + PCIE2_AUX_CLK_ROOT = 130, + ECSPI3_CLK_ROOT = 131, + OLD_MIPI_DSI_ESC_RX_ROOT = 132, + DISPLAY_HDMI_CLK_ROOT = 133, + CLK_ROOT_MAX, +}; + +enum clk_root_src { + OSC_25M_CLK, + ARM_PLL_CLK, + DRAM_PLL1_CLK, + VIDEO_PLL2_CLK, + VPU_PLL_CLK, + GPU_PLL_CLK, + SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_266M_CLK, + SYSTEM_PLL1_200M_CLK, + SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_133M_CLK, + SYSTEM_PLL1_100M_CLK, + SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL2_500M_CLK, + SYSTEM_PLL2_333M_CLK, + SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_166M_CLK, + SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, + AUDIO_PLL1_CLK, + AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, + OSC_32K_CLK, + EXT_CLK_1, + EXT_CLK_2, + EXT_CLK_3, + EXT_CLK_4, + OSC_27M_CLK, + ARM_A53_ALT_CLK, +}; + +/* CCGR index */ +enum clk_ccgr_index { + CCGR_DVFS = 0, + CCGR_ANAMIX = 1, + CCGR_CPU = 2, + CCGR_CSU = 4, + CCGR_DRAM1 = 5, + CCGR_DRAM2_OBSOLETE = 6, + CCGR_ECSPI1 = 7, + CCGR_ECSPI2 = 8, + CCGR_ECSPI3 = 9, + CCGR_ENET1 = 10, + CCGR_GPIO1 = 11, + CCGR_GPIO2 = 12, + CCGR_GPIO3 = 13, + CCGR_GPIO4 = 14, + CCGR_GPIO5 = 15, + CCGR_GPT1 = 16, + CCGR_GPT2 = 17, + CCGR_GPT3 = 18, + CCGR_GPT4 = 19, + CCGR_GPT5 = 20, + CCGR_GPT6 = 21, + CCGR_HS = 22, + CCGR_I2C1 = 23, + CCGR_I2C2 = 24, + CCGR_I2C3 = 25, + CCGR_I2C4 = 26, + CCGR_IOMUX = 27, + CCGR_IOMUX1 = 28, + CCGR_IOMUX2 = 29, + CCGR_IOMUX3 = 30, + CCGR_IOMUX4 = 31, + CCGR_M4 = 32, + CCGR_MU = 33, + CCGR_OCOTP = 34, + CCGR_OCRAM = 35, + CCGR_OCRAM_S = 36, + CCGR_PCIE = 37, + CCGR_PERFMON1 = 38, + CCGR_PERFMON2 = 39, + CCGR_PWM1 = 40, + CCGR_PWM2 = 41, + CCGR_PWM3 = 42, + CCGR_PWM4 = 43, + CCGR_QOS = 44, + CCGR_DISMIX = 45, + CCGR_MEGAMIX = 46, + CCGR_QSPI = 47, + CCGR_RAWNAND = 48, + CCGR_RDC = 49, + CCGR_ROM = 50, + CCGR_SAI1 = 51, + CCGR_SAI2 = 52, + CCGR_SAI3 = 53, + CCGR_SAI4 = 54, + CCGR_SAI5 = 55, + CCGR_SAI6 = 56, + CCGR_SCTR = 57, + CCGR_SDMA1 = 58, + CCGR_SDMA2 = 59, + CCGR_SEC_DEBUG = 60, + CCGR_SEMA1 = 61, + CCGR_SEMA2 = 62, + CCGR_SIM_DISPLAY = 63, + CCGR_SIM_ENET = 64, + CCGR_SIM_M = 65, + CCGR_SIM_MAIN = 66, + CCGR_SIM_S = 67, + CCGR_SIM_WAKEUP = 68, + CCGR_SIM_USB = 69, + CCGR_SIM_VPU = 70, + CCGR_SNVS = 71, + CCGR_TRACE = 72, + CCGR_UART1 = 73, + CCGR_UART2 = 74, + CCGR_UART3 = 75, + CCGR_UART4 = 76, + CCGR_USB_CTRL1 = 77, + CCGR_USB_CTRL2 = 78, + CCGR_USB_PHY1 = 79, + CCGR_USB_PHY2 = 80, + CCGR_USDHC1 = 81, + CCGR_USDHC2 = 82, + CCGR_WDOG1 = 83, + CCGR_WDOG2 = 84, + CCGR_WDOG3 = 85, + CCGR_VA53 = 86, + CCGR_GPU = 87, + CCGR_HEVC = 88, + CCGR_AVC = 89, + CCGR_VP9 = 90, + CCGR_HEVC_INTER = 91, + CCGR_GIC = 92, + CCGR_DISPLAY = 93, + CCGR_HDMI = 94, + CCGR_HDMI_PHY = 95, + CCGR_XTAL = 96, + CCGR_PLL = 97, + CCGR_TSENSOR = 98, + CCGR_VPU_DEC = 99, + CCGR_PCIE2 = 100, + CCGR_MIPI_CSI1 = 101, + CCGR_MIPI_CSI2 = 102, + CCGR_MAX, +}; + +/* src index */ +enum clk_src_index { + CLK_SRC_CKIL_SYNC_REQ = 0, + CLK_SRC_ARM_PLL_EN = 1, + CLK_SRC_GPU_PLL_EN = 2, + CLK_SRC_VPU_PLL_EN = 3, + CLK_SRC_DRAM_PLL_EN = 4, + CLK_SRC_SYSTEM_PLL1_EN = 5, + CLK_SRC_SYSTEM_PLL2_EN = 6, + CLK_SRC_SYSTEM_PLL3_EN = 7, + CLK_SRC_AUDIO_PLL1_EN = 8, + CLK_SRC_AUDIO_PLL2_EN = 9, + CLK_SRC_VIDEO_PLL1_EN = 10, + CLK_SRC_VIDEO_PLL2_EN = 11, + CLK_SRC_ARM_PLL = 12, + CLK_SRC_GPU_PLL = 13, + CLK_SRC_VPU_PLL = 14, + CLK_SRC_DRAM_PLL = 15, + CLK_SRC_SYSTEM_PLL1_800M = 16, + CLK_SRC_SYSTEM_PLL1_400M = 17, + CLK_SRC_SYSTEM_PLL1_266M = 18, + CLK_SRC_SYSTEM_PLL1_200M = 19, + CLK_SRC_SYSTEM_PLL1_160M = 20, + CLK_SRC_SYSTEM_PLL1_133M = 21, + CLK_SRC_SYSTEM_PLL1_100M = 22, + CLK_SRC_SYSTEM_PLL1_80M = 23, + CLK_SRC_SYSTEM_PLL1_40M = 24, + CLK_SRC_SYSTEM_PLL2_1000M = 25, + CLK_SRC_SYSTEM_PLL2_500M = 26, + CLK_SRC_SYSTEM_PLL2_333M = 27, + CLK_SRC_SYSTEM_PLL2_250M = 28, + CLK_SRC_SYSTEM_PLL2_200M = 29, + CLK_SRC_SYSTEM_PLL2_166M = 30, + CLK_SRC_SYSTEM_PLL2_125M = 31, + CLK_SRC_SYSTEM_PLL2_100M = 32, + CLK_SRC_SYSTEM_PLL2_50M = 33, + CLK_SRC_SYSTEM_PLL3 = 34, + CLK_SRC_AUDIO_PLL1 = 35, + CLK_SRC_AUDIO_PLL2 = 36, + CLK_SRC_VIDEO_PLL1 = 37, + CLK_SRC_VIDEO_PLL2 = 38, + CLK_SRC_OSC_25M = 39, + CLK_SRC_OSC_27M = 40, +}; + +/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/ +#define FRAC_PLL_LOCK_MASK BIT(31) +#define FRAC_PLL_CLKE_MASK BIT(21) +#define FRAC_PLL_PD_MASK BIT(19) +#define FRAC_PLL_REFCLK_SEL_MASK (0x3 << 16) +#define FRAC_PLL_LOCK_SEL_MASK BIT(15) +#define FRAC_PLL_BYPASS_MASK BIT(14) +#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13) +#define FRAC_PLL_NEWDIV_VAL_MASK BIT(12) +#define FRAC_PLL_NEWDIV_ACK_MASK BIT(11) +#define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5)) +#define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5) +#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5 +#define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f +#define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f) + +#define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16) +#define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16) +#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16) +#define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16) + +#define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7) +#define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7 +#define FRAC_PLL_INT_DIV_CTL_MASK 0x7f +#define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f) + +/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */ +#define SSCG_PLL_LOCK_MASK BIT(31) +#define SSCG_PLL_CLKE_MASK BIT(25) +#define SSCG_PLL_DIV2_CLKE_MASK BIT(23) +#define SSCG_PLL_DIV3_CLKE_MASK BIT(21) +#define SSCG_PLL_DIV4_CLKE_MASK BIT(19) +#define SSCG_PLL_DIV5_CLKE_MASK BIT(17) +#define SSCG_PLL_DIV6_CLKE_MASK BIT(15) +#define SSCG_PLL_DIV8_CLKE_MASK BIT(13) +#define SSCG_PLL_DIV10_CLKE_MASK BIT(11) +#define SSCG_PLL_DIV20_CLKE_MASK BIT(9) +#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9) +#define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9) +#define SSCG_PLL_PLL3_CLKE_MASK BIT(9) +#define SSCG_PLL_PD_MASK BIT(7) +#define SSCG_PLL_BYPASS1_MASK BIT(5) +#define SSCG_PLL_BYPASS2_MASK BIT(4) +#define SSCG_PLL_LOCK_SEL_MASK BIT(3) +#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2) +#define SSCG_PLL_REFCLK_SEL_MASK 0x3 +#define SSCG_PLL_REFCLK_SEL_OSC_25M (0) +#define SSCG_PLL_REFCLK_SEL_OSC_27M (1) +#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2) +#define SSCG_PLL_REFCLK_SEL_CLK_PN (3) + +#define SSCG_PLL_SSDS_MASK BIT(8) +#define SSCG_PLL_SSMD_MASK (0x7 << 5) +#define SSCG_PLL_SSMF_MASK (0xf << 1) +#define SSCG_PLL_SSE_MASK 0x1 + +#define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) +#define SSCG_PLL_REF_DIVR1_SHIFT 25 +#define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK) +#define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19) +#define SSCG_PLL_REF_DIVR2_SHIFT 19 +#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK) +#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13) +#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13 +#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \ + SSCG_PLL_FEEDBACK_DIV_F1_MASK) +#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7) +#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7 +#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \ + SSCG_PLL_FEEDBACK_DIV_F2_MASK) +#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1) +#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1 +#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \ + SSCG_PLL_OUTPUT_DIV_VAL_MASK) +#define SSCG_PLL_FILTER_RANGE_MASK 0x1 + +#define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16) +#define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8) +#define HW_DIGPROG_MINOR_MASK 0xff + +#define HW_OSC_27M_CLKE_MASK BIT(4) +#define HW_OSC_25M_CLKE_MASK BIT(2) +#define HW_OSC_32K_SEL_MASK 0x1 +#define HW_OSC_32K_SEL_RTC 0x1 +#define HW_OSC_32K_SEL_25M_DIV800 0x0 + +#define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20) +#define HW_FRAC_ARM_PLL_DIV_SHIFT 20 +#define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16) +#define HW_FRAC_VPU_PLL_DIV_SHIFT 16 +#define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12) +#define HW_FRAC_GPU_PLL_DIV_SHIFT 12 +#define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10) +#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10 +#define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4) +#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4 +#define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7 +#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0 + +#define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16) +#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16 +#define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14) +#define HW_SSCG_DRAM_PLL_DIV_SHIFT 14 +#define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8) +#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8 +#define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4) +#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4 +#define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7 +#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0 + +enum frac_pll_out_val { + FRAC_PLL_OUT_1000M, + FRAC_PLL_OUT_800M, +}; + +void init_nand_clk(void); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8m/crm_regs.h b/roms/u-boot/arch/arm/include/asm/arch-imx8m/crm_regs.h new file mode 100644 index 000000000..c42e6685d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8m/crm_regs.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + */ + +#ifndef _ASM_ARCH_IMX8M_CRM_REGS_H +#define _ASM_ARCH_IMX8M_CRM_REGS_H +/* Dummy header, some imx-common code needs this file */ +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8m/ddr.h b/roms/u-boot/arch/arm/include/asm/arch-imx8m/ddr.h new file mode 100644 index 000000000..0f1e832c0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8m/ddr.h @@ -0,0 +1,750 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + */ + +#ifndef __ASM_ARCH_IMX8M_DDR_H +#define __ASM_ARCH_IMX8M_DDR_H + +#include +#include +#include + +#define DDRC_DDR_SS_GPR0 0x3d000000 +#define DDRC_IPS_BASE_ADDR_0 0x3f400000 +#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) +#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000) + +struct ddrc_freq { + u32 res0[8]; + u32 derateen; + u32 derateint; + u32 res1[10]; + u32 rfshctl0; + u32 res2[4]; + u32 rfshtmg; + u32 rfshtmg1; + u32 res3[28]; + u32 init3; + u32 init4; + u32 res; + u32 init6; + u32 init7; + u32 res4[4]; + u32 dramtmg0; + u32 dramtmg1; + u32 dramtmg2; + u32 dramtmg3; + u32 dramtmg4; + u32 dramtmg5; + u32 dramtmg6; + u32 dramtmg7; + u32 dramtmg8; + u32 dramtmg9; + u32 dramtmg10; + u32 dramtmg11; + u32 dramtmg12; + u32 dramtmg13; + u32 dramtmg14; + u32 dramtmg15; + u32 dramtmg16; + u32 dramtmg17; + u32 res5[10]; + u32 mramtmg0; + u32 mramtmg1; + u32 mramtmg4; + u32 mramtmg9; + u32 zqctl0; + u32 res6[3]; + u32 dfitmg0; + u32 dfitmg1; + u32 res7[7]; + u32 dfitmg2; + u32 dfitmg3; + u32 res8[33]; + u32 odtcfg; +}; + +struct imx8m_ddrc_regs { + u32 mstr; + u32 stat; + u32 mstr1; + u32 res1; + u32 mrctrl0; + u32 mrctrl1; + u32 mrstat; + u32 mrctrl2; + u32 derateen; + u32 derateint; + u32 mstr2; + u32 res2; + u32 pwrctl; + u32 pwrtmg; + u32 hwlpctl; + u32 hwffcctl; + u32 hwffcstat; + u32 res3[3]; + u32 rfshctl0; + u32 rfshctl1; + u32 rfshctl2; + u32 rfshctl4; + u32 rfshctl3; + u32 rfshtmg; + u32 rfshtmg1; + u32 res4; + u32 ecccfg0; + u32 ecccfg1; + u32 eccstat; + u32 eccclr; + u32 eccerrcnt; + u32 ecccaddr0; + u32 ecccaddr1; + u32 ecccsyn0; + u32 ecccsyn1; + u32 ecccsyn2; + u32 eccbitmask0; + u32 eccbitmask1; + u32 eccbitmask2; + u32 eccuaddr0; + u32 eccuaddr1; + u32 eccusyn0; + u32 eccusyn1; + u32 eccusyn2; + u32 eccpoisonaddr0; + u32 eccpoisonaddr1; + u32 crcparctl0; + u32 crcparctl1; + u32 crcparctl2; + u32 crcparstat; + u32 init0; + u32 init1; + u32 init2; + u32 init3; + u32 init4; + u32 init5; + u32 init6; + u32 init7; + u32 dimmctl; + u32 rankctl; + u32 res5; + u32 chctl; + u32 dramtmg0; + u32 dramtmg1; + u32 dramtmg2; + u32 dramtmg3; + u32 dramtmg4; + u32 dramtmg5; + u32 dramtmg6; + u32 dramtmg7; + u32 dramtmg8; + u32 dramtmg9; + u32 dramtmg10; + u32 dramtmg11; + u32 dramtmg12; + u32 dramtmg13; + u32 dramtmg14; + u32 dramtmg15; + u32 dramtmg16; + u32 dramtmg17; + u32 res6[10]; + u32 mramtmg0; + u32 mramtmg1; + u32 mramtmg4; + u32 mramtmg9; + u32 zqctl0; + u32 zqctl1; + u32 zqctl2; + u32 zqstat; + u32 dfitmg0; + u32 dfitmg1; + u32 dfilpcfg0; + u32 dfilpcfg1; + u32 dfiupd0; + u32 dfiupd1; + u32 dfiupd2; + u32 res7; + u32 dfimisc; + u32 dfitmg2; + u32 dfitmg3; + u32 dfistat; + u32 dbictl; + u32 dfiphymstr; + u32 res8[14]; + u32 addrmap0; + u32 addrmap1; + u32 addrmap2; + u32 addrmap3; + u32 addrmap4; + u32 addrmap5; + u32 addrmap6; + u32 addrmap7; + u32 addrmap8; + u32 addrmap9; + u32 addrmap10; + u32 addrmap11; + u32 res9[4]; + u32 odtcfg; + u32 odtmap; + u32 res10[2]; + u32 sched; + u32 sched1; + u32 sched2; + u32 perfhpr1; + u32 res11; + u32 perflpr1; + u32 res12; + u32 perfwr1; + u32 res13[4]; + u32 dqmap0; + u32 dqmap1; + u32 dqmap2; + u32 dqmap3; + u32 dqmap4; + u32 dqmap5; + u32 res14[26]; + u32 dbg0; + u32 dbg1; + u32 dbgcam; + u32 dbgcmd; + u32 dbgstat; + u32 res15[3]; + u32 swctl; + u32 swstat; + u32 res16[2]; + u32 ocparcfg0; + u32 ocparcfg1; + u32 ocparcfg2; + u32 ocparcfg3; + u32 ocparstat0; + u32 ocparstat1; + u32 ocparwlog0; + u32 ocparwlog1; + u32 ocparwlog2; + u32 ocparawlog0; + u32 ocparawlog1; + u32 ocparrlog0; + u32 ocparrlog1; + u32 ocpararlog0; + u32 ocpararlog1; + u32 poisoncfg; + u32 poisonstat; + u32 adveccindex; + union { + u32 adveccstat; + u32 eccapstat; + }; + u32 eccpoisonpat0; + u32 eccpoisonpat1; + u32 eccpoisonpat2; + u32 res17[6]; + u32 caparpoisonctl; + u32 caparpoisonstat; + u32 res18[2]; + u32 dynbsmstat; + u32 res19[18]; + u32 pstat; + u32 pccfg; + struct { + u32 pcfgr; + u32 pcfgw; + u32 pcfgc; + struct { + u32 pcfgidmaskch0; + u32 pcfidvaluech0; + } pcfgid[16]; + u32 pctrl; + u32 pcfgqos0; + u32 pcfgqos1; + u32 pcfgwqos0; + u32 pcfgwqos1; + u32 res[4]; + } pcfg[16]; + struct { + u32 sarbase; + u32 sarsize; + } sar[4]; + u32 sbrctl; + u32 sbrstat; + u32 sbrwdata0; + u32 sbrwdata1; + u32 pdch; + u32 res20[755]; + /* umctl2_regs_dch1 */ + u32 ch1_stat; + u32 res21[2]; + u32 ch1_mrctrl0; + u32 ch1_mrctrl1; + u32 ch1_mrstat; + u32 ch1_mrctrl2; + u32 res22[4]; + u32 ch1_pwrctl; + u32 ch1_pwrtmg; + u32 ch1_hwlpctl; + u32 res23[15]; + u32 ch1_eccstat; + u32 ch1_eccclr; + u32 ch1_eccerrcnt; + u32 ch1_ecccaddr0; + u32 ch1_ecccaddr1; + u32 ch1_ecccsyn0; + u32 ch1_ecccsyn1; + u32 ch1_ecccsyn2; + u32 ch1_eccbitmask0; + u32 ch1_eccbitmask1; + u32 ch1_eccbitmask2; + u32 ch1_eccuaddr0; + u32 ch1_eccuaddr1; + u32 ch1_eccusyn0; + u32 ch1_eccusyn1; + u32 ch1_eccusyn2; + u32 res24[2]; + u32 ch1_crcparctl0; + u32 res25[2]; + u32 ch1_crcparstat; + u32 res26[46]; + u32 ch1_zqctl2; + u32 ch1_zqstat; + u32 res27[11]; + u32 ch1_dfistat; + u32 res28[33]; + u32 ch1_odtmap; + u32 res29[47]; + u32 ch1_dbg1; + u32 ch1_dbgcam; + u32 ch1_dbgcmd; + u32 ch1_dbgstat; + u32 res30[123]; + /* umctl2_regs_freq1 */ + struct ddrc_freq freq1; + u32 res31[109]; + /* umctl2_regs_addrmap_alt */ + u32 addrmap0_alt; + u32 addrmap1_alt; + u32 addrmap2_alt; + u32 addrmap3_alt; + u32 addrmap4_alt; + u32 addrmap5_alt; + u32 addrmap6_alt; + u32 addrmap7_alt; + u32 addrmap8_alt; + u32 addrmap9_alt; + u32 addrmap10_alt; + u32 addrmap11_alt; + u32 res32[758]; + /* umctl2_regs_freq2 */ + struct ddrc_freq freq2; + u32 res33[879]; + /* umctl2_regs_freq3 */ + struct ddrc_freq freq3; +}; + +struct imx8m_ddrphy_regs { + u32 reg[0xf0000]; +}; + +/* PHY State */ +enum pstate { + PS0, + PS1, + PS2, + PS3, +}; + +enum msg_response { + TRAIN_SUCCESS = 0x7, + TRAIN_STREAM_START = 0x8, + TRAIN_FAIL = 0xff, +}; + +#define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00) +#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) +#define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08) +#define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10) +#define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14) +#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18) +#define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c) +#define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20) +#define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24) +#define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28) +#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30) +#define DDRC_PWRTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x34) +#define DDRC_HWLPCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x38) +#define DDRC_HWFFCCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3c) +#define DDRC_HWFFCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x40) +#define DDRC_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x50) +#define DDRC_RFSHCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x54) +#define DDRC_RFSHCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x58) +#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60) +#define DDRC_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x64) +#define DDRC_ECCCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x70) +#define DDRC_ECCCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x74) +#define DDRC_ECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x78) +#define DDRC_ECCCLR(X) (DDRC_IPS_BASE_ADDR(X) + 0x7c) +#define DDRC_ECCERRCNT(X) (DDRC_IPS_BASE_ADDR(X) + 0x80) +#define DDRC_ECCCADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0x84) +#define DDRC_ECCCADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x88) +#define DDRC_ECCCSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0x8c) +#define DDRC_ECCCSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0x90) +#define DDRC_ECCCSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0x94) +#define DDRC_ECCBITMASK0(X) (DDRC_IPS_BASE_ADDR(X) + 0x98) +#define DDRC_ECCBITMASK1(X) (DDRC_IPS_BASE_ADDR(X) + 0x9c) +#define DDRC_ECCBITMASK2(X) (DDRC_IPS_BASE_ADDR(X) + 0xa0) +#define DDRC_ECCUADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xa4) +#define DDRC_ECCUADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xa8) +#define DDRC_ECCUSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0xac) +#define DDRC_ECCUSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0xb0) +#define DDRC_ECCUSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0xb4) +#define DDRC_ECCPOISONADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xb8) +#define DDRC_ECCPOISONADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xbc) +#define DDRC_CRCPARCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0xc0) +#define DDRC_CRCPARCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0xc4) +#define DDRC_CRCPARCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0xc8) +#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc) +#define DDRC_INIT0(X) (DDRC_IPS_BASE_ADDR(X) + 0xd0) +#define DDRC_INIT1(X) (DDRC_IPS_BASE_ADDR(X) + 0xd4) +#define DDRC_INIT2(X) (DDRC_IPS_BASE_ADDR(X) + 0xd8) +#define DDRC_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0xdc) +#define DDRC_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0xe0) +#define DDRC_INIT5(X) (DDRC_IPS_BASE_ADDR(X) + 0xe4) +#define DDRC_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0xe8) +#define DDRC_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0xec) +#define DDRC_DIMMCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf0) +#define DDRC_RANKCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf4) +#define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100) +#define DDRC_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x104) +#define DDRC_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x108) +#define DDRC_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x10c) +#define DDRC_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x110) +#define DDRC_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x114) +#define DDRC_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x118) +#define DDRC_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x11c) +#define DDRC_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x120) +#define DDRC_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x124) +#define DDRC_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x128) +#define DDRC_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x12c) +#define DDRC_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x130) +#define DDRC_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x134) +#define DDRC_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x138) +#define DDRC_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x13C) +#define DDRC_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x140) +#define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144) +#define DDRC_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x180) +#define DDRC_ZQCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x184) +#define DDRC_ZQCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x188) +#define DDRC_ZQSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18c) +#define DDRC_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x190) +#define DDRC_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x194) +#define DDRC_DFILPCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x198) +#define DDRC_DFILPCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x19c) +#define DDRC_DFIUPD0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a0) +#define DDRC_DFIUPD1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a4) +#define DDRC_DFIUPD2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a8) +#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0) +#define DDRC_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b4) +#define DDRC_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b8) +#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc) +#define DDRC_DBICTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c0) +#define DDRC_DFIPHYMSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c4) +#define DDRC_TRAINCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d0) +#define DDRC_TRAINCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d4) +#define DDRC_TRAINCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d8) +#define DDRC_TRAINSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1dc) +#define DDRC_ADDRMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x200) +#define DDRC_ADDRMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x204) +#define DDRC_ADDRMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x208) +#define DDRC_ADDRMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20c) +#define DDRC_ADDRMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x210) +#define DDRC_ADDRMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x214) +#define DDRC_ADDRMAP6(X) (DDRC_IPS_BASE_ADDR(X) + 0x218) +#define DDRC_ADDRMAP7(X) (DDRC_IPS_BASE_ADDR(X) + 0x21c) +#define DDRC_ADDRMAP8(X) (DDRC_IPS_BASE_ADDR(X) + 0x220) +#define DDRC_ADDRMAP9(X) (DDRC_IPS_BASE_ADDR(X) + 0x224) +#define DDRC_ADDRMAP10(X) (DDRC_IPS_BASE_ADDR(X) + 0x228) +#define DDRC_ADDRMAP11(X) (DDRC_IPS_BASE_ADDR(X) + 0x22c) +#define DDRC_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x240) +#define DDRC_ODTMAP(X) (DDRC_IPS_BASE_ADDR(X) + 0x244) +#define DDRC_SCHED(X) (DDRC_IPS_BASE_ADDR(X) + 0x250) +#define DDRC_SCHED1(X) (DDRC_IPS_BASE_ADDR(X) + 0x254) +#define DDRC_PERFHPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x25c) +#define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264) +#define DDRC_PERFWR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x26c) +#define DDRC_PERFVPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x274) +#define DDRC_PERFVPW1(X) (DDRC_IPS_BASE_ADDR(X) + 0x278) +#define DDRC_DQMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x280) +#define DDRC_DQMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x284) +#define DDRC_DQMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x288) +#define DDRC_DQMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x28c) +#define DDRC_DQMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x290) +#define DDRC_DQMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x294) +#define DDRC_DBG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x300) +#define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304) +#define DDRC_DBGCAM(X) (DDRC_IPS_BASE_ADDR(X) + 0x308) +#define DDRC_DBGCMD(X) (DDRC_IPS_BASE_ADDR(X) + 0x30c) +#define DDRC_DBGSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x310) +#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320) +#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324) +#define DDRC_OCPARCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x330) +#define DDRC_OCPARCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x334) +#define DDRC_OCPARCFG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x338) +#define DDRC_OCPARCFG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x33c) +#define DDRC_OCPARSTAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x340) +#define DDRC_OCPARSTAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x344) +#define DDRC_OCPARWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x348) +#define DDRC_OCPARWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x34c) +#define DDRC_OCPARWLOG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x350) +#define DDRC_OCPARAWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x354) +#define DDRC_OCPARAWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x358) +#define DDRC_OCPARRLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x35c) +#define DDRC_OCPARRLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x360) +#define DDRC_OCPARARLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x364) +#define DDRC_OCPARARLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x368) +#define DDRC_POISONCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x36C) +#define DDRC_POISONSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x370) + +#define DDRC_PSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3fc) +#define DDRC_PCCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x400) +#define DDRC_PCFGR_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x404) +#define DDRC_PCFGR_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404) +#define DDRC_PCFGR_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404) +#define DDRC_PCFGR_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404) +#define DDRC_PCFGW_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x408) +#define DDRC_PCFGW_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408) +#define DDRC_PCFGW_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408) +#define DDRC_PCFGW_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408) +#define DDRC_PCFGC_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x40c) +#define DDRC_PCFGIDMASKCH(X) (DDRC_IPS_BASE_ADDR(X) + 0x410) +#define DDRC_PCFGIDVALUECH(X) (DDRC_IPS_BASE_ADDR(X) + 0x414) +#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490) +#define DDRC_PCTRL_1(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0) +#define DDRC_PCTRL_2(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0) +#define DDRC_PCTRL_3(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0) +#define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) +#define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498) +#define DDRC_PCFGWQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x49c) +#define DDRC_PCFGWQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4a0) +#define DDRC_SARBASE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf04) +#define DDRC_SARSIZE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf08) +#define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24) +#define DDRC_SBRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xf28) +#define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c) +#define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30) +#define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34) +#define DDRC_SBRSTART0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf38) +#define DDRC_SBRRANGE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf40) + +#define DDRC_FREQ1_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x2020) +#define DDRC_FREQ1_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x2024) +#define DDRC_FREQ1_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2050) +#define DDRC_FREQ1_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2064) +#define DDRC_FREQ1_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20dc) +#define DDRC_FREQ1_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e0) +#define DDRC_FREQ1_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e8) +#define DDRC_FREQ1_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x20ec) +#define DDRC_FREQ1_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2100) +#define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104) +#define DDRC_FREQ1_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x2108) +#define DDRC_FREQ1_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x210c) +#define DDRC_FREQ1_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x2110) +#define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114) +#define DDRC_FREQ1_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x2118) +#define DDRC_FREQ1_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x211c) +#define DDRC_FREQ1_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x2120) +#define DDRC_FREQ1_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x2124) +#define DDRC_FREQ1_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x2128) +#define DDRC_FREQ1_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x212c) +#define DDRC_FREQ1_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x2130) +#define DDRC_FREQ1_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x2134) +#define DDRC_FREQ1_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x2138) +#define DDRC_FREQ1_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x213C) +#define DDRC_FREQ1_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x2140) +#define DDRC_FREQ1_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x2144) +#define DDRC_FREQ1_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2180) +#define DDRC_FREQ1_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190) +#define DDRC_FREQ1_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194) +#define DDRC_FREQ1_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) +#define DDRC_FREQ1_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) +#define DDRC_FREQ1_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) + +#define DDRC_FREQ2_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x3020) +#define DDRC_FREQ2_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3024) +#define DDRC_FREQ2_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3050) +#define DDRC_FREQ2_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3064) +#define DDRC_FREQ2_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x30dc) +#define DDRC_FREQ2_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e0) +#define DDRC_FREQ2_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e8) +#define DDRC_FREQ2_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x30ec) +#define DDRC_FREQ2_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3100) +#define DDRC_FREQ2_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3104) +#define DDRC_FREQ2_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3108) +#define DDRC_FREQ2_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x310c) +#define DDRC_FREQ2_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x3110) +#define DDRC_FREQ2_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x3114) +#define DDRC_FREQ2_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x3118) +#define DDRC_FREQ2_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x311c) +#define DDRC_FREQ2_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x3120) +#define DDRC_FREQ2_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x3124) +#define DDRC_FREQ2_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x3128) +#define DDRC_FREQ2_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x312c) +#define DDRC_FREQ2_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x3130) +#define DDRC_FREQ2_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x3134) +#define DDRC_FREQ2_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x3138) +#define DDRC_FREQ2_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x313C) +#define DDRC_FREQ2_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x3140) +#define DDRC_FREQ2_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x3144) +#define DDRC_FREQ2_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3180) +#define DDRC_FREQ2_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3190) +#define DDRC_FREQ2_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3194) +#define DDRC_FREQ2_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b4) +#define DDRC_FREQ2_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b8) +#define DDRC_FREQ2_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3240) + +#define DDRC_FREQ3_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x4020) +#define DDRC_FREQ3_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x4024) +#define DDRC_FREQ3_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4050) +#define DDRC_FREQ3_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4064) +#define DDRC_FREQ3_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x40dc) +#define DDRC_FREQ3_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e0) +#define DDRC_FREQ3_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e8) +#define DDRC_FREQ3_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x40ec) +#define DDRC_FREQ3_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4100) +#define DDRC_FREQ3_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4104) +#define DDRC_FREQ3_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x4108) +#define DDRC_FREQ3_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x410c) +#define DDRC_FREQ3_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x4110) +#define DDRC_FREQ3_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x4114) +#define DDRC_FREQ3_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x4118) +#define DDRC_FREQ3_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x411c) +#define DDRC_FREQ3_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x4120) +#define DDRC_FREQ3_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x4124) +#define DDRC_FREQ3_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x4128) +#define DDRC_FREQ3_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x412c) +#define DDRC_FREQ3_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x4130) +#define DDRC_FREQ3_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x4134) +#define DDRC_FREQ3_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x4138) +#define DDRC_FREQ3_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x413C) +#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140) + +#define DDRC_FREQ3_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4180) +#define DDRC_FREQ3_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4190) +#define DDRC_FREQ3_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4194) +#define DDRC_FREQ3_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b4) +#define DDRC_FREQ3_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b8) +#define DDRC_FREQ3_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4240) +#define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190) +#define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194) +#define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) +#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) +#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) + +#define DDRPHY_CalBusy(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4 * 0x020097) + +#define DRC_PERF_MON_BASE_ADDR(X) (0x3d800000 + ((X) * 0x2000000)) +#define DRC_PERF_MON_CNT0_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x0) +#define DRC_PERF_MON_CNT1_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4) +#define DRC_PERF_MON_CNT2_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x8) +#define DRC_PERF_MON_CNT3_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0xC) +#define DRC_PERF_MON_CNT0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x20) +#define DRC_PERF_MON_CNT1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x24) +#define DRC_PERF_MON_CNT2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x28) +#define DRC_PERF_MON_CNT3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x2C) +#define DRC_PERF_MON_MRR0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x40) +#define DRC_PERF_MON_MRR1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x44) +#define DRC_PERF_MON_MRR2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x48) +#define DRC_PERF_MON_MRR3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4C) +#define DRC_PERF_MON_MRR4_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x50) +#define DRC_PERF_MON_MRR5_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x54) +#define DRC_PERF_MON_MRR6_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x58) +#define DRC_PERF_MON_MRR7_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x5C) +#define DRC_PERF_MON_MRR8_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x60) +#define DRC_PERF_MON_MRR9_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x64) +#define DRC_PERF_MON_MRR10_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x68) +#define DRC_PERF_MON_MRR11_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x6C) +#define DRC_PERF_MON_MRR12_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x70) +#define DRC_PERF_MON_MRR13_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x74) +#define DRC_PERF_MON_MRR14_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x78) +#define DRC_PERF_MON_MRR15_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x7C) + +/* user data type */ +enum fw_type { + FW_1D_IMAGE, + FW_2D_IMAGE, +}; + +struct dram_cfg_param { + unsigned int reg; + unsigned int val; +}; + +struct dram_fsp_msg { + unsigned int drate; + enum fw_type fw_type; + struct dram_cfg_param *fsp_cfg; + unsigned int fsp_cfg_num; +}; + +struct dram_timing_info { + /* umctl2 config */ + struct dram_cfg_param *ddrc_cfg; + unsigned int ddrc_cfg_num; + /* ddrphy config */ + struct dram_cfg_param *ddrphy_cfg; + unsigned int ddrphy_cfg_num; + /* ddr fsp train info */ + struct dram_fsp_msg *fsp_msg; + unsigned int fsp_msg_num; + /* ddr phy trained CSR */ + struct dram_cfg_param *ddrphy_trained_csr; + unsigned int ddrphy_trained_csr_num; + /* ddr phy PIE */ + struct dram_cfg_param *ddrphy_pie; + unsigned int ddrphy_pie_num; + /* initialized drate table */ + unsigned int fsp_table[4]; +}; + +extern struct dram_timing_info dram_timing; + +void ddr_load_train_firmware(enum fw_type type); +int ddr_init(struct dram_timing_info *timing_info); +int ddr_cfg_phy(struct dram_timing_info *timing_info); +void load_lpddr4_phy_pie(void); +void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num); +void dram_config_save(struct dram_timing_info *info, unsigned long base); +void board_dram_ecc_scrub(void); +void ddrc_inline_ecc_scrub(unsigned int start_address, + unsigned int range_address); +void ddrc_inline_ecc_scrub_end(unsigned int start_address, + unsigned int range_address); + +/* utils function for ddr phy training */ +int wait_ddrphy_training_complete(void); +void ddrphy_init_set_dfi_clk(unsigned int drate); +void ddrphy_init_read_msg_block(enum fw_type type); + +void update_umctl2_rank_space_setting(unsigned int pstat_num); +void get_trained_CDD(unsigned int fsp); + +static inline void reg32_write(unsigned long addr, u32 val) +{ + writel(val, addr); +} + +static inline u32 reg32_read(unsigned long addr) +{ + return readl(addr); +} + +static inline void reg32setbit(unsigned long addr, u32 bit) +{ + setbits_le32(addr, (1 << bit)); +} + +#define dwc_ddrphy_apb_wr(addr, data) \ + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data) +#define dwc_ddrphy_apb_rd(addr) \ + reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr)) + +extern struct dram_cfg_param ddrphy_trained_csr[]; +extern uint32_t ddrphy_trained_csr_num; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8m/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-imx8m/gpio.h new file mode 100644 index 000000000..2d9fbcb0e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8m/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + */ + +#ifndef __ASM_ARCH_IMX8M_GPIO_H +#define __ASM_ARCH_IMX8M_GPIO_H + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8m/imx-regs.h b/roms/u-boot/arch/arm/include/asm/arch-imx8m/imx-regs.h new file mode 100644 index 000000000..b800da13a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -0,0 +1,517 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + */ + +#ifndef __ASM_ARCH_IMX8M_REGS_H__ +#define __ASM_ARCH_IMX8M_REGS_H__ + +#define ARCH_MXC + +#include + +#define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800 +#define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800 + +#define M4_BOOTROM_BASE_ADDR 0x007E0000 + +#define GPIO1_BASE_ADDR 0X30200000 +#define GPIO2_BASE_ADDR 0x30210000 +#define GPIO3_BASE_ADDR 0x30220000 +#define GPIO4_BASE_ADDR 0x30230000 +#define GPIO5_BASE_ADDR 0x30240000 +#define WDOG1_BASE_ADDR 0x30280000 +#define WDOG2_BASE_ADDR 0x30290000 +#define WDOG3_BASE_ADDR 0x302A0000 +#define IOMUXC_BASE_ADDR 0x30330000 +#define IOMUXC_GPR_BASE_ADDR 0x30340000 +#define OCOTP_BASE_ADDR 0x30350000 +#define ANATOP_BASE_ADDR 0x30360000 +#define CCM_BASE_ADDR 0x30380000 +#define SRC_BASE_ADDR 0x30390000 +#define GPC_BASE_ADDR 0x303A0000 + +#define SYSCNT_RD_BASE_ADDR 0x306A0000 +#define SYSCNT_CMP_BASE_ADDR 0x306B0000 +#define SYSCNT_CTRL_BASE_ADDR 0x306C0000 + +#define UART1_BASE_ADDR 0x30860000 +#define UART3_BASE_ADDR 0x30880000 +#define UART2_BASE_ADDR 0x30890000 +#define I2C1_BASE_ADDR 0x30A20000 +#define I2C2_BASE_ADDR 0x30A30000 +#define I2C3_BASE_ADDR 0x30A40000 +#define I2C4_BASE_ADDR 0x30A50000 +#define UART4_BASE_ADDR 0x30A60000 +#define USDHC1_BASE_ADDR 0x30B40000 +#define USDHC2_BASE_ADDR 0x30B50000 +#ifdef CONFIG_IMX8MM +#define USDHC3_BASE_ADDR 0x30B60000 +#endif + +#define TZASC_BASE_ADDR 0x32F80000 + +#define MXS_LCDIF_BASE IS_ENABLED(CONFIG_IMX8MQ) ? \ + 0x30320000 : 0x32e00000 + +#define SRC_IPS_BASE_ADDR 0x30390000 +#define SRC_DDRC_RCR_ADDR 0x30391000 +#define SRC_DDRC2_RCR_ADDR 0x30391004 + +#define DDRC_DDR_SS_GPR0 0x3d000000 +#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) +#define DDR_CSD1_BASE_ADDR 0x40000000 + +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000 +#define FEC_QUIRK_ENET_MAC + +#define CAAM_ARB_BASE_ADDR (0x00100000) +#define CAAM_ARB_END_ADDR (0x00107FFF) +#define CAAM_IPS_BASE_ADDR (0x30900000) +#define CONFIG_SYS_FSL_SEC_OFFSET (0) +#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000) +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ + CONFIG_SYS_FSL_JR0_OFFSET) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 +#if !defined(__ASSEMBLY__) +#include +#include +#include + +#define GPR_TZASC_EN BIT(0) +#define GPR_TZASC_EN_LOCK BIT(16) + +#define SRC_SCR_M4_ENABLE_OFFSET 3 +#define SRC_SCR_M4_ENABLE_MASK BIT(3) +#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0 +#define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0) +#define SRC_DDR1_ENABLE_MASK 0x8F000000UL +#define SRC_DDR2_ENABLE_MASK 0x8F000000UL +#define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3) +#define SRC_DDR1_RCR_PHY_RESET_MASK BIT(2) +#define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1) +#define SRC_DDR1_RCR_PRESET_N_MASK BIT(0) + +struct iomuxc_gpr_base_regs { + u32 gpr[47]; +}; + +struct ocotp_regs { + u32 ctrl; + u32 ctrl_set; + u32 ctrl_clr; + u32 ctrl_tog; + u32 timing; + u32 rsvd0[3]; + u32 data; + u32 rsvd1[3]; + u32 read_ctrl; + u32 rsvd2[3]; + u32 read_fuse_data; + u32 rsvd3[3]; + u32 sw_sticky; + u32 rsvd4[3]; + u32 scs; + u32 scs_set; + u32 scs_clr; + u32 scs_tog; + u32 crc_addr; + u32 rsvd5[3]; + u32 crc_value; + u32 rsvd6[3]; + u32 version; + u32 rsvd7[0xdb]; + + /* fuse banks */ + struct fuse_bank { + u32 fuse_regs[0x10]; + } bank[0]; +}; + +#ifdef CONFIG_IMX8MP +struct fuse_bank0_regs { + u32 lock; + u32 rsvd0[7]; + u32 uid_low; + u32 rsvd1[3]; + u32 uid_high; + u32 rsvd2[3]; +}; +#else +struct fuse_bank0_regs { + u32 lock; + u32 rsvd0[3]; + u32 uid_low; + u32 rsvd1[3]; + u32 uid_high; + u32 rsvd2[7]; +}; +#endif + +struct fuse_bank1_regs { + u32 tester3; + u32 rsvd0[3]; + u32 tester4; + u32 rsvd1[3]; + u32 tester5; + u32 rsvd2[3]; + u32 cfg0; + u32 rsvd3[3]; +}; + +struct fuse_bank3_regs { + u32 mem_trim0; + u32 rsvd0[3]; + u32 mem_trim1; + u32 rsvd1[3]; + u32 mem_trim2; + u32 rsvd2[3]; + u32 ana0; + u32 rsvd3[3]; +}; + +struct fuse_bank9_regs { + u32 mac_addr0; + u32 rsvd0[3]; + u32 mac_addr1; + u32 rsvd1[11]; +}; + +struct fuse_bank38_regs { + u32 ana_trim1; /* trim0 is at 0xD70, bank 37*/ + u32 rsvd0[3]; + u32 ana_trim2; + u32 rsvd1[3]; + u32 ana_trim3; + u32 rsvd2[3]; + u32 ana_trim4; + u32 rsvd3[3]; +}; + +struct fuse_bank39_regs { + u32 ana_trim5; + u32 rsvd[15]; +}; + +#ifdef CONFIG_IMX8MQ +struct anamix_pll { + u32 audio_pll1_cfg0; + u32 audio_pll1_cfg1; + u32 audio_pll2_cfg0; + u32 audio_pll2_cfg1; + u32 video_pll_cfg0; + u32 video_pll_cfg1; + u32 gpu_pll_cfg0; + u32 gpu_pll_cfg1; + u32 vpu_pll_cfg0; + u32 vpu_pll_cfg1; + u32 arm_pll_cfg0; + u32 arm_pll_cfg1; + u32 sys_pll1_cfg0; + u32 sys_pll1_cfg1; + u32 sys_pll1_cfg2; + u32 sys_pll2_cfg0; + u32 sys_pll2_cfg1; + u32 sys_pll2_cfg2; + u32 sys_pll3_cfg0; + u32 sys_pll3_cfg1; + u32 sys_pll3_cfg2; + u32 video_pll2_cfg0; + u32 video_pll2_cfg1; + u32 video_pll2_cfg2; + u32 dram_pll_cfg0; + u32 dram_pll_cfg1; + u32 dram_pll_cfg2; + u32 digprog; + u32 osc_misc_cfg; + u32 pllout_monitor_cfg; + u32 frac_pllout_div_cfg; + u32 sscg_pllout_div_cfg; +}; +#else +struct anamix_pll { + u32 audio_pll1_gnrl_ctl; + u32 audio_pll1_fdiv_ctl0; + u32 audio_pll1_fdiv_ctl1; + u32 audio_pll1_sscg_ctl; + u32 audio_pll1_mnit_ctl; + u32 audio_pll2_gnrl_ctl; + u32 audio_pll2_fdiv_ctl0; + u32 audio_pll2_fdiv_ctl1; + u32 audio_pll2_sscg_ctl; + u32 audio_pll2_mnit_ctl; + u32 video_pll1_gnrl_ctl; + u32 video_pll1_fdiv_ctl0; + u32 video_pll1_fdiv_ctl1; + u32 video_pll1_sscg_ctl; + u32 video_pll1_mnit_ctl; + u32 reserved[5]; + u32 dram_pll_gnrl_ctl; + u32 dram_pll_fdiv_ctl0; + u32 dram_pll_fdiv_ctl1; + u32 dram_pll_sscg_ctl; + u32 dram_pll_mnit_ctl; + u32 gpu_pll_gnrl_ctl; + u32 gpu_pll_div_ctl; + u32 gpu_pll_locked_ctl1; + u32 gpu_pll_mnit_ctl; + u32 vpu_pll_gnrl_ctl; + u32 vpu_pll_div_ctl; + u32 vpu_pll_locked_ctl1; + u32 vpu_pll_mnit_ctl; + u32 arm_pll_gnrl_ctl; + u32 arm_pll_div_ctl; + u32 arm_pll_locked_ctl1; + u32 arm_pll_mnit_ctl; + u32 sys_pll1_gnrl_ctl; + u32 sys_pll1_div_ctl; + u32 sys_pll1_locked_ctl1; + u32 reserved2[24]; + u32 sys_pll1_mnit_ctl; + u32 sys_pll2_gnrl_ctl; + u32 sys_pll2_div_ctl; + u32 sys_pll2_locked_ctl1; + u32 sys_pll2_mnit_ctl; + u32 sys_pll3_gnrl_ctl; + u32 sys_pll3_div_ctl; + u32 sys_pll3_locked_ctl1; + u32 sys_pll3_mnit_ctl; + u32 anamix_misc_ctl; + u32 anamix_clk_mnit_ctl; + u32 reserved3[437]; + u32 digprog; +}; +#endif + +/* System Reset Controller (SRC) */ +struct src { + u32 scr; + u32 a53rcr; + u32 a53rcr1; + u32 m4rcr; + u32 reserved1[4]; + u32 usbophy1_rcr; + u32 usbophy2_rcr; + u32 mipiphy_rcr; + u32 pciephy_rcr; + u32 hdmi_rcr; + u32 disp_rcr; + u32 reserved2[2]; + u32 gpu_rcr; + u32 vpu_rcr; + u32 pcie2_rcr; + u32 mipiphy1_rcr; + u32 mipiphy2_rcr; + u32 reserved3; + u32 sbmr1; + u32 srsr; + u32 reserved4[2]; + u32 sisr; + u32 simr; + u32 sbmr2; + u32 gpr1; + u32 gpr2; + u32 gpr3; + u32 gpr4; + u32 gpr5; + u32 gpr6; + u32 gpr7; + u32 gpr8; + u32 gpr9; + u32 gpr10; + u32 reserved5[985]; + u32 ddr1_rcr; + u32 ddr2_rcr; +}; + +#define WDOG_WDT_MASK BIT(3) +#define WDOG_WDZST_MASK BIT(0) +struct wdog_regs { + u16 wcr; /* Control */ + u16 wsr; /* Service */ + u16 wrsr; /* Reset Status */ + u16 wicr; /* Interrupt Control */ + u16 wmcr; /* Miscellaneous Control */ +}; + +struct bootrom_sw_info { + u8 reserved_1; + u8 boot_dev_instance; + u8 boot_dev_type; + u8 reserved_2; + u32 core_freq; + u32 axi_freq; + u32 ddr_freq; + u32 tick_freq; + u32 reserved_3[3]; +}; + +#define ROM_SW_INFO_ADDR_B0 (IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\ + 0x000009e8) +#define ROM_SW_INFO_ADDR_A0 0x000009e8 + +#define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \ + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \ + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0 + +struct gpc_reg { + u32 lpcr_bsc; + u32 lpcr_ad; + u32 lpcr_cpu1; + u32 lpcr_cpu2; + u32 lpcr_cpu3; + u32 slpcr; + u32 mst_cpu_mapping; + u32 mmdc_cpu_mapping; + u32 mlpcr; + u32 pgc_ack_sel; + u32 pgc_ack_sel_m4; + u32 gpc_misc; + u32 imr1_core0; + u32 imr2_core0; + u32 imr3_core0; + u32 imr4_core0; + u32 imr1_core1; + u32 imr2_core1; + u32 imr3_core1; + u32 imr4_core1; + u32 imr1_cpu1; + u32 imr2_cpu1; + u32 imr3_cpu1; + u32 imr4_cpu1; + u32 imr1_cpu3; + u32 imr2_cpu3; + u32 imr3_cpu3; + u32 imr4_cpu3; + u32 isr1_cpu0; + u32 isr2_cpu0; + u32 isr3_cpu0; + u32 isr4_cpu0; + u32 isr1_cpu1; + u32 isr2_cpu1; + u32 isr3_cpu1; + u32 isr4_cpu1; + u32 isr1_cpu2; + u32 isr2_cpu2; + u32 isr3_cpu2; + u32 isr4_cpu2; + u32 isr1_cpu3; + u32 isr2_cpu3; + u32 isr3_cpu3; + u32 isr4_cpu3; + u32 slt0_cfg; + u32 slt1_cfg; + u32 slt2_cfg; + u32 slt3_cfg; + u32 slt4_cfg; + u32 slt5_cfg; + u32 slt6_cfg; + u32 slt7_cfg; + u32 slt8_cfg; + u32 slt9_cfg; + u32 slt10_cfg; + u32 slt11_cfg; + u32 slt12_cfg; + u32 slt13_cfg; + u32 slt14_cfg; + u32 pgc_cpu_0_1_mapping; + u32 cpu_pgc_up_trg; + u32 mix_pgc_up_trg; + u32 pu_pgc_up_trg; + u32 cpu_pgc_dn_trg; + u32 mix_pgc_dn_trg; + u32 pu_pgc_dn_trg; + u32 lpcr_bsc2; + u32 pgc_cpu_2_3_mapping; + u32 lps_cpu0; + u32 lps_cpu1; + u32 lps_cpu2; + u32 lps_cpu3; + u32 gpc_gpr; + u32 gtor; + u32 debug_addr1; + u32 debug_addr2; + u32 cpu_pgc_up_status1; + u32 mix_pgc_up_status0; + u32 mix_pgc_up_status1; + u32 mix_pgc_up_status2; + u32 m4_mix_pgc_up_status0; + u32 m4_mix_pgc_up_status1; + u32 m4_mix_pgc_up_status2; + u32 pu_pgc_up_status0; + u32 pu_pgc_up_status1; + u32 pu_pgc_up_status2; + u32 m4_pu_pgc_up_status0; + u32 m4_pu_pgc_up_status1; + u32 m4_pu_pgc_up_status2; + u32 a53_lp_io_0; + u32 a53_lp_io_1; + u32 a53_lp_io_2; + u32 cpu_pgc_dn_status1; + u32 mix_pgc_dn_status0; + u32 mix_pgc_dn_status1; + u32 mix_pgc_dn_status2; + u32 m4_mix_pgc_dn_status0; + u32 m4_mix_pgc_dn_status1; + u32 m4_mix_pgc_dn_status2; + u32 pu_pgc_dn_status0; + u32 pu_pgc_dn_status1; + u32 pu_pgc_dn_status2; + u32 m4_pu_pgc_dn_status0; + u32 m4_pu_pgc_dn_status1; + u32 m4_pu_pgc_dn_status2; + u32 res[3]; + u32 mix_pdn_flg; + u32 pu_pdn_flg; + u32 m4_mix_pdn_flg; + u32 m4_pu_pdn_flg; + u32 imr1_core2; + u32 imr2_core2; + u32 imr3_core2; + u32 imr4_core2; + u32 imr1_core3; + u32 imr2_core3; + u32 imr3_core3; + u32 imr4_core3; + u32 pgc_ack_sel_pu; + u32 pgc_ack_sel_m4_pu; + u32 slt15_cfg; + u32 slt16_cfg; + u32 slt17_cfg; + u32 slt18_cfg; + u32 slt19_cfg; + u32 gpc_pu_pwrhsk; + u32 slt0_cfg_pu; + u32 slt1_cfg_pu; + u32 slt2_cfg_pu; + u32 slt3_cfg_pu; + u32 slt4_cfg_pu; + u32 slt5_cfg_pu; + u32 slt6_cfg_pu; + u32 slt7_cfg_pu; + u32 slt8_cfg_pu; + u32 slt9_cfg_pu; + u32 slt10_cfg_pu; + u32 slt11_cfg_pu; + u32 slt12_cfg_pu; + u32 slt13_cfg_pu; + u32 slt14_cfg_pu; + u32 slt15_cfg_pu; + u32 slt16_cfg_pu; + u32 slt17_cfg_pu; + u32 slt18_cfg_pu; + u32 slt19_cfg_pu; +}; + +struct pgc_reg { + u32 pgcr; + u32 pgpupscr; + u32 pgpdnscr; + u32 pgsr; + u32 pgauxsw; + u32 pgdr; +}; +#endif +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h b/roms/u-boot/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h new file mode 100644 index 000000000..210e96e1d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h @@ -0,0 +1,691 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018-2019 NXP + */ + +#ifndef __ASM_ARCH_IMX8MM_PINS_H__ +#define __ASM_ARCH_IMX8MM_PINS_H__ + +#include + +enum { + IMX8MM_PAD_GPIO1_IO00_GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO00_XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO00_CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO01_PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO01_XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO01_CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO02_GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO03_GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO03_USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO03_SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO04_GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO04_USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO04_SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO05_GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO05_ARM_PLATFORM_M4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO05_CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0), + IMX8MM_PAD_GPIO1_IO05_SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO06_GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO06_ENET1_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO06_USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO06_CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO07_ENET1_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0), + IMX8MM_PAD_GPIO1_IO07_USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO07_CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO08_ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO08_USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO08_CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_USDHC3_RESET_B = IOMUX_PAD(0x02B4, 0x004C, 4, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO10_USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO11_GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO11_USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO11_USDHC3_VSELECT = IOMUX_PAD(0x02BC, 0x0054, 4, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO11_CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0), + IMX8MM_PAD_GPIO1_IO11_CCM_OUT0 = IOMUX_PAD(0x02BC, 0x0054, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO12_GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO12_USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO12_SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO12_CCM_OUT1 = IOMUX_PAD(0x02C0, 0x0058, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO13_GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO13_USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO13_PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO13_CCM_OUT2 = IOMUX_PAD(0x02C4, 0x005C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO14_GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO14_USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO14_USDHC3_CD_B = IOMUX_PAD(0x02C8, 0x0060, 4, 0x0544, 2, 0), + IMX8MM_PAD_GPIO1_IO14_PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO14_CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO15_GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO15_USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO15_USDHC3_WP = IOMUX_PAD(0x02CC, 0x0064, 4, 0x0548, 2, 0), + IMX8MM_PAD_GPIO1_IO15_PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO15_CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_MDC_ENET1_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_MDC_GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_MDIO_ENET1_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0), + IMX8MM_PAD_ENET_MDIO_GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD3_ENET1_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD3_GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD2_ENET1_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD2_ENET1_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD2_CCM_ENET_REF_CLK_ROOT = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD2_GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD1_ENET1_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD1_GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD0_ENET1_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD0_GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TX_CTL_ENET1_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TX_CTL_GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TXC_ENET1_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TXC_ENET1_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TXC_GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RX_CTL_ENET1_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RX_CTL_GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RXC_ENET1_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RXC_ENET1_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RXC_GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD0_ENET1_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD0_GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD1_ENET1_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD1_GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD2_ENET1_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD2_GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD3_ENET1_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD3_GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_CLK_USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_CLK_GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_CMD_USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_CMD_GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA0_GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA1_GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA2_GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA3_GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA4_GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA5_GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA6_GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA7_GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_RESET_B_USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_STROBE_GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_CD_B_USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_CLK_USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CLK_GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CLK_CCM_OBSERVE0 = IOMUX_PAD(0x033C, 0x00D4, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_CMD_USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CMD_GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CMD_CCM_OBSERVE1 = IOMUX_PAD(0x0340, 0x00D8, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA0_GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA0_CCM_OBSERVE2 = IOMUX_PAD(0x0344, 0x00DC, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA1_GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA1_CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA2_GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA2_CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA3_SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_RESET_B_USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_RESET_B_SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_WP_USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_WP_GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_ALE_RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_ALE_GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE0_B_GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE1_B_RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE1_B_QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE1_B_USDHC3_STROBE = IOMUX_PAD(0x0364, 0x00FC, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE1_B_GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE2_B_RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE2_B_QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 = IOMUX_PAD(0x0368, 0x0100, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE2_B_GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE3_B_RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE3_B_QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 = IOMUX_PAD(0x036C, 0x0104, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE3_B_GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CLE_RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CLE_QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 = IOMUX_PAD(0x0370, 0x0108, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CLE_GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA00_GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA02_USDHC3_CD_B = IOMUX_PAD(0x037C, 0x0114, 2, 0x0544, 0, 0), + IMX8MM_PAD_NAND_DATA02_GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA03_USDHC3_WP = IOMUX_PAD(0x0380, 0x0118, 2, 0x0548, 0, 0), + IMX8MM_PAD_NAND_DATA03_GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA04_QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 = IOMUX_PAD(0x0384, 0x011C, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA04_GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA05_QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 = IOMUX_PAD(0x0388, 0x0120, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA05_GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA06_QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 = IOMUX_PAD(0x038C, 0x0124, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA06_GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA07_QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 = IOMUX_PAD(0x0390, 0x0128, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA07_GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DQS_RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DQS_QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DQS_GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_RE_B_QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 = IOMUX_PAD(0x0398, 0x0130, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_RE_B_GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_READY_B_USDHC3_RESET_B = IOMUX_PAD(0x039C, 0x0134, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_READY_B_GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK = IOMUX_PAD(0x03A0, 0x0138, 2 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WE_B_GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD = IOMUX_PAD(0x03A4, 0x013C, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WP_B_GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0), + IMX8MM_PAD_SAI5_RXFS_SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXFS_GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0), + IMX8MM_PAD_SAI5_RXC_SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXC_PDM_CLK = IOMUX_PAD(0x03AC, 0x0144, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXC_GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0), + IMX8MM_PAD_SAI5_RXD0_SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03B0, 0x0148, 4, 0x0534, 0, 0), + IMX8MM_PAD_SAI5_RXD0_GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0), + IMX8MM_PAD_SAI5_RXD1_SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD1_SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0), + IMX8MM_PAD_SAI5_RXD1_SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0), + IMX8MM_PAD_SAI5_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03B4, 0x014C, 4, 0x0538, 0, 0), + IMX8MM_PAD_SAI5_RXD1_GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0), + IMX8MM_PAD_SAI5_RXD2_SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD2_SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0), + IMX8MM_PAD_SAI5_RXD2_SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0), + IMX8MM_PAD_SAI5_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03B8, 0x0150, 4, 0x053C, 0, 0), + IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0), + IMX8MM_PAD_SAI5_RXD3_SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD3_SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0), + IMX8MM_PAD_SAI5_RXD3_SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03BC, 0x0154, 4, 0x0540, 0, 0), + IMX8MM_PAD_SAI5_RXD3_GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_MCLK_SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0), + IMX8MM_PAD_SAI5_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0), + IMX8MM_PAD_SAI5_MCLK_GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_MCLK_SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXFS_SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0), + IMX8MM_PAD_SAI1_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0), + IMX8MM_PAD_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXFS_GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXC_SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0), + IMX8MM_PAD_SAI1_RXC_ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXC_GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD0_SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0), + IMX8MM_PAD_SAI1_RXD0_SAI1_TX_DATA1 = IOMUX_PAD(0x03CC, 0x0164, 2, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03CC, 0x0164, 3, 0x0534, 1, 0), + IMX8MM_PAD_SAI1_RXD0_ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD1_SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0), + IMX8MM_PAD_SAI1_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03D0, 0x0168, 3, 0x0538, 1, 0), + IMX8MM_PAD_SAI1_RXD1_ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD1_GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD1_SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD2_SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0), + IMX8MM_PAD_SAI1_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03D4, 0x016C, 3, 0x053C, 1, 0), + IMX8MM_PAD_SAI1_RXD2_ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD2_GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD2_SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD3_SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x04E0, 1, 0), + IMX8MM_PAD_SAI1_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03D8, 0x0170, 3, 0x0540, 1, 0), + IMX8MM_PAD_SAI1_RXD3_ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD3_GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD3_SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD4_SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD4_SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0), + IMX8MM_PAD_SAI1_RXD4_SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0), + IMX8MM_PAD_SAI1_RXD4_ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD4_GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD4_SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD5_SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0), + IMX8MM_PAD_SAI1_RXD5_ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD6_SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD6_SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0), + IMX8MM_PAD_SAI1_RXD6_SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0), + IMX8MM_PAD_SAI1_RXD6_ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD6_GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD6_SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD7_SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0), + IMX8MM_PAD_SAI1_RXD7_SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0), + IMX8MM_PAD_SAI1_RXD7_SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXFS_SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0), + IMX8MM_PAD_SAI1_TXFS_SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0), + IMX8MM_PAD_SAI1_TXFS_ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXFS_GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXC_SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0), + IMX8MM_PAD_SAI1_TXC_SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0), + IMX8MM_PAD_SAI1_TXC_ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXC_GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD0_SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD1_SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD2_SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD3_SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD4_SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD4_SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0), + IMX8MM_PAD_SAI1_TXD4_SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0), + IMX8MM_PAD_SAI1_TXD4_ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD4_GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD4_SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD5_SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0), + IMX8MM_PAD_SAI1_TXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD6_SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD6_SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0), + IMX8MM_PAD_SAI1_TXD6_SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0), + IMX8MM_PAD_SAI1_TXD6_ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD6_GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD6_SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD7_SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0), + IMX8MM_PAD_SAI1_TXD7_PDM_CLK = IOMUX_PAD(0x0410, 0x01A8, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_MCLK_SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_MCLK_SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0), + IMX8MM_PAD_SAI1_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0), + IMX8MM_PAD_SAI1_MCLK_PDM_CLK = IOMUX_PAD(0x0414, 0x01AC, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_MCLK_GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_RXFS_SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0), + IMX8MM_PAD_SAI2_RXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 2, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_SAI2_RX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_UART1_TX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_UART1_RX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x04F4, 2, 0), + IMX8MM_PAD_SAI2_RXFS_GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_RXC_SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXC_SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0), + IMX8MM_PAD_SAI2_RXC_UART1_RX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x04F4, 3, 0), + IMX8MM_PAD_SAI2_RXC_UART1_TX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_RXD0_SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXD0_UART1_RTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x04F0, 2, 0), + IMX8MM_PAD_SAI2_RXD0_UART1_CTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXD0_GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_TXFS_SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_SAI2_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_UART1_CTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_UART1_RTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x04F0, 3, 0), + IMX8MM_PAD_SAI2_TXFS_GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_TXC_SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXC_SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXC_GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_TXD0_SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXD0_SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXD0_GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_MCLK_SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_MCLK_SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0), + IMX8MM_PAD_SAI2_MCLK_GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_RXFS_SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXFS_GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0), + IMX8MM_PAD_SAI3_RXFS_SAI3_RX_DATA1 = IOMUX_PAD(0x0434, 0x01CC, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXFS_GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_RXC_SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXC_GPT1_CLK = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0), + IMX8MM_PAD_SAI3_RXC_UART2_CTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXC_UART2_RTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x04F8, 2, 0), + IMX8MM_PAD_SAI3_RXC_GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_RXD_SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXD_GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXD_SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0), + IMX8MM_PAD_SAI3_RXD_UART2_RTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x04F8, 3, 0), + IMX8MM_PAD_SAI3_RXD_UART2_CTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXD_GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_TXFS_SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_GPT1_CAPTURE2 = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0), + IMX8MM_PAD_SAI3_TXFS_SAI3_TX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_UART2_RX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x04FC, 2, 0), + IMX8MM_PAD_SAI3_TXFS_UART2_TX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_TXC_SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXC_GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXC_SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0), + IMX8MM_PAD_SAI3_TXC_UART2_TX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXC_UART2_RX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x04FC, 3, 0), + IMX8MM_PAD_SAI3_TXC_GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_TXD_SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXD_GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXD_SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0), + IMX8MM_PAD_SAI3_TXD_GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_MCLK_SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_MCLK_PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_MCLK_SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0), + IMX8MM_PAD_SAI3_MCLK_GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SPDIF_TX_SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_TX_PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_TX_GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SPDIF_RX_SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_RX_PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_RX_GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_EXT_CLK_PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_EXT_CLK_GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SCLK_UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0), + IMX8MM_PAD_ECSPI1_SCLK_UART3_TX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SCLK_GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MOSI_UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MOSI_UART3_RX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0), + IMX8MM_PAD_ECSPI1_MOSI_GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MISO_UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MISO_UART3_RTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0), + IMX8MM_PAD_ECSPI1_MISO_GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_SS0_ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SS0_UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0), + IMX8MM_PAD_ECSPI1_SS0_UART3_CTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SCLK_UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0), + IMX8MM_PAD_ECSPI2_SCLK_UART4_TX = IOMUX_PAD(0x046C, 0x0204, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SCLK_GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MOSI_UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MOSI_UART4_RX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0), + IMX8MM_PAD_ECSPI2_MOSI_GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MISO_UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MISO_UART4_RTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0), + IMX8MM_PAD_ECSPI2_MISO_GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_SS0_ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SS0_UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0), + IMX8MM_PAD_ECSPI2_SS0_UART4_CTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C1_SCL_I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + IMX8MM_PAD_I2C1_SCL_ENET1_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C1_SDA_I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + IMX8MM_PAD_I2C1_SDA_ENET1_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0), + IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C2_SCL_I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SCL_ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SCL_USDHC3_CD_B = IOMUX_PAD(0x0484, 0x021C, 2, 0x0544, 1, 0), + IMX8MM_PAD_I2C2_SCL_GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C2_SDA_I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SDA_ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SDA_USDHC3_WP = IOMUX_PAD(0x0488, 0x0220, 2, 0x0548, 1, 0), + IMX8MM_PAD_I2C2_SDA_GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C3_SCL_I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SCL_PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SCL_GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SCL_GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C3_SDA_I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SDA_PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SDA_GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SDA_GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C4_SCL_I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SCL_PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SCL_PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0), + IMX8MM_PAD_I2C4_SCL_GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C4_SDA_I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SDA_PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SDA_GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART1_RXD_UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0), + IMX8MM_PAD_UART1_RXD_UART1_TX = IOMUX_PAD(0x049C, 0x0234, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART1_RXD_ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART1_RXD_GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART1_TXD_UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART1_TXD_UART1_RX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x04F4, 1, 0), + IMX8MM_PAD_UART1_TXD_ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART1_TXD_GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART2_RXD_UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0), + IMX8MM_PAD_UART2_RXD_UART2_TX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART2_RXD_ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART2_RXD_GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART2_TXD_UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART2_TXD_UART2_RX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x04FC, 1, 0), + IMX8MM_PAD_UART2_TXD_ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART2_TXD_GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART3_RXD_UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0), + IMX8MM_PAD_UART3_RXD_UART3_TX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART3_RXD_UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART3_RXD_UART1_RTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0), + IMX8MM_PAD_UART3_RXD_USDHC3_RESET_B = IOMUX_PAD(0x04AC, 0x0244, 2, 0x0000, 0, 0), + IMX8MM_PAD_UART3_RXD_GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART3_TXD_UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART3_TXD_UART3_RX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0504, 3, 0), + IMX8MM_PAD_UART3_TXD_UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0), + IMX8MM_PAD_UART3_TXD_UART1_CTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART3_TXD_USDHC3_VSELECT = IOMUX_PAD(0x04B0, 0x0248, 2, 0x0000, 0, 0), + IMX8MM_PAD_UART3_TXD_GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART4_RXD_UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0), + IMX8MM_PAD_UART4_RXD_UART4_TX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART4_RXD_UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART4_RXD_UART2_RTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0), + IMX8MM_PAD_UART4_RXD_PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0), + IMX8MM_PAD_UART4_RXD_GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART4_TXD_UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART4_TXD_UART4_RX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x050C, 3, 0), + IMX8MM_PAD_UART4_TXD_UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0), + IMX8MM_PAD_UART4_TXD_UART2_CTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART4_TXD_GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0), +}; +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8m/imx8mn_pins.h b/roms/u-boot/arch/arm/include/asm/arch-imx8m/imx8mn_pins.h new file mode 100644 index 000000000..b4298f2b8 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8m/imx8mn_pins.h @@ -0,0 +1,763 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __ASM_ARCH_IMX8MN_PINS_H__ +#define __ASM_ARCH_IMX8MN_PINS_H__ + +#include + +enum { + IMX8MN_PAD_BOOT_MODE2__CCMSRCGPCMIX_BOOT_MODE2 = IOMUX_PAD(0x025C, 0x0020, 0, 0x0000, 0, 0), + IMX8MN_PAD_BOOT_MODE2__I2C1_SCL = IOMUX_PAD(0x025C, 0x0020, 1, 0x055C, 3, 0), + + IMX8MN_PAD_BOOT_MODE3__CCMSRCGPCMIX_BOOT_MODE3 = IOMUX_PAD(0x0260, 0x0024, 0, 0x0000, 0, 0), + IMX8MN_PAD_BOOT_MODE3__I2C1_SDA = IOMUX_PAD(0x0260, 0x0024, 1, 0x056C, 3, 0), + + IMX8MN_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO00__ANAMIX_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO00__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0), + + IMX8MN_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO01__ANAMIX_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO01__CCMSRCGPCMIX_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0), + + IMX8MN_PAD_GPIO1_IO02__GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0), + + IMX8MN_PAD_GPIO1_IO03__GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO03__USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO03__SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO03__ANAMIX_XTAL_OK = IOMUX_PAD(0x029C, 0x0034, 6, 0x0000, 0, 0), + + IMX8MN_PAD_GPIO1_IO04__GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO04__USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO04__SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO04__ANAMIX_XTAL_OK_LV = IOMUX_PAD(0x02A0, 0x0038, 6, 0x0000, 0, 0), + + IMX8MN_PAD_GPIO1_IO05__GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO05__M4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO05__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0), + IMX8MN_PAD_GPIO1_IO05__CCMSRCGPCMIX_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0), + + IMX8MN_PAD_GPIO1_IO06__GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO06__ENET1_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO06__USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO06__CCMSRCGPCMIX_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0), + + IMX8MN_PAD_GPIO1_IO07__GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO07__ENET1_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0), + IMX8MN_PAD_GPIO1_IO07__USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO07__CCMSRCGPCMIX_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0), + + IMX8MN_PAD_GPIO1_IO08__GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO08__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x02B0, 0x0048, 2, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO08__USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO08__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0), + + IMX8MN_PAD_GPIO1_IO09__GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO09__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x02B4, 0x004C, 2, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO09__USDHC3_RESET_B = IOMUX_PAD(0x02B4, 0x004C, 4, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO09__SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO09__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0), + + IMX8MN_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO10__USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO10__PWM3_OUT = IOMUX_PAD(0x02B8, 0x0050, 2, 0x0000, 0, 0), + + IMX8MN_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO11__PWM2_OUT = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO11__USDHC3_VSELECT = IOMUX_PAD(0x02BC, 0x0054, 4, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO11__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0), + IMX8MN_PAD_GPIO1_IO11__CCMSRCGPCMIX_OUT0 = IOMUX_PAD(0x02BC, 0x0054, 6, 0x0000, 0, 0), + + IMX8MN_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO12__USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO12__SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO12__CCMSRCGPCMIX_OUT1 = IOMUX_PAD(0x02C0, 0x0058, 6, 0x0000, 0, 0), + + IMX8MN_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO13__USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO13__PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO13__CCMSRCGPCMIX_OUT2 = IOMUX_PAD(0x02C4, 0x005C, 6, 0x0000, 0, 0), + + IMX8MN_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO14__USDHC3_CD_B = IOMUX_PAD(0x02C8, 0x0060, 4, 0x0598, 2, 0), + IMX8MN_PAD_GPIO1_IO14__PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO14__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0), + + IMX8MN_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO15__USDHC3_WP = IOMUX_PAD(0x02CC, 0x0064, 4, 0x05B8, 2, 0), + IMX8MN_PAD_GPIO1_IO15__PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0), + IMX8MN_PAD_GPIO1_IO15__CCMSRCGPCMIX_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0), + + IMX8MN_PAD_ENET_MDC__ENET1_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0), + IMX8MN_PAD_ENET_MDC__SAI6_TX_DATA0 = IOMUX_PAD(0x02D0, 0x0068, 2, 0x0000, 0, 0), + IMX8MN_PAD_ENET_MDC__PDM_BIT_STREAM3 = IOMUX_PAD(0x02D0, 0x0068, 3, 0x0540, 1, 0), + IMX8MN_PAD_ENET_MDC__SPDIF1_OUT = IOMUX_PAD(0x02D0, 0x0068, 4, 0x0000, 0, 0), + IMX8MN_PAD_ENET_MDC__GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0), + IMX8MN_PAD_ENET_MDC__USDHC3_STROBE = IOMUX_PAD(0x02D0, 0x0068, 6, 0x059C, 1, 0), + + IMX8MN_PAD_ENET_MDIO__ENET1_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0), + IMX8MN_PAD_ENET_MDIO__SAI6_TX_SYNC = IOMUX_PAD(0x02D4, 0x006C, 2, 0x0000, 0, 0), + IMX8MN_PAD_ENET_MDIO__PDM_BIT_STREAM2 = IOMUX_PAD(0x02D4, 0x006C, 3, 0x053C, 1, 0), + IMX8MN_PAD_ENET_MDIO__SPDIF1_IN = IOMUX_PAD(0x02D4, 0x006C, 4, 0x05CC, 1, 0), + IMX8MN_PAD_ENET_MDIO__GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0), + IMX8MN_PAD_ENET_MDIO__USDHC3_DATA5 = IOMUX_PAD(0x02D4, 0x006C, 6, 0x0550, 1, 0), + + IMX8MN_PAD_ENET_TD3__ENET1_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0), + IMX8MN_PAD_ENET_TD3__SAI6_TX_BCLK = IOMUX_PAD(0x02D8, 0x0070, 2, 0x0000, 0, 0), + IMX8MN_PAD_ENET_TD3__PDM_BIT_STREAM1 = IOMUX_PAD(0x02D8, 0x0070, 3, 0x0538, 1, 0), + IMX8MN_PAD_ENET_TD3__SPDIF1_EXT_CLK = IOMUX_PAD(0x02D8, 0x0070, 4, 0x0568, 1, 0), + IMX8MN_PAD_ENET_TD3__GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0), + IMX8MN_PAD_ENET_TD3__USDHC3_DATA6 = IOMUX_PAD(0x02D8, 0x0070, 6, 0x0584, 1, 0), + + IMX8MN_PAD_ENET_TD2__ENET1_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0), + IMX8MN_PAD_ENET_TD2__ENET1_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x05A4, 0, 0), + IMX8MN_PAD_ENET_TD2__CCMSRCGPCMIX_ENET_REF_CLK_ROOT = IOMUX_PAD(0x02DC, 0x0074, 1, 0x05A4, 0, 0), + IMX8MN_PAD_ENET_TD2__SAI6_RX_DATA0 = IOMUX_PAD(0x02DC, 0x0074, 2, 0x0000, 0, 0), + IMX8MN_PAD_ENET_TD2__PDM_BIT_STREAM3 = IOMUX_PAD(0x02DC, 0x0074, 3, 0x0540, 2, 0), + IMX8MN_PAD_ENET_TD2__GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0), + IMX8MN_PAD_ENET_TD2__USDHC3_DATA7 = IOMUX_PAD(0x02DC, 0x0074, 6, 0x054C, 1, 0), + + IMX8MN_PAD_ENET_TD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0), + IMX8MN_PAD_ENET_TD1__SAI6_RX_SYNC = IOMUX_PAD(0x02E0, 0x0078, 2, 0x0000, 0, 0), + IMX8MN_PAD_ENET_TD1__PDM_BIT_STREAM2 = IOMUX_PAD(0x02E0, 0x0078, 3, 0x053C, 2, 0), + IMX8MN_PAD_ENET_TD1__GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0), + IMX8MN_PAD_ENET_TD1__USDHC3_CD_B = IOMUX_PAD(0x02E0, 0x0078, 6, 0x0598, 3, 0), + + IMX8MN_PAD_ENET_TD0__ENET1_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0), + IMX8MN_PAD_ENET_TD0__SAI6_RX_BCLK = IOMUX_PAD(0x02E4, 0x007C, 2, 0x0000, 0, 0), + IMX8MN_PAD_ENET_TD0__PDM_BIT_STREAM1 = IOMUX_PAD(0x02E4, 0x007C, 3, 0x0538, 2, 0), + IMX8MN_PAD_ENET_TD0__GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0), + IMX8MN_PAD_ENET_TD0__USDHC3_WP = IOMUX_PAD(0x02E4, 0x007C, 6, 0x05B8, 3, 0), + + IMX8MN_PAD_ENET_TX_CTL__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0), + IMX8MN_PAD_ENET_TX_CTL__SAI6_MCLK = IOMUX_PAD(0x02E8, 0x0080, 2, 0x0000, 0, 0), + IMX8MN_PAD_ENET_TX_CTL__GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0), + IMX8MN_PAD_ENET_TX_CTL__USDHC3_DATA0 = IOMUX_PAD(0x02E8, 0x0080, 6, 0x05B4, 1, 0), + + IMX8MN_PAD_ENET_TXC__ENET1_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0), + IMX8MN_PAD_ENET_TXC__ENET1_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0), + IMX8MN_PAD_ENET_TXC__SAI7_TX_DATA0 = IOMUX_PAD(0x02EC, 0x0084, 2, 0x0000, 0, 0), + IMX8MN_PAD_ENET_TXC__GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0), + IMX8MN_PAD_ENET_TXC__USDHC3_DATA1 = IOMUX_PAD(0x02EC, 0x0084, 6, 0x05B0, 1, 0), + + IMX8MN_PAD_ENET_RX_CTL__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0574, 0, 0), + IMX8MN_PAD_ENET_RX_CTL__SAI7_TX_SYNC = IOMUX_PAD(0x02F0, 0x0088, 2, 0x0000, 0, 0), + IMX8MN_PAD_ENET_RX_CTL__PDM_BIT_STREAM3 = IOMUX_PAD(0x02F0, 0x0088, 3, 0x0540, 3, 0), + IMX8MN_PAD_ENET_RX_CTL__GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0), + IMX8MN_PAD_ENET_RX_CTL__USDHC3_DATA2 = IOMUX_PAD(0x02F0, 0x0088, 6, 0x05E4, 1, 0), + + IMX8MN_PAD_ENET_RXC__ENET1_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0), + IMX8MN_PAD_ENET_RXC__ENET1_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x05C8, 0, 0), + IMX8MN_PAD_ENET_RXC__SAI7_TX_BCLK = IOMUX_PAD(0x02F4, 0x008C, 2, 0x0000, 0, 0), + IMX8MN_PAD_ENET_RXC__PDM_BIT_STREAM2 = IOMUX_PAD(0x02F4, 0x008C, 3, 0x053C, 3, 0), + IMX8MN_PAD_ENET_RXC__GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0), + IMX8MN_PAD_ENET_RXC__USDHC3_DATA3 = IOMUX_PAD(0x02F4, 0x008C, 6, 0x05E0, 1, 0), + + IMX8MN_PAD_ENET_RD0__ENET1_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x057C, 0, 0), + IMX8MN_PAD_ENET_RD0__SAI7_RX_DATA0 = IOMUX_PAD(0x02F8, 0x0090, 2, 0x0000, 0, 0), + IMX8MN_PAD_ENET_RD0__PDM_BIT_STREAM1 = IOMUX_PAD(0x02F8, 0x0090, 3, 0x0538, 3, 0), + IMX8MN_PAD_ENET_RD0__GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0), + IMX8MN_PAD_ENET_RD0__USDHC3_DATA4 = IOMUX_PAD(0x02F8, 0x0090, 6, 0x0558, 1, 0), + + IMX8MN_PAD_ENET_RD1__ENET1_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0554, 0, 0), + IMX8MN_PAD_ENET_RD1__SAI7_RX_SYNC = IOMUX_PAD(0x02FC, 0x0094, 2, 0x0000, 0, 0), + IMX8MN_PAD_ENET_RD1__PDM_BIT_STREAM0 = IOMUX_PAD(0x02FC, 0x0094, 3, 0x0534, 1, 0), + IMX8MN_PAD_ENET_RD1__GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0), + IMX8MN_PAD_ENET_RD1__USDHC3_RESET_B = IOMUX_PAD(0x02FC, 0x0094, 6, 0x0000, 0, 0), + + IMX8MN_PAD_ENET_RD2__ENET1_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0), + IMX8MN_PAD_ENET_RD2__SAI7_RX_BCLK = IOMUX_PAD(0x0300, 0x0098, 2, 0x0000, 0, 0), + IMX8MN_PAD_ENET_RD2__PDM_CLK = IOMUX_PAD(0x0300, 0x0098, 3, 0x0000, 0, 0), + IMX8MN_PAD_ENET_RD2__GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0), + IMX8MN_PAD_ENET_RD2__USDHC3_CLK = IOMUX_PAD(0x0300, 0x0098, 6, 0x05A0, 1, 0), + + IMX8MN_PAD_ENET_RD3__ENET1_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0), + IMX8MN_PAD_ENET_RD3__SAI7_MCLK = IOMUX_PAD(0x0304, 0x009C, 2, 0x0000, 0, 0), + IMX8MN_PAD_ENET_RD3__SPDIF1_IN = IOMUX_PAD(0x0304, 0x009C, 3, 0x05CC, 5, 0), + IMX8MN_PAD_ENET_RD3__GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0), + IMX8MN_PAD_ENET_RD3__USDHC3_CMD = IOMUX_PAD(0x0304, 0x009C, 6, 0x05DC, 1, 0), + + IMX8MN_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD1_CLK__ENET1_MDC = IOMUX_PAD(0x0308, 0x00A0, 1, 0x0000, 0, 0), + IMX8MN_PAD_SD1_CLK__UART1_DCE_TX = IOMUX_PAD(0x0308, 0x00A0, 4, 0x0000, 0, 0), + IMX8MN_PAD_SD1_CLK__UART1_DTE_RX = IOMUX_PAD(0x0308, 0x00A0, 4, 0x04F4, 4, 0), + IMX8MN_PAD_SD1_CLK__GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD1_CMD__ENET1_MDIO = IOMUX_PAD(0x030C, 0x00A4, 1, 0x04C0, 3, 0), + IMX8MN_PAD_SD1_CMD__UART1_DCE_RX = IOMUX_PAD(0x030C, 0x00A4, 4, 0x04F4, 5, 0), + IMX8MN_PAD_SD1_CMD__UART1_DTE_TX = IOMUX_PAD(0x030C, 0x00A4, 4, 0x0000, 0, 0), + IMX8MN_PAD_SD1_CMD__GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA0__ENET1_RGMII_TD1 = IOMUX_PAD(0x0310, 0x00A8, 1, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA0__UART1_DCE_RTS_B = IOMUX_PAD(0x0310, 0x00A8, 4, 0x04F0, 4, 0), + IMX8MN_PAD_SD1_DATA0__UART1_DTE_CTS_B = IOMUX_PAD(0x0310, 0x00A8, 4, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA0__GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA1__ENET1_RGMII_TD0 = IOMUX_PAD(0x0314, 0x00AC, 1, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA1__UART1_DCE_CTS_B = IOMUX_PAD(0x0314, 0x00AC, 4, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA1__UART1_DTE_RTS_B = IOMUX_PAD(0x0314, 0x00AC, 4, 0x04F0, 5, 0), + IMX8MN_PAD_SD1_DATA1__GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA2__ENET1_RGMII_RD0 = IOMUX_PAD(0x0318, 0x00B0, 1, 0x057C, 1, 0), + IMX8MN_PAD_SD1_DATA2__UART2_DCE_TX = IOMUX_PAD(0x0318, 0x00B0, 4, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA2__UART2_DTE_RX = IOMUX_PAD(0x0318, 0x00B0, 4, 0x04FC, 4, 0), + IMX8MN_PAD_SD1_DATA2__GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA3__ENET1_RGMII_RD1 = IOMUX_PAD(0x031C, 0x00B4, 1, 0x0554, 1, 0), + IMX8MN_PAD_SD1_DATA3__UART2_DCE_RX = IOMUX_PAD(0x031C, 0x00B4, 4, 0x04FC, 5, 0), + IMX8MN_PAD_SD1_DATA3__UART2_DTE_TX = IOMUX_PAD(0x031C, 0x00B4, 4, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA3__GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA4__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x0320, 0x00B8, 1, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA4__I2C1_SCL = IOMUX_PAD(0x0320, 0x00B8, 3, 0x055C, 1, 0), + IMX8MN_PAD_SD1_DATA4__UART2_DCE_RTS_B = IOMUX_PAD(0x0320, 0x00B8, 4, 0x04F8, 4, 0), + IMX8MN_PAD_SD1_DATA4__UART2_DTE_CTS_B = IOMUX_PAD(0x0320, 0x00B8, 4, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA4__GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA5__ENET1_TX_ER = IOMUX_PAD(0x0324, 0x00BC, 1, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA5__I2C1_SDA = IOMUX_PAD(0x0324, 0x00BC, 3, 0x056C, 1, 0), + IMX8MN_PAD_SD1_DATA5__UART2_DCE_CTS_B = IOMUX_PAD(0x0324, 0x00BC, 4, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA5__UART2_DTE_RTS_B = IOMUX_PAD(0x0324, 0x00BC, 4, 0x04F8, 5, 0), + IMX8MN_PAD_SD1_DATA5__GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA6__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x0328, 0x00C0, 1, 0x0574, 1, 0), + IMX8MN_PAD_SD1_DATA6__I2C2_SCL = IOMUX_PAD(0x0328, 0x00C0, 3, 0x05D0, 1, 0), + IMX8MN_PAD_SD1_DATA6__UART3_DCE_TX = IOMUX_PAD(0x0328, 0x00C0, 4, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA6__UART3_DTE_RX = IOMUX_PAD(0x0328, 0x00C0, 4, 0x0504, 4, 0), + IMX8MN_PAD_SD1_DATA6__GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA7__ENET1_RX_ER = IOMUX_PAD(0x032C, 0x00C4, 1, 0x05C8, 1, 0), + IMX8MN_PAD_SD1_DATA7__I2C2_SDA = IOMUX_PAD(0x032C, 0x00C4, 3, 0x0560, 1, 0), + IMX8MN_PAD_SD1_DATA7__UART3_DCE_RX = IOMUX_PAD(0x032C, 0x00C4, 4, 0x0504, 5, 0), + IMX8MN_PAD_SD1_DATA7__UART3_DTE_TX = IOMUX_PAD(0x032C, 0x00C4, 4, 0x0000, 0, 0), + IMX8MN_PAD_SD1_DATA7__GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SD1_RESET_B__USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD1_RESET_B__ENET1_TX_CLK = IOMUX_PAD(0x0330, 0x00C8, 1, 0x05A4, 1, 0), + IMX8MN_PAD_SD1_RESET_B__CCMSRCGPCMIX_ENET_REF_CLK_ROOT = IOMUX_PAD(0x0330, 0x00C8, 1, 0x05A4, 0, 0), + IMX8MN_PAD_SD1_RESET_B__I2C3_SCL = IOMUX_PAD(0x0330, 0x00C8, 3, 0x0588, 1, 0), + IMX8MN_PAD_SD1_RESET_B__UART3_DCE_RTS_B = IOMUX_PAD(0x0330, 0x00C8, 4, 0x0500, 2, 0), + IMX8MN_PAD_SD1_RESET_B__UART3_DTE_CTS_B = IOMUX_PAD(0x0330, 0x00C8, 4, 0x0000, 0, 0), + IMX8MN_PAD_SD1_RESET_B__GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD1_STROBE__I2C3_SDA = IOMUX_PAD(0x0334, 0x00CC, 3, 0x05BC, 1, 0), + IMX8MN_PAD_SD1_STROBE__UART3_DCE_CTS_B = IOMUX_PAD(0x0334, 0x00CC, 4, 0x0000, 0, 0), + IMX8MN_PAD_SD1_STROBE__UART3_DTE_RTS_B = IOMUX_PAD(0x0334, 0x00CC, 4, 0x0500, 3, 0), + IMX8MN_PAD_SD1_STROBE__GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD2_CD_B__GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0), + IMX8MN_PAD_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK = IOMUX_PAD(0x0338, 0x00D0, 6, 0x0000, 0, 0), + + IMX8MN_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD2_CLK__SAI5_RX_SYNC = IOMUX_PAD(0x033C, 0x00D4, 1, 0x04E4, 1, 0), + IMX8MN_PAD_SD2_CLK__ECSPI2_SCLK = IOMUX_PAD(0x033C, 0x00D4, 2, 0x0580, 1, 0), + IMX8MN_PAD_SD2_CLK__UART4_DCE_RX = IOMUX_PAD(0x033C, 0x00D4, 3, 0x050C, 4, 0), + IMX8MN_PAD_SD2_CLK__UART4_DTE_TX = IOMUX_PAD(0x033C, 0x00D4, 3, 0x0000, 0, 0), + IMX8MN_PAD_SD2_CLK__SAI5_MCLK = IOMUX_PAD(0x033C, 0x00D4, 4, 0x0594, 1, 0), + IMX8MN_PAD_SD2_CLK__GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0), + IMX8MN_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 = IOMUX_PAD(0x033C, 0x00D4, 6, 0x0000, 0, 0), + + IMX8MN_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD2_CMD__SAI5_RX_BCLK = IOMUX_PAD(0x0340, 0x00D8, 1, 0x04D0, 1, 0), + IMX8MN_PAD_SD2_CMD__ECSPI2_MOSI = IOMUX_PAD(0x0340, 0x00D8, 2, 0x0590, 1, 0), + IMX8MN_PAD_SD2_CMD__UART4_DCE_TX = IOMUX_PAD(0x0340, 0x00D8, 3, 0x0000, 0, 0), + IMX8MN_PAD_SD2_CMD__UART4_DTE_RX = IOMUX_PAD(0x0340, 0x00D8, 3, 0x050C, 5, 0), + IMX8MN_PAD_SD2_CMD__PDM_CLK = IOMUX_PAD(0x0340, 0x00D8, 4, 0x0000, 0, 0), + IMX8MN_PAD_SD2_CMD__GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0), + IMX8MN_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 = IOMUX_PAD(0x0340, 0x00D8, 6, 0x0000, 0, 0), + + IMX8MN_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD2_DATA0__SAI5_RX_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 1, 0x04D4, 1, 0), + IMX8MN_PAD_SD2_DATA0__I2C4_SDA = IOMUX_PAD(0x0344, 0x00DC, 2, 0x058C, 1, 0), + IMX8MN_PAD_SD2_DATA0__UART2_DCE_RX = IOMUX_PAD(0x0344, 0x00DC, 3, 0x04FC, 6, 0), + IMX8MN_PAD_SD2_DATA0__UART2_DTE_TX = IOMUX_PAD(0x0344, 0x00DC, 3, 0x0000, 0, 0), + IMX8MN_PAD_SD2_DATA0__PDM_BIT_STREAM0 = IOMUX_PAD(0x0344, 0x00DC, 4, 0x0534, 2, 0), + IMX8MN_PAD_SD2_DATA0__GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0), + IMX8MN_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 = IOMUX_PAD(0x0344, 0x00DC, 6, 0x0000, 0, 0), + + IMX8MN_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD2_DATA1__SAI5_TX_SYNC = IOMUX_PAD(0x0348, 0x00E0, 1, 0x04EC, 1, 0), + IMX8MN_PAD_SD2_DATA1__I2C4_SCL = IOMUX_PAD(0x0348, 0x00E0, 2, 0x05D4, 1, 0), + IMX8MN_PAD_SD2_DATA1__UART2_DCE_TX = IOMUX_PAD(0x0348, 0x00E0, 3, 0x0000, 0, 0), + IMX8MN_PAD_SD2_DATA1__UART2_DTE_RX = IOMUX_PAD(0x0348, 0x00E0, 3, 0x04FC, 7, 0), + IMX8MN_PAD_SD2_DATA1__PDM_BIT_STREAM1 = IOMUX_PAD(0x0348, 0x00E0, 4, 0x0538, 4, 0), + IMX8MN_PAD_SD2_DATA1__GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0), + IMX8MN_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0), + + IMX8MN_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD2_DATA2__SAI5_TX_BCLK = IOMUX_PAD(0x034C, 0x00E4, 1, 0x04E8, 1, 0), + IMX8MN_PAD_SD2_DATA2__ECSPI2_SS0 = IOMUX_PAD(0x034C, 0x00E4, 2, 0x0570, 2, 0), + IMX8MN_PAD_SD2_DATA2__SPDIF1_OUT = IOMUX_PAD(0x034C, 0x00E4, 3, 0x0000, 0, 0), + IMX8MN_PAD_SD2_DATA2__PDM_BIT_STREAM2 = IOMUX_PAD(0x034C, 0x00E4, 4, 0x053C, 4, 0), + IMX8MN_PAD_SD2_DATA2__GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0), + IMX8MN_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0), + + IMX8MN_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD2_DATA3__SAI5_TX_DATA0 = IOMUX_PAD(0x0350, 0x00E8, 1, 0x0000, 0, 0), + IMX8MN_PAD_SD2_DATA3__ECSPI2_MISO = IOMUX_PAD(0x0350, 0x00E8, 2, 0x0578, 1, 0), + IMX8MN_PAD_SD2_DATA3__SPDIF1_IN = IOMUX_PAD(0x0350, 0x00E8, 3, 0x05CC, 2, 0), + IMX8MN_PAD_SD2_DATA3__PDM_BIT_STREAM3 = IOMUX_PAD(0x0350, 0x00E8, 4, 0x0540, 4, 0), + IMX8MN_PAD_SD2_DATA3__GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0), + IMX8MN_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0), + + IMX8MN_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD2_RESET_B__GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0), + IMX8MN_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0), + + IMX8MN_PAD_SD2_WP__USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0), + IMX8MN_PAD_SD2_WP__GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0), + IMX8MN_PAD_SD2_WP__CORESIGHT_EVENTI = IOMUX_PAD(0x0358, 0x00F0, 6, 0x0000, 0, 0), + + IMX8MN_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0), + IMX8MN_PAD_NAND_ALE__QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0), + IMX8MN_PAD_NAND_ALE__PDM_BIT_STREAM0 = IOMUX_PAD(0x035C, 0x00F4, 3, 0x0534, 3, 0), + IMX8MN_PAD_NAND_ALE__UART3_DCE_RX = IOMUX_PAD(0x035C, 0x00F4, 4, 0x0504, 6, 0), + IMX8MN_PAD_NAND_ALE__UART3_DTE_TX = IOMUX_PAD(0x035C, 0x00F4, 4, 0x0000, 0, 0), + IMX8MN_PAD_NAND_ALE__GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0), + IMX8MN_PAD_NAND_ALE__CORESIGHT_TRACE_CLK = IOMUX_PAD(0x035C, 0x00F4, 6, 0x0000, 0, 0), + + IMX8MN_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0), + IMX8MN_PAD_NAND_CE0_B__QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0), + IMX8MN_PAD_NAND_CE0_B__PDM_BIT_STREAM1 = IOMUX_PAD(0x0360, 0x00F8, 3, 0x0538, 5, 0), + IMX8MN_PAD_NAND_CE0_B__UART3_DCE_TX = IOMUX_PAD(0x0360, 0x00F8, 4, 0x0000, 0, 0), + IMX8MN_PAD_NAND_CE0_B__UART3_DTE_RX = IOMUX_PAD(0x0360, 0x00F8, 4, 0x0504, 7, 0), + IMX8MN_PAD_NAND_CE0_B__GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0), + IMX8MN_PAD_NAND_CE0_B__CORESIGHT_TRACE_CTL = IOMUX_PAD(0x0360, 0x00F8, 6, 0x0000, 0, 0), + + IMX8MN_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0), + IMX8MN_PAD_NAND_CE1_B__QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0), + IMX8MN_PAD_NAND_CE1_B__USDHC3_STROBE = IOMUX_PAD(0x0364, 0x00FC, 2, 0x059C, 0, 0), + IMX8MN_PAD_NAND_CE1_B__PDM_BIT_STREAM0 = IOMUX_PAD(0x0364, 0x00FC, 3, 0x0534, 4, 0), + IMX8MN_PAD_NAND_CE1_B__I2C4_SCL = IOMUX_PAD(0x0364, 0x00FC, 4, 0x05D4, 2, 0), + IMX8MN_PAD_NAND_CE1_B__GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0), + IMX8MN_PAD_NAND_CE1_B__CORESIGHT_TRACE0 = IOMUX_PAD(0x0364, 0x00FC, 6, 0x0000, 0, 0), + + IMX8MN_PAD_NAND_CE2_B__RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0), + IMX8MN_PAD_NAND_CE2_B__QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0), + IMX8MN_PAD_NAND_CE2_B__USDHC3_DATA5 = IOMUX_PAD(0x0368, 0x0100, 2, 0x0550, 0, 0), + IMX8MN_PAD_NAND_CE2_B__PDM_BIT_STREAM1 = IOMUX_PAD(0x0368, 0x0100, 3, 0x0538, 6, 0), + IMX8MN_PAD_NAND_CE2_B__I2C4_SDA = IOMUX_PAD(0x0368, 0x0100, 4, 0x058C, 2, 0), + IMX8MN_PAD_NAND_CE2_B__GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0), + IMX8MN_PAD_NAND_CE2_B__CORESIGHT_TRACE1 = IOMUX_PAD(0x0368, 0x0100, 6, 0x0000, 0, 0), + + IMX8MN_PAD_NAND_CE3_B__RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0), + IMX8MN_PAD_NAND_CE3_B__QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0), + IMX8MN_PAD_NAND_CE3_B__USDHC3_DATA6 = IOMUX_PAD(0x036C, 0x0104, 2, 0x0584, 0, 0), + IMX8MN_PAD_NAND_CE3_B__PDM_BIT_STREAM2 = IOMUX_PAD(0x036C, 0x0104, 3, 0x053C, 5, 0), + IMX8MN_PAD_NAND_CE3_B__I2C3_SDA = IOMUX_PAD(0x036C, 0x0104, 4, 0x05BC, 2, 0), + IMX8MN_PAD_NAND_CE3_B__GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0), + IMX8MN_PAD_NAND_CE3_B__CORESIGHT_TRACE2 = IOMUX_PAD(0x036C, 0x0104, 6, 0x0000, 0, 0), + + IMX8MN_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0), + IMX8MN_PAD_NAND_CLE__QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0), + IMX8MN_PAD_NAND_CLE__USDHC3_DATA7 = IOMUX_PAD(0x0370, 0x0108, 2, 0x054C, 0, 0), + IMX8MN_PAD_NAND_CLE__GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0), + IMX8MN_PAD_NAND_CLE__CORESIGHT_TRACE3 = IOMUX_PAD(0x0370, 0x0108, 6, 0x0000, 0, 0), + + IMX8MN_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA00__QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA00__PDM_BIT_STREAM2 = IOMUX_PAD(0x0374, 0x010C, 3, 0x053C, 6, 0), + IMX8MN_PAD_NAND_DATA00__UART4_DCE_RX = IOMUX_PAD(0x0374, 0x010C, 4, 0x050C, 6, 0), + IMX8MN_PAD_NAND_DATA00__UART4_DTE_TX = IOMUX_PAD(0x0374, 0x010C, 4, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA00__GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA00__CORESIGHT_TRACE4 = IOMUX_PAD(0x0374, 0x010C, 6, 0x0000, 0, 0), + + IMX8MN_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA01__QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA01__PDM_BIT_STREAM3 = IOMUX_PAD(0x0378, 0x0110, 3, 0x0540, 5, 0), + IMX8MN_PAD_NAND_DATA01__UART4_DCE_TX = IOMUX_PAD(0x0378, 0x0110, 4, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA01__UART4_DTE_RX = IOMUX_PAD(0x0378, 0x0110, 4, 0x050C, 7, 0), + IMX8MN_PAD_NAND_DATA01__GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA01__CORESIGHT_TRACE5 = IOMUX_PAD(0x0378, 0x0110, 6, 0x0000, 0, 0), + + IMX8MN_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA02__USDHC3_CD_B = IOMUX_PAD(0x037C, 0x0114, 2, 0x0598, 0, 0), + IMX8MN_PAD_NAND_DATA02__I2C4_SDA = IOMUX_PAD(0x037C, 0x0114, 4, 0x058C, 3, 0), + IMX8MN_PAD_NAND_DATA02__GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA02__CORESIGHT_TRACE6 = IOMUX_PAD(0x037C, 0x0114, 6, 0x0000, 0, 0), + + IMX8MN_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA03__QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA03__USDHC3_WP = IOMUX_PAD(0x0380, 0x0118, 2, 0x05B8, 0, 0), + IMX8MN_PAD_NAND_DATA03__GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA03__CORESIGHT_TRACE7 = IOMUX_PAD(0x0380, 0x0118, 6, 0x0000, 0, 0), + + IMX8MN_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA04__QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA04__USDHC3_DATA0 = IOMUX_PAD(0x0384, 0x011C, 2, 0x05B4, 0, 0), + IMX8MN_PAD_NAND_DATA04__GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA04__CORESIGHT_TRACE8 = IOMUX_PAD(0x0384, 0x011C, 6, 0x0000, 0, 0), + + IMX8MN_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA05__QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA05__USDHC3_DATA1 = IOMUX_PAD(0x0388, 0x0120, 2, 0x05B0, 0, 0), + IMX8MN_PAD_NAND_DATA05__GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA05__CORESIGHT_TRACE9 = IOMUX_PAD(0x0388, 0x0120, 6, 0x0000, 0, 0), + + IMX8MN_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA06__QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA06__USDHC3_DATA2 = IOMUX_PAD(0x038C, 0x0124, 2, 0x05E4, 0, 0), + IMX8MN_PAD_NAND_DATA06__GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA06__CORESIGHT_TRACE10 = IOMUX_PAD(0x038C, 0x0124, 6, 0x0000, 0, 0), + + IMX8MN_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA07__QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA07__USDHC3_DATA3 = IOMUX_PAD(0x0390, 0x0128, 2, 0x05E0, 0, 0), + IMX8MN_PAD_NAND_DATA07__GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DATA07__CORESIGHT_TRACE11 = IOMUX_PAD(0x0390, 0x0128, 6, 0x0000, 0, 0), + + IMX8MN_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DQS__QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DQS__PDM_CLK = IOMUX_PAD(0x0394, 0x012C, 3, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DQS__I2C3_SCL = IOMUX_PAD(0x0394, 0x012C, 4, 0x0588, 2, 0), + IMX8MN_PAD_NAND_DQS__GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0), + IMX8MN_PAD_NAND_DQS__CORESIGHT_TRACE12 = IOMUX_PAD(0x0394, 0x012C, 6, 0x0000, 0, 0), + + IMX8MN_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0), + IMX8MN_PAD_NAND_RE_B__QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0), + IMX8MN_PAD_NAND_RE_B__USDHC3_DATA4 = IOMUX_PAD(0x0398, 0x0130, 2, 0x0558, 0, 0), + IMX8MN_PAD_NAND_RE_B__PDM_BIT_STREAM1 = IOMUX_PAD(0x0398, 0x0130, 3, 0x0538, 7, 0), + IMX8MN_PAD_NAND_RE_B__GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0), + IMX8MN_PAD_NAND_RE_B__CORESIGHT_TRACE13 = IOMUX_PAD(0x0398, 0x0130, 6, 0x0000, 0, 0), + + IMX8MN_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0), + IMX8MN_PAD_NAND_READY_B__USDHC3_RESET_B = IOMUX_PAD(0x039C, 0x0134, 2, 0x0000, 0, 0), + IMX8MN_PAD_NAND_READY_B__PDM_BIT_STREAM3 = IOMUX_PAD(0x039C, 0x0134, 3, 0x0540, 6, 0), + IMX8MN_PAD_NAND_READY_B__I2C3_SCL = IOMUX_PAD(0x039C, 0x0134, 4, 0x0588, 3, 0), + IMX8MN_PAD_NAND_READY_B__GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0), + IMX8MN_PAD_NAND_READY_B__CORESIGHT_TRACE14 = IOMUX_PAD(0x039C, 0x0134, 6, 0x0000, 0, 0), + + IMX8MN_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0), + IMX8MN_PAD_NAND_WE_B__USDHC3_CLK = IOMUX_PAD(0x03A0, 0x0138, 2 | IOMUX_CONFIG_SION, 0x05A0, 0, 0), + IMX8MN_PAD_NAND_WE_B__I2C3_SDA = IOMUX_PAD(0x03A0, 0x0138, 4, 0x05BC, 3, 0), + IMX8MN_PAD_NAND_WE_B__GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0), + IMX8MN_PAD_NAND_WE_B__CORESIGHT_TRACE15 = IOMUX_PAD(0x03A0, 0x0138, 6, 0x0000, 0, 0), + + IMX8MN_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0), + IMX8MN_PAD_NAND_WP_B__USDHC3_CMD = IOMUX_PAD(0x03A4, 0x013C, 2, 0x05DC, 0, 0), + IMX8MN_PAD_NAND_WP_B__I2C4_SDA = IOMUX_PAD(0x03A4, 0x013C, 4, 0x058C, 4, 0), + IMX8MN_PAD_NAND_WP_B__GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0), + IMX8MN_PAD_NAND_WP_B__CORESIGHT_EVENTO = IOMUX_PAD(0x03A4, 0x013C, 6, 0x0000, 0, 0), + + IMX8MN_PAD_SAI5_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0), + IMX8MN_PAD_SAI5_RXFS__GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SAI5_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0), + IMX8MN_PAD_SAI5_RXC__PDM_CLK = IOMUX_PAD(0x03AC, 0x0144, 4, 0x0000, 0, 0), + IMX8MN_PAD_SAI5_RXC__GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SAI5_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0), + IMX8MN_PAD_SAI5_RXD0__PDM_BIT_STREAM0 = IOMUX_PAD(0x03B0, 0x0148, 4, 0x0534, 0, 0), + IMX8MN_PAD_SAI5_RXD0__GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SAI5_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0), + IMX8MN_PAD_SAI5_RXD1__SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0), + IMX8MN_PAD_SAI5_RXD1__PDM_BIT_STREAM1 = IOMUX_PAD(0x03B4, 0x014C, 4, 0x0538, 0, 0), + IMX8MN_PAD_SAI5_RXD1__GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SAI5_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0), + IMX8MN_PAD_SAI5_RXD2__SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0), + IMX8MN_PAD_SAI5_RXD2__PDM_BIT_STREAM2 = IOMUX_PAD(0x03B8, 0x0150, 4, 0x053C, 0, 0), + IMX8MN_PAD_SAI5_RXD2__GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SAI5_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0), + IMX8MN_PAD_SAI5_RXD3__SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0), + IMX8MN_PAD_SAI5_RXD3__PDM_BIT_STREAM3 = IOMUX_PAD(0x03BC, 0x0154, 4, 0x0540, 0, 0), + IMX8MN_PAD_SAI5_RXD3__GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SAI5_MCLK__SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x0594, 0, 0), + IMX8MN_PAD_SAI5_MCLK__GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SAI2_RXFS__SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_RXFS__SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0), + IMX8MN_PAD_SAI2_RXFS__SAI5_TX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 2, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_RXFS__SAI2_RX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 3, 0x05AC, 0, 0), + IMX8MN_PAD_SAI2_RXFS__UART1_DCE_TX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_RXFS__UART1_DTE_RX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x04F4, 2, 0), + IMX8MN_PAD_SAI2_RXFS__GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_RXFS__PDM_BIT_STREAM2 = IOMUX_PAD(0x0418, 0x01B0, 6, 0x053C, 7, 0), + + IMX8MN_PAD_SAI2_RXC__SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_RXC__SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0), + IMX8MN_PAD_SAI2_RXC__UART1_DCE_RX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x04F4, 3, 0), + IMX8MN_PAD_SAI2_RXC__UART1_DTE_TX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_RXC__GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_RXC__PDM_BIT_STREAM1 = IOMUX_PAD(0x041C, 0x01B4, 6, 0x0538, 8, 0), + + IMX8MN_PAD_SAI2_RXD0__SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_RXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_RXD0__SAI2_TX_DATA1 = IOMUX_PAD(0x0420, 0x01B8, 3, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_RXD0__UART1_DCE_RTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x04F0, 2, 0), + IMX8MN_PAD_SAI2_RXD0__UART1_DTE_CTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_RXD0__GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_RXD0__PDM_BIT_STREAM3 = IOMUX_PAD(0x0420, 0x01B8, 6, 0x0540, 7, 0), + + IMX8MN_PAD_SAI2_TXFS__SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_TXFS__SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_TXFS__SAI2_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 3, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_TXFS__UART1_DCE_CTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_TXFS__UART1_DTE_RTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x04F0, 3, 0), + IMX8MN_PAD_SAI2_TXFS__GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_TXFS__PDM_BIT_STREAM2 = IOMUX_PAD(0x0424, 0x01BC, 6, 0x053C, 8, 0), + + IMX8MN_PAD_SAI2_TXC__SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_TXC__SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_TXC__GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_TXC__PDM_BIT_STREAM1 = IOMUX_PAD(0x0428, 0x01C0, 6, 0x0538, 9, 0), + + IMX8MN_PAD_SAI2_TXD0__SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_TXD0__SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_TXD0__GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_TXD0__CCMSRCGPCMIX_BOOT_MODE4 = IOMUX_PAD(0x042C, 0x01C4, 6, 0x0540, 8, 0), + + IMX8MN_PAD_SAI2_MCLK__SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_MCLK__SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x0594, 2, 0), + IMX8MN_PAD_SAI2_MCLK__GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0), + IMX8MN_PAD_SAI2_MCLK__SAI3_MCLK = IOMUX_PAD(0x0430, 0x01C8, 6, 0x05C0, 1, 0), + + IMX8MN_PAD_SAI3_RXFS__SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_RXFS__GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x05F0, 0, 0), + IMX8MN_PAD_SAI3_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0), + IMX8MN_PAD_SAI3_RXFS__SAI3_RX_DATA1 = IOMUX_PAD(0x0434, 0x01CC, 3, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_RXFS__SPDIF1_IN = IOMUX_PAD(0x0434, 0x01CC, 4, 0x05CC, 3, 0), + IMX8MN_PAD_SAI3_RXFS__GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_RXFS__PDM_BIT_STREAM0 = IOMUX_PAD(0x0434, 0x01CC, 6, 0x0534, 5, 0), + + IMX8MN_PAD_SAI3_RXC__SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_RXC__GPT1_CLK = IOMUX_PAD(0x0438, 0x01D0, 1, 0x05E8, 0, 0), + IMX8MN_PAD_SAI3_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0), + IMX8MN_PAD_SAI3_RXC__SAI2_RX_DATA1 = IOMUX_PAD(0x0438, 0x01D0, 3, 0x05AC, 2, 0), + IMX8MN_PAD_SAI3_RXC__UART2_DCE_CTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_RXC__UART2_DTE_RTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x04F8, 2, 0), + IMX8MN_PAD_SAI3_RXC__GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_RXC__PDM_CLK = IOMUX_PAD(0x0438, 0x01D0, 6, 0x0000, 0, 0), + + IMX8MN_PAD_SAI3_RXD__SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_RXD__GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_RXD__SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0), + IMX8MN_PAD_SAI3_RXD__SAI3_TX_DATA1 = IOMUX_PAD(0x043C, 0x01D4, 3, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_RXD__UART2_DCE_RTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x04F8, 3, 0), + IMX8MN_PAD_SAI3_RXD__UART2_DTE_CTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_RXD__GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_RXD__PDM_BIT_STREAM1 = IOMUX_PAD(0x043C, 0x01D4, 6, 0x0538, 10, 0), + + IMX8MN_PAD_SAI3_TXFS__SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_TXFS__GPT1_CAPTURE2 = IOMUX_PAD(0x0440, 0x01D8, 1, 0x05EC, 0, 0), + IMX8MN_PAD_SAI3_TXFS__SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 1, 0), + IMX8MN_PAD_SAI3_TXFS__SAI3_TX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 3, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_TXFS__UART2_DCE_RX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x04FC, 2, 0), + IMX8MN_PAD_SAI3_TXFS__UART2_DTE_TX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_TXFS__GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_TXFS__PDM_BIT_STREAM3 = IOMUX_PAD(0x0440, 0x01D8, 6, 0x0540, 9, 0), + + IMX8MN_PAD_SAI3_TXC__SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_TXC__GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_TXC__SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 1, 0), + IMX8MN_PAD_SAI3_TXC__SAI2_TX_DATA1 = IOMUX_PAD(0x0444, 0x01DC, 3, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_TXC__UART2_DCE_TX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_TXC__UART2_DTE_RX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x04FC, 3, 0), + IMX8MN_PAD_SAI3_TXC__GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_TXC__PDM_BIT_STREAM2 = IOMUX_PAD(0x0444, 0x01DC, 6, 0x053C, 9, 0), + + IMX8MN_PAD_SAI3_TXD__SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_TXD__GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_TXD__SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 1, 0), + IMX8MN_PAD_SAI3_TXD__SPDIF1_EXT_CLK = IOMUX_PAD(0x0448, 0x01E0, 4, 0x0568, 2, 0), + IMX8MN_PAD_SAI3_TXD__GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_TXD__CCMSRCGPCMIX_BOOT_MODE5 = IOMUX_PAD(0x0448, 0x01E0, 6, 0x0000, 0, 0), + + IMX8MN_PAD_SAI3_MCLK__SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x05C0, 0, 0), + IMX8MN_PAD_SAI3_MCLK__PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_MCLK__SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x0594, 3, 0), + IMX8MN_PAD_SAI3_MCLK__SPDIF1_OUT = IOMUX_PAD(0x044C, 0x01E4, 4, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_MCLK__GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0), + IMX8MN_PAD_SAI3_MCLK__SPDIF1_IN = IOMUX_PAD(0x044C, 0x01E4, 6, 0x05CC, 4, 0), + + IMX8MN_PAD_SPDIF_TX__SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0), + IMX8MN_PAD_SPDIF_TX__PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0), + IMX8MN_PAD_SPDIF_TX__GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SPDIF_RX__SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x05CC, 0, 0), + IMX8MN_PAD_SPDIF_RX__PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0), + IMX8MN_PAD_SPDIF_RX__GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0), + + IMX8MN_PAD_SPDIF_EXT_CLK__SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0568, 0, 0), + IMX8MN_PAD_SPDIF_EXT_CLK__PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0), + IMX8MN_PAD_SPDIF_EXT_CLK__GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0), + + IMX8MN_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x05D8, 0, 0), + IMX8MN_PAD_ECSPI1_SCLK__UART3_DCE_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0), + IMX8MN_PAD_ECSPI1_SCLK__UART3_DTE_TX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0000, 0, 0), + IMX8MN_PAD_ECSPI1_SCLK__I2C1_SCL = IOMUX_PAD(0x045C, 0x01F4, 2, 0x055C, 2, 0), + IMX8MN_PAD_ECSPI1_SCLK__SAI5_RX_SYNC = IOMUX_PAD(0x045C, 0x01F4, 3, 0x04DC, 2, 0), + IMX8MN_PAD_ECSPI1_SCLK__GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0), + + IMX8MN_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x05A8, 0, 0), + IMX8MN_PAD_ECSPI1_MOSI__UART3_DCE_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0000, 0, 0), + IMX8MN_PAD_ECSPI1_MOSI__UART3_DTE_RX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0), + IMX8MN_PAD_ECSPI1_MOSI__I2C1_SDA = IOMUX_PAD(0x0460, 0x01F8, 2, 0x056C, 2, 0), + IMX8MN_PAD_ECSPI1_MOSI__SAI5_RX_BCLK = IOMUX_PAD(0x0460, 0x01F8, 3, 0x04D0, 3, 0), + IMX8MN_PAD_ECSPI1_MOSI__GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0), + + IMX8MN_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x05C4, 0, 0), + IMX8MN_PAD_ECSPI1_MISO__UART3_DCE_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0000, 0, 0), + IMX8MN_PAD_ECSPI1_MISO__UART3_DTE_RTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0), + IMX8MN_PAD_ECSPI1_MISO__I2C2_SCL = IOMUX_PAD(0x0464, 0x01FC, 2, 0x05D0, 2, 0), + IMX8MN_PAD_ECSPI1_MISO__SAI5_RX_DATA0 = IOMUX_PAD(0x0464, 0x01FC, 3, 0x04D4, 3, 0), + IMX8MN_PAD_ECSPI1_MISO__GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0), + + IMX8MN_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0564, 0, 0), + IMX8MN_PAD_ECSPI1_SS0__UART3_DCE_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0), + IMX8MN_PAD_ECSPI1_SS0__UART3_DTE_CTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0000, 0, 0), + IMX8MN_PAD_ECSPI1_SS0__I2C2_SDA = IOMUX_PAD(0x0468, 0x0200, 2, 0x0560, 2, 0), + IMX8MN_PAD_ECSPI1_SS0__SAI5_RX_DATA1 = IOMUX_PAD(0x0468, 0x0200, 3, 0x04D8, 2, 0), + IMX8MN_PAD_ECSPI1_SS0__SAI5_TX_SYNC = IOMUX_PAD(0x0468, 0x0200, 4, 0x04EC, 3, 0), + IMX8MN_PAD_ECSPI1_SS0__GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0), + + IMX8MN_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0580, 0, 0), + IMX8MN_PAD_ECSPI2_SCLK__UART4_DCE_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0), + IMX8MN_PAD_ECSPI2_SCLK__UART4_DTE_TX = IOMUX_PAD(0x046C, 0x0204, 1, 0x0000, 0, 0), + IMX8MN_PAD_ECSPI2_SCLK__I2C3_SCL = IOMUX_PAD(0x046C, 0x0204, 2, 0x0588, 4, 0), + IMX8MN_PAD_ECSPI2_SCLK__SAI5_RX_DATA2 = IOMUX_PAD(0x046C, 0x0204, 3, 0x0000, 0, 0), + IMX8MN_PAD_ECSPI2_SCLK__SAI5_TX_BCLK = IOMUX_PAD(0x046C, 0x0204, 4, 0x04E8, 3, 0), + IMX8MN_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0), + + IMX8MN_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0590, 0, 0), + IMX8MN_PAD_ECSPI2_MOSI__UART4_DCE_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0), + IMX8MN_PAD_ECSPI2_MOSI__UART4_DTE_RX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0), + IMX8MN_PAD_ECSPI2_MOSI__I2C3_SDA = IOMUX_PAD(0x0470, 0x0208, 2, 0x05BC, 4, 0), + IMX8MN_PAD_ECSPI2_MOSI__SAI5_RX_DATA3 = IOMUX_PAD(0x0470, 0x0208, 3, 0x04E0, 2, 0), + IMX8MN_PAD_ECSPI2_MOSI__SAI5_TX_DATA0 = IOMUX_PAD(0x0470, 0x0208, 4, 0x0000, 0, 0), + IMX8MN_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0), + + IMX8MN_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0578, 0, 0), + IMX8MN_PAD_ECSPI2_MISO__UART4_DCE_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0000, 0, 0), + IMX8MN_PAD_ECSPI2_MISO__UART4_DTE_RTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0), + IMX8MN_PAD_ECSPI2_MISO__I2C4_SCL = IOMUX_PAD(0x0474, 0x020C, 2, 0x05D4, 3, 0), + IMX8MN_PAD_ECSPI2_MISO__SAI5_MCLK = IOMUX_PAD(0x0474, 0x020C, 3, 0x0594, 4, 0), + IMX8MN_PAD_ECSPI2_MISO__GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0), + + IMX8MN_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0570, 0, 0), + IMX8MN_PAD_ECSPI2_SS0__UART4_DCE_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0), + IMX8MN_PAD_ECSPI2_SS0__UART4_DTE_CTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0000, 0, 0), + IMX8MN_PAD_ECSPI2_SS0__I2C4_SDA = IOMUX_PAD(0x0478, 0x0210, 2, 0x058C, 5, 0), + IMX8MN_PAD_ECSPI2_SS0__GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0), + + IMX8MN_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, 0 | IOMUX_CONFIG_SION, 0x055C, 0, 0), + IMX8MN_PAD_I2C1_SCL__ENET1_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0), + IMX8MN_PAD_I2C1_SCL__ECSPI1_SCLK = IOMUX_PAD(0x047C, 0x0214, 3, 0x05D8, 1, 0), + IMX8MN_PAD_I2C1_SCL__GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0), + + IMX8MN_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, 0 | IOMUX_CONFIG_SION, 0x056C, 0, 0), + IMX8MN_PAD_I2C1_SDA__ENET1_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0), + IMX8MN_PAD_I2C1_SDA__ECSPI1_MOSI = IOMUX_PAD(0x0480, 0x0218, 3, 0x05A8, 1, 0), + IMX8MN_PAD_I2C1_SDA__GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0), + + IMX8MN_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0, 0x05D0, 0, 0), + IMX8MN_PAD_I2C2_SCL__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0), + IMX8MN_PAD_I2C2_SCL__USDHC3_CD_B = IOMUX_PAD(0x0484, 0x021C, 2, 0x0598, 1, 0), + IMX8MN_PAD_I2C2_SCL__ECSPI1_MISO = IOMUX_PAD(0x0484, 0x021C, 3, 0x05C4, 1, 0), + IMX8MN_PAD_I2C2_SCL__GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0), + + IMX8MN_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0, 0x0560, 0, 0), + IMX8MN_PAD_I2C2_SDA__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0), + IMX8MN_PAD_I2C2_SDA__USDHC3_WP = IOMUX_PAD(0x0488, 0x0220, 2, 0x05B8, 1, 0), + IMX8MN_PAD_I2C2_SDA__ECSPI1_SS0 = IOMUX_PAD(0x0488, 0x0220, 3, 0x0564, 1, 0), + IMX8MN_PAD_I2C2_SDA__GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0), + + IMX8MN_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, 0, 0x0588, 0, 0), + IMX8MN_PAD_I2C3_SCL__PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0), + IMX8MN_PAD_I2C3_SCL__GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0), + IMX8MN_PAD_I2C3_SCL__ECSPI2_SCLK = IOMUX_PAD(0x048C, 0x0224, 3, 0x0580, 2, 0), + IMX8MN_PAD_I2C3_SCL__GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0), + + IMX8MN_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, 0, 0x05BC, 0, 0), + IMX8MN_PAD_I2C3_SDA__PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0), + IMX8MN_PAD_I2C3_SDA__GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0), + IMX8MN_PAD_I2C3_SDA__ECSPI2_MOSI = IOMUX_PAD(0x0490, 0x0228, 3, 0x0590, 2, 0), + IMX8MN_PAD_I2C3_SDA__GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0), + + IMX8MN_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, 0, 0x05D4, 0, 0), + IMX8MN_PAD_I2C4_SCL__PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0), + IMX8MN_PAD_I2C4_SCL__ECSPI2_MISO = IOMUX_PAD(0x0494, 0x022C, 3, 0x0578, 2, 0), + IMX8MN_PAD_I2C4_SCL__GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0), + + IMX8MN_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, 0, 0x058C, 0, 0), + IMX8MN_PAD_I2C4_SDA__PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0), + IMX8MN_PAD_I2C4_SDA__ECSPI2_SS0 = IOMUX_PAD(0x0498, 0x0230, 3, 0x0570, 1, 0), + IMX8MN_PAD_I2C4_SDA__GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0), + + IMX8MN_PAD_UART1_RXD__UART1_DCE_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0), + IMX8MN_PAD_UART1_RXD__UART1_DTE_TX = IOMUX_PAD(0x049C, 0x0234, 0, 0x0000, 0, 0), + IMX8MN_PAD_UART1_RXD__ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0), + IMX8MN_PAD_UART1_RXD__GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0), + + IMX8MN_PAD_UART1_TXD__UART1_DCE_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0), + IMX8MN_PAD_UART1_TXD__UART1_DTE_RX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x04F4, 1, 0), + IMX8MN_PAD_UART1_TXD__ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0), + IMX8MN_PAD_UART1_TXD__GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0), + + IMX8MN_PAD_UART2_RXD__UART2_DCE_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0), + IMX8MN_PAD_UART2_RXD__UART2_DTE_TX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x0000, 0, 0), + IMX8MN_PAD_UART2_RXD__ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0), + IMX8MN_PAD_UART2_RXD__GPT1_COMPARE3 = IOMUX_PAD(0x04A4, 0x023C, 3, 0x0000, 0, 0), + IMX8MN_PAD_UART2_RXD__GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0), + + IMX8MN_PAD_UART2_TXD__UART2_DCE_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0), + IMX8MN_PAD_UART2_TXD__UART2_DTE_RX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x04FC, 1, 0), + IMX8MN_PAD_UART2_TXD__ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0), + IMX8MN_PAD_UART2_TXD__GPT1_COMPARE2 = IOMUX_PAD(0x04A8, 0x0240, 3, 0x0000, 0, 0), + IMX8MN_PAD_UART2_TXD__GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0), + + IMX8MN_PAD_UART3_RXD__UART3_DCE_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0), + IMX8MN_PAD_UART3_RXD__UART3_DTE_TX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0000, 0, 0), + IMX8MN_PAD_UART3_RXD__UART1_DCE_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x0000, 0, 0), + IMX8MN_PAD_UART3_RXD__UART1_DTE_RTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0), + IMX8MN_PAD_UART3_RXD__USDHC3_RESET_B = IOMUX_PAD(0x04AC, 0x0244, 2, 0x0000, 0, 0), + IMX8MN_PAD_UART3_RXD__GPT1_CAPTURE2 = IOMUX_PAD(0x04AC, 0x0244, 3, 0x05EC, 1, 0), + IMX8MN_PAD_UART3_RXD__GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0), + + IMX8MN_PAD_UART3_TXD__UART3_DCE_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0), + IMX8MN_PAD_UART3_TXD__UART3_DTE_RX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0504, 3, 0), + IMX8MN_PAD_UART3_TXD__UART1_DCE_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0), + IMX8MN_PAD_UART3_TXD__UART1_DTE_CTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x0000, 0, 0), + IMX8MN_PAD_UART3_TXD__USDHC3_VSELECT = IOMUX_PAD(0x04B0, 0x0248, 2, 0x0000, 0, 0), + IMX8MN_PAD_UART3_TXD__GPT1_CLK = IOMUX_PAD(0x04B0, 0x0248, 3, 0x05E8, 1, 0), + IMX8MN_PAD_UART3_TXD__GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0), + + IMX8MN_PAD_UART4_RXD__UART4_DCE_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0), + IMX8MN_PAD_UART4_RXD__UART4_DTE_TX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x0000, 0, 0), + IMX8MN_PAD_UART4_RXD__UART2_DCE_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x0000, 0, 0), + IMX8MN_PAD_UART4_RXD__UART2_DTE_RTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0), + IMX8MN_PAD_UART4_RXD__GPT1_COMPARE1 = IOMUX_PAD(0x04B4, 0x024C, 3, 0x0000, 0, 0), + IMX8MN_PAD_UART4_RXD__GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0), + + IMX8MN_PAD_UART4_TXD__UART4_DCE_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0), + IMX8MN_PAD_UART4_TXD__UART4_DTE_RX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x050C, 3, 0), + IMX8MN_PAD_UART4_TXD__UART2_DCE_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0), + IMX8MN_PAD_UART4_TXD__UART2_DTE_CTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x0000, 0, 0), + IMX8MN_PAD_UART4_TXD__GPT1_CAPTURE1 = IOMUX_PAD(0x04B8, 0x0250, 3, 0x05F0, 1, 0), + IMX8MN_PAD_UART4_TXD__GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0), +}; +#endif /* __ASM_ARCH_IMX8MN_PINS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8m/imx8mp_pins.h b/roms/u-boot/arch/arm/include/asm/arch-imx8m/imx8mp_pins.h new file mode 100644 index 000000000..e7f322182 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8m/imx8mp_pins.h @@ -0,0 +1,1080 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __ASM_ARCH_IMX8MP_PINS_H__ +#define __ASM_ARCH_IMX8MP_PINS_H__ + +#include + +enum { + MX8MP_PAD_GPIO1_IO00__GPIO1_IO00 = IOMUX_PAD(0x0274, 0x0014, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0274, 0x0014, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO00__MEDIAMIX_ISP_FL_TRIG_0 = IOMUX_PAD(0x0274, 0x0014, 3, 0x05D4, 0, 0), + MX8MP_PAD_GPIO1_IO00__ANAMIX_REF_CLK_32K = IOMUX_PAD(0x0274, 0x0014, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO00__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x0274, 0x0014, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO00__SJC_FAIL = IOMUX_PAD(0x0274, 0x0014, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO01__GPIO1_IO01 = IOMUX_PAD(0x0278, 0x0018, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0278, 0x0018, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO01__MEDIAMIX_ISP_SHUTTER_TRIG_0 = IOMUX_PAD(0x0278, 0x0018, 3, 0x05DC, 0, 0), + MX8MP_PAD_GPIO1_IO01__ANAMIX_REF_CLK_24M = IOMUX_PAD(0x0278, 0x0018, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO01__CCMSRCGPCMIX_EXT_CLK2 = IOMUX_PAD(0x0278, 0x0018, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO01__SJC_ACTIVE = IOMUX_PAD(0x0278, 0x0018, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO02__GPIO1_IO02 = IOMUX_PAD(0x027C, 0x001C, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x027C, 0x001C, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO02__MEDIAMIX_ISP_FLASH_TRIG_0 = IOMUX_PAD(0x027C, 0x001C, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_ANY = IOMUX_PAD(0x027C, 0x001C, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO02__SJC_DE_B = IOMUX_PAD(0x027C, 0x001C, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO03__GPIO1_IO03 = IOMUX_PAD(0x0280, 0x0020, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__USDHC1_VSELECT = IOMUX_PAD(0x0280, 0x0020, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__MEDIAMIX_ISP_PRELIGHT_TRIG_0 = IOMUX_PAD(0x0280, 0x0020, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__SDMA1_EXT_EVENT00 = IOMUX_PAD(0x0280, 0x0020, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__ANAMIX_XTAL_OK = IOMUX_PAD(0x0280, 0x0020, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__SJC_DONE = IOMUX_PAD(0x0280, 0x0020, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO04__GPIO1_IO04 = IOMUX_PAD(0x0284, 0x0024, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__USDHC2_VSELECT = IOMUX_PAD(0x0284, 0x0024, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__MEDIAMIX_ISP_SHUTTER_OPEN_0 = IOMUX_PAD(0x0284, 0x0024, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__SDMA1_EXT_EVENT01 = IOMUX_PAD(0x0284, 0x0024, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__ANAMIX_XTAL_OK_LV = IOMUX_PAD(0x0284, 0x0024, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__USDHC1_TEST_TRIG = IOMUX_PAD(0x0284, 0x0024, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO05__GPIO1_IO05 = IOMUX_PAD(0x0288, 0x0028, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO05__M7_NMI = IOMUX_PAD(0x0288, 0x0028, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO05__MEDIAMIX_ISP_FL_TRIG_1 = IOMUX_PAD(0x0288, 0x0028, 3, 0x05D8, 0, 0), + MX8MP_PAD_GPIO1_IO05__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x0288, 0x0028, 5, 0x0554, 0, 0), + MX8MP_PAD_GPIO1_IO05__CCMSRCGPCMIX_INT_BOOT = IOMUX_PAD(0x0288, 0x0028, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO05__USDHC2_TEST_TRIG = IOMUX_PAD(0x0288, 0x0028, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO06__GPIO1_IO06 = IOMUX_PAD(0x028C, 0x002C, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO06__ENET_QOS_MDC = IOMUX_PAD(0x028C, 0x002C, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO06__MEDIAMIX_ISP_SHUTTER_TRIG_1 = IOMUX_PAD(0x028C, 0x002C, 3, 0x05E0, 0, 0), + MX8MP_PAD_GPIO1_IO06__USDHC1_CD_B = IOMUX_PAD(0x028C, 0x002C, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO06__CCMSRCGPCMIX_EXT_CLK3 = IOMUX_PAD(0x028C, 0x002C, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO06__ECSPI1_TEST_TRIG = IOMUX_PAD(0x028C, 0x002C, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO07__GPIO1_IO07 = IOMUX_PAD(0x0290, 0x0030, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO07__ENET_QOS_MDIO = IOMUX_PAD(0x0290, 0x0030, 1, 0x0590, 0, 0), + MX8MP_PAD_GPIO1_IO07__MEDIAMIX_ISP_FLASH_TRIG_1 = IOMUX_PAD(0x0290, 0x0030, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO07__USDHC1_WP = IOMUX_PAD(0x0290, 0x0030, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO07__CCMSRCGPCMIX_EXT_CLK4 = IOMUX_PAD(0x0290, 0x0030, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO07__ECSPI2_TEST_TRIG = IOMUX_PAD(0x0290, 0x0030, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO08__GPIO1_IO08 = IOMUX_PAD(0x0294, 0x0034, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN = IOMUX_PAD(0x0294, 0x0034, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x0294, 0x0034, 2, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__MEDIAMIX_ISP_PRELIGHT_TRIG_1 = IOMUX_PAD(0x0294, 0x0034, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN = IOMUX_PAD(0x0294, 0x0034, 4, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__USDHC2_RESET_B = IOMUX_PAD(0x0294, 0x0034, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x0294, 0x0034, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__FLEXSPI_TEST_TRIG = IOMUX_PAD(0x0294, 0x0034, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO09__GPIO1_IO09 = IOMUX_PAD(0x0298, 0x0038, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT = IOMUX_PAD(0x0298, 0x0038, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x0298, 0x0038, 2, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__MEDIAMIX_ISP_SHUTTER_OPEN_1 = IOMUX_PAD(0x0298, 0x0038, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__USDHC3_RESET_B = IOMUX_PAD(0x0298, 0x0038, 4, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__AUDIOMIX_EXT_EVENT00 = IOMUX_PAD(0x0298, 0x0038, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x0298, 0x0038, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__RAWNAND_TEST_TRIG = IOMUX_PAD(0x0298, 0x0038, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x029C, 0x003C, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO10__HSIOMIX_usb1_OTG_ID = IOMUX_PAD(0x029C, 0x003C, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO10__PWM3_OUT = IOMUX_PAD(0x029C, 0x003C, 2, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO10__OCOTP_FUSE_LATCHED = IOMUX_PAD(0x029C, 0x003C, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x02A0, 0x0040, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__HSIOMIX_usb2_OTG_ID = IOMUX_PAD(0x02A0, 0x0040, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__PWM2_OUT = IOMUX_PAD(0x02A0, 0x0040, 2, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__USDHC3_VSELECT = IOMUX_PAD(0x02A0, 0x0040, 4, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x02A0, 0x0040, 5, 0x0554, 1, 0), + MX8MP_PAD_GPIO1_IO11__CCMSRCGPCMIX_OUT0 = IOMUX_PAD(0x02A0, 0x0040, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x02A0, 0x0040, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x02A4, 0x0044, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO12__HSIOMIX_usb1_OTG_PWR = IOMUX_PAD(0x02A4, 0x0044, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO12__AUDIOMIX_EXT_EVENT01 = IOMUX_PAD(0x02A4, 0x0044, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO12__CCMSRCGPCMIX_OUT1 = IOMUX_PAD(0x02A4, 0x0044, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT00 = IOMUX_PAD(0x02A4, 0x0044, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x02A8, 0x0048, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO13__HSIOMIX_usb1_OTG_OC = IOMUX_PAD(0x02A8, 0x0048, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO13__PWM2_OUT = IOMUX_PAD(0x02A8, 0x0048, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO13__CCMSRCGPCMIX_OUT2 = IOMUX_PAD(0x02A8, 0x0048, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT01 = IOMUX_PAD(0x02A8, 0x0048, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x02AC, 0x004C, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO14__HSIOMIX_usb2_OTG_PWR = IOMUX_PAD(0x02AC, 0x004C, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO14__USDHC3_CD_B = IOMUX_PAD(0x02AC, 0x004C, 4, 0x0608, 0, 0), + MX8MP_PAD_GPIO1_IO14__PWM3_OUT = IOMUX_PAD(0x02AC, 0x004C, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO14__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x02AC, 0x004C, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT02 = IOMUX_PAD(0x02AC, 0x004C, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x02B0, 0x0050, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO15__HSIOMIX_usb2_OTG_OC = IOMUX_PAD(0x02B0, 0x0050, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO15__USDHC3_WP = IOMUX_PAD(0x02B0, 0x0050, 4, 0x0634, 0, 0), + MX8MP_PAD_GPIO1_IO15__PWM4_OUT = IOMUX_PAD(0x02B0, 0x0050, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO15__CCMSRCGPCMIX_CLKO2 = IOMUX_PAD(0x02B0, 0x0050, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO15__CSU_CSU_INT_DEB = IOMUX_PAD(0x02B0, 0x0050, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_MDC__ENET_QOS_MDC = IOMUX_PAD(0x02B4, 0x0054, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00 = IOMUX_PAD(0x02B4, 0x0054, 2, 0x0000, 0, 0), + MX8MP_PAD_ENET_MDC__GPIO1_IO16 = IOMUX_PAD(0x02B4, 0x0054, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_MDC__USDHC3_STROBE = IOMUX_PAD(0x02B4, 0x0054, 6, 0x0630, 0, 0), + MX8MP_PAD_ENET_MDC__SIM_M_HADDR15 = IOMUX_PAD(0x02B4, 0x0054, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_MDIO__ENET_QOS_MDIO = IOMUX_PAD(0x02B8, 0x0058, 0, 0x0590, 1, 0), + MX8MP_PAD_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC = IOMUX_PAD(0x02B8, 0x0058, 2, 0x0528, 0, 0), + MX8MP_PAD_ENET_MDIO__GPIO1_IO17 = IOMUX_PAD(0x02B8, 0x0058, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_MDIO__USDHC3_DATA5 = IOMUX_PAD(0x02B8, 0x0058, 6, 0x0624, 0, 0), + MX8MP_PAD_ENET_MDIO__SIM_M_HADDR16 = IOMUX_PAD(0x02B8, 0x0058, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TD3__ENET_QOS_RGMII_TD3 = IOMUX_PAD(0x02BC, 0x005C, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK = IOMUX_PAD(0x02BC, 0x005C, 2, 0x0524, 0, 0), + MX8MP_PAD_ENET_TD3__GPIO1_IO18 = IOMUX_PAD(0x02BC, 0x005C, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD3__USDHC3_DATA6 = IOMUX_PAD(0x02BC, 0x005C, 6, 0x0628, 0, 0), + MX8MP_PAD_ENET_TD3__SIM_M_HADDR17 = IOMUX_PAD(0x02BC, 0x005C, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TD2__ENET_QOS_RGMII_TD2 = IOMUX_PAD(0x02C0, 0x0060, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK = IOMUX_PAD(0x02C0, 0x0060, 1, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00 = IOMUX_PAD(0x02C0, 0x0060, 2, 0x051C, 0, 0), + MX8MP_PAD_ENET_TD2__GPIO1_IO19 = IOMUX_PAD(0x02C0, 0x0060, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD2__USDHC3_DATA7 = IOMUX_PAD(0x02C0, 0x0060, 6, 0x062C, 0, 0), + MX8MP_PAD_ENET_TD2__SIM_M_HADDR18 = IOMUX_PAD(0x02C0, 0x0060, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TD1__ENET_QOS_RGMII_TD1 = IOMUX_PAD(0x02C4, 0x0064, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC = IOMUX_PAD(0x02C4, 0x0064, 2, 0x0520, 0, 0), + MX8MP_PAD_ENET_TD1__GPIO1_IO20 = IOMUX_PAD(0x02C4, 0x0064, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD1__USDHC3_CD_B = IOMUX_PAD(0x02C4, 0x0064, 6, 0x0608, 1, 0), + MX8MP_PAD_ENET_TD1__SIM_M_HADDR19 = IOMUX_PAD(0x02C4, 0x0064, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TD0__ENET_QOS_RGMII_TD0 = IOMUX_PAD(0x02C8, 0x0068, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK = IOMUX_PAD(0x02C8, 0x0068, 2, 0x0518, 0, 0), + MX8MP_PAD_ENET_TD0__GPIO1_IO21 = IOMUX_PAD(0x02C8, 0x0068, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD0__USDHC3_WP = IOMUX_PAD(0x02C8, 0x0068, 6, 0x0634, 1, 0), + MX8MP_PAD_ENET_TD0__SIM_M_HADDR20 = IOMUX_PAD(0x02C8, 0x0068, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL = IOMUX_PAD(0x02CC, 0x006C, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK = IOMUX_PAD(0x02CC, 0x006C, 2, 0x0514, 0, 0), + MX8MP_PAD_ENET_TX_CTL__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x02CC, 0x006C, 3, 0x0000, 0, 0), + MX8MP_PAD_ENET_TX_CTL__GPIO1_IO22 = IOMUX_PAD(0x02CC, 0x006C, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TX_CTL__USDHC3_DATA0 = IOMUX_PAD(0x02CC, 0x006C, 6, 0x0610, 0, 0), + MX8MP_PAD_ENET_TX_CTL__SIM_M_HADDR21 = IOMUX_PAD(0x02CC, 0x006C, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK = IOMUX_PAD(0x02D0, 0x0070, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TXC__ENET_QOS_TX_ER = IOMUX_PAD(0x02D0, 0x0070, 1, 0x0000, 0, 0), + MX8MP_PAD_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00 = IOMUX_PAD(0x02D0, 0x0070, 2, 0x0000, 0, 0), + MX8MP_PAD_ENET_TXC__GPIO1_IO23 = IOMUX_PAD(0x02D0, 0x0070, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TXC__USDHC3_DATA1 = IOMUX_PAD(0x02D0, 0x0070, 6, 0x0614, 0, 0), + MX8MP_PAD_ENET_TXC__SIM_M_HADDR22 = IOMUX_PAD(0x02D0, 0x0070, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL = IOMUX_PAD(0x02D4, 0x0074, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC = IOMUX_PAD(0x02D4, 0x0074, 2, 0x0540, 0, 0), + MX8MP_PAD_ENET_RX_CTL__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x02D4, 0x0074, 3, 0x04CC, 0, 0), + MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24 = IOMUX_PAD(0x02D4, 0x0074, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RX_CTL__USDHC3_DATA2 = IOMUX_PAD(0x02D4, 0x0074, 6, 0x0618, 0, 0), + MX8MP_PAD_ENET_RX_CTL__SIM_M_HADDR23 = IOMUX_PAD(0x02D4, 0x0074, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK = IOMUX_PAD(0x02D8, 0x0078, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RXC__ENET_QOS_RX_ER = IOMUX_PAD(0x02D8, 0x0078, 1, 0x0000, 0, 0), + MX8MP_PAD_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK = IOMUX_PAD(0x02D8, 0x0078, 2, 0x053C, 0, 0), + MX8MP_PAD_ENET_RXC__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x02D8, 0x0078, 3, 0x04C8, 0, 0), + MX8MP_PAD_ENET_RXC__GPIO1_IO25 = IOMUX_PAD(0x02D8, 0x0078, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RXC__USDHC3_DATA3 = IOMUX_PAD(0x02D8, 0x0078, 6, 0x061C, 0, 0), + MX8MP_PAD_ENET_RXC__SIM_M_HADDR24 = IOMUX_PAD(0x02D8, 0x0078, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RD0__ENET_QOS_RGMII_RD0 = IOMUX_PAD(0x02DC, 0x007C, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00 = IOMUX_PAD(0x02DC, 0x007C, 2, 0x0534, 0, 0), + MX8MP_PAD_ENET_RD0__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x02DC, 0x007C, 3, 0x04C4, 0, 0), + MX8MP_PAD_ENET_RD0__GPIO1_IO26 = IOMUX_PAD(0x02DC, 0x007C, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD0__USDHC3_DATA4 = IOMUX_PAD(0x02DC, 0x007C, 6, 0x0620, 0, 0), + MX8MP_PAD_ENET_RD0__SIM_M_HADDR25 = IOMUX_PAD(0x02DC, 0x007C, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RD1__ENET_QOS_RGMII_RD1 = IOMUX_PAD(0x02E0, 0x0080, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC = IOMUX_PAD(0x02E0, 0x0080, 2, 0x0538, 0, 0), + MX8MP_PAD_ENET_RD1__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x02E0, 0x0080, 3, 0x04C0, 0, 0), + MX8MP_PAD_ENET_RD1__GPIO1_IO27 = IOMUX_PAD(0x02E0, 0x0080, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD1__USDHC3_RESET_B = IOMUX_PAD(0x02E0, 0x0080, 6, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD1__SIM_M_HADDR26 = IOMUX_PAD(0x02E0, 0x0080, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RD2__ENET_QOS_RGMII_RD2 = IOMUX_PAD(0x02E4, 0x0084, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK = IOMUX_PAD(0x02E4, 0x0084, 2, 0x0530, 0, 0), + MX8MP_PAD_ENET_RD2__AUDIOMIX_CLK = IOMUX_PAD(0x02E4, 0x0084, 3, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD2__GPIO1_IO28 = IOMUX_PAD(0x02E4, 0x0084, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD2__USDHC3_CLK = IOMUX_PAD(0x02E4, 0x0084, 6, 0x0604, 0, 0), + MX8MP_PAD_ENET_RD2__SIM_M_HADDR27 = IOMUX_PAD(0x02E4, 0x0084, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RD3__ENET_QOS_RGMII_RD3 = IOMUX_PAD(0x02E8, 0x0088, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD3__AUDIOMIX_SAI7_MCLK = IOMUX_PAD(0x02E8, 0x0088, 2, 0x052C, 0, 0), + MX8MP_PAD_ENET_RD3__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x02E8, 0x0088, 3, 0x0544, 0, 0), + MX8MP_PAD_ENET_RD3__GPIO1_IO29 = IOMUX_PAD(0x02E8, 0x0088, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD3__USDHC3_CMD = IOMUX_PAD(0x02E8, 0x0088, 6, 0x060C, 0, 0), + MX8MP_PAD_ENET_RD3__SIM_M_HADDR28 = IOMUX_PAD(0x02E8, 0x0088, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x02EC, 0x008C, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_CLK__ENET1_MDC = IOMUX_PAD(0x02EC, 0x008C, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_CLK__I2C5_SCL = IOMUX_PAD(0x02EC, 0x008C, 3 | IOMUX_CONFIG_SION, 0x05C4, 0, 0), + MX8MP_PAD_SD1_CLK__UART1_DCE_TX = IOMUX_PAD(0x02EC, 0x008C, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_CLK__UART1_DTE_RX = IOMUX_PAD(0x02EC, 0x008C, 4, 0x05E8, 0, 0), + MX8MP_PAD_SD1_CLK__GPIO2_IO00 = IOMUX_PAD(0x02EC, 0x008C, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_CLK__SIM_M_HADDR29 = IOMUX_PAD(0x02EC, 0x008C, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x02F0, 0x0090, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_CMD__ENET1_MDIO = IOMUX_PAD(0x02F0, 0x0090, 1, 0x057C, 0, 0), + MX8MP_PAD_SD1_CMD__I2C5_SDA = IOMUX_PAD(0x02F0, 0x0090, 3 | IOMUX_CONFIG_SION, 0x05C8, 0, 0), + MX8MP_PAD_SD1_CMD__UART1_DCE_RX = IOMUX_PAD(0x02F0, 0x0090, 4, 0x05E8, 1, 0), + MX8MP_PAD_SD1_CMD__UART1_DTE_TX = IOMUX_PAD(0x02F0, 0x0090, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_CMD__GPIO2_IO01 = IOMUX_PAD(0x02F0, 0x0090, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_CMD__SIM_M_HADDR30 = IOMUX_PAD(0x02F0, 0x0090, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x02F4, 0x0094, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA0__ENET1_RGMII_TD1 = IOMUX_PAD(0x02F4, 0x0094, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA0__I2C6_SCL = IOMUX_PAD(0x02F4, 0x0094, 3 | IOMUX_CONFIG_SION, 0x05CC, 0, 0), + MX8MP_PAD_SD1_DATA0__UART1_DCE_RTS = IOMUX_PAD(0x02F4, 0x0094, 4, 0x05E4, 0, 0), + MX8MP_PAD_SD1_DATA0__UART1_DTE_CTS = IOMUX_PAD(0x02F4, 0x0094, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA0__GPIO2_IO02 = IOMUX_PAD(0x02F4, 0x0094, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA0__SIM_M_HADDR31 = IOMUX_PAD(0x02F4, 0x0094, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x02F8, 0x0098, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA1__ENET1_RGMII_TD0 = IOMUX_PAD(0x02F8, 0x0098, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA1__I2C6_SDA = IOMUX_PAD(0x02F8, 0x0098, 3 | IOMUX_CONFIG_SION, 0x05D0, 0, 0), + MX8MP_PAD_SD1_DATA1__UART1_DCE_CTS = IOMUX_PAD(0x02F8, 0x0098, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA1__UART1_DTE_RTS = IOMUX_PAD(0x02F8, 0x0098, 4, 0x05E4, 1, 0), + MX8MP_PAD_SD1_DATA1__GPIO2_IO03 = IOMUX_PAD(0x02F8, 0x0098, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA1__SIM_M_HBURST00 = IOMUX_PAD(0x02F8, 0x0098, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x02FC, 0x009C, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA2__ENET1_RGMII_RD0 = IOMUX_PAD(0x02FC, 0x009C, 1, 0x0580, 0, 0), + MX8MP_PAD_SD1_DATA2__I2C4_SCL = IOMUX_PAD(0x02FC, 0x009C, 3 | IOMUX_CONFIG_SION, 0x05BC, 0, 0), + MX8MP_PAD_SD1_DATA2__UART2_DCE_TX = IOMUX_PAD(0x02FC, 0x009C, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA2__UART2_DTE_RX = IOMUX_PAD(0x02FC, 0x009C, 4, 0x05F0, 0, 0), + MX8MP_PAD_SD1_DATA2__GPIO2_IO04 = IOMUX_PAD(0x02FC, 0x009C, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA2__SIM_M_HBURST01 = IOMUX_PAD(0x02FC, 0x009C, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x0300, 0x00A0, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA3__ENET1_RGMII_RD1 = IOMUX_PAD(0x0300, 0x00A0, 1, 0x0584, 0, 0), + MX8MP_PAD_SD1_DATA3__I2C4_SDA = IOMUX_PAD(0x0300, 0x00A0, 3 | IOMUX_CONFIG_SION, 0x05C0, 0, 0), + MX8MP_PAD_SD1_DATA3__UART2_DCE_RX = IOMUX_PAD(0x0300, 0x00A0, 4, 0x05F0, 1, 0), + MX8MP_PAD_SD1_DATA3__UART2_DTE_TX = IOMUX_PAD(0x0300, 0x00A0, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA3__GPIO2_IO05 = IOMUX_PAD(0x0300, 0x00A0, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA3__SIM_M_HBURST02 = IOMUX_PAD(0x0300, 0x00A0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x0304, 0x00A4, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA4__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x0304, 0x00A4, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA4__I2C1_SCL = IOMUX_PAD(0x0304, 0x00A4, 3 | IOMUX_CONFIG_SION, 0x05A4, 0, 0), + MX8MP_PAD_SD1_DATA4__UART2_DCE_RTS = IOMUX_PAD(0x0304, 0x00A4, 4, 0x05EC, 0, 0), + MX8MP_PAD_SD1_DATA4__UART2_DTE_CTS = IOMUX_PAD(0x0304, 0x00A4, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA4__GPIO2_IO06 = IOMUX_PAD(0x0304, 0x00A4, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA4__SIM_M_HRESP = IOMUX_PAD(0x0304, 0x00A4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x0308, 0x00A8, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA5__ENET1_TX_ER = IOMUX_PAD(0x0308, 0x00A8, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA5__I2C1_SDA = IOMUX_PAD(0x0308, 0x00A8, 3 | IOMUX_CONFIG_SION, 0x05A8, 0, 0), + MX8MP_PAD_SD1_DATA5__UART2_DCE_CTS = IOMUX_PAD(0x0308, 0x00A8, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA5__UART2_DTE_RTS = IOMUX_PAD(0x0308, 0x00A8, 4, 0x05EC, 1, 0), + MX8MP_PAD_SD1_DATA5__GPIO2_IO07 = IOMUX_PAD(0x0308, 0x00A8, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA5__TPSMP_HDATA05 = IOMUX_PAD(0x0308, 0x00A8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x030C, 0x00AC, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA6__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x030C, 0x00AC, 1, 0x0588, 0, 0), + MX8MP_PAD_SD1_DATA6__I2C2_SCL = IOMUX_PAD(0x030C, 0x00AC, 3 | IOMUX_CONFIG_SION, 0x05AC, 0, 0), + MX8MP_PAD_SD1_DATA6__UART3_DCE_TX = IOMUX_PAD(0x030C, 0x00AC, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA6__UART3_DTE_RX = IOMUX_PAD(0x030C, 0x00AC, 4, 0x05F8, 0, 0), + MX8MP_PAD_SD1_DATA6__GPIO2_IO08 = IOMUX_PAD(0x030C, 0x00AC, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA6__TPSMP_HDATA06 = IOMUX_PAD(0x030C, 0x00AC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x0310, 0x00B0, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA7__ENET1_RX_ER = IOMUX_PAD(0x0310, 0x00B0, 1, 0x058C, 0, 0), + MX8MP_PAD_SD1_DATA7__I2C2_SDA = IOMUX_PAD(0x0310, 0x00B0, 3 | IOMUX_CONFIG_SION, 0x05B0, 0, 0), + MX8MP_PAD_SD1_DATA7__UART3_DCE_RX = IOMUX_PAD(0x0310, 0x00B0, 4, 0x05F8, 1, 0), + MX8MP_PAD_SD1_DATA7__UART3_DTE_TX = IOMUX_PAD(0x0310, 0x00B0, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA7__GPIO2_IO09 = IOMUX_PAD(0x0310, 0x00B0, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA7__TPSMP_HDATA07 = IOMUX_PAD(0x0310, 0x00B0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_RESET_B__USDHC1_RESET_B = IOMUX_PAD(0x0314, 0x00B4, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_RESET_B__ENET1_TX_CLK = IOMUX_PAD(0x0314, 0x00B4, 1, 0x0578, 0, 0), + MX8MP_PAD_SD1_RESET_B__I2C3_SCL = IOMUX_PAD(0x0314, 0x00B4, 3 | IOMUX_CONFIG_SION, 0x05B4, 0, 0), + MX8MP_PAD_SD1_RESET_B__UART3_DCE_RTS = IOMUX_PAD(0x0314, 0x00B4, 4, 0x05F4, 0, 0), + MX8MP_PAD_SD1_RESET_B__UART3_DTE_CTS = IOMUX_PAD(0x0314, 0x00B4, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_RESET_B__GPIO2_IO10 = IOMUX_PAD(0x0314, 0x00B4, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_RESET_B__ECSPI3_TEST_TRIG = IOMUX_PAD(0x0314, 0x00B4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x0318, 0x00B8, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_STROBE__I2C3_SDA = IOMUX_PAD(0x0318, 0x00B8, 3 | IOMUX_CONFIG_SION, 0x05B8, 0, 0), + MX8MP_PAD_SD1_STROBE__UART3_DCE_CTS = IOMUX_PAD(0x0318, 0x00B8, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_STROBE__UART3_DTE_RTS = IOMUX_PAD(0x0318, 0x00B8, 4, 0x05F4, 1, 0), + MX8MP_PAD_SD1_STROBE__GPIO2_IO11 = IOMUX_PAD(0x0318, 0x00B8, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_STROBE__USDHC3_TEST_TRIG = IOMUX_PAD(0x0318, 0x00B8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x031C, 0x00BC, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_CD_B__GPIO2_IO12 = IOMUX_PAD(0x031C, 0x00BC, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK = IOMUX_PAD(0x031C, 0x00BC, 6, 0x0000, 0, 0), + + MX8MP_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x0320, 0x00C0, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_CLK__ECSPI2_SCLK = IOMUX_PAD(0x0320, 0x00C0, 2, 0x0568, 0, 0), + MX8MP_PAD_SD2_CLK__UART4_DCE_RX = IOMUX_PAD(0x0320, 0x00C0, 3, 0x0600, 0, 0), + MX8MP_PAD_SD2_CLK__UART4_DTE_TX = IOMUX_PAD(0x0320, 0x00C0, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_CLK__GPIO2_IO13 = IOMUX_PAD(0x0320, 0x00C0, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 = IOMUX_PAD(0x0320, 0x00C0, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_CLK__OBSERVE_MUX_OUT00 = IOMUX_PAD(0x0320, 0x00C0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0324, 0x00C4, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__ECSPI2_MOSI = IOMUX_PAD(0x0324, 0x00C4, 2, 0x0570, 0, 0), + MX8MP_PAD_SD2_CMD__UART4_DCE_TX = IOMUX_PAD(0x0324, 0x00C4, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__UART4_DTE_RX = IOMUX_PAD(0x0324, 0x00C4, 3, 0x0600, 1, 0), + MX8MP_PAD_SD2_CMD__AUDIOMIX_CLK = IOMUX_PAD(0x0324, 0x00C4, 4, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__GPIO2_IO14 = IOMUX_PAD(0x0324, 0x00C4, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 = IOMUX_PAD(0x0324, 0x00C4, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__OBSERVE_MUX_OUT01 = IOMUX_PAD(0x0324, 0x00C4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0328, 0x00C8, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA0__I2C4_SDA = IOMUX_PAD(0x0328, 0x00C8, 2 | IOMUX_CONFIG_SION, 0x05C0, 1, 0), + MX8MP_PAD_SD2_DATA0__UART2_DCE_RX = IOMUX_PAD(0x0328, 0x00C8, 3, 0x05F0, 2, 0), + MX8MP_PAD_SD2_DATA0__UART2_DTE_TX = IOMUX_PAD(0x0328, 0x00C8, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA0__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x0328, 0x00C8, 4, 0x04C0, 1, 0), + MX8MP_PAD_SD2_DATA0__GPIO2_IO15 = IOMUX_PAD(0x0328, 0x00C8, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 = IOMUX_PAD(0x0328, 0x00C8, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA0__OBSERVE_MUX_OUT02 = IOMUX_PAD(0x0328, 0x00C8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x032C, 0x00CC, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA1__I2C4_SCL = IOMUX_PAD(0x032C, 0x00CC, 2 | IOMUX_CONFIG_SION, 0x05BC, 1, 0), + MX8MP_PAD_SD2_DATA1__UART2_DCE_TX = IOMUX_PAD(0x032C, 0x00CC, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA1__UART2_DTE_RX = IOMUX_PAD(0x032C, 0x00CC, 3, 0x05F0, 3, 0), + MX8MP_PAD_SD2_DATA1__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x032C, 0x00CC, 4, 0x04C4, 1, 0), + MX8MP_PAD_SD2_DATA1__GPIO2_IO16 = IOMUX_PAD(0x032C, 0x00CC, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x032C, 0x00CC, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA1__OBSERVE_MUX_OUT03 = IOMUX_PAD(0x032C, 0x00CC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x0330, 0x00D0, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA2__ECSPI2_SS0 = IOMUX_PAD(0x0330, 0x00D0, 2, 0x0574, 0, 0), + MX8MP_PAD_SD2_DATA2__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x0330, 0x00D0, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA2__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x0330, 0x00D0, 4, 0x04C8, 1, 0), + MX8MP_PAD_SD2_DATA2__GPIO2_IO17 = IOMUX_PAD(0x0330, 0x00D0, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x0330, 0x00D0, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA2__OBSERVE_MUX_OUT04 = IOMUX_PAD(0x0330, 0x00D0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0334, 0x00D4, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA3__ECSPI2_MISO = IOMUX_PAD(0x0334, 0x00D4, 2, 0x056C, 0, 0), + MX8MP_PAD_SD2_DATA3__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0334, 0x00D4, 3, 0x0544, 1, 0), + MX8MP_PAD_SD2_DATA3__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x0334, 0x00D4, 4, 0x04CC, 1, 0), + MX8MP_PAD_SD2_DATA3__GPIO2_IO18 = IOMUX_PAD(0x0334, 0x00D4, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET = IOMUX_PAD(0x0334, 0x00D4, 6, 0x0000, 0, 0), + + MX8MP_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x0338, 0x00D8, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 = IOMUX_PAD(0x0338, 0x00D8, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET = IOMUX_PAD(0x0338, 0x00D8, 6, 0x0000, 0, 0), + + MX8MP_PAD_SD2_WP__USDHC2_WP = IOMUX_PAD(0x033C, 0x00DC, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_WP__GPIO2_IO20 = IOMUX_PAD(0x033C, 0x00DC, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_WP__CORESIGHT_EVENTI = IOMUX_PAD(0x033C, 0x00DC, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_WP__SIM_M_HMASTLOCK = IOMUX_PAD(0x033C, 0x00DC, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x0340, 0x00E0, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__FLEXSPI_A_SCLK = IOMUX_PAD(0x0340, 0x00E0, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK = IOMUX_PAD(0x0340, 0x00E0, 2, 0x04E8, 0, 0), + MX8MP_PAD_NAND_ALE__MEDIAMIX_ISP_FL_TRIG_0 = IOMUX_PAD(0x0340, 0x00E0, 3, 0x05D4, 1, 0), + MX8MP_PAD_NAND_ALE__UART3_DCE_RX = IOMUX_PAD(0x0340, 0x00E0, 4, 0x05F8, 2, 0), + MX8MP_PAD_NAND_ALE__UART3_DTE_TX = IOMUX_PAD(0x0340, 0x00E0, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__GPIO3_IO00 = IOMUX_PAD(0x0340, 0x00E0, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__CORESIGHT_TRACE_CLK = IOMUX_PAD(0x0340, 0x00E0, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__SIM_M_HPROT00 = IOMUX_PAD(0x0340, 0x00E0, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0344, 0x00E4, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__FLEXSPI_A_SS0_B = IOMUX_PAD(0x0344, 0x00E4, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00 = IOMUX_PAD(0x0344, 0x00E4, 2, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__MEDIAMIX_ISP_SHUTTER_TRIG_0 = IOMUX_PAD(0x0344, 0x00E4, 3, 0x05DC, 1, 0), + MX8MP_PAD_NAND_CE0_B__UART3_DCE_TX = IOMUX_PAD(0x0344, 0x00E4, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__UART3_DTE_RX = IOMUX_PAD(0x0344, 0x00E4, 4, 0x05F8, 3, 0), + MX8MP_PAD_NAND_CE0_B__GPIO3_IO01 = IOMUX_PAD(0x0344, 0x00E4, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__CORESIGHT_TRACE_CTL = IOMUX_PAD(0x0344, 0x00E4, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__SIM_M_HPROT01 = IOMUX_PAD(0x0344, 0x00E4, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0348, 0x00E8, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE1_B__FLEXSPI_A_SS1_B = IOMUX_PAD(0x0348, 0x00E8, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE1_B__USDHC3_STROBE = IOMUX_PAD(0x0348, 0x00E8, 2, 0x0630, 1, 0), + MX8MP_PAD_NAND_CE1_B__I2C4_SCL = IOMUX_PAD(0x0348, 0x00E8, 4 | IOMUX_CONFIG_SION, 0x05BC, 2, 0), + MX8MP_PAD_NAND_CE1_B__GPIO3_IO02 = IOMUX_PAD(0x0348, 0x00E8, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE1_B__CORESIGHT_TRACE00 = IOMUX_PAD(0x0348, 0x00E8, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE1_B__SIM_M_HPROT02 = IOMUX_PAD(0x0348, 0x00E8, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CE2_B__RAWNAND_CE2_B = IOMUX_PAD(0x034C, 0x00EC, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE2_B__FLEXSPI_B_SS0_B = IOMUX_PAD(0x034C, 0x00EC, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 = IOMUX_PAD(0x034C, 0x00EC, 2, 0x0624, 1, 0), + MX8MP_PAD_NAND_CE2_B__I2C4_SDA = IOMUX_PAD(0x034C, 0x00EC, 4 | IOMUX_CONFIG_SION, 0x05C0, 2, 0), + MX8MP_PAD_NAND_CE2_B__GPIO3_IO03 = IOMUX_PAD(0x034C, 0x00EC, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE2_B__CORESIGHT_TRACE01 = IOMUX_PAD(0x034C, 0x00EC, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE2_B__SIM_M_HPROT03 = IOMUX_PAD(0x034C, 0x00EC, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CE3_B__RAWNAND_CE3_B = IOMUX_PAD(0x0350, 0x00F0, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE3_B__FLEXSPI_B_SS1_B = IOMUX_PAD(0x0350, 0x00F0, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 = IOMUX_PAD(0x0350, 0x00F0, 2, 0x0628, 1, 0), + MX8MP_PAD_NAND_CE3_B__I2C3_SDA = IOMUX_PAD(0x0350, 0x00F0, 4 | IOMUX_CONFIG_SION, 0x05B8, 1, 0), + MX8MP_PAD_NAND_CE3_B__GPIO3_IO04 = IOMUX_PAD(0x0350, 0x00F0, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE3_B__CORESIGHT_TRACE02 = IOMUX_PAD(0x0350, 0x00F0, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE3_B__SIM_M_HADDR00 = IOMUX_PAD(0x0350, 0x00F0, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0354, 0x00F4, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__FLEXSPI_B_SCLK = IOMUX_PAD(0x0354, 0x00F4, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__USDHC3_DATA7 = IOMUX_PAD(0x0354, 0x00F4, 2, 0x062C, 1, 0), + MX8MP_PAD_NAND_CLE__UART4_DCE_RX = IOMUX_PAD(0x0354, 0x00F4, 4, 0x0600, 2, 0), + MX8MP_PAD_NAND_CLE__UART4_DTE_TX = IOMUX_PAD(0x0354, 0x00F4, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__GPIO3_IO05 = IOMUX_PAD(0x0354, 0x00F4, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__CORESIGHT_TRACE03 = IOMUX_PAD(0x0354, 0x00F4, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__SIM_M_HADDR01 = IOMUX_PAD(0x0354, 0x00F4, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0358, 0x00F8, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__FLEXSPI_A_DATA00 = IOMUX_PAD(0x0358, 0x00F8, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00 = IOMUX_PAD(0x0358, 0x00F8, 2, 0x04E4, 0, 0), + MX8MP_PAD_NAND_DATA00__MEDIAMIX_ISP_FLASH_TRIG_0 = IOMUX_PAD(0x0358, 0x00F8, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__UART4_DCE_RX = IOMUX_PAD(0x0358, 0x00F8, 4, 0x0600, 3, 0), + MX8MP_PAD_NAND_DATA00__UART4_DTE_TX = IOMUX_PAD(0x0358, 0x00F8, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__GPIO3_IO06 = IOMUX_PAD(0x0358, 0x00F8, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__CORESIGHT_TRACE04 = IOMUX_PAD(0x0358, 0x00F8, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__SIM_M_HADDR02 = IOMUX_PAD(0x0358, 0x00F8, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x035C, 0x00FC, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__FLEXSPI_A_DATA01 = IOMUX_PAD(0x035C, 0x00FC, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC = IOMUX_PAD(0x035C, 0x00FC, 2, 0x04EC, 0, 0), + MX8MP_PAD_NAND_DATA01__MEDIAMIX_ISP_PRELIGHT_TRIG_0 = IOMUX_PAD(0x035C, 0x00FC, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__UART4_DCE_TX = IOMUX_PAD(0x035C, 0x00FC, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__UART4_DTE_RX = IOMUX_PAD(0x035C, 0x00FC, 4, 0x0600, 4, 0), + MX8MP_PAD_NAND_DATA01__GPIO3_IO07 = IOMUX_PAD(0x035C, 0x00FC, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__CORESIGHT_TRACE05 = IOMUX_PAD(0x035C, 0x00FC, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__SIM_M_HADDR03 = IOMUX_PAD(0x035C, 0x00FC, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x0360, 0x0100, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__FLEXSPI_A_DATA02 = IOMUX_PAD(0x0360, 0x0100, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__USDHC3_CD_B = IOMUX_PAD(0x0360, 0x0100, 2, 0x0608, 2, 0), + MX8MP_PAD_NAND_DATA02__UART4_DCE_CTS = IOMUX_PAD(0x0360, 0x0100, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__UART4_DTE_RTS = IOMUX_PAD(0x0360, 0x0100, 3, 0x05FC, 0, 0), + MX8MP_PAD_NAND_DATA02__I2C4_SDA = IOMUX_PAD(0x0360, 0x0100, 4 | IOMUX_CONFIG_SION, 0x05C0, 3, 0), + MX8MP_PAD_NAND_DATA02__GPIO3_IO08 = IOMUX_PAD(0x0360, 0x0100, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__CORESIGHT_TRACE06 = IOMUX_PAD(0x0360, 0x0100, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__SIM_M_HADDR04 = IOMUX_PAD(0x0360, 0x0100, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0364, 0x0104, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__FLEXSPI_A_DATA03 = IOMUX_PAD(0x0364, 0x0104, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__USDHC3_WP = IOMUX_PAD(0x0364, 0x0104, 2, 0x0634, 2, 0), + MX8MP_PAD_NAND_DATA03__UART4_DCE_RTS = IOMUX_PAD(0x0364, 0x0104, 3, 0x05FC, 1, 0), + MX8MP_PAD_NAND_DATA03__UART4_DTE_CTS = IOMUX_PAD(0x0364, 0x0104, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__MEDIAMIX_ISP_FL_TRIG_1 = IOMUX_PAD(0x0364, 0x0104, 4, 0x05D8, 1, 0), + MX8MP_PAD_NAND_DATA03__GPIO3_IO09 = IOMUX_PAD(0x0364, 0x0104, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__CORESIGHT_TRACE07 = IOMUX_PAD(0x0364, 0x0104, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__SIM_M_HADDR05 = IOMUX_PAD(0x0364, 0x0104, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x0368, 0x0108, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__FLEXSPI_B_DATA00 = IOMUX_PAD(0x0368, 0x0108, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 = IOMUX_PAD(0x0368, 0x0108, 2, 0x0610, 1, 0), + MX8MP_PAD_NAND_DATA04__FLEXSPI_A_DATA04 = IOMUX_PAD(0x0368, 0x0108, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__MEDIAMIX_ISP_SHUTTER_TRIG_1 = IOMUX_PAD(0x0368, 0x0108, 4, 0x05E0, 1, 0), + MX8MP_PAD_NAND_DATA04__GPIO3_IO10 = IOMUX_PAD(0x0368, 0x0108, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__CORESIGHT_TRACE08 = IOMUX_PAD(0x0368, 0x0108, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__SIM_M_HADDR06 = IOMUX_PAD(0x0368, 0x0108, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x036C, 0x010C, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__FLEXSPI_B_DATA01 = IOMUX_PAD(0x036C, 0x010C, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 = IOMUX_PAD(0x036C, 0x010C, 2, 0x0614, 1, 0), + MX8MP_PAD_NAND_DATA05__FLEXSPI_A_DATA05 = IOMUX_PAD(0x036C, 0x010C, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__MEDIAMIX_ISP_FLASH_TRIG_1 = IOMUX_PAD(0x036C, 0x010C, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__GPIO3_IO11 = IOMUX_PAD(0x036C, 0x010C, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__CORESIGHT_TRACE09 = IOMUX_PAD(0x036C, 0x010C, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__SIM_M_HADDR07 = IOMUX_PAD(0x036C, 0x010C, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x0370, 0x0110, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__FLEXSPI_B_DATA02 = IOMUX_PAD(0x0370, 0x0110, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 = IOMUX_PAD(0x0370, 0x0110, 2, 0x0618, 1, 0), + MX8MP_PAD_NAND_DATA06__FLEXSPI_A_DATA06 = IOMUX_PAD(0x0370, 0x0110, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__MEDIAMIX_ISP_PRELIGHT_TRIG_1 = IOMUX_PAD(0x0370, 0x0110, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__GPIO3_IO12 = IOMUX_PAD(0x0370, 0x0110, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__CORESIGHT_TRACE10 = IOMUX_PAD(0x0370, 0x0110, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__SIM_M_HADDR08 = IOMUX_PAD(0x0370, 0x0110, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0374, 0x0114, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__FLEXSPI_B_DATA03 = IOMUX_PAD(0x0374, 0x0114, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 = IOMUX_PAD(0x0374, 0x0114, 2, 0x061C, 1, 0), + MX8MP_PAD_NAND_DATA07__FLEXSPI_A_DATA07 = IOMUX_PAD(0x0374, 0x0114, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__MEDIAMIX_ISP_SHUTTER_OPEN_1 = IOMUX_PAD(0x0374, 0x0114, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__GPIO3_IO13 = IOMUX_PAD(0x0374, 0x0114, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__CORESIGHT_TRACE11 = IOMUX_PAD(0x0374, 0x0114, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__SIM_M_HADDR09 = IOMUX_PAD(0x0374, 0x0114, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0378, 0x0118, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__FLEXSPI_A_DQS = IOMUX_PAD(0x0378, 0x0118, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__AUDIOMIX_SAI3_MCLK = IOMUX_PAD(0x0378, 0x0118, 2, 0x04E0, 0, 0), + MX8MP_PAD_NAND_DQS__MEDIAMIX_ISP_SHUTTER_OPEN_0 = IOMUX_PAD(0x0378, 0x0118, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__I2C3_SCL = IOMUX_PAD(0x0378, 0x0118, 4 | IOMUX_CONFIG_SION, 0x05B4, 1, 0), + MX8MP_PAD_NAND_DQS__GPIO3_IO14 = IOMUX_PAD(0x0378, 0x0118, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__CORESIGHT_TRACE12 = IOMUX_PAD(0x0378, 0x0118, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__SIM_M_HADDR10 = IOMUX_PAD(0x0378, 0x0118, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x037C, 0x011C, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__FLEXSPI_B_DQS = IOMUX_PAD(0x037C, 0x011C, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 = IOMUX_PAD(0x037C, 0x011C, 2, 0x0620, 1, 0), + MX8MP_PAD_NAND_RE_B__UART4_DCE_TX = IOMUX_PAD(0x037C, 0x011C, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__UART4_DTE_RX = IOMUX_PAD(0x037C, 0x011C, 4, 0x0600, 5, 0), + MX8MP_PAD_NAND_RE_B__GPIO3_IO15 = IOMUX_PAD(0x037C, 0x011C, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__CORESIGHT_TRACE13 = IOMUX_PAD(0x037C, 0x011C, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__SIM_M_HADDR11 = IOMUX_PAD(0x037C, 0x011C, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x0380, 0x0120, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_READY_B__USDHC3_RESET_B = IOMUX_PAD(0x0380, 0x0120, 2, 0x0000, 0, 0), + MX8MP_PAD_NAND_READY_B__I2C3_SCL = IOMUX_PAD(0x0380, 0x0120, 4 | IOMUX_CONFIG_SION, 0x05B4, 2, 0), + MX8MP_PAD_NAND_READY_B__GPIO3_IO16 = IOMUX_PAD(0x0380, 0x0120, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_READY_B__CORESIGHT_TRACE14 = IOMUX_PAD(0x0380, 0x0120, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_READY_B__SIM_M_HADDR12 = IOMUX_PAD(0x0380, 0x0120, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x0384, 0x0124, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_WE_B__USDHC3_CLK = IOMUX_PAD(0x0384, 0x0124, 2, 0x0604, 1, 0), + MX8MP_PAD_NAND_WE_B__I2C3_SDA = IOMUX_PAD(0x0384, 0x0124, 4 | IOMUX_CONFIG_SION, 0x05B8, 2, 0), + MX8MP_PAD_NAND_WE_B__GPIO3_IO17 = IOMUX_PAD(0x0384, 0x0124, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_WE_B__CORESIGHT_TRACE15 = IOMUX_PAD(0x0384, 0x0124, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_WE_B__SIM_M_HADDR13 = IOMUX_PAD(0x0384, 0x0124, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x0388, 0x0128, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_WP_B__USDHC3_CMD = IOMUX_PAD(0x0388, 0x0128, 2, 0x060C, 1, 0), + MX8MP_PAD_NAND_WP_B__I2C4_SCL = IOMUX_PAD(0x0388, 0x0128, 4 | IOMUX_CONFIG_SION, 0x05BC, 3, 0), + MX8MP_PAD_NAND_WP_B__GPIO3_IO18 = IOMUX_PAD(0x0388, 0x0128, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_WP_B__CORESIGHT_EVENTO = IOMUX_PAD(0x0388, 0x0128, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_WP_B__SIM_M_HADDR14 = IOMUX_PAD(0x0388, 0x0128, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC = IOMUX_PAD(0x038C, 0x012C, 0, 0x0508, 0, 0), + MX8MP_PAD_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 = IOMUX_PAD(0x038C, 0x012C, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXFS__PWM4_OUT = IOMUX_PAD(0x038C, 0x012C, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXFS__I2C6_SCL = IOMUX_PAD(0x038C, 0x012C, 3 | IOMUX_CONFIG_SION, 0x05CC, 1, 0), + MX8MP_PAD_SAI5_RXFS__GPIO3_IO19 = IOMUX_PAD(0x038C, 0x012C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXC__AUDIOMIX_SAI5_RX_BCLK = IOMUX_PAD(0x0390, 0x0130, 0, 0x04F4, 0, 0), + MX8MP_PAD_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01 = IOMUX_PAD(0x0390, 0x0130, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXC__PWM3_OUT = IOMUX_PAD(0x0390, 0x0130, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXC__I2C6_SDA = IOMUX_PAD(0x0390, 0x0130, 3 | IOMUX_CONFIG_SION, 0x05D0, 1, 0), + MX8MP_PAD_SAI5_RXC__AUDIOMIX_CLK = IOMUX_PAD(0x0390, 0x0130, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXC__GPIO3_IO20 = IOMUX_PAD(0x0390, 0x0130, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 = IOMUX_PAD(0x0394, 0x0134, 0, 0x04F8, 0, 0), + MX8MP_PAD_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02 = IOMUX_PAD(0x0394, 0x0134, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD0__PWM2_OUT = IOMUX_PAD(0x0394, 0x0134, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD0__I2C5_SCL = IOMUX_PAD(0x0394, 0x0134, 3 | IOMUX_CONFIG_SION, 0x05C4, 1, 0), + MX8MP_PAD_SAI5_RXD0__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x0394, 0x0134, 4, 0x04C0, 2, 0), + MX8MP_PAD_SAI5_RXD0__GPIO3_IO21 = IOMUX_PAD(0x0394, 0x0134, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 = IOMUX_PAD(0x0398, 0x0138, 0, 0x04FC, 0, 0), + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03 = IOMUX_PAD(0x0398, 0x0138, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x0398, 0x0138, 2, 0x04D8, 0, 0), + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC = IOMUX_PAD(0x0398, 0x0138, 3, 0x0510, 0, 0), + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x0398, 0x0138, 4, 0x04C4, 2, 0), + MX8MP_PAD_SAI5_RXD1__GPIO3_IO22 = IOMUX_PAD(0x0398, 0x0138, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD1__CAN1_TX = IOMUX_PAD(0x0398, 0x0138, 6, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02 = IOMUX_PAD(0x039C, 0x013C, 0, 0x0500, 0, 0), + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04 = IOMUX_PAD(0x039C, 0x013C, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x039C, 0x013C, 2, 0x04D8, 1, 0), + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK = IOMUX_PAD(0x039C, 0x013C, 3, 0x050C, 0, 0), + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x039C, 0x013C, 4, 0x04C8, 2, 0), + MX8MP_PAD_SAI5_RXD2__GPIO3_IO23 = IOMUX_PAD(0x039C, 0x013C, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD2__CAN1_RX = IOMUX_PAD(0x039C, 0x013C, 6, 0x054C, 0, 0), + + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03 = IOMUX_PAD(0x03A0, 0x0140, 0, 0x0504, 0, 0), + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05 = IOMUX_PAD(0x03A0, 0x0140, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x03A0, 0x0140, 2, 0x04D8, 2, 0), + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 = IOMUX_PAD(0x03A0, 0x0140, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x03A0, 0x0140, 4, 0x04CC, 2, 0), + MX8MP_PAD_SAI5_RXD3__GPIO3_IO24 = IOMUX_PAD(0x03A0, 0x0140, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD3__CAN2_TX = IOMUX_PAD(0x03A0, 0x0140, 6, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_MCLK__AUDIOMIX_SAI5_MCLK = IOMUX_PAD(0x03A4, 0x0144, 0, 0x04F0, 0, 0), + MX8MP_PAD_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK = IOMUX_PAD(0x03A4, 0x0144, 1, 0x04D4, 0, 0), + MX8MP_PAD_SAI5_MCLK__PWM1_OUT = IOMUX_PAD(0x03A4, 0x0144, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI5_MCLK__I2C5_SDA = IOMUX_PAD(0x03A4, 0x0144, 3 | IOMUX_CONFIG_SION, 0x05C8, 1, 0), + MX8MP_PAD_SAI5_MCLK__GPIO3_IO25 = IOMUX_PAD(0x03A4, 0x0144, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI5_MCLK__CAN2_RX = IOMUX_PAD(0x03A4, 0x0144, 6, 0x0550, 0, 0), + + MX8MP_PAD_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC = IOMUX_PAD(0x03A8, 0x0148, 0, 0x04D0, 0, 0), + MX8MP_PAD_SAI1_RXFS__AUDIOMIX_SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0148, 1, 0x0508, 1, 0), + MX8MP_PAD_SAI1_RXFS__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x03A8, 0x0148, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXFS__GPIO4_IO00 = IOMUX_PAD(0x03A8, 0x0148, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK = IOMUX_PAD(0x03AC, 0x014C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXC__AUDIOMIX_SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x014C, 1, 0x04F4, 1, 0), + MX8MP_PAD_SAI1_RXC__AUDIOMIX_CLK = IOMUX_PAD(0x03AC, 0x014C, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXC__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x03AC, 0x014C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXC__GPIO4_IO01 = IOMUX_PAD(0x03AC, 0x014C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 = IOMUX_PAD(0x03B0, 0x0150, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI5_RX_DATA00 = IOMUX_PAD(0x03B0, 0x0150, 1, 0x04F8, 1, 0), + MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01 = IOMUX_PAD(0x03B0, 0x0150, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD0__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x03B0, 0x0150, 3, 0x04C0, 3, 0), + MX8MP_PAD_SAI1_RXD0__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x03B0, 0x0150, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD0__GPIO4_IO02 = IOMUX_PAD(0x03B0, 0x0150, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 = IOMUX_PAD(0x03B4, 0x0154, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD1__AUDIOMIX_SAI5_RX_DATA01 = IOMUX_PAD(0x03B4, 0x0154, 1, 0x04FC, 1, 0), + MX8MP_PAD_SAI1_RXD1__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x03B4, 0x0154, 3, 0x04C4, 3, 0), + MX8MP_PAD_SAI1_RXD1__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x03B4, 0x0154, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD1__GPIO4_IO03 = IOMUX_PAD(0x03B4, 0x0154, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 = IOMUX_PAD(0x03B8, 0x0158, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD2__AUDIOMIX_SAI5_RX_DATA02 = IOMUX_PAD(0x03B8, 0x0158, 1, 0x0500, 1, 0), + MX8MP_PAD_SAI1_RXD2__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x03B8, 0x0158, 3, 0x04C8, 3, 0), + MX8MP_PAD_SAI1_RXD2__ENET1_MDC = IOMUX_PAD(0x03B8, 0x0158, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD2__GPIO4_IO04 = IOMUX_PAD(0x03B8, 0x0158, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03 = IOMUX_PAD(0x03BC, 0x015C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD3__AUDIOMIX_SAI5_RX_DATA03 = IOMUX_PAD(0x03BC, 0x015C, 1, 0x0504, 1, 0), + MX8MP_PAD_SAI1_RXD3__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x03BC, 0x015C, 3, 0x04CC, 3, 0), + MX8MP_PAD_SAI1_RXD3__ENET1_MDIO = IOMUX_PAD(0x03BC, 0x015C, 4, 0x057C, 1, 0), + MX8MP_PAD_SAI1_RXD3__GPIO4_IO05 = IOMUX_PAD(0x03BC, 0x015C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04 = IOMUX_PAD(0x03C0, 0x0160, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK = IOMUX_PAD(0x03C0, 0x0160, 1, 0x0524, 1, 0), + MX8MP_PAD_SAI1_RXD4__AUDIOMIX_SAI6_RX_BCLK = IOMUX_PAD(0x03C0, 0x0160, 2, 0x0518, 1, 0), + MX8MP_PAD_SAI1_RXD4__ENET1_RGMII_RD0 = IOMUX_PAD(0x03C0, 0x0160, 4, 0x0580, 1, 0), + MX8MP_PAD_SAI1_RXD4__GPIO4_IO06 = IOMUX_PAD(0x03C0, 0x0160, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI1_RX_DATA05 = IOMUX_PAD(0x03C4, 0x0164, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI6_TX_DATA00 = IOMUX_PAD(0x03C4, 0x0164, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00 = IOMUX_PAD(0x03C4, 0x0164, 2, 0x051C, 1, 0), + MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x0164, 3, 0x04D0, 1, 0), + MX8MP_PAD_SAI1_RXD5__ENET1_RGMII_RD1 = IOMUX_PAD(0x03C4, 0x0164, 4, 0x0584, 1, 0), + MX8MP_PAD_SAI1_RXD5__GPIO4_IO07 = IOMUX_PAD(0x03C4, 0x0164, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD6__AUDIOMIX_SAI1_RX_DATA06 = IOMUX_PAD(0x03C8, 0x0168, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD6__AUDIOMIX_SAI6_TX_SYNC = IOMUX_PAD(0x03C8, 0x0168, 1, 0x0528, 1, 0), + MX8MP_PAD_SAI1_RXD6__AUDIOMIX_SAI6_RX_SYNC = IOMUX_PAD(0x03C8, 0x0168, 2, 0x0520, 1, 0), + MX8MP_PAD_SAI1_RXD6__ENET1_RGMII_RD2 = IOMUX_PAD(0x03C8, 0x0168, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD6__GPIO4_IO08 = IOMUX_PAD(0x03C8, 0x0168, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI1_RX_DATA07 = IOMUX_PAD(0x03CC, 0x016C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI6_MCLK = IOMUX_PAD(0x03CC, 0x016C, 1, 0x0514, 1, 0), + MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x03CC, 0x016C, 2, 0x04D8, 3, 0), + MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI1_TX_DATA04 = IOMUX_PAD(0x03CC, 0x016C, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD7__ENET1_RGMII_RD3 = IOMUX_PAD(0x03CC, 0x016C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD7__GPIO4_IO09 = IOMUX_PAD(0x03CC, 0x016C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x03D0, 0x0170, 0, 0x04D8, 4, 0), + MX8MP_PAD_SAI1_TXFS__AUDIOMIX_SAI5_TX_SYNC = IOMUX_PAD(0x03D0, 0x0170, 1, 0x0510, 1, 0), + MX8MP_PAD_SAI1_TXFS__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x03D0, 0x0170, 4, 0x0588, 1, 0), + MX8MP_PAD_SAI1_TXFS__GPIO4_IO10 = IOMUX_PAD(0x03D0, 0x0170, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK = IOMUX_PAD(0x03D4, 0x0174, 0, 0x04D4, 1, 0), + MX8MP_PAD_SAI1_TXC__AUDIOMIX_SAI5_TX_BCLK = IOMUX_PAD(0x03D4, 0x0174, 1, 0x050C, 1, 0), + MX8MP_PAD_SAI1_TXC__ENET1_RGMII_RXC = IOMUX_PAD(0x03D4, 0x0174, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXC__GPIO4_IO11 = IOMUX_PAD(0x03D4, 0x0174, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 = IOMUX_PAD(0x03D8, 0x0178, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD0__AUDIOMIX_SAI5_TX_DATA00 = IOMUX_PAD(0x03D8, 0x0178, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD0__ENET1_RGMII_TD0 = IOMUX_PAD(0x03D8, 0x0178, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD0__GPIO4_IO12 = IOMUX_PAD(0x03D8, 0x0178, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 = IOMUX_PAD(0x03DC, 0x017C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD1__AUDIOMIX_SAI5_TX_DATA01 = IOMUX_PAD(0x03DC, 0x017C, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x03DC, 0x017C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD1__GPIO4_IO13 = IOMUX_PAD(0x03DC, 0x017C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 = IOMUX_PAD(0x03E0, 0x0180, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD2__AUDIOMIX_SAI5_TX_DATA02 = IOMUX_PAD(0x03E0, 0x0180, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD2__ENET1_RGMII_TD2 = IOMUX_PAD(0x03E0, 0x0180, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD2__GPIO4_IO14 = IOMUX_PAD(0x03E0, 0x0180, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 = IOMUX_PAD(0x03E4, 0x0184, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD3__AUDIOMIX_SAI5_TX_DATA03 = IOMUX_PAD(0x03E4, 0x0184, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD3__ENET1_RGMII_TD3 = IOMUX_PAD(0x03E4, 0x0184, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD3__GPIO4_IO15 = IOMUX_PAD(0x03E4, 0x0184, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 = IOMUX_PAD(0x03E8, 0x0188, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD4__AUDIOMIX_SAI6_RX_BCLK = IOMUX_PAD(0x03E8, 0x0188, 1, 0x0518, 2, 0), + MX8MP_PAD_SAI1_TXD4__AUDIOMIX_SAI6_TX_BCLK = IOMUX_PAD(0x03E8, 0x0188, 2, 0x0524, 2, 0), + MX8MP_PAD_SAI1_TXD4__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x03E8, 0x0188, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD4__GPIO4_IO16 = IOMUX_PAD(0x03E8, 0x0188, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 = IOMUX_PAD(0x03EC, 0x018C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD5__AUDIOMIX_SAI6_RX_DATA00 = IOMUX_PAD(0x03EC, 0x018C, 1, 0x051C, 2, 0), + MX8MP_PAD_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00 = IOMUX_PAD(0x03EC, 0x018C, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD5__ENET1_RGMII_TXC = IOMUX_PAD(0x03EC, 0x018C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD5__GPIO4_IO17 = IOMUX_PAD(0x03EC, 0x018C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 = IOMUX_PAD(0x03F0, 0x0190, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD6__AUDIOMIX_SAI6_RX_SYNC = IOMUX_PAD(0x03F0, 0x0190, 1, 0x0520, 2, 0), + MX8MP_PAD_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC = IOMUX_PAD(0x03F0, 0x0190, 2, 0x0528, 2, 0), + MX8MP_PAD_SAI1_TXD6__ENET1_RX_ER = IOMUX_PAD(0x03F0, 0x0190, 4, 0x058C, 1, 0), + MX8MP_PAD_SAI1_TXD6__GPIO4_IO18 = IOMUX_PAD(0x03F0, 0x0190, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 = IOMUX_PAD(0x03F4, 0x0194, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD7__AUDIOMIX_SAI6_MCLK = IOMUX_PAD(0x03F4, 0x0194, 1, 0x0514, 2, 0), + MX8MP_PAD_SAI1_TXD7__AUDIOMIX_CLK = IOMUX_PAD(0x03F4, 0x0194, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD7__ENET1_TX_ER = IOMUX_PAD(0x03F4, 0x0194, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD7__GPIO4_IO19 = IOMUX_PAD(0x03F4, 0x0194, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI1_MCLK = IOMUX_PAD(0x03F8, 0x0198, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI5_MCLK = IOMUX_PAD(0x03F8, 0x0198, 1, 0x04F0, 1, 0), + MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK = IOMUX_PAD(0x03F8, 0x0198, 2, 0x04D4, 2, 0), + MX8MP_PAD_SAI1_MCLK__ENET1_TX_CLK = IOMUX_PAD(0x03F8, 0x0198, 4, 0x0578, 1, 0), + MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 = IOMUX_PAD(0x03F8, 0x0198, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI2_RX_SYNC = IOMUX_PAD(0x03FC, 0x019C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC = IOMUX_PAD(0x03FC, 0x019C, 1, 0x0510, 2, 0), + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI5_TX_DATA01 = IOMUX_PAD(0x03FC, 0x019C, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI2_RX_DATA01 = IOMUX_PAD(0x03FC, 0x019C, 3, 0x04DC, 0, 0), + MX8MP_PAD_SAI2_RXFS__UART1_DCE_TX = IOMUX_PAD(0x03FC, 0x019C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXFS__UART1_DTE_RX = IOMUX_PAD(0x03FC, 0x019C, 4, 0x05E8, 2, 0), + MX8MP_PAD_SAI2_RXFS__GPIO4_IO21 = IOMUX_PAD(0x03FC, 0x019C, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x03FC, 0x019C, 6, 0x04C8, 4, 0), + MX8MP_PAD_SAI2_RXFS__SIM_M_HSIZE00 = IOMUX_PAD(0x03FC, 0x019C, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK = IOMUX_PAD(0x0400, 0x01A0, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK = IOMUX_PAD(0x0400, 0x01A0, 1, 0x050C, 2, 0), + MX8MP_PAD_SAI2_RXC__CAN1_TX = IOMUX_PAD(0x0400, 0x01A0, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXC__UART1_DCE_RX = IOMUX_PAD(0x0400, 0x01A0, 4, 0x05E8, 3, 0), + MX8MP_PAD_SAI2_RXC__UART1_DTE_TX = IOMUX_PAD(0x0400, 0x01A0, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXC__GPIO4_IO22 = IOMUX_PAD(0x0400, 0x01A0, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXC__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x0400, 0x01A0, 6, 0x04C4, 4, 0), + MX8MP_PAD_SAI2_RXC__SIM_M_HSIZE01 = IOMUX_PAD(0x0400, 0x01A0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 = IOMUX_PAD(0x0404, 0x01A4, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 = IOMUX_PAD(0x0404, 0x01A4, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT = IOMUX_PAD(0x0404, 0x01A4, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__AUDIOMIX_SAI2_TX_DATA01 = IOMUX_PAD(0x0404, 0x01A4, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__UART1_DCE_RTS = IOMUX_PAD(0x0404, 0x01A4, 4, 0x05E4, 2, 0), + MX8MP_PAD_SAI2_RXD0__UART1_DTE_CTS = IOMUX_PAD(0x0404, 0x01A4, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__GPIO4_IO23 = IOMUX_PAD(0x0404, 0x01A4, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x0404, 0x01A4, 6, 0x04CC, 4, 0), + MX8MP_PAD_SAI2_RXD0__SIM_M_HSIZE02 = IOMUX_PAD(0x0404, 0x01A4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC = IOMUX_PAD(0x0408, 0x01A8, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01 = IOMUX_PAD(0x0408, 0x01A8, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT = IOMUX_PAD(0x0408, 0x01A8, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__AUDIOMIX_SAI2_TX_DATA01 = IOMUX_PAD(0x0408, 0x01A8, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__UART1_DCE_CTS = IOMUX_PAD(0x0408, 0x01A8, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__UART1_DTE_RTS = IOMUX_PAD(0x0408, 0x01A8, 4, 0x05E4, 3, 0), + MX8MP_PAD_SAI2_TXFS__GPIO4_IO24 = IOMUX_PAD(0x0408, 0x01A8, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x0408, 0x01A8, 6, 0x04C8, 5, 0), + MX8MP_PAD_SAI2_TXFS__SIM_M_HWRITE = IOMUX_PAD(0x0408, 0x01A8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK = IOMUX_PAD(0x040C, 0x01AC, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02 = IOMUX_PAD(0x040C, 0x01AC, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXC__CAN1_RX = IOMUX_PAD(0x040C, 0x01AC, 3, 0x054C, 1, 0), + MX8MP_PAD_SAI2_TXC__GPIO4_IO25 = IOMUX_PAD(0x040C, 0x01AC, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXC__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x040C, 0x01AC, 6, 0x04C4, 5, 0), + MX8MP_PAD_SAI2_TXC__SIM_M_HREADYOUT = IOMUX_PAD(0x040C, 0x01AC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 = IOMUX_PAD(0x0410, 0x01B0, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03 = IOMUX_PAD(0x0410, 0x01B0, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN = IOMUX_PAD(0x0410, 0x01B0, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__CAN2_TX = IOMUX_PAD(0x0410, 0x01B0, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN = IOMUX_PAD(0x0410, 0x01B0, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__GPIO4_IO26 = IOMUX_PAD(0x0410, 0x01B0, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__CCMSRCGPCMIX_BOOT_MODE04 = IOMUX_PAD(0x0410, 0x01B0, 6, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__TPSMP_CLK = IOMUX_PAD(0x0410, 0x01B0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI2_MCLK = IOMUX_PAD(0x0414, 0x01B4, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI5_MCLK = IOMUX_PAD(0x0414, 0x01B4, 1, 0x04F0, 2, 0), + MX8MP_PAD_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN = IOMUX_PAD(0x0414, 0x01B4, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_MCLK__CAN2_RX = IOMUX_PAD(0x0414, 0x01B4, 3, 0x0550, 1, 0), + MX8MP_PAD_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN = IOMUX_PAD(0x0414, 0x01B4, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_MCLK__GPIO4_IO27 = IOMUX_PAD(0x0414, 0x01B4, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI3_MCLK = IOMUX_PAD(0x0414, 0x01B4, 6, 0x04E0, 1, 0), + MX8MP_PAD_SAI2_MCLK__TPSMP_HDATA_DIR = IOMUX_PAD(0x0414, 0x01B4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC = IOMUX_PAD(0x0418, 0x01B8, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01 = IOMUX_PAD(0x0418, 0x01B8, 1, 0x04DC, 1, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC = IOMUX_PAD(0x0418, 0x01B8, 2, 0x0508, 2, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 = IOMUX_PAD(0x0418, 0x01B8, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0418, 0x01B8, 4, 0x0544, 2, 0), + MX8MP_PAD_SAI3_RXFS__GPIO4_IO28 = IOMUX_PAD(0x0418, 0x01B8, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x0418, 0x01B8, 6, 0x04C0, 4, 0), + MX8MP_PAD_SAI3_RXFS__TPSMP_HTRANS00 = IOMUX_PAD(0x0418, 0x01B8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK = IOMUX_PAD(0x041C, 0x01BC, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02 = IOMUX_PAD(0x041C, 0x01BC, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK = IOMUX_PAD(0x041C, 0x01BC, 2, 0x04F4, 2, 0), + MX8MP_PAD_SAI3_RXC__GPT1_CLK = IOMUX_PAD(0x041C, 0x01BC, 3, 0x059C, 0, 0), + MX8MP_PAD_SAI3_RXC__UART2_DCE_CTS = IOMUX_PAD(0x041C, 0x01BC, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__UART2_DTE_RTS = IOMUX_PAD(0x041C, 0x01BC, 4, 0x05EC, 2, 0), + MX8MP_PAD_SAI3_RXC__GPIO4_IO29 = IOMUX_PAD(0x041C, 0x01BC, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__AUDIOMIX_CLK = IOMUX_PAD(0x041C, 0x01BC, 6, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__TPSMP_HTRANS01 = IOMUX_PAD(0x041C, 0x01BC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 = IOMUX_PAD(0x0420, 0x01C0, 0, 0x04E4, 1, 0), + MX8MP_PAD_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03 = IOMUX_PAD(0x0420, 0x01C0, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 = IOMUX_PAD(0x0420, 0x01C0, 2, 0x04F8, 2, 0), + MX8MP_PAD_SAI3_RXD__UART2_DCE_RTS = IOMUX_PAD(0x0420, 0x01C0, 4, 0x05EC, 3, 0), + MX8MP_PAD_SAI3_RXD__UART2_DTE_CTS = IOMUX_PAD(0x0420, 0x01C0, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXD__GPIO4_IO30 = IOMUX_PAD(0x0420, 0x01C0, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXD__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x0420, 0x01C0, 6, 0x04C4, 6, 0), + MX8MP_PAD_SAI3_RXD__TPSMP_HDATA00 = IOMUX_PAD(0x0420, 0x01C0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC = IOMUX_PAD(0x0424, 0x01C4, 0, 0x04EC, 1, 0), + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01 = IOMUX_PAD(0x0424, 0x01C4, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI5_RX_DATA01 = IOMUX_PAD(0x0424, 0x01C4, 2, 0x04FC, 2, 0), + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01 = IOMUX_PAD(0x0424, 0x01C4, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXFS__UART2_DCE_RX = IOMUX_PAD(0x0424, 0x01C4, 4, 0x05F0, 4, 0), + MX8MP_PAD_SAI3_TXFS__UART2_DTE_TX = IOMUX_PAD(0x0424, 0x01C4, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXFS__GPIO4_IO31 = IOMUX_PAD(0x0424, 0x01C4, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x0424, 0x01C4, 6, 0x04CC, 5, 0), + MX8MP_PAD_SAI3_TXFS__TPSMP_HDATA01 = IOMUX_PAD(0x0424, 0x01C4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK = IOMUX_PAD(0x0428, 0x01C8, 0, 0x04E8, 1, 0), + MX8MP_PAD_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02 = IOMUX_PAD(0x0428, 0x01C8, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXC__AUDIOMIX_SAI5_RX_DATA02 = IOMUX_PAD(0x0428, 0x01C8, 2, 0x0500, 2, 0), + MX8MP_PAD_SAI3_TXC__GPT1_CAPTURE1 = IOMUX_PAD(0x0428, 0x01C8, 3, 0x0594, 0, 0), + MX8MP_PAD_SAI3_TXC__UART2_DCE_TX = IOMUX_PAD(0x0428, 0x01C8, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXC__UART2_DTE_RX = IOMUX_PAD(0x0428, 0x01C8, 4, 0x05F0, 5, 0), + MX8MP_PAD_SAI3_TXC__GPIO5_IO00 = IOMUX_PAD(0x0428, 0x01C8, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXC__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x0428, 0x01C8, 6, 0x04C8, 6, 0), + MX8MP_PAD_SAI3_TXC__TPSMP_HDATA02 = IOMUX_PAD(0x0428, 0x01C8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 = IOMUX_PAD(0x042C, 0x01CC, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03 = IOMUX_PAD(0x042C, 0x01CC, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03 = IOMUX_PAD(0x042C, 0x01CC, 2, 0x0504, 2, 0), + MX8MP_PAD_SAI3_TXD__GPT1_CAPTURE2 = IOMUX_PAD(0x042C, 0x01CC, 3, 0x0598, 0, 0), + MX8MP_PAD_SAI3_TXD__AUDIOMIX_SPDIF_EXT_CLK = IOMUX_PAD(0x042C, 0x01CC, 4, 0x0548, 0, 0), + MX8MP_PAD_SAI3_TXD__GPIO5_IO01 = IOMUX_PAD(0x042C, 0x01CC, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXD__CCMSRCGPCMIX_BOOT_MODE05 = IOMUX_PAD(0x042C, 0x01CC, 6, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXD__TPSMP_HDATA03 = IOMUX_PAD(0x042C, 0x01CC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SAI3_MCLK = IOMUX_PAD(0x0430, 0x01D0, 0, 0x04E0, 2, 0), + MX8MP_PAD_SAI3_MCLK__PWM4_OUT = IOMUX_PAD(0x0430, 0x01D0, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SAI5_MCLK = IOMUX_PAD(0x0430, 0x01D0, 2, 0x04F0, 3, 0), + MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x0430, 0x01D0, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_MCLK__GPIO5_IO02 = IOMUX_PAD(0x0430, 0x01D0, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0430, 0x01D0, 6, 0x0544, 3, 0), + MX8MP_PAD_SAI3_MCLK__TPSMP_HDATA04 = IOMUX_PAD(0x0430, 0x01D0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SPDIF_TX__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x0434, 0x01D4, 0, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_TX__PWM3_OUT = IOMUX_PAD(0x0434, 0x01D4, 1, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_TX__I2C5_SCL = IOMUX_PAD(0x0434, 0x01D4, 2 | IOMUX_CONFIG_SION, 0x05C4, 2, 0), + MX8MP_PAD_SPDIF_TX__GPT1_COMPARE1 = IOMUX_PAD(0x0434, 0x01D4, 3, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_TX__CAN1_TX = IOMUX_PAD(0x0434, 0x01D4, 4, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_TX__GPIO5_IO03 = IOMUX_PAD(0x0434, 0x01D4, 5, 0x0000, 0, 0), + + MX8MP_PAD_SPDIF_RX__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0438, 0x01D8, 0, 0x0544, 4, 0), + MX8MP_PAD_SPDIF_RX__PWM2_OUT = IOMUX_PAD(0x0438, 0x01D8, 1, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_RX__I2C5_SDA = IOMUX_PAD(0x0438, 0x01D8, 2 | IOMUX_CONFIG_SION, 0x05C8, 2, 0), + MX8MP_PAD_SPDIF_RX__GPT1_COMPARE2 = IOMUX_PAD(0x0438, 0x01D8, 3, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_RX__CAN1_RX = IOMUX_PAD(0x0438, 0x01D8, 4, 0x054C, 2, 0), + MX8MP_PAD_SPDIF_RX__GPIO5_IO04 = IOMUX_PAD(0x0438, 0x01D8, 5, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_EXT_CLK__GPT1_COMPARE3 = IOMUX_PAD(0x043C, 0x01DC, 3, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_EXT_CLK__GPIO5_IO05 = IOMUX_PAD(0x043C, 0x01DC, 5, 0x0000, 0, 0), + + MX8MP_PAD_SPDIF_EXT_CLK__AUDIOMIX_SPDIF_EXT_CLK = IOMUX_PAD(0x043C, 0x01DC, 0, 0x0548, 1, 0), + MX8MP_PAD_SPDIF_EXT_CLK__PWM1_OUT = IOMUX_PAD(0x043C, 0x01DC, 1, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x0440, 0x01E0, 0, 0x0558, 0, 0), + MX8MP_PAD_ECSPI1_SCLK__UART3_DCE_RX = IOMUX_PAD(0x0440, 0x01E0, 1, 0x05F8, 4, 0), + MX8MP_PAD_ECSPI1_SCLK__UART3_DTE_TX = IOMUX_PAD(0x0440, 0x01E0, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_SCLK__I2C1_SCL = IOMUX_PAD(0x0440, 0x01E0, 2 | IOMUX_CONFIG_SION, 0x05A4, 1, 0), + MX8MP_PAD_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC = IOMUX_PAD(0x0440, 0x01E0, 3, 0x0538, 1, 0), + MX8MP_PAD_ECSPI1_SCLK__GPIO5_IO06 = IOMUX_PAD(0x0440, 0x01E0, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_SCLK__TPSMP_HDATA08 = IOMUX_PAD(0x0440, 0x01E0, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0444, 0x01E4, 0, 0x0560, 0, 0), + MX8MP_PAD_ECSPI1_MOSI__UART3_DCE_TX = IOMUX_PAD(0x0444, 0x01E4, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_MOSI__UART3_DTE_RX = IOMUX_PAD(0x0444, 0x01E4, 1, 0x05F8, 5, 0), + MX8MP_PAD_ECSPI1_MOSI__I2C1_SDA = IOMUX_PAD(0x0444, 0x01E4, 2 | IOMUX_CONFIG_SION, 0x05A8, 1, 0), + MX8MP_PAD_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK = IOMUX_PAD(0x0444, 0x01E4, 3, 0x0530, 1, 0), + MX8MP_PAD_ECSPI1_MOSI__GPIO5_IO07 = IOMUX_PAD(0x0444, 0x01E4, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_MOSI__TPSMP_HDATA09 = IOMUX_PAD(0x0444, 0x01E4, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0448, 0x01E8, 0, 0x055C, 0, 0), + MX8MP_PAD_ECSPI1_MISO__UART3_DCE_CTS = IOMUX_PAD(0x0448, 0x01E8, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_MISO__UART3_DTE_RTS = IOMUX_PAD(0x0448, 0x01E8, 1, 0x05F4, 2, 0), + MX8MP_PAD_ECSPI1_MISO__I2C2_SCL = IOMUX_PAD(0x0448, 0x01E8, 2 | IOMUX_CONFIG_SION, 0x05AC, 1, 0), + MX8MP_PAD_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00 = IOMUX_PAD(0x0448, 0x01E8, 3, 0x0534, 1, 0), + MX8MP_PAD_ECSPI1_MISO__GPIO5_IO08 = IOMUX_PAD(0x0448, 0x01E8, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_MISO__TPSMP_HDATA10 = IOMUX_PAD(0x0448, 0x01E8, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x044C, 0x01EC, 0, 0x0564, 0, 0), + MX8MP_PAD_ECSPI1_SS0__UART3_DCE_RTS = IOMUX_PAD(0x044C, 0x01EC, 1, 0x05F4, 3, 0), + MX8MP_PAD_ECSPI1_SS0__UART3_DTE_CTS = IOMUX_PAD(0x044C, 0x01EC, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_SS0__I2C2_SDA = IOMUX_PAD(0x044C, 0x01EC, 2 | IOMUX_CONFIG_SION, 0x05B0, 1, 0), + MX8MP_PAD_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC = IOMUX_PAD(0x044C, 0x01EC, 3, 0x0540, 1, 0), + MX8MP_PAD_ECSPI1_SS0__GPIO5_IO09 = IOMUX_PAD(0x044C, 0x01EC, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_SS0__TPSMP_HDATA11 = IOMUX_PAD(0x044C, 0x01EC, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x0450, 0x01F0, 0, 0x0568, 1, 0), + MX8MP_PAD_ECSPI2_SCLK__UART4_DCE_RX = IOMUX_PAD(0x0450, 0x01F0, 1, 0x0600, 6, 0), + MX8MP_PAD_ECSPI2_SCLK__UART4_DTE_TX = IOMUX_PAD(0x0450, 0x01F0, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SCLK__I2C3_SCL = IOMUX_PAD(0x0450, 0x01F0, 2 | IOMUX_CONFIG_SION, 0x05B4, 3, 0), + MX8MP_PAD_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK = IOMUX_PAD(0x0450, 0x01F0, 3, 0x053C, 1, 0), + MX8MP_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x0450, 0x01F0, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SCLK__TPSMP_HDATA12 = IOMUX_PAD(0x0450, 0x01F0, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0454, 0x01F4, 0, 0x0570, 1, 0), + MX8MP_PAD_ECSPI2_MOSI__UART4_DCE_TX = IOMUX_PAD(0x0454, 0x01F4, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MOSI__UART4_DTE_RX = IOMUX_PAD(0x0454, 0x01F4, 1, 0x0600, 7, 0), + MX8MP_PAD_ECSPI2_MOSI__I2C3_SDA = IOMUX_PAD(0x0454, 0x01F4, 2 | IOMUX_CONFIG_SION, 0x05B8, 3, 0), + MX8MP_PAD_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00 = IOMUX_PAD(0x0454, 0x01F4, 3, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0454, 0x01F4, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MOSI__TPSMP_HDATA13 = IOMUX_PAD(0x0454, 0x01F4, 7, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MISO__GPIO5_IO12 = IOMUX_PAD(0x0458, 0x01F8, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MISO__TPSMP_HDATA14 = IOMUX_PAD(0x0458, 0x01F8, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0458, 0x01F8, 0, 0x056C, 1, 0), + MX8MP_PAD_ECSPI2_MISO__UART4_DCE_CTS = IOMUX_PAD(0x0458, 0x01F8, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MISO__UART4_DTE_RTS = IOMUX_PAD(0x0458, 0x01F8, 1, 0x05FC, 2, 0), + MX8MP_PAD_ECSPI2_MISO__I2C4_SCL = IOMUX_PAD(0x0458, 0x01F8, 2 | IOMUX_CONFIG_SION, 0x05BC, 4, 0), + MX8MP_PAD_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK = IOMUX_PAD(0x0458, 0x01F8, 3, 0x052C, 1, 0), + MX8MP_PAD_ECSPI2_MISO__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x0458, 0x01F8, 4, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x045C, 0x01FC, 0, 0x0574, 1, 0), + MX8MP_PAD_ECSPI2_SS0__UART4_DCE_RTS = IOMUX_PAD(0x045C, 0x01FC, 1, 0x05FC, 3, 0), + MX8MP_PAD_ECSPI2_SS0__UART4_DTE_CTS = IOMUX_PAD(0x045C, 0x01FC, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SS0__I2C4_SDA = IOMUX_PAD(0x045C, 0x01FC, 2 | IOMUX_CONFIG_SION, 0x05C0, 4, 0), + MX8MP_PAD_ECSPI2_SS0__CCMSRCGPCMIX_CLKO2 = IOMUX_PAD(0x045C, 0x01FC, 4, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SS0__GPIO5_IO13 = IOMUX_PAD(0x045C, 0x01FC, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SS0__TPSMP_HDATA15 = IOMUX_PAD(0x045C, 0x01FC, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x0460, 0x0200, 0 | IOMUX_CONFIG_SION, 0x05A4, 2, 0), + MX8MP_PAD_I2C1_SCL__ENET_QOS_MDC = IOMUX_PAD(0x0460, 0x0200, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C1_SCL__ECSPI1_SCLK = IOMUX_PAD(0x0460, 0x0200, 3, 0x0558, 1, 0), + MX8MP_PAD_I2C1_SCL__GPIO5_IO14 = IOMUX_PAD(0x0460, 0x0200, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C1_SCL__TPSMP_HDATA16 = IOMUX_PAD(0x0460, 0x0200, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0464, 0x0204, 0 | IOMUX_CONFIG_SION, 0x05A8, 2, 0), + MX8MP_PAD_I2C1_SDA__ENET_QOS_MDIO = IOMUX_PAD(0x0464, 0x0204, 1, 0x0590, 2, 0), + MX8MP_PAD_I2C1_SDA__ECSPI1_MOSI = IOMUX_PAD(0x0464, 0x0204, 3, 0x0560, 1, 0), + MX8MP_PAD_I2C1_SDA__GPIO5_IO15 = IOMUX_PAD(0x0464, 0x0204, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C1_SDA__TPSMP_HDATA17 = IOMUX_PAD(0x0464, 0x0204, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0468, 0x0208, 0 | IOMUX_CONFIG_SION, 0x05AC, 2, 0), + MX8MP_PAD_I2C2_SCL__ENET_QOS_1588_EVENT1_IN = IOMUX_PAD(0x0468, 0x0208, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SCL__USDHC3_CD_B = IOMUX_PAD(0x0468, 0x0208, 2, 0x0608, 3, 0), + MX8MP_PAD_I2C2_SCL__ECSPI1_MISO = IOMUX_PAD(0x0468, 0x0208, 3, 0x055C, 1, 0), + MX8MP_PAD_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN = IOMUX_PAD(0x0468, 0x0208, 4, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SCL__GPIO5_IO16 = IOMUX_PAD(0x0468, 0x0208, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SCL__TPSMP_HDATA18 = IOMUX_PAD(0x0468, 0x0208, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x046C, 0x020C, 0 | IOMUX_CONFIG_SION, 0x05B0, 2, 0), + MX8MP_PAD_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT = IOMUX_PAD(0x046C, 0x020C, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SDA__USDHC3_WP = IOMUX_PAD(0x046C, 0x020C, 2, 0x0634, 3, 0), + MX8MP_PAD_I2C2_SDA__ECSPI1_SS0 = IOMUX_PAD(0x046C, 0x020C, 3, 0x0564, 1, 0), + MX8MP_PAD_I2C2_SDA__GPIO5_IO17 = IOMUX_PAD(0x046C, 0x020C, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SDA__TPSMP_HDATA19 = IOMUX_PAD(0x046C, 0x020C, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x0470, 0x0210, 0 | IOMUX_CONFIG_SION, 0x05B4, 4, 0), + MX8MP_PAD_I2C3_SCL__PWM4_OUT = IOMUX_PAD(0x0470, 0x0210, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SCL__GPT2_CLK = IOMUX_PAD(0x0470, 0x0210, 2, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SCL__ECSPI2_SCLK = IOMUX_PAD(0x0470, 0x0210, 3, 0x0568, 2, 0), + MX8MP_PAD_I2C3_SCL__GPIO5_IO18 = IOMUX_PAD(0x0470, 0x0210, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SCL__TPSMP_HDATA20 = IOMUX_PAD(0x0470, 0x0210, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x0474, 0x0214, 0 | IOMUX_CONFIG_SION, 0x05B8, 4, 0), + MX8MP_PAD_I2C3_SDA__PWM3_OUT = IOMUX_PAD(0x0474, 0x0214, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SDA__GPT3_CLK = IOMUX_PAD(0x0474, 0x0214, 2, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SDA__ECSPI2_MOSI = IOMUX_PAD(0x0474, 0x0214, 3, 0x0570, 2, 0), + MX8MP_PAD_I2C3_SDA__GPIO5_IO19 = IOMUX_PAD(0x0474, 0x0214, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SDA__TPSMP_HDATA21 = IOMUX_PAD(0x0474, 0x0214, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x0478, 0x0218, 0 | IOMUX_CONFIG_SION, 0x05BC, 5, 0), + MX8MP_PAD_I2C4_SCL__PWM2_OUT = IOMUX_PAD(0x0478, 0x0218, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C4_SCL__HSIOMIX_PCIE_CLKREQ_B = IOMUX_PAD(0x0478, 0x0218, 2, 0x05A0, 0, 0), + MX8MP_PAD_I2C4_SCL__ECSPI2_MISO = IOMUX_PAD(0x0478, 0x0218, 3, 0x056C, 2, 0), + MX8MP_PAD_I2C4_SCL__GPIO5_IO20 = IOMUX_PAD(0x0478, 0x0218, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C4_SCL__TPSMP_HDATA22 = IOMUX_PAD(0x0478, 0x0218, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x047C, 0x021C, 0 | IOMUX_CONFIG_SION, 0x05C0, 5, 0), + MX8MP_PAD_I2C4_SDA__PWM1_OUT = IOMUX_PAD(0x047C, 0x021C, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C4_SDA__ECSPI2_SS0 = IOMUX_PAD(0x047C, 0x021C, 3, 0x0574, 2, 0), + MX8MP_PAD_I2C4_SDA__GPIO5_IO21 = IOMUX_PAD(0x047C, 0x021C, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C4_SDA__TPSMP_HDATA23 = IOMUX_PAD(0x047C, 0x021C, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART1_RXD__UART1_DCE_RX = IOMUX_PAD(0x0480, 0x0220, 0, 0x05E8, 4, 0), + + MX8MP_PAD_UART1_RXD__UART1_DTE_TX = IOMUX_PAD(0x0480, 0x0220, 0, 0x0000, 0, 0), + MX8MP_PAD_UART1_RXD__ECSPI3_SCLK = IOMUX_PAD(0x0480, 0x0220, 1, 0x0000, 0, 0), + MX8MP_PAD_UART1_RXD__GPIO5_IO22 = IOMUX_PAD(0x0480, 0x0220, 5, 0x0000, 0, 0), + MX8MP_PAD_UART1_RXD__TPSMP_HDATA24 = IOMUX_PAD(0x0480, 0x0220, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART1_TXD__UART1_DCE_TX = IOMUX_PAD(0x0484, 0x0224, 0, 0x0000, 0, 0), + + MX8MP_PAD_UART1_TXD__UART1_DTE_RX = IOMUX_PAD(0x0484, 0x0224, 0, 0x05E8, 5, 0), + MX8MP_PAD_UART1_TXD__ECSPI3_MOSI = IOMUX_PAD(0x0484, 0x0224, 1, 0x0000, 0, 0), + MX8MP_PAD_UART1_TXD__GPIO5_IO23 = IOMUX_PAD(0x0484, 0x0224, 5, 0x0000, 0, 0), + MX8MP_PAD_UART1_TXD__TPSMP_HDATA25 = IOMUX_PAD(0x0484, 0x0224, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART2_RXD__UART2_DCE_RX = IOMUX_PAD(0x0488, 0x0228, 0, 0x05F0, 6, 0), + + MX8MP_PAD_UART2_RXD__UART2_DTE_TX = IOMUX_PAD(0x0488, 0x0228, 0, 0x0000, 0, 0), + MX8MP_PAD_UART2_RXD__ECSPI3_MISO = IOMUX_PAD(0x0488, 0x0228, 1, 0x0000, 0, 0), + MX8MP_PAD_UART2_RXD__GPT1_COMPARE3 = IOMUX_PAD(0x0488, 0x0228, 3, 0x0000, 0, 0), + MX8MP_PAD_UART2_RXD__GPIO5_IO24 = IOMUX_PAD(0x0488, 0x0228, 5, 0x0000, 0, 0), + MX8MP_PAD_UART2_RXD__TPSMP_HDATA26 = IOMUX_PAD(0x0488, 0x0228, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART2_TXD__UART2_DCE_TX = IOMUX_PAD(0x048C, 0x022C, 0, 0x0000, 0, 0), + + MX8MP_PAD_UART2_TXD__UART2_DTE_RX = IOMUX_PAD(0x048C, 0x022C, 0, 0x05F0, 7, 0), + MX8MP_PAD_UART2_TXD__ECSPI3_SS0 = IOMUX_PAD(0x048C, 0x022C, 1, 0x0000, 0, 0), + MX8MP_PAD_UART2_TXD__GPT1_COMPARE2 = IOMUX_PAD(0x048C, 0x022C, 3, 0x0000, 0, 0), + MX8MP_PAD_UART2_TXD__GPIO5_IO25 = IOMUX_PAD(0x048C, 0x022C, 5, 0x0000, 0, 0), + MX8MP_PAD_UART2_TXD__TPSMP_HDATA27 = IOMUX_PAD(0x048C, 0x022C, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART3_RXD__UART3_DCE_RX = IOMUX_PAD(0x0490, 0x0230, 0, 0x05F8, 6, 0), + + MX8MP_PAD_UART3_RXD__UART3_DTE_TX = IOMUX_PAD(0x0490, 0x0230, 0, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__UART1_DCE_CTS = IOMUX_PAD(0x0490, 0x0230, 1, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__UART1_DTE_RTS = IOMUX_PAD(0x0490, 0x0230, 1, 0x05E4, 4, 0), + MX8MP_PAD_UART3_RXD__USDHC3_RESET_B = IOMUX_PAD(0x0490, 0x0230, 2, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__GPT1_CAPTURE2 = IOMUX_PAD(0x0490, 0x0230, 3, 0x0598, 1, 0), + MX8MP_PAD_UART3_RXD__CAN2_TX = IOMUX_PAD(0x0490, 0x0230, 4, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__GPIO5_IO26 = IOMUX_PAD(0x0490, 0x0230, 5, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__TPSMP_HDATA28 = IOMUX_PAD(0x0490, 0x0230, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART3_TXD__UART3_DCE_TX = IOMUX_PAD(0x0494, 0x0234, 0, 0x0000, 0, 0), + + MX8MP_PAD_UART3_TXD__UART3_DTE_RX = IOMUX_PAD(0x0494, 0x0234, 0, 0x05F8, 7, 0), + MX8MP_PAD_UART3_TXD__UART1_DCE_RTS = IOMUX_PAD(0x0494, 0x0234, 1, 0x05E4, 5, 0), + MX8MP_PAD_UART3_TXD__UART1_DTE_CTS = IOMUX_PAD(0x0494, 0x0234, 1, 0x0000, 0, 0), + MX8MP_PAD_UART3_TXD__USDHC3_VSELECT = IOMUX_PAD(0x0494, 0x0234, 2, 0x0000, 0, 0), + MX8MP_PAD_UART3_TXD__GPT1_CLK = IOMUX_PAD(0x0494, 0x0234, 3, 0x059C, 1, 0), + MX8MP_PAD_UART3_TXD__CAN2_RX = IOMUX_PAD(0x0494, 0x0234, 4, 0x0550, 2, 0), + MX8MP_PAD_UART3_TXD__GPIO5_IO27 = IOMUX_PAD(0x0494, 0x0234, 5, 0x0000, 0, 0), + MX8MP_PAD_UART3_TXD__TPSMP_HDATA29 = IOMUX_PAD(0x0494, 0x0234, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART4_RXD__UART4_DCE_RX = IOMUX_PAD(0x0498, 0x0238, 0, 0x0600, 8, 0), + + MX8MP_PAD_UART4_RXD__UART4_DTE_TX = IOMUX_PAD(0x0498, 0x0238, 0, 0x0000, 0, 0), + MX8MP_PAD_UART4_RXD__UART2_DCE_CTS = IOMUX_PAD(0x0498, 0x0238, 1, 0x0000, 0, 0), + MX8MP_PAD_UART4_RXD__UART2_DTE_RTS = IOMUX_PAD(0x0498, 0x0238, 1, 0x05EC, 4, 0), + MX8MP_PAD_UART4_RXD__HSIOMIX_PCIE_CLKREQ_B = IOMUX_PAD(0x0498, 0x0238, 2, 0x05A0, 1, 0), + MX8MP_PAD_UART4_RXD__GPT1_COMPARE1 = IOMUX_PAD(0x0498, 0x0238, 3, 0x0000, 0, 0), + MX8MP_PAD_UART4_RXD__I2C6_SCL = IOMUX_PAD(0x0498, 0x0238, 4 | IOMUX_CONFIG_SION, 0x05CC, 2, 0), + MX8MP_PAD_UART4_RXD__GPIO5_IO28 = IOMUX_PAD(0x0498, 0x0238, 5, 0x0000, 0, 0), + MX8MP_PAD_UART4_RXD__TPSMP_HDATA30 = IOMUX_PAD(0x0498, 0x0238, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART4_TXD__UART4_DCE_TX = IOMUX_PAD(0x049C, 0x023C, 0, 0x0000, 0, 0), + + MX8MP_PAD_UART4_TXD__UART4_DTE_RX = IOMUX_PAD(0x049C, 0x023C, 0, 0x0600, 9, 0), + MX8MP_PAD_UART4_TXD__UART2_DCE_RTS = IOMUX_PAD(0x049C, 0x023C, 1, 0x05EC, 5, 0), + MX8MP_PAD_UART4_TXD__UART2_DTE_CTS = IOMUX_PAD(0x049C, 0x023C, 1, 0x0000, 0, 0), + MX8MP_PAD_UART4_TXD__GPT1_CAPTURE1 = IOMUX_PAD(0x049C, 0x023C, 3, 0x0594, 1, 0), + MX8MP_PAD_UART4_TXD__I2C6_SDA = IOMUX_PAD(0x049C, 0x023C, 4 | IOMUX_CONFIG_SION, 0x05D0, 2, 0), + MX8MP_PAD_UART4_TXD__GPIO5_IO29 = IOMUX_PAD(0x049C, 0x023C, 5, 0x0000, 0, 0), + MX8MP_PAD_UART4_TXD__TPSMP_HDATA31 = IOMUX_PAD(0x049C, 0x023C, 7, 0x0000, 0, 0), + + MX8MP_PAD_HDMI_DDC_SCL__HDMIMIX_EARC_SCL = IOMUX_PAD(0x04A0, 0x0240, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SCL__I2C5_SCL = IOMUX_PAD(0x04A0, 0x0240, 3 | IOMUX_CONFIG_SION, 0x05C4, 3, 0), + MX8MP_PAD_HDMI_DDC_SCL__CAN1_TX = IOMUX_PAD(0x04A0, 0x0240, 4, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SCL__GPIO3_IO26 = IOMUX_PAD(0x04A0, 0x0240, 5, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SCL__AUDIOMIX_test_out00 = IOMUX_PAD(0x04A0, 0x0240, 6, 0x0000, 0, 0), + + MX8MP_PAD_HDMI_DDC_SDA__HDMIMIX_EARC_SDA = IOMUX_PAD(0x04A4, 0x0244, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SDA__I2C5_SDA = IOMUX_PAD(0x04A4, 0x0244, 3 | IOMUX_CONFIG_SION, 0x05C8, 3, 0), + MX8MP_PAD_HDMI_DDC_SDA__CAN1_RX = IOMUX_PAD(0x04A4, 0x0244, 4, 0x054C, 3, 0), + MX8MP_PAD_HDMI_DDC_SDA__GPIO3_IO27 = IOMUX_PAD(0x04A4, 0x0244, 5, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SDA__AUDIOMIX_test_out01 = IOMUX_PAD(0x04A4, 0x0244, 6, 0x0000, 0, 0), + + MX8MP_PAD_HDMI_CEC__HDMIMIX_EARC_CEC = IOMUX_PAD(0x04A8, 0x0248, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_CEC__I2C6_SCL = IOMUX_PAD(0x04A8, 0x0248, 3 | IOMUX_CONFIG_SION, 0x05CC, 3, 0), + MX8MP_PAD_HDMI_CEC__CAN2_TX = IOMUX_PAD(0x04A8, 0x0248, 4, 0x0000, 0, 0), + MX8MP_PAD_HDMI_CEC__GPIO3_IO28 = IOMUX_PAD(0x04A8, 0x0248, 5, 0x0000, 0, 0), + + MX8MP_PAD_HDMI_HPD__HDMIMIX_EARC_DC_HPD = IOMUX_PAD(0x04AC, 0x024C, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_HPD__AUDIOMIX_EARC_HDMI_HPD_O = IOMUX_PAD(0x04AC, 0x024C, 1, 0x0000, 0, 0), + MX8MP_PAD_HDMI_HPD__I2C6_SDA = IOMUX_PAD(0x04AC, 0x024C, 3 | IOMUX_CONFIG_SION, 0x05D0, 3, 0), + MX8MP_PAD_HDMI_HPD__CAN2_RX = IOMUX_PAD(0x04AC, 0x024C, 4, 0x0550, 3, 0), + MX8MP_PAD_HDMI_HPD__GPIO3_IO29 = IOMUX_PAD(0x04AC, 0x024C, 5, 0x0000, 0, 0), +}; +#endif /* __ASM_ARCH_IMX8MP_PINS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h b/roms/u-boot/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h new file mode 100644 index 000000000..c71913f20 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h @@ -0,0 +1,622 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 NXP + */ + +#ifndef __ASM_ARCH_IMX8MQ_PINS_H__ +#define __ASM_ARCH_IMX8MQ_PINS_H__ + +#include + +enum { + IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO00__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO00__CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO00__JTAG_FAIL = IOMUX_PAD(0x0290, 0x0028, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO01__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO01__CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO01__JTAG_ACTIVE = IOMUX_PAD(0x0294, 0x002C, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO02__GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO02__JTAG_DE_B = IOMUX_PAD(0x0298, 0x0030, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO03__USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO03__SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO03__XTALOSC_XTAL_OK = IOMUX_PAD(0x029C, 0x0034, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO03__JTAG_DONE = IOMUX_PAD(0x029C, 0x0034, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO04__SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO04__XTALOSC_XTAL_OK_1V = IOMUX_PAD(0x02A0, 0x0038, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO05__ARM_PLATFORM_CM4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO05__CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0), + IMX8MQ_PAD_GPIO1_IO05__SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO06__ENET_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO06__USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO06__CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO07__ENET_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0), + IMX8MQ_PAD_GPIO1_IO07__USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO07__CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO08__ENET_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO08__USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO08__CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO09__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO09__SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO09__CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO10__USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO11__USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO11__CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0), + + IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO12__USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO12__SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT0 = IOMUX_PAD(0x02C0, 0x0058, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO13__USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO13__PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT1 = IOMUX_PAD(0x02C4, 0x005C, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO14__USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO14__PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO14__CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT2 = IOMUX_PAD(0x02C8, 0x0060, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO15__USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO15__PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO15__CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO15__CSU_CSU_INT_DEB = IOMUX_PAD(0x02CC, 0x0064, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_MDC__GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0), + IMX8MQ_PAD_ENET_MDIO__GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD3__GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD2__ENET_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD2__GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD1__GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD0__GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TX_CTL__ENET_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TX_CTL__GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TXC__ENET_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TXC__GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RXC__ENET_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_CLK__GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_CMD__GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA0__GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA1__GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA2__GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA3__GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA4__GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA5__GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA6__GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA7__GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_RESET_B__USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_STROBE__GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_CLK__GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_CMD__GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA0__GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA1__GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA1__CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA2__GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA2__CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA3__GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA3__SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_RESET_B__SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_WP__USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_WP__GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_ALE__GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE0_B__GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE1_B__QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CE2_B__RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE2_B__QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE2_B__GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CE3_B__RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE3_B__QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CLE__QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA00__GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA04__QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA05__QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA06__QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA07__QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DQS__QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DQS__GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_RE_B__QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0), + IMX8MQ_PAD_SAI5_RXFS__SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0), + IMX8MQ_PAD_SAI5_RXC__SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0), + IMX8MQ_PAD_SAI5_RXD0__SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0), + IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0), + IMX8MQ_PAD_SAI5_RXD1__SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0), + IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0), + IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0), + IMX8MQ_PAD_SAI5_RXD2__SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0), + IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0), + IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0), + IMX8MQ_PAD_SAI5_RXD3__SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_MCLK__SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0), + IMX8MQ_PAD_SAI5_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0), + IMX8MQ_PAD_SAI5_MCLK__SAI4_MCLK = IOMUX_PAD(0x03C0, 0x0158, 2, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_MCLK__SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXFS__SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0), + IMX8MQ_PAD_SAI1_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0), + IMX8MQ_PAD_SAI1_RXFS__ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXFS__GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXC__SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0), + IMX8MQ_PAD_SAI1_RXC__ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXC__GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD0__SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0), + IMX8MQ_PAD_SAI1_RXD0__ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD0__GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD0__SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD1__SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0), + IMX8MQ_PAD_SAI1_RXD1__ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD1__GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD1__SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD2__SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0), + IMX8MQ_PAD_SAI1_RXD2__ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD2__GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD2__SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD3__SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x04E0, 1, 0), + IMX8MQ_PAD_SAI1_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD3__ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD3__GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD3__SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD4__SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0), + IMX8MQ_PAD_SAI1_RXD5__ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD6__SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD7__SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0), + IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXFS__SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0), + IMX8MQ_PAD_SAI1_TXFS__SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0), + IMX8MQ_PAD_SAI1_TXFS__ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXC__SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0), + IMX8MQ_PAD_SAI1_TXC__SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0), + IMX8MQ_PAD_SAI1_TXC__ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD0__SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD0__ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD0__GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD0__SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD1__SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD1__SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD1__ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD1__GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD1__SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD2__SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD2__SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD2__ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD2__GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD2__SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD3__SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD3__SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD3__ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD3__GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD3__SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD4__SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD4__SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0), + IMX8MQ_PAD_SAI1_TXD4__SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0), + IMX8MQ_PAD_SAI1_TXD4__ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD4__GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD4__SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD5__SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0), + IMX8MQ_PAD_SAI1_TXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD5__ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD5__GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD5__SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD6__SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD6__SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0), + IMX8MQ_PAD_SAI1_TXD6__SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0), + IMX8MQ_PAD_SAI1_TXD6__ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD6__GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD6__SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD7__SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD7__SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0), + IMX8MQ_PAD_SAI1_TXD7__ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD7__GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD7__SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_MCLK__SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_MCLK__SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0), + IMX8MQ_PAD_SAI1_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0), + IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_RXFS__SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_RXFS__SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0), + IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_RXC__SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_RXC__SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0), + IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_RXD0__SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_RXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_RXD0__GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_TXFS__SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXFS__SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXFS__GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_TXC__SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXC__SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXC__GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_TXD0__SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXD0__SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXD0__GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_MCLK__SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_MCLK__SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0), + IMX8MQ_PAD_SAI2_MCLK__GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_RXFS__SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXFS__GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0), + IMX8MQ_PAD_SAI3_RXFS__GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_RXC__SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXC__GPT1_CAPTURE2 = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0), + IMX8MQ_PAD_SAI3_RXC__GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_RXD__SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXD__GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXD__SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0), + IMX8MQ_PAD_SAI3_RXD__GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_TXFS__SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXFS__GPT1_CLK = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXFS__SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0), + IMX8MQ_PAD_SAI3_TXFS__GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_TXC__SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXC__GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXC__SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0), + IMX8MQ_PAD_SAI3_TXC__GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_TXD__SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXD__GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXD__SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0), + IMX8MQ_PAD_SAI3_TXD__GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_MCLK__SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_MCLK__PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_MCLK__SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0), + IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SPDIF_TX__SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_TX__PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SPDIF_RX__SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_RX__PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SPDIF_EXT_CLK__SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_EXT_CLK__PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_EXT_CLK__GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI1_SCLK__UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0), + IMX8MQ_PAD_ECSPI1_SCLK__GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI1_MOSI__UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0), + IMX8MQ_PAD_ECSPI1_MOSI__GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0), + IMX8MQ_PAD_ECSPI1_MISO__GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI1_SS0__UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0), + IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0), + IMX8MQ_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0), + IMX8MQ_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0), + IMX8MQ_PAD_ECSPI2_MISO__GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0), + IMX8MQ_PAD_ECSPI2_SS0__GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, 0x10 | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C1_SCL__ENET_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, 0x10 | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C1_SDA__ENET_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0), + IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0x10 | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C2_SCL__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0x10 | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C2_SDA__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, 0x10 | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SCL__PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SCL__GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, 0x10 | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SDA__PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SDA__GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, 0x10 | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C4_SCL__PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C4_SCL__PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0), + IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, 0x10 | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C4_SDA__PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C4_SDA__PCIE2_CLKREQ_B = IOMUX_PAD(0x0498, 0x0230, 2, 0x0528, 0, 0), + IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART1_RXD__UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0), + IMX8MQ_PAD_UART1_RXD__ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0), + IMX8MQ_PAD_UART1_RXD__GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART1_TXD__UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0), + IMX8MQ_PAD_UART1_TXD__ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0), + IMX8MQ_PAD_UART1_TXD__GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART2_RXD__UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0), + IMX8MQ_PAD_UART2_RXD__ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_UART2_RXD__GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART2_TXD__UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0), + IMX8MQ_PAD_UART2_TXD__ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0), + IMX8MQ_PAD_UART2_TXD__GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART3_RXD__UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0), + IMX8MQ_PAD_UART3_RXD__UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0), + IMX8MQ_PAD_UART3_RXD__GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART3_TXD__UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0), + IMX8MQ_PAD_UART3_TXD__UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0), + IMX8MQ_PAD_UART3_TXD__GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART4_RXD__UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0), + IMX8MQ_PAD_UART4_RXD__UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0), + IMX8MQ_PAD_UART4_RXD__PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0), + IMX8MQ_PAD_UART4_RXD__GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART4_TXD__UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0), + IMX8MQ_PAD_UART4_TXD__UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0), + IMX8MQ_PAD_UART4_TXD__PCIE2_CLKREQ_B = IOMUX_PAD(0x04B8, 0x0250, 2, 0x0528, 1, 0), + IMX8MQ_PAD_UART4_TXD__GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0), +}; +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8m/lpddr4_define.h b/roms/u-boot/arch/arm/include/asm/arch-imx8m/lpddr4_define.h new file mode 100644 index 000000000..caf5bafb6 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8m/lpddr4_define.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __LPDDR4_DEFINE_H_ +#define __LPDDR4_DEFINE_H_ + +#define LPDDR4_DVFS_DBI +#define DDR_ONE_RANK +/* #define LPDDR4_DBI_ON */ +#define DFI_BUG_WR +#define M845S_4GBx2 +#define PRETRAIN + +/* DRAM MR setting */ +#ifdef LPDDR4_DBI_ON +#define LPDDR4_MR3 0xf1 +#define LPDDR4_PHY_DMIPinPresent 0x1 +#else +#define LPDDR4_MR3 0x31 +#define LPDDR4_PHY_DMIPinPresent 0x0 +#endif + +#ifdef DDR_ONE_RANK +#define LPDDR4_CS 0x1 +#else +#define LPDDR4_CS 0x3 +#endif + +/* PHY training feature */ +#define LPDDR4_HDT_CTL_2D 0xC8 +#define LPDDR4_HDT_CTL_3200_1D 0xC8 +#define LPDDR4_HDT_CTL_400_1D 0xC8 +#define LPDDR4_HDT_CTL_100_1D 0xC8 + +/* 400/100 training seq */ +#define LPDDR4_TRAIN_SEQ_P2 0x121f +#define LPDDR4_TRAIN_SEQ_P1 0x121f +#define LPDDR4_TRAIN_SEQ_P0 0x121f +#define LPDDR4_TRAIN_SEQ_100 0x121f +#define LPDDR4_TRAIN_SEQ_400 0x121f + +/* 2D share & weight */ +#define LPDDR4_2D_WEIGHT 0x1f7f +#define LPDDR4_2D_SHARE 1 +#define LPDDR4_CATRAIN_3200_1d 0 +#define LPDDR4_CATRAIN_400 0 +#define LPDDR4_CATRAIN_100 0 +#define LPDDR4_CATRAIN_3200_2d 0 + +/* MRS parameter */ +/* for LPDDR4 Rtt */ +#define LPDDR4_RTT40 6 +#define LPDDR4_RTT48 5 +#define LPDDR4_RTT60 4 +#define LPDDR4_RTT80 3 +#define LPDDR4_RTT120 2 +#define LPDDR4_RTT240 1 +#define LPDDR4_RTT_DIS 0 + +/* for LPDDR4 Ron */ +#define LPDDR4_RON34 7 +#define LPDDR4_RON40 6 +#define LPDDR4_RON48 5 +#define LPDDR4_RON60 4 +#define LPDDR4_RON80 3 + +#define LPDDR4_PHY_ADDR_RON60 0x1 +#define LPDDR4_PHY_ADDR_RON40 0x3 +#define LPDDR4_PHY_ADDR_RON30 0x7 +#define LPDDR4_PHY_ADDR_RON24 0xf +#define LPDDR4_PHY_ADDR_RON20 0x1f + +/* for read channel */ +#define LPDDR4_RON LPDDR4_RON40 +#define LPDDR4_PHY_RTT 30 +#define LPDDR4_PHY_VREF_VALUE 17 + +/* for write channel */ +#define LPDDR4_PHY_RON 30 +#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40 +#define LPDDR4_RTT_DQ LPDDR4_RTT40 +#define LPDDR4_RTT_CA LPDDR4_RTT40 +#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40 +#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40 +#define LPDDR4_VREF_VALUE_CA ((1 << 6) | (0xd)) +#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1 << 6) | (0xd)) +#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1 << 6) | (0xd)) +#define LPDDR4_MR22_RANK0 ((0 << 5) | (1 << 4) | (0 << 3) | \ + (LPDDR4_RTT40)) +#define LPDDR4_MR22_RANK1 ((1 << 5) | (1 << 4) | (1 << 3) | \ + (LPDDR4_RTT40)) + +#define LPDDR4_MR3_PU_CAL 1 + +#endif /* __LPDDR4_DEFINE_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8m/power-domain.h b/roms/u-boot/arch/arm/include/asm/arch-imx8m/power-domain.h new file mode 100644 index 000000000..7a833e564 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8m/power-domain.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 NXP + */ + +#ifndef _ASM_ARCH_IMX8M_POWER_DOMAIN_H +#define _ASM_ARCH_IMX8M_POWER_DOMAIN_H + +struct imx8m_power_domain_plat { + int resource_id; + int has_pd; + struct power_domain pd; +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-imx8m/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-imx8m/sys_proto.h new file mode 100644 index 000000000..d328542ec --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imx8m/sys_proto.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 NXP + */ + +#ifndef __ARCH_IMX8M_SYS_PROTO_H +#define __ARCH_NMX8M_SYS_PROTO_H + +#include + +void set_wdog_reset(struct wdog_regs *wdog); +void enable_tzc380(void); +void restore_boot_params(void); +extern unsigned long rom_pointer[]; +enum boot_device get_boot_device(void); +bool is_usb_boot(void); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-imxrt/clock.h b/roms/u-boot/arch/arm/include/asm/arch-imxrt/clock.h new file mode 100644 index 000000000..7409028b9 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imxrt/clock.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-imxrt/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-imxrt/gpio.h new file mode 100644 index 000000000..da31a7438 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imxrt/gpio.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +/* GPIO registers */ +struct gpio_regs { + u32 gpio_dr; /* data */ + u32 gpio_dir; /* direction */ + u32 gpio_psr; /* pad satus */ +}; +#endif + +#endif /* __ASM_ARCH_GPIO_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-imxrt/imx-regs.h b/roms/u-boot/arch/arm/include/asm/arch-imxrt/imx-regs.h new file mode 100644 index 000000000..d01e6ca2e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imxrt/imx-regs.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright(C) 2019 + * Author(s): Giulio Benetti + */ + +#ifndef __ASM_ARCH_IMX_REGS_H__ +#define __ASM_ARCH_IMX_REGS_H__ + +#define ARCH_MXC + +#define GPIO1_BASE_ADDR 0x401B8000 +#define GPIO2_BASE_ADDR 0x401BC000 +#define GPIO3_BASE_ADDR 0x401C0000 +#define GPIO4_BASE_ADDR 0x401C4000 +#define GPIO5_BASE_ADDR 0x400C0000 + +#define ANATOP_BASE_ADDR 0x400d8000 + +#define MXS_LCDIF_BASE 0x402b8000 + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include +#endif + +#define USB_BASE_ADDR 0x402E0000 +#define USB_PHY0_BASE_ADDR 0x400D9000 +#define USB_PHY1_BASE_ADDR 0x400DA000 + +#endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-imxrt/imxrt.h b/roms/u-boot/arch/arm/include/asm/arch-imxrt/imxrt.h new file mode 100644 index 000000000..1cb2c57d3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imxrt/imxrt.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +#ifndef _ASM_ARCH_IMXRT_H +#define _ASM_ARCH_IMXRT_H + +#endif /* _ASM_ARCH_IMXRT_H */ + diff --git a/roms/u-boot/arch/arm/include/asm/arch-imxrt/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-imxrt/sys_proto.h new file mode 100644 index 000000000..eb878e672 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-imxrt/sys_proto.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 NXP + */ + +#ifndef _ASM_ARCH_SYS_PROTO_H +#define _ASM_ARCH_SYS_PROTO_H + +#include + +#endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/clk.h b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/clk.h new file mode 100644 index 000000000..5ab48a9d3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 by Vladimir Zapolskiy + */ + +#ifndef _LPC32XX_CLK_H +#define _LPC32XX_CLK_H + +#include + +#define OSC_CLK_FREQUENCY 13000000 +#define RTC_CLK_FREQUENCY 32768 + +/* Clocking and Power Control Registers */ +struct clk_pm_regs { + u32 reserved0[5]; + u32 boot_map; /* Boot Map Control Register */ + u32 p0_intr_er; /* Port 0/1 Start and Interrupt Enable */ + u32 usbdiv_ctrl; /* USB Clock Pre-Divide Register */ + /* Internal Start Signal Sources Registers */ + u32 start_er_int; /* Start Enable Register */ + u32 start_rsr_int; /* Start Raw Status Register */ + u32 start_sr_int; /* Start Status Register */ + u32 start_apr_int; /* Start Activation Polarity Register */ + /* Device Pin Start Signal Sources Registers */ + u32 start_er_pin; /* Start Enable Register */ + u32 start_rsr_pin; /* Start Raw Status Register */ + u32 start_sr_pin; /* Start Status Register */ + u32 start_apr_pin; /* Start Activation Polarity Register */ + /* Clock Control Registers */ + u32 hclkdiv_ctrl; /* HCLK Divider Control Register */ + u32 pwr_ctrl; /* Power Control Register */ + u32 pll397_ctrl; /* PLL397 Control Register */ + u32 osc_ctrl; /* Main Oscillator Control Register */ + u32 sysclk_ctrl; /* SYSCLK Control Register */ + u32 lcdclk_ctrl; /* LCD Clock Control Register */ + u32 hclkpll_ctrl; /* HCLK PLL Control Register */ + u32 reserved1; + u32 adclk_ctrl1; /* ADC Clock Control1 Register */ + u32 usb_ctrl; /* USB Control Register */ + u32 sdramclk_ctrl; /* SDRAM Clock Control Register */ + u32 ddr_lap_nom; /* DDR Calibration Nominal Value */ + u32 ddr_lap_count; /* DDR Calibration Measured Value */ + u32 ddr_cal_delay; /* DDR Calibration Delay Value */ + u32 ssp_ctrl; /* SSP Control Register */ + u32 i2s_ctrl; /* I2S Clock Control Register */ + u32 ms_ctrl; /* Memory Card Control Register */ + u32 reserved2[3]; + u32 macclk_ctrl; /* Ethernet MAC Clock Control Register */ + u32 reserved3[4]; + u32 test_clk; /* Test Clock Selection Register */ + u32 sw_int; /* Software Interrupt Register */ + u32 i2cclk_ctrl; /* I2C Clock Control Register */ + u32 keyclk_ctrl; /* Keyboard Scan Clock Control Register */ + u32 adclk_ctrl; /* ADC Clock Control Register */ + u32 pwmclk_ctrl; /* PWM Clock Control Register */ + u32 timclk_ctrl; /* Watchdog and Highspeed Timer Control */ + u32 timclk_ctrl1; /* Motor and Timer Clock Control */ + u32 spi_ctrl; /* SPI Control Register */ + u32 flashclk_ctrl; /* NAND Flash Clock Control Register */ + u32 reserved4; + u32 u3clk; /* UART 3 Clock Control Register */ + u32 u4clk; /* UART 4 Clock Control Register */ + u32 u5clk; /* UART 5 Clock Control Register */ + u32 u6clk; /* UART 6 Clock Control Register */ + u32 irdaclk; /* IrDA Clock Control Register */ + u32 uartclk_ctrl; /* UART Clock Control Register */ + u32 dmaclk_ctrl; /* DMA Clock Control Register */ + u32 autoclk_ctrl; /* Autoclock Control Register */ +}; + +/* HCLK Divider Control Register bits */ +#define CLK_HCLK_DDRAM_MASK (0x3 << 7) +#define CLK_HCLK_DDRAM_HALF (0x2 << 7) +#define CLK_HCLK_DDRAM_NOMINAL (0x1 << 7) +#define CLK_HCLK_DDRAM_STOPPED (0x0 << 7) +#define CLK_HCLK_PERIPH_DIV_MASK (0x1F << 2) +#define CLK_HCLK_PERIPH_DIV(n) ((((n) - 1) & 0x1F) << 2) +#define CLK_HCLK_ARM_PLL_DIV_MASK (0x3 << 0) +#define CLK_HCLK_ARM_PLL_DIV_4 (0x2 << 0) +#define CLK_HCLK_ARM_PLL_DIV_2 (0x1 << 0) +#define CLK_HCLK_ARM_PLL_DIV_1 (0x0 << 0) + +/* Power Control Register bits */ +#define CLK_PWR_HCLK_RUN_PERIPH (1 << 10) +#define CLK_PWR_EMC_SREFREQ (1 << 9) +#define CLK_PWR_EMC_SREFREQ_UPDATE (1 << 8) +#define CLK_PWR_SDRAM_SREFREQ (1 << 7) +#define CLK_PWR_HIGHCORE_LEVEL (1 << 5) +#define CLK_PWR_SYSCLKEN_LEVEL (1 << 4) +#define CLK_PWR_SYSCLKEN_CTRL (1 << 3) +#define CLK_PWR_NORMAL_RUN (1 << 2) +#define CLK_PWR_HIGHCORE_CTRL (1 << 1) +#define CLK_PWR_STOP_MODE (1 << 0) + +/* SYSCLK Control Register bits */ +#define CLK_SYSCLK_PLL397 (1 << 1) +#define CLK_SYSCLK_MUX (1 << 0) + +/* HCLK PLL Control Register bits */ +#define CLK_HCLK_PLL_OPERATING (1 << 16) +#define CLK_HCLK_PLL_BYPASS (1 << 15) +#define CLK_HCLK_PLL_DIRECT (1 << 14) +#define CLK_HCLK_PLL_FEEDBACK (1 << 13) +#define CLK_HCLK_PLL_POSTDIV_MASK (0x3 << 11) +#define CLK_HCLK_PLL_POSTDIV_16 (0x3 << 11) +#define CLK_HCLK_PLL_POSTDIV_8 (0x2 << 11) +#define CLK_HCLK_PLL_POSTDIV_4 (0x1 << 11) +#define CLK_HCLK_PLL_POSTDIV_2 (0x0 << 11) +#define CLK_HCLK_PLL_PREDIV_MASK (0x3 << 9) +#define CLK_HCLK_PLL_PREDIV_4 (0x3 << 9) +#define CLK_HCLK_PLL_PREDIV_3 (0x2 << 9) +#define CLK_HCLK_PLL_PREDIV_2 (0x1 << 9) +#define CLK_HCLK_PLL_PREDIV_1 (0x0 << 9) +#define CLK_HCLK_PLL_FEEDBACK_DIV_MASK (0xFF << 1) +#define CLK_HCLK_PLL_FEEDBACK_DIV(n) ((((n) - 1) & 0xFF) << 1) +#define CLK_HCLK_PLL_LOCKED (1 << 0) + +/* Ethernet MAC Clock Control Register bits */ +#define CLK_MAC_RMII (0x3 << 3) +#define CLK_MAC_MII (0x1 << 3) +#define CLK_MAC_MASTER (1 << 2) +#define CLK_MAC_SLAVE (1 << 1) +#define CLK_MAC_REG (1 << 0) + +/* I2C Clock Control Register bits */ +#define CLK_I2C2_ENABLE (1 << 1) +#define CLK_I2C1_ENABLE (1 << 0) + +/* Timer Clock Control1 Register bits */ +#define CLK_TIMCLK_MOTOR (1 << 6) +#define CLK_TIMCLK_TIMER3 (1 << 5) +#define CLK_TIMCLK_TIMER2 (1 << 4) +#define CLK_TIMCLK_TIMER1 (1 << 3) +#define CLK_TIMCLK_TIMER0 (1 << 2) +#define CLK_TIMCLK_TIMER5 (1 << 1) +#define CLK_TIMCLK_TIMER4 (1 << 0) + +/* Timer Clock Control Register bits */ +#define CLK_TIMCLK_HSTIMER (1 << 1) +#define CLK_TIMCLK_WATCHDOG (1 << 0) + +/* UART Clock Control Register bits */ +#define CLK_UART(n) (1 << ((n) - 3)) + +/* UARTn Clock Select Registers bits */ +#define CLK_UART_HCLK (1 << 16) +#define CLK_UART_X_DIV(n) (((n) & 0xFF) << 8) +#define CLK_UART_Y_DIV(n) (((n) & 0xFF) << 0) + +/* DMA Clock Control Register bits */ +#define CLK_DMA_ENABLE (1 << 0) + +/* NAND Clock Control Register bits */ +#define CLK_NAND_SLC (1 << 0) +#define CLK_NAND_MLC (1 << 1) +#define CLK_NAND_SLC_SELECT (1 << 2) +#define CLK_NAND_MLC_INT (1 << 5) + +/* SSP Clock Control Register bits */ +#define CLK_SSP0_ENABLE_CLOCK (1 << 0) + +/* SDRAMCLK register bits */ +#define CLK_SDRAM_DDR_SEL (1 << 1) + +/* USB control register definitions */ +#define CLK_USBCTRL_PLL_STS (1 << 0) +#define CLK_USBCTRL_FDBK_PLUS1(n) (((n) & 0xFF) << 1) +#define CLK_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11) +#define CLK_USBCTRL_PLL_PWRUP (1 << 16) +#define CLK_USBCTRL_CLK_EN1 (1 << 17) +#define CLK_USBCTRL_CLK_EN2 (1 << 18) +#define CLK_USBCTRL_BUS_KEEPER (0x1 << 19) +#define CLK_USBCTRL_USBHSTND_EN (1 << 21) +#define CLK_USBCTRL_USBDVND_EN (1 << 22) +#define CLK_USBCTRL_HCLK_EN (1 << 24) + +unsigned int get_sys_clk_rate(void); +unsigned int get_hclk_pll_rate(void); +unsigned int get_hclk_clk_div(void); +unsigned int get_hclk_clk_rate(void); +unsigned int get_periph_clk_div(void); +unsigned int get_periph_clk_rate(void); +unsigned int get_sdram_clk_rate(void); + +#endif /* _LPC32XX_CLK_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/config.h b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/config.h new file mode 100644 index 000000000..0836091af --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/config.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Common definitions for LPC32XX board configurations + * + * Copyright (C) 2011-2015 Vladimir Zapolskiy + */ + +#ifndef _LPC32XX_CONFIG_H +#define _LPC32XX_CONFIG_H + + +/* Basic CPU architecture */ + +/* UART configuration */ +#if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \ + (CONFIG_SYS_LPC32XX_UART == 7) +#if !defined(CONFIG_LPC32XX_HSUART) +#define CONFIG_LPC32XX_HSUART +#endif +#endif + +#if !defined(CONFIG_SYS_NS16550_CLK) +#define CONFIG_SYS_NS16550_CLK 13000000 +#endif + +#define CONFIG_SYS_BAUDRATE_TABLE \ + { 9600, 19200, 38400, 57600, 115200, 230400, 460800 } + +/* Ethernet */ +#define LPC32XX_ETH_BASE ETHERNET_BASE + +/* NAND */ +#if defined(CONFIG_NAND_LPC32XX_SLC) +#define NAND_LARGE_BLOCK_PAGE_SIZE 0x800 +#define NAND_SMALL_BLOCK_PAGE_SIZE 0x200 + +#if !defined(CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE +#endif + +#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE) +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE) +#define CONFIG_SYS_NAND_OOBSIZE 16 +#define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, } +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#else +#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value" +#endif + +#define CONFIG_SYS_NAND_ECCSIZE 0x100 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#endif /* CONFIG_NAND_LPC32XX_SLC */ + +/* NOR Flash */ + +/* USB OHCI */ +#if defined(CONFIG_USB_OHCI_LPC32XX) +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lpc32xx-ohci" +#endif + +#endif /* _LPC32XX_CONFIG_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/cpu.h b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/cpu.h new file mode 100644 index 000000000..7e0b781e4 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/cpu.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 by Vladimir Zapolskiy + */ + +#ifndef _LPC32XX_CPU_H +#define _LPC32XX_CPU_H + +/* LPC32XX Memory map */ + +/* AHB physical base addresses */ +#define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */ +#define SSP0_BASE 0x20084000 /* SSP0 registers base */ +#define SD_CARD_BASE 0x20098000 /* SD card interface registers base */ +#define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */ +#define DMA_BASE 0x31000000 /* DMA controller registers base */ +#define USB_BASE 0x31020000 /* USB registers base */ +#define LCD_BASE 0x31040000 /* LCD registers base */ +#define ETHERNET_BASE 0x31060000 /* Ethernet registers base */ +#define EMC_BASE 0x31080000 /* EMC configuration registers base */ + +/* FAB peripherals base addresses */ +#define CLK_PM_BASE 0x40004000 /* System control registers base */ +#define HS_UART1_BASE 0x40014000 /* High speed UART 1 registers base */ +#define HS_UART2_BASE 0x40018000 /* High speed UART 2 registers base */ +#define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */ +#define RTC_BASE 0x40024000 /* RTC registers base */ +#define GPIO_BASE 0x40028000 /* GPIO registers base */ +#define MUX_BASE 0x40028000 /* MUX registers base */ +#define WDT_BASE 0x4003C000 /* Watchdog timer registers base */ +#define TIMER0_BASE 0x40044000 /* Timer0 registers base */ +#define TIMER1_BASE 0x4004C000 /* Timer1 registers base */ +#define UART_CTRL_BASE 0x40054000 /* UART control regsisters base */ + +/* APB peripherals base addresses */ +#define UART3_BASE 0x40080000 /* UART 3 registers base */ +#define UART4_BASE 0x40088000 /* UART 4 registers base */ +#define UART5_BASE 0x40090000 /* UART 5 registers base */ +#define UART6_BASE 0x40098000 /* UART 6 registers base */ +#define I2C1_BASE 0x400A0000 /* I2C 1 registers base */ +#define I2C2_BASE 0x400A8000 /* I2C 2 registers base */ + +/* External SDRAM Memory Bank base addresses */ +#define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */ +#define EMC_DYCS1_BASE 0xA0000000 /* SDRAM DYCS1 base address */ + +/* External Static Memory Bank base addresses */ +#define EMC_CS0_BASE 0xE0000000 +#define EMC_CS1_BASE 0xE1000000 +#define EMC_CS2_BASE 0xE2000000 +#define EMC_CS3_BASE 0xE3000000 + +#endif /* _LPC32XX_CPU_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/dma.h b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/dma.h new file mode 100644 index 000000000..d69e3c466 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/dma.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * LPC32xx DMA Controller Interface + * + * Copyright (C) 2008 by NXP Semiconductors + * @Author: Kevin Wells + * @Descr: Definitions for LPC3250 chip + * @References: NXP LPC3250 User's Guide + */ + +#ifndef _LPC32XX_DMA_H +#define _LPC32XX_DMA_H + +/* + * DMA linked list structure used with a channel's LLI register; + * refer to UM10326, "LPC32x0 and LPC32x0/01 User manual" - Rev. 3 + * tables 84, 85, 86 & 87 for details. + */ +struct lpc32xx_dmac_ll { + u32 dma_src; + u32 dma_dest; + u32 next_lli; + u32 next_ctrl; +}; + +/* control register definitions */ +#define DMAC_CHAN_INT_TC_EN (1 << 31) /* channel terminal count interrupt */ +#define DMAC_CHAN_DEST_AUTOINC (1 << 27) /* automatic destination increment */ +#define DMAC_CHAN_SRC_AUTOINC (1 << 26) /* automatic source increment */ +#define DMAC_CHAN_DEST_AHB1 (1 << 25) /* AHB1 master for dest. transfer */ +#define DMAC_CHAN_DEST_WIDTH_32 (1 << 22) /* Destination data width selection */ +#define DMAC_CHAN_SRC_WIDTH_32 (1 << 19) /* Source data width selection */ +#define DMAC_CHAN_DEST_BURST_1 0 +#define DMAC_CHAN_DEST_BURST_4 (1 << 15) /* Destination data burst size */ +#define DMAC_CHAN_SRC_BURST_1 0 +#define DMAC_CHAN_SRC_BURST_4 (1 << 12) /* Source data burst size */ + +/* + * config_ch register definitions + * DMAC_CHAN_FLOW_D_xxx: flow control with DMA as the controller + * DMAC_DEST_PERIP: Macro for loading destination peripheral + * DMAC_SRC_PERIP: Macro for loading source peripheral + */ +#define DMAC_CHAN_FLOW_D_M2P (0x1 << 11) +#define DMAC_CHAN_FLOW_D_P2M (0x2 << 11) +#define DMAC_DEST_PERIP(n) (((n) & 0x1F) << 6) +#define DMAC_SRC_PERIP(n) (((n) & 0x1F) << 1) + +/* + * config_ch register definitions + * (source and destination peripheral ID numbers). + * These can be used with the DMAC_DEST_PERIP and DMAC_SRC_PERIP macros. + */ +#define DMA_PERID_NAND1 1 + +/* Channel enable bit */ +#define DMAC_CHAN_ENABLE (1 << 0) + +int lpc32xx_dma_get_channel(void); +int lpc32xx_dma_start_xfer(unsigned int channel, + const struct lpc32xx_dmac_ll *desc, u32 config); +int lpc32xx_dma_wait_status(unsigned int channel); + +#endif /* _LPC32XX_DMA_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/emc.h b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/emc.h new file mode 100644 index 000000000..20698a3d2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/emc.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 by Vladimir Zapolskiy + */ + +#ifndef _LPC32XX_EMC_H +#define _LPC32XX_EMC_H + +#include + +/* EMC Registers */ +struct emc_regs { + u32 ctrl; /* Controls operation of the EMC */ + u32 status; /* Provides EMC status information */ + u32 config; /* Configures operation of the EMC */ + u32 reserved0[5]; + u32 control; /* Controls dyn memory operation */ + u32 refresh; /* Configures dyn memory refresh operation */ + u32 read_config; /* Configures the dyn memory read strategy */ + u32 reserved1; + u32 t_rp; /* Precharge command period */ + u32 t_ras; /* Active to precharge command period */ + u32 t_srex; /* Self-refresh exit time */ + u32 reserved2[2]; + u32 t_wr; /* Write recovery time */ + u32 t_rc; /* Active to active command period */ + u32 t_rfc; /* Auto-refresh period */ + u32 t_xsr; /* Exit self-refresh to active command time */ + u32 t_rrd; /* Active bank A to active bank B latency */ + u32 t_mrd; /* Load mode register to active command time */ + u32 t_cdlr; /* Last data in to read command time */ + u32 reserved3[8]; + u32 extended_wait; /* time for static memory rd/wr transfers */ + u32 reserved4[31]; + u32 config0; /* Configuration information for the SDRAM */ + u32 rascas0; /* RAS and CAS latencies for the SDRAM */ + u32 reserved5[6]; + u32 config1; /* Configuration information for the SDRAM */ + u32 rascas1; /* RAS and CAS latencies for the SDRAM */ + u32 reserved6[54]; + struct emc_stat_t { + u32 config; /* Static memory configuration */ + u32 waitwen; /* Delay from chip select to write enable */ + u32 waitoen; /* Delay to output enable */ + u32 waitrd; /* Delay to a read access */ + u32 waitpage; /* Delay for async page mode read */ + u32 waitwr; /* Delay to a write access */ + u32 waitturn; /* Number of bus turnaround cycles */ + u32 reserved; + } stat[4]; + u32 reserved7[96]; + struct emc_ahb_t { + u32 control; /* Control register for AHB */ + u32 status; /* Status register for AHB */ + u32 timeout; /* Timeout register for AHB */ + u32 reserved[5]; + } ahb[5]; +}; + +/* Static Memory Configuration Register bits */ +#define EMC_STAT_CONFIG_WP (1 << 20) +#define EMC_STAT_CONFIG_EW (1 << 8) +#define EMC_STAT_CONFIG_PB (1 << 7) +#define EMC_STAT_CONFIG_PC (1 << 6) +#define EMC_STAT_CONFIG_PM (1 << 3) +#define EMC_STAT_CONFIG_32BIT (2 << 0) +#define EMC_STAT_CONFIG_16BIT (1 << 0) +#define EMC_STAT_CONFIG_8BIT (0 << 0) + +/* Static Memory Delay Registers */ +#define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F) +#define EMC_STAT_WAITOEN(n) ((n) & 0x0F) +#define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F) +#define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F) +#define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F) +#define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F) + +/* EMC settings for DRAM */ +struct emc_dram_settings { + u32 cmddelay; + u32 config0; + u32 rascas0; + u32 rdconfig; + u32 trp; + u32 tras; + u32 tsrex; + u32 twr; + u32 trc; + u32 trfc; + u32 txsr; + u32 trrd; + u32 tmrd; + u32 tcdlr; + u32 refresh; + u32 mode; + u32 emode; +}; + +#endif /* _LPC32XX_EMC_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/gpio.h new file mode 100644 index 000000000..93e7a8875 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/gpio.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * LPC32xx GPIO interface + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD + */ + +/** + * GPIO Register map for LPC32xx + */ + +struct gpio_regs { + u32 p3_inp_state; + u32 p3_outp_set; + u32 p3_outp_clr; + u32 p3_outp_state; + /* Watch out! the following are shared between p2 and p3 */ + u32 p2_p3_dir_set; + u32 p2_p3_dir_clr; + u32 p2_p3_dir_state; + /* Now back to 'one register for one port' */ + u32 p2_inp_state; + u32 p2_outp_set; + u32 p2_outp_clr; + u32 reserved1[6]; + u32 p0_inp_state; + u32 p0_outp_set; + u32 p0_outp_clr; + u32 p0_outp_state; + u32 p0_dir_set; + u32 p0_dir_clr; + u32 p0_dir_state; + u32 reserved2; + u32 p1_inp_state; + u32 p1_outp_set; + u32 p1_outp_clr; + u32 p1_outp_state; + u32 p1_dir_set; + u32 p1_dir_clr; + u32 p1_dir_state; +}; diff --git a/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h new file mode 100644 index 000000000..762bbeee0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * LPC32xx GPIO interface macro for pin mapping. + * + * (C) Copyright 2015 DENX Software Engineering GmbH + * Written-by: Sylvain Lemieux + */ + +#ifndef _LPC32XX_GPIO_GRP_H +#define _LPC32XX_GPIO_GRP_H + +/* + * Macro to map the pin for the lpc32xx_gpio driver. + * Note: - GPIOS are considered here as homogeneous and linear from 0 to 159; + * mapping is done per register, as group of 32. + * (see drivers/gpio/lpc32xx_gpio.c for details). + * - macros can be use with the following pins: + * P0.0 - P0.7 + * P1.0 - P1.23 + * P2.0 - P2.12 + * P3 GPI_0 - GPI_9 / GPI_15 - GPI_23 / GPI_25 / GPI_27 - GPI_28 + * P3 GPO_0 - GPO_23 + * P3 GPIO_0 - GPIO_5 (output register only) + */ +#define LPC32XX_GPIO_P0_GRP 0 +#define LPC32XX_GPIO_P1_GRP 32 +#define LPC32XX_GPIO_P2_GRP 64 +#define LPC32XX_GPO_P3_GRP 96 +#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25) +#define LPC32XX_GPI_P3_GRP 128 + +/* + * A specific GPIO can be selected with this macro + * ie, GPIO P0.1 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P0_GRP, 1) + * See the LPC32x0 User's guide for GPIO group numbers + */ +#define LPC32XX_GPIO(x, y) ((x) + (y)) + +#endif /* _LPC32XX_GPIO_GRP_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/i2c.h b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/i2c.h new file mode 100644 index 000000000..3918178d3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/i2c.h @@ -0,0 +1,36 @@ +#ifndef _LPC32XX_I2C_H +#define _LPC32XX_I2C_H + +#include + +/* i2c register set */ +struct lpc32xx_i2c_base { + union { + u32 rx; + u32 tx; + }; + u32 stat; + u32 ctrl; + u32 clk_hi; + u32 clk_lo; + u32 adr; + u32 rxfl; + u32 txfl; + u32 rxb; + u32 txb; + u32 stx; + u32 stxfl; +}; + +#if CONFIG_IS_ENABLED(DM_I2C) +enum { + I2C_0, I2C_1, I2C_2, +}; + +struct lpc32xx_i2c_dev { + struct lpc32xx_i2c_base *base; + int index; + uint speed; +}; +#endif /* CONFIG_DM_I2C */ +#endif /* _LPC32XX_I2C_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/mux.h b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/mux.h new file mode 100644 index 000000000..d661e8236 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/mux.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * LPC32xx MUX interface + * + * (C) Copyright 2015 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD + */ + +/** + * MUX register map for LPC32xx + */ + +struct mux_regs { + u32 reserved1[10]; + u32 p2_mux_set; + u32 p2_mux_clr; + u32 p2_mux_state; + u32 reserved2[51]; + u32 p_mux_set; + u32 p_mux_clr; + u32 p_mux_state; + u32 reserved3; + u32 p3_mux_set; + u32 p3_mux_clr; + u32 p3_mux_state; + u32 reserved4; + u32 p0_mux_set; + u32 p0_mux_clr; + u32 p0_mux_state; + u32 reserved5; + u32 p1_mux_set; + u32 p1_mux_clr; + u32 p1_mux_state; +}; diff --git a/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/sys_proto.h new file mode 100644 index 000000000..4675dc3c5 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/sys_proto.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 Vladimir Zapolskiy + */ + +#ifndef _LPC32XX_SYS_PROTO_H +#define _LPC32XX_SYS_PROTO_H + +#include + +void lpc32xx_uart_init(unsigned int uart_id); +void lpc32xx_dma_init(void); +void lpc32xx_mac_init(void); +void lpc32xx_mlc_nand_init(void); +void lpc32xx_slc_nand_init(void); +void lpc32xx_i2c_init(unsigned int devnum); +void lpc32xx_ssp_init(void); +void lpc32xx_usb_init(void); +#if defined(CONFIG_SPL_BUILD) +void ddr_init(const struct emc_dram_settings *dram); +#endif +#endif /* _LPC32XX_SYS_PROTO_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/timer.h b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/timer.h new file mode 100644 index 000000000..302bd6bab --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/timer.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 by Vladimir Zapolskiy + */ + +#ifndef _LPC32XX_TIMER_H +#define _LPC32XX_TIMER_H + +#include + +/* Timer/Counter Registers */ +struct timer_regs { + u32 ir; /* Interrupt Register */ + u32 tcr; /* Timer Control Register */ + u32 tc; /* Timer Counter */ + u32 pr; /* Prescale Register */ + u32 pc; /* Prescale Counter */ + u32 mcr; /* Match Control Register */ + u32 mr[4]; /* Match Registers */ + u32 ccr; /* Capture Control Register */ + u32 cr[4]; /* Capture Registers */ + u32 emr; /* External Match Register */ + u32 reserved[12]; + u32 ctcr; /* Count Control Register */ +}; + +/* Timer/Counter Interrupt Register bits */ +#define TIMER_IR_CR(n) (1 << ((n) + 4)) +#define TIMER_IR_MR(n) (1 << (n)) + +/* Timer/Counter Timer Control Register bits */ +#define TIMER_TCR_COUNTER_RESET (1 << 1) +#define TIMER_TCR_COUNTER_ENABLE (1 << 0) +#define TIMER_TCR_COUNTER_DISABLE (0 << 0) + +/* Timer/Counter Match Control Register bits */ +#define TIMER_MCR_STOP(n) (1 << (3 * (n) + 2)) +#define TIMER_MCR_RESET(n) (1 << (3 * (n) + 1)) +#define TIMER_MCR_INTERRUPT(n) (1 << (3 * (n))) + +/* Timer/Counter Capture Control Register bits */ +#define TIMER_CCR_INTERRUPT(n) (1 << (3 * (n) + 2)) +#define TIMER_CCR_FALLING_EDGE(n) (1 << (3 * (n) + 1)) +#define TIMER_CCR_RISING_EDGE(n) (1 << (3 * (n))) + +/* Timer/Counter External Match Register bits */ +#define TIMER_EMR_EMC_TOGGLE(n) (0x3 << (2 * (n) + 4)) +#define TIMER_EMR_EMC_SET(n) (0x2 << (2 * (n) + 4)) +#define TIMER_EMR_EMC_CLEAR(n) (0x1 << (2 * (n) + 4)) +#define TIMER_EMR_EMC_NOTHING(n) (0x0 << (2 * (n) + 4)) +#define TIMER_EMR_EM(n) (1 << (n)) + +/* Timer/Counter Count Control Register bits */ +#define TIMER_CTCR_INPUT(n) ((n) << 2) +#define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0) +#define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0) +#define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0) +#define TIMER_CTCR_MODE_TIMER (0x0 << 0) + +#endif /* _LPC32XX_TIMER_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/uart.h b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/uart.h new file mode 100644 index 000000000..8ffd8676f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/uart.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 by Vladimir Zapolskiy + */ + +#ifndef _LPC32XX_UART_H +#define _LPC32XX_UART_H + +#include + +/* 14-clock UART Registers */ +struct hsuart_regs { + union { + u32 rx; /* Receiver FIFO */ + u32 tx; /* Transmitter FIFO */ + }; + u32 level; /* FIFO Level Register */ + u32 iir; /* Interrupt ID Register */ + u32 ctrl; /* Control Register */ + u32 rate; /* Rate Control Register */ +}; + +/* 14-clock UART Receiver FIFO Register bits */ +#define HSUART_RX_BREAK (1 << 10) +#define HSUART_RX_ERROR (1 << 9) +#define HSUART_RX_EMPTY (1 << 8) +#define HSUART_RX_DATA (0xff << 0) + +/* 14-clock UART Level Register bits */ +#define HSUART_LEVEL_TX (0xff << 8) +#define HSUART_LEVEL_RX (0xff << 0) + +/* 14-clock UART Interrupt Identification Register bits */ +#define HSUART_IIR_TX_INT_SET (1 << 6) +#define HSUART_IIR_RX_OE (1 << 5) +#define HSUART_IIR_BRK (1 << 4) +#define HSUART_IIR_FE (1 << 3) +#define HSUART_IIR_RX_TIMEOUT (1 << 2) +#define HSUART_IIR_RX_TRIG (1 << 1) +#define HSUART_IIR_TX (1 << 0) + +/* 14-clock UART Control Register bits */ +#define HSUART_CTRL_HRTS_INV (1 << 21) +#define HSUART_CTRL_HRTS_TRIG_48 (0x3 << 19) +#define HSUART_CTRL_HRTS_TRIG_32 (0x2 << 19) +#define HSUART_CTRL_HRTS_TRIG_16 (0x1 << 19) +#define HSUART_CTRL_HRTS_TRIG_8 (0x0 << 19) +#define HSUART_CTRL_HRTS_EN (1 << 18) +#define HSUART_CTRL_TMO_16 (0x3 << 16) +#define HSUART_CTRL_TMO_8 (0x2 << 16) +#define HSUART_CTRL_TMO_4 (0x1 << 16) +#define HSUART_CTRL_TMO_DISABLED (0x0 << 16) +#define HSUART_CTRL_HCTS_INV (1 << 15) +#define HSUART_CTRL_HCTS_EN (1 << 14) +#define HSUART_CTRL_HSU_OFFSET(n) ((n) << 9) +#define HSUART_CTRL_HSU_BREAK (1 << 8) +#define HSUART_CTRL_HSU_ERR_INT_EN (1 << 7) +#define HSUART_CTRL_HSU_RX_INT_EN (1 << 6) +#define HSUART_CTRL_HSU_TX_INT_EN (1 << 5) +#define HSUART_CTRL_HSU_RX_TRIG_48 (0x5 << 2) +#define HSUART_CTRL_HSU_RX_TRIG_32 (0x4 << 2) +#define HSUART_CTRL_HSU_RX_TRIG_16 (0x3 << 2) +#define HSUART_CTRL_HSU_RX_TRIG_8 (0x2 << 2) +#define HSUART_CTRL_HSU_RX_TRIG_4 (0x1 << 2) +#define HSUART_CTRL_HSU_RX_TRIG_1 (0x0 << 2) +#define HSUART_CTRL_HSU_TX_TRIG_16 (0x3 << 0) +#define HSUART_CTRL_HSU_TX_TRIG_8 (0x2 << 0) +#define HSUART_CTRL_HSU_TX_TRIG_4 (0x1 << 0) +#define HSUART_CTRL_HSU_TX_TRIG_0 (0x0 << 0) + +/* UART Control Registers */ +struct uart_ctrl_regs { + u32 ctrl; /* Control Register */ + u32 clkmode; /* Clock Mode Register */ + u32 loop; /* Loopback Control Register */ +}; + +/* UART Control Register bits */ +#define UART_CTRL_UART3_MD_CTRL (1 << 11) +#define UART_CTRL_HDPX_INV (1 << 10) +#define UART_CTRL_HDPX_EN (1 << 9) +#define UART_CTRL_UART6_IRDA (1 << 5) +#define UART_CTRL_IR_TX6_INV (1 << 4) +#define UART_CTRL_IR_RX6_INV (1 << 3) +#define UART_CTRL_IR_RX_LENGTH (1 << 2) +#define UART_CTRL_IR_TX_LENGTH (1 << 1) +#define UART_CTRL_UART5_USB_MODE (1 << 0) + +/* UART Clock Mode Register bits */ +#define UART_CLKMODE_STATX(n) (1 << ((n) + 16)) +#define UART_CLKMODE_STAT (1 << 14) +#define UART_CLKMODE_MASK(n) (0x3 << (2 * (n) - 2)) +#define UART_CLKMODE_AUTO(n) (0x2 << (2 * (n) - 2)) +#define UART_CLKMODE_ON(n) (0x1 << (2 * (n) - 2)) +#define UART_CLKMODE_OFF(n) (0x0 << (2 * (n) - 2)) + +/* UART Loopback Control Register bits */ +#define UART_LOOPBACK(n) (1 << ((n) - 1)) + +#endif /* _LPC32XX_UART_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/wdt.h b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/wdt.h new file mode 100644 index 000000000..dd0fc1682 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/wdt.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 by Vladimir Zapolskiy + */ + +#ifndef _LPC32XX_WDT_H +#define _LPC32XX_WDT_H + +#include + +/* Watchdog Timer Registers */ +struct wdt_regs { + u32 isr; /* Interrupt Status Register */ + u32 ctrl; /* Control Register */ + u32 counter; /* Counter Value Register */ + u32 mctrl; /* Match Control Register */ + u32 match0; /* Match 0 Register */ + u32 emr; /* External Match Control Register */ + u32 pulse; /* Reset Pulse Length Register */ + u32 res; /* Reset Source Register */ +}; + +/* Watchdog Timer Control Register bits */ +#define WDTIM_CTRL_PAUSE_EN (1 << 2) +#define WDTIM_CTRL_RESET_COUNT (1 << 1) +#define WDTIM_CTRL_COUNT_ENAB (1 << 0) + +/* Watchdog Timer Match Control Register bits */ +#define WDTIM_MCTRL_RESFRC2 (1 << 6) +#define WDTIM_MCTRL_RESFRC1 (1 << 5) +#define WDTIM_MCTRL_M_RES2 (1 << 4) +#define WDTIM_MCTRL_M_RES1 (1 << 3) +#define WDTIM_MCTRL_STOP_COUNT0 (1 << 2) +#define WDTIM_MCTRL_RESET_COUNT0 (1 << 1) +#define WDTIM_MCTRL_MR0_INT (1 << 0) + +#endif /* _LPC32XX_WDT_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-ls102xa/clock.h b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/clock.h new file mode 100644 index 000000000..01978c08f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/clock.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + */ + +#ifndef __ASM_ARCH_LS102XA_CLOCK_H_ +#define __ASM_ARCH_LS102XA_CLOCK_H_ + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_UART_CLK, + MXC_I2C_CLK, + MXC_DSPI_CLK, +}; + +unsigned int mxc_get_clock(enum mxc_clock clk); +ulong get_ddr_freq(ulong); +uint get_svr(void); + +#endif /* __ASM_ARCH_LS102XA_CLOCK_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-ls102xa/config.h b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/config.h new file mode 100644 index 000000000..3884948a2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/config.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014, Freescale Semiconductor + */ + +#ifndef _ASM_ARMV7_LS102XA_CONFIG_ +#define _ASM_ARMV7_LS102XA_CONFIG_ + +#define OCRAM_BASE_ADDR 0x10000000 +#define OCRAM_SIZE 0x00010000 +#define OCRAM_BASE_S_ADDR 0x10010000 +#define OCRAM_S_SIZE 0x00010000 + +#define CONFIG_SYS_IMMR 0x01000000 +#define CONFIG_SYS_DCSRBAR 0x20000000 + +#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) +#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000) + +#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000) +#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) +#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) +#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) +#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) +#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) +#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) +#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) +#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) +#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) +#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) +#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) +#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) +#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000) +#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) + +#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000 +#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000 +#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 +#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 +#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000 +#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000 + +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) + +#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000) + +#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) +#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) +#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) + +#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) + +#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) +#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) + +#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) + +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) + +#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL +#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL +#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL +#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */ +/* + * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR) + * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr. + */ +#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \ + CONFIG_SYS_PCIE1_VIRT_ADDR) +#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ + CONFIG_SYS_PCIE2_VIRT_ADDR) + +/* SATA */ +#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#ifdef CONFIG_DDR_SPD +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE +#endif + +#define CONFIG_SYS_FSL_IFC_BE +#define CONFIG_SYS_FSL_ESDHC_BE +#define CONFIG_SYS_FSL_WDOG_BE +#define CONFIG_SYS_FSL_DSPI_BE +#define CONFIG_SYS_FSL_DCU_BE +#define CONFIG_SYS_FSL_SEC_MON_LE +#define CONFIG_SYS_FSL_SFP_VER_3_2 +#define CONFIG_SYS_FSL_SFP_BE +#define CONFIG_SYS_FSL_SRK_LE + +#define DCU_LAYER_MAX_NUM 16 + +#ifdef CONFIG_ARCH_LS1021A +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 +#else +#error SoC not defined +#endif + +#define FSL_IFC_COMPAT "fsl,ifc" +#define FSL_QSPI_COMPAT "fsl,ls1021a-qspi" +#define FSL_DSPI_COMPAT "fsl,ls1021a-v1.0-dspi" + +#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h new file mode 100644 index 000000000..d99a6f318 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __FSL_SERDES_H +#define __FSL_SERDES_H + +#include + +enum srds_prtcl { + /* + * Nobody will check whether the device 'NONE' has been configured, + * So use it to indicate if the serdes_prtcl_map has been initialized. + */ + NONE = 0, + PCIE1, + PCIE2, + SATA1, + SGMII_TSEC1, + SGMII_TSEC2, +}; + +enum srds { + FSL_SRDS_1 = 0, + FSL_SRDS_2 = 1, +}; + +int is_serdes_configured(enum srds_prtcl device); +void fsl_serdes_init(void); +const char *serdes_clock_to_string(u32 clock); + +int serdes_get_first_lane(u32 sd, enum srds_prtcl device); +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); + +#endif /* __FSL_SERDES_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-ls102xa/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/gpio.h new file mode 100644 index 000000000..517652b5d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/gpio.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +/* + * Dummy header file to enable CONFIG_OF_CONTROL. + * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. + * It includes via , so those SoCs that enable + * OF_CONTROL must have arch/gpio.h. + */ + +#ifndef __ASM_ARCH_LS102XA_GPIO_H_ +#define __ASM_ARCH_LS102XA_GPIO_H_ + +struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; + u32 gpibe; +}; + +struct mpc8xxx_gpio_plat { + ulong addr; + ulong size; + uint ngpios; +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h new file mode 100644 index 000000000..f2ba18234 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -0,0 +1,432 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __ASM_ARCH_LS102XA_IMMAP_H_ +#define __ASM_ARCH_LS102XA_IMMAP_H_ +#include + +#define SVR_MAJ(svr) (((svr) >> 4) & 0xf) +#define SVR_MIN(svr) (((svr) >> 0) & 0xf) +#define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff) +#define IS_E_PROCESSOR(svr) (svr & 0x80000) +#define IS_SVR_REV(svr, maj, min) \ + ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min)) + +#define SOC_VER_SLS1020 0x00 +#define SOC_VER_LS1020 0x10 +#define SOC_VER_LS1021 0x11 +#define SOC_VER_LS1022 0x12 + +#define SOC_MAJOR_VER_1_0 0x1 +#define SOC_MAJOR_VER_2_0 0x2 + +#define CCSR_BRR_OFFSET 0xe4 +#define CCSR_SCRATCHRW1_OFFSET 0x200 + +#define RCWSR0_SYS_PLL_RAT_SHIFT 25 +#define RCWSR0_SYS_PLL_RAT_MASK 0x1f +#define RCWSR0_MEM_PLL_RAT_SHIFT 16 +#define RCWSR0_MEM_PLL_RAT_MASK 0x3f + +#define RCWSR4_SRDS1_PRTCL_SHIFT 24 +#define RCWSR4_SRDS1_PRTCL_MASK 0xff000000 + +#define TIMER_COMP_VAL 0xffffffffffffffffull +#define ARCH_TIMER_CTRL_ENABLE (1 << 0) +#define SYS_COUNTER_CTRL_ENABLE (1 << 24) + +#define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000 +#define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000 + +#define DCFG_DCSR_PORCR1 0 + +/* + * Define default values for some CCSR macros to make header files cleaner + * + * To completely disable CCSR relocation in a board header file, define + * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS + * to a value that is the same as CONFIG_SYS_CCSRBAR. + */ + +#ifdef CONFIG_SYS_CCSRBAR_PHYS +#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly." +#endif + +#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#undef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif + +#ifndef CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf +#else +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR +#endif + +#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CONFIG_SYS_CCSRBAR_PHYS_LOW) + +struct sys_info { + unsigned long freq_processor[CONFIG_MAX_CPUS]; + unsigned long freq_systembus; + unsigned long freq_ddrbus; + unsigned long freq_localbus; +}; + +#define CCSR_DEVDISR1_QE 0x00000001 + +/* Device Configuration and Pin Control */ +struct ccsr_gur { + u32 porsr1; /* POR status 1 */ + u32 porsr2; /* POR status 2 */ + u8 res_008[0x20-0x8]; + u32 gpporcr1; /* General-purpose POR configuration */ + u32 gpporcr2; + u32 dcfg_fusesr; /* Fuse status register */ + u8 res_02c[0x70-0x2c]; + u32 devdisr; /* Device disable control */ + u32 devdisr2; /* Device disable control 2 */ + u32 devdisr3; /* Device disable control 3 */ + u32 devdisr4; /* Device disable control 4 */ + u32 devdisr5; /* Device disable control 5 */ + u8 res_084[0x94-0x84]; + u32 coredisru; /* uppper portion for support of 64 cores */ + u32 coredisrl; /* lower portion for support of 64 cores */ + u8 res_09c[0xa4-0x9c]; + u32 svr; /* System version */ + u8 res_0a8[0xb0-0xa8]; + u32 rstcr; /* Reset control */ + u32 rstrqpblsr; /* Reset request preboot loader status */ + u8 res_0b8[0xc0-0xb8]; + u32 rstrqmr1; /* Reset request mask */ + u8 res_0c4[0xc8-0xc4]; + u32 rstrqsr1; /* Reset request status */ + u8 res_0cc[0xd4-0xcc]; + u32 rstrqwdtmrl; /* Reset request WDT mask */ + u8 res_0d8[0xdc-0xd8]; + u32 rstrqwdtsrl; /* Reset request WDT status */ + u8 res_0e0[0xe4-0xe0]; + u32 brrl; /* Boot release */ + u8 res_0e8[0x100-0xe8]; + u32 rcwsr[16]; /* Reset control word status */ +#define RCW_SB_EN_REG_INDEX 7 +#define RCW_SB_EN_MASK 0x00200000 + u8 res_140[0x200-0x140]; + u32 scratchrw[4]; /* Scratch Read/Write */ + u8 res_210[0x300-0x210]; + u32 scratchw1r[4]; /* Scratch Read (Write once) */ + u8 res_310[0x400-0x310]; + u32 crstsr; + u8 res_404[0x550-0x404]; + u32 sataliodnr; + u8 res_554[0x604-0x554]; + u32 pamubypenr; + u32 dmacr1; + u8 res_60c[0x740-0x60c]; /* add more registers when needed */ + u32 tp_ityp[64]; /* Topology Initiator Type Register */ + struct { + u32 upper; + u32 lower; + } tp_cluster[1]; /* Core Cluster n Topology Register */ + u8 res_848[0xe60-0x848]; + u32 ddrclkdr; + u8 res_e60[0xe68-0xe64]; + u32 ifcclkdr; + u8 res_e68[0xe80-0xe6c]; + u32 sdhcpcr; +}; + +#define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00 +#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 +#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 +#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 +#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 +#define SCFG_PIXCLKCR_PXCKEN 0x80000000 +#define SCFG_QSPI_CLKSEL 0x50100000 +#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 +#define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000 +#define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000 +#define SCFG_SNPCNFGCR_USB3_RD_WR 0x00300000 +#define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000 +#define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000 +#define SCFG_ENDIANCR_LE 0x80000000 +#define SCFG_DPSLPCR_WDRR_EN 0x00000001 +#define SCFG_PMCINTECR_LPUART 0x40000000 +#define SCFG_PMCINTECR_FTM 0x20000000 +#define SCFG_PMCINTECR_GPIO 0x10000000 +#define SCFG_PMCINTECR_IRQ0 0x08000000 +#define SCFG_PMCINTECR_IRQ1 0x04000000 +#define SCFG_PMCINTECR_ETSECRXG0 0x00800000 +#define SCFG_PMCINTECR_ETSECRXG1 0x00400000 +#define SCFG_PMCINTECR_ETSECERRG0 0x00080000 +#define SCFG_PMCINTECR_ETSECERRG1 0x00040000 +#define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000 + +#define SCFG_BASE 0x01570000 +#define SCFG_USB3PRM1CR 0x070 +#define SCFG_USB_TXVREFTUNE 0x9 +#define SCFG_USB_SQRXTUNE_MASK 0x7 +#define SCFG_USB3PRM2CR 0x074 +#define SCFG_USB_PCSTXSWINGFULL_MASK 0x0000FE00 +#define SCFG_USB_PCSTXSWINGFULL_VAL 0x00008E00 + +#define USB_PHY_BASE 0x08510000 +#define USB_PHY_RX_OVRD_IN_HI 0x200c +#define USB_PHY_RX_EQ_VAL_1 0x0000 +#define USB_PHY_RX_EQ_VAL_2 0x8000 +#define USB_PHY_RX_EQ_VAL_3 0x8004 +#define USB_PHY_RX_EQ_VAL_4 0x800C + +/* Supplemental Configuration Unit */ +struct ccsr_scfg { + u32 dpslpcr; + u32 resv0[2]; + u32 etsecclkdpslpcr; + u32 resv1[5]; + u32 fuseovrdcr; + u32 pixclkcr; + u32 resv2[5]; + u32 spimsicr; + u32 resv3[6]; + u32 pex1pmwrcr; + u32 pex1pmrdsr; + u32 resv4[3]; + u32 usb3prm1cr; + u32 usb4prm2cr; + u32 pex1rdmsgpldlsbsr; + u32 pex1rdmsgpldmsbsr; + u32 pex2rdmsgpldlsbsr; + u32 pex2rdmsgpldmsbsr; + u32 pex1rdmmsgrqsr; + u32 pex2rdmmsgrqsr; + u32 spimsiclrcr; + u32 pexmscportsr[2]; + u32 pex2pmwrcr; + u32 resv5[24]; + u32 mac1_streamid; + u32 mac2_streamid; + u32 mac3_streamid; + u32 pex1_streamid; + u32 pex2_streamid; + u32 dma_streamid; + u32 sata_streamid; + u32 usb3_streamid; + u32 qe_streamid; + u32 sdhc_streamid; + u32 adma_streamid; + u32 letechsftrstcr; + u32 core0_sft_rst; + u32 core1_sft_rst; + u32 resv6[1]; + u32 usb_hi_addr; + u32 etsecclkadjcr; + u32 sai_clk; + u32 resv7[1]; + u32 dcu_streamid; + u32 usb2_streamid; + u32 ftm_reset; + u32 altcbar; + u32 qspi_cfg; + u32 pmcintecr; + u32 pmcintlecr; + u32 pmcintsr; + u32 qos1; + u32 qos2; + u32 qos3; + u32 cci_cfg; + u32 endiancr; + u32 etsecdmamcr; + u32 usb3prm3cr; + u32 resv9[1]; + u32 debug_streamid; + u32 resv10[5]; + u32 snpcnfgcr; + u32 hrstcr; + u32 intpcr; + u32 resv12[20]; + u32 scfgrevcr; + u32 coresrencr; + u32 pex2pmrdsr; + u32 eddrtqcfg; + u32 ddrc2cr; + u32 ddrc3cr; + u32 ddrc4cr; + u32 ddrgcr; + u32 resv13[120]; + u32 qeioclkcr; + u32 etsecmcr; + u32 sdhciovserlcr; + u32 resv14[61]; + u32 sparecr[8]; + u32 resv15[248]; + u32 core0sftrstsr; + u32 clusterpmcr; +}; + +/* Clocking */ +struct ccsr_clk { + struct { + u32 clkcncsr; /* core cluster n clock control status */ + u8 res_004[0x1c]; + } clkcsr[2]; + u8 res_040[0x7c0]; /* 0x100 */ + struct { + u32 pllcngsr; + u8 res_804[0x1c]; + } pllcgsr[2]; + u8 res_840[0x1c0]; + u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ + u8 res_a04[0x1fc]; + u32 pllpgsr; /* 0xc00 Platform PLL General Status */ + u8 res_c04[0x1c]; + u32 plldgsr; /* 0xc20 DDR PLL General Status */ + u8 res_c24[0x3dc]; +}; + +/* System Counter */ +struct sctr_regs { + u32 cntcr; + u32 cntsr; + u32 cntcv1; + u32 cntcv2; + u32 resv1[4]; + u32 cntfid0; + u32 cntfid1; + u32 resv2[1002]; + u32 counterid[12]; +}; + +#define MAX_SERDES 1 +#define SRDS_MAX_LANES 4 +#define SRDS_MAX_BANK 2 + +#define SRDS_RSTCTL_RST 0x80000000 +#define SRDS_RSTCTL_RSTDONE 0x40000000 +#define SRDS_RSTCTL_RSTERR 0x20000000 +#define SRDS_RSTCTL_SWRST 0x10000000 +#define SRDS_RSTCTL_SDEN 0x00000020 +#define SRDS_RSTCTL_SDRST_B 0x00000040 +#define SRDS_RSTCTL_PLLRST_B 0x00000080 +#define SRDS_PLLCR0_POFF 0x80000000 +#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 +#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 +#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 +#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 +#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 +#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 +#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 +#define SRDS_PLLCR0_PLL_LCK 0x00800000 +#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 +#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 +#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 +#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 +#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 +#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 +#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 +#define SRDS_PLLCR1_PLL_BWSEL 0x08000000 + +struct ccsr_serdes { + struct { + u32 rstctl; /* Reset Control Register */ + + u32 pllcr0; /* PLL Control Register 0 */ + + u32 pllcr1; /* PLL Control Register 1 */ + u32 res_0c; /* 0x00c */ + u32 pllcr3; + u32 pllcr4; + u8 res_18[0x20-0x18]; + } bank[2]; + u8 res_40[0x90-0x40]; + u32 srdstcalcr; /* 0x90 TX Calibration Control */ + u8 res_94[0xa0-0x94]; + u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ + u8 res_a4[0xb0-0xa4]; + u32 srdsgr0; /* 0xb0 General Register 0 */ + u8 res_b4[0xe0-0xb4]; + u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ + u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ + u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ + u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ + u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ + u8 res_f4[0x100-0xf4]; + struct { + u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ + u8 res_104[0x120-0x104]; + } srdslnpssr[4]; + u8 res_180[0x300-0x180]; + u32 srdspexeqcr; + u32 srdspexeqpcr[11]; + u8 res_330[0x400-0x330]; + u32 srdspexapcr; + u8 res_404[0x440-0x404]; + u32 srdspexbpcr; + u8 res_444[0x800-0x444]; + struct { + u32 gcr0; /* 0x800 General Control Register 0 */ + u32 gcr1; /* 0x804 General Control Register 1 */ + u32 gcr2; /* 0x808 General Control Register 2 */ + u32 sscr0; + u32 recr0; /* 0x810 Receive Equalization Control */ + u32 recr1; + u32 tecr0; /* 0x818 Transmit Equalization Control */ + u32 sscr1; + u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ + u8 res_824[0x83c-0x824]; + u32 tcsr3; + } lane[4]; /* Lane A, B, C, D, E, F, G, H */ + u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ +}; + +#define RCPM_POWMGTCSR 0x130 +#define RCPM_POWMGTCSR_SERDES_PW 0x80000000 +#define RCPM_POWMGTCSR_LPM20_REQ 0x00100000 +#define RCPM_POWMGTCSR_LPM20_ST 0x00000200 +#define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100 +#define RCPM_IPPDEXPCR0 0x140 +#define RCPM_IPPDEXPCR0_ETSEC 0x80000000 +#define RCPM_IPPDEXPCR0_GPIO 0x00000040 +#define RCPM_IPPDEXPCR1 0x144 +#define RCPM_IPPDEXPCR1_LPUART 0x40000000 +#define RCPM_IPPDEXPCR1_FLEXTIMER 0x20000000 +#define RCPM_IPPDEXPCR1_OCRAM1 0x10000000 +#define RCPM_NFIQOUTR 0x15c +#define RCPM_NIRQOUTR 0x16c +#define RCPM_DSIMSKR 0x18c +#define RCPM_CLPCL10SETR 0x1c4 +#define RCPM_CLPCL10SETR_C0 0x00000001 + +struct ccsr_rcpm { + u8 rev1[0x4c]; + u32 twaitsr; + u8 rev2[0xe0]; + u32 powmgtcsr; + u8 rev3[0xc]; + u32 ippdexpcr0; + u32 ippdexpcr1; + u8 rev4[0x14]; + u32 nfiqoutr; + u8 rev5[0xc]; + u32 nirqoutr; + u8 rev6[0x1c]; + u32 dsimskr; + u8 rev7[0x34]; + u32 clpcl10setr; +}; + +uint get_svr(void); + +#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-ls102xa/imx-regs.h b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/imx-regs.h new file mode 100644 index 000000000..64853d897 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/imx-regs.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + */ + +#ifndef __ASM_ARCH_IMX_REGS_H__ +#define __ASM_ARCH_IMX_REGS_H__ + +#define I2C_QUIRK_REG /* enable 8-bit driver */ + +#endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h new file mode 100644 index 000000000..5d6a4e76b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __FSL_LS102XA_DEVDIS_H_ +#define __FSL_LS102XA_DEVDIS_H_ + +#include + +const struct devdis_table devdis_tbl[] = { + { "pbl", 0x0, 0x80000000 }, /* PBL */ + { "esdhc", 0x0, 0x20000000 }, /* eSDHC */ + { "qdma", 0x0, 0x800000 }, /* qDMA */ + { "edma", 0x0, 0x400000 }, /* eDMA */ + { "usb3", 0x0, 0x84000 }, /* USB3.0 controller and PHY*/ + { "usb2", 0x0, 0x40000 }, /* USB2.0 controller */ + { "sata", 0x0, 0x8000 }, /* SATA */ + { "sec", 0x0, 0x200 }, /* SEC */ + { "dcu", 0x0, 0x2 }, /* Display controller Unit */ + { "qe", 0x0, 0x1 }, /* QUICC Engine */ + { "etsec1", 0x1, 0x80000000 }, /* eTSEC1 controller */ + { "etesc2", 0x1, 0x40000000 }, /* eTSEC2 controller */ + { "etsec3", 0x1, 0x20000000 }, /* eTSEC3 controller */ + { "pex1", 0x2, 0x80000000 }, /* PCIE controller 1 */ + { "pex2", 0x2, 0x40000000 }, /* PCIE controller 2 */ + { "duart1", 0x3, 0x20000000 }, /* DUART1 */ + { "duart2", 0x3, 0x10000000 }, /* DUART2 */ + { "qspi", 0x3, 0x8000000 }, /* QSPI */ + { "ddr", 0x4, 0x80000000 }, /* DDR */ + { "ocram1", 0x4, 0x8000000 }, /* OCRAM1 */ + { "ifc", 0x4, 0x800000 }, /* IFC */ + { "gpio", 0x4, 0x400000 }, /* GPIO */ + { "dbg", 0x4, 0x200000 }, /* DBG */ + { "can1", 0x4, 0x80000 }, /* FlexCAN1 */ + { "can2_4", 0x4, 0x40000 }, /* FlexCAN2_3_4 */ + { "ftm2_8", 0x4, 0x20000 }, /* FlexTimer2_3_4_5_6_7_8 */ + { "secmon", 0x4, 0x4000 }, /* Security Monitor */ + { "wdog1_2", 0x4, 0x400 }, /* WatchDog1_2 */ + { "i2c2_3", 0x4, 0x200 }, /* I2C2_3 */ + { "sai1_4", 0x4, 0x100 }, /* SAI1_2_3_4 */ + { "lpuart2_6", 0x4, 0x80 }, /* LPUART2_3_4_5_6 */ + { "dspi1_2", 0x4, 0x40 }, /* DSPI1_2 */ + { "asrc", 0x4, 0x20 }, /* ASRC */ + { "spdif", 0x4, 0x10 }, /* SPDIF */ + { "i2c1", 0x4, 0x4 }, /* I2C1 */ + { "lpuart1", 0x4, 0x2 }, /* LPUART1 */ + { "ftm1", 0x4, 0x1 }, /* FlexTimer1 */ +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h new file mode 100644 index 000000000..1fde8bce5 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __FSL_LS102XA_SOC_H +#define __FSL_LS102XA_SOC_H + +unsigned int get_soc_major_rev(void); +int arch_soc_init(void); +int ls102xa_smmu_stream_id_init(void); + +void erratum_a008850_post(void); + +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 +void erratum_a010315(void); +#endif + +#endif /* __FSL_LS102XA_SOC_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h new file mode 100644 index 000000000..93b0a2609 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __FSL_LS102XA_STREAM_ID_H_ +#define __FSL_LS102XA_STREAM_ID_H_ + +#include + +#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \ + { .compat = name, \ + .id = { idA }, .num_ids = 1, \ + .reg_offset = off + CONFIG_SYS_IMMR, \ + .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + } + +#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \ + { .compat = name, \ + .id = { idA, idB }, .num_ids = 2, \ + .reg_offset = off + CONFIG_SYS_IMMR, \ + .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + } + +/* + * handle both old and new versioned SEC properties: + * "fsl,secX.Y" became "fsl,sec-vX.Y" during development + */ +#define SET_SEC_JR_LIODN_ENTRY(jrnum, liodnA, liodnB) \ + SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \ + offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \ + SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\ + offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum) + +/* This is a bit evil since we treat rtic param as both a string & hex value */ +#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \ + SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \ + liodnA, \ + offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \ + SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \ + liodnA, \ + offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)) + +#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \ + SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \ + offsetof(ccsr_sec_t, decoliodnr[num].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, 0) + +struct liodn_id_table { + const char *compat; + u32 id[2]; + u8 num_ids; + phys_addr_t compat_offset; + unsigned long reg_offset; +}; + +struct smmu_stream_id { + uint16_t offset; + uint16_t stream_id; + char dev_name[32]; +}; + +void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size); +void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-ls102xa/ns_access.h b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/ns_access.h new file mode 100644 index 000000000..b6daf32e5 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/ns_access.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __FSL_NS_ACCESS_H_ +#define __FSL_NS_ACCESS_H_ + +enum csu_cslx_ind { + CSU_CSLX_PCIE2_IO = 0, + CSU_CSLX_PCIE1_IO, + CSU_CSLX_MG2TPR_IP, + CSU_CSLX_IFC_MEM, + CSU_CSLX_OCRAM, + CSU_CSLX_GIC, + CSU_CSLX_PCIE1, + CSU_CSLX_OCRAM2, + CSU_CSLX_QSPI_MEM, + CSU_CSLX_PCIE2, + CSU_CSLX_SATA, + CSU_CSLX_USB3, + CSU_CSLX_SERDES = 32, + CSU_CSLX_QDMA, + CSU_CSLX_LPUART2, + CSU_CSLX_LPUART1, + CSU_CSLX_LPUART4, + CSU_CSLX_LPUART3, + CSU_CSLX_LPUART6, + CSU_CSLX_LPUART5, + CSU_CSLX_DSPI2 = 40, + CSU_CSLX_DSPI1, + CSU_CSLX_QSPI, + CSU_CSLX_ESDHC, + CSU_CSLX_2D_ACE, + CSU_CSLX_IFC, + CSU_CSLX_I2C1, + CSU_CSLX_USB2, + CSU_CSLX_I2C3, + CSU_CSLX_I2C2, + CSU_CSLX_DUART2 = 50, + CSU_CSLX_DUART1, + CSU_CSLX_WDT2, + CSU_CSLX_WDT1, + CSU_CSLX_EDMA, + CSU_CSLX_SYS_CNT, + CSU_CSLX_DMA_MUX2, + CSU_CSLX_DMA_MUX1, + CSU_CSLX_DDR, + CSU_CSLX_QUICC, + CSU_CSLX_DCFG_CCU_RCPM = 60, + CSU_CSLX_SECURE_BOOTROM, + CSU_CSLX_SFP, + CSU_CSLX_TMU, + CSU_CSLX_SECURE_MONITOR, + CSU_CSLX_RESERVED0, + CSU_CSLX_ETSEC1, + CSU_CSLX_SEC5_5, + CSU_CSLX_ETSEC3, + CSU_CSLX_ETSEC2, + CSU_CSLX_GPIO2 = 70, + CSU_CSLX_GPIO1, + CSU_CSLX_GPIO4, + CSU_CSLX_GPIO3, + CSU_CSLX_PLATFORM_CONT, + CSU_CSLX_CSU, + CSU_CSLX_ASRC, + CSU_CSLX_SPDIF, + CSU_CSLX_FLEXCAN2, + CSU_CSLX_FLEXCAN1, + CSU_CSLX_FLEXCAN4 = 80, + CSU_CSLX_FLEXCAN3, + CSU_CSLX_SAI2, + CSU_CSLX_SAI1, + CSU_CSLX_SAI4, + CSU_CSLX_SAI3, + CSU_CSLX_FTM2, + CSU_CSLX_FTM1, + CSU_CSLX_FTM4, + CSU_CSLX_FTM3, + CSU_CSLX_FTM6 = 90, + CSU_CSLX_FTM5, + CSU_CSLX_FTM8, + CSU_CSLX_FTM7, + CSU_CSLX_EPU, + CSU_CSLX_COP_DCSR, + CSU_CSLX_DDI, + CSU_CSLX_GDI, + CSU_CSLX_RESERVED1, + CSU_CSLX_USB3_PHY = 116, + CSU_CSLX_RESERVED2, + CSU_CSLX_MAX, +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-ls102xa/soc.h b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/soc.h new file mode 100644 index 000000000..e69de29bb diff --git a/roms/u-boot/arch/arm/include/asm/arch-ls102xa/spl.h b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/spl.h new file mode 100644 index 000000000..990c74d75 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/spl.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __ASM_ARCH_SPL_H__ +#define __ASM_ARCH_SPL_H__ + +#define BOOT_DEVICE_NONE 0 +#define BOOT_DEVICE_XIP 1 +#define BOOT_DEVICE_XIPWAIT 2 +#define BOOT_DEVICE_NAND 3 +#define BOOT_DEVICE_ONENAND 4 +#define BOOT_DEVICE_MMC1 5 +#define BOOT_DEVICE_MMC2 6 +#define BOOT_DEVICE_MMC2_2 7 +#define BOOT_DEVICE_SPI 10 + +#endif /* __ASM_ARCH_SPL_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-ls102xa/svr.h b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/svr.h new file mode 100644 index 000000000..52b27e2d6 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-ls102xa/svr.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#ifndef _ASM_LS102X_SVR_H_ +#define _ASM_LS102X_SVR_H_ + +#define SVR_LS102XA 0 +#define SVR_VAR_PER_SHIFT 8 +#define SVR_LS102XA_MASK 0x700 + +#endif /* _ASM_LS102X_SVR_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mediatek/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-mediatek/gpio.h new file mode 100644 index 000000000..4ea102063 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mediatek/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef __MEDIATEK_GPIO_H +#define __MEDIATEK_GPIO_H + +#endif /* __MEDIATEK_GPIO_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mediatek/misc.h b/roms/u-boot/arch/arm/include/asm/arch-mediatek/misc.h new file mode 100644 index 000000000..2530e78a5 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mediatek/misc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef __MEDIATEK_MISC_H_ +#define __MEDIATEK_MISC_H_ + +#define VER_BASE 0x08000000 +#define VER_SIZE 0x10 + +#define APHW_CODE 0x00 +#define APHW_SUBCODE 0x04 +#define APHW_VER 0x08 +#define APSW_VER 0x0c + +#endif /* __MEDIATEK_MISC_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mediatek/reset.h b/roms/u-boot/arch/arm/include/asm/arch-mediatek/reset.h new file mode 100644 index 000000000..4ba0bad94 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mediatek/reset.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef __MEDIATEK_RESET_H +#define __MEDIATEK_RESET_H + +struct udevice; + +int mediatek_reset_bind(struct udevice *pdev, u32 regofs, u32 num_regs); + +#endif /* __MEDIATEK_RESET_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/axg.h b/roms/u-boot/arch/arm/include/asm/arch-meson/axg.h new file mode 100644 index 000000000..12042de93 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/axg.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef __AXG_H__ +#define __AXG_H__ + +#ifndef __ASSEMBLY__ +#include +#endif + +#define AXG_AOBUS_BASE 0xff800000 +#define AXG_PERIPHS_BASE 0xff634400 +#define AXG_HIU_BASE 0xff63c000 +#define AXG_ETH_BASE 0xff3f0000 + +/* Always-On Peripherals registers */ +#define AXG_AO_ADDR(off) (AXG_AOBUS_BASE + ((off) << 2)) + +#define AXG_AO_SEC_GP_CFG0 AXG_AO_ADDR(0x90) +#define AXG_AO_SEC_GP_CFG3 AXG_AO_ADDR(0x93) +#define AXG_AO_SEC_GP_CFG4 AXG_AO_ADDR(0x94) +#define AXG_AO_SEC_GP_CFG5 AXG_AO_ADDR(0x95) + +#define AXG_AO_BOOT_DEVICE 0xF +#define AXG_AO_MEM_SIZE_MASK 0xFFFF0000 +#define AXG_AO_MEM_SIZE_SHIFT 16 +#define AXG_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 +#define AXG_AO_BL31_RSVMEM_SIZE_SHIFT 16 +#define AXG_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF + +#endif /* __AXG_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/boot.h b/roms/u-boot/arch/arm/include/asm/arch-meson/boot.h new file mode 100644 index 000000000..c67d12d06 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/boot.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef __MESON_BOOT_H__ +#define __MESON_BOOT_H__ + +#include + +/* Boot device */ +#define BOOT_DEVICE_RESERVED 0 +#define BOOT_DEVICE_EMMC 1 +#define BOOT_DEVICE_NAND 2 +#define BOOT_DEVICE_SPI 3 +#define BOOT_DEVICE_SD 4 +#define BOOT_DEVICE_USB 5 + +int meson_get_boot_device(void); + +int meson_get_soc_rev(char *buff, size_t buff_len); + +#endif /* __MESON_BOOT_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/clock-axg.h b/roms/u-boot/arch/arm/include/asm/arch-meson/clock-axg.h new file mode 100644 index 000000000..1ef88e4fa --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/clock-axg.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 - AmLogic, Inc. + * Copyright 2018 - Beniamino Galvani + * Copyright 2018 - BayLibre, SAS + * Author: Neil Armstrong + */ +#ifndef _ARCH_MESON_CLOCK_AXG_H_ +#define _ARCH_MESON_CLOCK_AXG_H_ + +/* + * Clock controller register offsets + * + * Register offsets from the data sheet are listed in comment blocks below. + * Those offsets must be multiplied by 4 before adding them to the base address + * to get the right value + */ +#define HHI_GP0_PLL_CNTL 0x40 +#define HHI_GP0_PLL_CNTL2 0x44 +#define HHI_GP0_PLL_CNTL3 0x48 +#define HHI_GP0_PLL_CNTL4 0x4c +#define HHI_GP0_PLL_CNTL5 0x50 +#define HHI_GP0_PLL_STS 0x54 +#define HHI_GP0_PLL_CNTL1 0x58 +#define HHI_HIFI_PLL_CNTL 0x80 +#define HHI_HIFI_PLL_CNTL2 0x84 +#define HHI_HIFI_PLL_CNTL3 0x88 +#define HHI_HIFI_PLL_CNTL4 0x8C +#define HHI_HIFI_PLL_CNTL5 0x90 +#define HHI_HIFI_PLL_STS 0x94 +#define HHI_HIFI_PLL_CNTL1 0x98 + +#define HHI_XTAL_DIVN_CNTL 0xbc +#define HHI_GCLK2_MPEG0 0xc0 +#define HHI_GCLK2_MPEG1 0xc4 +#define HHI_GCLK2_MPEG2 0xc8 +#define HHI_GCLK2_OTHER 0xd0 +#define HHI_GCLK2_AO 0xd4 +#define HHI_PCIE_PLL_CNTL 0xd8 +#define HHI_PCIE_PLL_CNTL1 0xdC +#define HHI_PCIE_PLL_CNTL2 0xe0 +#define HHI_PCIE_PLL_CNTL3 0xe4 +#define HHI_PCIE_PLL_CNTL4 0xe8 +#define HHI_PCIE_PLL_CNTL5 0xec +#define HHI_PCIE_PLL_CNTL6 0xf0 +#define HHI_PCIE_PLL_STS 0xf4 + +#define HHI_MEM_PD_REG0 0x100 +#define HHI_VPU_MEM_PD_REG0 0x104 +#define HHI_VIID_CLK_DIV 0x128 +#define HHI_VIID_CLK_CNTL 0x12c + +#define HHI_GCLK_MPEG0 0x140 +#define HHI_GCLK_MPEG1 0x144 +#define HHI_GCLK_MPEG2 0x148 +#define HHI_GCLK_OTHER 0x150 +#define HHI_GCLK_AO 0x154 +#define HHI_SYS_CPU_CLK_CNTL1 0x15c +#define HHI_SYS_CPU_RESET_CNTL 0x160 +#define HHI_VID_CLK_DIV 0x164 +#define HHI_SPICC_HCLK_CNTL 0x168 + +#define HHI_MPEG_CLK_CNTL 0x174 +#define HHI_VID_CLK_CNTL 0x17c +#define HHI_TS_CLK_CNTL 0x190 +#define HHI_VID_CLK_CNTL2 0x194 +#define HHI_SYS_CPU_CLK_CNTL0 0x19c +#define HHI_VID_PLL_CLK_DIV 0x1a0 +#define HHI_VPU_CLK_CNTL 0x1bC + +#define HHI_VAPBCLK_CNTL 0x1F4 + +#define HHI_GEN_CLK_CNTL 0x228 + +#define HHI_VDIN_MEAS_CLK_CNTL 0x250 +#define HHI_NAND_CLK_CNTL 0x25C +#define HHI_SD_EMMC_CLK_CNTL 0x264 + +#define HHI_MPLL_CNTL 0x280 +#define HHI_MPLL_CNTL2 0x284 +#define HHI_MPLL_CNTL3 0x288 +#define HHI_MPLL_CNTL4 0x28C +#define HHI_MPLL_CNTL5 0x290 +#define HHI_MPLL_CNTL6 0x294 +#define HHI_MPLL_CNTL7 0x298 +#define HHI_MPLL_CNTL8 0x29C +#define HHI_MPLL_CNTL9 0x2A0 +#define HHI_MPLL_CNTL10 0x2A4 + +#define HHI_MPLL3_CNTL0 0x2E0 +#define HHI_MPLL3_CNTL1 0x2E4 +#define HHI_PLL_TOP_MISC 0x2E8 + +#define HHI_SYS_PLL_CNTL1 0x2FC +#define HHI_SYS_PLL_CNTL 0x300 +#define HHI_SYS_PLL_CNTL2 0x304 +#define HHI_SYS_PLL_CNTL3 0x308 +#define HHI_SYS_PLL_CNTL4 0x30c +#define HHI_SYS_PLL_CNTL5 0x310 +#define HHI_SYS_PLL_STS 0x314 +#define HHI_DPLL_TOP_I 0x318 +#define HHI_DPLL_TOP2_I 0x31C + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/clock-g12a.h b/roms/u-boot/arch/arm/include/asm/arch-meson/clock-g12a.h new file mode 100644 index 000000000..d52e27e00 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/clock-g12a.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 - AmLogic, Inc. + * Copyright 2018 - Beniamino Galvani + * Copyright 2018 - BayLibre, SAS + * Author: Neil Armstrong + */ +#ifndef _ARCH_MESON_CLOCK_G12A_H_ +#define _ARCH_MESON_CLOCK_G12A_H_ + +/* + * Clock controller register offsets + * + * Register offsets from the data sheet are listed in comment blocks below. + * Those offsets must be multiplied by 4 before adding them to the base address + * to get the right value + */ + +#define HHI_MIPI_CNTL0 0x000 +#define HHI_MIPI_CNTL1 0x004 +#define HHI_MIPI_CNTL2 0x008 +#define HHI_MIPI_STS 0x00C +#define HHI_GP0_PLL_CNTL0 0x040 +#define HHI_GP0_PLL_CNTL1 0x044 +#define HHI_GP0_PLL_CNTL2 0x048 +#define HHI_GP0_PLL_CNTL3 0x04C +#define HHI_GP0_PLL_CNTL4 0x050 +#define HHI_GP0_PLL_CNTL5 0x054 +#define HHI_GP0_PLL_CNTL6 0x058 +#define HHI_GP0_PLL_STS 0x05C +#define HHI_PCIE_PLL_CNTL0 0x098 +#define HHI_PCIE_PLL_CNTL1 0x09C +#define HHI_PCIE_PLL_CNTL2 0x0A0 +#define HHI_PCIE_PLL_CNTL3 0x0A4 +#define HHI_PCIE_PLL_CNTL4 0x0A8 +#define HHI_PCIE_PLL_CNTL5 0x0AC +#define HHI_PCIE_PLL_STS 0x0B8 +#define HHI_HIFI_PLL_CNTL0 0x0D8 +#define HHI_HIFI_PLL_CNTL1 0x0DC +#define HHI_HIFI_PLL_CNTL2 0x0E0 +#define HHI_HIFI_PLL_CNTL3 0x0E4 +#define HHI_HIFI_PLL_CNTL4 0x0E8 +#define HHI_HIFI_PLL_CNTL5 0x0EC +#define HHI_HIFI_PLL_CNTL6 0x0F0 +#define HHI_VIID_CLK_DIV 0x128 +#define HHI_VIID_CLK_CNTL 0x12C +#define HHI_GCLK_MPEG0 0x140 +#define HHI_GCLK_MPEG1 0x144 +#define HHI_GCLK_MPEG2 0x148 +#define HHI_GCLK_OTHER 0x150 +#define HHI_GCLK_OTHER2 0x154 +#define HHI_VID_CLK_DIV 0x164 +#define HHI_MPEG_CLK_CNTL 0x174 +#define HHI_AUD_CLK_CNTL 0x178 +#define HHI_VID_CLK_CNTL 0x17c +#define HHI_TS_CLK_CNTL 0x190 +#define HHI_VID_CLK_CNTL2 0x194 +#define HHI_SYS_CPU_CLK_CNTL0 0x19c +#define HHI_VID_PLL_CLK_DIV 0x1A0 +#define HHI_MALI_CLK_CNTL 0x1b0 +#define HHI_VPU_CLKC_CNTL 0x1b4 +#define HHI_VPU_CLK_CNTL 0x1bC +#define HHI_HDMI_CLK_CNTL 0x1CC +#define HHI_VDEC_CLK_CNTL 0x1E0 +#define HHI_VDEC2_CLK_CNTL 0x1E4 +#define HHI_VDEC3_CLK_CNTL 0x1E8 +#define HHI_VDEC4_CLK_CNTL 0x1EC +#define HHI_HDCP22_CLK_CNTL 0x1F0 +#define HHI_VAPBCLK_CNTL 0x1F4 +#define HHI_VPU_CLKB_CNTL 0x20C +#define HHI_GEN_CLK_CNTL 0x228 +#define HHI_VDIN_MEAS_CLK_CNTL 0x250 +#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254 +#define HHI_NAND_CLK_CNTL 0x25C +#define HHI_SD_EMMC_CLK_CNTL 0x264 +#define HHI_MPLL_CNTL0 0x278 +#define HHI_MPLL_CNTL1 0x27C +#define HHI_MPLL_CNTL2 0x280 +#define HHI_MPLL_CNTL3 0x284 +#define HHI_MPLL_CNTL4 0x288 +#define HHI_MPLL_CNTL5 0x28c +#define HHI_MPLL_CNTL6 0x290 +#define HHI_MPLL_CNTL7 0x294 +#define HHI_MPLL_CNTL8 0x298 +#define HHI_FIX_PLL_CNTL0 0x2A0 +#define HHI_FIX_PLL_CNTL1 0x2A4 +#define HHI_FIX_PLL_CNTL3 0x2AC +#define HHI_SYS_PLL_CNTL0 0x2f4 +#define HHI_SYS_PLL_CNTL1 0x2f8 +#define HHI_SYS_PLL_CNTL2 0x2fc +#define HHI_SYS_PLL_CNTL3 0x300 +#define HHI_SYS_PLL_CNTL4 0x304 +#define HHI_SYS_PLL_CNTL5 0x308 +#define HHI_SYS_PLL_CNTL6 0x30c +#define HHI_HDMI_PLL_CNTL0 0x320 +#define HHI_HDMI_PLL_CNTL1 0x324 +#define HHI_HDMI_PLL_CNTL2 0x328 +#define HHI_HDMI_PLL_CNTL3 0x32c +#define HHI_HDMI_PLL_CNTL4 0x330 +#define HHI_HDMI_PLL_CNTL5 0x334 +#define HHI_HDMI_PLL_CNTL6 0x338 +#define HHI_SPICC_CLK_CNTL 0x3dc + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/clock-gx.h b/roms/u-boot/arch/arm/include/asm/arch-meson/clock-gx.h new file mode 100644 index 000000000..13a2e7688 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/clock-gx.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 - AmLogic, Inc. + * Copyright 2018 - Beniamino Galvani + */ +#ifndef _ARCH_MESON_CLOCK_GX_H_ +#define _ARCH_MESON_CLOCK_GX_H_ + +/* + * Clock controller register offsets + * + * Register offsets from the data sheet are listed in comment blocks below. + * Those offsets must be multiplied by 4 before adding them to the base address + * to get the right value + */ +#define SCR 0x2C /* 0x0b offset in data sheet */ +#define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */ + +#define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */ +#define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ +#define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ +#define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */ +#define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */ +#define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */ + +#define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */ +#define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */ + +#define HHI_MEM_PD_REG0 0x100 /* 0x40 offset in data sheet */ +#define HHI_MEM_PD_REG1 0x104 /* 0x41 offset in data sheet */ +#define HHI_VPU_MEM_PD_REG1 0x108 /* 0x42 offset in data sheet */ +#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ +#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ + +#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ +#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ +#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ +#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ +#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ +#define HHI_SYS_OSCIN_CNTL 0x158 /* 0x56 offset in data sheet */ +#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ +#define HHI_SYS_CPU_RESET_CNTL 0x160 /* 0x58 offset in data sheet */ +#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ + +#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ +#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ +#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ +#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */ +#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ +#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ +#define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ +#define HHI_AUD_CLK_CNTL3 0x1a4 /* 0x69 offset in data sheet */ +#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */ +#define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */ + +#define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */ +#define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */ +#define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */ +#define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */ +#define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */ +#define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */ +#define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */ + +#define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */ +#define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */ +#define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */ +#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ +#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ + +#define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */ +#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */ +#define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */ + +#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ +#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ +#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ +#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ +#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ +#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ +#define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */ +#define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */ +#define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ +#define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */ + +#define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */ +#define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */ +#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ +#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ + +#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ +#define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */ +#define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */ +#define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */ +#define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */ +#define HHI_DPLL_TOP_I 0x318 /* 0xc6 offset in data sheet */ +#define HHI_DPLL_TOP2_I 0x31C /* 0xc7 offset in data sheet */ +#define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ +#define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ +#define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ +#define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ +#define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ +#define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */ +#define HHI_HDMI_PLL_CNTL_I 0x338 /* 0xce offset in data sheet */ +#define HHI_HDMI_PLL_CNTL7 0x33C /* 0xcf offset in data sheet */ + +#define HHI_HDMI_PHY_CNTL0 0x3A0 /* 0xe8 offset in data sheet */ +#define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */ +#define HHI_HDMI_PHY_CNTL2 0x3A8 /* 0xea offset in data sheet */ +#define HHI_HDMI_PHY_CNTL3 0x3AC /* 0xeb offset in data sheet */ + +#define HHI_VID_LOCK_CLK_CNTL 0x3C8 /* 0xf2 offset in data sheet */ +#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */ +#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */ + +ulong meson_measure_clk_rate(unsigned int clk); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/eth.h b/roms/u-boot/arch/arm/include/asm/arch-meson/eth.h new file mode 100644 index 000000000..c0070615c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/eth.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef __MESON_ETH_H__ +#define __MESON_ETH_H__ + +/* Generate an unique MAC address based on the HW serial */ +int meson_generate_serial_ethaddr(void); + +#endif /* __MESON_ETH_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/g12a.h b/roms/u-boot/arch/arm/include/asm/arch-meson/g12a.h new file mode 100644 index 000000000..ef4f301f7 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/g12a.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef __G12A_H__ +#define __G12A_H__ + +#ifndef __ASSEMBLY__ +#include +#endif + +#define G12A_AOBUS_BASE 0xff800000 +#define G12A_PERIPHS_BASE 0xff634400 +#define G12A_HIU_BASE 0xff63c000 +#define G12A_ETH_PHY_BASE 0xff64c000 +#define G12A_ETH_BASE 0xff3f0000 + +/* Always-On Peripherals registers */ +#define G12A_AO_ADDR(off) (G12A_AOBUS_BASE + ((off) << 2)) + +#define G12A_AO_SEC_GP_CFG0 G12A_AO_ADDR(0x90) +#define G12A_AO_SEC_GP_CFG3 G12A_AO_ADDR(0x93) +#define G12A_AO_SEC_GP_CFG4 G12A_AO_ADDR(0x94) +#define G12A_AO_SEC_GP_CFG5 G12A_AO_ADDR(0x95) + +#define G12A_AO_BOOT_DEVICE 0xF +#define G12A_AO_MEM_SIZE_MASK 0xFFFF0000 +#define G12A_AO_MEM_SIZE_SHIFT 16 +#define G12A_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 +#define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16 +#define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF + +#endif /* __G12A_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-meson/gpio.h new file mode 100644 index 000000000..d0142f16e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/gpio.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 - Beniamino Galvani + */ + +#ifndef __ASM_ARCH_MESON_GPIO_H +#define __ASM_ARCH_MESON_GPIO_H + + +#endif /* __ASM_ARCH_MESON_GPIO_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/gx.h b/roms/u-boot/arch/arm/include/asm/arch-meson/gx.h new file mode 100644 index 000000000..26ec5d0bc --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/gx.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 - Beniamino Galvani + */ + +#ifndef __GX_H__ +#define __GX_H__ + +#ifndef __ASSEMBLY__ +#include +#endif + +#define GX_FIRMWARE_MEM_SIZE 0x1000000 + +#define GX_AOBUS_BASE 0xc8100000 +#define GX_PERIPHS_BASE 0xc8834400 +#define GX_HIU_BASE 0xc883c000 +#define GX_ETH_BASE 0xc9410000 + +/* Always-On Peripherals registers */ +#define GX_AO_ADDR(off) (GX_AOBUS_BASE + ((off) << 2)) + +#define GX_AO_SEC_GP_CFG0 GX_AO_ADDR(0x90) +#define GX_AO_SEC_GP_CFG3 GX_AO_ADDR(0x93) +#define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94) +#define GX_AO_SEC_GP_CFG5 GX_AO_ADDR(0x95) + +#define GX_AO_BOOT_DEVICE 0xF +#define GX_AO_MEM_SIZE_MASK 0xFFFF0000 +#define GX_AO_MEM_SIZE_SHIFT 16 +#define GX_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 +#define GX_AO_BL31_RSVMEM_SIZE_SHIFT 16 +#define GX_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF + +/* Peripherals registers */ +#define GX_PERIPHS_ADDR(off) (GX_PERIPHS_BASE + ((off) << 2)) + +/* GPIO registers 0 to 6 */ +#define _GX_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n)) +#define GX_GPIO_EN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 0) +#define GX_GPIO_IN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1) +#define GX_GPIO_OUT(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2) + +#endif /* __GX_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/i2c.h b/roms/u-boot/arch/arm/include/asm/arch-meson/i2c.h new file mode 100644 index 000000000..aa474a05b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/i2c.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 - Beniamino Galvani + */ +#ifndef _MESON_I2C_H_ +#define _MESON_I2C_H_ + +#define MESON_I2C_CLK_RATE 167000000 + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/mem.h b/roms/u-boot/arch/arm/include/asm/arch-meson/mem.h new file mode 100644 index 000000000..a65100aeb --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/mem.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef __MESON_MEM_H__ +#define __MESON_MEM_H__ + +/* Configure the reserved memory zones exported by the secure registers + * into EFI and DTB reserved memory entries. + */ +void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size); +void meson_init_reserved_memory(void *fdt); + +#endif /* __MESON_MEM_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/meson-vpu.h b/roms/u-boot/arch/arm/include/asm/arch-meson/meson-vpu.h new file mode 100644 index 000000000..f31dfa6ad --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/meson-vpu.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Maxime Jourdan + */ + +#ifndef __MESON_VPU_H__ +#define __MESON_VPU_H__ + +/* Allow reserving the framebuffer memory region */ +void meson_vpu_rsv_fb(void *fdt); + +#endif /* __MESON_VPU_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/sm.h b/roms/u-boot/arch/arm/include/asm/arch-meson/sm.h new file mode 100644 index 000000000..f3ae46a6d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/sm.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 - Beniamino Galvani + */ + +#ifndef __MESON_SM_H__ +#define __MESON_SM_H__ + +ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size); + +#define SM_SERIAL_SIZE 12 + +int meson_sm_get_serial(void *buffer, size_t size); + +enum { + REBOOT_REASON_COLD = 0, + REBOOT_REASON_NORMAL = 1, + REBOOT_REASON_RECOVERY = 2, + REBOOT_REASON_UPDATE = 3, + REBOOT_REASON_FASTBOOT = 4, + REBOOT_REASON_SUSPEND_OFF = 5, + REBOOT_REASON_HIBERNATE = 6, + REBOOT_REASON_BOOTLOADER = 7, + REBOOT_REASON_SHUTDOWN_REBOOT = 8, + REBOOT_REASON_RPMBP = 9, + REBOOT_REASON_CRASH_DUMP = 11, + REBOOT_REASON_KERNEL_PANIC = 12, + REBOOT_REASON_WATCHDOG_REBOOT = 13, +}; + +int meson_sm_get_reboot_reason(void); + +#endif /* __MESON_SM_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/usb-gx.h b/roms/u-boot/arch/arm/include/asm/arch-meson/usb-gx.h new file mode 100644 index 000000000..61f1809df --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/usb-gx.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 BayLibre SAS + * Author: Neil Armstrong + */ +#ifndef _ARCH_MESON_USB_GX_H_ +#define _ARCH_MESON_USB_GX_H_ + +#include +#include + +/* TOFIX add set_mode to struct phy_ops */ +void phy_meson_gxl_usb2_set_mode(struct phy *phy, enum usb_dr_mode mode); + +int dwc3_meson_gxl_force_mode(struct udevice *dev, enum usb_dr_mode mode); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-meson/usb.h b/roms/u-boot/arch/arm/include/asm/arch-meson/usb.h new file mode 100644 index 000000000..b794b5ce7 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-meson/usb.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef __MESON_USB_H__ +#define __MESON_USB_H__ + +int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode); + +#endif /* __MESON_USB_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mvebu/spi.h b/roms/u-boot/arch/arm/include/asm/arch-mvebu/spi.h new file mode 100644 index 000000000..58b6c32c4 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mvebu/spi.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * Derived from drivers/spi/mpc8xxx_spi.c + */ + +#ifndef __KW_SPI_H__ +#define __KW_SPI_H__ + +/* SPI Registers on kirkwood SOC */ +struct kwspi_registers { + u32 ctrl; /* 0x10600 */ + u32 cfg; /* 0x10604 */ + u32 dout; /* 0x10608 */ + u32 din; /* 0x1060c */ + u32 irq_cause; /* 0x10610 */ + u32 irq_mask; /* 0x10614 */ + u32 timing1; /* 0x10618 */ + u32 timing2; /* 0x1061c */ + u32 dw_cfg; /* 0x10620 - Direct Write Configuration */ +}; + +/* Control Register */ +#define KWSPI_CSN_ACT (1 << 0) /* Activates serial memory interface */ +#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ +#define KWSPI_CS_SHIFT 2 /* chip select shift */ +#define KWSPI_CS_MASK 0x7 /* chip select mask */ + +/* Configuration Register */ +#define KWSPI_CLKPRESCL_MASK 0x1f +#define KWSPI_CLKPRESCL_MIN 0x12 +#define KWSPI_XFERLEN_1BYTE 0 +#define KWSPI_XFERLEN_2BYTE (1 << 5) +#define KWSPI_XFERLEN_MASK (1 << 5) +#define KWSPI_ADRLEN_1BYTE 0 +#define KWSPI_ADRLEN_2BYTE (1 << 8) +#define KWSPI_ADRLEN_3BYTE (2 << 8) +#define KWSPI_ADRLEN_4BYTE (3 << 8) +#define KWSPI_ADRLEN_MASK (3 << 8) +#define KWSPI_CPOL (1 << 11) +#define KWSPI_CPHA (1 << 12) +#define KWSPI_TXLSBF (1 << 13) +#define KWSPI_RXLSBF (1 << 14) + +/* Timing Parameters 1 Register */ +#define KW_SPI_TMISO_SAMPLE_OFFSET 6 +#define KW_SPI_TMISO_SAMPLE_MASK (0x3 << KW_SPI_TMISO_SAMPLE_OFFSET) +#define KW_SPI_TMISO_SAMPLE_1 (1 << KW_SPI_TMISO_SAMPLE_OFFSET) +#define KW_SPI_TMISO_SAMPLE_2 (2 << KW_SPI_TMISO_SAMPLE_OFFSET) + +#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ +#define KWSPI_IRQMASK 0 /* mask SPI interrupt */ +#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ + +#define KWSPI_TIMEOUT 10000 + +#endif /* __KW_SPI_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx25/clock.h b/roms/u-boot/arch/arm/include/asm/arch-mx25/clock.h new file mode 100644 index 000000000..3045b78d0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx25/clock.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * + * (c) 2009 Ilya Yanok, Emcraft Systems + * + * Modified for mx25 by John Rigby + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +#ifdef CONFIG_MX25_HCLK_FREQ +#define MXC_HCLK CONFIG_MX25_HCLK_FREQ +#else +#define MXC_HCLK 24000000 +#endif + +#ifdef CONFIG_MX25_CLK32 +#define MXC_CLK32 CONFIG_MX25_CLK32 +#else +#define MXC_CLK32 32768 +#endif + +enum mxc_clock { + /* PER clocks (do not change order) */ + MXC_CSI_CLK, + MXC_EPIT_CLK, + MXC_ESAI_CLK, + MXC_ESDHC1_CLK, + MXC_ESDHC2_CLK, + MXC_GPT_CLK, + MXC_I2C_CLK, + MXC_LCDC_CLK, + MXC_NFC_CLK, + MXC_OWIRE_CLK, + MXC_PWM_CLK, + MXC_SIM1_CLK, + MXC_SIM2_CLK, + MXC_SSI1_CLK, + MXC_SSI2_CLK, + MXC_UART_CLK, + /* Other clocks */ + MXC_ARM_CLK, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_CSPI_CLK, + MXC_FEC_CLK, + MXC_CLK_NUM +}; + +int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq); +unsigned int mxc_get_clock(enum mxc_clock clk); + +#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK) +#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx25/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-mx25/gpio.h new file mode 100644 index 000000000..1205695ce --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx25/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, + */ + + +#ifndef __ASM_ARCH_MX25_GPIO_H +#define __ASM_ARCH_MX25_GPIO_H + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx25/imx-regs.h b/roms/u-boot/arch/arm/include/asm/arch-mx25/imx-regs.h new file mode 100644 index 000000000..57809697c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -0,0 +1,504 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2009, DENX Software Engineering + * Author: John Rigby + * and arch-mx27/imx-regs.h + * Copyright (C) 2007 Pengutronix, + * Sascha Hauer + * Copyright (C) 2009 Ilya Yanok, + * Emcraft Systems + */ + +#ifndef _IMX_REGS_H +#define _IMX_REGS_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include + +/* Clock Control Module (CCM) registers */ +struct ccm_regs { + u32 mpctl; /* Core PLL Control */ + u32 upctl; /* USB PLL Control */ + u32 cctl; /* Clock Control */ + u32 cgr0; /* Clock Gating Control 0 */ + u32 cgr1; /* Clock Gating Control 1 */ + u32 cgr2; /* Clock Gating Control 2 */ + u32 pcdr[4]; /* PER Clock Dividers */ + u32 rcsr; /* CCM Status */ + u32 crdr; /* CCM Reset and Debug */ + u32 dcvr0; /* DPTC Comparator Value 0 */ + u32 dcvr1; /* DPTC Comparator Value 1 */ + u32 dcvr2; /* DPTC Comparator Value 2 */ + u32 dcvr3; /* DPTC Comparator Value 3 */ + u32 ltr0; /* Load Tracking 0 */ + u32 ltr1; /* Load Tracking 1 */ + u32 ltr2; /* Load Tracking 2 */ + u32 ltr3; /* Load Tracking 3 */ + u32 ltbr0; /* Load Tracking Buffer 0 */ + u32 ltbr1; /* Load Tracking Buffer 1 */ + u32 pcmr0; /* Power Management Control 0 */ + u32 pcmr1; /* Power Management Control 1 */ + u32 pcmr2; /* Power Management Control 2 */ + u32 mcr; /* Miscellaneous Control */ + u32 lpimr0; /* Low Power Interrupt Mask 0 */ + u32 lpimr1; /* Low Power Interrupt Mask 1 */ +}; + +/* Enhanced SDRAM Controller (ESDRAMC) registers */ +struct esdramc_regs { + u32 ctl0; /* control 0 */ + u32 cfg0; /* configuration 0 */ + u32 ctl1; /* control 1 */ + u32 cfg1; /* configuration 1 */ + u32 misc; /* miscellaneous */ + u32 pad[3]; + u32 cdly1; /* Delay Line 1 configuration debug */ + u32 cdly2; /* delay line 2 configuration debug */ + u32 cdly3; /* delay line 3 configuration debug */ + u32 cdly4; /* delay line 4 configuration debug */ + u32 cdly5; /* delay line 5 configuration debug */ + u32 cdlyl; /* delay line cycle length debug */ +}; + +/* General Purpose Timer (GPT) registers */ +struct gpt_regs { + u32 ctrl; /* control */ + u32 pre; /* prescaler */ + u32 stat; /* status */ + u32 intr; /* interrupt */ + u32 cmp[3]; /* output compare 1-3 */ + u32 capt[2]; /* input capture 1-2 */ + u32 counter; /* counter */ +}; + +/* Watchdog Timer (WDOG) registers */ +struct wdog_regs { + u16 wcr; /* Control */ + u16 wsr; /* Service */ + u16 wrsr; /* Reset Status */ + u16 wicr; /* Interrupt Control */ + u16 wmcr; /* Misc Control */ +}; + +/* IIM control registers */ +struct iim_regs { + u32 iim_stat; + u32 iim_statm; + u32 iim_err; + u32 iim_emask; + u32 iim_fctl; + u32 iim_ua; + u32 iim_la; + u32 iim_sdat; + u32 iim_prev; + u32 iim_srev; + u32 iim_prg_p; + u32 iim_scs0; + u32 iim_scs1; + u32 iim_scs2; + u32 iim_scs3; + u32 res1[0x1f1]; + struct fuse_bank { + u32 fuse_regs[0x20]; + u32 fuse_rsvd[0xe0]; + } bank[3]; +}; + +struct fuse_bank0_regs { + u32 fuse0_7[8]; + u32 uid[8]; + u32 fuse16_25[0xa]; + u32 mac_addr[6]; +}; + +struct fuse_bank1_regs { + u32 fuse0_21[0x16]; + u32 usr5; + u32 fuse23_29[7]; + u32 usr6[2]; +}; + +/* Multi-Layer AHB Crossbar Switch (MAX) registers */ +struct max_regs { + u32 mpr0; + u32 pad00[3]; + u32 sgpcr0; + u32 pad01[59]; + u32 mpr1; + u32 pad02[3]; + u32 sgpcr1; + u32 pad03[59]; + u32 mpr2; + u32 pad04[3]; + u32 sgpcr2; + u32 pad05[59]; + u32 mpr3; + u32 pad06[3]; + u32 sgpcr3; + u32 pad07[59]; + u32 mpr4; + u32 pad08[3]; + u32 sgpcr4; + u32 pad09[251]; + u32 mgpcr0; + u32 pad10[63]; + u32 mgpcr1; + u32 pad11[63]; + u32 mgpcr2; + u32 pad12[63]; + u32 mgpcr3; + u32 pad13[63]; + u32 mgpcr4; +}; + +/* AHB <-> IP-Bus Interface (AIPS) */ +struct aips_regs { + u32 mpr_0_7; + u32 mpr_8_15; +}; +/* LCD controller registers */ +struct lcdc_regs { + u32 lssar; /* Screen Start Address */ + u32 lsr; /* Size */ + u32 lvpwr; /* Virtual Page Width */ + u32 lcpr; /* Cursor Position */ + u32 lcwhb; /* Cursor Width Height and Blink */ + u32 lccmr; /* Color Cursor Mapping */ + u32 lpcr; /* Panel Configuration */ + u32 lhcr; /* Horizontal Configuration */ + u32 lvcr; /* Vertical Configuration */ + u32 lpor; /* Panning Offset */ + u32 lscr; /* Sharp Configuration */ + u32 lpccr; /* PWM Contrast Control */ + u32 ldcr; /* DMA Control */ + u32 lrmcr; /* Refresh Mode Control */ + u32 licr; /* Interrupt Configuration */ + u32 lier; /* Interrupt Enable */ + u32 lisr; /* Interrupt Status */ + u32 res0[3]; + u32 lgwsar; /* Graphic Window Start Address */ + u32 lgwsr; /* Graphic Window Size */ + u32 lgwvpwr; /* Graphic Window Virtual Page Width Regist */ + u32 lgwpor; /* Graphic Window Panning Offset */ + u32 lgwpr; /* Graphic Window Position */ + u32 lgwcr; /* Graphic Window Control */ + u32 lgwdcr; /* Graphic Window DMA Control */ + u32 res1[5]; + u32 lauscr; /* AUS Mode Control */ + u32 lausccr; /* AUS mode Cursor Control */ + u32 res2[31 + 64*7]; + u32 bglut; /* Background Lookup Table */ + u32 gwlut; /* Graphic Window Lookup Table */ +}; + +/* Wireless External Interface Module Registers */ +struct weim_regs { + u32 cscr0u; /* Chip Select 0 Upper Register */ + u32 cscr0l; /* Chip Select 0 Lower Register */ + u32 cscr0a; /* Chip Select 0 Addition Register */ + u32 pad0; + u32 cscr1u; /* Chip Select 1 Upper Register */ + u32 cscr1l; /* Chip Select 1 Lower Register */ + u32 cscr1a; /* Chip Select 1 Addition Register */ + u32 pad1; + u32 cscr2u; /* Chip Select 2 Upper Register */ + u32 cscr2l; /* Chip Select 2 Lower Register */ + u32 cscr2a; /* Chip Select 2 Addition Register */ + u32 pad2; + u32 cscr3u; /* Chip Select 3 Upper Register */ + u32 cscr3l; /* Chip Select 3 Lower Register */ + u32 cscr3a; /* Chip Select 3 Addition Register */ + u32 pad3; + u32 cscr4u; /* Chip Select 4 Upper Register */ + u32 cscr4l; /* Chip Select 4 Lower Register */ + u32 cscr4a; /* Chip Select 4 Addition Register */ + u32 pad4; + u32 cscr5u; /* Chip Select 5 Upper Register */ + u32 cscr5l; /* Chip Select 5 Lower Register */ + u32 cscr5a; /* Chip Select 5 Addition Register */ + u32 pad5; + u32 wcr; /* WEIM Configuration Register */ +}; + +/* Multi-Master Memory Interface */ +struct m3if_regs { + u32 ctl; /* Control Register */ + u32 wcfg0; /* Watermark Configuration Register 0 */ + u32 wcfg1; /* Watermark Configuration Register1 */ + u32 wcfg2; /* Watermark Configuration Register2 */ + u32 wcfg3; /* Watermark Configuration Register 3 */ + u32 wcfg4; /* Watermark Configuration Register 4 */ + u32 wcfg5; /* Watermark Configuration Register 5 */ + u32 wcfg6; /* Watermark Configuration Register 6 */ + u32 wcfg7; /* Watermark Configuration Register 7 */ + u32 wcsr; /* Watermark Control and Status Register */ + u32 scfg0; /* Snooping Configuration Register 0 */ + u32 scfg1; /* Snooping Configuration Register 1 */ + u32 scfg2; /* Snooping Configuration Register 2 */ + u32 ssr0; /* Snooping Status Register 0 */ + u32 ssr1; /* Snooping Status Register 1 */ + u32 res0; + u32 mlwe0; /* Master Lock WEIM CS0 Register */ + u32 mlwe1; /* Master Lock WEIM CS1 Register */ + u32 mlwe2; /* Master Lock WEIM CS2 Register */ + u32 mlwe3; /* Master Lock WEIM CS3 Register */ + u32 mlwe4; /* Master Lock WEIM CS4 Register */ + u32 mlwe5; /* Master Lock WEIM CS5 Register */ +}; + +/* Pulse width modulation */ +struct pwm_regs { + u32 cr; /* Control Register */ + u32 sr; /* Status Register */ + u32 ir; /* Interrupt Register */ + u32 sar; /* Sample Register */ + u32 pr; /* Period Register */ + u32 cnr; /* Counter Register */ +}; + +/* Enhanced Periodic Interrupt Timer */ +struct epit_regs { + u32 cr; /* Control register */ + u32 sr; /* Status register */ + u32 lr; /* Load register */ + u32 cmpr; /* Compare register */ + u32 cnr; /* Counter register */ +}; + +#endif + +#define ARCH_MXC + +/* AIPS 1 */ +#define IMX_AIPS1_BASE (0x43F00000) +#define IMX_MAX_BASE (0x43F04000) +#define IMX_CLKCTL_BASE (0x43F08000) +#define IMX_ETB_SLOT4_BASE (0x43F0C000) +#define IMX_ETB_SLOT5_BASE (0x43F10000) +#define IMX_ECT_CTIO_BASE (0x43F18000) +#define I2C1_BASE_ADDR (0x43F80000) +#define I2C3_BASE_ADDR (0x43F84000) +#define IMX_CAN1_BASE (0x43F88000) +#define IMX_CAN2_BASE (0x43F8C000) +#define UART1_BASE (0x43F90000) +#define UART2_BASE (0x43F94000) +#define I2C2_BASE_ADDR (0x43F98000) +#define IMX_OWIRE_BASE (0x43F9C000) +#define IMX_CSPI1_BASE (0x43FA4000) +#define IMX_KPP_BASE (0x43FA8000) +#define IMX_IOPADMUX_BASE (0x43FAC000) +#define IOMUXC_BASE_ADDR IMX_IOPADMUX_BASE +#define IMX_IOPADCTL_BASE (0x43FAC22C) +#define IMX_IOPADGRPCTL_BASE (0x43FAC418) +#define IMX_IOPADINPUTSEL_BASE (0x43FAC460) +#define IMX_AUDMUX_BASE (0x43FB0000) +#define IMX_ECT_IP1_BASE (0x43FB8000) +#define IMX_ECT_IP2_BASE (0x43FBC000) + +/* SPBA */ +#define IMX_SPBA_BASE (0x50000000) +#define IMX_CSPI3_BASE (0x50004000) +#define UART4_BASE (0x50008000) +#define UART3_BASE (0x5000C000) +#define IMX_CSPI2_BASE (0x50010000) +#define IMX_SSI2_BASE (0x50014000) +#define IMX_ESAI_BASE (0x50018000) +#define IMX_ATA_DMA_BASE (0x50020000) +#define IMX_SIM1_BASE (0x50024000) +#define IMX_SIM2_BASE (0x50028000) +#define UART5_BASE (0x5002C000) +#define IMX_TSC_BASE (0x50030000) +#define IMX_SSI1_BASE (0x50034000) +#define IMX_FEC_BASE (0x50038000) +#define IMX_SPBA_CTRL_BASE (0x5003C000) + +/* AIPS 2 */ +#define IMX_AIPS2_BASE (0x53F00000) +#define IMX_CCM_BASE (0x53F80000) +#define IMX_GPT4_BASE (0x53F84000) +#define IMX_GPT3_BASE (0x53F88000) +#define IMX_GPT2_BASE (0x53F8C000) +#define IMX_GPT1_BASE (0x53F90000) +#define IMX_EPIT1_BASE (0x53F94000) +#define IMX_EPIT2_BASE (0x53F98000) +#define IMX_GPIO4_BASE (0x53F9C000) +#define IMX_PWM2_BASE (0x53FA0000) +#define IMX_GPIO3_BASE (0x53FA4000) +#define IMX_PWM3_BASE (0x53FA8000) +#define IMX_SCC_BASE (0x53FAC000) +#define IMX_SCM_BASE (0x53FAE000) +#define IMX_SMN_BASE (0x53FAF000) +#define IMX_RNGD_BASE (0x53FB0000) +#define IMX_MMC_SDHC1_BASE (0x53FB4000) +#define IMX_MMC_SDHC2_BASE (0x53FB8000) +#define IMX_LCDC_BASE (0x53FBC000) +#define IMX_SLCDC_BASE (0x53FC0000) +#define IMX_PWM4_BASE (0x53FC8000) +#define IMX_GPIO1_BASE (0x53FCC000) +#define IMX_GPIO2_BASE (0x53FD0000) +#define IMX_SDMA_BASE (0x53FD4000) +#define IMX_WDT_BASE (0x53FDC000) +#define WDOG1_BASE_ADDR IMX_WDT_BASE +#define IMX_PWM1_BASE (0x53FE0000) +#define IMX_RTIC_BASE (0x53FEC000) +#define IMX_IIM_BASE (0x53FF0000) +#define IIM_BASE_ADDR IMX_IIM_BASE +#define IMX_USB_BASE (0x53FF4000) +/* + * This is in contradiction to the imx25 reference manual, which says that + * port 1's registers start at 0x53FF4200. The correct base address for + * port 1 is 0x53FF4400. The kernel uses 0x53FF4400 as well. + */ +#define IMX_USB_PORT_OFFSET 0x400 +#define IMX_CSI_BASE (0x53FF8000) +#define IMX_DRYICE_BASE (0x53FFC000) + +#define IMX_ARM926_ROMPATCH (0x60000000) +#define IMX_ARM926_ASIC (0x68000000) + +/* 128K Internal Static RAM */ +#define IMX_RAM_BASE (0x78000000) +#define IMX_RAM_SIZE (128 * 1024) + +/* SDRAM BANKS */ +#define IMX_SDRAM_BANK0_BASE (0x80000000) +#define IMX_SDRAM_BANK1_BASE (0x90000000) + +#define IMX_WEIM_CS0 (0xA0000000) +#define IMX_WEIM_CS1 (0xA8000000) +#define IMX_WEIM_CS2 (0xB0000000) +#define IMX_WEIM_CS3 (0xB2000000) +#define IMX_WEIM_CS4 (0xB4000000) +#define IMX_ESDRAMC_BASE (0xB8001000) +#define IMX_WEIM_CTRL_BASE (0xB8002000) +#define IMX_M3IF_CTRL_BASE (0xB8003000) +#define IMX_EMI_CTRL_BASE (0xB8004000) + +/* NAND Flash Controller */ +#define IMX_NFC_BASE (0xBB000000) +#define NFC_BASE_ADDR IMX_NFC_BASE + +/* CCM bitfields */ +#define CCM_PLL_MFI_SHIFT 10 +#define CCM_PLL_MFI_MASK 0xf +#define CCM_PLL_MFN_SHIFT 0 +#define CCM_PLL_MFN_MASK 0x3ff +#define CCM_PLL_MFD_SHIFT 16 +#define CCM_PLL_MFD_MASK 0x3ff +#define CCM_PLL_PD_SHIFT 26 +#define CCM_PLL_PD_MASK 0xf +#define CCM_CCTL_ARM_DIV_SHIFT 30 +#define CCM_CCTL_ARM_DIV_MASK 3 +#define CCM_CCTL_AHB_DIV_SHIFT 28 +#define CCM_CCTL_AHB_DIV_MASK 3 +#define CCM_CCTL_ARM_SRC (1 << 14) +#define CCM_CGR1_GPT1 (1 << 19) +#define CCM_PERCLK_REG(clk) (clk / 4) +#define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4)) +#define CCM_PERCLK_MASK 0x3f +#define CCM_RCSR_NF_16BIT_SEL (1 << 14) +#define CCM_RCSR_NF_PS(v) ((v >> 26) & 3) +#define CCM_CRDR_BT_UART_SRC_SHIFT 29 +#define CCM_CRDR_BT_UART_SRC_MASK 7 + +/* ESDRAM Controller register bitfields */ +#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) +#define ESDCTL_BL (1 << 7) +#define ESDCTL_FP (1 << 8) +#define ESDCTL_PWDT(x) (((x) & 3) << 10) +#define ESDCTL_SREFR(x) (((x) & 7) << 13) +#define ESDCTL_DSIZ_16_UPPER (0 << 16) +#define ESDCTL_DSIZ_16_LOWER (1 << 16) +#define ESDCTL_DSIZ_32 (2 << 16) +#define ESDCTL_COL8 (0 << 20) +#define ESDCTL_COL9 (1 << 20) +#define ESDCTL_COL10 (2 << 20) +#define ESDCTL_ROW11 (0 << 24) +#define ESDCTL_ROW12 (1 << 24) +#define ESDCTL_ROW13 (2 << 24) +#define ESDCTL_ROW14 (3 << 24) +#define ESDCTL_ROW15 (4 << 24) +#define ESDCTL_SP (1 << 27) +#define ESDCTL_SMODE_NORMAL (0 << 28) +#define ESDCTL_SMODE_PRECHARGE (1 << 28) +#define ESDCTL_SMODE_AUTO_REF (2 << 28) +#define ESDCTL_SMODE_LOAD_MODE (3 << 28) +#define ESDCTL_SMODE_MAN_REF (4 << 28) +#define ESDCTL_SDE (1 << 31) + +#define ESDCFG_TRC(x) (((x) & 0xf) << 0) +#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) +#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) +#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) +#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) +#define ESDCFG_TWR (1 << 15) +#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) +#define ESDCFG_TRP(x) (((x) & 0x3) << 18) +#define ESDCFG_TWTR (1 << 20) +#define ESDCFG_TXP(x) (((x) & 0x3) << 21) + +#define ESDMISC_RST (1 << 1) +#define ESDMISC_MDDREN (1 << 2) +#define ESDMISC_MDDR_DL_RST (1 << 3) +#define ESDMISC_MDDR_MDIS (1 << 4) +#define ESDMISC_LHD (1 << 5) +#define ESDMISC_MA10_SHARE (1 << 6) +#define ESDMISC_SDRAM_RDY (1 << 31) + +/* GPT bits */ +#define GPT_CTRL_SWR (1 << 15) /* Software reset */ +#define GPT_CTRL_FRR (1 << 9) /* Freerun / restart */ +#define GPT_CTRL_CLKSOURCE_32 (4 << 6) /* Clock source */ +#define GPT_CTRL_TEN 1 /* Timer enable */ + +/* WDOG enable */ +#define WCR_WDE 0x04 +#define WSR_UNLOCK1 0x5555 +#define WSR_UNLOCK2 0xAAAA + +/* MAX bits */ +#define MAX_MGPCR_AULB(x) (((x) & 0x7) << 0) + +/* M3IF bits */ +#define M3IF_CTL_MRRP(x) (((x) & 0xff) << 0) + +/* WEIM bits */ +/* 13 fields of the upper CS control register */ +#define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ + cnc, wsc, ew, wws, edc) \ + ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \ + (psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \ + (cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0) +/* 12 fields of the lower CS control register */ +#define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \ + csa, ebc, dsz, csn, psr, cre, wrap, csen) \ + ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ + (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ + (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) +/* 14 fields of the additional CS control register */ +#define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ + wwu, age, cnc2, fce) \ + ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ + (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ + (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ + (age) << 2 | (cnc2) << 1 | (fce) << 0) + +/* Names used in GPIO driver */ +#define GPIO1_BASE_ADDR IMX_GPIO1_BASE +#define GPIO2_BASE_ADDR IMX_GPIO2_BASE +#define GPIO3_BASE_ADDR IMX_GPIO3_BASE +#define GPIO4_BASE_ADDR IMX_GPIO4_BASE + +/* + * CSPI register definitions + */ +#define MXC_SPI_BASE_ADDRESSES \ + IMX_CSPI1_BASE, \ + IMX_CSPI2_BASE, \ + IMX_CSPI3_BASE + +#endif /* _IMX_REGS_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx25/iomux-mx25.h b/roms/u-boot/arch/arm/include/asm/arch-mx25/iomux-mx25.h new file mode 100644 index 000000000..1ce7a8586 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx25/iomux-mx25.h @@ -0,0 +1,537 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 ADVANSEE + * Benoît Thébaudeau + * + * Based on mainline Linux i.MX iomux-mx25.h file: + * Copyright (C) 2009 by Lothar Wassmann + * + * Based on Linux arch/arm/mach-mx25/mx25_pins.h: + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * and Linux arch/arm/plat-mxc/include/mach/iomux-mx35.h: + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH + */ + +#ifndef __IOMUX_MX25_H__ +#define __IOMUX_MX25_H__ + +#include + +/* Pad control groupings */ +#define MX25_KPP_ROW_PAD_CTRL PAD_CTL_PUS_100K_UP +#define MX25_KPP_COL_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) + +/* + * The naming convention for the pad modes is MX25_PAD___ + * If or refers to a GPIO, it is named GPIO__ + * See also iomux-v3.h + */ + +/* PAD MUX ALT INPSE PATH PADCTRL */ +enum { + MX25_PAD_A10__A10 = IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A10__GPIO_4_0 = IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_A13__A13 = IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A13__GPIO_4_1 = IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_A14__A14 = IOMUX_PAD(0x230, 0x010, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A14__GPIO_2_0 = IOMUX_PAD(0x230, 0x010, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_A15__A15 = IOMUX_PAD(0x234, 0x014, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A15__GPIO_2_1 = IOMUX_PAD(0x234, 0x014, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_A16__A16 = IOMUX_PAD(0x000, 0x018, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A16__GPIO_2_2 = IOMUX_PAD(0x000, 0x018, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_A17__A17 = IOMUX_PAD(0x238, 0x01c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A17__GPIO_2_3 = IOMUX_PAD(0x238, 0x01c, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_A18__A18 = IOMUX_PAD(0x23c, 0x020, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A18__GPIO_2_4 = IOMUX_PAD(0x23c, 0x020, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_A18__FEC_COL = IOMUX_PAD(0x23c, 0x020, 0x07, 0x504, 0, NO_PAD_CTRL), + + MX25_PAD_A19__A19 = IOMUX_PAD(0x240, 0x024, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A19__FEC_RX_ER = IOMUX_PAD(0x240, 0x024, 0x07, 0x518, 0, NO_PAD_CTRL), + MX25_PAD_A19__GPIO_2_5 = IOMUX_PAD(0x240, 0x024, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_A20__A20 = IOMUX_PAD(0x244, 0x028, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A20__GPIO_2_6 = IOMUX_PAD(0x244, 0x028, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_A20__FEC_RDATA2 = IOMUX_PAD(0x244, 0x028, 0x07, 0x50c, 0, NO_PAD_CTRL), + + MX25_PAD_A21__A21 = IOMUX_PAD(0x248, 0x02c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A21__GPIO_2_7 = IOMUX_PAD(0x248, 0x02c, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_A21__FEC_RDATA3 = IOMUX_PAD(0x248, 0x02c, 0x07, 0x510, 0, NO_PAD_CTRL), + + MX25_PAD_A22__A22 = IOMUX_PAD(0x000, 0x030, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A22__GPIO_2_8 = IOMUX_PAD(0x000, 0x030, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_A23__A23 = IOMUX_PAD(0x24c, 0x034, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A23__GPIO_2_9 = IOMUX_PAD(0x24c, 0x034, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_A24__A24 = IOMUX_PAD(0x250, 0x038, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A24__GPIO_2_10 = IOMUX_PAD(0x250, 0x038, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_A24__FEC_RX_CLK = IOMUX_PAD(0x250, 0x038, 0x07, 0x514, 0, NO_PAD_CTRL), + + MX25_PAD_A25__A25 = IOMUX_PAD(0x254, 0x03c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A25__GPIO_2_11 = IOMUX_PAD(0x254, 0x03c, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_A25__FEC_CRS = IOMUX_PAD(0x254, 0x03c, 0x07, 0x508, 0, NO_PAD_CTRL), + + MX25_PAD_EB0__EB0 = IOMUX_PAD(0x258, 0x040, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_EB0__AUD4_TXD = IOMUX_PAD(0x258, 0x040, 0x04, 0x464, 0, NO_PAD_CTRL), + MX25_PAD_EB0__GPIO_2_12 = IOMUX_PAD(0x258, 0x040, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_EB1__EB1 = IOMUX_PAD(0x25c, 0x044, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_EB1__AUD4_RXD = IOMUX_PAD(0x25c, 0x044, 0x04, 0x460, 0, NO_PAD_CTRL), + MX25_PAD_EB1__GPIO_2_13 = IOMUX_PAD(0x25c, 0x044, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_OE__OE = IOMUX_PAD(0x260, 0x048, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_OE__AUD4_TXC = IOMUX_PAD(0x260, 0x048, 0x04, 0, 0, NO_PAD_CTRL), + MX25_PAD_OE__GPIO_2_14 = IOMUX_PAD(0x260, 0x048, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CS0__CS0 = IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CS0__GPIO_4_2 = IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CS1__CS1 = IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CS1__NF_CE3 = IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL), + MX25_PAD_CS1__GPIO_4_3 = IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CS4__CS4 = IOMUX_PAD(0x264, 0x054, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CS4__NF_CE1 = IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL), + MX25_PAD_CS4__UART5_CTS = IOMUX_PAD(0x264, 0x054, 0x03, 0, 0, NO_PAD_CTRL), + MX25_PAD_CS4__GPIO_3_20 = IOMUX_PAD(0x264, 0x054, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CS5__CS5 = IOMUX_PAD(0x268, 0x058, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CS5__NF_CE2 = IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL), + MX25_PAD_CS5__UART5_RTS = IOMUX_PAD(0x268, 0x058, 0x03, 0x574, 0, NO_PAD_CTRL), + MX25_PAD_CS5__GPIO_3_21 = IOMUX_PAD(0x268, 0x058, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_NF_CE0__NF_CE0 = IOMUX_PAD(0x26c, 0x05c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_NF_CE0__GPIO_3_22 = IOMUX_PAD(0x26c, 0x05c, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_ECB__ECB = IOMUX_PAD(0x270, 0x060, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_ECB__UART5_TXD_MUX = IOMUX_PAD(0x270, 0x060, 0x03, 0, 0, NO_PAD_CTRL), + MX25_PAD_ECB__GPIO_3_23 = IOMUX_PAD(0x270, 0x060, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_LBA__LBA = IOMUX_PAD(0x274, 0x064, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_LBA__UART5_RXD_MUX = IOMUX_PAD(0x274, 0x064, 0x03, 0x578, 0, NO_PAD_CTRL), + MX25_PAD_LBA__GPIO_3_24 = IOMUX_PAD(0x274, 0x064, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_BCLK__BCLK = IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_BCLK__GPIO_4_4 = IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_RW__RW = IOMUX_PAD(0x278, 0x06c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_RW__AUD4_TXFS = IOMUX_PAD(0x278, 0x06c, 0x04, 0x474, 0, NO_PAD_CTRL), + MX25_PAD_RW__GPIO_3_25 = IOMUX_PAD(0x278, 0x06c, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_NFWE_B__NFWE_B = IOMUX_PAD(0x000, 0x070, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_NFWE_B__GPIO_3_26 = IOMUX_PAD(0x000, 0x070, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_NFRE_B__NFRE_B = IOMUX_PAD(0x000, 0x074, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_NFRE_B__GPIO_3_27 = IOMUX_PAD(0x000, 0x074, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_NFALE__NFALE = IOMUX_PAD(0x000, 0x078, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_NFALE__GPIO_3_28 = IOMUX_PAD(0x000, 0x078, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_NFCLE__NFCLE = IOMUX_PAD(0x000, 0x07c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_NFCLE__GPIO_3_29 = IOMUX_PAD(0x000, 0x07c, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_NFWP_B__NFWP_B = IOMUX_PAD(0x000, 0x080, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_NFWP_B__GPIO_3_30 = IOMUX_PAD(0x000, 0x080, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_NFRB__NFRB = IOMUX_PAD(0x27c, 0x084, 0x00, 0, 0, PAD_CTL_PKE), + MX25_PAD_NFRB__GPIO_3_31 = IOMUX_PAD(0x27c, 0x084, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_D15__D15 = IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_D15__LD16 = IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_D15__GPIO_4_5 = IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_D14__D14 = IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_D14__LD17 = IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_D14__GPIO_4_6 = IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_D13__D13 = IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_D13__LD18 = IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_D13__GPIO_4_7 = IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_D12__D12 = IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_D12__GPIO_4_8 = IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_D11__D11 = IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_D11__GPIO_4_9 = IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_D10__D10 = IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_D10__GPIO_4_10 = IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_D10__USBOTG_OC = IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP), + + MX25_PAD_D9__D9 = IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_D9__GPIO_4_11 = IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_D9__USBH2_PWR = IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE), + + MX25_PAD_D8__D8 = IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_D8__GPIO_4_12 = IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_D8__USBH2_OC = IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP), + + MX25_PAD_D7__D7 = IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_D7__GPIO_4_13 = IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_D6__D6 = IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_D6__GPIO_4_14 = IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_D5__D5 = IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_D5__GPIO_4_15 = IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_D4__D4 = IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_D4__GPIO_4_16 = IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_D3__D3 = IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_D3__GPIO_4_17 = IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_D2__D2 = IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_D2__GPIO_4_18 = IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_D1__D1 = IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_D1__GPIO_4_19 = IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_D0__D0 = IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_D0__GPIO_4_20 = IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_LD0__LD0 = IOMUX_PAD(0x2c0, 0x0c8, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD0__CSI_D0 = IOMUX_PAD(0x2c0, 0x0c8, 0x02, 0x488, 0, NO_PAD_CTRL), + MX25_PAD_LD0__GPIO_2_15 = IOMUX_PAD(0x2c0, 0x0c8, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_LD1__LD1 = IOMUX_PAD(0x2c4, 0x0cc, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD1__CSI_D1 = IOMUX_PAD(0x2c4, 0x0cc, 0x02, 0x48c, 0, NO_PAD_CTRL), + MX25_PAD_LD1__GPIO_2_16 = IOMUX_PAD(0x2c4, 0x0cc, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_LD2__LD2 = IOMUX_PAD(0x2c8, 0x0d0, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD2__GPIO_2_17 = IOMUX_PAD(0x2c8, 0x0d0, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_LD3__LD3 = IOMUX_PAD(0x2cc, 0x0d4, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD3__GPIO_2_18 = IOMUX_PAD(0x2cc, 0x0d4, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_LD4__LD4 = IOMUX_PAD(0x2d0, 0x0d8, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD4__GPIO_2_19 = IOMUX_PAD(0x2d0, 0x0d8, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_LD5__LD5 = IOMUX_PAD(0x2d4, 0x0dc, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD5__GPIO_1_19 = IOMUX_PAD(0x2d4, 0x0dc, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_LD6__LD6 = IOMUX_PAD(0x2d8, 0x0e0, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD6__GPIO_1_20 = IOMUX_PAD(0x2d8, 0x0e0, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_LD7__LD7 = IOMUX_PAD(0x2dc, 0x0e4, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD7__GPIO_1_21 = IOMUX_PAD(0x2dc, 0x0e4, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_LD8__LD8 = IOMUX_PAD(0x2e0, 0x0e8, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD8__FEC_TX_ERR = IOMUX_PAD(0x2e0, 0x0e8, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_LD9__LD9 = IOMUX_PAD(0x2e4, 0x0ec, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD9__FEC_COL = IOMUX_PAD(0x2e4, 0x0ec, 0x05, 0x504, 1, NO_PAD_CTRL), + + MX25_PAD_LD10__LD10 = IOMUX_PAD(0x2e8, 0x0f0, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD10__FEC_RX_ER = IOMUX_PAD(0x2e8, 0x0f0, 0x05, 0x518, 1, NO_PAD_CTRL), + + MX25_PAD_LD11__LD11 = IOMUX_PAD(0x2ec, 0x0f4, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD11__FEC_RDATA2 = IOMUX_PAD(0x2ec, 0x0f4, 0x05, 0x50c, 1, NO_PAD_CTRL), + + MX25_PAD_LD12__LD12 = IOMUX_PAD(0x2f0, 0x0f8, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD12__FEC_RDATA3 = IOMUX_PAD(0x2f0, 0x0f8, 0x05, 0x510, 1, NO_PAD_CTRL), + + MX25_PAD_LD13__LD13 = IOMUX_PAD(0x2f4, 0x0fc, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD13__FEC_TDATA2 = IOMUX_PAD(0x2f4, 0x0fc, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_LD14__LD14 = IOMUX_PAD(0x2f8, 0x100, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD14__FEC_TDATA3 = IOMUX_PAD(0x2f8, 0x100, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_LD15__LD15 = IOMUX_PAD(0x2fc, 0x104, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD15__FEC_RX_CLK = IOMUX_PAD(0x2fc, 0x104, 0x05, 0x514, 1, NO_PAD_CTRL), + + MX25_PAD_HSYNC__HSYNC = IOMUX_PAD(0x300, 0x108, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_HSYNC__GPIO_1_22 = IOMUX_PAD(0x300, 0x108, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_VSYNC__VSYNC = IOMUX_PAD(0x304, 0x10c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_VSYNC__GPIO_1_23 = IOMUX_PAD(0x304, 0x10c, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_LSCLK__LSCLK = IOMUX_PAD(0x308, 0x110, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_LSCLK__GPIO_1_24 = IOMUX_PAD(0x308, 0x110, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_OE_ACD__OE_ACD = IOMUX_PAD(0x30c, 0x114, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_OE_ACD__GPIO_1_25 = IOMUX_PAD(0x30c, 0x114, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CONTRAST__CONTRAST = IOMUX_PAD(0x310, 0x118, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CONTRAST__PWM4_PWMO = IOMUX_PAD(0x310, 0x118, 0x04, 0, 0, NO_PAD_CTRL), + MX25_PAD_CONTRAST__FEC_CRS = IOMUX_PAD(0x310, 0x118, 0x05, 0x508, 1, NO_PAD_CTRL), + + MX25_PAD_PWM__PWM = IOMUX_PAD(0x314, 0x11c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_PWM__GPIO_1_26 = IOMUX_PAD(0x314, 0x11c, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_PWM__USBH2_OC = IOMUX_PAD(0x314, 0x11c, 0x06, 0x580, 1, PAD_CTL_PUS_100K_UP), + + MX25_PAD_CSI_D2__CSI_D2 = IOMUX_PAD(0x318, 0x120, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D2__UART5_RXD_MUX = IOMUX_PAD(0x318, 0x120, 0x01, 0x578, 1, NO_PAD_CTRL), + MX25_PAD_CSI_D2__GPIO_1_27 = IOMUX_PAD(0x318, 0x120, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D2__CSPI3_MOSI = IOMUX_PAD(0x318, 0x120, 0x07, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CSI_D3__CSI_D3 = IOMUX_PAD(0x31c, 0x124, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D3__GPIO_1_28 = IOMUX_PAD(0x31c, 0x124, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D3__CSPI3_MISO = IOMUX_PAD(0x31c, 0x124, 0x07, 0x4b4, 1, NO_PAD_CTRL), + + MX25_PAD_CSI_D4__CSI_D4 = IOMUX_PAD(0x320, 0x128, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D4__UART5_RTS = IOMUX_PAD(0x320, 0x128, 0x01, 0x574, 1, NO_PAD_CTRL), + MX25_PAD_CSI_D4__GPIO_1_29 = IOMUX_PAD(0x320, 0x128, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D4__CSPI3_SCLK = IOMUX_PAD(0x320, 0x128, 0x07, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CSI_D5__CSI_D5 = IOMUX_PAD(0x324, 0x12c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D5__GPIO_1_30 = IOMUX_PAD(0x324, 0x12c, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D5__CSPI3_RDY = IOMUX_PAD(0x324, 0x12c, 0x07, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CSI_D6__CSI_D6 = IOMUX_PAD(0x328, 0x130, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D6__GPIO_1_31 = IOMUX_PAD(0x328, 0x130, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CSI_D7__CSI_D7 = IOMUX_PAD(0x32c, 0x134, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D7__GPIO_1_6 = IOMUX_PAD(0x32c, 0x134, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CSI_D8__CSI_D8 = IOMUX_PAD(0x330, 0x138, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D8__GPIO_1_7 = IOMUX_PAD(0x330, 0x138, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CSI_D9__CSI_D9 = IOMUX_PAD(0x334, 0x13c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D9__GPIO_4_21 = IOMUX_PAD(0x334, 0x13c, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x338, 0x140, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_MCLK__GPIO_1_8 = IOMUX_PAD(0x338, 0x140, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x33c, 0x144, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_VSYNC__GPIO_1_9 = IOMUX_PAD(0x33c, 0x144, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x340, 0x148, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_HSYNC__GPIO_1_10 = IOMUX_PAD(0x340, 0x148, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x344, 0x14c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_PIXCLK__GPIO_1_11 = IOMUX_PAD(0x344, 0x14c, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x348, 0x150, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_I2C1_CLK__GPIO_1_12 = IOMUX_PAD(0x348, 0x150, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x34c, 0x154, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_I2C1_DAT__GPIO_1_13 = IOMUX_PAD(0x34c, 0x154, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_MOSI__GPIO_1_14 = IOMUX_PAD(0x350, 0x158, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x354, 0x15c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_MISO__GPIO_1_15 = IOMUX_PAD(0x354, 0x15c, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x358, 0x160, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_SS0__GPIO_1_16 = IOMUX_PAD(0x358, 0x160, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_SS1__I2C3_DAT = IOMUX_PAD(0x35c, 0x164, 0x01, 0x528, 1, NO_PAD_CTRL), + MX25_PAD_CSPI1_SS1__GPIO_1_17 = IOMUX_PAD(0x35c, 0x164, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x360, 0x168, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_SCLK__GPIO_1_18 = IOMUX_PAD(0x360, 0x168, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CSPI1_RDY__CSPI1_RDY = IOMUX_PAD(0x364, 0x16c, 0x00, 0, 0, PAD_CTL_PKE), + MX25_PAD_CSPI1_RDY__GPIO_2_22 = IOMUX_PAD(0x364, 0x16c, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x368, 0x170, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN), + MX25_PAD_UART1_RXD__GPIO_4_22 = IOMUX_PAD(0x368, 0x170, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x36c, 0x174, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_UART1_TXD__GPIO_4_23 = IOMUX_PAD(0x36c, 0x174, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x00, 0, 0, PAD_CTL_PUS_100K_UP), + MX25_PAD_UART1_RTS__CSI_D0 = IOMUX_PAD(0x370, 0x178, 0x01, 0x488, 1, NO_PAD_CTRL), + MX25_PAD_UART1_RTS__GPIO_4_24 = IOMUX_PAD(0x370, 0x178, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x374, 0x17c, 0x00, 0, 0, PAD_CTL_PUS_100K_UP), + MX25_PAD_UART1_CTS__CSI_D1 = IOMUX_PAD(0x374, 0x17c, 0x01, 0x48c, 1, NO_PAD_CTRL), + MX25_PAD_UART1_CTS__GPIO_4_25 = IOMUX_PAD(0x374, 0x17c, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x378, 0x180, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_UART2_RXD__GPIO_4_26 = IOMUX_PAD(0x378, 0x180, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x37c, 0x184, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_UART2_TXD__GPIO_4_27 = IOMUX_PAD(0x37c, 0x184, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_UART2_RTS__UART2_RTS = IOMUX_PAD(0x380, 0x188, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_UART2_RTS__FEC_COL = IOMUX_PAD(0x380, 0x188, 0x02, 0x504, 2, NO_PAD_CTRL), + MX25_PAD_UART2_RTS__GPIO_4_28 = IOMUX_PAD(0x380, 0x188, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_UART2_CTS__FEC_RX_ER = IOMUX_PAD(0x384, 0x18c, 0x02, 0x518, 2, NO_PAD_CTRL), + MX25_PAD_UART2_CTS__UART2_CTS = IOMUX_PAD(0x384, 0x18c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_UART2_CTS__GPIO_4_29 = IOMUX_PAD(0x384, 0x18c, 0x05, 0, 0, NO_PAD_CTRL), + + /* + * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD + * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM + * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon + * bug that configuring the SD1_CMD function doesn't enable the input path for + * this pin. + * This might have side effects for other hardware units that are connected to + * that pin and use the respective function as input. + */ + MX25_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP), + MX25_PAD_SD1_CMD__FEC_RDATA2 = IOMUX_PAD(0x388, 0x190, 0x02, 0x50c, 2, NO_PAD_CTRL), + MX25_PAD_SD1_CMD__GPIO_2_23 = IOMUX_PAD(0x388, 0x190, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x38c, 0x194, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), + MX25_PAD_SD1_CLK__FEC_RDATA3 = IOMUX_PAD(0x38c, 0x194, 0x02, 0x510, 2, NO_PAD_CTRL), + MX25_PAD_SD1_CLK__GPIO_2_24 = IOMUX_PAD(0x38c, 0x194, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x390, 0x198, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), + MX25_PAD_SD1_DATA0__GPIO_2_25 = IOMUX_PAD(0x390, 0x198, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x394, 0x19c, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), + MX25_PAD_SD1_DATA1__AUD7_RXD = IOMUX_PAD(0x394, 0x19c, 0x03, 0x478, 0, NO_PAD_CTRL), + MX25_PAD_SD1_DATA1__GPIO_2_26 = IOMUX_PAD(0x394, 0x19c, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x398, 0x1a0, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), + MX25_PAD_SD1_DATA2__FEC_RX_CLK = IOMUX_PAD(0x398, 0x1a0, 0x05, 0x514, 2, NO_PAD_CTRL), + MX25_PAD_SD1_DATA2__GPIO_2_27 = IOMUX_PAD(0x398, 0x1a0, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), + MX25_PAD_SD1_DATA3__FEC_CRS = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0x508, 2, NO_PAD_CTRL), + MX25_PAD_SD1_DATA3__GPIO_2_28 = IOMUX_PAD(0x39c, 0x1a4, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_KPP_ROW0__KPP_ROW0 = IOMUX_PAD(0x3a0, 0x1a8, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), + MX25_PAD_KPP_ROW0__GPIO_2_29 = IOMUX_PAD(0x3a0, 0x1a8, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_KPP_ROW1__KPP_ROW1 = IOMUX_PAD(0x3a4, 0x1ac, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), + MX25_PAD_KPP_ROW1__GPIO_2_30 = IOMUX_PAD(0x3a4, 0x1ac, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_KPP_ROW2__KPP_ROW2 = IOMUX_PAD(0x3a8, 0x1b0, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), + MX25_PAD_KPP_ROW2__CSI_D0 = IOMUX_PAD(0x3a8, 0x1b0, 0x03, 0x488, 2, NO_PAD_CTRL), + MX25_PAD_KPP_ROW2__GPIO_2_31 = IOMUX_PAD(0x3a8, 0x1b0, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_KPP_ROW3__KPP_ROW3 = IOMUX_PAD(0x3ac, 0x1b4, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), + MX25_PAD_KPP_ROW3__CSI_LD1 = IOMUX_PAD(0x3ac, 0x1b4, 0x03, 0x48c, 2, NO_PAD_CTRL), + MX25_PAD_KPP_ROW3__GPIO_3_0 = IOMUX_PAD(0x3ac, 0x1b4, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_KPP_COL0__KPP_COL0 = IOMUX_PAD(0x3b0, 0x1b8, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), + MX25_PAD_KPP_COL0__UART4_RXD_MUX = IOMUX_PAD(0x3b0, 0x1b8, 0x01, 0x570, 1, NO_PAD_CTRL), + MX25_PAD_KPP_COL0__AUD5_TXD = IOMUX_PAD(0x3b0, 0x1b8, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), + MX25_PAD_KPP_COL0__GPIO_3_1 = IOMUX_PAD(0x3b0, 0x1b8, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_KPP_COL1__KPP_COL1 = IOMUX_PAD(0x3b4, 0x1bc, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), + MX25_PAD_KPP_COL1__UART4_TXD_MUX = IOMUX_PAD(0x3b4, 0x1bc, 0x01, 0, 0, NO_PAD_CTRL), + MX25_PAD_KPP_COL1__AUD5_RXD = IOMUX_PAD(0x3b4, 0x1bc, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), + MX25_PAD_KPP_COL1__GPIO_3_2 = IOMUX_PAD(0x3b4, 0x1bc, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_KPP_COL2__KPP_COL2 = IOMUX_PAD(0x3b8, 0x1c0, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), + MX25_PAD_KPP_COL2__UART4_RTS = IOMUX_PAD(0x3b8, 0x1c0, 0x01, 0, 0, NO_PAD_CTRL), + MX25_PAD_KPP_COL2__AUD5_TXC = IOMUX_PAD(0x3b8, 0x1c0, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), + MX25_PAD_KPP_COL2__GPIO_3_3 = IOMUX_PAD(0x3b8, 0x1c0, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_KPP_COL3__KPP_COL3 = IOMUX_PAD(0x3bc, 0x1c4, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), + MX25_PAD_KPP_COL3__UART4_CTS = IOMUX_PAD(0x3bc, 0x1c4, 0x01, 0, 0, NO_PAD_CTRL), + MX25_PAD_KPP_COL3__AUD5_TXFS = IOMUX_PAD(0x3bc, 0x1c4, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), + MX25_PAD_KPP_COL3__GPIO_3_4 = IOMUX_PAD(0x3bc, 0x1c4, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x3c0, 0x1c8, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_FEC_MDC__AUD4_TXD = IOMUX_PAD(0x3c0, 0x1c8, 0x02, 0x464, 1, NO_PAD_CTRL), + MX25_PAD_FEC_MDC__GPIO_3_5 = IOMUX_PAD(0x3c0, 0x1c8, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x3c4, 0x1cc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP), + MX25_PAD_FEC_MDIO__AUD4_RXD = IOMUX_PAD(0x3c4, 0x1cc, 0x02, 0x460, 1, NO_PAD_CTRL), + MX25_PAD_FEC_MDIO__GPIO_3_6 = IOMUX_PAD(0x3c4, 0x1cc, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_FEC_TDATA0__FEC_TDATA0 = IOMUX_PAD(0x3c8, 0x1d0, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_FEC_TDATA0__GPIO_3_7 = IOMUX_PAD(0x3c8, 0x1d0, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_FEC_TDATA1__FEC_TDATA1 = IOMUX_PAD(0x3cc, 0x1d4, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_FEC_TDATA1__AUD4_TXFS = IOMUX_PAD(0x3cc, 0x1d4, 0x02, 0x474, 1, NO_PAD_CTRL), + MX25_PAD_FEC_TDATA1__GPIO_3_8 = IOMUX_PAD(0x3cc, 0x1d4, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x3d0, 0x1d8, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_FEC_TX_EN__GPIO_3_9 = IOMUX_PAD(0x3d0, 0x1d8, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_FEC_RDATA0__FEC_RDATA0 = IOMUX_PAD(0x3d4, 0x1dc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), + MX25_PAD_FEC_RDATA0__GPIO_3_10 = IOMUX_PAD(0x3d4, 0x1dc, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_FEC_RDATA1__FEC_RDATA1 = IOMUX_PAD(0x3d8, 0x1e0, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), + MX25_PAD_FEC_RDATA1__GPIO_3_11 = IOMUX_PAD(0x3d8, 0x1e0, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x3dc, 0x1e4, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), + MX25_PAD_FEC_RX_DV__CAN2_RX = IOMUX_PAD(0x3dc, 0x1e4, 0x04, 0x484, 0, PAD_CTL_PUS_22K_UP), + MX25_PAD_FEC_RX_DV__GPIO_3_12 = IOMUX_PAD(0x3dc, 0x1e4, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x3e0, 0x1e8, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), + MX25_PAD_FEC_TX_CLK__GPIO_3_13 = IOMUX_PAD(0x3e0, 0x1e8, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_RTCK__RTCK = IOMUX_PAD(0x3e4, 0x1ec, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_RTCK__OWIRE = IOMUX_PAD(0x3e4, 0x1ec, 0x01, 0, 0, NO_PAD_CTRL), + MX25_PAD_RTCK__GPIO_3_14 = IOMUX_PAD(0x3e4, 0x1ec, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_DE_B__DE_B = IOMUX_PAD(0x3ec, 0x1f0, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_DE_B__GPIO_2_20 = IOMUX_PAD(0x3ec, 0x1f0, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_TDO__TDO = IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL), + + MX25_PAD_GPIO_A__GPIO_A = IOMUX_PAD(0x3f0, 0x1f4, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_GPIO_A__CAN1_TX = IOMUX_PAD(0x3f0, 0x1f4, 0x06, 0, 0, PAD_CTL_PUS_22K_UP), + MX25_PAD_GPIO_A__USBOTG_PWR = IOMUX_PAD(0x3f0, 0x1f4, 0x02, 0, 0, PAD_CTL_PKE), + + MX25_PAD_GPIO_B__GPIO_B = IOMUX_PAD(0x3f4, 0x1f8, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_GPIO_B__CAN1_RX = IOMUX_PAD(0x3f4, 0x1f8, 0x06, 0x480, 1, PAD_CTL_PUS_22K_UP), + MX25_PAD_GPIO_B__USBOTG_OC = IOMUX_PAD(0x3f4, 0x1f8, 0x02, 0x57c, 1, PAD_CTL_PUS_100K_UP), + + MX25_PAD_GPIO_C__GPIO_C = IOMUX_PAD(0x3f8, 0x1fc, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_GPIO_C__CAN2_TX = IOMUX_PAD(0x3f8, 0x1fc, 0x06, 0, 0, PAD_CTL_PUS_22K_UP), + + MX25_PAD_GPIO_D__GPIO_D = IOMUX_PAD(0x3fc, 0x200, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_GPIO_E__LD16 = IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_GPIO_D__CAN2_RX = IOMUX_PAD(0x3fc, 0x200, 0x06, 0x484, 1, PAD_CTL_PUS_22K_UP), + + MX25_PAD_GPIO_E__GPIO_E = IOMUX_PAD(0x400, 0x204, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_GPIO_F__LD17 = IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_GPIO_E__I2C3_CLK = IOMUX_PAD(0x400, 0x204, 0x01, 0x524, 2, NO_PAD_CTRL), + MX25_PAD_GPIO_E__AUD7_TXD = IOMUX_PAD(0x400, 0x204, 0x04, 0, 0, NO_PAD_CTRL), + + MX25_PAD_GPIO_F__GPIO_F = IOMUX_PAD(0x404, 0x208, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_GPIO_F__AUD7_TXC = IOMUX_PAD(0x404, 0x208, 0x04, 0, 0, NO_PAD_CTRL), + + MX25_PAD_EXT_ARMCLK__EXT_ARMCLK = IOMUX_PAD(0x000, 0x20c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_EXT_ARMCLK__GPIO_3_15 = IOMUX_PAD(0x000, 0x20c, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK = IOMUX_PAD(0x000, 0x210, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_UPLL_BYPCLK__GPIO_3_16 = IOMUX_PAD(0x000, 0x210, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_VSTBY_REQ__VSTBY_REQ = IOMUX_PAD(0x408, 0x214, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_VSTBY_REQ__AUD7_TXFS = IOMUX_PAD(0x408, 0x214, 0x04, 0, 0, NO_PAD_CTRL), + MX25_PAD_VSTBY_REQ__GPIO_3_17 = IOMUX_PAD(0x408, 0x214, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_VSTBY_ACK__VSTBY_ACK = IOMUX_PAD(0x40c, 0x218, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_VSTBY_ACK__GPIO_3_18 = IOMUX_PAD(0x40c, 0x218, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_POWER_FAIL__POWER_FAIL = IOMUX_PAD(0x410, 0x21c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_POWER_FAIL__AUD7_RXD = IOMUX_PAD(0x410, 0x21c, 0x04, 0x478, 1, NO_PAD_CTRL), + MX25_PAD_POWER_FAIL__GPIO_3_19 = IOMUX_PAD(0x410, 0x21c, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CLKO__CLKO = IOMUX_PAD(0x414, 0x220, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CLKO__GPIO_2_21 = IOMUX_PAD(0x414, 0x220, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_BOOT_MODE0__BOOT_MODE0 = IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_BOOT_MODE0__GPIO_4_30 = IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_BOOT_MODE1__BOOT_MODE1 = IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_BOOT_MODE1__GPIO_4_31 = IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL), + + MX25_PAD_CTL_GRP_DVS_MISC = IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL), + MX25_PAD_CTL_GRP_DSE_FEC = IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL), + MX25_PAD_CTL_GRP_DVS_JTAG = IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL), + MX25_PAD_CTL_GRP_DSE_NFC = IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL), + MX25_PAD_CTL_GRP_DSE_CSI = IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL), + MX25_PAD_CTL_GRP_DSE_WEIM = IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL), + MX25_PAD_CTL_GRP_DSE_DDR = IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL), + MX25_PAD_CTL_GRP_DVS_CRM = IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL), + MX25_PAD_CTL_GRP_DSE_KPP = IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL), + MX25_PAD_CTL_GRP_DSE_SDHC1 = IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL), + MX25_PAD_CTL_GRP_DSE_LCD = IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL), + MX25_PAD_CTL_GRP_DSE_UART = IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL), + MX25_PAD_CTL_GRP_DVS_NFC = IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL), + MX25_PAD_CTL_GRP_DVS_CSI = IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL), + MX25_PAD_CTL_GRP_DSE_CSPI1 = IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL), + MX25_PAD_CTL_GRP_DDRTYPE = IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL), + MX25_PAD_CTL_GRP_DVS_SDHC1 = IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL), + MX25_PAD_CTL_GRP_DVS_LCD = IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL), +}; + +#endif /* __IOMUX_MX25_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx25/macro.h b/roms/u-boot/arch/arm/include/asm/arch-mx25/macro.h new file mode 100644 index 000000000..68bddf495 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx25/macro.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 + * Matthias Weisser + * + * (C) Copyright 2009 DENX Software Engineering + * Author: John Rigby + * + * Common asm macros for imx25 + */ + +#ifndef __ASM_ARM_ARCH_MACRO_H__ +#define __ASM_ARM_ARCH_MACRO_H__ +#ifdef __ASSEMBLY__ + +#include +#include +#include + +/* + * AIPS setup - Only setup MPROTx registers. + * The PACR default values are good. + * + * Default argument values: + * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to + * user-mode. + */ +.macro init_aips mpr=0x77777777 + ldr r0, =IMX_AIPS1_BASE + ldr r1, =\mpr + str r1, [r0, #AIPS_MPR_0_7] + str r1, [r0, #AIPS_MPR_8_15] + ldr r2, =IMX_AIPS2_BASE + str r1, [r2, #AIPS_MPR_0_7] + str r1, [r2, #AIPS_MPR_8_15] +.endm + +/* + * MAX (Multi-Layer AHB Crossbar Switch) setup + * + * Default argument values: + * - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA + * - SGPCR: always park on last master + * - MGPCR: restore default values + */ +.macro init_max mpr=0x00043210, sgpcr=0x00000010, mgpcr=0x00000000 + ldr r0, =IMX_MAX_BASE + ldr r1, =\mpr + str r1, [r0, #MAX_MPR0] /* for S0 */ + str r1, [r0, #MAX_MPR1] /* for S1 */ + str r1, [r0, #MAX_MPR2] /* for S2 */ + str r1, [r0, #MAX_MPR3] /* for S3 */ + str r1, [r0, #MAX_MPR4] /* for S4 */ + ldr r1, =\sgpcr + str r1, [r0, #MAX_SGPCR0] /* for S0 */ + str r1, [r0, #MAX_SGPCR1] /* for S1 */ + str r1, [r0, #MAX_SGPCR2] /* for S2 */ + str r1, [r0, #MAX_SGPCR3] /* for S3 */ + str r1, [r0, #MAX_SGPCR4] /* for S4 */ + ldr r1, =\mgpcr + str r1, [r0, #MAX_MGPCR0] /* for M0 */ + str r1, [r0, #MAX_MGPCR1] /* for M1 */ + str r1, [r0, #MAX_MGPCR2] /* for M2 */ + str r1, [r0, #MAX_MGPCR3] /* for M3 */ + str r1, [r0, #MAX_MGPCR4] /* for M4 */ +.endm + +/* + * M3IF setup + * + * Default argument values: + * - CTL: + * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001 + * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000 + * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000 + * MRRP[3] = USBH not on priority list (0 << 3) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 + * MRRP[5] = eSDHC1/ATA/FEC not on priority list (0 << 5) = 0x00000000 + * MRRP[6] = LCDC/SLCDC/MAX2 not on priority list (0 << 6) = 0x00000000 + * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000 + * ------------ + * 0x00000001 + */ +.macro init_m3if ctl=0x00000001 + /* M3IF Control Register (M3IFCTL) */ + write32 IMX_M3IF_CTRL_BASE, \ctl +.endm + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARM_ARCH_MACRO_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx27/clock.h b/roms/u-boot/arch/arm/include/asm/arch-mx27/clock.h new file mode 100644 index 000000000..ab96431cb --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx27/clock.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * + * (c) 2009 Ilya Yanok, Emcraft Systems + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +enum mxc_clock { + MXC_ARM_CLK, + MXC_I2C_CLK, + MXC_UART_CLK, + MXC_ESDHC_CLK, + MXC_FEC_CLK, +}; + +unsigned int mxc_get_clock(enum mxc_clock clk); +#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK) +#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx27/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-mx27/gpio.h new file mode 100644 index 000000000..9f342eb7f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx27/gpio.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 + * Philippe Reynes + */ + + +#ifndef __ASM_ARCH_MX27_GPIO_H +#define __ASM_ARCH_MX27_GPIO_H + +/* GPIO registers */ +struct gpio_regs { + u32 gpio_dir; /* DDIR */ + u32 ocr1; + u32 ocr2; + u32 iconfa1; + u32 iconfa2; + u32 iconfb1; + u32 iconfb2; + u32 gpio_dr; /* DR */ + u32 gius; + u32 gpio_psr; /* SSR */ + u32 icr1; + u32 icr2; + u32 imr; + u32 isr; + u32 gpr; + u32 swr; + u32 puen; + u32 res[0x2f]; +}; + +/* This structure is used by the function imx_gpio_mode */ +struct gpio_port_regs { + struct gpio_regs port[6]; +}; + +/* + * GPIO Module and I/O Multiplexer + */ +#define PORTA 0 +#define PORTB 1 +#define PORTC 2 +#define PORTD 3 +#define PORTE 4 +#define PORTF 5 + +#define GPIO_PIN_MASK 0x1f +#define GPIO_PORT_SHIFT 5 +#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) +#define GPIO_PORTA (PORTA << GPIO_PORT_SHIFT) +#define GPIO_PORTB (PORTB << GPIO_PORT_SHIFT) +#define GPIO_PORTC (PORTC << GPIO_PORT_SHIFT) +#define GPIO_PORTD (PORTD << GPIO_PORT_SHIFT) +#define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT) +#define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT) + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx27/imx-regs.h b/roms/u-boot/arch/arm/include/asm/arch-mx27/imx-regs.h new file mode 100644 index 000000000..d39f6b035 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -0,0 +1,480 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (c) 2007 Pengutronix, Sascha Hauer + * (c) 2009 Ilya Yanok, Emcraft Systems + */ + +#ifndef _IMX_REGS_H +#define _IMX_REGS_H + +#include + +#ifndef __ASSEMBLY__ + +extern void imx_gpio_mode (int gpio_mode); + +#ifdef CONFIG_MXC_UART +extern void mx27_uart1_init_pins(void); +#endif /* CONFIG_MXC_UART */ + +#ifdef CONFIG_FEC_MXC +extern void mx27_fec_init_pins(void); +#endif /* CONFIG_FEC_MXC */ + +#ifdef CONFIG_MMC_MXC +extern void mx27_sd1_init_pins(void); +extern void mx27_sd2_init_pins(void); +#endif /* CONFIG_MMC_MXC */ + +/* AIPI */ +struct aipi_regs { + u32 psr0; + u32 psr1; +}; + +/* System Control */ +struct system_control_regs { + u32 res[5]; + u32 fmcr; + u32 gpcr; + u32 wbcr; + u32 dscr1; + u32 dscr2; + u32 dscr3; + u32 dscr4; + u32 dscr5; + u32 dscr6; + u32 dscr7; + u32 dscr8; + u32 dscr9; + u32 dscr10; + u32 dscr11; + u32 dscr12; + u32 dscr13; + u32 pscr; + u32 pmcr; + u32 res1; + u32 dcvr0; + u32 dcvr1; + u32 dcvr2; + u32 dcvr3; +}; + +/* Chip Select Registers */ +struct weim_regs { + u32 cs0u; /* Chip Select 0 Upper Register */ + u32 cs0l; /* Chip Select 0 Lower Register */ + u32 cs0a; /* Chip Select 0 Addition Register */ + u32 pad0; + u32 cs1u; /* Chip Select 1 Upper Register */ + u32 cs1l; /* Chip Select 1 Lower Register */ + u32 cs1a; /* Chip Select 1 Addition Register */ + u32 pad1; + u32 cs2u; /* Chip Select 2 Upper Register */ + u32 cs2l; /* Chip Select 2 Lower Register */ + u32 cs2a; /* Chip Select 2 Addition Register */ + u32 pad2; + u32 cs3u; /* Chip Select 3 Upper Register */ + u32 cs3l; /* Chip Select 3 Lower Register */ + u32 cs3a; /* Chip Select 3 Addition Register */ + u32 pad3; + u32 cs4u; /* Chip Select 4 Upper Register */ + u32 cs4l; /* Chip Select 4 Lower Register */ + u32 cs4a; /* Chip Select 4 Addition Register */ + u32 pad4; + u32 cs5u; /* Chip Select 5 Upper Register */ + u32 cs5l; /* Chip Select 5 Lower Register */ + u32 cs5a; /* Chip Select 5 Addition Register */ + u32 pad5; + u32 eim; /* WEIM Configuration Register */ +}; + +/* SDRAM Controller registers */ +struct esdramc_regs { +/* Enhanced SDRAM Control Register 0 */ + u32 esdctl0; +/* Enhanced SDRAM Configuration Register 0 */ + u32 esdcfg0; +/* Enhanced SDRAM Control Register 1 */ + u32 esdctl1; +/* Enhanced SDRAM Configuration Register 1 */ + u32 esdcfg1; +/* Enhanced SDRAM Miscellanious Register */ + u32 esdmisc; +}; + +/* Watchdog Registers*/ +struct wdog_regs { + u16 wcr; + u16 wsr; + u16 wstr; +}; + +/* PLL registers */ +struct pll_regs { + u32 cscr; /* Clock Source Control Register */ + u32 mpctl0; /* MCU PLL Control Register 0 */ + u32 mpctl1; /* MCU PLL Control Register 1 */ + u32 spctl0; /* System PLL Control Register 0 */ + u32 spctl1; /* System PLL Control Register 1 */ + u32 osc26mctl; /* Oscillator 26M Register */ + u32 pcdr0; /* Peripheral Clock Divider Register 0 */ + u32 pcdr1; /* Peripheral Clock Divider Register 1 */ + u32 pccr0; /* Peripheral Clock Control Register 0 */ + u32 pccr1; /* Peripheral Clock Control Register 1 */ + u32 ccsr; /* Clock Control Status Register */ +}; + +/* + * Definitions for the clocksource registers + */ +struct gpt_regs { + u32 gpt_tctl; + u32 gpt_tprer; + u32 gpt_tcmp; + u32 gpt_tcr; + u32 gpt_tcn; + u32 gpt_tstat; +}; + +/* IIM Control Registers */ +struct iim_regs { + u32 iim_stat; + u32 iim_statm; + u32 iim_err; + u32 iim_emask; + u32 iim_fctl; + u32 iim_ua; + u32 iim_la; + u32 iim_sdat; + u32 iim_prev; + u32 iim_srev; + u32 iim_prg_p; + u32 iim_scs0; + u32 iim_scs1; + u32 iim_scs2; + u32 iim_scs3; + u32 res[0x1f1]; + struct fuse_bank { + u32 fuse_regs[0x20]; + u32 fuse_rsvd[0xe0]; + } bank[2]; +}; + +struct fuse_bank0_regs { + u32 fuse0_3[5]; + u32 mac_addr[6]; + u32 fuse10_31[0x16]; +}; + +#endif + +#define ARCH_MXC + +#define IMX_IO_BASE 0x10000000 + +#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) +#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE) +#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) +#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) +#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) +#define IMX_RTC_BASE (0x07000 + IMX_IO_BASE) +#define UART1_BASE (0x0a000 + IMX_IO_BASE) +#define UART2_BASE (0x0b000 + IMX_IO_BASE) +#define UART3_BASE (0x0c000 + IMX_IO_BASE) +#define UART4_BASE (0x0d000 + IMX_IO_BASE) +#define I2C1_BASE_ADDR (0x12000 + IMX_IO_BASE) +#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) +#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) +#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE) +#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE) +#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE) +#define I2C2_BASE_ADDR (0x1D000 + IMX_IO_BASE) +#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE) +#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) +#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) +#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE) +#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE) +#define IIM_BASE_ADDR IMX_IIM_BASE +#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE) + +#define IMX_NFC_BASE (0xD8000000) +#define IMX_ESD_BASE (0xD8001000) +#define IMX_WEIM_BASE (0xD8002000) + +#define NFC_BASE_ADDR IMX_NFC_BASE + + +/* FMCR System Control bit definition*/ +#define UART4_RXD_CTL (1 << 25) +#define UART4_RTS_CTL (1 << 24) +#define KP_COL6_CTL (1 << 18) +#define KP_ROW7_CTL (1 << 17) +#define KP_ROW6_CTL (1 << 16) +#define PC_WAIT_B_CTL (1 << 14) +#define PC_READY_CTL (1 << 13) +#define PC_VS1_CTL (1 << 12) +#define PC_VS2_CTL (1 << 11) +#define PC_BVD1_CTL (1 << 10) +#define PC_BVD2_CTL (1 << 9) +#define IOS16_CTL (1 << 8) +#define NF_FMS (1 << 5) +#define NF_16BIT_SEL (1 << 4) +#define SLCDC_SEL (1 << 2) +#define SDCS1_SEL (1 << 1) +#define SDCS0_SEL (1 << 0) + + +/* important definition of some bits of WCR */ +#define WCR_WDE 0x04 + +#define CSCR_MPEN (1 << 0) +#define CSCR_SPEN (1 << 1) +#define CSCR_FPM_EN (1 << 2) +#define CSCR_OSC26M_DIS (1 << 3) +#define CSCR_OSC26M_DIV1P5 (1 << 4) +#define CSCR_AHB_DIV +#define CSCR_ARM_DIV +#define CSCR_ARM_SRC_MPLL (1 << 15) +#define CSCR_MCU_SEL (1 << 16) +#define CSCR_SP_SEL (1 << 17) +#define CSCR_MPLL_RESTART (1 << 18) +#define CSCR_SPLL_RESTART (1 << 19) +#define CSCR_MSHC_SEL (1 << 20) +#define CSCR_H264_SEL (1 << 21) +#define CSCR_SSI1_SEL (1 << 22) +#define CSCR_SSI2_SEL (1 << 23) +#define CSCR_SD_CNT +#define CSCR_USB_DIV +#define CSCR_UPDATE_DIS (1 << 31) + +#define MPCTL1_BRMO (1 << 6) +#define MPCTL1_LF (1 << 15) + +#define PCCR0_SSI2_EN (1 << 0) +#define PCCR0_SSI1_EN (1 << 1) +#define PCCR0_SLCDC_EN (1 << 2) +#define PCCR0_SDHC3_EN (1 << 3) +#define PCCR0_SDHC2_EN (1 << 4) +#define PCCR0_SDHC1_EN (1 << 5) +#define PCCR0_SDC_EN (1 << 6) +#define PCCR0_SAHARA_EN (1 << 7) +#define PCCR0_RTIC_EN (1 << 8) +#define PCCR0_RTC_EN (1 << 9) +#define PCCR0_PWM_EN (1 << 11) +#define PCCR0_OWIRE_EN (1 << 12) +#define PCCR0_MSHC_EN (1 << 13) +#define PCCR0_LCDC_EN (1 << 14) +#define PCCR0_KPP_EN (1 << 15) +#define PCCR0_IIM_EN (1 << 16) +#define PCCR0_I2C2_EN (1 << 17) +#define PCCR0_I2C1_EN (1 << 18) +#define PCCR0_GPT6_EN (1 << 19) +#define PCCR0_GPT5_EN (1 << 20) +#define PCCR0_GPT4_EN (1 << 21) +#define PCCR0_GPT3_EN (1 << 22) +#define PCCR0_GPT2_EN (1 << 23) +#define PCCR0_GPT1_EN (1 << 24) +#define PCCR0_GPIO_EN (1 << 25) +#define PCCR0_FEC_EN (1 << 26) +#define PCCR0_EMMA_EN (1 << 27) +#define PCCR0_DMA_EN (1 << 28) +#define PCCR0_CSPI3_EN (1 << 29) +#define PCCR0_CSPI2_EN (1 << 30) +#define PCCR0_CSPI1_EN (1 << 31) + +#define PCCR1_MSHC_BAUDEN (1 << 2) +#define PCCR1_NFC_BAUDEN (1 << 3) +#define PCCR1_SSI2_BAUDEN (1 << 4) +#define PCCR1_SSI1_BAUDEN (1 << 5) +#define PCCR1_H264_BAUDEN (1 << 6) +#define PCCR1_PERCLK4_EN (1 << 7) +#define PCCR1_PERCLK3_EN (1 << 8) +#define PCCR1_PERCLK2_EN (1 << 9) +#define PCCR1_PERCLK1_EN (1 << 10) +#define PCCR1_HCLK_USB (1 << 11) +#define PCCR1_HCLK_SLCDC (1 << 12) +#define PCCR1_HCLK_SAHARA (1 << 13) +#define PCCR1_HCLK_RTIC (1 << 14) +#define PCCR1_HCLK_LCDC (1 << 15) +#define PCCR1_HCLK_H264 (1 << 16) +#define PCCR1_HCLK_FEC (1 << 17) +#define PCCR1_HCLK_EMMA (1 << 18) +#define PCCR1_HCLK_EMI (1 << 19) +#define PCCR1_HCLK_DMA (1 << 20) +#define PCCR1_HCLK_CSI (1 << 21) +#define PCCR1_HCLK_BROM (1 << 22) +#define PCCR1_HCLK_ATA (1 << 23) +#define PCCR1_WDT_EN (1 << 24) +#define PCCR1_USB_EN (1 << 25) +#define PCCR1_UART6_EN (1 << 26) +#define PCCR1_UART5_EN (1 << 27) +#define PCCR1_UART4_EN (1 << 28) +#define PCCR1_UART3_EN (1 << 29) +#define PCCR1_UART2_EN (1 << 30) +#define PCCR1_UART1_EN (1 << 31) + +/* SDRAM Controller registers bitfields */ +#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) +#define ESDCTL_BL (1 << 7) +#define ESDCTL_FP (1 << 8) +#define ESDCTL_PWDT(x) (((x) & 3) << 10) +#define ESDCTL_SREFR(x) (((x) & 7) << 13) +#define ESDCTL_DSIZ_16_UPPER (0 << 16) +#define ESDCTL_DSIZ_16_LOWER (1 << 16) +#define ESDCTL_DSIZ_32 (2 << 16) +#define ESDCTL_COL8 (0 << 20) +#define ESDCTL_COL9 (1 << 20) +#define ESDCTL_COL10 (2 << 20) +#define ESDCTL_ROW11 (0 << 24) +#define ESDCTL_ROW12 (1 << 24) +#define ESDCTL_ROW13 (2 << 24) +#define ESDCTL_ROW14 (3 << 24) +#define ESDCTL_ROW15 (4 << 24) +#define ESDCTL_SP (1 << 27) +#define ESDCTL_SMODE_NORMAL (0 << 28) +#define ESDCTL_SMODE_PRECHARGE (1 << 28) +#define ESDCTL_SMODE_AUTO_REF (2 << 28) +#define ESDCTL_SMODE_LOAD_MODE (3 << 28) +#define ESDCTL_SMODE_MAN_REF (4 << 28) +#define ESDCTL_SDE (1 << 31) + +#define ESDCFG_TRC(x) (((x) & 0xf) << 0) +#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) +#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) +#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) +#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) +#define ESDCFG_TWR (1 << 15) +#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) +#define ESDCFG_TRP(x) (((x) & 0x3) << 18) +#define ESDCFG_TWTR (1 << 20) +#define ESDCFG_TXP(x) (((x) & 0x3) << 21) + +#define ESDMISC_RST (1 << 1) +#define ESDMISC_MDDREN (1 << 2) +#define ESDMISC_MDDR_DL_RST (1 << 3) +#define ESDMISC_MDDR_MDIS (1 << 4) +#define ESDMISC_LHD (1 << 5) +#define ESDMISC_MA10_SHARE (1 << 6) +#define ESDMISC_SDRAM_RDY (1 << 31) + +#define PC5_PF_I2C2_DATA (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5) +#define PC6_PF_I2C2_CLK (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6) +#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7) +#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8) +#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9) +#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10) +#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11) +#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12) +#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13) + +#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0) +#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1) +#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2) +#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3) +#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4) +#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5) +#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6) +#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7) +#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8) +#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9) +#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10) +#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11) +#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12) +#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13) +#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14) +#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15) +#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16) +#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23) + +#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0) +#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1) +#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2) +#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3) +#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4) +#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6) +#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7) +#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8) +#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9) +#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10) +#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11) +#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12) +#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13) +#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14) +#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) +#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) +#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) +#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) +#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) +#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) +#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) +#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) +#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) +#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) +#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) +#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) +#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) +#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17) +#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18) +#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24) +#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25) + +/* Clocksource Bitfields */ +#define TCTL_SWR (1 << 15) /* Software reset */ +#define TCTL_FRR (1 << 8) /* Freerun / restart */ +#define TCTL_CAP (3 << 6) /* Capture Edge */ +#define TCTL_OM (1 << 5) /* output mode */ +#define TCTL_IRQEN (1 << 4) /* interrupt enable */ +#define TCTL_CLKSOURCE 1 /* Clock source bit position */ +#define TCTL_TEN 1 /* Timer enable */ +#define TPRER_PRES 0xff /* Prescale */ +#define TSTAT_CAPT (1 << 1) /* Capture event */ +#define TSTAT_COMP 1 /* Compare event */ + +#define GPIO1_BASE_ADDR 0x10015000 +#define GPIO2_BASE_ADDR 0x10015100 +#define GPIO3_BASE_ADDR 0x10015200 +#define GPIO4_BASE_ADDR 0x10015300 +#define GPIO5_BASE_ADDR 0x10015400 +#define GPIO6_BASE_ADDR 0x10015500 + +#define GPIO_OUT (1 << 8) +#define GPIO_IN (0 << 8) +#define GPIO_PUEN (1 << 9) + +#define GPIO_PF (1 << 10) +#define GPIO_AF (1 << 11) + +#define GPIO_OCR_SHIFT 12 +#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) +#define GPIO_AIN (0 << GPIO_OCR_SHIFT) +#define GPIO_BIN (1 << GPIO_OCR_SHIFT) +#define GPIO_CIN (2 << GPIO_OCR_SHIFT) +#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) + +#define GPIO_AOUT_SHIFT 14 +#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) + +#define GPIO_BOUT_SHIFT 16 +#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) + +#define IIM_STAT_BUSY (1 << 7) +#define IIM_STAT_PRGD (1 << 1) +#define IIM_STAT_SNSD (1 << 0) +#define IIM_ERR_PRGE (1 << 7) +#define IIM_ERR_WPE (1 << 6) +#define IIM_ERR_OPE (1 << 5) +#define IIM_ERR_RPE (1 << 4) +#define IIM_ERR_WLRE (1 << 3) +#define IIM_ERR_SNSE (1 << 2) +#define IIM_ERR_PARITYE (1 << 1) + +#endif /* _IMX_REGS_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx27/mxcmmc.h b/roms/u-boot/arch/arm/include/asm/arch-mx27/mxcmmc.h new file mode 100644 index 000000000..52fb0ab57 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx27/mxcmmc.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2009 Ilya Yanok + */ + +#ifndef ASM_ARCH_MXCMMC_H +#define ASM_ARCH_MXCMMC_H + +int mxc_mmc_init(struct bd_info *bis); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx27/regs-rtc.h b/roms/u-boot/arch/arm/include/asm/arch-mx27/regs-rtc.h new file mode 100644 index 000000000..8434f4c1c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx27/regs-rtc.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX27 RTC Register Definitions + * + * Copyright (C) 2012 Philippe Reynes + */ + +#ifndef __MX27_REGS_RTC_H__ +#define __MX27_REGS_RTC_H__ + +#ifndef __ASSEMBLY__ +struct rtc_regs { + u32 hourmin; + u32 seconds; + u32 alrm_hm; + u32 alrm_sec; + u32 rtcctl; + u32 rtcisr; + u32 rtcienr; + u32 stpwch; + u32 dayr; + u32 dayalarm; +}; +#endif /* __ASSEMBLY__ */ + +#endif /* __MX28_REGS_RTC_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx31/clock.h b/roms/u-boot/arch/arm/include/asm/arch-mx31/clock.h new file mode 100644 index 000000000..e99e115f7 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx31/clock.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +#define MXC_HCLK CONFIG_MX31_HCLK_FREQ + +#define MXC_CLK32 CONFIG_MX31_CLK32 + +enum mxc_clock { + MXC_ARM_CLK, + MXC_IPG_CLK, + MXC_IPG_PERCLK, + MXC_CSPI_CLK, + MXC_UART_CLK, + MXC_IPU_CLK, + MXC_ESDHC_CLK, + MXC_I2C_CLK, +}; + +unsigned int mxc_get_clock(enum mxc_clock clk); +extern u32 imx_get_uartclk(void); +extern void mx31_gpio_mux(unsigned long mode); +extern void mx31_set_pad(enum iomux_pins pin, u32 config); +extern void mx31_set_gpr(enum iomux_gp_func gp, char en); + +void mx31_uart1_hw_init(void); +void mx31_uart2_hw_init(void); +void mx31_spi2_hw_init(void); + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx31/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-mx31/gpio.h new file mode 100644 index 000000000..45e9fc619 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx31/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, + */ + + +#ifndef __ASM_ARCH_MX31_GPIO_H +#define __ASM_ARCH_MX31_GPIO_H + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx31/imx-regs.h b/roms/u-boot/arch/arm/include/asm/arch-mx31/imx-regs.h new file mode 100644 index 000000000..566db549e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -0,0 +1,895 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (c) 2007 Pengutronix, Sascha Hauer + */ + +#ifndef __ASM_ARCH_MX31_IMX_REGS_H +#define __ASM_ARCH_MX31_IMX_REGS_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include + +/* Clock control module registers */ +struct clock_control_regs { + u32 ccmr; + u32 pdr0; + u32 pdr1; + u32 rcsr; + u32 mpctl; + u32 upctl; + u32 spctl; + u32 cosr; + u32 cgr0; + u32 cgr1; + u32 cgr2; + u32 wimr0; + u32 ldc; + u32 dcvr0; + u32 dcvr1; + u32 dcvr2; + u32 dcvr3; + u32 ltr0; + u32 ltr1; + u32 ltr2; + u32 ltr3; + u32 ltbr0; + u32 ltbr1; + u32 pmcr0; + u32 pmcr1; + u32 pdr2; +}; + +/* IIM control registers */ +struct iim_regs { + u32 iim_stat; + u32 iim_statm; + u32 iim_err; + u32 iim_emask; + u32 iim_fctl; + u32 iim_ua; + u32 iim_la; + u32 iim_sdat; + u32 iim_prev; + u32 iim_srev; + u32 iim_prg_p; + u32 iim_scs0; + u32 iim_scs1; + u32 iim_scs2; + u32 iim_scs3; + u32 res[0x1f1]; + struct fuse_bank { + u32 fuse_regs[0x20]; + u32 fuse_rsvd[0xe0]; + } bank[3]; +}; + +struct fuse_bank0_regs { + u32 fuse0_5[6]; + u32 usr; + u32 fuse7_15[9]; +}; + +struct fuse_bank2_regs { + u32 fuse0; + u32 uid[8]; + u32 fuse9_15[7]; +}; + +struct iomuxc_regs { + u32 unused1; + u32 unused2; + u32 gpr; +}; + +struct mx3_cpu_type { + u8 srev; + u32 v; +}; + +#define IOMUX_PADNUM_MASK 0x1ff +#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK) + +/* + * various IOMUX pad functions + */ +enum iomux_pad_config { + PAD_CTL_NOLOOPBACK = 0x0 << 9, + PAD_CTL_LOOPBACK = 0x1 << 9, + PAD_CTL_PKE_NONE = 0x0 << 8, + PAD_CTL_PKE_ENABLE = 0x1 << 8, + PAD_CTL_PUE_KEEPER = 0x0 << 7, + PAD_CTL_PUE_PUD = 0x1 << 7, + PAD_CTL_100K_PD = 0x0 << 5, + PAD_CTL_100K_PU = 0x1 << 5, + PAD_CTL_47K_PU = 0x2 << 5, + PAD_CTL_22K_PU = 0x3 << 5, + PAD_CTL_HYS_CMOS = 0x0 << 4, + PAD_CTL_HYS_SCHMITZ = 0x1 << 4, + PAD_CTL_ODE_CMOS = 0x0 << 3, + PAD_CTL_ODE_OpenDrain = 0x1 << 3, + PAD_CTL_DRV_NORMAL = 0x0 << 1, + PAD_CTL_DRV_HIGH = 0x1 << 1, + PAD_CTL_DRV_MAX = 0x2 << 1, + PAD_CTL_SRE_SLOW = 0x0 << 0, + PAD_CTL_SRE_FAST = 0x1 << 0 +}; + +/* + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ + +enum iomux_pins { + MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0), + MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1), + MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2), + MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3), + MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4), + MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5), + MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6), + MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7), + MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8), + MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9), + MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10), + MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11), + MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12), + MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13), + MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14), + MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15), + MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16), + MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17), + MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18), + MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), + MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), + MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), + MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), + MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), + MX31_PIN_READ = IOMUX_PIN(0xff, 24), + MX31_PIN_WRITE = IOMUX_PIN(0xff, 25), + MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26), + MX31_PIN_SER_RS = IOMUX_PIN(89, 27), + MX31_PIN_LCS1 = IOMUX_PIN(88, 28), + MX31_PIN_LCS0 = IOMUX_PIN(87, 29), + MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30), + MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31), + MX31_PIN_SD_D_I = IOMUX_PIN(84, 32), + MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), + MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), + MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), + MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36), + MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), + MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), + MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), + MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), + MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), + MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), + MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), + MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), + MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), + MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), + MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), + MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), + MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), + MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), + MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), + MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), + MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), + MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), + MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55), + MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56), + MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57), + MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58), + MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59), + MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60), + MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61), + MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62), + MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63), + MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64), + MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65), + MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66), + MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67), + MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68), + MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69), + MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70), + MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71), + MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72), + MX31_PIN_USB_BYP = IOMUX_PIN(31, 73), + MX31_PIN_USB_OC = IOMUX_PIN(30, 74), + MX31_PIN_USB_PWR = IOMUX_PIN(29, 75), + MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76), + MX31_PIN_DE_B = IOMUX_PIN(0xff, 77), + MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78), + MX31_PIN_TDO = IOMUX_PIN(0xff, 79), + MX31_PIN_TDI = IOMUX_PIN(0xff, 80), + MX31_PIN_TMS = IOMUX_PIN(0xff, 81), + MX31_PIN_TCK = IOMUX_PIN(0xff, 82), + MX31_PIN_RTCK = IOMUX_PIN(0xff, 83), + MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84), + MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85), + MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86), + MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87), + MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88), + MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89), + MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90), + MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91), + MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92), + MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93), + MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94), + MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95), + MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96), + MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97), + MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98), + MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99), + MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100), + MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101), + MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102), + MX31_PIN_TXD2 = IOMUX_PIN(28, 103), + MX31_PIN_RXD2 = IOMUX_PIN(27, 104), + MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105), + MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106), + MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107), + MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108), + MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109), + MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110), + MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111), + MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112), + MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113), + MX31_PIN_CTS1 = IOMUX_PIN(39, 114), + MX31_PIN_RTS1 = IOMUX_PIN(38, 115), + MX31_PIN_TXD1 = IOMUX_PIN(37, 116), + MX31_PIN_RXD1 = IOMUX_PIN(36, 117), + MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118), + MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119), + MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120), + MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121), + MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122), + MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123), + MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124), + MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125), + MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126), + MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127), + MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128), + MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129), + MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130), + MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131), + MX31_PIN_SFS6 = IOMUX_PIN(26, 132), + MX31_PIN_SCK6 = IOMUX_PIN(25, 133), + MX31_PIN_SRXD6 = IOMUX_PIN(24, 134), + MX31_PIN_STXD6 = IOMUX_PIN(23, 135), + MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136), + MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137), + MX31_PIN_SRXD5 = IOMUX_PIN(22, 138), + MX31_PIN_STXD5 = IOMUX_PIN(21, 139), + MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140), + MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141), + MX31_PIN_SRXD4 = IOMUX_PIN(20, 142), + MX31_PIN_STXD4 = IOMUX_PIN(19, 143), + MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144), + MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145), + MX31_PIN_SRXD3 = IOMUX_PIN(18, 146), + MX31_PIN_STXD3 = IOMUX_PIN(17, 147), + MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148), + MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149), + MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150), + MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151), + MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152), + MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153), + MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154), + MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155), + MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156), + MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157), + MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158), + MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159), + MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160), + MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161), + MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162), + MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163), + MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164), + MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165), + MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166), + MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167), + MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168), + MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169), + MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170), + MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171), + MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172), + MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173), + MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174), + MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175), + MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176), + MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177), + MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178), + MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179), + MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180), + MX31_PIN_D0 = IOMUX_PIN(0xff, 181), + MX31_PIN_D1 = IOMUX_PIN(0xff, 182), + MX31_PIN_D2 = IOMUX_PIN(0xff, 183), + MX31_PIN_D3 = IOMUX_PIN(0xff, 184), + MX31_PIN_D4 = IOMUX_PIN(0xff, 185), + MX31_PIN_D5 = IOMUX_PIN(0xff, 186), + MX31_PIN_D6 = IOMUX_PIN(0xff, 187), + MX31_PIN_D7 = IOMUX_PIN(0xff, 188), + MX31_PIN_D8 = IOMUX_PIN(0xff, 189), + MX31_PIN_D9 = IOMUX_PIN(0xff, 190), + MX31_PIN_D10 = IOMUX_PIN(0xff, 191), + MX31_PIN_D11 = IOMUX_PIN(0xff, 192), + MX31_PIN_D12 = IOMUX_PIN(0xff, 193), + MX31_PIN_D13 = IOMUX_PIN(0xff, 194), + MX31_PIN_D14 = IOMUX_PIN(0xff, 195), + MX31_PIN_D15 = IOMUX_PIN(0xff, 196), + MX31_PIN_NFRB = IOMUX_PIN(16, 197), + MX31_PIN_NFCE_B = IOMUX_PIN(15, 198), + MX31_PIN_NFWP_B = IOMUX_PIN(14, 199), + MX31_PIN_NFCLE = IOMUX_PIN(13, 200), + MX31_PIN_NFALE = IOMUX_PIN(12, 201), + MX31_PIN_NFRE_B = IOMUX_PIN(11, 202), + MX31_PIN_NFWE_B = IOMUX_PIN(10, 203), + MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204), + MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205), + MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206), + MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207), + MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208), + MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209), + MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210), + MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211), + MX31_PIN_SDWE = IOMUX_PIN(0xff, 212), + MX31_PIN_CAS = IOMUX_PIN(0xff, 213), + MX31_PIN_RAS = IOMUX_PIN(0xff, 214), + MX31_PIN_RW = IOMUX_PIN(0xff, 215), + MX31_PIN_BCLK = IOMUX_PIN(0xff, 216), + MX31_PIN_LBA = IOMUX_PIN(0xff, 217), + MX31_PIN_ECB = IOMUX_PIN(0xff, 218), + MX31_PIN_CS5 = IOMUX_PIN(0xff, 219), + MX31_PIN_CS4 = IOMUX_PIN(0xff, 220), + MX31_PIN_CS3 = IOMUX_PIN(0xff, 221), + MX31_PIN_CS2 = IOMUX_PIN(0xff, 222), + MX31_PIN_CS1 = IOMUX_PIN(0xff, 223), + MX31_PIN_CS0 = IOMUX_PIN(0xff, 224), + MX31_PIN_OE = IOMUX_PIN(0xff, 225), + MX31_PIN_EB1 = IOMUX_PIN(0xff, 226), + MX31_PIN_EB0 = IOMUX_PIN(0xff, 227), + MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228), + MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229), + MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230), + MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231), + MX31_PIN_SD31 = IOMUX_PIN(0xff, 232), + MX31_PIN_SD30 = IOMUX_PIN(0xff, 233), + MX31_PIN_SD29 = IOMUX_PIN(0xff, 234), + MX31_PIN_SD28 = IOMUX_PIN(0xff, 235), + MX31_PIN_SD27 = IOMUX_PIN(0xff, 236), + MX31_PIN_SD26 = IOMUX_PIN(0xff, 237), + MX31_PIN_SD25 = IOMUX_PIN(0xff, 238), + MX31_PIN_SD24 = IOMUX_PIN(0xff, 239), + MX31_PIN_SD23 = IOMUX_PIN(0xff, 240), + MX31_PIN_SD22 = IOMUX_PIN(0xff, 241), + MX31_PIN_SD21 = IOMUX_PIN(0xff, 242), + MX31_PIN_SD20 = IOMUX_PIN(0xff, 243), + MX31_PIN_SD19 = IOMUX_PIN(0xff, 244), + MX31_PIN_SD18 = IOMUX_PIN(0xff, 245), + MX31_PIN_SD17 = IOMUX_PIN(0xff, 246), + MX31_PIN_SD16 = IOMUX_PIN(0xff, 247), + MX31_PIN_SD15 = IOMUX_PIN(0xff, 248), + MX31_PIN_SD14 = IOMUX_PIN(0xff, 249), + MX31_PIN_SD13 = IOMUX_PIN(0xff, 250), + MX31_PIN_SD12 = IOMUX_PIN(0xff, 251), + MX31_PIN_SD11 = IOMUX_PIN(0xff, 252), + MX31_PIN_SD10 = IOMUX_PIN(0xff, 253), + MX31_PIN_SD9 = IOMUX_PIN(0xff, 254), + MX31_PIN_SD8 = IOMUX_PIN(0xff, 255), + MX31_PIN_SD7 = IOMUX_PIN(0xff, 256), + MX31_PIN_SD6 = IOMUX_PIN(0xff, 257), + MX31_PIN_SD5 = IOMUX_PIN(0xff, 258), + MX31_PIN_SD4 = IOMUX_PIN(0xff, 259), + MX31_PIN_SD3 = IOMUX_PIN(0xff, 260), + MX31_PIN_SD2 = IOMUX_PIN(0xff, 261), + MX31_PIN_SD1 = IOMUX_PIN(0xff, 262), + MX31_PIN_SD0 = IOMUX_PIN(0xff, 263), + MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264), + MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265), + MX31_PIN_A25 = IOMUX_PIN(0xff, 266), + MX31_PIN_A24 = IOMUX_PIN(0xff, 267), + MX31_PIN_A23 = IOMUX_PIN(0xff, 268), + MX31_PIN_A22 = IOMUX_PIN(0xff, 269), + MX31_PIN_A21 = IOMUX_PIN(0xff, 270), + MX31_PIN_A20 = IOMUX_PIN(0xff, 271), + MX31_PIN_A19 = IOMUX_PIN(0xff, 272), + MX31_PIN_A18 = IOMUX_PIN(0xff, 273), + MX31_PIN_A17 = IOMUX_PIN(0xff, 274), + MX31_PIN_A16 = IOMUX_PIN(0xff, 275), + MX31_PIN_A14 = IOMUX_PIN(0xff, 276), + MX31_PIN_A15 = IOMUX_PIN(0xff, 277), + MX31_PIN_A13 = IOMUX_PIN(0xff, 278), + MX31_PIN_A12 = IOMUX_PIN(0xff, 279), + MX31_PIN_A11 = IOMUX_PIN(0xff, 280), + MX31_PIN_MA10 = IOMUX_PIN(0xff, 281), + MX31_PIN_A10 = IOMUX_PIN(0xff, 282), + MX31_PIN_A9 = IOMUX_PIN(0xff, 283), + MX31_PIN_A8 = IOMUX_PIN(0xff, 284), + MX31_PIN_A7 = IOMUX_PIN(0xff, 285), + MX31_PIN_A6 = IOMUX_PIN(0xff, 286), + MX31_PIN_A5 = IOMUX_PIN(0xff, 287), + MX31_PIN_A4 = IOMUX_PIN(0xff, 288), + MX31_PIN_A3 = IOMUX_PIN(0xff, 289), + MX31_PIN_A2 = IOMUX_PIN(0xff, 290), + MX31_PIN_A1 = IOMUX_PIN(0xff, 291), + MX31_PIN_A0 = IOMUX_PIN(0xff, 292), + MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293), + MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294), + MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295), + MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296), + MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297), + MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298), + MX31_PIN_CKIL = IOMUX_PIN(0xff, 299), + MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300), + MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301), + MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302), + MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303), + MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304), + MX31_PIN_CLKO = IOMUX_PIN(0xff, 305), + MX31_PIN_POR_B = IOMUX_PIN(0xff, 306), + MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307), + MX31_PIN_CKIH = IOMUX_PIN(0xff, 308), + MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309), + MX31_PIN_SRX0 = IOMUX_PIN(34, 310), + MX31_PIN_STX0 = IOMUX_PIN(33, 311), + MX31_PIN_SVEN0 = IOMUX_PIN(32, 312), + MX31_PIN_SRST0 = IOMUX_PIN(67, 313), + MX31_PIN_SCLK0 = IOMUX_PIN(66, 314), + MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315), + MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316), + MX31_PIN_GPIO1_6 = IOMUX_PIN(6, 317), + MX31_PIN_GPIO1_5 = IOMUX_PIN(5, 318), + MX31_PIN_GPIO1_4 = IOMUX_PIN(4, 319), + MX31_PIN_GPIO1_3 = IOMUX_PIN(3, 320), + MX31_PIN_GPIO1_2 = IOMUX_PIN(2, 321), + MX31_PIN_GPIO1_1 = IOMUX_PIN(1, 322), + MX31_PIN_GPIO1_0 = IOMUX_PIN(0, 323), + MX31_PIN_PWMO = IOMUX_PIN(9, 324), + MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325), + MX31_PIN_COMPARE = IOMUX_PIN(8, 326), + MX31_PIN_CAPTURE = IOMUX_PIN(7, 327), +}; + +/* + * various IOMUX general purpose functions + */ +enum iomux_gp_func { + MUX_PGP_FIRI = 1 << 0, + MUX_DDR_MODE = 1 << 1, + MUX_PGP_CSPI_BB = 1 << 2, + MUX_PGP_ATA_1 = 1 << 3, + MUX_PGP_ATA_2 = 1 << 4, + MUX_PGP_ATA_3 = 1 << 5, + MUX_PGP_ATA_4 = 1 << 6, + MUX_PGP_ATA_5 = 1 << 7, + MUX_PGP_ATA_6 = 1 << 8, + MUX_PGP_ATA_7 = 1 << 9, + MUX_PGP_ATA_8 = 1 << 10, + MUX_PGP_UH2 = 1 << 11, + MUX_SDCTL_CSD0_SEL = 1 << 12, + MUX_SDCTL_CSD1_SEL = 1 << 13, + MUX_CSPI1_UART3 = 1 << 14, + MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, + MUX_TAMPER_DETECT_EN = 1 << 16, + MUX_PGP_USB_4WIRE = 1 << 17, + MUX_PGP_USB_COMMON = 1 << 18, + MUX_SDHC_MEMSTICK1 = 1 << 19, + MUX_SDHC_MEMSTICK2 = 1 << 20, + MUX_PGP_SPLL_BYP = 1 << 21, + MUX_PGP_UPLL_BYP = 1 << 22, + MUX_PGP_MSHC1_CLK_SEL = 1 << 23, + MUX_PGP_MSHC2_CLK_SEL = 1 << 24, + MUX_CSPI3_UART5_SEL = 1 << 25, + MUX_PGP_ATA_9 = 1 << 26, + MUX_PGP_USB_SUSPEND = 1 << 27, + MUX_PGP_USB_OTG_LOOPBACK = 1 << 28, + MUX_PGP_USB_HS1_LOOPBACK = 1 << 29, + MUX_PGP_USB_HS2_LOOPBACK = 1 << 30, + MUX_CLKO_DDR_MODE = 1 << 31, +}; + +/* Bit definitions for RCSR register in CCM */ +#define CCM_RCSR_NF16B (1 << 31) +#define CCM_RCSR_NFMS (1 << 30) + +/* WEIM CS control registers */ +struct mx31_weim_cscr { + u32 upper; + u32 lower; + u32 additional; + u32 reserved; +}; + +struct mx31_weim { + struct mx31_weim_cscr cscr[6]; +}; + +/* ESD control registers */ +struct esdc_regs { + u32 ctl0; + u32 cfg0; + u32 ctl1; + u32 cfg1; + u32 misc; + u32 dly[5]; + u32 dlyl; +}; + +#endif + +#define ARCH_MXC + +#define __REG(x) (*((volatile u32 *)(x))) +#define __REG16(x) (*((volatile u16 *)(x))) +#define __REG8(x) (*((volatile u8 *)(x))) + +#define CCM_BASE 0x53f80000 +#define CCM_CCMR (CCM_BASE + 0x00) +#define CCM_PDR0 (CCM_BASE + 0x04) +#define CCM_PDR1 (CCM_BASE + 0x08) +#define CCM_RCSR (CCM_BASE + 0x0c) +#define CCM_MPCTL (CCM_BASE + 0x10) +#define CCM_UPCTL (CCM_BASE + 0x14) +#define CCM_SPCTL (CCM_BASE + 0x18) +#define CCM_COSR (CCM_BASE + 0x1C) +#define CCM_CGR0 (CCM_BASE + 0x20) +#define CCM_CGR1 (CCM_BASE + 0x24) +#define CCM_CGR2 (CCM_BASE + 0x28) + +#define CCMR_MDS (1 << 7) +#define CCMR_SBYCS (1 << 4) +#define CCMR_MPE (1 << 3) +#define CCMR_PRCS_MASK (3 << 1) +#define CCMR_FPM (1 << 1) +#define CCMR_CKIH (2 << 1) + +#define MX31_IIM_BASE_ADDR 0x5001C000 +#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR + +#define PDR0_CSI_PODF(x) (((x) & 0x3f) << 26) +#define PDR0_CSI_PRDF(x) (((x) & 0x7) << 23) +#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16) +#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11) +#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8) +#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6) +#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3) +#define PDR0_MCU_PODF(x) ((x) & 0x7) + +#define PDR1_USB_PRDF(x) (((x) & 0x3) << 30) +#define PDR1_USB_PODF(x) (((x) & 0x7) << 27) +#define PDR1_FIRI_PRDF(x) (((x) & 0x7) << 24) +#define PDR1_FIRI_PODF(x) (((x) & 0x3f) << 18) +#define PDR1_SSI2_PRDF(x) (((x) & 0x7) << 15) +#define PDR1_SSI2_PODF(x) (((x) & 0x3f) << 9) +#define PDR1_SSI1_PRDF(x) (((x) & 0x7) << 6) +#define PDR1_SSI1_PODF(x) ((x) & 0x3f) + +#define PLL_BRMO(x) (((x) & 0x1) << 31) +#define PLL_PD(x) (((x) & 0xf) << 26) +#define PLL_MFD(x) (((x) & 0x3ff) << 16) +#define PLL_MFI(x) (((x) & 0xf) << 10) +#define PLL_MFN(x) (((x) & 0x3ff) << 0) + +#define GET_PDR0_CSI_PODF(x) (((x) >> 26) & 0x3f) +#define GET_PDR0_CSI_PRDF(x) (((x) >> 23) & 0x7) +#define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f) +#define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7) +#define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7) +#define GET_PDR0_IPG_PODF(x) (((x) >> 6) & 0x3) +#define GET_PDR0_MAX_PODF(x) (((x) >> 3) & 0x7) +#define GET_PDR0_MCU_PODF(x) ((x) & 0x7) + +#define GET_PLL_PD(x) (((x) >> 26) & 0xf) +#define GET_PLL_MFD(x) (((x) >> 16) & 0x3ff) +#define GET_PLL_MFI(x) (((x) >> 10) & 0xf) +#define GET_PLL_MFN(x) (((x) >> 0) & 0x3ff) + + +#define WEIM_ESDCTL0 0xB8001000 +#define WEIM_ESDCFG0 0xB8001004 +#define WEIM_ESDCTL1 0xB8001008 +#define WEIM_ESDCFG1 0xB800100C +#define WEIM_ESDMISC 0xB8001010 + +#define UART1_BASE 0x43F90000 +#define UART2_BASE 0x43F94000 +#define UART3_BASE 0x5000C000 +#define UART4_BASE 0x43FB0000 +#define UART5_BASE 0x43FB4000 + +#define I2C1_BASE_ADDR 0x43f80000 +#define I2C1_CLK_OFFSET 26 +#define I2C2_BASE_ADDR 0x43F98000 +#define I2C2_CLK_OFFSET 28 +#define I2C3_BASE_ADDR 0x43f84000 +#define I2C3_CLK_OFFSET 30 + +#define ESDCTL_SDE (1 << 31) +#define ESDCTL_CMD_RW (0 << 28) +#define ESDCTL_CMD_PRECHARGE (1 << 28) +#define ESDCTL_CMD_AUTOREFRESH (2 << 28) +#define ESDCTL_CMD_LOADMODEREG (3 << 28) +#define ESDCTL_CMD_MANUALREFRESH (4 << 28) +#define ESDCTL_ROW_13 (2 << 24) +#define ESDCTL_ROW(x) ((x) << 24) +#define ESDCTL_COL_9 (1 << 20) +#define ESDCTL_COL(x) ((x) << 20) +#define ESDCTL_DSIZ(x) ((x) << 16) +#define ESDCTL_SREFR(x) ((x) << 13) +#define ESDCTL_PWDT(x) ((x) << 10) +#define ESDCTL_FP(x) ((x) << 8) +#define ESDCTL_BL(x) ((x) << 7) +#define ESDCTL_PRCT(x) ((x) << 0) + +#define ESDCTL_BASE_ADDR 0xB8001000 + +/* 13 fields of the upper CS control register */ +#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ + cnc, wsc, ew, wws, edc) \ + ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\ + (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\ + (wws) << 4 | (edc) << 0) +/* 12 fields of the lower CS control register */ +#define CSCR_L(oea, oen, ebwa, ebwn, \ + csa, ebc, dsz, csn, psr, cre, wrap, csen) \ + ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ + (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ + (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) +/* 14 fields of the additional CS control register */ +#define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ + wwu, age, cnc2, fce) \ + ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ + (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ + (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ + (age) << 2 | (cnc2) << 1 | (fce) << 0) + +#define WEIM_BASE 0xb8002000 + +#define IOMUXC_BASE 0x43FAC000 +#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4) +#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4) + +#define IPU_BASE 0x53fc0000 +#define IPU_CONF IPU_BASE + +#define IPU_CONF_PXL_ENDIAN (1<<8) +#define IPU_CONF_DU_EN (1<<7) +#define IPU_CONF_DI_EN (1<<6) +#define IPU_CONF_ADC_EN (1<<5) +#define IPU_CONF_SDC_EN (1<<4) +#define IPU_CONF_PF_EN (1<<3) +#define IPU_CONF_ROT_EN (1<<2) +#define IPU_CONF_IC_EN (1<<1) +#define IPU_CONF_CSI_EN (1<<0) + +#define ARM_PPMRR 0x40000015 + +#define WDOG1_BASE_ADDR 0x53FDC000 + +/* + * GPIO + */ +#define GPIO1_BASE_ADDR 0x53FCC000 +#define GPIO2_BASE_ADDR 0x53FD0000 +#define GPIO3_BASE_ADDR 0x53FA4000 +#define GPIO_DR 0x00000000 /* data register */ +#define GPIO_GDIR 0x00000004 /* direction register */ +#define GPIO_PSR 0x00000008 /* pad status register */ + +/* + * Signal Multiplexing (IOMUX) + */ + +/* bits in the SW_MUX_CTL registers */ +#define MUX_CTL_OUT_GPIO_DR (0 << 4) +#define MUX_CTL_OUT_FUNC (1 << 4) +#define MUX_CTL_OUT_ALT1 (2 << 4) +#define MUX_CTL_OUT_ALT2 (3 << 4) +#define MUX_CTL_OUT_ALT3 (4 << 4) +#define MUX_CTL_OUT_ALT4 (5 << 4) +#define MUX_CTL_OUT_ALT5 (6 << 4) +#define MUX_CTL_OUT_ALT6 (7 << 4) +#define MUX_CTL_IN_NONE (0 << 0) +#define MUX_CTL_IN_GPIO (1 << 0) +#define MUX_CTL_IN_FUNC (2 << 0) +#define MUX_CTL_IN_ALT1 (4 << 0) +#define MUX_CTL_IN_ALT2 (8 << 0) + +#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC) +#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1) +#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2) +#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO) + +/* Register offsets based on IOMUXC_BASE */ +/* 0x00 .. 0x7b */ +#define MUX_CTL_CSPI3_MISO 0x0c +#define MUX_CTL_CSPI3_SCLK 0x0d +#define MUX_CTL_CSPI3_SPI_RDY 0x0e +#define MUX_CTL_CSPI3_MOSI 0x13 + +#define MUX_CTL_SD1_DATA1 0x18 +#define MUX_CTL_SD1_DATA2 0x19 +#define MUX_CTL_SD1_DATA3 0x1a +#define MUX_CTL_SD1_CMD 0x1d +#define MUX_CTL_SD1_CLK 0x1e +#define MUX_CTL_SD1_DATA0 0x1f + +#define MUX_CTL_USBH2_DATA1 0x40 +#define MUX_CTL_USBH2_DIR 0x44 +#define MUX_CTL_USBH2_STP 0x45 +#define MUX_CTL_USBH2_NXT 0x46 +#define MUX_CTL_USBH2_DATA0 0x47 +#define MUX_CTL_USBH2_CLK 0x4B + +#define MUX_CTL_TXD2 0x70 +#define MUX_CTL_RTS2 0x71 +#define MUX_CTL_CTS2 0x72 +#define MUX_CTL_RXD2 0x77 + +#define MUX_CTL_RTS1 0x7c +#define MUX_CTL_CTS1 0x7d +#define MUX_CTL_DTR_DCE1 0x7e +#define MUX_CTL_DSR_DCE1 0x7f +#define MUX_CTL_CSPI2_SCLK 0x80 +#define MUX_CTL_CSPI2_SPI_RDY 0x81 +#define MUX_CTL_RXD1 0x82 +#define MUX_CTL_TXD1 0x83 +#define MUX_CTL_CSPI2_MISO 0x84 +#define MUX_CTL_CSPI2_SS0 0x85 +#define MUX_CTL_CSPI2_SS1 0x86 +#define MUX_CTL_CSPI2_SS2 0x87 +#define MUX_CTL_CSPI1_SS2 0x88 +#define MUX_CTL_CSPI1_SCLK 0x89 +#define MUX_CTL_CSPI1_SPI_RDY 0x8a +#define MUX_CTL_CSPI2_MOSI 0x8b +#define MUX_CTL_CSPI1_MOSI 0x8c +#define MUX_CTL_CSPI1_MISO 0x8d +#define MUX_CTL_CSPI1_SS0 0x8e +#define MUX_CTL_CSPI1_SS1 0x8f +#define MUX_CTL_STXD6 0x90 +#define MUX_CTL_SRXD6 0x91 +#define MUX_CTL_SCK6 0x92 +#define MUX_CTL_SFS6 0x93 + +#define MUX_CTL_STXD3 0x9C +#define MUX_CTL_SRXD3 0x9D +#define MUX_CTL_SCK3 0x9E +#define MUX_CTL_SFS3 0x9F + +#define MUX_CTL_NFC_WP 0xD0 +#define MUX_CTL_NFC_CE 0xD1 +#define MUX_CTL_NFC_RB 0xD2 +#define MUX_CTL_NFC_WE 0xD4 +#define MUX_CTL_NFC_RE 0xD5 +#define MUX_CTL_NFC_ALE 0xD6 +#define MUX_CTL_NFC_CLE 0xD7 + + +#define MUX_CTL_CAPTURE 0x150 +#define MUX_CTL_COMPARE 0x151 + +/* + * Helper macros for the MUX_[contact name]__[pin function] macros + */ +#define IOMUX_MODE_POS 9 +#define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact)) + +/* + * These macros can be used in mx31_gpio_mux() and have the form + * MUX_[contact name]__[pin function] + */ +#define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC) +#define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC) +#define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC) +#define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC) + +#define MUX_RXD2__UART2_RXD_MUX IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC) +#define MUX_TXD2__UART2_TXD_MUX IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC) +#define MUX_RTS2__UART2_RTS_B IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC) +#define MUX_CTS2__UART2_CTS_B IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC) + +#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC) +#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC) +#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC) +#define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC) +#define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC) +#define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \ + IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC) +#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC) + +#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC) +#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC) +#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC) +#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC) +#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC) +#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \ + IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC) +#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC) + +#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1) +#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1) + +/* PAD control registers for SDR/DDR */ +#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C) +#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270) +#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274) +#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278) +#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C) +#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280) +#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284) +#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288) +#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C) +#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290) +#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294) +#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298) +#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C) +#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0) +#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4) +#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8) +#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC) +#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0) +#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4) +#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8) +#define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC) +#define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0) +#define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4) +#define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8) +#define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC) +#define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0) +#define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4) +#define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8) +#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC) + +/* + * Memory regions and CS + */ +#define IPU_MEM_BASE 0x70000000 +#define CSD0_BASE 0x80000000 +#define CSD1_BASE 0x90000000 +#define CS0_BASE 0xA0000000 +#define CS1_BASE 0xA8000000 +#define CS2_BASE 0xB0000000 +#define CS3_BASE 0xB2000000 +#define CS4_BASE 0xB4000000 +#define CS4_PSRAM_BASE 0xB5000000 +#define CS5_BASE 0xB6000000 +#define PCMCIA_MEM_BASE 0xC0000000 + +/* + * NAND controller + */ +#define NFC_BASE_ADDR 0xB8000000 + +/* SD card controller */ +#define SDHC1_BASE_ADDR 0x50004000 +#define SDHC2_BASE_ADDR 0x50008000 + +/* + * Internal RAM (16KB) + */ +#define IRAM_BASE_ADDR 0x1FFFC000 +#define IRAM_SIZE (16 * 1024) + +#define MX31_AIPS1_BASE_ADDR 0x43f00000 +#define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000) +#define IMX_USB_PORT_OFFSET 0x200 + +/* + * CSPI register definitions + */ +#define MXC_SPI_BASE_ADDRESSES \ + 0x43fa4000, \ + 0x50010000, \ + 0x53f84000, + +/* + * Generic timer support + */ +#ifdef CONFIG_MX31_CLK32 +#define CONFIG_SYS_TIMER_RATE CONFIG_MX31_CLK32 +#else +#define CONFIG_SYS_TIMER_RATE 32768 +#endif + +#endif /* __ASM_ARCH_MX31_IMX_REGS_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx31/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-mx31/sys_proto.h new file mode 100644 index 000000000..29fc0fda0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx31/sys_proto.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 + * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at + */ + +#ifndef _MX31_SYS_PROTO_H_ +#define _MX31_SYS_PROTO_H_ + +#include + +struct mxc_weimcs { + u32 upper; + u32 lower; + u32 additional; +}; + +void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs); +int mxc_mmc_init(struct bd_info *bis); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx35/clock.h b/roms/u-boot/arch/arm/include/asm/arch-mx35/clock.h new file mode 100644 index 000000000..cb0b53a69 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx35/clock.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +#ifdef CONFIG_MX35_HCLK_FREQ +#define MXC_HCLK CONFIG_MX35_HCLK_FREQ +#else +#define MXC_HCLK 24000000 +#endif + +#ifdef CONFIG_MX35_CLK32 +#define MXC_CLK32 CONFIG_MX35_CLK32 +#else +#define MXC_CLK32 32768 +#endif + +enum mxc_clock { + MXC_ARM_CLK, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_IPG_PERCLK, + MXC_UART_CLK, + MXC_ESDHC1_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, + MXC_USB_CLK, + MXC_CSPI_CLK, + MXC_FEC_CLK, + MXC_I2C_CLK, +}; + +enum mxc_main_clock { + CPU_CLK, + AHB_CLK, + IPG_CLK, + IPG_PER_CLK, + NFC_CLK, + USB_CLK, + HSP_CLK, +}; + +enum mxc_peri_clock { + UART1_BAUD, + UART2_BAUD, + UART3_BAUD, + SSI1_BAUD, + SSI2_BAUD, + CSI_BAUD, + MSHC_CLK, + ESDHC1_CLK, + ESDHC2_CLK, + ESDHC3_CLK, + SPDIF_CLK, + SPI1_CLK, + SPI2_CLK, +}; + +u32 imx_get_uartclk(void); +u32 imx_get_fecclk(void); +unsigned int mxc_get_clock(enum mxc_clock clk); + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx35/crm_regs.h b/roms/u-boot/arch/arm/include/asm/arch-mx35/crm_regs.h new file mode 100644 index 000000000..fc65a3ad3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx35/crm_regs.h @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. + */ + +#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__ +#define __CPU_ARM1136_MX35_CRM_REGS_H__ + +/* Register bit definitions */ +#define MXC_CCM_CCMR_WFI (1 << 30) +#define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29) +#define MXC_CCM_CCMR_VSTBY (1 << 28) +#define MXC_CCM_CCMR_WBEN (1 << 27) +#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20 +#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) +#define MXC_CCM_CCMR_ROMW_OFFSET 18 +#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18) +#define MXC_CCM_CCMR_RAMW_OFFSET 16 +#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16) +#define MXC_CCM_CCMR_LPM_OFFSET 14 +#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) +#define MXC_CCM_CCMR_UPE (1 << 9) +#define MXC_CCM_CCMR_MPE (1 << 3) + +#define MXC_CCM_PDR0_PER_SEL (1 << 26) +#define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23) +#define MXC_CCM_PDR0_HSP_PODF_OFFSET 20 +#define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20) +#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16 +#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) +#define MXC_CCM_PDR0_CKIL_SEL (1 << 15) +#define MXC_CCM_PDR0_PER_PODF_OFFSET 12 +#define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12) +#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 +#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9) +#define MXC_CCM_PDR0_AUTO_CON 0x1 + +#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28 +#define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28) +#define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22 +#define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22) +#define MXC_CCM_PDR1_MSHC_M_U (1 << 7) + +#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27 +#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) +#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24 +#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24) +#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16 +#define MXC_CCM_PDR2_CSI_PODF_MASK (0x3F << 16) +#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 +#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) +#define MXC_CCM_PDR2_CSI_M_U (1 << 7) +#define MXC_CCM_PDR2_SSI_M_U (1 << 6) +#define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0 +#define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F) + +#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29 +#define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29) +#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 +#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) +#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) +#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 +#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x3F << 16) +#define MXC_CCM_PDR3_UART_M_U (1 << 14) +#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 +#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x3F << 8) +#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) +#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 +#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x3F) + +#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28 +#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28) +#define MXC_CCM_PDR4_USB_PODF_OFFSET 22 +#define MXC_CCM_PDR4_USB_PODF_MASK (0x3F << 22) +#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16 +#define MXC_CCM_PDR4_PER0_PODF_MASK (0x3F << 16) +#define MXC_CCM_PDR4_UART_PODF_OFFSET 10 +#define MXC_CCM_PDR4_UART_PODF_MASK (0x3F << 10) +#define MXC_CCM_PDR4_USB_M_U (1 << 9) + +/* Bit definitions for RCSR */ +#define MXC_CCM_RCSR_BUS_WIDTH (1 << 29) +#define MXC_CCM_RCSR_BUS_16BIT (1 << 29) +#define MXC_CCM_RCSR_PAGE_SIZE (3 << 27) +#define MXC_CCM_RCSR_PAGE_512 (0 << 27) +#define MXC_CCM_RCSR_PAGE_2K (1 << 27) +#define MXC_CCM_RCSR_PAGE_4K1 (2 << 27) +#define MXC_CCM_RCSR_PAGE_4K2 (3 << 27) +#define MXC_CCM_RCSR_SOFT_RESET (1 << 15) +#define MXC_CCM_RCSR_NF16B (1 << 14) +#define MXC_CCM_RCSR_NFC_4K (1 << 9) +#define MXC_CCM_RCSR_NFC_FMS (1 << 8) + +/* Bit definitions for both MCU, PERIPHERAL PLL control registers */ +#define MXC_CCM_PCTL_BRM 0x80000000 +#define MXC_CCM_PCTL_PD_OFFSET 26 +#define MXC_CCM_PCTL_PD_MASK (0xF << 26) +#define MXC_CCM_PCTL_MFD_OFFSET 16 +#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) +#define MXC_CCM_PCTL_MFI_OFFSET 10 +#define MXC_CCM_PCTL_MFI_MASK (0xF << 10) +#define MXC_CCM_PCTL_MFN_OFFSET 0 +#define MXC_CCM_PCTL_MFN_MASK 0x3FF + +/* Bit definitions for Audio clock mux register*/ +#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12 +#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12) +#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8 +#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8) +#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4 +#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4) +#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0 +#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0) + +/* Bit definitions for Clock gating Register*/ +#define MXC_CCM_CGR_CG_MASK 0x3 +#define MXC_CCM_CGR_CG_OFF 0x0 +#define MXC_CCM_CGR_CG_RUN_ON 0x1 +#define MXC_CCM_CGR_CG_RUN_WAIT_ON 0x2 +#define MXC_CCM_CGR_CG_ON 0x3 + +#define MXC_CCM_CGR0_ASRC_OFFSET 0 +#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0) +#define MXC_CCM_CGR0_ATA_OFFSET 2 +#define MXC_CCM_CGR0_ATA_MASK (0x3 << 2) +#define MXC_CCM_CGR0_CAN1_OFFSET 6 +#define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6) +#define MXC_CCM_CGR0_CAN2_OFFSET 8 +#define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8) +#define MXC_CCM_CGR0_CSPI1_OFFSET 10 +#define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10) +#define MXC_CCM_CGR0_CSPI2_OFFSET 12 +#define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12) +#define MXC_CCM_CGR0_ECT_OFFSET 14 +#define MXC_CCM_CGR0_ECT_MASK (0x3 << 14) +#define MXC_CCM_CGR0_EDIO_OFFSET 16 +#define MXC_CCM_CGR0_EDIO_MASK (0x3 << 16) +#define MXC_CCM_CGR0_EMI_OFFSET 18 +#define MXC_CCM_CGR0_EMI_MASK (0x3 << 18) +#define MXC_CCM_CGR0_EPIT1_OFFSET 20 +#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20) +#define MXC_CCM_CGR0_EPIT2_OFFSET 22 +#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22) +#define MXC_CCM_CGR0_ESAI_OFFSET 24 +#define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24) +#define MXC_CCM_CGR0_ESDHC1_OFFSET 26 +#define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26) +#define MXC_CCM_CGR0_ESDHC2_OFFSET 28 +#define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28) +#define MXC_CCM_CGR0_ESDHC3_OFFSET 30 +#define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30) + +#define MXC_CCM_CGR1_FEC_OFFSET 0 +#define MXC_CCM_CGR1_FEC_MASK (0x3 << 0) +#define MXC_CCM_CGR1_GPIO1_OFFSET 2 +#define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2) +#define MXC_CCM_CGR1_GPIO2_OFFSET 4 +#define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4) +#define MXC_CCM_CGR1_GPIO3_OFFSET 6 +#define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6) +#define MXC_CCM_CGR1_GPT_OFFSET 8 +#define MXC_CCM_CGR1_GPT_MASK (0x3 << 8) +#define MXC_CCM_CGR1_I2C1_OFFSET 10 +#define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10) +#define MXC_CCM_CGR1_I2C2_OFFSET 12 +#define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12) +#define MXC_CCM_CGR1_I2C3_OFFSET 14 +#define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14) +#define MXC_CCM_CGR1_IOMUXC_OFFSET 16 +#define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16) +#define MXC_CCM_CGR1_IPU_OFFSET 18 +#define MXC_CCM_CGR1_IPU_MASK (0x3 << 18) +#define MXC_CCM_CGR1_KPP_OFFSET 20 +#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) +#define MXC_CCM_CGR1_MLB_OFFSET 22 +#define MXC_CCM_CGR1_MLB_MASK (0x3 << 22) +#define MXC_CCM_CGR1_MSHC_OFFSET 24 +#define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24) +#define MXC_CCM_CGR1_OWIRE_OFFSET 26 +#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26) +#define MXC_CCM_CGR1_PWM_OFFSET 28 +#define MXC_CCM_CGR1_PWM_MASK (0x3 << 28) +#define MXC_CCM_CGR1_RNGC_OFFSET 30 +#define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30) + +#define MXC_CCM_CGR2_RTC_OFFSET 0 +#define MXC_CCM_CGR2_RTC_MASK (0x3 << 0) +#define MXC_CCM_CGR2_RTIC_OFFSET 2 +#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2) +#define MXC_CCM_CGR2_SCC_OFFSET 4 +#define MXC_CCM_CGR2_SCC_MASK (0x3 << 4) +#define MXC_CCM_CGR2_SDMA_OFFSET 6 +#define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6) +#define MXC_CCM_CGR2_SPBA_OFFSET 8 +#define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8) +#define MXC_CCM_CGR2_SPDIF_OFFSET 10 +#define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10) +#define MXC_CCM_CGR2_SSI1_OFFSET 12 +#define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12) +#define MXC_CCM_CGR2_SSI2_OFFSET 14 +#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14) +#define MXC_CCM_CGR2_UART1_OFFSET 16 +#define MXC_CCM_CGR2_UART1_MASK (0x3 << 16) +#define MXC_CCM_CGR2_UART2_OFFSET 18 +#define MXC_CCM_CGR2_UART2_MASK (0x3 << 18) +#define MXC_CCM_CGR2_UART3_OFFSET 20 +#define MXC_CCM_CGR2_UART3_MASK (0x3 << 20) +#define MXC_CCM_CGR2_USBOTG_OFFSET 22 +#define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22) +#define MXC_CCM_CGR2_WDOG_OFFSET 24 +#define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24) +#define MXC_CCM_CGR2_MAX_OFFSET 26 +#define MXC_CCM_CGR2_MAX_MASK (0x3 << 26) +#define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26) +#define MXC_CCM_CGR2_AUDMUX_OFFSET 30 +#define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30) + +#define MXC_CCM_CGR3_CSI_OFFSET 0 +#define MXC_CCM_CGR3_CSI_MASK (0x3 << 0) +#define MXC_CCM_CGR3_IIM_OFFSET 2 +#define MXC_CCM_CGR3_IIM_MASK (0x3 << 2) +#define MXC_CCM_CGR3_GPU2D_OFFSET 4 +#define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4) + +#define MXC_CCM_COSR_CLKOSEL_MASK 0x1F +#define MXC_CCM_COSR_CLKOSEL_OFFSET 0 +#define MXC_CCM_COSR_CLKOEN (1 << 5) +#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) +#define MXC_CCM_COSR_CLKOUT_DIV_MASK (0x3F << 10) +#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET 10 +#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) +#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16 +#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18) +#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18 +#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20) +#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20 +#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22) +#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22 +#define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24) +#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26) +#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26 + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx35/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-mx35/gpio.h new file mode 100644 index 000000000..b3d36394a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx35/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, + */ + + +#ifndef __ASM_ARCH_MX35_GPIO_H +#define __ASM_ARCH_MX35_GPIO_H + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx35/imx-regs.h b/roms/u-boot/arch/arm/include/asm/arch-mx35/imx-regs.h new file mode 100644 index 000000000..35090047c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -0,0 +1,356 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (c) 2007 Pengutronix, Sascha Hauer + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + */ + +#ifndef __ASM_ARCH_MX35_H +#define __ASM_ARCH_MX35_H + +#define ARCH_MXC + +/* + * IRAM + */ +#define IRAM_BASE_ADDR 0x10000000 /* internal ram */ +#define IRAM_SIZE 0x00020000 /* 128 KB */ + +#define LOW_LEVEL_SRAM_STACK 0x1001E000 + +/* + * AIPS 1 + */ +#define AIPS1_BASE_ADDR 0x43F00000 +#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR +#define MAX_BASE_ADDR 0x43F04000 +#define EVTMON_BASE_ADDR 0x43F08000 +#define CLKCTL_BASE_ADDR 0x43F0C000 +#define I2C1_BASE_ADDR 0x43F80000 +#define I2C3_BASE_ADDR 0x43F84000 +#define ATA_BASE_ADDR 0x43F8C000 +#define UART1_BASE 0x43F90000 +#define UART2_BASE 0x43F94000 +#define I2C2_BASE_ADDR 0x43F98000 +#define CSPI1_BASE_ADDR 0x43FA4000 +#define IOMUXC_BASE_ADDR 0x43FAC000 + +/* + * SPBA + */ +#define SPBA_BASE_ADDR 0x50000000 +#define UART3_BASE 0x5000C000 +#define CSPI2_BASE_ADDR 0x50010000 +#define ATA_DMA_BASE_ADDR 0x50020000 +#define FEC_BASE_ADDR 0x50038000 +#define SPBA_CTRL_BASE_ADDR 0x5003C000 + +/* + * AIPS 2 + */ +#define AIPS2_BASE_ADDR 0x53F00000 +#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR +#define CCM_BASE_ADDR 0x53F80000 +#define GPT1_BASE_ADDR 0x53F90000 +#define EPIT1_BASE_ADDR 0x53F94000 +#define EPIT2_BASE_ADDR 0x53F98000 +#define GPIO3_BASE_ADDR 0x53FA4000 +#define MMC_SDHC1_BASE_ADDR 0x53FB4000 +#define MMC_SDHC2_BASE_ADDR 0x53FB8000 +#define MMC_SDHC3_BASE_ADDR 0x53FBC000 +#define IPU_CTRL_BASE_ADDR 0x53FC0000 +#define GPIO1_BASE_ADDR 0x53FCC000 +#define GPIO2_BASE_ADDR 0x53FD0000 +#define SDMA_BASE_ADDR 0x53FD4000 +#define RTC_BASE_ADDR 0x53FD8000 +#define WDOG1_BASE_ADDR 0x53FDC000 +#define PWM_BASE_ADDR 0x53FE0000 +#define RTIC_BASE_ADDR 0x53FEC000 +#define IIM_BASE_ADDR 0x53FF0000 +#define IMX_USB_BASE 0x53FF4000 +#define IMX_USB_PORT_OFFSET 0x400 + +#define IMX_CCM_BASE CCM_BASE_ADDR + +/* + * ROMPATCH and AVIC + */ +#define ROMPATCH_BASE_ADDR 0x60000000 +#define AVIC_BASE_ADDR 0x68000000 + +/* + * NAND, SDRAM, WEIM, M3IF, EMI controllers + */ +#define EXT_MEM_CTRL_BASE 0xB8000000 +#define ESDCTL_BASE_ADDR 0xB8001000 +#define WEIM_BASE_ADDR 0xB8002000 +#define WEIM_CTRL_CS0 WEIM_BASE_ADDR +#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10) +#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20) +#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30) +#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40) +#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50) +#define M3IF_BASE_ADDR 0xB8003000 +#define EMI_BASE_ADDR 0xB8004000 + +#define NFC_BASE_ADDR 0xBB000000 + +/* + * Memory regions and CS + */ +#define IPU_MEM_BASE_ADDR 0x70000000 +#define CSD0_BASE_ADDR 0x80000000 +#define CSD1_BASE_ADDR 0x90000000 +#define CS0_BASE_ADDR 0xA0000000 +#define CS1_BASE_ADDR 0xA8000000 +#define CS2_BASE_ADDR 0xB0000000 +#define CS3_BASE_ADDR 0xB2000000 +#define CS4_BASE_ADDR 0xB4000000 +#define CS5_BASE_ADDR 0xB6000000 + +/* + * IRQ Controller Register Definitions. + */ +#define AVIC_NIMASK 0x04 +#define AVIC_INTTYPEH 0x18 +#define AVIC_INTTYPEL 0x1C + +/* L210 */ +#define L2CC_BASE_ADDR 0x30000000 +#define L2_CACHE_LINE_SIZE 32 +#define L2_CACHE_CTL_REG 0x100 +#define L2_CACHE_AUX_CTL_REG 0x104 +#define L2_CACHE_SYNC_REG 0x730 +#define L2_CACHE_INV_LINE_REG 0x770 +#define L2_CACHE_INV_WAY_REG 0x77C +#define L2_CACHE_CLEAN_LINE_REG 0x7B0 +#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0 +#define L2_CACHE_DBG_CTL_REG 0xF40 + +#define CLKMODE_AUTO 0 +#define CLKMODE_CONSUMER 1 + +#define PLL_PD(x) (((x) & 0xf) << 26) +#define PLL_MFD(x) (((x) & 0x3ff) << 16) +#define PLL_MFI(x) (((x) & 0xf) << 10) +#define PLL_MFN(x) (((x) & 0x3ff) << 0) + +#define _PLL_BRM(x) ((x) << 31) +#define _PLL_PD(x) (((x) - 1) << 26) +#define _PLL_MFD(x) (((x) - 1) << 16) +#define _PLL_MFI(x) ((x) << 10) +#define _PLL_MFN(x) (x) +#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ + (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ + _PLL_MFN(mfn)) + +#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) +#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) +#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) + +#define CSCR_U(x) (WEIM_CTRL_CS#x + 0) +#define CSCR_L(x) (WEIM_CTRL_CS#x + 4) +#define CSCR_A(x) (WEIM_CTRL_CS#x + 8) + +#define IIM_SREV 0x24 +#define ROMPATCH_REV 0x40 + +#define IPU_CONF IPU_CTRL_BASE_ADDR + +#define IPU_CONF_PXL_ENDIAN (1<<8) +#define IPU_CONF_DU_EN (1<<7) +#define IPU_CONF_DI_EN (1<<6) +#define IPU_CONF_ADC_EN (1<<5) +#define IPU_CONF_SDC_EN (1<<4) +#define IPU_CONF_PF_EN (1<<3) +#define IPU_CONF_ROT_EN (1<<2) +#define IPU_CONF_IC_EN (1<<1) +#define IPU_CONF_CSI_EN (1<<0) + +/* + * CSPI register definitions + */ +#define MXC_SPI_BASE_ADDRESSES \ + 0x43fa4000, \ + 0x50010000, + +#define GPIO_PORT_NUM 3 +#define GPIO_NUM_PIN 32 + +#define CHIP_REV_1_0 0x10 +#define CHIP_REV_2_0 0x20 + +#define BOARD_REV_1_0 0x0 +#define BOARD_REV_2_0 0x1 + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include + +/* Clock Control Module (CCM) registers */ +struct ccm_regs { + u32 ccmr; /* Control */ + u32 pdr0; /* Post divider 0 */ + u32 pdr1; /* Post divider 1 */ + u32 pdr2; /* Post divider 2 */ + u32 pdr3; /* Post divider 3 */ + u32 pdr4; /* Post divider 4 */ + u32 rcsr; /* CCM Status */ + u32 mpctl; /* Core PLL Control */ + u32 ppctl; /* Peripheral PLL Control */ + u32 acmr; /* Audio clock mux */ + u32 cosr; /* Clock out source */ + u32 cgr0; /* Clock Gating Control 0 */ + u32 cgr1; /* Clock Gating Control 1 */ + u32 cgr2; /* Clock Gating Control 2 */ + u32 cgr3; /* Clock Gating Control 3 */ + u32 reserved; + u32 dcvr0; /* DPTC Comparator 0 */ + u32 dcvr1; /* DPTC Comparator 0 */ + u32 dcvr2; /* DPTC Comparator 0 */ + u32 dcvr3; /* DPTC Comparator 0 */ + u32 ltr0; /* Load Tracking 0 */ + u32 ltr1; /* Load Tracking 1 */ + u32 ltr2; /* Load Tracking 2 */ + u32 ltr3; /* Load Tracking 3 */ + u32 ltbr0; /* Load Tracking Buffer 0 */ +}; + +/* IIM control registers */ +struct iim_regs { + u32 iim_stat; + u32 iim_statm; + u32 iim_err; + u32 iim_emask; + u32 iim_fctl; + u32 iim_ua; + u32 iim_la; + u32 iim_sdat; + u32 iim_prev; + u32 iim_srev; + u32 iim_prg_p; + u32 iim_scs0; + u32 iim_scs1; + u32 iim_scs2; + u32 iim_scs3; + u32 res1[0x1f1]; + struct fuse_bank { + u32 fuse_regs[0x20]; + u32 fuse_rsvd[0xe0]; + } bank[3]; +}; + +struct fuse_bank0_regs { + u32 fuse0_7[8]; + u32 uid[8]; + u32 fuse16_31[0x10]; +}; + +struct fuse_bank1_regs { + u32 fuse0_21[0x16]; + u32 usr; + u32 fuse23_31[9]; +}; + +/* General Purpose Timer (GPT) registers */ +struct gpt_regs { + u32 ctrl; /* control */ + u32 pre; /* prescaler */ + u32 stat; /* status */ + u32 intr; /* interrupt */ + u32 cmp[3]; /* output compare 1-3 */ + u32 capt[2]; /* input capture 1-2 */ + u32 counter; /* counter */ +}; + +struct esdc_regs { + u32 esdctl0; + u32 esdcfg0; + u32 esdctl1; + u32 esdcfg1; + u32 esdmisc; + u32 reserved[4]; + u32 esdcdly[5]; + u32 esdcdlyl; +}; + +#define ESDC_MISC_RST (1 << 1) +#define ESDC_MISC_MDDR_EN (1 << 2) +#define ESDC_MISC_MDDR_DL_RST (1 << 3) +#define ESDC_MISC_DDR_EN (1 << 8) +#define ESDC_MISC_DDR2_EN (1 << 9) + +/* Multi-Layer AHB Crossbar Switch (MAX) registers */ +struct max_regs { + u32 mpr0; + u32 pad00[3]; + u32 sgpcr0; + u32 pad01[59]; + u32 mpr1; + u32 pad02[3]; + u32 sgpcr1; + u32 pad03[59]; + u32 mpr2; + u32 pad04[3]; + u32 sgpcr2; + u32 pad05[59]; + u32 mpr3; + u32 pad06[3]; + u32 sgpcr3; + u32 pad07[59]; + u32 mpr4; + u32 pad08[3]; + u32 sgpcr4; + u32 pad09[251]; + u32 mgpcr0; + u32 pad10[63]; + u32 mgpcr1; + u32 pad11[63]; + u32 mgpcr2; + u32 pad12[63]; + u32 mgpcr3; + u32 pad13[63]; + u32 mgpcr4; + u32 pad14[63]; + u32 mgpcr5; +}; + +/* AHB <-> IP-Bus Interface (AIPS) */ +struct aips_regs { + u32 mpr_0_7; + u32 mpr_8_15; + u32 pad0[6]; + u32 pacr_0_7; + u32 pacr_8_15; + u32 pacr_16_23; + u32 pacr_24_31; + u32 pad1[4]; + u32 opacr_0_7; + u32 opacr_8_15; + u32 opacr_16_23; + u32 opacr_24_31; + u32 opacr_32_39; +}; + +/* + * NFMS bit in RCSR register for pagesize of nandflash + */ +#define NFMS_BIT 8 +#define NFMS_NF_DWIDTH 14 +#define NFMS_NF_PG_SZ 8 + +#define CCM_RCSR_NF_16BIT_SEL (1 << 14) + +#endif + +/* + * Generic timer support + */ +#ifdef CONFIG_MX35_CLK32 +#define CONFIG_SYS_TIMER_RATE CONFIG_MX35_CLK32 +#else +#define CONFIG_SYS_TIMER_RATE 32768 +#endif + +#define CONFIG_SYS_TIMER_COUNTER (GPT1_BASE_ADDR+36) + +#endif /* __ASM_ARCH_MX35_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx35/iomux-mx35.h b/roms/u-boot/arch/arm/include/asm/arch-mx35/iomux-mx35.h new file mode 100644 index 000000000..f519c69fd --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx35/iomux-mx35.h @@ -0,0 +1,1259 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 ADVANSEE + * Benoît Thébaudeau + * + * Based on mainline Linux i.MX iomux-mx35.h file: + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH + */ + +#ifndef __IOMUX_MX35_H__ +#define __IOMUX_MX35_H__ + +#include + +/* + * The naming convention for the pad modes is MX35_PAD___ + * If or refers to a GPIO, it is named GPIO_ + * See also iomux-v3.h + */ + +/* PAD MUX ALT INPSE PATH PADCTRL */ +enum { + MX35_PAD_CAPTURE__GPT_CAPIN1 = IOMUX_PAD(0x328, 0x004, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CAPTURE__GPT_CMPOUT2 = IOMUX_PAD(0x328, 0x004, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CAPTURE__CSPI2_SS1 = IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL), + MX35_PAD_CAPTURE__EPIT1_EPITO = IOMUX_PAD(0x328, 0x004, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CAPTURE__CCM_CLK32K = IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL), + MX35_PAD_CAPTURE__GPIO1_4 = IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL), + + MX35_PAD_COMPARE__GPT_CMPOUT1 = IOMUX_PAD(0x32c, 0x008, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_COMPARE__GPT_CAPIN2 = IOMUX_PAD(0x32c, 0x008, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_COMPARE__GPT_CMPOUT3 = IOMUX_PAD(0x32c, 0x008, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_COMPARE__EPIT2_EPITO = IOMUX_PAD(0x32c, 0x008, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_COMPARE__GPIO1_5 = IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL), + MX35_PAD_COMPARE__SDMA_EXTDMA_2 = IOMUX_PAD(0x32c, 0x008, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_WDOG_RST__WDOG_WDOG_B = IOMUX_PAD(0x330, 0x00c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_WDOG_RST__IPU_FLASH_STROBE = IOMUX_PAD(0x330, 0x00c, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_WDOG_RST__GPIO1_6 = IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL), + + MX35_PAD_GPIO1_0__GPIO1_0 = IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL), + MX35_PAD_GPIO1_0__CCM_PMIC_RDY = IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL), + MX35_PAD_GPIO1_0__OWIRE_LINE = IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL), + MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 = IOMUX_PAD(0x334, 0x010, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_GPIO1_1__GPIO1_1 = IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL), + MX35_PAD_GPIO1_1__PWM_PWMO = IOMUX_PAD(0x338, 0x014, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_GPIO1_1__CSPI1_SS2 = IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL), + MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT = IOMUX_PAD(0x338, 0x014, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 = IOMUX_PAD(0x338, 0x014, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_GPIO2_0__GPIO2_0 = IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL), + MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK = IOMUX_PAD(0x33c, 0x018, 1, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_GPIO3_0__GPIO3_0 = IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL), + MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK = IOMUX_PAD(0x340, 0x01c, 1, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_RESET_IN_B__CCM_RESET_IN_B = IOMUX_PAD(0x344, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_POR_B__CCM_POR_B = IOMUX_PAD(0x348, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CLKO__CCM_CLKO = IOMUX_PAD(0x34c, 0x020, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CLKO__GPIO1_8 = IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL), + + MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 = IOMUX_PAD(0x350, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 = IOMUX_PAD(0x354, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 = IOMUX_PAD(0x358, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 = IOMUX_PAD(0x35c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 = IOMUX_PAD(0x360, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_VSTBY__CCM_VSTBY = IOMUX_PAD(0x364, 0x024, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_VSTBY__GPIO1_7 = IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL), + + MX35_PAD_A0__EMI_EIM_DA_L_0 = IOMUX_PAD(0x368, 0x028, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A1__EMI_EIM_DA_L_1 = IOMUX_PAD(0x36c, 0x02c, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A2__EMI_EIM_DA_L_2 = IOMUX_PAD(0x370, 0x030, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A3__EMI_EIM_DA_L_3 = IOMUX_PAD(0x374, 0x034, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A4__EMI_EIM_DA_L_4 = IOMUX_PAD(0x378, 0x038, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A5__EMI_EIM_DA_L_5 = IOMUX_PAD(0x37c, 0x03c, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A6__EMI_EIM_DA_L_6 = IOMUX_PAD(0x380, 0x040, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A7__EMI_EIM_DA_L_7 = IOMUX_PAD(0x384, 0x044, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A8__EMI_EIM_DA_H_8 = IOMUX_PAD(0x388, 0x048, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A9__EMI_EIM_DA_H_9 = IOMUX_PAD(0x38c, 0x04c, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A10__EMI_EIM_DA_H_10 = IOMUX_PAD(0x390, 0x050, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_MA10__EMI_MA10 = IOMUX_PAD(0x394, 0x054, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A11__EMI_EIM_DA_H_11 = IOMUX_PAD(0x398, 0x058, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A12__EMI_EIM_DA_H_12 = IOMUX_PAD(0x39c, 0x05c, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A13__EMI_EIM_DA_H_13 = IOMUX_PAD(0x3a0, 0x060, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A14__EMI_EIM_DA_H2_14 = IOMUX_PAD(0x3a4, 0x064, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A15__EMI_EIM_DA_H2_15 = IOMUX_PAD(0x3a8, 0x068, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A16__EMI_EIM_A_16 = IOMUX_PAD(0x3ac, 0x06c, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A17__EMI_EIM_A_17 = IOMUX_PAD(0x3b0, 0x070, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A18__EMI_EIM_A_18 = IOMUX_PAD(0x3b4, 0x074, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A19__EMI_EIM_A_19 = IOMUX_PAD(0x3b8, 0x078, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A20__EMI_EIM_A_20 = IOMUX_PAD(0x3bc, 0x07c, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A21__EMI_EIM_A_21 = IOMUX_PAD(0x3c0, 0x080, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A22__EMI_EIM_A_22 = IOMUX_PAD(0x3c4, 0x084, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A23__EMI_EIM_A_23 = IOMUX_PAD(0x3c8, 0x088, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A24__EMI_EIM_A_24 = IOMUX_PAD(0x3cc, 0x08c, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_A25__EMI_EIM_A_25 = IOMUX_PAD(0x3d0, 0x090, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SDBA1__EMI_EIM_SDBA1 = IOMUX_PAD(0x3d4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SDBA0__EMI_EIM_SDBA0 = IOMUX_PAD(0x3d8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD0__EMI_DRAM_D_0 = IOMUX_PAD(0x3dc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD1__EMI_DRAM_D_1 = IOMUX_PAD(0x3e0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD2__EMI_DRAM_D_2 = IOMUX_PAD(0x3e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD3__EMI_DRAM_D_3 = IOMUX_PAD(0x3e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD4__EMI_DRAM_D_4 = IOMUX_PAD(0x3ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD5__EMI_DRAM_D_5 = IOMUX_PAD(0x3f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD6__EMI_DRAM_D_6 = IOMUX_PAD(0x3f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD7__EMI_DRAM_D_7 = IOMUX_PAD(0x3f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD8__EMI_DRAM_D_8 = IOMUX_PAD(0x3fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD9__EMI_DRAM_D_9 = IOMUX_PAD(0x400, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD10__EMI_DRAM_D_10 = IOMUX_PAD(0x404, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD11__EMI_DRAM_D_11 = IOMUX_PAD(0x408, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD12__EMI_DRAM_D_12 = IOMUX_PAD(0x40c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD13__EMI_DRAM_D_13 = IOMUX_PAD(0x410, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD14__EMI_DRAM_D_14 = IOMUX_PAD(0x414, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD15__EMI_DRAM_D_15 = IOMUX_PAD(0x418, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD16__EMI_DRAM_D_16 = IOMUX_PAD(0x41c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD17__EMI_DRAM_D_17 = IOMUX_PAD(0x420, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD18__EMI_DRAM_D_18 = IOMUX_PAD(0x424, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD19__EMI_DRAM_D_19 = IOMUX_PAD(0x428, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD20__EMI_DRAM_D_20 = IOMUX_PAD(0x42c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD21__EMI_DRAM_D_21 = IOMUX_PAD(0x430, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD22__EMI_DRAM_D_22 = IOMUX_PAD(0x434, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD23__EMI_DRAM_D_23 = IOMUX_PAD(0x438, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD24__EMI_DRAM_D_24 = IOMUX_PAD(0x43c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD25__EMI_DRAM_D_25 = IOMUX_PAD(0x440, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD26__EMI_DRAM_D_26 = IOMUX_PAD(0x444, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD27__EMI_DRAM_D_27 = IOMUX_PAD(0x448, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD28__EMI_DRAM_D_28 = IOMUX_PAD(0x44c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD29__EMI_DRAM_D_29 = IOMUX_PAD(0x450, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD30__EMI_DRAM_D_30 = IOMUX_PAD(0x454, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD31__EMI_DRAM_D_31 = IOMUX_PAD(0x458, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_DQM0__EMI_DRAM_DQM_0 = IOMUX_PAD(0x45c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_DQM1__EMI_DRAM_DQM_1 = IOMUX_PAD(0x460, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_DQM2__EMI_DRAM_DQM_2 = IOMUX_PAD(0x464, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_DQM3__EMI_DRAM_DQM_3 = IOMUX_PAD(0x468, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_EB0__EMI_EIM_EB0_B = IOMUX_PAD(0x46c, 0x094, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_EB1__EMI_EIM_EB1_B = IOMUX_PAD(0x470, 0x098, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_OE__EMI_EIM_OE = IOMUX_PAD(0x474, 0x09c, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CS0__EMI_EIM_CS0 = IOMUX_PAD(0x478, 0x0a0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CS1__EMI_EIM_CS1 = IOMUX_PAD(0x47c, 0x0a4, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CS1__EMI_NANDF_CE3 = IOMUX_PAD(0x47c, 0x0a4, 3, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CS2__EMI_EIM_CS2 = IOMUX_PAD(0x480, 0x0a8, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CS3__EMI_EIM_CS3 = IOMUX_PAD(0x484, 0x0ac, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CS4__EMI_EIM_CS4 = IOMUX_PAD(0x488, 0x0b0, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CS4__EMI_DTACK_B = IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL), + MX35_PAD_CS4__EMI_NANDF_CE1 = IOMUX_PAD(0x488, 0x0b0, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CS4__GPIO1_20 = IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL), + + MX35_PAD_CS5__EMI_EIM_CS5 = IOMUX_PAD(0x48c, 0x0b4, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CS5__CSPI2_SS2 = IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL), + MX35_PAD_CS5__CSPI1_SS2 = IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL), + MX35_PAD_CS5__EMI_NANDF_CE2 = IOMUX_PAD(0x48c, 0x0b4, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CS5__GPIO1_21 = IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL), + + MX35_PAD_NF_CE0__EMI_NANDF_CE0 = IOMUX_PAD(0x490, 0x0b8, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_NF_CE0__GPIO1_22 = IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL), + + MX35_PAD_ECB__EMI_EIM_ECB = IOMUX_PAD(0x494, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LBA__EMI_EIM_LBA = IOMUX_PAD(0x498, 0x0bc, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_BCLK__EMI_EIM_BCLK = IOMUX_PAD(0x49c, 0x0c0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_RW__EMI_EIM_RW = IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_RAS__EMI_DRAM_RAS = IOMUX_PAD(0x4a4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CAS__EMI_DRAM_CAS = IOMUX_PAD(0x4a8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SDWE__EMI_DRAM_SDWE = IOMUX_PAD(0x4ac, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 = IOMUX_PAD(0x4b0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 = IOMUX_PAD(0x4b4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SDCLK__EMI_DRAM_SDCLK = IOMUX_PAD(0x4b8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 = IOMUX_PAD(0x4bc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 = IOMUX_PAD(0x4c0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 = IOMUX_PAD(0x4c4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 = IOMUX_PAD(0x4c8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_NFWE_B__EMI_NANDF_WE_B = IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 = IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL), + MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL), + MX35_PAD_NFWE_B__GPIO2_18 = IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL), + MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 = IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_NFRE_B__EMI_NANDF_RE_B = IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR = IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL), + MX35_PAD_NFRE_B__IPU_DISPB_BCLK = IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_NFRE_B__GPIO2_19 = IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL), + MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 = IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_NFALE__EMI_NANDF_ALE = IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_NFALE__USB_TOP_USBH2_STP = IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_NFALE__IPU_DISPB_CS0 = IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_NFALE__GPIO2_20 = IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL), + MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 = IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_NFCLE__EMI_NANDF_CLE = IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_NFCLE__USB_TOP_USBH2_NXT = IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL), + MX35_PAD_NFCLE__IPU_DISPB_PAR_RS = IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_NFCLE__GPIO2_21 = IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL), + MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 = IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_NFWP_B__EMI_NANDF_WP_B = IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 = IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL), + MX35_PAD_NFWP_B__IPU_DISPB_WR = IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_NFWP_B__GPIO2_22 = IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL), + MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL = IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_NFRB__EMI_NANDF_RB = IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_NFRB__IPU_DISPB_RD = IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_NFRB__GPIO2_23 = IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL), + MX35_PAD_NFRB__ARM11P_TOP_TRCLK = IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D15__EMI_EIM_D_15 = IOMUX_PAD(0x4e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D14__EMI_EIM_D_14 = IOMUX_PAD(0x4e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D13__EMI_EIM_D_13 = IOMUX_PAD(0x4ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D12__EMI_EIM_D_12 = IOMUX_PAD(0x4f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D11__EMI_EIM_D_11 = IOMUX_PAD(0x4f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D10__EMI_EIM_D_10 = IOMUX_PAD(0x4f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D9__EMI_EIM_D_9 = IOMUX_PAD(0x4fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D8__EMI_EIM_D_8 = IOMUX_PAD(0x500, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D7__EMI_EIM_D_7 = IOMUX_PAD(0x504, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D6__EMI_EIM_D_6 = IOMUX_PAD(0x508, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D5__EMI_EIM_D_5 = IOMUX_PAD(0x50c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D4__EMI_EIM_D_4 = IOMUX_PAD(0x510, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D3__EMI_EIM_D_3 = IOMUX_PAD(0x514, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D2__EMI_EIM_D_2 = IOMUX_PAD(0x518, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D1__EMI_EIM_D_1 = IOMUX_PAD(0x51c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D0__EMI_EIM_D_0 = IOMUX_PAD(0x520, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CSI_D8__IPU_CSI_D_8 = IOMUX_PAD(0x524, 0x0e0, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSI_D8__KPP_COL_0 = IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL), + MX35_PAD_CSI_D8__GPIO1_20 = IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL), + MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 = IOMUX_PAD(0x524, 0x0e0, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CSI_D9__IPU_CSI_D_9 = IOMUX_PAD(0x528, 0x0e4, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSI_D9__KPP_COL_1 = IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL), + MX35_PAD_CSI_D9__GPIO1_21 = IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL), + MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 = IOMUX_PAD(0x528, 0x0e4, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CSI_D10__IPU_CSI_D_10 = IOMUX_PAD(0x52c, 0x0e8, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSI_D10__KPP_COL_2 = IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL), + MX35_PAD_CSI_D10__GPIO1_22 = IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL), + MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 = IOMUX_PAD(0x52c, 0x0e8, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CSI_D11__IPU_CSI_D_11 = IOMUX_PAD(0x530, 0x0ec, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSI_D11__KPP_COL_3 = IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL), + MX35_PAD_CSI_D11__GPIO1_23 = IOMUX_PAD(0x530, 0x0ec, 5, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CSI_D12__IPU_CSI_D_12 = IOMUX_PAD(0x534, 0x0f0, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSI_D12__KPP_ROW_0 = IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL), + MX35_PAD_CSI_D12__GPIO1_24 = IOMUX_PAD(0x534, 0x0f0, 5, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CSI_D13__IPU_CSI_D_13 = IOMUX_PAD(0x538, 0x0f4, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSI_D13__KPP_ROW_1 = IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL), + MX35_PAD_CSI_D13__GPIO1_25 = IOMUX_PAD(0x538, 0x0f4, 5, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CSI_D14__IPU_CSI_D_14 = IOMUX_PAD(0x53c, 0x0f8, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSI_D14__KPP_ROW_2 = IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL), + MX35_PAD_CSI_D14__GPIO1_26 = IOMUX_PAD(0x53c, 0x0f8, 5, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CSI_D15__IPU_CSI_D_15 = IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL), + MX35_PAD_CSI_D15__KPP_ROW_3 = IOMUX_PAD(0x540, 0x0fc, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSI_D15__GPIO1_27 = IOMUX_PAD(0x540, 0x0fc, 5, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CSI_MCLK__IPU_CSI_MCLK = IOMUX_PAD(0x544, 0x100, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSI_MCLK__GPIO1_28 = IOMUX_PAD(0x544, 0x100, 5, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC = IOMUX_PAD(0x548, 0x104, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSI_VSYNC__GPIO1_29 = IOMUX_PAD(0x548, 0x104, 5, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC = IOMUX_PAD(0x54c, 0x108, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSI_HSYNC__GPIO1_30 = IOMUX_PAD(0x54c, 0x108, 5, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK = IOMUX_PAD(0x550, 0x10c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSI_PIXCLK__GPIO1_31 = IOMUX_PAD(0x550, 0x10c, 5, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_I2C1_CLK__I2C1_SCL = IOMUX_PAD(0x554, 0x110, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_I2C1_CLK__GPIO2_24 = IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL), + MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK = IOMUX_PAD(0x554, 0x110, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_I2C1_DAT__I2C1_SDA = IOMUX_PAD(0x558, 0x114, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_I2C1_DAT__GPIO2_25 = IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL), + + MX35_PAD_I2C2_CLK__I2C2_SCL = IOMUX_PAD(0x55c, 0x118, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_I2C2_CLK__CAN1_TXCAN = IOMUX_PAD(0x55c, 0x118, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR = IOMUX_PAD(0x55c, 0x118, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_I2C2_CLK__GPIO2_26 = IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL), + MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x55c, 0x118, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_I2C2_DAT__I2C2_SDA = IOMUX_PAD(0x560, 0x11c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_I2C2_DAT__CAN1_RXCAN = IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL), + MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC = IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL), + MX35_PAD_I2C2_DAT__GPIO2_27 = IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL), + MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x560, 0x11c, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_STXD4__AUDMUX_AUD4_TXD = IOMUX_PAD(0x564, 0x120, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_STXD4__GPIO2_28 = IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL), + MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 = IOMUX_PAD(0x564, 0x120, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SRXD4__AUDMUX_AUD4_RXD = IOMUX_PAD(0x568, 0x124, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SRXD4__GPIO2_29 = IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL), + MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 = IOMUX_PAD(0x568, 0x124, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SCK4__AUDMUX_AUD4_TXC = IOMUX_PAD(0x56c, 0x128, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SCK4__GPIO2_30 = IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL), + MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 = IOMUX_PAD(0x56c, 0x128, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x570, 0x12c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_STXFS4__GPIO2_31 = IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL), + MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 = IOMUX_PAD(0x570, 0x12c, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_STXD5__AUDMUX_AUD5_TXD = IOMUX_PAD(0x574, 0x130, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x574, 0x130, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_STXD5__CSPI2_MOSI = IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL), + MX35_PAD_STXD5__GPIO1_0 = IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL), + MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 = IOMUX_PAD(0x574, 0x130, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SRXD5__AUDMUX_AUD5_RXD = IOMUX_PAD(0x578, 0x134, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL), + MX35_PAD_SRXD5__CSPI2_MISO = IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL), + MX35_PAD_SRXD5__GPIO1_1 = IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL), + MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 = IOMUX_PAD(0x578, 0x134, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SCK5__AUDMUX_AUD5_TXC = IOMUX_PAD(0x57c, 0x138, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL), + MX35_PAD_SCK5__CSPI2_SCLK = IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL), + MX35_PAD_SCK5__GPIO1_2 = IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL), + MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 = IOMUX_PAD(0x57c, 0x138, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x580, 0x13c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_STXFS5__CSPI2_RDY = IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL), + MX35_PAD_STXFS5__GPIO1_3 = IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL), + MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 = IOMUX_PAD(0x580, 0x13c, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SCKR__ESAI_SCKR = IOMUX_PAD(0x584, 0x140, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SCKR__GPIO1_4 = IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL), + MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 = IOMUX_PAD(0x584, 0x140, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_FSR__ESAI_FSR = IOMUX_PAD(0x588, 0x144, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FSR__GPIO1_5 = IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL), + MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 = IOMUX_PAD(0x588, 0x144, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_HCKR__ESAI_HCKR = IOMUX_PAD(0x58c, 0x148, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_HCKR__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x58c, 0x148, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_HCKR__CSPI2_SS0 = IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL), + MX35_PAD_HCKR__IPU_FLASH_STROBE = IOMUX_PAD(0x58c, 0x148, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_HCKR__GPIO1_6 = IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL), + MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 = IOMUX_PAD(0x58c, 0x148, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SCKT__ESAI_SCKT = IOMUX_PAD(0x590, 0x14c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SCKT__GPIO1_7 = IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL), + MX35_PAD_SCKT__IPU_CSI_D_0 = IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL), + MX35_PAD_SCKT__KPP_ROW_2 = IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL), + + MX35_PAD_FST__ESAI_FST = IOMUX_PAD(0x594, 0x150, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FST__GPIO1_8 = IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL), + MX35_PAD_FST__IPU_CSI_D_1 = IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL), + MX35_PAD_FST__KPP_ROW_3 = IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL), + + MX35_PAD_HCKT__ESAI_HCKT = IOMUX_PAD(0x598, 0x154, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_HCKT__AUDMUX_AUD5_RXC = IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL), + MX35_PAD_HCKT__GPIO1_9 = IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL), + MX35_PAD_HCKT__IPU_CSI_D_2 = IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL), + MX35_PAD_HCKT__KPP_COL_3 = IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL), + + MX35_PAD_TX5_RX0__ESAI_TX5_RX0 = IOMUX_PAD(0x59c, 0x158, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC = IOMUX_PAD(0x59c, 0x158, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX5_RX0__CSPI2_SS2 = IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL), + MX35_PAD_TX5_RX0__CAN2_TXCAN = IOMUX_PAD(0x59c, 0x158, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX5_RX0__UART2_DTR = IOMUX_PAD(0x59c, 0x158, 4, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX5_RX0__GPIO1_10 = IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL), + MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 = IOMUX_PAD(0x59c, 0x158, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_TX4_RX1__ESAI_TX4_RX1 = IOMUX_PAD(0x5a0, 0x15c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x5a0, 0x15c, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX4_RX1__CSPI2_SS3 = IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL), + MX35_PAD_TX4_RX1__CAN2_RXCAN = IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL), + MX35_PAD_TX4_RX1__UART2_DSR = IOMUX_PAD(0x5a0, 0x15c, 4, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX4_RX1__GPIO1_11 = IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL), + MX35_PAD_TX4_RX1__IPU_CSI_D_3 = IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL), + MX35_PAD_TX4_RX1__KPP_ROW_0 = IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL), + + MX35_PAD_TX3_RX2__ESAI_TX3_RX2 = IOMUX_PAD(0x5a4, 0x160, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX3_RX2__I2C3_SCL = IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL), + MX35_PAD_TX3_RX2__EMI_NANDF_CE1 = IOMUX_PAD(0x5a4, 0x160, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX3_RX2__GPIO1_12 = IOMUX_PAD(0x5a4, 0x160, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX3_RX2__IPU_CSI_D_4 = IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL), + MX35_PAD_TX3_RX2__KPP_ROW_1 = IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL), + + MX35_PAD_TX2_RX3__ESAI_TX2_RX3 = IOMUX_PAD(0x5a8, 0x164, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX2_RX3__I2C3_SDA = IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL), + MX35_PAD_TX2_RX3__EMI_NANDF_CE2 = IOMUX_PAD(0x5a8, 0x164, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX2_RX3__GPIO1_13 = IOMUX_PAD(0x5a8, 0x164, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX2_RX3__IPU_CSI_D_5 = IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL), + MX35_PAD_TX2_RX3__KPP_COL_0 = IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL), + + MX35_PAD_TX1__ESAI_TX1 = IOMUX_PAD(0x5ac, 0x168, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX1__CCM_PMIC_RDY = IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL), + MX35_PAD_TX1__CSPI1_SS2 = IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL), + MX35_PAD_TX1__EMI_NANDF_CE3 = IOMUX_PAD(0x5ac, 0x168, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX1__UART2_RI = IOMUX_PAD(0x5ac, 0x168, 4, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX1__GPIO1_14 = IOMUX_PAD(0x5ac, 0x168, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX1__IPU_CSI_D_6 = IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL), + MX35_PAD_TX1__KPP_COL_1 = IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL), + + MX35_PAD_TX0__ESAI_TX0 = IOMUX_PAD(0x5b0, 0x16c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL), + MX35_PAD_TX0__CSPI1_SS3 = IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL), + MX35_PAD_TX0__EMI_DTACK_B = IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL), + MX35_PAD_TX0__UART2_DCD = IOMUX_PAD(0x5b0, 0x16c, 4, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX0__GPIO1_15 = IOMUX_PAD(0x5b0, 0x16c, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TX0__IPU_CSI_D_7 = IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL), + MX35_PAD_TX0__KPP_COL_2 = IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL), + + MX35_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x5b4, 0x170, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSPI1_MOSI__GPIO1_16 = IOMUX_PAD(0x5b4, 0x170, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 = IOMUX_PAD(0x5b4, 0x170, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x5b8, 0x174, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSPI1_MISO__GPIO1_17 = IOMUX_PAD(0x5b8, 0x174, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 = IOMUX_PAD(0x5b8, 0x174, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x5bc, 0x178, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSPI1_SS0__OWIRE_LINE = IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL), + MX35_PAD_CSPI1_SS0__CSPI2_SS3 = IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL), + MX35_PAD_CSPI1_SS0__GPIO1_18 = IOMUX_PAD(0x5bc, 0x178, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 = IOMUX_PAD(0x5bc, 0x178, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x5c0, 0x17c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSPI1_SS1__PWM_PWMO = IOMUX_PAD(0x5c0, 0x17c, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSPI1_SS1__CCM_CLK32K = IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL), + MX35_PAD_CSPI1_SS1__GPIO1_19 = IOMUX_PAD(0x5c0, 0x17c, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 = IOMUX_PAD(0x5c0, 0x17c, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 = IOMUX_PAD(0x5c0, 0x17c, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x5c4, 0x180, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSPI1_SCLK__GPIO3_4 = IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL), + MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 = IOMUX_PAD(0x5c4, 0x180, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 = IOMUX_PAD(0x5c4, 0x180, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY = IOMUX_PAD(0x5c8, 0x184, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 = IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL), + MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 = IOMUX_PAD(0x5c8, 0x184, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 = IOMUX_PAD(0x5c8, 0x184, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_RXD1__UART1_RXD_MUX = IOMUX_PAD(0x5cc, 0x188, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_RXD1__CSPI2_MOSI = IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL), + MX35_PAD_RXD1__KPP_COL_4 = IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL), + MX35_PAD_RXD1__GPIO3_6 = IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL), + MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 = IOMUX_PAD(0x5cc, 0x188, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_TXD1__UART1_TXD_MUX = IOMUX_PAD(0x5d0, 0x18c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TXD1__CSPI2_MISO = IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL), + MX35_PAD_TXD1__KPP_COL_5 = IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL), + MX35_PAD_TXD1__GPIO3_7 = IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL), + MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 = IOMUX_PAD(0x5d0, 0x18c, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_RTS1__UART1_RTS = IOMUX_PAD(0x5d4, 0x190, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_RTS1__CSPI2_SCLK = IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL), + MX35_PAD_RTS1__I2C3_SCL = IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL), + MX35_PAD_RTS1__IPU_CSI_D_0 = IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL), + MX35_PAD_RTS1__KPP_COL_6 = IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL), + MX35_PAD_RTS1__GPIO3_8 = IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL), + MX35_PAD_RTS1__EMI_NANDF_CE1 = IOMUX_PAD(0x5d4, 0x190, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 = IOMUX_PAD(0x5d4, 0x190, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CTS1__UART1_CTS = IOMUX_PAD(0x5d8, 0x194, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CTS1__CSPI2_RDY = IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL), + MX35_PAD_CTS1__I2C3_SDA = IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL), + MX35_PAD_CTS1__IPU_CSI_D_1 = IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL), + MX35_PAD_CTS1__KPP_COL_7 = IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL), + MX35_PAD_CTS1__GPIO3_9 = IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL), + MX35_PAD_CTS1__EMI_NANDF_CE2 = IOMUX_PAD(0x5d8, 0x194, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 = IOMUX_PAD(0x5d8, 0x194, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_RXD2__UART2_RXD_MUX = IOMUX_PAD(0x5dc, 0x198, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_RXD2__KPP_ROW_4 = IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL), + MX35_PAD_RXD2__GPIO3_10 = IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL), + + MX35_PAD_TXD2__UART2_TXD_MUX = IOMUX_PAD(0x5e0, 0x19c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL), + MX35_PAD_TXD2__KPP_ROW_5 = IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL), + MX35_PAD_TXD2__GPIO3_11 = IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL), + + MX35_PAD_RTS2__UART2_RTS = IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_RTS2__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL), + MX35_PAD_RTS2__CAN2_RXCAN = IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL), + MX35_PAD_RTS2__IPU_CSI_D_2 = IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL), + MX35_PAD_RTS2__KPP_ROW_6 = IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL), + MX35_PAD_RTS2__GPIO3_12 = IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL), + MX35_PAD_RTS2__AUDMUX_AUD5_RXC = IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_RTS2__UART3_RXD_MUX = IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL), + + MX35_PAD_CTS2__UART2_CTS = IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CTS2__CAN2_TXCAN = IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CTS2__IPU_CSI_D_3 = IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL), + MX35_PAD_CTS2__KPP_ROW_7 = IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL), + MX35_PAD_CTS2__GPIO3_13 = IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL), + MX35_PAD_CTS2__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CTS2__UART3_TXD_MUX = IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_RTCK__ARM11P_TOP_RTCK = IOMUX_PAD(0x5ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_TCK__SJC_TCK = IOMUX_PAD(0x5f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_TMS__SJC_TMS = IOMUX_PAD(0x5f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_TDI__SJC_TDI = IOMUX_PAD(0x5f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_TDO__SJC_TDO = IOMUX_PAD(0x5fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_TRSTB__SJC_TRSTB = IOMUX_PAD(0x600, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_DE_B__SJC_DE_B = IOMUX_PAD(0x604, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SJC_MOD__SJC_MOD = IOMUX_PAD(0x608, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR = IOMUX_PAD(0x60c, 0x1a8, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR = IOMUX_PAD(0x60c, 0x1a8, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_USBOTG_PWR__GPIO3_14 = IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL), + + MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC = IOMUX_PAD(0x610, 0x1ac, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC = IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL), + MX35_PAD_USBOTG_OC__GPIO3_15 = IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL), + + MX35_PAD_LD0__IPU_DISPB_DAT_0 = IOMUX_PAD(0x614, 0x1b0, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD0__GPIO2_0 = IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL), + MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 = IOMUX_PAD(0x614, 0x1b0, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD1__IPU_DISPB_DAT_1 = IOMUX_PAD(0x618, 0x1b4, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD1__GPIO2_1 = IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL), + MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 = IOMUX_PAD(0x618, 0x1b4, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD2__IPU_DISPB_DAT_2 = IOMUX_PAD(0x61c, 0x1b8, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD2__GPIO2_2 = IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL), + MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 = IOMUX_PAD(0x61c, 0x1b8, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD3__IPU_DISPB_DAT_3 = IOMUX_PAD(0x620, 0x1bc, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD3__GPIO2_3 = IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL), + MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 = IOMUX_PAD(0x620, 0x1bc, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD4__IPU_DISPB_DAT_4 = IOMUX_PAD(0x624, 0x1c0, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD4__GPIO2_4 = IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL), + MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 = IOMUX_PAD(0x624, 0x1c0, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD5__IPU_DISPB_DAT_5 = IOMUX_PAD(0x628, 0x1c4, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD5__GPIO2_5 = IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL), + MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 = IOMUX_PAD(0x628, 0x1c4, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD6__IPU_DISPB_DAT_6 = IOMUX_PAD(0x62c, 0x1c8, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD6__GPIO2_6 = IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL), + MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 = IOMUX_PAD(0x62c, 0x1c8, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD7__IPU_DISPB_DAT_7 = IOMUX_PAD(0x630, 0x1cc, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD7__GPIO2_7 = IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL), + MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 = IOMUX_PAD(0x630, 0x1cc, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD8__IPU_DISPB_DAT_8 = IOMUX_PAD(0x634, 0x1d0, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD8__GPIO2_8 = IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL), + MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 = IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD9__IPU_DISPB_DAT_9 = IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD9__GPIO2_9 = IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL), + MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 = IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD10__IPU_DISPB_DAT_10 = IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD10__GPIO2_10 = IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL), + MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 = IOMUX_PAD(0x63c, 0x1d8, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD11__IPU_DISPB_DAT_11 = IOMUX_PAD(0x640, 0x1dc, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD11__GPIO2_11 = IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL), + MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 = IOMUX_PAD(0x640, 0x1dc, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD11__ARM11P_TOP_TRACE_4 = IOMUX_PAD(0x640, 0x1dc, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD12__IPU_DISPB_DAT_12 = IOMUX_PAD(0x644, 0x1e0, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD12__GPIO2_12 = IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL), + MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 = IOMUX_PAD(0x644, 0x1e0, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD12__ARM11P_TOP_TRACE_5 = IOMUX_PAD(0x644, 0x1e0, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD13__IPU_DISPB_DAT_13 = IOMUX_PAD(0x648, 0x1e4, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD13__GPIO2_13 = IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL), + MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 = IOMUX_PAD(0x648, 0x1e4, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD13__ARM11P_TOP_TRACE_6 = IOMUX_PAD(0x648, 0x1e4, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD14__IPU_DISPB_DAT_14 = IOMUX_PAD(0x64c, 0x1e8, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD14__GPIO2_14 = IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL), + MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x64c, 0x1e8, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD14__ARM11P_TOP_TRACE_7 = IOMUX_PAD(0x64c, 0x1e8, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD15__IPU_DISPB_DAT_15 = IOMUX_PAD(0x650, 0x1ec, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD15__GPIO2_15 = IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL), + MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x650, 0x1ec, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD15__ARM11P_TOP_TRACE_8 = IOMUX_PAD(0x650, 0x1ec, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD16__IPU_DISPB_DAT_16 = IOMUX_PAD(0x654, 0x1f0, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD16__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL), + MX35_PAD_LD16__GPIO2_16 = IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL), + MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x654, 0x1f0, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD16__ARM11P_TOP_TRACE_9 = IOMUX_PAD(0x654, 0x1f0, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD17__IPU_DISPB_DAT_17 = IOMUX_PAD(0x658, 0x1f4, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD17__IPU_DISPB_CS2 = IOMUX_PAD(0x658, 0x1f4, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD17__GPIO2_17 = IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL), + MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x658, 0x1f4, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD17__ARM11P_TOP_TRACE_10 = IOMUX_PAD(0x658, 0x1f4, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD18__IPU_DISPB_DAT_18 = IOMUX_PAD(0x65c, 0x1f8, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD18__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL), + MX35_PAD_LD18__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL), + MX35_PAD_LD18__ESDHC3_CMD = IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL), + MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 = IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL), + MX35_PAD_LD18__GPIO3_24 = IOMUX_PAD(0x65c, 0x1f8, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x65c, 0x1f8, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD18__ARM11P_TOP_TRACE_11 = IOMUX_PAD(0x65c, 0x1f8, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD19__IPU_DISPB_DAT_19 = IOMUX_PAD(0x660, 0x1fc, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD19__IPU_DISPB_BCLK = IOMUX_PAD(0x660, 0x1fc, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD19__IPU_DISPB_CS1 = IOMUX_PAD(0x660, 0x1fc, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD19__ESDHC3_CLK = IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL), + MX35_PAD_LD19__USB_TOP_USBOTG_DIR = IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL), + MX35_PAD_LD19__GPIO3_25 = IOMUX_PAD(0x660, 0x1fc, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x660, 0x1fc, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD19__ARM11P_TOP_TRACE_12 = IOMUX_PAD(0x660, 0x1fc, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD20__IPU_DISPB_DAT_20 = IOMUX_PAD(0x664, 0x200, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD20__IPU_DISPB_CS0 = IOMUX_PAD(0x664, 0x200, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD20__IPU_DISPB_SD_CLK = IOMUX_PAD(0x664, 0x200, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD20__ESDHC3_DAT0 = IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL), + MX35_PAD_LD20__GPIO3_26 = IOMUX_PAD(0x664, 0x200, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 = IOMUX_PAD(0x664, 0x200, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD20__ARM11P_TOP_TRACE_13 = IOMUX_PAD(0x664, 0x200, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD21__IPU_DISPB_DAT_21 = IOMUX_PAD(0x668, 0x204, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD21__IPU_DISPB_PAR_RS = IOMUX_PAD(0x668, 0x204, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD21__IPU_DISPB_SER_RS = IOMUX_PAD(0x668, 0x204, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD21__ESDHC3_DAT1 = IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL), + MX35_PAD_LD21__USB_TOP_USBOTG_STP = IOMUX_PAD(0x668, 0x204, 4, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD21__GPIO3_27 = IOMUX_PAD(0x668, 0x204, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x668, 0x204, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD21__ARM11P_TOP_TRACE_14 = IOMUX_PAD(0x668, 0x204, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD22__IPU_DISPB_DAT_22 = IOMUX_PAD(0x66c, 0x208, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD22__IPU_DISPB_WR = IOMUX_PAD(0x66c, 0x208, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD22__IPU_DISPB_SD_D_I = IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL), + MX35_PAD_LD22__ESDHC3_DAT2 = IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL), + MX35_PAD_LD22__USB_TOP_USBOTG_NXT = IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL), + MX35_PAD_LD22__GPIO3_28 = IOMUX_PAD(0x66c, 0x208, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x66c, 0x208, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD22__ARM11P_TOP_TRCTL = IOMUX_PAD(0x66c, 0x208, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_LD23__IPU_DISPB_DAT_23 = IOMUX_PAD(0x670, 0x20c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD23__IPU_DISPB_RD = IOMUX_PAD(0x670, 0x20c, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD23__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL), + MX35_PAD_LD23__ESDHC3_DAT3 = IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL), + MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 = IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL), + MX35_PAD_LD23__GPIO3_29 = IOMUX_PAD(0x670, 0x20c, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x670, 0x20c, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_LD23__ARM11P_TOP_TRCLK = IOMUX_PAD(0x670, 0x20c, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC = IOMUX_PAD(0x674, 0x210, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL), + MX35_PAD_D3_HSYNC__GPIO3_30 = IOMUX_PAD(0x674, 0x210, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x674, 0x210, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 = IOMUX_PAD(0x674, 0x210, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK = IOMUX_PAD(0x678, 0x214, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK = IOMUX_PAD(0x678, 0x214, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_FPSHIFT__GPIO3_31 = IOMUX_PAD(0x678, 0x214, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 = IOMUX_PAD(0x678, 0x214, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 = IOMUX_PAD(0x678, 0x214, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY = IOMUX_PAD(0x67c, 0x218, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O = IOMUX_PAD(0x67c, 0x218, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_DRDY__GPIO1_0 = IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL), + MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 = IOMUX_PAD(0x67c, 0x218, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 = IOMUX_PAD(0x67c, 0x218, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_CONTRAST__IPU_DISPB_CONTR = IOMUX_PAD(0x680, 0x21c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CONTRAST__GPIO1_1 = IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL), + MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 = IOMUX_PAD(0x680, 0x21c, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 = IOMUX_PAD(0x680, 0x21c, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC = IOMUX_PAD(0x684, 0x220, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 = IOMUX_PAD(0x684, 0x220, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_VSYNC__GPIO1_2 = IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL), + MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD = IOMUX_PAD(0x684, 0x220, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 = IOMUX_PAD(0x684, 0x220, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D3_REV__IPU_DISPB_D3_REV = IOMUX_PAD(0x688, 0x224, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_REV__IPU_DISPB_SER_RS = IOMUX_PAD(0x688, 0x224, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_REV__GPIO1_3 = IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL), + MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x688, 0x224, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 = IOMUX_PAD(0x688, 0x224, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS = IOMUX_PAD(0x68c, 0x228, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_CLS__IPU_DISPB_CS2 = IOMUX_PAD(0x68c, 0x228, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_CLS__GPIO1_4 = IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL), + MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x68c, 0x228, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 = IOMUX_PAD(0x68c, 0x228, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL = IOMUX_PAD(0x690, 0x22c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL), + MX35_PAD_D3_SPL__GPIO1_5 = IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL), + MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x690, 0x22c, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 = IOMUX_PAD(0x690, 0x22c, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD1_CMD__ESDHC1_CMD = IOMUX_PAD(0x694, 0x230, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD1_CMD__MSHC_SCLK = IOMUX_PAD(0x694, 0x230, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL), + MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 = IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL), + MX35_PAD_SD1_CMD__GPIO1_6 = IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL), + MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL = IOMUX_PAD(0x694, 0x230, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD1_CLK__ESDHC1_CLK = IOMUX_PAD(0x698, 0x234, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD1_CLK__MSHC_BS = IOMUX_PAD(0x698, 0x234, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD1_CLK__IPU_DISPB_BCLK = IOMUX_PAD(0x698, 0x234, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 = IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL), + MX35_PAD_SD1_CLK__GPIO1_7 = IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL), + MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK = IOMUX_PAD(0x698, 0x234, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD1_DATA0__ESDHC1_DAT0 = IOMUX_PAD(0x69c, 0x238, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD1_DATA0__MSHC_DATA_0 = IOMUX_PAD(0x69c, 0x238, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 = IOMUX_PAD(0x69c, 0x238, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 = IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL), + MX35_PAD_SD1_DATA0__GPIO1_8 = IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL), + MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 = IOMUX_PAD(0x69c, 0x238, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD1_DATA1__ESDHC1_DAT1 = IOMUX_PAD(0x6a0, 0x23c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD1_DATA1__MSHC_DATA_1 = IOMUX_PAD(0x6a0, 0x23c, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS = IOMUX_PAD(0x6a0, 0x23c, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 = IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL), + MX35_PAD_SD1_DATA1__GPIO1_9 = IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL), + MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 = IOMUX_PAD(0x6a0, 0x23c, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD1_DATA2__ESDHC1_DAT2 = IOMUX_PAD(0x6a4, 0x240, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD1_DATA2__MSHC_DATA_2 = IOMUX_PAD(0x6a4, 0x240, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD1_DATA2__IPU_DISPB_WR = IOMUX_PAD(0x6a4, 0x240, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 = IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL), + MX35_PAD_SD1_DATA2__GPIO1_10 = IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL), + MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 = IOMUX_PAD(0x6a4, 0x240, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD1_DATA3__ESDHC1_DAT3 = IOMUX_PAD(0x6a8, 0x244, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD1_DATA3__MSHC_DATA_3 = IOMUX_PAD(0x6a8, 0x244, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD1_DATA3__IPU_DISPB_RD = IOMUX_PAD(0x6a8, 0x244, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 = IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL), + MX35_PAD_SD1_DATA3__GPIO1_11 = IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL), + MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 = IOMUX_PAD(0x6a8, 0x244, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD2_CMD__ESDHC2_CMD = IOMUX_PAD(0x6ac, 0x248, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD2_CMD__I2C3_SCL = IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL), + MX35_PAD_SD2_CMD__ESDHC1_DAT4 = IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL), + MX35_PAD_SD2_CMD__IPU_CSI_D_2 = IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL), + MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 = IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL), + MX35_PAD_SD2_CMD__GPIO2_0 = IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL), + MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x6ac, 0x248, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL), + + MX35_PAD_SD2_CLK__ESDHC2_CLK = IOMUX_PAD(0x6b0, 0x24c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD2_CLK__I2C3_SDA = IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL), + MX35_PAD_SD2_CLK__ESDHC1_DAT5 = IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL), + MX35_PAD_SD2_CLK__IPU_CSI_D_3 = IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL), + MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 = IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL), + MX35_PAD_SD2_CLK__GPIO2_1 = IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL), + MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL), + MX35_PAD_SD2_CLK__IPU_DISPB_CS2 = IOMUX_PAD(0x6b0, 0x24c, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_SD2_DATA0__ESDHC2_DAT0 = IOMUX_PAD(0x6b4, 0x250, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD2_DATA0__UART3_RXD_MUX = IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL), + MX35_PAD_SD2_DATA0__ESDHC1_DAT6 = IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL), + MX35_PAD_SD2_DATA0__IPU_CSI_D_4 = IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL), + MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 = IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL), + MX35_PAD_SD2_DATA0__GPIO2_2 = IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL), + MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL), + + MX35_PAD_SD2_DATA1__ESDHC2_DAT1 = IOMUX_PAD(0x6b8, 0x254, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD2_DATA1__UART3_TXD_MUX = IOMUX_PAD(0x6b8, 0x254, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD2_DATA1__ESDHC1_DAT7 = IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL), + MX35_PAD_SD2_DATA1__IPU_CSI_D_5 = IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL), + MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 = IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL), + MX35_PAD_SD2_DATA1__GPIO2_3 = IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL), + + MX35_PAD_SD2_DATA2__ESDHC2_DAT2 = IOMUX_PAD(0x6bc, 0x258, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD2_DATA2__UART3_RTS = IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL), + MX35_PAD_SD2_DATA2__CAN1_RXCAN = IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL), + MX35_PAD_SD2_DATA2__IPU_CSI_D_6 = IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL), + MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 = IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL), + MX35_PAD_SD2_DATA2__GPIO2_4 = IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL), + + MX35_PAD_SD2_DATA3__ESDHC2_DAT3 = IOMUX_PAD(0x6c0, 0x25c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD2_DATA3__UART3_CTS = IOMUX_PAD(0x6c0, 0x25c, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD2_DATA3__CAN1_TXCAN = IOMUX_PAD(0x6c0, 0x25c, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_SD2_DATA3__IPU_CSI_D_7 = IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL), + MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 = IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL), + MX35_PAD_SD2_DATA3__GPIO2_5 = IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL), + + MX35_PAD_ATA_CS0__ATA_CS0 = IOMUX_PAD(0x6c4, 0x260, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_CS0__CSPI1_SS3 = IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL), + MX35_PAD_ATA_CS0__IPU_DISPB_CS1 = IOMUX_PAD(0x6c4, 0x260, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_CS0__GPIO2_6 = IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL), + MX35_PAD_ATA_CS0__IPU_DIAGB_0 = IOMUX_PAD(0x6c4, 0x260, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 = IOMUX_PAD(0x6c4, 0x260, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_CS1__ATA_CS1 = IOMUX_PAD(0x6c8, 0x264, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_CS1__IPU_DISPB_CS2 = IOMUX_PAD(0x6c8, 0x264, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_CS1__CSPI2_SS0 = IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL), + MX35_PAD_ATA_CS1__GPIO2_7 = IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL), + MX35_PAD_ATA_CS1__IPU_DIAGB_1 = IOMUX_PAD(0x6c8, 0x264, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 = IOMUX_PAD(0x6c8, 0x264, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DIOR__ATA_DIOR = IOMUX_PAD(0x6cc, 0x268, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DIOR__ESDHC3_DAT0 = IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR = IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 = IOMUX_PAD(0x6cc, 0x268, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DIOR__CSPI2_SS1 = IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DIOR__GPIO2_8 = IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DIOR__IPU_DIAGB_2 = IOMUX_PAD(0x6cc, 0x268, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 = IOMUX_PAD(0x6cc, 0x268, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DIOW__ATA_DIOW = IOMUX_PAD(0x6d0, 0x26c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DIOW__ESDHC3_DAT1 = IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP = IOMUX_PAD(0x6d0, 0x26c, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 = IOMUX_PAD(0x6d0, 0x26c, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DIOW__CSPI2_MOSI = IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL), + MX35_PAD_ATA_DIOW__GPIO2_9 = IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DIOW__IPU_DIAGB_3 = IOMUX_PAD(0x6d0, 0x26c, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 = IOMUX_PAD(0x6d0, 0x26c, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DMACK__ATA_DMACK = IOMUX_PAD(0x6d4, 0x270, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DMACK__ESDHC3_DAT2 = IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT = IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DMACK__CSPI2_MISO = IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL), + MX35_PAD_ATA_DMACK__GPIO2_10 = IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DMACK__IPU_DIAGB_4 = IOMUX_PAD(0x6d4, 0x270, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 = IOMUX_PAD(0x6d4, 0x270, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_RESET_B__ATA_RESET_B = IOMUX_PAD(0x6d8, 0x274, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 = IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL), + MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 = IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL), + MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O = IOMUX_PAD(0x6d8, 0x274, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_RESET_B__CSPI2_RDY = IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL), + MX35_PAD_ATA_RESET_B__GPIO2_11 = IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL), + MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 = IOMUX_PAD(0x6d8, 0x274, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 = IOMUX_PAD(0x6d8, 0x274, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_IORDY__ATA_IORDY = IOMUX_PAD(0x6dc, 0x278, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_IORDY__ESDHC3_DAT4 = IOMUX_PAD(0x6dc, 0x278, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 = IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL), + MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL), + MX35_PAD_ATA_IORDY__ESDHC2_DAT4 = IOMUX_PAD(0x6dc, 0x278, 4, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_IORDY__GPIO2_12 = IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL), + MX35_PAD_ATA_IORDY__IPU_DIAGB_6 = IOMUX_PAD(0x6dc, 0x278, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 = IOMUX_PAD(0x6dc, 0x278, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DATA0__ATA_DATA_0 = IOMUX_PAD(0x6e0, 0x27c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA0__ESDHC3_DAT5 = IOMUX_PAD(0x6e0, 0x27c, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 = IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL), + MX35_PAD_ATA_DATA0__ESDHC2_DAT5 = IOMUX_PAD(0x6e0, 0x27c, 4, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA0__GPIO2_13 = IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA0__IPU_DIAGB_7 = IOMUX_PAD(0x6e0, 0x27c, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 = IOMUX_PAD(0x6e0, 0x27c, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DATA1__ATA_DATA_1 = IOMUX_PAD(0x6e4, 0x280, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA1__ESDHC3_DAT6 = IOMUX_PAD(0x6e4, 0x280, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 = IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK = IOMUX_PAD(0x6e4, 0x280, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA1__ESDHC2_DAT6 = IOMUX_PAD(0x6e4, 0x280, 4, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA1__GPIO2_14 = IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA1__IPU_DIAGB_8 = IOMUX_PAD(0x6e4, 0x280, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 = IOMUX_PAD(0x6e4, 0x280, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DATA2__ATA_DATA_2 = IOMUX_PAD(0x6e8, 0x284, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA2__ESDHC3_DAT7 = IOMUX_PAD(0x6e8, 0x284, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 = IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS = IOMUX_PAD(0x6e8, 0x284, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA2__ESDHC2_DAT7 = IOMUX_PAD(0x6e8, 0x284, 4, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA2__GPIO2_15 = IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA2__IPU_DIAGB_9 = IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 = IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DATA3__ATA_DATA_3 = IOMUX_PAD(0x6ec, 0x288, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA3__ESDHC3_CLK = IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 = IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA3__CSPI2_SCLK = IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL), + MX35_PAD_ATA_DATA3__GPIO2_16 = IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA3__IPU_DIAGB_10 = IOMUX_PAD(0x6ec, 0x288, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 = IOMUX_PAD(0x6ec, 0x288, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DATA4__ATA_DATA_4 = IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA4__ESDHC3_CMD = IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 = IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA4__GPIO2_17 = IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA4__IPU_DIAGB_11 = IOMUX_PAD(0x6f0, 0x28c, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 = IOMUX_PAD(0x6f0, 0x28c, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DATA5__ATA_DATA_5 = IOMUX_PAD(0x6f4, 0x290, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 = IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA5__GPIO2_18 = IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA5__IPU_DIAGB_12 = IOMUX_PAD(0x6f4, 0x290, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 = IOMUX_PAD(0x6f4, 0x290, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DATA6__ATA_DATA_6 = IOMUX_PAD(0x6f8, 0x294, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA6__CAN1_TXCAN = IOMUX_PAD(0x6f8, 0x294, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA6__UART1_DTR = IOMUX_PAD(0x6f8, 0x294, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD = IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA6__GPIO2_19 = IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA6__IPU_DIAGB_13 = IOMUX_PAD(0x6f8, 0x294, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DATA7__ATA_DATA_7 = IOMUX_PAD(0x6fc, 0x298, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA7__CAN1_RXCAN = IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL), + MX35_PAD_ATA_DATA7__UART1_DSR = IOMUX_PAD(0x6fc, 0x298, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD = IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA7__GPIO2_20 = IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA7__IPU_DIAGB_14 = IOMUX_PAD(0x6fc, 0x298, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DATA8__ATA_DATA_8 = IOMUX_PAD(0x700, 0x29c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA8__UART3_RTS = IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA8__UART1_RI = IOMUX_PAD(0x700, 0x29c, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC = IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA8__GPIO2_21 = IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA8__IPU_DIAGB_15 = IOMUX_PAD(0x700, 0x29c, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DATA9__ATA_DATA_9 = IOMUX_PAD(0x704, 0x2a0, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA9__UART3_CTS = IOMUX_PAD(0x704, 0x2a0, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA9__UART1_DCD = IOMUX_PAD(0x704, 0x2a0, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA9__GPIO2_22 = IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA9__IPU_DIAGB_16 = IOMUX_PAD(0x704, 0x2a0, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DATA10__ATA_DATA_10 = IOMUX_PAD(0x708, 0x2a4, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA10__UART3_RXD_MUX = IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL), + MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC = IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA10__GPIO2_23 = IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA10__IPU_DIAGB_17 = IOMUX_PAD(0x708, 0x2a4, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DATA11__ATA_DATA_11 = IOMUX_PAD(0x70c, 0x2a8, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA11__UART3_TXD_MUX = IOMUX_PAD(0x70c, 0x2a8, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA11__GPIO2_24 = IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA11__IPU_DIAGB_18 = IOMUX_PAD(0x70c, 0x2a8, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DATA12__ATA_DATA_12 = IOMUX_PAD(0x710, 0x2ac, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA12__I2C3_SCL = IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL), + MX35_PAD_ATA_DATA12__GPIO2_25 = IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA12__IPU_DIAGB_19 = IOMUX_PAD(0x710, 0x2ac, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DATA13__ATA_DATA_13 = IOMUX_PAD(0x714, 0x2b0, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA13__I2C3_SDA = IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL), + MX35_PAD_ATA_DATA13__GPIO2_26 = IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA13__IPU_DIAGB_20 = IOMUX_PAD(0x714, 0x2b0, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DATA14__ATA_DATA_14 = IOMUX_PAD(0x718, 0x2b4, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA14__IPU_CSI_D_0 = IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL), + MX35_PAD_ATA_DATA14__KPP_ROW_0 = IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL), + MX35_PAD_ATA_DATA14__GPIO2_27 = IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA14__IPU_DIAGB_21 = IOMUX_PAD(0x718, 0x2b4, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DATA15__ATA_DATA_15 = IOMUX_PAD(0x71c, 0x2b8, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DATA15__IPU_CSI_D_1 = IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL), + MX35_PAD_ATA_DATA15__KPP_ROW_1 = IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL), + MX35_PAD_ATA_DATA15__GPIO2_28 = IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DATA15__IPU_DIAGB_22 = IOMUX_PAD(0x71c, 0x2b8, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_INTRQ__ATA_INTRQ = IOMUX_PAD(0x720, 0x2bc, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 = IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL), + MX35_PAD_ATA_INTRQ__KPP_ROW_2 = IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL), + MX35_PAD_ATA_INTRQ__GPIO2_29 = IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL), + MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 = IOMUX_PAD(0x720, 0x2bc, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN = IOMUX_PAD(0x724, 0x2c0, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 = IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL), + MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 = IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL), + MX35_PAD_ATA_BUFF_EN__GPIO2_30 = IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL), + MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 = IOMUX_PAD(0x724, 0x2c0, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DMARQ__ATA_DMARQ = IOMUX_PAD(0x728, 0x2c4, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 = IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL), + MX35_PAD_ATA_DMARQ__KPP_COL_0 = IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL), + MX35_PAD_ATA_DMARQ__GPIO2_31 = IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 = IOMUX_PAD(0x728, 0x2c4, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 = IOMUX_PAD(0x728, 0x2c4, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DA0__ATA_DA_0 = IOMUX_PAD(0x72c, 0x2c8, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DA0__IPU_CSI_D_5 = IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL), + MX35_PAD_ATA_DA0__KPP_COL_1 = IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL), + MX35_PAD_ATA_DA0__GPIO3_0 = IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL), + MX35_PAD_ATA_DA0__IPU_DIAGB_26 = IOMUX_PAD(0x72c, 0x2c8, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 = IOMUX_PAD(0x72c, 0x2c8, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DA1__ATA_DA_1 = IOMUX_PAD(0x730, 0x2cc, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DA1__IPU_CSI_D_6 = IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL), + MX35_PAD_ATA_DA1__KPP_COL_2 = IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL), + MX35_PAD_ATA_DA1__GPIO3_1 = IOMUX_PAD(0x730, 0x2cc, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DA1__IPU_DIAGB_27 = IOMUX_PAD(0x730, 0x2cc, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 = IOMUX_PAD(0x730, 0x2cc, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_ATA_DA2__ATA_DA_2 = IOMUX_PAD(0x734, 0x2d0, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DA2__IPU_CSI_D_7 = IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL), + MX35_PAD_ATA_DA2__KPP_COL_3 = IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL), + MX35_PAD_ATA_DA2__GPIO3_2 = IOMUX_PAD(0x734, 0x2d0, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DA2__IPU_DIAGB_28 = IOMUX_PAD(0x734, 0x2d0, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 = IOMUX_PAD(0x734, 0x2d0, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_MLB_CLK__MLB_MLBCLK = IOMUX_PAD(0x738, 0x2d4, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_MLB_CLK__GPIO3_3 = IOMUX_PAD(0x738, 0x2d4, 5, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_MLB_DAT__MLB_MLBDAT = IOMUX_PAD(0x73c, 0x2d8, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_MLB_DAT__GPIO3_4 = IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL), + + MX35_PAD_MLB_SIG__MLB_MLBSIG = IOMUX_PAD(0x740, 0x2dc, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_MLB_SIG__GPIO3_5 = IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL), + + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x744, 0x2e0, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 = IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL), + MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX = IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL), + MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR = IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL), + MX35_PAD_FEC_TX_CLK__CSPI2_MOSI = IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL), + MX35_PAD_FEC_TX_CLK__GPIO3_6 = IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL), + MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL), + MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 = IOMUX_PAD(0x744, 0x2e0, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK = IOMUX_PAD(0x748, 0x2e4, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 = IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL), + MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX = IOMUX_PAD(0x748, 0x2e4, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP = IOMUX_PAD(0x748, 0x2e4, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_RX_CLK__CSPI2_MISO = IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL), + MX35_PAD_FEC_RX_CLK__GPIO3_7 = IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL), + MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I = IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL), + MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 = IOMUX_PAD(0x748, 0x2e4, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x74c, 0x2e8, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 = IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL), + MX35_PAD_FEC_RX_DV__UART3_RTS = IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL), + MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT = IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL), + MX35_PAD_FEC_RX_DV__CSPI2_SCLK = IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL), + MX35_PAD_FEC_RX_DV__GPIO3_8 = IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL), + MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK = IOMUX_PAD(0x74c, 0x2e8, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 = IOMUX_PAD(0x74c, 0x2e8, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_FEC_COL__FEC_COL = IOMUX_PAD(0x750, 0x2ec, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_COL__ESDHC1_DAT7 = IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL), + MX35_PAD_FEC_COL__UART3_CTS = IOMUX_PAD(0x750, 0x2ec, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 = IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL), + MX35_PAD_FEC_COL__CSPI2_RDY = IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL), + MX35_PAD_FEC_COL__GPIO3_9 = IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL), + MX35_PAD_FEC_COL__IPU_DISPB_SER_RS = IOMUX_PAD(0x750, 0x2ec, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 = IOMUX_PAD(0x750, 0x2ec, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_FEC_RDATA0__FEC_RDATA_0 = IOMUX_PAD(0x754, 0x2f0, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA0__PWM_PWMO = IOMUX_PAD(0x754, 0x2f0, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA0__UART3_DTR = IOMUX_PAD(0x754, 0x2f0, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 = IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA0__CSPI2_SS0 = IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA0__GPIO3_10 = IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 = IOMUX_PAD(0x754, 0x2f0, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 = IOMUX_PAD(0x754, 0x2f0, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_FEC_TDATA0__FEC_TDATA_0 = IOMUX_PAD(0x758, 0x2f4, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x758, 0x2f4, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA0__UART3_DSR = IOMUX_PAD(0x758, 0x2f4, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 = IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA0__CSPI2_SS1 = IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA0__GPIO3_11 = IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 = IOMUX_PAD(0x758, 0x2f4, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 = IOMUX_PAD(0x758, 0x2f4, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x75c, 0x2f8, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL), + MX35_PAD_FEC_TX_EN__UART3_RI = IOMUX_PAD(0x75c, 0x2f8, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 = IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL), + MX35_PAD_FEC_TX_EN__GPIO3_12 = IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL), + MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS = IOMUX_PAD(0x75c, 0x2f8, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 = IOMUX_PAD(0x75c, 0x2f8, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x760, 0x2fc, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_MDC__CAN2_TXCAN = IOMUX_PAD(0x760, 0x2fc, 1, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_MDC__UART3_DCD = IOMUX_PAD(0x760, 0x2fc, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 = IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL), + MX35_PAD_FEC_MDC__GPIO3_13 = IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL), + MX35_PAD_FEC_MDC__IPU_DISPB_WR = IOMUX_PAD(0x760, 0x2fc, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 = IOMUX_PAD(0x760, 0x2fc, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x764, 0x300, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_MDIO__CAN2_RXCAN = IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL), + MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 = IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL), + MX35_PAD_FEC_MDIO__GPIO3_14 = IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL), + MX35_PAD_FEC_MDIO__IPU_DISPB_RD = IOMUX_PAD(0x764, 0x300, 6, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 = IOMUX_PAD(0x764, 0x300, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_FEC_TX_ERR__FEC_TX_ERR = IOMUX_PAD(0x768, 0x304, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_TX_ERR__OWIRE_LINE = IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL), + MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL), + MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 = IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL), + MX35_PAD_FEC_TX_ERR__GPIO3_15 = IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL), + MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL), + MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 = IOMUX_PAD(0x768, 0x304, 7, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_FEC_RX_ERR__FEC_RX_ERR = IOMUX_PAD(0x76c, 0x308, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 = IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL), + MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 = IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL), + MX35_PAD_FEC_RX_ERR__KPP_COL_4 = IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL), + MX35_PAD_FEC_RX_ERR__GPIO3_16 = IOMUX_PAD(0x76c, 0x308, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL), + + MX35_PAD_FEC_CRS__FEC_CRS = IOMUX_PAD(0x770, 0x30c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_CRS__IPU_CSI_D_1 = IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL), + MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR = IOMUX_PAD(0x770, 0x30c, 3, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_CRS__KPP_COL_5 = IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL), + MX35_PAD_FEC_CRS__GPIO3_17 = IOMUX_PAD(0x770, 0x30c, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_CRS__IPU_FLASH_STROBE = IOMUX_PAD(0x770, 0x30c, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_FEC_RDATA1__FEC_RDATA_1 = IOMUX_PAD(0x774, 0x310, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 = IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC = IOMUX_PAD(0x774, 0x310, 2, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC = IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA1__KPP_COL_6 = IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA1__GPIO3_18 = IOMUX_PAD(0x774, 0x310, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 = IOMUX_PAD(0x774, 0x310, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_FEC_TDATA1__FEC_TDATA_1 = IOMUX_PAD(0x778, 0x314, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 = IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA1__KPP_COL_7 = IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA1__GPIO3_19 = IOMUX_PAD(0x778, 0x314, 5, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 = IOMUX_PAD(0x778, 0x314, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_FEC_RDATA2__FEC_RDATA_2 = IOMUX_PAD(0x77c, 0x318, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 = IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA2__KPP_ROW_4 = IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA2__GPIO3_20 = IOMUX_PAD(0x77c, 0x318, 5, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_FEC_TDATA2__FEC_TDATA_2 = IOMUX_PAD(0x780, 0x31c, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 = IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD = IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA2__KPP_ROW_5 = IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA2__GPIO3_21 = IOMUX_PAD(0x780, 0x31c, 5, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_FEC_RDATA3__FEC_RDATA_3 = IOMUX_PAD(0x784, 0x320, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 = IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC = IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA3__KPP_ROW_6 = IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL), + MX35_PAD_FEC_RDATA3__GPIO3_22 = IOMUX_PAD(0x784, 0x320, 6, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_FEC_TDATA3__FEC_TDATA_3 = IOMUX_PAD(0x788, 0x324, 0, 0x0, 0, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 = IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA3__KPP_ROW_7 = IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL), + MX35_PAD_FEC_TDATA3__GPIO3_23 = IOMUX_PAD(0x788, 0x324, 5, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK = IOMUX_PAD(0x78c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), + + MX35_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(0x790, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +}; + +#endif /* __IOMUX_MX35_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx35/lowlevel_macro.S b/roms/u-boot/arch/arm/include/asm/arch-mx35/lowlevel_macro.S new file mode 100644 index 000000000..4b1c9f863 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx35/lowlevel_macro.S @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + */ + +#include +#include +#include + +/* + * AIPS setup - Only setup MPROTx registers. + * The PACR default values are good. + * + * Default argument values: + * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to + * user-mode. + * - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for + * SDMA to access them. + */ +.macro init_aips mpr=0x77777777, opacr=0x00000000 + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =\mpr + str r1, [r0, #AIPS_MPR_0_7] + str r1, [r0, #AIPS_MPR_8_15] + ldr r2, =AIPS2_BASE_ADDR + str r1, [r2, #AIPS_MPR_0_7] + str r1, [r2, #AIPS_MPR_8_15] + + /* Did not change the AIPS control registers access type. */ + ldr r1, =\opacr + str r1, [r0, #AIPS_OPACR_0_7] + str r1, [r0, #AIPS_OPACR_8_15] + str r1, [r0, #AIPS_OPACR_16_23] + str r1, [r0, #AIPS_OPACR_24_31] + str r1, [r0, #AIPS_OPACR_32_39] + str r1, [r2, #AIPS_OPACR_0_7] + str r1, [r2, #AIPS_OPACR_8_15] + str r1, [r2, #AIPS_OPACR_16_23] + str r1, [r2, #AIPS_OPACR_24_31] + str r1, [r2, #AIPS_OPACR_32_39] +.endm + +/* + * MAX (Multi-Layer AHB Crossbar Switch) setup + * + * Default argument values: + * - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1 + * - SGPCR: always park on last master + * - MGPCR: restore default values + */ +.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000 + ldr r0, =MAX_BASE_ADDR + ldr r1, =\mpr + str r1, [r0, #MAX_MPR0] /* for S0 */ + str r1, [r0, #MAX_MPR1] /* for S1 */ + str r1, [r0, #MAX_MPR2] /* for S2 */ + str r1, [r0, #MAX_MPR3] /* for S3 */ + str r1, [r0, #MAX_MPR4] /* for S4 */ + ldr r1, =\sgpcr + str r1, [r0, #MAX_SGPCR0] /* for S0 */ + str r1, [r0, #MAX_SGPCR1] /* for S1 */ + str r1, [r0, #MAX_SGPCR2] /* for S2 */ + str r1, [r0, #MAX_SGPCR3] /* for S3 */ + str r1, [r0, #MAX_SGPCR4] /* for S4 */ + ldr r1, =\mgpcr + str r1, [r0, #MAX_MGPCR0] /* for M0 */ + str r1, [r0, #MAX_MGPCR1] /* for M1 */ + str r1, [r0, #MAX_MGPCR2] /* for M2 */ + str r1, [r0, #MAX_MGPCR3] /* for M3 */ + str r1, [r0, #MAX_MGPCR4] /* for M4 */ + str r1, [r0, #MAX_MGPCR5] /* for M5 */ +.endm + +/* + * M3IF setup + * + * Default argument values: + * - CTL: + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000 + * ------------ + * 0x00000040 + */ +.macro init_m3if ctl=0x00000040 + /* M3IF Control Register (M3IFCTL) */ + write32 M3IF_BASE_ADDR, \ctl +.endm + +.macro core_init + mrc p15, 0, r1, c1, c0, 0 + + /* Set branch prediction enable */ + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #7 + mcr p15, 0, r0, c1, c0, 1 + orr r1, r1, #1 << 11 + + /* Set unaligned access enable */ + orr r1, r1, #1 << 22 + + /* Set low int latency enable */ + orr r1, r1, #1 << 21 + + mcr p15, 0, r1, c1, c0, 0 + + mov r0, #0 + + mcr p15, 0, r0, c15, c2, 4 + + mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */ + mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */ + mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */ + + /* Setup the Peripheral Port Memory Remap Register */ + ldr r0, =0x40000015 /* Start from AIPS 2-GB region */ + mcr p15, 0, r0, c15, c2, 4 +.endm diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx35/mmc_host_def.h b/roms/u-boot/arch/arm/include/asm/arch-mx35/mmc_host_def.h new file mode 100644 index 000000000..81c19bb32 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx35/mmc_host_def.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2008 + * Texas Instruments, + * Syed Mohammed Khasim + */ + +#ifndef MMC_HOST_DEF_H +#define MMC_HOST_DEF_H + +/* Driver definitions */ +#define MMCSD_SECTOR_SIZE 512 + +#endif /* MMC_HOST_DEF_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx35/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-mx35/sys_proto.h new file mode 100644 index 000000000..6e8b84128 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx35/sys_proto.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + */ + +#ifndef _MX35_SYS_PROTO_H_ +#define _MX35_SYS_PROTO_H_ + +#include + +void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config, u32 row, + u32 col, u32 dsize, u32 refresh); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx5/clock.h b/roms/u-boot/arch/arm/include/asm/arch-mx5/clock.h new file mode 100644 index 000000000..63a51042e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx5/clock.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +#ifdef CONFIG_SYS_MX5_HCLK +#define MXC_HCLK CONFIG_SYS_MX5_HCLK +#else +#define MXC_HCLK 24000000 +#endif + +#ifdef CONFIG_SYS_MX5_CLK32 +#define MXC_CLK32 CONFIG_SYS_MX5_CLK32 +#else +#define MXC_CLK32 32768 +#endif + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_IPG_PERCLK, + MXC_UART_CLK, + MXC_CSPI_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, + MXC_ESDHC4_CLK, + MXC_FEC_CLK, + MXC_SATA_CLK, + MXC_DDR_CLK, + MXC_NFC_CLK, + MXC_PERIPH_CLK, + MXC_I2C_CLK, + MXC_LDB_CLK, +}; + +u32 imx_get_uartclk(void); +u32 imx_get_fecclk(void); +unsigned int mxc_get_clock(enum mxc_clock clk); +int mxc_set_clock(u32 ref, u32 freq, u32 clk_type); +void set_usb_phy_clk(void); +void enable_usb_phy1_clk(bool enable); +void enable_usb_phy2_clk(bool enable); +void set_usboh3_clk(void); +void enable_usboh3_clk(bool enable); +void mxc_set_sata_internal_clock(void); +int enable_i2c_clk(unsigned char enable, unsigned i2c_num); +void enable_nfc_clk(unsigned char enable); +void enable_efuse_prog_supply(bool enable); + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx5/crm_regs.h b/roms/u-boot/arch/arm/include/asm/arch-mx5/crm_regs.h new file mode 100644 index 000000000..9d54ab7fb --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -0,0 +1,616 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 Freescale Semiconductor, Inc. + */ + +#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ + +#define MXC_CCM_BASE CCM_BASE_ADDR + +/* DPLL register mapping structure */ +struct mxc_pll_reg { + u32 ctrl; + u32 config; + u32 op; + u32 mfd; + u32 mfn; + u32 mfn_minus; + u32 mfn_plus; + u32 hfs_op; + u32 hfs_mfd; + u32 hfs_mfn; + u32 mfn_togc; + u32 destat; +}; + +/* Register maping of CCM*/ +struct mxc_ccm_reg { + u32 ccr; /* 0x0000 */ + u32 ccdr; + u32 csr; + u32 ccsr; + u32 cacrr; /* 0x0010*/ + u32 cbcdr; + u32 cbcmr; + u32 cscmr1; + u32 cscmr2; /* 0x0020 */ + u32 cscdr1; + u32 cs1cdr; + u32 cs2cdr; + u32 cdcdr; /* 0x0030 */ + u32 chsccdr; + u32 cscdr2; + u32 cscdr3; + u32 cscdr4; /* 0x0040 */ + u32 cwdr; + u32 cdhipr; + u32 cdcr; + u32 ctor; /* 0x0050 */ + u32 clpcr; + u32 cisr; + u32 cimr; + u32 ccosr; /* 0x0060 */ + u32 cgpr; + u32 CCGR0; + u32 CCGR1; + u32 CCGR2; /* 0x0070 */ + u32 CCGR3; + u32 CCGR4; + u32 CCGR5; + u32 CCGR6; /* 0x0080 */ +#ifdef CONFIG_MX53 + u32 CCGR7; /* 0x0084 */ +#endif + u32 cmeor; +}; + +/* Define the bits in register CCR */ +#define MXC_CCM_CCR_COSC_EN (0x1 << 12) +#if defined(CONFIG_MX51) +#define MXC_CCM_CCR_FPM_MULT (0x1 << 11) +#endif +#define MXC_CCM_CCR_CAMP2_EN (0x1 << 10) +#define MXC_CCM_CCR_CAMP1_EN (0x1 << 9) +#if defined(CONFIG_MX51) +#define MXC_CCM_CCR_FPM_EN (0x1 << 8) +#endif +#define MXC_CCM_CCR_OSCNT_OFFSET 0 +#define MXC_CCM_CCR_OSCNT_MASK 0xFF +#define MXC_CCM_CCR_OSCNT(v) ((v) & 0xFF) +#define MXC_CCM_CCR_OSCNT_RD(r) ((r) & 0xFF) + +/* Define the bits in register CCSR */ +#if defined(CONFIG_MX51) +#define MXC_CCM_CCSR_LP_APM (0x1 << 9) +#elif defined(CONFIG_MX53) +#define MXC_CCM_CCSR_LP_APM (0x1 << 10) +#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (0x1 << 9) +#endif +#define MXC_CCM_CCSR_STEP_SEL_OFFSET 7 +#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) +#define MXC_CCM_CCSR_STEP_SEL(v) (((v) & 0x3) << 7) +#define MXC_CCM_CCSR_STEP_SEL_RD(r) (((r) >> 7) & 0x3) +#define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET 5 +#define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK (0x3 << 5) +#define MXC_CCM_CCSR_PLL2_DIV_PODF(v) (((v) & 0x3) << 5) +#define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r) (((r) >> 5) & 0x3) +#define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET 3 +#define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK (0x3 << 3) +#define MXC_CCM_CCSR_PLL3_DIV_PODF(v) (((v) & 0x3) << 3) +#define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r) (((r) >> 3) & 0x3) +#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (0x1 << 2) +#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (0x1 << 1) +#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL 0x1 + +/* Define the bits in register CACRR */ +#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 +#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 +#define MXC_CCM_CACRR_ARM_PODF(v) ((v) & 0x7) +#define MXC_CCM_CACRR_ARM_PODF_RD(r) ((r) & 0x7) + +/* Define the bits in register CBCDR */ +#define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30) +#define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27 +#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) +#define MXC_CCM_CBCDR_DDR_PODF(v) (((v) & 0x7) << 27) +#define MXC_CCM_CBCDR_DDR_PODF_RD(r) (((r) >> 27) & 0x7) +#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) +#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) +#define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22 +#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) +#define MXC_CCM_CBCDR_EMI_PODF(v) (((v) & 0x7) << 22) +#define MXC_CCM_CBCDR_EMI_PODF_RD(r) (((r) >> 22) & 0x7) +#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19 +#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) +#define MXC_CCM_CBCDR_AXI_B_PODF(v) (((v) & 0x7) << 19) +#define MXC_CCM_CBCDR_AXI_B_PODF_RD(r) (((r) >> 19) & 0x7) +#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16 +#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) +#define MXC_CCM_CBCDR_AXI_A_PODF(v) (((v) & 0x7) << 16) +#define MXC_CCM_CBCDR_AXI_A_PODF_RD(r) (((r) >> 16) & 0x7) +#define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13 +#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) +#define MXC_CCM_CBCDR_NFC_PODF(v) (((v) & 0x7) << 13) +#define MXC_CCM_CBCDR_NFC_PODF_RD(r) (((r) >> 13) & 0x7) +#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 +#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) +#define MXC_CCM_CBCDR_AHB_PODF(v) (((v) & 0x7) << 10) +#define MXC_CCM_CBCDR_AHB_PODF_RD(r) (((r) >> 10) & 0x7) +#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 +#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) +#define MXC_CCM_CBCDR_IPG_PODF(v) (((v) & 0x3) << 8) +#define MXC_CCM_CBCDR_IPG_PODF_RD(r) (((r) >> 8) & 0x3) +#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6 +#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) +#define MXC_CCM_CBCDR_PERCLK_PRED1(v) (((v) & 0x3) << 6) +#define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r) (((r) >> 6) & 0x3) +#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3 +#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) +#define MXC_CCM_CBCDR_PERCLK_PRED2(v) (((v) & 0x7) << 3) +#define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r) (((r) >> 3) & 0x7) +#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0 +#define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7 +#define MXC_CCM_CBCDR_PERCLK_PODF(v) ((v) & 0x7) +#define MXC_CCM_CBCDR_PERCLK_PODF_RD(r) ((r) & 0x7) + +/* Define the bits in register CSCMR1 */ +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30 +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v) (((v) & 0x3) << 30) +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r) (((r) >> 30) & 0x3) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28 +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v) (((v) & 0x3) << 28) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r) (((r) >> 28) & 0x3) +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24 +#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR1_UART_CLK_SEL(v) (((v) & 0x3) << 24) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r) (((r) >> 24) & 0x3) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22 +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v) (((v) & 0x3) << 22) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r) (((r) >> 22) & 0x3) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20 +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v) (((v) & 0x3) << 20) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r) (((r) >> 20) & 0x3) +#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) +#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16 +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v) (((v) & 0x3) << 16) +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r) (((r) >> 16) & 0x3) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14 +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v) (((v) & 0x3) << 14) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r) (((r) >> 14) & 0x3) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v) (((v) & 0x3) << 12) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r) (((r) >> 12) & 0x3) +#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) +#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8 +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v) (((v) & 0x3) << 8) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r) (((r) >> 8) & 0x3) +#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) +#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4 +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v) (((v) & 0x3) << 4) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r) (((r) >> 4) & 0x3) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2 +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v) (((v) & 0x3) << 2) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r) (((r) >> 2) & 0x3) +#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1 + +/* Define the bits in register CSCMR2 */ +#define MXC_CCM_CSCMR2_DI0_CLK_SEL_OFFSET 26 +#define MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK (0x7 << 26) +#define MXC_CCM_CSCMR2_DI0_CLK_SEL(v) (((v) & 0x7) << 26) +#define MXC_CCM_CSCMR2_DI0_CLK_SEL_RD(r) (((r) >> 26) & 0x7) + +#define MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK 5 + +/* Define the bits in register CSCDR2 */ +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25 +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v) (((v) & 0x7) << 25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r) (((r) >> 25) & 0x7) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19 +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v) (((v) & 0x3F) << 19) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r) (((r) >> 19) & 0x3F) +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16 +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR2_SIM_CLK_PRED(v) (((v) & 0x7) << 16) +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r) (((r) >> 16) & 0x7) +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9 +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR2_SIM_CLK_PODF(v) (((v) & 0x3F) << 9) +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r) (((r) >> 9) & 0x3F) +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6 +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v) (((v) & 0x7) << 6) +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r) (((r) >> 6) & 0x7) +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET 0 +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK 0x3F +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v) ((v) & 0x3F) +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r) ((r) & 0x3F) + +/* Define the bits in register CBCMR */ +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v) (((v) & 0x3) << 14) +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r) (((r) >> 14) & 0x3) +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12 +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v) (((v) & 0x3) << 12) +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r) (((r) >> 12) & 0x3) +#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10 +#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CBCMR_DDR_CLK_SEL(v) (((v) & 0x3) << 10) +#define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r) (((r) >> 10) & 0x3) +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8 +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v) (((v) & 0x3) << 8) +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r) (((r) >> 8) & 0x3) +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6 +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v) (((v) & 0x3) << 6) +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r) (((r) >> 6) & 0x3) +#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4 +#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CBCMR_GPU_CLK_SEL(v) (((v) & 0x3) << 4) +#define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r) (((r) >> 4) & 0x3) +#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) + +/* Define the bits in register CSCDR1 */ +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22 +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v) (((v) & 0x7) << 22) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r) (((r) >> 22) & 0x7) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19 +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v) (((v) & 0x7) << 19) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r) (((r) >> 19) & 0x7) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16 +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v) (((v) & 0x7) << 16) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r) (((r) >> 16) & 0x7) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14 +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF(v) (((v) & 0x3) << 14) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r) (((r) >> 14) & 0x3) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11 +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v) (((v) & 0x7) << 11) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r) (((r) >> 11) & 0x7) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v) (((v) & 0x7) << 8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r) (((r) >> 8) & 0x7) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v) (((v) & 0x3) << 6) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r) (((r) >> 6) & 0x3) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3 +#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) +#define MXC_CCM_CSCDR1_UART_CLK_PRED(v) (((v) & 0x7) << 3) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r) (((r) >> 3) & 0x7) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7 +#define MXC_CCM_CSCDR1_UART_CLK_PODF(v) ((v) & 0x7) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r) ((r) & 0x7) + +/* Define the bits in register CCDR */ +#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) + +/* Define the bits in register CGPR */ +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) + +/* Define the bits in register CCGRx */ +#define MXC_CCM_CCGR_CG_MASK 0x3 +#define MXC_CCM_CCGR_CG_OFF 0x0 +#define MXC_CCM_CCGR_CG_RUN_ON 0x1 +#define MXC_CCM_CCGR_CG_ON 0x3 + +#define MXC_CCM_CCGR0_ARM_BUS_OFFSET 0 +#define MXC_CCM_CCGR0_ARM_BUS(v) (((v) & 0x3) << 0) +#define MXC_CCM_CCGR0_ARM_AXI_OFFSET 2 +#define MXC_CCM_CCGR0_ARM_AXI(v) (((v) & 0x3) << 2) +#define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET 4 +#define MXC_CCM_CCGR0_ARM_DEBUG(v) (((v) & 0x3) << 4) +#define MXC_CCM_CCGR0_TZIC_OFFSET 6 +#define MXC_CCM_CCGR0_TZIC(v) (((v) & 0x3) << 6) +#define MXC_CCM_CCGR0_DAP_OFFSET 8 +#define MXC_CCM_CCGR0_DAP(v) (((v) & 0x3) << 8) +#define MXC_CCM_CCGR0_TPIU_OFFSET 10 +#define MXC_CCM_CCGR0_TPIU(v) (((v) & 0x3) << 10) +#define MXC_CCM_CCGR0_CTI2_OFFSET 12 +#define MXC_CCM_CCGR0_CTI2(v) (((v) & 0x3) << 12) +#define MXC_CCM_CCGR0_CTI3_OFFSET 14 +#define MXC_CCM_CCGR0_CTI3(v) (((v) & 0x3) << 14) +#define MXC_CCM_CCGR0_AHBMUX1_OFFSET 16 +#define MXC_CCM_CCGR0_AHBMUX1(v) (((v) & 0x3) << 16) +#define MXC_CCM_CCGR0_AHBMUX2_OFFSET 18 +#define MXC_CCM_CCGR0_AHBMUX2(v) (((v) & 0x3) << 18) +#define MXC_CCM_CCGR0_ROMCP_OFFSET 20 +#define MXC_CCM_CCGR0_ROMCP(v) (((v) & 0x3) << 20) +#define MXC_CCM_CCGR0_ROM_OFFSET 22 +#define MXC_CCM_CCGR0_ROM(v) (((v) & 0x3) << 22) +#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 24 +#define MXC_CCM_CCGR0_AIPS_TZ1(v) (((v) & 0x3) << 24) +#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 26 +#define MXC_CCM_CCGR0_AIPS_TZ2(v) (((v) & 0x3) << 26) +#define MXC_CCM_CCGR0_AHB_MAX_OFFSET 28 +#define MXC_CCM_CCGR0_AHB_MAX(v) (((v) & 0x3) << 28) +#define MXC_CCM_CCGR0_IIM_OFFSET 30 +#define MXC_CCM_CCGR0_IIM(v) (((v) & 0x3) << 30) + +#define MXC_CCM_CCGR1_TMAX1_OFFSET 0 +#define MXC_CCM_CCGR1_TMAX1(v) (((v) & 0x3) << 0) +#define MXC_CCM_CCGR1_TMAX2_OFFSET 2 +#define MXC_CCM_CCGR1_TMAX2(v) (((v) & 0x3) << 2) +#define MXC_CCM_CCGR1_TMAX3_OFFSET 4 +#define MXC_CCM_CCGR1_TMAX3(v) (((v) & 0x3) << 4) +#define MXC_CCM_CCGR1_UART1_IPG_OFFSET 6 +#define MXC_CCM_CCGR1_UART1_IPG(v) (((v) & 0x3) << 6) +#define MXC_CCM_CCGR1_UART1_PER_OFFSET 8 +#define MXC_CCM_CCGR1_UART1_PER(v) (((v) & 0x3) << 8) +#define MXC_CCM_CCGR1_UART2_IPG_OFFSET 10 +#define MXC_CCM_CCGR1_UART2_IPG(v) (((v) & 0x3) << 10) +#define MXC_CCM_CCGR1_UART2_PER_OFFSET 12 +#define MXC_CCM_CCGR1_UART2_PER(v) (((v) & 0x3) << 12) +#define MXC_CCM_CCGR1_UART3_IPG_OFFSET 14 +#define MXC_CCM_CCGR1_UART3_IPG(v) (((v) & 0x3) << 14) +#define MXC_CCM_CCGR1_UART3_PER_OFFSET 16 +#define MXC_CCM_CCGR1_UART3_PER(v) (((v) & 0x3) << 16) +#define MXC_CCM_CCGR1_I2C1_OFFSET 18 +#define MXC_CCM_CCGR1_I2C1(v) (((v) & 0x3) << 18) +#define MXC_CCM_CCGR1_I2C2_OFFSET 20 +#define MXC_CCM_CCGR1_I2C2(v) (((v) & 0x3) << 20) +#if defined(CONFIG_MX51) +#define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET 22 +#define MXC_CCM_CCGR1_HSI2C_IPG(v) (((v) & 0x3) << 22) +#define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET 24 +#define MXC_CCM_CCGR1_HSI2C_SERIAL(v) (((v) & 0x3) << 24) +#elif defined(CONFIG_MX53) +#define MXC_CCM_CCGR1_I2C3_OFFSET 22 +#define MXC_CCM_CCGR1_I2C3(v) (((v) & 0x3) << 22) +#endif +#define MXC_CCM_CCGR1_FIRI_IPG_OFFSET 26 +#define MXC_CCM_CCGR1_FIRI_IPG(v) (((v) & 0x3) << 26) +#define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET 28 +#define MXC_CCM_CCGR1_FIRI_SERIAL(v) (((v) & 0x3) << 28) +#define MXC_CCM_CCGR1_SCC_OFFSET 30 +#define MXC_CCM_CCGR1_SCC(v) (((v) & 0x3) << 30) + +#if defined(CONFIG_MX51) +#define MXC_CCM_CCGR2_USB_PHY_OFFSET 0 +#define MXC_CCM_CCGR2_USB_PHY(v) (((v) & 0x3) << 0) +#endif +#define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET 2 +#define MXC_CCM_CCGR2_EPIT1_IPG(v) (((v) & 0x3) << 2) +#define MXC_CCM_CCGR2_EPIT1_HF_OFFSET 4 +#define MXC_CCM_CCGR2_EPIT1_HF(v) (((v) & 0x3) << 4) +#define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET 6 +#define MXC_CCM_CCGR2_EPIT2_IPG(v) (((v) & 0x3) << 6) +#define MXC_CCM_CCGR2_EPIT2_HF_OFFSET 8 +#define MXC_CCM_CCGR2_EPIT2_HF(v) (((v) & 0x3) << 8) +#define MXC_CCM_CCGR2_PWM1_IPG_OFFSET 10 +#define MXC_CCM_CCGR2_PWM1_IPG(v) (((v) & 0x3) << 10) +#define MXC_CCM_CCGR2_PWM1_HF_OFFSET 12 +#define MXC_CCM_CCGR2_PWM1_HF(v) (((v) & 0x3) << 12) +#define MXC_CCM_CCGR2_PWM2_IPG_OFFSET 14 +#define MXC_CCM_CCGR2_PWM2_IPG(v) (((v) & 0x3) << 14) +#define MXC_CCM_CCGR2_PWM2_HF_OFFSET 16 +#define MXC_CCM_CCGR2_PWM2_HF(v) (((v) & 0x3) << 16) +#define MXC_CCM_CCGR2_GPT_IPG_OFFSET 18 +#define MXC_CCM_CCGR2_GPT_IPG(v) (((v) & 0x3) << 18) +#define MXC_CCM_CCGR2_GPT_HF_OFFSET 20 +#define MXC_CCM_CCGR2_GPT_HF(v) (((v) & 0x3) << 20) +#define MXC_CCM_CCGR2_OWIRE_OFFSET 22 +#define MXC_CCM_CCGR2_OWIRE(v) (((v) & 0x3) << 22) +#define MXC_CCM_CCGR2_FEC_OFFSET 24 +#define MXC_CCM_CCGR2_FEC(v) (((v) & 0x3) << 24) +#define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET 26 +#define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v) (((v) & 0x3) << 26) +#define MXC_CCM_CCGR2_USBOH3_60M_OFFSET 28 +#define MXC_CCM_CCGR2_USBOH3_60M(v) (((v) & 0x3) << 28) +#define MXC_CCM_CCGR2_TVE_OFFSET 30 +#define MXC_CCM_CCGR2_TVE(v) (((v) & 0x3) << 30) + +#define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET 0 +#define MXC_CCM_CCGR3_ESDHC1_IPG(v) (((v) & 0x3) << 0) +#define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET 2 +#define MXC_CCM_CCGR3_ESDHC1_PER(v) (((v) & 0x3) << 2) +#define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET 4 +#define MXC_CCM_CCGR3_ESDHC2_IPG(v) (((v) & 0x3) << 4) +#define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET 6 +#define MXC_CCM_CCGR3_ESDHC2_PER(v) (((v) & 0x3) << 6) +#define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET 8 +#define MXC_CCM_CCGR3_ESDHC3_IPG(v) (((v) & 0x3) << 8) +#define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET 10 +#define MXC_CCM_CCGR3_ESDHC3_PER(v) (((v) & 0x3) << 10) +#define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET 12 +#define MXC_CCM_CCGR3_ESDHC4_IPG(v) (((v) & 0x3) << 12) +#define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET 14 +#define MXC_CCM_CCGR3_ESDHC4_PER(v) (((v) & 0x3) << 14) +#define MXC_CCM_CCGR3_SSI1_IPG_OFFSET 16 +#define MXC_CCM_CCGR3_SSI1_IPG(v) (((v) & 0x3) << 16) +#define MXC_CCM_CCGR3_SSI1_SSI_OFFSET 18 +#define MXC_CCM_CCGR3_SSI1_SSI(v) (((v) & 0x3) << 18) +#define MXC_CCM_CCGR3_SSI2_IPG_OFFSET 20 +#define MXC_CCM_CCGR3_SSI2_IPG(v) (((v) & 0x3) << 20) +#define MXC_CCM_CCGR3_SSI2_SSI_OFFSET 22 +#define MXC_CCM_CCGR3_SSI2_SSI(v) (((v) & 0x3) << 22) +#define MXC_CCM_CCGR3_SSI3_IPG_OFFSET 24 +#define MXC_CCM_CCGR3_SSI3_IPG(v) (((v) & 0x3) << 24) +#define MXC_CCM_CCGR3_SSI3_SSI_OFFSET 26 +#define MXC_CCM_CCGR3_SSI3_SSI(v) (((v) & 0x3) << 26) +#define MXC_CCM_CCGR3_SSI_EXT1_OFFSET 28 +#define MXC_CCM_CCGR3_SSI_EXT1(v) (((v) & 0x3) << 28) +#define MXC_CCM_CCGR3_SSI_EXT2_OFFSET 30 +#define MXC_CCM_CCGR3_SSI_EXT2(v) (((v) & 0x3) << 30) + +#define MXC_CCM_CCGR4_PATA_OFFSET 0 +#define MXC_CCM_CCGR4_PATA(v) (((v) & 0x3) << 0) +#if defined(CONFIG_MX51) +#define MXC_CCM_CCGR4_SIM_IPG_OFFSET 2 +#define MXC_CCM_CCGR4_SIM_IPG(v) (((v) & 0x3) << 2) +#define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET 4 +#define MXC_CCM_CCGR4_SIM_SERIAL(v) (((v) & 0x3) << 4) +#elif defined(CONFIG_MX53) +#define MXC_CCM_CCGR4_SATA_OFFSET 2 +#define MXC_CCM_CCGR4_SATA(v) (((v) & 0x3) << 2) +#define MXC_CCM_CCGR4_CAN2_IPG_OFFSET 6 +#define MXC_CCM_CCGR4_CAN2_IPG(v) (((v) & 0x3) << 6) +#define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET 8 +#define MXC_CCM_CCGR4_CAN2_SERIAL(v) (((v) & 0x3) << 8) +#define MXC_CCM_CCGR4_USB_PHY1_OFFSET 10 +#define MXC_CCM_CCGR4_USB_PHY1(v) (((v) & 0x3) << 10) +#define MXC_CCM_CCGR4_USB_PHY2_OFFSET 12 +#define MXC_CCM_CCGR4_USB_PHY2(v) (((v) & 0x3) << 12) +#endif +#define MXC_CCM_CCGR4_SAHARA_OFFSET 14 +#define MXC_CCM_CCGR4_SAHARA(v) (((v) & 0x3) << 14) +#define MXC_CCM_CCGR4_RTIC_OFFSET 16 +#define MXC_CCM_CCGR4_RTIC(v) (((v) & 0x3) << 16) +#define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET 18 +#define MXC_CCM_CCGR4_ECSPI1_IPG(v) (((v) & 0x3) << 18) +#define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET 20 +#define MXC_CCM_CCGR4_ECSPI1_PER(v) (((v) & 0x3) << 20) +#define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET 22 +#define MXC_CCM_CCGR4_ECSPI2_IPG(v) (((v) & 0x3) << 22) +#define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET 24 +#define MXC_CCM_CCGR4_ECSPI2_PER(v) (((v) & 0x3) << 24) +#define MXC_CCM_CCGR4_CSPI_IPG_OFFSET 26 +#define MXC_CCM_CCGR4_CSPI_IPG(v) (((v) & 0x3) << 26) +#define MXC_CCM_CCGR4_SRTC_OFFSET 28 +#define MXC_CCM_CCGR4_SRTC(v) (((v) & 0x3) << 28) +#define MXC_CCM_CCGR4_SDMA_OFFSET 30 +#define MXC_CCM_CCGR4_SDMA(v) (((v) & 0x3) << 30) + +#define MXC_CCM_CCGR5_SPBA_OFFSET 0 +#define MXC_CCM_CCGR5_SPBA(v) (((v) & 0x3) << 0) +#define MXC_CCM_CCGR5_GPU_OFFSET 2 +#define MXC_CCM_CCGR5_GPU(v) (((v) & 0x3) << 2) +#define MXC_CCM_CCGR5_GARB_OFFSET 4 +#define MXC_CCM_CCGR5_GARB(v) (((v) & 0x3) << 4) +#define MXC_CCM_CCGR5_VPU_OFFSET 6 +#define MXC_CCM_CCGR5_VPU(v) (((v) & 0x3) << 6) +#define MXC_CCM_CCGR5_VPU_REF_OFFSET 8 +#define MXC_CCM_CCGR5_VPU_REF(v) (((v) & 0x3) << 8) +#define MXC_CCM_CCGR5_IPU_OFFSET 10 +#define MXC_CCM_CCGR5_IPU(v) (((v) & 0x3) << 10) +#if defined(CONFIG_MX51) +#define MXC_CCM_CCGR5_IPUMUX12_OFFSET 12 +#define MXC_CCM_CCGR5_IPUMUX12(v) (((v) & 0x3) << 12) +#elif defined(CONFIG_MX53) +#define MXC_CCM_CCGR5_IPUMUX1_OFFSET 12 +#define MXC_CCM_CCGR5_IPUMUX1(v) (((v) & 0x3) << 12) +#endif +#define MXC_CCM_CCGR5_EMI_FAST_OFFSET 14 +#define MXC_CCM_CCGR5_EMI_FAST(v) (((v) & 0x3) << 14) +#define MXC_CCM_CCGR5_EMI_SLOW_OFFSET 16 +#define MXC_CCM_CCGR5_EMI_SLOW(v) (((v) & 0x3) << 16) +#define MXC_CCM_CCGR5_EMI_INT1_OFFSET 18 +#define MXC_CCM_CCGR5_EMI_INT1(v) (((v) & 0x3) << 18) +#define MXC_CCM_CCGR5_EMI_ENFC_OFFSET 20 +#define MXC_CCM_CCGR5_EMI_ENFC(v) (((v) & 0x3) << 20) +#define MXC_CCM_CCGR5_EMI_WRCK_OFFSET 22 +#define MXC_CCM_CCGR5_EMI_WRCK(v) (((v) & 0x3) << 22) +#define MXC_CCM_CCGR5_GPC_IPG_OFFSET 24 +#define MXC_CCM_CCGR5_GPC_IPG(v) (((v) & 0x3) << 24) +#define MXC_CCM_CCGR5_SPDIF0_OFFSET 26 +#define MXC_CCM_CCGR5_SPDIF0(v) (((v) & 0x3) << 26) +#if defined(CONFIG_MX51) +#define MXC_CCM_CCGR5_SPDIF1_OFFSET 28 +#define MXC_CCM_CCGR5_SPDIF1(v) (((v) & 0x3) << 28) +#endif +#define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET 30 +#define MXC_CCM_CCGR5_SPDIF_IPG(v) (((v) & 0x3) << 30) + +#if defined(CONFIG_MX53) +#define MXC_CCM_CCGR6_IPUMUX2_OFFSET 0 +#define MXC_CCM_CCGR6_IPUMUX2(v) (((v) & 0x3) << 0) +#define MXC_CCM_CCGR6_OCRAM_OFFSET 2 +#define MXC_CCM_CCGR6_OCRAM(v) (((v) & 0x3) << 2) +#endif +#define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET 4 +#define MXC_CCM_CCGR6_CSI_MCLK1(v) (((v) & 0x3) << 4) +#if defined(CONFIG_MX51) +#define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET 6 +#define MXC_CCM_CCGR6_CSI_MCLK2(v) (((v) & 0x3) << 6) +#define MXC_CCM_CCGR6_EMI_GARB_OFFSET 8 +#define MXC_CCM_CCGR6_EMI_GARB(v) (((v) & 0x3) << 8) +#elif defined(CONFIG_MX53) +#define MXC_CCM_CCGR6_EMI_INT2_OFFSET 8 +#define MXC_CCM_CCGR6_EMI_INT2(v) (((v) & 0x3) << 8) +#endif +#define MXC_CCM_CCGR6_IPU_DI0_OFFSET 10 +#define MXC_CCM_CCGR6_IPU_DI0(v) (((v) & 0x3) << 10) +#define MXC_CCM_CCGR6_IPU_DI1_OFFSET 12 +#define MXC_CCM_CCGR6_IPU_DI1(v) (((v) & 0x3) << 12) +#define MXC_CCM_CCGR6_GPU2D_OFFSET 14 +#define MXC_CCM_CCGR6_GPU2D(v) (((v) & 0x3) << 14) +#if defined(CONFIG_MX53) +#define MXC_CCM_CCGR6_ESAI_IPG_OFFSET 16 +#define MXC_CCM_CCGR6_ESAI_IPG(v) (((v) & 0x3) << 16) +#define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET 18 +#define MXC_CCM_CCGR6_ESAI_ROOT(v) (((v) & 0x3) << 18) +#define MXC_CCM_CCGR6_CAN1_IPG_OFFSET 20 +#define MXC_CCM_CCGR6_CAN1_IPG(v) (((v) & 0x3) << 20) +#define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET 22 +#define MXC_CCM_CCGR6_CAN1_SERIAL(v) (((v) & 0x3) << 22) +#define MXC_CCM_CCGR6_PL301_4X1_OFFSET 24 +#define MXC_CCM_CCGR6_PL301_4X1(v) (((v) & 0x3) << 24) +#define MXC_CCM_CCGR6_PL301_2X2_OFFSET 26 +#define MXC_CCM_CCGR6_PL301_2X2(v) (((v) & 0x3) << 26) +#define MXC_CCM_CCGR6_LDB_DI0_OFFSET 28 +#define MXC_CCM_CCGR6_LDB_DI0(v) (((v) & 0x3) << 28) +#define MXC_CCM_CCGR6_LDB_DI1_OFFSET 30 +#define MXC_CCM_CCGR6_LDB_DI1(v) (((v) & 0x3) << 30) + +#define MXC_CCM_CCGR7_ASRC_IPG_OFFSET 0 +#define MXC_CCM_CCGR7_ASRC_IPG(v) (((v) & 0x3) << 0) +#define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET 2 +#define MXC_CCM_CCGR7_ASRC_ASRCK(v) (((v) & 0x3) << 2) +#define MXC_CCM_CCGR7_MLB_OFFSET 4 +#define MXC_CCM_CCGR7_MLB(v) (((v) & 0x3) << 4) +#define MXC_CCM_CCGR7_IEEE1588_OFFSET 6 +#define MXC_CCM_CCGR7_IEEE1588(v) (((v) & 0x3) << 6) +#define MXC_CCM_CCGR7_UART4_IPG_OFFSET 8 +#define MXC_CCM_CCGR7_UART4_IPG(v) (((v) & 0x3) << 8) +#define MXC_CCM_CCGR7_UART4_PER_OFFSET 10 +#define MXC_CCM_CCGR7_UART4_PER(v) (((v) & 0x3) << 10) +#define MXC_CCM_CCGR7_UART5_IPG_OFFSET 12 +#define MXC_CCM_CCGR7_UART5_IPG(v) (((v) & 0x3) << 12) +#define MXC_CCM_CCGR7_UART5_PER_OFFSET 14 +#define MXC_CCM_CCGR7_UART5_PER(v) (((v) & 0x3) << 14) +#endif + +/* Define the bits in register CLPCR */ +#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) + +#define MXC_DPLLC_CTL_HFSM (1 << 7) +#define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12) + +#define MXC_DPLLC_OP_PDF_MASK 0xf +#define MXC_DPLLC_OP_MFI_OFFSET 4 +#define MXC_DPLLC_OP_MFI_MASK (0xf << 4) +#define MXC_DPLLC_OP_MFI(v) (((v) & 0xf) << 4) +#define MXC_DPLLC_OP_MFI_RD(r) (((r) >> 4) & 0xf) + +#define MXC_DPLLC_MFD_MFD_MASK 0x7ffffff + +#define MXC_DPLLC_MFN_MFN_MASK 0x7ffffff + +#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx5/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-mx5/gpio.h new file mode 100644 index 000000000..dad40bd3d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx5/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, + */ + + +#ifndef __ASM_ARCH_MX5_GPIO_H +#define __ASM_ARCH_MX5_GPIO_H + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx5/imx-regs.h b/roms/u-boot/arch/arm/include/asm/arch-mx5/imx-regs.h new file mode 100644 index 000000000..2731b7fb5 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -0,0 +1,526 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 Freescale Semiconductor, Inc. + */ + +#ifndef __ASM_ARCH_MX5_IMX_REGS_H__ +#define __ASM_ARCH_MX5_IMX_REGS_H__ + +#define ARCH_MXC + +#if defined(CONFIG_MX51) +#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ +#define IPU_SOC_BASE_ADDR 0x40000000 +#define IPU_SOC_OFFSET 0x1E000000 +#define SPBA0_BASE_ADDR 0x70000000 +#define AIPS1_BASE_ADDR 0x73F00000 +#define AIPS2_BASE_ADDR 0x83F00000 +#define CSD0_BASE_ADDR 0x90000000 +#define CSD1_BASE_ADDR 0xA0000000 +#define NFC_BASE_ADDR_AXI 0xCFFF0000 +#define CS1_BASE_ADDR 0xB8000000 +#elif defined(CONFIG_MX53) +#define IPU_SOC_BASE_ADDR 0x18000000 +#define IPU_SOC_OFFSET 0x06000000 +#define SPBA0_BASE_ADDR 0x50000000 +#define AIPS1_BASE_ADDR 0x53F00000 +#define AIPS2_BASE_ADDR 0x63F00000 +#define CSD0_BASE_ADDR 0x70000000 +#define CSD1_BASE_ADDR 0xB0000000 +#define NFC_BASE_ADDR_AXI 0xF7FF0000 +#define IRAM_BASE_ADDR 0xF8000000 +#define CS1_BASE_ADDR 0xF4000000 +#define SATA_BASE_ADDR 0x10000000 +#else +#error "CPU_TYPE not defined" +#endif + +#define IRAM_SIZE 0x00020000 /* 128 KB */ + +/* + * SPBA global module enabled #0 + */ +#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) +#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) +#define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000) +#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) +#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) +#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) +#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) +#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) +#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) +#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) +#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) +#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) + +/* + * AIPS 1 + */ +#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) +#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) +#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) +#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) +#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) +#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) +#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) +#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) +#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) +#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) +#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) +#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) +#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) +#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) +#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) +#define UART1_BASE (AIPS1_BASE_ADDR + 0x000BC000) +#define UART2_BASE (AIPS1_BASE_ADDR + 0x000C0000) +#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) +#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) +#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) + +#if defined(CONFIG_MX53) +#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) +#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) +#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) +#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000) +#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000) +#endif +/* + * AIPS 2 + */ +#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) +#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) +#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) +#ifdef CONFIG_MX53 +#define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000) +#endif +#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) +#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) +#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) +#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) +#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) +#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) +#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) +#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) +#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) +#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) +#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) +#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) +#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) +#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) +#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) +#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) +#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) +#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) +#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) +#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) +#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) +#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) +#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) +#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) +#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) +#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) +#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) +#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) +#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) + +#if defined(CONFIG_MX53) +#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) +#endif + +/* + * WEIM CSnGCR1 + */ +#define CSEN 1 +#define SWR (1 << 1) +#define SRD (1 << 2) +#define MUM (1 << 3) +#define WFL (1 << 4) +#define RFL (1 << 5) +#define CRE (1 << 6) +#define CREP (1 << 7) +#define BL(x) (((x) & 0x7) << 8) +#define WC (1 << 11) +#define BCD(x) (((x) & 0x3) << 12) +#define BCS(x) (((x) & 0x3) << 14) +#define DSZ(x) (((x) & 0x7) << 16) +#define SP (1 << 19) +#define CSREC(x) (((x) & 0x7) << 20) +#define AUS (1 << 23) +#define GBC(x) (((x) & 0x7) << 24) +#define WP (1 << 27) +#define PSZ(x) (((x) & 0x0f << 28) + +/* + * WEIM CSnGCR2 + */ +#define ADH(x) (((x) & 0x3)) +#define DAPS(x) (((x) & 0x0f << 4) +#define DAE (1 << 8) +#define DAP (1 << 9) +#define MUX16_BYP (1 << 12) + +/* + * WEIM CSnRCR1 + */ +#define RCSN(x) (((x) & 0x7)) +#define RCSA(x) (((x) & 0x7) << 4) +#define OEN(x) (((x) & 0x7) << 8) +#define OEA(x) (((x) & 0x7) << 12) +#define RADVN(x) (((x) & 0x7) << 16) +#define RAL (1 << 19) +#define RADVA(x) (((x) & 0x7) << 20) +#define RWSC(x) (((x) & 0x3f) << 24) + +/* + * WEIM CSnRCR2 + */ +#define RBEN(x) (((x) & 0x7)) +#define RBE (1 << 3) +#define RBEA(x) (((x) & 0x7) << 4) +#define RL(x) (((x) & 0x3) << 8) +#define PAT(x) (((x) & 0x7) << 12) +#define APR (1 << 15) + +/* + * WEIM CSnWCR1 + */ +#define WCSN(x) (((x) & 0x7)) +#define WCSA(x) (((x) & 0x7) << 3) +#define WEN(x) (((x) & 0x7) << 6) +#define WEA(x) (((x) & 0x7) << 9) +#define WBEN(x) (((x) & 0x7) << 12) +#define WBEA(x) (((x) & 0x7) << 15) +#define WADVN(x) (((x) & 0x7) << 18) +#define WADVA(x) (((x) & 0x7) << 21) +#define WWSC(x) (((x) & 0x3f) << 24) +#define WBED1 (1 << 30) +#define WAL (1 << 31) + +/* + * WEIM CSnWCR2 + */ +#define WBED 1 + +/* + * CSPI register definitions + */ +#define MXC_SPI_BASE_ADDRESSES \ + CSPI1_BASE_ADDR, \ + CSPI2_BASE_ADDR, \ + CSPI3_BASE_ADDR, + +/* + * Number of GPIO pins per port + */ +#define GPIO_NUM_PIN 32 + +#define IIM_SREV 0x24 +#define ROM_SI_REV 0x48 + +#define NFC_BUF_SIZE 0x1000 + +/* M4IF */ +#define M4IF_FBPM0 0x40 +#define M4IF_FIDBP 0x48 +#define M4IF_GENP_WEIM_MM_MASK 0x00000001 +#define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000 + +/* Assuming 24MHz input clock with doubler ON */ +/* MFI PDF */ +#define DP_OP_864 ((8 << 4) + ((1 - 1) << 0)) +#define DP_MFD_864 (180 - 1) /* PL Dither mode */ +#define DP_MFN_864 180 +#define DP_MFN_800_DIT 60 /* PL Dither mode */ + +#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) +#define DP_MFD_850 (48 - 1) +#define DP_MFN_850 41 + +#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) +#define DP_MFD_800 (3 - 1) +#define DP_MFN_800 1 + +#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) +#define DP_MFD_700 (24 - 1) +#define DP_MFN_700 7 + +#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) +#define DP_MFD_665 (96 - 1) +#define DP_MFN_665 89 + +#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) +#define DP_MFD_532 (24 - 1) +#define DP_MFN_532 13 + +#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) +#define DP_MFD_400 (3 - 1) +#define DP_MFN_400 1 + +#define DP_OP_455 ((9 << 4) + ((2 - 1) << 0)) +#define DP_MFD_455 (48 - 1) +#define DP_MFN_455 23 + +#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) +#define DP_MFD_216 (4 - 1) +#define DP_MFN_216 3 + +#define IMX_IIM_BASE (IIM_BASE_ADDR) + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include + +#define __REG(x) (*((volatile u32 *)(x))) +#define __REG16(x) (*((volatile u16 *)(x))) +#define __REG8(x) (*((volatile u8 *)(x))) + +struct clkctl { + u32 ccr; + u32 ccdr; + u32 csr; + u32 ccsr; + u32 cacrr; + u32 cbcdr; + u32 cbcmr; + u32 cscmr1; + u32 cscmr2; + u32 cscdr1; + u32 cs1cdr; + u32 cs2cdr; + u32 cdcdr; + u32 chsccdr; + u32 cscdr2; + u32 cscdr3; + u32 cscdr4; + u32 cwdr; + u32 cdhipr; + u32 cdcr; + u32 ctor; + u32 clpcr; + u32 cisr; + u32 cimr; + u32 ccosr; + u32 cgpr; + u32 ccgr0; + u32 ccgr1; + u32 ccgr2; + u32 ccgr3; + u32 ccgr4; + u32 ccgr5; + u32 ccgr6; +#if defined(CONFIG_MX53) + u32 ccgr7; +#endif + u32 cmeor; +}; + +/* DPLL registers */ +struct dpll { + u32 dp_ctl; + u32 dp_config; + u32 dp_op; + u32 dp_mfd; + u32 dp_mfn; + u32 dp_mfn_minus; + u32 dp_mfn_plus; + u32 dp_hfs_op; + u32 dp_hfs_mfd; + u32 dp_hfs_mfn; + u32 dp_mfn_togc; + u32 dp_destat; +}; +/* WEIM registers */ +struct weim { + u32 cs0gcr1; + u32 cs0gcr2; + u32 cs0rcr1; + u32 cs0rcr2; + u32 cs0wcr1; + u32 cs0wcr2; + u32 cs1gcr1; + u32 cs1gcr2; + u32 cs1rcr1; + u32 cs1rcr2; + u32 cs1wcr1; + u32 cs1wcr2; + u32 cs2gcr1; + u32 cs2gcr2; + u32 cs2rcr1; + u32 cs2rcr2; + u32 cs2wcr1; + u32 cs2wcr2; + u32 cs3gcr1; + u32 cs3gcr2; + u32 cs3rcr1; + u32 cs3rcr2; + u32 cs3wcr1; + u32 cs3wcr2; + u32 cs4gcr1; + u32 cs4gcr2; + u32 cs4rcr1; + u32 cs4rcr2; + u32 cs4wcr1; + u32 cs4wcr2; + u32 cs5gcr1; + u32 cs5gcr2; + u32 cs5rcr1; + u32 cs5rcr2; + u32 cs5wcr1; + u32 cs5wcr2; + u32 wcr; + u32 wiar; + u32 ear; +}; + +#if defined(CONFIG_MX51) +struct iomuxc { + u32 gpr[2]; + u32 omux0; + u32 omux1; + u32 omux2; + u32 omux3; + u32 omux4; +}; +#elif defined(CONFIG_MX53) +struct iomuxc { + u32 gpr[3]; + u32 omux0; + u32 omux1; + u32 omux2; + u32 omux3; + u32 omux4; +}; +#endif + +#define IOMUXC_GPR2_BITMAP_SPWG 0 +#define IOMUXC_GPR2_BITMAP_JEIDA 1 + +#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 +#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1 << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) +#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA << \ + IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) +#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG << \ + IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) + +#define IOMUXC_GPR2_DATA_WIDTH_18 0 +#define IOMUXC_GPR2_DATA_WIDTH_24 1 + +#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 +#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) +#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18 << \ + IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) +#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24 << \ + IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) + +#define IOMUXC_GPR2_MODE_DISABLED 0 +#define IOMUXC_GPR2_MODE_ENABLED_DI0 1 +#define IOMUXC_GPR2_MODE_ENABLED_DI1 3 + +#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 +#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) +#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED << \ + IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) +#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0 << \ + IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) +#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1 << \ + IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) + +/* System Reset Controller (SRC) */ +struct src { + u32 scr; + u32 sbmr; + u32 srsr; + u32 reserved1[2]; + u32 sisr; + u32 simr; +}; + +struct srtc_regs { + u32 lpscmr; /* 0x00 */ + u32 lpsclr; /* 0x04 */ + u32 lpsar; /* 0x08 */ + u32 lpsmcr; /* 0x0c */ + u32 lpcr; /* 0x10 */ + u32 lpsr; /* 0x14 */ + u32 lppdr; /* 0x18 */ + u32 lpgr; /* 0x1c */ + u32 hpcmr; /* 0x20 */ + u32 hpclr; /* 0x24 */ + u32 hpamr; /* 0x28 */ + u32 hpalr; /* 0x2c */ + u32 hpcr; /* 0x30 */ + u32 hpisr; /* 0x34 */ + u32 hpienr; /* 0x38 */ +}; + +struct iim_regs { + u32 stat; + u32 statm; + u32 err; + u32 emask; + u32 fctl; + u32 ua; + u32 la; + u32 sdat; + u32 prev; + u32 srev; + u32 prg_p; + u32 scs0; + u32 scs1; + u32 scs2; + u32 scs3; + u32 res0[0x1f1]; + struct fuse_bank { + u32 fuse_regs[0x20]; + u32 fuse_rsvd[0xe0]; +#if defined(CONFIG_MX51) + } bank[4]; +#elif defined(CONFIG_MX53) + } bank[5]; +#endif +}; + +struct fuse_bank0_regs { + u32 fuse0_7[8]; + u32 uid[8]; + u32 fuse16_23[8]; +#if defined(CONFIG_MX51) + u32 imei[8]; +#elif defined(CONFIG_MX53) + u32 gp[8]; +#endif +}; + +struct fuse_bank1_regs { + u32 fuse0_8[9]; + u32 mac_addr[6]; + u32 fuse15_31[0x11]; +}; + +#if defined(CONFIG_MX53) +struct fuse_bank4_regs { + u32 fuse0_4[5]; + u32 gp[3]; + u32 fuse8_31[0x18]; +}; +#endif + +#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) +#define PWMCR_DOZEEN (1 << 24) +#define PWMCR_WAITEN (1 << 23) +#define PWMCR_DBGEN (1 << 22) +#define PWMCR_CLKSRC_IPG_HIGH (2 << 16) +#define PWMCR_CLKSRC_IPG (1 << 16) +#define PWMCR_EN (1 << 0) + +struct pwm_regs { + u32 cr; + u32 sr; + u32 ir; + u32 sar; + u32 pr; + u32 cnr; +}; + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx51.h b/roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx51.h new file mode 100644 index 000000000..7f8a23848 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx51.h @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2009-2010 Amit Kucheria + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2009-2012 Genesi USA, Inc. + */ + +/* + * The vast majority of this file is taken from the Linux kernel at + * commit 5d23b39 + */ + +#ifndef __IOMUX_MX51_H__ +#define __IOMUX_MX51_H__ + +#include + +/* Pad control groupings */ +#define MX51_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \ + PAD_CTL_HYS | PAD_CTL_SRE_FAST) +#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_HYS) +#define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_HYS) +#define MX51_USBH_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) +#define MX51_ECSPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_HYS | \ + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) +#define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SRE_FAST | PAD_CTL_DVS) +#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST) + +#define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS) +#define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS) +#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) + +/* + * The naming convention for the pad modes is MX51_PAD___ + * If or refers to a GPIO, it is named GPIO_ + * See also iomux-v3.h + */ + +/* PAD MUX ALT INPSE PATH PADCTRL */ +enum { + MX51_PAD_EIM_D16__USBH2_DATA0 = IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_EIM_D17__GPIO2_1 = IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_EIM_D17__USBH2_DATA1 = IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_EIM_D18__USBH2_DATA2 = IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_EIM_D19__USBH2_DATA3 = IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_EIM_D20__USBH2_DATA4 = IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_EIM_D21__GPIO2_5 = IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_EIM_D21__USBH2_DATA5 = IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_EIM_D22__USBH2_DATA6 = IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_EIM_D23__USBH2_DATA7 = IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL), + MX51_PAD_EIM_D26__UART3_TXD = IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL), + MX51_PAD_EIM_D27__GPIO2_9 = IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_EIM_A16__GPIO2_10 = IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_EIM_A17__GPIO2_11 = IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_EIM_A20__GPIO2_14 = IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_EIM_A22__GPIO2_16 = IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_EIM_A24__USBH2_CLK = IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_EIM_A25__USBH2_DIR = IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_EIM_A26__GPIO2_20 = IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_EIM_A26__USBH2_STP = IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_EIM_A27__USBH2_NXT = IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_EIM_EB2__FEC_MDIO = IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, PAD_CTL_PUS_22K_UP | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_HYS), + MX51_PAD_EIM_EB3__FEC_RDATA1 = IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL), + MX51_PAD_EIM_EB3__GPIO2_23 = IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_EIM_CS0__GPIO2_25 = IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_EIM_CS2__FEC_RDATA2 = IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL), + MX51_PAD_EIM_CS2__GPIO2_27 = IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_EIM_CS3__FEC_RDATA3 = IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL), + MX51_PAD_EIM_CS3__GPIO2_28 = IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_EIM_CS4__FEC_RX_ER = IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2), + MX51_PAD_EIM_CS4__GPIO2_29 = IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_EIM_CS5__FEC_CRS = IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2), + MX51_PAD_DRAM_RAS__DRAM_RAS = IOMUX_PAD(0x4a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DRAM_CAS__DRAM_CAS = IOMUX_PAD(0x4a8, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DRAM_SDWE__DRAM_SDWE = IOMUX_PAD(0x4ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0 = IOMUX_PAD(0x4b0, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1 = IOMUX_PAD(0x4b4, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DRAM_SDCLK__DRAM_SDCLK = IOMUX_PAD(0x4b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DRAM_SDQS0__DRAM_SDQS0 = IOMUX_PAD(0x4bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DRAM_SDQS1__DRAM_SDQS1 = IOMUX_PAD(0x4c0, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DRAM_SDQS2__DRAM_SDQS2 = IOMUX_PAD(0x4c4, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DRAM_SDQS3__DRAM_SDQS3 = IOMUX_PAD(0x4c8, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DRAM_CS0__DRAM_CS0 = IOMUX_PAD(0x4cc, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DRAM_CS1__DRAM_CS1 = IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DRAM_DQM0__DRAM_DQM0 = IOMUX_PAD(0x4d4, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DRAM_DQM1__DRAM_DQM1 = IOMUX_PAD(0x4d8, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DRAM_DQM2__DRAM_DQM2 = IOMUX_PAD(0x4dc, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DRAM_DQM3__DRAM_DQM3 = IOMUX_PAD(0x4e0, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_WE_B__PATA_DIOW = IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_RE_B__PATA_DIOR = IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_ALE__PATA_BUFFER_EN = IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_CLE__PATA_RESET_B = IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_WP_B__PATA_DMACK = IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_RB0__PATA_DMARQ = IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_RB1__PATA_IORDY = IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_RB2__FEC_COL = IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2), + MX51_PAD_NANDF_RB2__GPIO3_10 = IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_NANDF_RB3__FEC_RX_CLK = IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2), + MX51_PAD_NANDF_RB3__GPIO3_11 = IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_GPIO_NAND__PATA_INTRQ = IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_CS2__FEC_TX_ER = IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5), + MX51_PAD_NANDF_CS2__PATA_CS_0 = IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_CS3__FEC_MDC = IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5), + MX51_PAD_NANDF_CS3__PATA_CS_1 = IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_CS4__FEC_TDATA1 = IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5), + MX51_PAD_NANDF_CS4__PATA_DA_0 = IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_CS5__FEC_TDATA2 = IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5), + MX51_PAD_NANDF_CS5__PATA_DA_1 = IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_CS6__FEC_TDATA3 = IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5), + MX51_PAD_NANDF_CS6__PATA_DA_2 = IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_CS7__FEC_TX_EN = IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5), + MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK = IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4), + MX51_PAD_NANDF_D15__GPIO3_25 = IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_NANDF_D15__PATA_DATA15 = IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_D14__GPIO3_26 = IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_NANDF_D14__PATA_DATA14 = IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_D13__GPIO3_27 = IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_NANDF_D13__PATA_DATA13 = IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_D12__PATA_DATA12 = IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_D11__FEC_RX_DV = IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_D11__PATA_DATA11 = IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_D10__GPIO3_30 = IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_NANDF_D10__PATA_DATA10 = IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_D9__FEC_RDATA0 = IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4), + MX51_PAD_NANDF_D9__GPIO3_31 = IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_NANDF_D9__PATA_DATA9 = IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_D8__FEC_TDATA0 = IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5), + MX51_PAD_NANDF_D8__PATA_DATA8 = IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_D7__PATA_DATA7 = IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_D6__PATA_DATA6 = IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_D5__PATA_DATA5 = IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_D4__PATA_DATA4 = IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_D3__PATA_DATA3 = IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_D2__PATA_DATA2 = IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_D1__PATA_DATA1 = IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_D0__PATA_DATA0 = IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_CSI2_D12__GPIO4_9 = IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_CSI2_D13__GPIO4_10 = IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), + MX51_PAD_CSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), + MX51_PAD_CSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), + MX51_PAD_CSPI1_SS0__GPIO4_24 = IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_CSPI1_SS1__ECSPI1_SS1 = IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), + MX51_PAD_CSPI1_SS1__GPIO4_25 = IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_CSPI1_RDY__ECSPI1_RDY = IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), + MX51_PAD_CSPI1_RDY__GPIO4_26 = IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), + MX51_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL), + MX51_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL), + MX51_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL), + MX51_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL), + MX51_PAD_USBH1_CLK__USBH1_CLK = IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_USBH1_DIR__USBH1_DIR = IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_USBH1_STP__GPIO1_27 = IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_USBH1_STP__USBH1_STP = IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_USBH1_NXT__USBH1_NXT = IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_USBH1_DATA0__USBH1_DATA0 = IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_USBH1_DATA1__USBH1_DATA1 = IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_USBH1_DATA2__USBH1_DATA2 = IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_USBH1_DATA3__USBH1_DATA3 = IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_USBH1_DATA4__USBH1_DATA4 = IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_USBH1_DATA5__USBH1_DATA5 = IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_USBH1_DATA6__USBH1_DATA6 = IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_USBH1_DATA7__USBH1_DATA7 = IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH_PAD_CTRL), + MX51_PAD_DI1_PIN11__ECSPI1_SS2 = IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL), + MX51_PAD_DI1_PIN12__GPIO3_1 = IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL), + MX51_PAD_DI1_PIN13__GPIO3_2 = IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL), + MX51_PAD_DI1_D0_CS__GPIO3_3 = IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL), + MX51_PAD_DI1_D1_CS__GPIO3_4 = IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL), + MX51_PAD_DISPB2_SER_DIN__GPIO3_5 = IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL), + MX51_PAD_DISPB2_SER_DIO__GPIO3_6 = IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL), + MX51_PAD_DI1_PIN3__DI1_PIN3 = IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DI1_PIN2__DI1_PIN2 = IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DI2_PIN2__FEC_MDC = IOMUX_PAD(0x74C, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5), + MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK = IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DI_GP4__DI2_PIN15 = IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP2_DAT6__FEC_TDAT1 = IOMUX_PAD(0x774, 0x36C, 2, __NA_, 0, MX51_PAD_CTRL_5), + MX51_PAD_DISP2_DAT7__FEC_TDAT2 = IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5), + MX51_PAD_DISP2_DAT8__FEC_TDAT3 = IOMUX_PAD(0x77C, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5), + MX51_PAD_DISP2_DAT9__FEC_TX_EN = IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5), + MX51_PAD_DISP2_DAT10__FEC_COL = IOMUX_PAD(0x784, 0x37C, 2, 0x94c, 0x1, MX51_PAD_CTRL_2), + MX51_PAD_DISP2_DAT11__FEC_RXCLK = IOMUX_PAD(0x788, 0x380, 2, 0x968, 0x1, MX51_PAD_CTRL_2), + MX51_PAD_DISP2_DAT12__FEC_RX_DV = IOMUX_PAD(0x78C, 0x384, 2, 0x96c, 0x1, MX51_PAD_CTRL_4), + MX51_PAD_DISP2_DAT13__FEC_TX_CLK = IOMUX_PAD(0x790, 0x388, 2, 0x974, 0x1, MX51_PAD_CTRL_4), + MX51_PAD_DISP2_DAT14__FEC_RDAT0 = IOMUX_PAD(0x794, 0x38C, 2, 0x958, 0x1, MX51_PAD_CTRL_4), + MX51_PAD_DISP2_DAT15__FEC_TDAT0 = IOMUX_PAD(0x798, 0x390, 2, 0x0, 0, MX51_PAD_CTRL_5), + MX51_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), + MX51_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS), + MX51_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), + MX51_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), + MX51_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), + MX51_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), + MX51_PAD_GPIO1_0__GPIO1_0 = IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_GPIO1_0__SD1_CD = IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL), + MX51_PAD_GPIO1_1__SD1_WP = IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL), + MX51_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), + MX51_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS), + MX51_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), + MX51_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), + MX51_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), + MX51_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), + MX51_PAD_GPIO1_2__GPIO1_2 = IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_GPIO1_2__PWM1_PWMO = IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_GPIO1_3__GPIO1_3 = IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_GPIO1_5__GPIO1_5 = IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_GPIO1_6__GPIO1_6 = IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_GPIO1_7__GPIO1_7 = IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_GPIO1_7__SD2_WP = IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL), + MX51_PAD_GPIO1_8__SD2_CD = IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL), + MX51_GRP_DDRPKS = IOMUX_PAD(0x820, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_DRAM_B4 = IOMUX_PAD(0x82c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_PKEDDR = IOMUX_PAD(0x838, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_DDR_A0 = IOMUX_PAD(0x83c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_DDR_A1 = IOMUX_PAD(0x848, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_DDRAPUS = IOMUX_PAD(0x84c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_HYSDDR0 = IOMUX_PAD(0x85c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_HYSDDR1 = IOMUX_PAD(0x864, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_HYSDDR2 = IOMUX_PAD(0x86c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_HYSDDR3 = IOMUX_PAD(0x874, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_DRAM_SR_B0 = IOMUX_PAD(0x878, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_DDRAPKS = IOMUX_PAD(0x87c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_DRAM_SR_B1 = IOMUX_PAD(0x880, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_DDRPUS = IOMUX_PAD(0x884, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_DRAM_SR_B2 = IOMUX_PAD(0x88c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_PKEADDR = IOMUX_PAD(0x890, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_DRAM_SR_B4 = IOMUX_PAD(0x89c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_INMODE1 = IOMUX_PAD(0x8a0, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_DRAM_B0 = IOMUX_PAD(0x8a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_DRAM_B1 = IOMUX_PAD(0x8ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_DRAM_B2 = IOMUX_PAD(0x8b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL), + MX51_GRP_DDR_SR_A1 = IOMUX_PAD(0x8bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL), +}; + +#endif /* __IOMUX_MX51_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx53.h b/roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx53.h new file mode 100644 index 000000000..cbc08b0a2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx53.h @@ -0,0 +1,1215 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 ADVANSEE + * Benoît Thébaudeau + * + * Based on Freescale's Linux i.MX iomux-mx53.h file: + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __IOMUX_MX53_H__ +#define __IOMUX_MX53_H__ + +#include + +/* Pad control groupings */ +#define MX53_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) + +/* + * The naming convention for the pad modes is MX53_PAD___ + * If refers to a GPIO, it is named GPIO_ + * If refers to a GPIO, it is named GPIO_ + * See also iomux-v3.h + */ + +/* PAD MUX ALT INPSE PATH PADCTRL */ +enum { + MX53_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_19__GPIO4_5 = IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 = IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_19__FEC_TDATA_3 = IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL0__GPIO4_6 = IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL0__UART4_TXD_MUX = IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL0__FEC_RDATA_3 = IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW0__GPIO4_7 = IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW0__UART4_RXD_MUX = IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL), + MX53_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW0__FEC_TX_ER = IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL1__GPIO4_8 = IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL1__UART5_TXD_MUX = IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL1__FEC_RX_CLK = IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL1__USBPHY1_TXREADY = IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW1__GPIO4_9 = IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW1__UART5_RXD_MUX = IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL), + MX53_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW1__FEC_COL = IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW1__USBPHY1_RXVALID = IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL2__GPIO4_10 = IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL2__FEC_MDIO = IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL2__FEC_RDATA_2 = IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE = IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW2__GPIO4_11 = IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW2__FEC_MDC = IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW2__FEC_TDATA_2 = IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW2__USBPHY1_RXERROR = IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL3__GPIO4_12 = IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL3__USBOH3_H2_DP = IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL3__FEC_CRS = IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK = IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW3__GPIO4_13 = IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW3__USBOH3_H2_DM = IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK = IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW3__CCM_PLL4_BYP = IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 = IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL4__GPIO4_14 = IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL4__IPU_SISG_4 = IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL), + MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL), + MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 = IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW4__GPIO4_15 = IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW4__IPU_SISG_5 = IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID = IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK = IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_DISP_CLK__GPIO4_16 = IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR = IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 = IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 = IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID = IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 = IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN15__GPIO4_17 = IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 = IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 = IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN15__USBPHY1_BVALID = IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 = IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN2__GPIO4_18 = IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 = IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 = IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION = IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 = IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN3__GPIO4_19 = IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 = IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 = IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN3__USBPHY1_IDDIG = IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 = IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN4__GPIO4_20 = IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN4__ESDHC1_WP = IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 = IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT = IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 = IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT0__GPIO4_21 = IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT0__CSPI_SCLK = IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 = IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN = IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 = IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY = IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 = IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT1__GPIO4_22 = IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT1__CSPI_MOSI = IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 = IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL + = IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 = IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID = IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 = IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT2__GPIO4_23 = IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT2__CSPI_MISO = IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 = IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 = IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE = IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 = IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT3__GPIO4_24 = IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT3__CSPI_SS0 = IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 = IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 = IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR = IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 = IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT4__GPIO4_25 = IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT4__CSPI_SS1 = IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 = IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 = IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK = IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 = IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT5__GPIO4_26 = IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT5__CSPI_SS2 = IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 = IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 = IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 = IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 = IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT6__GPIO4_27 = IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT6__CSPI_SS3 = IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 = IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 = IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 = IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 = IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT7__GPIO4_28 = IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT7__CSPI_RDY = IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 = IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 = IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID = IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 = IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT8__GPIO4_29 = IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 = IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT8__USBPHY2_AVALID = IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 = IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT9__GPIO4_30 = IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 = IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 = IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 = IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT10__GPIO4_31 = IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP = IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 + = IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 = IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 = IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 = IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT11__GPIO5_5 = IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT = IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 + = IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 = IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 = IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 = IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT12__GPIO5_6 = IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK = IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 + = IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 = IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 = IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 = IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT13__GPIO5_7 = IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 + = IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 = IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 = IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 = IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT14__GPIO5_8 = IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 + = IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 = IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 = IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 = IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT15__GPIO5_9 = IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 + = IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 = IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 = IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 = IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT16__GPIO5_10 = IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 + = IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 = IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 = IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 = IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT17__GPIO5_11 = IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 + = IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 = IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 = IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT18__GPIO5_12 = IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 + = IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 = IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 = IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 = IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT19__GPIO5_13 = IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 + = IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 = IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 = IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 = IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT20__GPIO5_14 = IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 + = IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 = IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT20__SATA_PHY_TDI = IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 = IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT21__GPIO5_15 = IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 = IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT21__SATA_PHY_TDO = IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 = IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT22__GPIO5_16 = IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 = IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT22__SATA_PHY_TCK = IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 = IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT23__GPIO5_17 = IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 = IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_DISP0_DAT23__SATA_PHY_TMS = IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK = IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_PIXCLK__GPIO5_18 = IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 = IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC = IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_MCLK__GPIO5_19 = IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK = IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 = IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_MCLK__TPIU_TRCTL = IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN = IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DATA_EN__GPIO5_20 = IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 = IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK = IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC = IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_VSYNC__GPIO5_21 = IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 = IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 = IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 = IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT4__GPIO5_22 = IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP = IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 = IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 = IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 = IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT5__GPIO5_23 = IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT5__KPP_ROW_5 = IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT = IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 = IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 = IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 = IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT6__GPIO5_24 = IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT6__KPP_COL_6 = IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK = IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 = IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 = IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 = IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT7__GPIO5_25 = IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT7__KPP_ROW_6 = IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR = IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 = IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 = IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 = IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT8__GPIO5_26 = IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT8__KPP_COL_7 = IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC = IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 = IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 = IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 = IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT9__GPIO5_27 = IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT9__KPP_ROW_7 = IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR = IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 = IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 = IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 = IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT10__GPIO5_28 = IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT10__UART1_TXD_MUX = IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 = IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 = IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 = IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT11__GPIO5_29 = IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT11__UART1_RXD_MUX = IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL), + MX53_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 = IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 = IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 = IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT12__GPIO5_30 = IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT12__UART4_TXD_MUX = IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 = IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 = IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 = IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 = IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT13__GPIO5_31 = IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT13__UART4_RXD_MUX = IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL), + MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 = IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 = IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 = IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 = IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT14__GPIO6_0 = IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT14__UART5_TXD_MUX = IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 = IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 = IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 = IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 = IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT15__GPIO6_1 = IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT15__UART5_RXD_MUX = IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL), + MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 = IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 = IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 = IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 = IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT16__GPIO6_2 = IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL), + MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 = IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 = IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 = IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 = IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT17__GPIO6_3 = IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 = IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 = IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 = IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 = IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT18__GPIO6_4 = IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL), + MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 = IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 = IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 = IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 = IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT19__GPIO6_5 = IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 = IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 = IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK = IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A25__EMI_WEIM_A_25 = IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A25__GPIO5_2 = IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A25__IPU_DI1_PIN12 = IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A25__CSPI_SS1 = IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL), + MX53_PAD_EIM_A25__IPU_DI0_D1_CS = IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A25__USBPHY1_BISTOK = IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 = IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB2__GPIO2_30 = IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS = IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL), + MX53_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL), + MX53_PAD_EIM_D16__EMI_WEIM_D_16 = IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D16__GPIO3_16 = IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D16__IPU_DI0_PIN5 = IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK = IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL), + MX53_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL), + MX53_PAD_EIM_D17__EMI_WEIM_D_17 = IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D17__GPIO3_17 = IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D17__IPU_DI0_PIN6 = IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN = IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL), + MX53_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D18__EMI_WEIM_D_18 = IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D18__GPIO3_18 = IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D18__IPU_DI0_PIN7 = IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO = IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL), + MX53_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL), + MX53_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D18__IPU_DI1_D0_CS = IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D19__EMI_WEIM_D_19 = IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D19__GPIO3_19 = IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D19__IPU_DI0_PIN8 = IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS = IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL), + MX53_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_EIM_D19__USBOH3_USBH2_OC = IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D20__EMI_WEIM_D_20 = IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D20__GPIO3_20 = IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D20__IPU_DI0_PIN16 = IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D20__IPU_SER_DISP0_CS = IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D20__CSPI_SS0 = IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL), + MX53_PAD_EIM_D20__EPIT2_EPITO = IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D20__UART1_RTS = IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL), + MX53_PAD_EIM_D20__USBOH3_USBH2_PWR = IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D21__EMI_WEIM_D_21 = IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D21__GPIO3_21 = IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D21__IPU_DI0_PIN17 = IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK = IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D21__CSPI_SCLK = IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL), + MX53_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL), + MX53_PAD_EIM_D21__USBOH3_USBOTG_OC = IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL), + MX53_PAD_EIM_D22__EMI_WEIM_D_22 = IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D22__GPIO3_22 = IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D22__IPU_DI0_PIN1 = IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN = IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D22__CSPI_MISO = IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL), + MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D23__EMI_WEIM_D_23 = IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D23__GPIO3_23 = IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_EIM_D23__UART1_DCD = IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D23__IPU_DI0_D0_CS = IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D23__IPU_DI1_PIN2 = IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN = IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D23__IPU_DI1_PIN14 = IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 = IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB3__GPIO2_31 = IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB3__UART3_RTS = IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL), + MX53_PAD_EIM_EB3__UART1_RI = IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB3__IPU_DI1_PIN3 = IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC = IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB3__IPU_DI1_PIN16 = IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D24__EMI_WEIM_D_24 = IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D24__GPIO3_24 = IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D24__UART3_TXD_MUX = IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL), + MX53_PAD_EIM_D24__CSPI_SS2 = IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL), + MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL), + MX53_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D25__EMI_WEIM_D_25 = IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D25__GPIO3_25 = IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D25__UART3_RXD_MUX = IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL), + MX53_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL), + MX53_PAD_EIM_D25__CSPI_SS3 = IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL), + MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC = IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL), + MX53_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D25__UART1_DSR = IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D26__EMI_WEIM_D_26 = IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D26__GPIO3_26 = IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D26__UART2_TXD_MUX = IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_EIM_D26__FIRI_RXD = IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D26__IPU_CSI0_D_1 = IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D26__IPU_DI1_PIN11 = IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D26__IPU_SISG_2 = IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 = IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D27__EMI_WEIM_D_27 = IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D27__GPIO3_27 = IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D27__UART2_RXD_MUX = IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL), + MX53_PAD_EIM_D27__FIRI_TXD = IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D27__IPU_CSI0_D_0 = IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D27__IPU_DI1_PIN13 = IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D27__IPU_SISG_3 = IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 = IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D28__EMI_WEIM_D_28 = IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D28__GPIO3_28 = IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D28__UART2_CTS = IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO = IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL), + MX53_PAD_EIM_D28__CSPI_MOSI = IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL), + MX53_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL), + MX53_PAD_EIM_D28__IPU_EXT_TRIG = IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D28__IPU_DI0_PIN13 = IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D29__EMI_WEIM_D_29 = IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D29__GPIO3_29 = IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D29__UART2_RTS = IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL), + MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS = IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D29__CSPI_SS0 = IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL), + MX53_PAD_EIM_D29__IPU_DI1_PIN15 = IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D29__IPU_CSI1_VSYNC = IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D29__IPU_DI0_PIN14 = IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D30__EMI_WEIM_D_30 = IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D30__GPIO3_30 = IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_EIM_D30__IPU_CSI0_D_3 = IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D30__IPU_DI0_PIN11 = IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 = IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D30__USBOH3_USBH2_OC = IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL), + MX53_PAD_EIM_D31__EMI_WEIM_D_31 = IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D31__GPIO3_31 = IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL), + MX53_PAD_EIM_D31__IPU_CSI0_D_2 = IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D31__IPU_DI0_PIN12 = IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 = IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_D31__USBOH3_USBH2_PWR = IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A24__EMI_WEIM_A_24 = IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A24__GPIO5_4 = IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 = IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A24__IPU_CSI1_D_19 = IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A24__IPU_SISG_2 = IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A24__USBPHY2_BVALID = IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A23__EMI_WEIM_A_23 = IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A23__GPIO6_6 = IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 = IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A23__IPU_CSI1_D_18 = IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A23__IPU_SISG_3 = IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A23__USBPHY2_ENDSESSION = IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A22__EMI_WEIM_A_22 = IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A22__GPIO2_16 = IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 = IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A22__IPU_CSI1_D_17 = IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A22__SRC_BT_CFG1_7 = IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A21__EMI_WEIM_A_21 = IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A21__GPIO2_17 = IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 = IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A21__IPU_CSI1_D_16 = IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A21__SRC_BT_CFG1_6 = IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A20__EMI_WEIM_A_20 = IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A20__GPIO2_18 = IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 = IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A20__IPU_CSI1_D_15 = IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A20__SRC_BT_CFG1_5 = IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A19__EMI_WEIM_A_19 = IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A19__GPIO2_19 = IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 = IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A19__IPU_CSI1_D_14 = IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A19__SRC_BT_CFG1_4 = IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A18__EMI_WEIM_A_18 = IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A18__GPIO2_20 = IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 = IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A18__IPU_CSI1_D_13 = IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A18__SRC_BT_CFG1_3 = IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A17__EMI_WEIM_A_17 = IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A17__GPIO2_21 = IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 = IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A17__IPU_CSI1_D_12 = IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A17__SRC_BT_CFG1_2 = IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A16__EMI_WEIM_A_16 = IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A16__GPIO2_22 = IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK = IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK = IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_A16__SRC_BT_CFG1_1 = IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 = IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_CS0__GPIO2_23 = IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL), + MX53_PAD_EIM_CS0__IPU_DI1_PIN5 = IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 = IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_CS1__GPIO2_24 = IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL), + MX53_PAD_EIM_CS1__IPU_DI1_PIN6 = IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_OE__EMI_WEIM_OE = IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_OE__GPIO2_25 = IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL), + MX53_PAD_EIM_OE__IPU_DI1_PIN7 = IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_OE__USBPHY2_IDDIG = IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_RW__EMI_WEIM_RW = IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_RW__GPIO2_26 = IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL), + MX53_PAD_EIM_RW__IPU_DI1_PIN8 = IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT = IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_LBA__EMI_WEIM_LBA = IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_LBA__GPIO2_27 = IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL), + MX53_PAD_EIM_LBA__IPU_DI1_PIN17 = IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 = IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 = IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB0__GPIO2_28 = IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 = IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB0__IPU_CSI1_D_11 = IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB0__GPC_PMIC_RDY = IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 = IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 = IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB1__GPIO2_29 = IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 = IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB1__IPU_CSI1_D_10 = IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 = IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 = IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA0__GPIO3_0 = IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 = IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA0__IPU_CSI1_D_9 = IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 = IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 = IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA1__GPIO3_1 = IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 = IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA1__IPU_CSI1_D_8 = IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 = IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 = IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA2__GPIO3_2 = IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 = IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA2__IPU_CSI1_D_7 = IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 = IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 = IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA3__GPIO3_3 = IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 = IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA3__IPU_CSI1_D_6 = IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 = IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 = IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA4__GPIO3_4 = IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 = IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA4__IPU_CSI1_D_5 = IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 = IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 = IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA5__GPIO3_5 = IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 = IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA5__IPU_CSI1_D_4 = IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 = IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 = IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA6__GPIO3_6 = IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 = IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA6__IPU_CSI1_D_3 = IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 = IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 = IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA7__GPIO3_7 = IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 = IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA7__IPU_CSI1_D_2 = IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 = IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 = IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA8__GPIO3_8 = IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 = IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA8__IPU_CSI1_D_1 = IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 = IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 = IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA9__GPIO3_9 = IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 = IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA9__IPU_CSI1_D_0 = IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 = IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 = IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA10__GPIO3_10 = IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA10__IPU_DI1_PIN15 = IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN = IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL), + MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 = IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 = IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA11__GPIO3_11 = IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA11__IPU_DI1_PIN2 = IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC = IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL), + MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 = IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA12__GPIO3_12 = IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA12__IPU_DI1_PIN3 = IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC = IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL), + MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 = IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA13__GPIO3_13 = IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA13__IPU_DI1_D0_CS = IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL), + MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 = IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA14__GPIO3_14 = IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA14__IPU_DI1_D1_CS = IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 = IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA15__GPIO3_15 = IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA15__IPU_DI1_PIN1 = IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_DA15__IPU_DI1_PIN4 = IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B = IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_WE_B__GPIO6_12 = IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B = IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_RE_B__GPIO6_13 = IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT = IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_WAIT__GPIO5_0 = IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B = IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS1_TX3_P__GPIO6_22 = IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 = IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS1_TX2_P__GPIO6_24 = IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 = IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS1_CLK_P__GPIO6_26 = IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK = IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS1_TX1_P__GPIO6_28 = IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 = IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS1_TX0_P__GPIO6_30 = IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 = IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS0_TX3_P__GPIO7_22 = IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 = IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS0_CLK_P__GPIO7_24 = IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS0_TX2_P__GPIO7_26 = IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 = IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS0_TX1_P__GPIO7_28 = IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS0_TX0_P__GPIO7_30 = IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_10__GPIO4_0 = IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_10__OSC32k_32K_OUT = IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_11__GPIO4_1 = IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_12__GPIO4_2 = IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_13__GPIO4_3 = IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_14__GPIO4_4 = IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE = IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CLE__GPIO6_7 = IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 = IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE = IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_ALE__GPIO6_8 = IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 = IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B = IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_WP_B__GPIO6_9 = IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 = IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 = IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_RB0__GPIO6_10 = IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 = IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 = IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS0__GPIO6_11 = IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 = IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 = IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS1__GPIO6_14 = IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS1__MLB_MLBCLK = IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 = IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 = IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS2__GPIO6_15 = IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS2__IPU_SISG_0 = IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS2__EMI_WEIM_CRE = IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK = IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS2__MLB_MLBSIG = IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 = IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 = IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS3__GPIO6_16 = IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS3__IPU_SISG_1 = IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS3__ESAI1_TX1 = IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 = IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS3__MLB_MLBDAT = IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL), + MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 = IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL), + MX53_PAD_FEC_MDIO__GPIO1_22 = IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_MDIO__ESAI1_SCKR = IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL), + MX53_PAD_FEC_MDIO__FEC_COL = IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL), + MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 = IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 = IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK = IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_REF_CLK__GPIO1_23 = IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL), + MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 = IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 = IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_RX_ER__FEC_RX_ER = IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_RX_ER__GPIO1_24 = IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL), + MX53_PAD_FEC_RX_ER__FEC_RX_CLK = IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL), + MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 = IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_CRS_DV__FEC_RX_DV = IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_CRS_DV__GPIO1_25 = IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL), + MX53_PAD_FEC_RXD1__FEC_RDATA_1 = IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_RXD1__GPIO1_26 = IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_RXD1__ESAI1_FST = IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL), + MX53_PAD_FEC_RXD1__MLB_MLBSIG = IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL), + MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 = IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_RXD0__FEC_RDATA_0 = IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_RXD0__GPIO1_27 = IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_RXD0__ESAI1_HCKT = IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL), + MX53_PAD_FEC_RXD0__OSC32k_32K_OUT = IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_TX_EN__GPIO1_28 = IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 = IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL), + MX53_PAD_FEC_TXD1__FEC_TDATA_1 = IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_TXD1__GPIO1_29 = IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 = IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL), + MX53_PAD_FEC_TXD1__MLB_MLBCLK = IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL), + MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK = IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_TXD0__FEC_TDATA_0 = IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_TXD0__GPIO1_30 = IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 = IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL), + MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 = IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_MDC__GPIO1_31 = IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 = IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL), + MX53_PAD_FEC_MDC__MLB_MLBDAT = IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL), + MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG = IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 = IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DIOW__PATA_DIOW = IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DIOW__GPIO6_17 = IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DIOW__UART1_TXD_MUX = IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 = IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DMACK__PATA_DMACK = IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DMACK__GPIO6_18 = IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DMACK__UART1_RXD_MUX = IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL), + MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 = IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DMARQ__PATA_DMARQ = IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DMARQ__GPIO7_0 = IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX = IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 = IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 = IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN = IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_BUFFER_EN__GPIO7_1 = IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX = IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL), + MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 = IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 = IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_INTRQ__PATA_INTRQ = IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_INTRQ__GPIO7_2 = IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_INTRQ__UART2_CTS = IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_PATA_INTRQ__CAN1_TXCAN = IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 = IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 = IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DIOR__PATA_DIOR = IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DIOR__GPIO7_3 = IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DIOR__UART2_RTS = IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL), + MX53_PAD_PATA_DIOR__CAN1_RXCAN = IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL), + MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 = IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B = IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_RESET_B__GPIO7_4 = IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_RESET_B__ESDHC3_CMD = IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_RESET_B__UART1_CTS = IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_PATA_RESET_B__CAN2_TXCAN = IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 = IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_IORDY__PATA_IORDY = IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_IORDY__GPIO7_5 = IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_IORDY__ESDHC3_CLK = IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_IORDY__UART1_RTS = IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL), + MX53_PAD_PATA_IORDY__CAN2_RXCAN = IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL), + MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 = IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DA_0__PATA_DA_0 = IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DA_0__GPIO7_6 = IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DA_0__ESDHC3_RST = IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DA_0__OWIRE_LINE = IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 = IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DA_1__PATA_DA_1 = IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DA_1__GPIO7_7 = IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DA_1__ESDHC4_CMD = IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DA_1__UART3_CTS = IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 = IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DA_2__PATA_DA_2 = IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DA_2__GPIO7_8 = IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DA_2__ESDHC4_CLK = IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DA_2__UART3_RTS = IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL), + MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 = IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_CS_0__PATA_CS_0 = IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_CS_0__GPIO7_9 = IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_CS_0__UART3_TXD_MUX = IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 = IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_CS_1__PATA_CS_1 = IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_CS_1__GPIO7_10 = IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_CS_1__UART3_RXD_MUX = IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL), + MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 = IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA0__PATA_DATA_0 = IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA0__GPIO2_0 = IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 = IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA0__ESDHC3_DAT4 = IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 = IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 = IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 = IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA1__PATA_DATA_1 = IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA1__GPIO2_1 = IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 = IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA1__ESDHC3_DAT5 = IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 = IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 = IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA2__PATA_DATA_2 = IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA2__GPIO2_2 = IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 = IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA2__ESDHC3_DAT6 = IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 = IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 = IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA3__PATA_DATA_3 = IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA3__GPIO2_3 = IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 = IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA3__ESDHC3_DAT7 = IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 = IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 = IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA4__PATA_DATA_4 = IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA4__GPIO2_4 = IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 = IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA4__ESDHC4_DAT4 = IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 = IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 = IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA5__PATA_DATA_5 = IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA5__GPIO2_5 = IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 = IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA5__ESDHC4_DAT5 = IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 = IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 = IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA6__PATA_DATA_6 = IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA6__GPIO2_6 = IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 = IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA6__ESDHC4_DAT6 = IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 = IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 = IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA7__PATA_DATA_7 = IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA7__GPIO2_7 = IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 = IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA7__ESDHC4_DAT7 = IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 = IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 = IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA8__PATA_DATA_8 = IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA8__GPIO2_8 = IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA8__ESDHC1_DAT4 = IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 = IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA8__ESDHC3_DAT0 = IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 = IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 = IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA9__PATA_DATA_9 = IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA9__GPIO2_9 = IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA9__ESDHC1_DAT5 = IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 = IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA9__ESDHC3_DAT1 = IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 = IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 = IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA10__PATA_DATA_10 = IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA10__GPIO2_10 = IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA10__ESDHC1_DAT6 = IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 = IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA10__ESDHC3_DAT2 = IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 = IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 = IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA11__PATA_DATA_11 = IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA11__GPIO2_11 = IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA11__ESDHC1_DAT7 = IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 = IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA11__ESDHC3_DAT3 = IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 = IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 = IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA12__PATA_DATA_12 = IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA12__GPIO2_12 = IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA12__ESDHC2_DAT4 = IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 = IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA12__ESDHC4_DAT0 = IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 = IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 = IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA13__PATA_DATA_13 = IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA13__GPIO2_13 = IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA13__ESDHC2_DAT5 = IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 = IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA13__ESDHC4_DAT1 = IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 = IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 = IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA14__PATA_DATA_14 = IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA14__GPIO2_14 = IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA14__ESDHC2_DAT6 = IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 = IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA14__ESDHC4_DAT2 = IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 = IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 = IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA15__PATA_DATA_15 = IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA15__GPIO2_15 = IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA15__ESDHC2_DAT7 = IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 = IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA15__ESDHC4_DAT3 = IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 = IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 = IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 = IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_SD1_DATA0__GPIO1_16 = IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_DATA0__GPT_CAPIN1 = IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_DATA0__CSPI_MISO = IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL), + MX53_PAD_SD1_DATA0__CCM_PLL3_BYP = IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL), + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 = IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_SD1_DATA1__GPIO1_17 = IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_DATA1__GPT_CAPIN2 = IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_DATA1__CSPI_SS0 = IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL), + MX53_PAD_SD1_DATA1__CCM_PLL4_BYP = IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL), + MX53_PAD_SD1_CMD__ESDHC1_CMD = IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_SD1_CMD__GPIO1_18 = IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_CMD__GPT_CMPOUT1 = IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_CMD__CSPI_MOSI = IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL), + MX53_PAD_SD1_CMD__CCM_PLL1_BYP = IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL), + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 = IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_SD1_DATA2__GPIO1_19 = IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_DATA2__GPT_CMPOUT2 = IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_DATA2__PWM2_PWMO = IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_DATA2__WDOG1_WDOG_B = IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_DATA2__CSPI_SS1 = IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL), + MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_DATA2__CCM_PLL2_BYP = IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL), + MX53_PAD_SD1_CLK__ESDHC1_CLK = IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_SD1_CLK__GPIO1_20 = IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_CLK__OSC32k_32K_OUT = IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_CLK__CSPI_SCLK = IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL), + MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 = IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 = IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_SD1_DATA3__GPIO1_21 = IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_DATA3__GPT_CMPOUT3 = IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_DATA3__PWM1_PWMO = IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_DATA3__WDOG2_WDOG_B = IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_DATA3__CSPI_SS2 = IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL), + MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 = IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD2_CLK__ESDHC2_CLK = IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_SD2_CLK__GPIO1_10 = IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL), + MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL), + MX53_PAD_SD2_CLK__CSPI_SCLK = IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL), + MX53_PAD_SD2_CLK__SCC_RANDOM_V = IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD2_CMD__ESDHC2_CMD = IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_SD2_CMD__GPIO1_11 = IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL), + MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL), + MX53_PAD_SD2_CMD__CSPI_MOSI = IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL), + MX53_PAD_SD2_CMD__SCC_RANDOM = IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD2_DATA3__ESDHC2_DAT3 = IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_SD2_DATA3__GPIO1_12 = IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD2_DATA3__KPP_COL_6 = IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL), + MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC = IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL), + MX53_PAD_SD2_DATA3__CSPI_SS2 = IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL), + MX53_PAD_SD2_DATA3__SJC_DONE = IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD2_DATA2__ESDHC2_DAT2 = IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_SD2_DATA2__GPIO1_13 = IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD2_DATA2__KPP_ROW_6 = IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL), + MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD = IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL), + MX53_PAD_SD2_DATA2__CSPI_SS1 = IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL), + MX53_PAD_SD2_DATA2__SJC_FAIL = IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD2_DATA1__ESDHC2_DAT1 = IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_SD2_DATA1__GPIO1_14 = IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD2_DATA1__KPP_COL_7 = IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL), + MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL), + MX53_PAD_SD2_DATA1__CSPI_SS0 = IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL), + MX53_PAD_SD2_DATA1__RTIC_SEC_VIO = IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD2_DATA0__ESDHC2_DAT0 = IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), + MX53_PAD_SD2_DATA0__GPIO1_15 = IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_SD2_DATA0__KPP_ROW_7 = IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL), + MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL), + MX53_PAD_SD2_DATA0__CSPI_MISO = IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL), + MX53_PAD_SD2_DATA0__RTIC_DONE_INT = IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_0__GPIO1_0 = IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL), + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK = IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_0__SRTC_ALARM_DEB = IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_0__CSU_TD = IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_1__GPIO1_1 = IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL), + MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK = IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_1__ESDHC1_CD = IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_9__ESAI1_FSR = IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_9__GPIO1_9 = IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_9__KPP_COL_6 = IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL), + MX53_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_9__PWM1_PWMO = IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_9__WDOG1_WDOG_B = IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_9__ESDHC1_WP = IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_9__SCC_FAIL_STATE = IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_3__GPIO1_3 = IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_3__DPLLIP1_TOG_EN = IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 = IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL), + MX53_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_6__GPIO1_6 = IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 = IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_6__ESDHC2_LCTL = IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL), + MX53_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_2__GPIO1_2 = IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL), + MX53_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 = IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_2__ESDHC2_WP = IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL), + MX53_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_4__GPIO1_4 = IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL), + MX53_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 = IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_4__ESDHC2_CD = IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_4__SCC_SEC_STATE = IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_5__GPIO1_5 = IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL), + MX53_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 = IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL), + MX53_PAD_GPIO_5__CCM_PLL1_BYP = IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_7__GPIO1_7 = IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_7__UART2_TXD_MUX = IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL), + MX53_PAD_GPIO_7__FIRI_RXD = IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_7__CCM_PLL2_BYP = IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_8__GPIO1_8 = IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, NO_PAD_CTRL), + MX53_PAD_GPIO_8__UART2_RXD_MUX = IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL), + MX53_PAD_GPIO_8__FIRI_TXD = IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_8__CCM_PLL3_BYP = IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_16__GPIO7_11 = IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT = IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 = IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL), + MX53_PAD_GPIO_16__SJC_DE_B = IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_17__ESAI1_TX0 = IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_17__GPIO7_12 = IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_17__GPC_PMIC_RDY = IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG = IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_17__SPDIF_OUT1 = IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_17__IPU_SNOOP2 = IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_18__ESAI1_TX1 = IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_18__GPIO7_13 = IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_18__OWIRE_LINE = IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG = IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK = IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL), + MX53_PAD_GPIO_18__ESDHC1_LCTL = IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL), + MX53_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL), +}; + +#endif /* __IOMUX_MX53_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx5/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-mx5/sys_proto.h new file mode 100644 index 000000000..c8aff2b65 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + */ +#ifndef __SYS_PROTO_IMX5_ +#define __SYS_PROTO_IMX5_ + +#include + +#endif /* __SYS_PROTO_IMX5_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/clock.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/clock.h new file mode 100644 index 000000000..8ae497157 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/clock.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +#include + +#ifdef CONFIG_SYS_MX6_HCLK +#define MXC_HCLK CONFIG_SYS_MX6_HCLK +#else +#define MXC_HCLK 24000000 +#endif + +#ifdef CONFIG_SYS_MX6_CLK32 +#define MXC_CLK32 CONFIG_SYS_MX6_CLK32 +#else +#define MXC_CLK32 32768 +#endif + +struct cmd_tbl; + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_PER_CLK, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_IPG_PERCLK, + MXC_UART_CLK, + MXC_CSPI_CLK, + MXC_AXI_CLK, + MXC_EMI_SLOW_CLK, + MXC_DDR_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, + MXC_ESDHC4_CLK, + MXC_SATA_CLK, + MXC_NFC_CLK, + MXC_I2C_CLK, +}; + +enum ldb_di_clock { + MXC_PLL5_CLK = 0, + MXC_PLL2_PFD0_CLK, + MXC_PLL2_PFD2_CLK, + MXC_MMDC_CH1_CLK, + MXC_PLL3_SW_CLK, +}; + +enum enet_freq { + ENET_25MHZ, + ENET_50MHZ, + ENET_100MHZ, + ENET_125MHZ, +}; + +u32 imx_get_uartclk(void); +u32 imx_get_fecclk(void); +unsigned int mxc_get_clock(enum mxc_clock clk); +void setup_gpmi_io_clk(u32 cfg); +void hab_caam_clock_enable(unsigned char enable); +void enable_ocotp_clk(unsigned char enable); +void enable_usboh3_clk(unsigned char enable); +void enable_uart_clk(unsigned char enable); +int enable_usdhc_clk(unsigned char enable, unsigned bus_num); +int enable_sata_clock(void); +void disable_sata_clock(void); +int enable_pcie_clock(void); +int enable_i2c_clk(unsigned char enable, unsigned i2c_num); +int enable_spi_clk(unsigned char enable, unsigned spi_num); +void enable_ipu_clock(void); +void disable_ipu_clock(void); +int enable_fec_anatop_clock(int fec_id, enum enet_freq freq); +void enable_enet_clk(unsigned char enable); +int enable_lcdif_clock(u32 base_addr, bool enable); +void enable_qspi_clk(int qspi_num); +void enable_thermal_clk(void); +void mxs_set_lcdclk(u32 base_addr, u32 freq); +void select_ldb_di_clock_source(enum ldb_di_clock clk); +void enable_eim_clk(unsigned char enable); +int do_mx6_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]); +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/crm_regs.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/crm_regs.h new file mode 100644 index 000000000..4174f244a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -0,0 +1,1309 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ +#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ + +#define CCM_CCOSR 0x020c4060 +#define CCM_CCGR0 0x020C4068 +#define CCM_CCGR1 0x020C406c +#define CCM_CCGR2 0x020C4070 +#define CCM_CCGR3 0x020C4074 +#define CCM_CCGR4 0x020C4078 +#define CCM_CCGR5 0x020C407c +#define CCM_CCGR6 0x020C4080 + +#define PMU_MISC2 0x020C8170 + +#ifndef __ASSEMBLY__ +struct mxc_ccm_reg { + u32 ccr; /* 0x0000 */ + u32 ccdr; + u32 csr; + u32 ccsr; + u32 cacrr; /* 0x0010*/ + u32 cbcdr; + u32 cbcmr; + u32 cscmr1; + u32 cscmr2; /* 0x0020 */ + u32 cscdr1; + u32 cs1cdr; + u32 cs2cdr; + u32 cdcdr; /* 0x0030 */ + u32 chsccdr; + u32 cscdr2; + u32 cscdr3; + u32 cscdr4; /* 0x0040 */ + u32 resv0; + u32 cdhipr; + u32 cdcr; + u32 ctor; /* 0x0050 */ + u32 clpcr; + u32 cisr; + u32 cimr; + u32 ccosr; /* 0x0060 */ + u32 cgpr; + u32 CCGR0; + u32 CCGR1; + u32 CCGR2; /* 0x0070 */ + u32 CCGR3; + u32 CCGR4; + u32 CCGR5; + u32 CCGR6; /* 0x0080 */ + u32 CCGR7; + u32 cmeor; + u32 resv[0xfdd]; + u32 analog_pll_sys; /* 0x4000 */ + u32 analog_pll_sys_set; + u32 analog_pll_sys_clr; + u32 analog_pll_sys_tog; + u32 analog_usb1_pll_480_ctrl; /* 0x4010 */ + u32 analog_usb1_pll_480_ctrl_set; + u32 analog_usb1_pll_480_ctrl_clr; + u32 analog_usb1_pll_480_ctrl_tog; + u32 analog_reserved0[4]; + u32 analog_pll_528; /* 0x4030 */ + u32 analog_pll_528_set; + u32 analog_pll_528_clr; + u32 analog_pll_528_tog; + u32 analog_pll_528_ss; /* 0x4040 */ + u32 analog_reserved1[3]; + u32 analog_pll_528_num; /* 0x4050 */ + u32 analog_reserved2[3]; + u32 analog_pll_528_denom; /* 0x4060 */ + u32 analog_reserved3[3]; + u32 analog_pll_audio; /* 0x4070 */ + u32 analog_pll_audio_set; + u32 analog_pll_audio_clr; + u32 analog_pll_audio_tog; + u32 analog_pll_audio_num; /* 0x4080*/ + u32 analog_reserved4[3]; + u32 analog_pll_audio_denom; /* 0x4090 */ + u32 analog_reserved5[3]; + u32 analog_pll_video; /* 0x40a0 */ + u32 analog_pll_video_set; + u32 analog_pll_video_clr; + u32 analog_pll_video_tog; + u32 analog_pll_video_num; /* 0x40b0 */ + u32 analog_reserved6[3]; + u32 analog_pll_video_denom; /* 0x40c0 */ + u32 analog_reserved7[7]; + u32 analog_pll_enet; /* 0x40e0 */ + u32 analog_pll_enet_set; + u32 analog_pll_enet_clr; + u32 analog_pll_enet_tog; + u32 analog_pfd_480; /* 0x40f0 */ + u32 analog_pfd_480_set; + u32 analog_pfd_480_clr; + u32 analog_pfd_480_tog; + u32 analog_pfd_528; /* 0x4100 */ + u32 analog_pfd_528_set; + u32 analog_pfd_528_clr; + u32 analog_pfd_528_tog; + /* PMU Memory Map/Register Definition */ + u32 pmu_reg_1p1; + u32 pmu_reg_1p1_set; + u32 pmu_reg_1p1_clr; + u32 pmu_reg_1p1_tog; + u32 pmu_reg_3p0; + u32 pmu_reg_3p0_set; + u32 pmu_reg_3p0_clr; + u32 pmu_reg_3p0_tog; + u32 pmu_reg_2p5; + u32 pmu_reg_2p5_set; + u32 pmu_reg_2p5_clr; + u32 pmu_reg_2p5_tog; + u32 pmu_reg_core; + u32 pmu_reg_core_set; + u32 pmu_reg_core_clr; + u32 pmu_reg_core_tog; + u32 pmu_misc0; + u32 pmu_misc0_set; + u32 pmu_misc0_clr; + u32 pmu_misc0_tog; + u32 pmu_misc1; + u32 pmu_misc1_set; + u32 pmu_misc1_clr; + u32 pmu_misc1_tog; + u32 pmu_misc2; + u32 pmu_misc2_set; + u32 pmu_misc2_clr; + u32 pmu_misc2_tog; + /* TEMPMON Memory Map/Register Definition */ + u32 tempsense0; + u32 tempsense0_set; + u32 tempsense0_clr; + u32 tempsense0_tog; + u32 tempsense1; + u32 tempsense1_set; + u32 tempsense1_clr; + u32 tempsense1_tog; + /* USB Analog Memory Map/Register Definition */ + u32 usb1_vbus_detect; + u32 usb1_vbus_detect_set; + u32 usb1_vbus_detect_clr; + u32 usb1_vbus_detect_tog; + u32 usb1_chrg_detect; + u32 usb1_chrg_detect_set; + u32 usb1_chrg_detect_clr; + u32 usb1_chrg_detect_tog; + u32 usb1_vbus_det_stat; + u32 usb1_vbus_det_stat_set; + u32 usb1_vbus_det_stat_clr; + u32 usb1_vbus_det_stat_tog; + u32 usb1_chrg_det_stat; + u32 usb1_chrg_det_stat_set; + u32 usb1_chrg_det_stat_clr; + u32 usb1_chrg_det_stat_tog; + u32 usb1_loopback; + u32 usb1_loopback_set; + u32 usb1_loopback_clr; + u32 usb1_loopback_tog; + u32 usb1_misc; + u32 usb1_misc_set; + u32 usb1_misc_clr; + u32 usb1_misc_tog; + u32 usb2_vbus_detect; + u32 usb2_vbus_detect_set; + u32 usb2_vbus_detect_clr; + u32 usb2_vbus_detect_tog; + u32 usb2_chrg_detect; + u32 usb2_chrg_detect_set; + u32 usb2_chrg_detect_clr; + u32 usb2_chrg_detect_tog; + u32 usb2_vbus_det_stat; + u32 usb2_vbus_det_stat_set; + u32 usb2_vbus_det_stat_clr; + u32 usb2_vbus_det_stat_tog; + u32 usb2_chrg_det_stat; + u32 usb2_chrg_det_stat_set; + u32 usb2_chrg_det_stat_clr; + u32 usb2_chrg_det_stat_tog; + u32 usb2_loopback; + u32 usb2_loopback_set; + u32 usb2_loopback_clr; + u32 usb2_loopback_tog; + u32 usb2_misc; + u32 usb2_misc_set; + u32 usb2_misc_clr; + u32 usb2_misc_tog; + u32 digprog; + u32 reserved1[7]; + /* For i.MX 6SoloLite */ + u32 digprog_sololite; +}; +#endif + +/* Define the bits in register CCR */ +#define MXC_CCM_CCR_RBC_EN (1 << 27) +#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) +#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 +/* CCR_WB does not exist on i.MX6SX/UL */ +#define MXC_CCM_CCR_WB_COUNT_MASK 0x7 +#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) +#define MXC_CCM_CCR_COSC_EN (1 << 12) +#ifdef CONFIG_MX6SX +#define MXC_CCM_CCR_OSCNT_MASK 0x7F +#else +#define MXC_CCM_CCR_OSCNT_MASK 0xFF +#endif +#define MXC_CCM_CCR_OSCNT_OFFSET 0 + +/* Define the bits in register CCDR */ +#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) +#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) +/* Exists on i.MX6QP */ +#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18) + +/* Define the bits in register CSR */ +#define MXC_CCM_CSR_COSC_READY (1 << 5) +#define MXC_CCM_CSR_REF_EN_B (1 << 0) + +/* Define the bits in register CCSR */ +#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15) +#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14) +#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13) +#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12) +#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11) +#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10) +#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9) +#define MXC_CCM_CCSR_STEP_SEL (1 << 8) +#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) +#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) +#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) + +/* Define the bits in register CACRR */ +#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 +#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 + +/* Define the bits in register CBCDR */ +#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) +#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 +#define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26) +#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) +/* MMDC_CH0 not exists on i.MX6SX */ +#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) +#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 +#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) +#define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 +#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) +#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 +#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) +#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 +#define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) +#define MXC_CCM_CBCDR_AXI_SEL (1 << 6) +#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) +#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 +#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) +#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0 + +/* Define the bits in register CBCMR */ +#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) +#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 +#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) +#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 +/* LCDIF on i.MX6SX/UL */ +#define MXC_CCM_CBCMR_LCDIF1_PODF_MASK (0x7 << 23) +#define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET 23 +#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) +#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 +#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) +#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 +#define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20) +#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) +#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 +#ifndef CONFIG_MX6SX +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 +#endif +#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) +#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 +#ifndef CONFIG_MX6SX +#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) +#endif +#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) +#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 +#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 +/* Exists on i.MX6QP */ +#define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1) + +/* Define the bits in register CSCMR1 */ +#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) +#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 +/* QSPI1 exist on i.MX6SX/UL */ +#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26) +#define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26 +#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) +#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 +#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) +#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 +/* LCFIF2_PODF on i.MX6SX */ +#define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK (0x7 << 20) +#define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET 20 +/* LCDIF_PIX_PODF on i.MX6SL */ +#define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK (0x7 << 20) +#define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET 20 +/* ACLK_EMI on i.MX6DQ/SDL/DQP */ +#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) +#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 +/* CSCMR1_GPMI/BCH exist on i.MX6UL */ +#define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19) +#define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18) +#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) +#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) +#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) +#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) +#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 +/* QSPI1 exist on i.MX6SX/UL */ +#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7) +#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7 +/* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */ +#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6) +#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6 + +#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F + +/* Define the bits in register CSCMR2 */ +#ifdef CONFIG_MX6SX +#define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21) +#define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21 +#endif +#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) +#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 +#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) +#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) +/* CSCMR1_CAN_CLK exists on i.MX6SX/QP */ +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8 + +#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2) +#define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2 + +/* Define the bits in register CSCDR1 */ +#ifndef CONFIG_MX6SX +#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) +#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 +#endif +/* CSCDR1_GPMI/BCH exist on i.MX6UL */ +#define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22 +#define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19 + +#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 +#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19 +#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) +#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 +#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 +#ifndef CONFIG_MX6SX +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) +#endif +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F +#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 +/* UART_CLK_SEL exists on i.MX6SL/SX/QP */ +#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) + +/* Define the bits in register CS1CDR */ +/* MX6UL, !MX6ULL */ +#define MXC_CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CS1CDR_SAI3_CLK_PRED_OFFSET 22 +#define MXC_CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS1CDR_SAI3_CLK_PODF_OFFSET 16 +#define MXC_CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS1CDR_SAI1_CLK_PRED_OFFSET 6 +#define MXC_CCM_CS1CDR_SAI1_CLK_PODF_MASK 0x3F +#define MXC_CCM_CS1CDR_SAI1_CLK_PODF_OFFSET 0 + +#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) +#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 +#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22 +#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 +#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) +#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9 +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6 +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 + +/* Define the bits in register CS2CDR */ +/* QSPI2 on i.MX6SX */ +#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21) +#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21 +#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21) +#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18) +#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18 +#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18) +#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15) +#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15 +#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15) + +#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) +#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 +#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21) +#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) +#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 +#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) + +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15 +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16 +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16) + +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \ + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \ + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \ + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)) + +#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) +#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 +#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) +#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9 +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6 +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 + +/* Define the bits in register CDCDR */ +#ifndef CONFIG_MX6SX +#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) +#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 +#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) +#endif +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22 +#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12 +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9 +#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) +#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 + +/* Define the bits in register CHSCCDR */ +/* i.MX6SX */ +#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15) +#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15 +#define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12) +#define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12 +#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9) +#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9 +#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6) +#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6 +#define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3) +#define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3 +#define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7) +#define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0 + +#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) +#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 +#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) +#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 +#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) +#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 +#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) +#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 +#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) +#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 +#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) +#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 + +/* i.MX6ULL */ +#define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK (0x7 << 15) +#define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET 15 +#define MXC_CCM_CHSCCDR_EPDC_PODF_MASK (0x7 << 12) +#define MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET 12 +#define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK (0x7 << 9) +#define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_OFFSET 9 + +#define CHSCCDR_CLK_SEL_LDB_DI0 3 +#define CHSCCDR_PODF_DIVIDE_BY_3 2 +#define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 + +/* Define the bits in register CSCDR2 */ +#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 +/* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */ +#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18) +/* LCDIF1 on i.MX6SX/UL */ +#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK (0x7 << 15) +#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET 15 +#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK (0x7 << 12) +#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET 12 +#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0x7 << 9) +#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET 9 +/* LCDIF2 on i.MX6SX */ +#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK (0x7 << 6) +#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET 6 +#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK (0x7 << 3) +#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET 3 +#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK (0x7 << 0) +#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET 0 + +/*LCD on i.MX6SL */ +#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK (0x7 << 6) +#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET 6 +#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK (0x7 << 3) +#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET 3 + +/* All IPU2_DI1 are LCDIF1 on MX6SX */ +#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) +#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 +#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) +#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 +#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) +#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 +/* All IPU2_DI0 are LCDIF2 on MX6SX */ +#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) +#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 +#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) +#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3 +#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7 +#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0 + +/* Define the bits in register CSCDR3 */ +#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) +#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16 +#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14 +#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11 +#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) +#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 + +/* For i.MX6SL */ +#define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_MASK (0x7 << 16) +#define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_OFFSET 16 +#define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET 14 + +/* Define the bits in register CDHIPR */ +#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) +#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) +#ifndef CONFIG_MX6SX +#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) +#endif +#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) +#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) +#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) +#define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 + +/* Define the bits in register CLPCR */ +#define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) +#define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) +#ifndef CONFIG_MX6SX +#define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) +#define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) +#define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) +#endif +#define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) +#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) +#ifndef CONFIG_MX6SX +#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) +#define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) +#endif +#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16) +#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) +#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) +#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 +#define MXC_CCM_CLPCR_VSTBY (1 << 8) +#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) +#define MXC_CCM_CLPCR_SBYOS (1 << 6) +#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) +#ifndef CONFIG_MX6SX +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 +#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) +#endif +#define MXC_CCM_CLPCR_LPM_MASK 0x3 +#define MXC_CCM_CLPCR_LPM_OFFSET 0 + +/* Define the bits in register CISR */ +#define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) +#ifndef CONFIG_MX6SX +#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) +#endif +#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) +#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) +#define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) +#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) +#define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) +#define MXC_CCM_CISR_COSC_READY (1 << 6) +#define MXC_CCM_CISR_LRF_PLL 1 + +/* Define the bits in register CIMR */ +#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) +#ifndef CONFIG_MX6SX +#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) +#endif +#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) +#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) +#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) +#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) +#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) +#define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) +#define MXC_CCM_CIMR_MASK_LRF_PLL 1 + +/* Define the bits in register CCOSR */ +#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) +#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) +#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 +#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 +#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) +#define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8) +#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) +#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) +#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 +#define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF +#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 + +/* Define the bits in registers CGPR */ +#define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16) +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) +#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) +#define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 + +/* Define the bits in registers CCGRx */ +#define MXC_CCM_CCGR_CG_MASK 3 + +/* i.MX 6ULL */ +#define MXC_CCM_CCGR0_DCP_CLK_OFFSET 10 +#define MXC_CCM_CCGR0_DCP_CLK_MASK (3 << MXC_CCM_CCGR0_DCP_CLK_OFFSET) +#define MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET 12 +#define MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET) + +#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0 +#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET) +#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2 +#define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET) +#define MXC_CCM_CCGR0_APBHDMA_OFFSET 4 +#define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET) +#define MXC_CCM_CCGR0_ASRC_OFFSET 6 +#define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET) +#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8 +#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET) +#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10 +#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET) +#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12 +#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET) +#define MXC_CCM_CCGR0_CAN1_OFFSET 14 +#define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET) +#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16 +#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET) +#define MXC_CCM_CCGR0_CAN2_OFFSET 18 +#define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET) +#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20 +#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET) +#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22 +#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET) +#define MXC_CCM_CCGR0_DCIC1_OFFSET 24 +#define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET) +#define MXC_CCM_CCGR0_DCIC2_OFFSET 26 +#define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET) +#ifdef CONFIG_MX6SX +#define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30 +#define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET) +#else +#define MXC_CCM_CCGR0_DTCP_OFFSET 28 +#define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET) +#endif + +#define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0 +#define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET) +#define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2 +#define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET) +#define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4 +#define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET) +#define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6 +#define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET) +#define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8 +#define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET) +/* CCGR1_ENET does not exist on i.MX6SX/UL */ +#define MXC_CCM_CCGR1_ENET_OFFSET 10 +#define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET) +#define MXC_CCM_CCGR1_EPIT1S_OFFSET 12 +#define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET) +#define MXC_CCM_CCGR1_EPIT2S_OFFSET 14 +#define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET) +#define MXC_CCM_CCGR1_ESAIS_OFFSET 16 +#define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET) +#ifdef CONFIG_MX6SX +#define MXC_CCM_CCGR1_WAKEUP_OFFSET 18 +#define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET) +#endif +#define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20 +#define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET) +#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22 +#define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET) +#ifndef CONFIG_MX6SX +#define MXC_CCM_CCGR1_GPU2D_OFFSET 24 +#define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET) +#endif +#define MXC_CCM_CCGR1_GPU3D_OFFSET 26 +#define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET) +#ifdef CONFIG_MX6SX +#define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28 +#define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET) +#define MXC_CCM_CCGR1_CANFD_OFFSET 30 +#define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET) +#endif + +#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0 +#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) +/* i.MX6SX/UL */ +#define MXC_CCM_CCGR2_CSI_OFFSET 2 +#define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET) + +#ifndef CONFIG_MX6SX +#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4 +#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) +#endif +#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6 +#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET) +#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8 +#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET) +#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10 +#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET) +#define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8 +#define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET) +#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12 +#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET) +#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14 +#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET) +#define MXC_CCM_CCGR2_IPMUX1_OFFSET 16 +#define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET) +#define MXC_CCM_CCGR2_IPMUX2_OFFSET 18 +#define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET) +#define MXC_CCM_CCGR2_IPMUX3_OFFSET 20 +#define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET) +#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 +#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) +/* i.MX6SX/UL LCD and PXP */ +#define MXC_CCM_CCGR2_LCD_OFFSET 28 +#define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET) +#define MXC_CCM_CCGR2_PXP_OFFSET 30 +#define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET) + +#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24 +#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) +#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 +#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) + +/* i.MX6ULL */ +#define MXC_CCM_CCGR2_ESAI_CLK_OFFSET 0 +#define MXC_CCM_CCGR2_ESAI_CLK_MASK (3 << MXC_CCM_CCGR2_ESAI_CLK_OFFSET) +#define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET 4 +#define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_MASK (3 << MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET) + +/* Exist on i.MX6SX */ +#define MXC_CCM_CCGR3_M4_OFFSET 2 +#define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET) +/* i.MX6ULL */ +#define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET 4 +#define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET) +#define MXC_CCM_CCGR3_ENET_OFFSET 4 +#define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET) +#define MXC_CCM_CCGR3_QSPI_OFFSET 14 +#define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET) + +/* i.MX6SL */ +#define MXC_CCM_CCGR3_LCDIF_AXI_OFFSET 6 +#define MXC_CCM_CCGR3_LCDIF_AXI_MASK (3 << MXC_CCM_CCGR3_LCDIF_AXI_OFFSET) +#define MXC_CCM_CCGR3_LCDIF_PIX_OFFSET 8 +#define MXC_CCM_CCGR3_LCDIF_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF_PIX_OFFSET) + +#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 +#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET) +#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 +#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) +#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4 +#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET) + +#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6 +#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET) +#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8 +#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET) +#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10 +#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET) +#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12 +#define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET) + +/* QSPI1 exists on i.MX6SX/UL */ +#define MXC_CCM_CCGR3_QSPI1_OFFSET 14 +#define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET) + +#define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14 +#define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET) +#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16 +#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET) + +/* A7_CLKDIV/WDOG1 on i.MX6UL */ +#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16 +#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET) +#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18 +#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET) + +#define MXC_CCM_CCGR3_MLB_OFFSET 18 +#define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET) +#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20 +#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET) +#ifndef CONFIG_MX6SX +#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22 +#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET) +#endif +#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24 +#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) +#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 +#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) + +#define MXC_CCM_CCGR3_DISP_AXI_OFFSET 6 +#define MXC_CCM_CCGR3_DISP_AXI_MASK (3 << MXC_CCM_CCGR3_DISP_AXI_OFFSET) +#define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET 8 +#define MXC_CCM_CCGR3_LCDIF2_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET) +#define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET 10 +#define MXC_CCM_CCGR3_LCDIF1_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET) +/* AXI on i.MX6UL */ +#define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28 +#define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET) +#define MXC_CCM_CCGR3_OCRAM_OFFSET 28 +#define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET) + +/* GPIO4 on i.MX6UL/ULL */ +#define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30 +#define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET) + +#ifndef CONFIG_MX6SX +#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30 +#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) +#endif + +/* i.MX6ULL */ +#define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET 30 +#define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_MASK (3 << MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET) + +#define MXC_CCM_CCGR4_PCIE_OFFSET 0 +#define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET) +/* QSPI2 on i.MX6SX */ +#define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10 +#define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET) +#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8 +#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET) +#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12 +#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET) +#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14 +#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET) +#define MXC_CCM_CCGR4_PWM1_OFFSET 16 +#define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET) +#define MXC_CCM_CCGR4_PWM2_OFFSET 18 +#define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET) +#define MXC_CCM_CCGR4_PWM3_OFFSET 20 +#define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET) +#define MXC_CCM_CCGR4_PWM4_OFFSET 22 +#define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET) +#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24 +#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET) +#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26 +#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET) +#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28 +#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET) +#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30 +#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET) + +#define MXC_CCM_CCGR5_ROM_OFFSET 0 +#define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET) +#ifndef CONFIG_MX6SX +#define MXC_CCM_CCGR5_SATA_OFFSET 4 +#define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET) +#endif +#define MXC_CCM_CCGR5_SDMA_OFFSET 6 +#define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET) +#define MXC_CCM_CCGR5_SPBA_OFFSET 12 +#define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET) +#define MXC_CCM_CCGR5_SPDIF_OFFSET 14 +#define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET) +#define MXC_CCM_CCGR5_SSI1_OFFSET 18 +#define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET) +#define MXC_CCM_CCGR5_SSI2_OFFSET 20 +#define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET) +#define MXC_CCM_CCGR5_SSI3_OFFSET 22 +#define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET) +#define MXC_CCM_CCGR5_UART_OFFSET 24 +#define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET) +#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26 +#define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET) +#ifdef CONFIG_MX6SX +#define MXC_CCM_CCGR5_SAI1_OFFSET 20 +#define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET) +#define MXC_CCM_CCGR5_SAI2_OFFSET 30 +#define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET) +#endif + +/* PRG_CLK0 exists on i.MX6QP */ +#define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << 24) + +#define MXC_CCM_CCGR6_USBOH3_OFFSET 0 +#define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET) +#define MXC_CCM_CCGR6_USDHC1_OFFSET 2 +#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET) +#define MXC_CCM_CCGR6_USDHC2_OFFSET 4 +#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET) +#define MXC_CCM_CCGR6_SIM1_CLK_OFFSET 6 +#define MXC_CCM_CCGR6_SIM1_CLK_MASK (3 << MXC_CCM_CCGR6_SIM1_CLK_OFFSET) +#define MXC_CCM_CCGR6_SIM2_CLK_OFFSET 8 +#define MXC_CCM_CCGR6_SIM2_CLK_MASK (3 << MXC_CCM_CCGR6_SIM2_CLK_OFFSET) +/* i.MX6ULL */ +#define MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET 8 +#define MXC_CCM_CCGR6_IPMUX4_CLK_MASK (3 << MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET) +/* GPMI/BCH on i.MX6UL */ +#define MXC_CCM_CCGR6_BCH_OFFSET 6 +#define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET) +#define MXC_CCM_CCGR6_GPMI_OFFSET 8 +#define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET) + +#define MXC_CCM_CCGR6_USDHC3_OFFSET 6 +#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET) +#define MXC_CCM_CCGR6_USDHC4_OFFSET 8 +#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET) +#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 +#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET) +/* i.MX6ULL */ +#define MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET 18 +#define MXC_CCM_CCGR6_AIPS_TZ3_CLK_MASK (3 << MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET) +/* The following *CCGR6* exist only i.MX6SX */ +#define MXC_CCM_CCGR6_PWM8_OFFSET 16 +#define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET) +#define MXC_CCM_CCGR6_VADC_OFFSET 20 +#define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET) +#define MXC_CCM_CCGR6_GIS_OFFSET 22 +#define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET) +#define MXC_CCM_CCGR6_I2C4_OFFSET 24 +#define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET) +#define MXC_CCM_CCGR6_PWM5_OFFSET 26 +#define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET) +#define MXC_CCM_CCGR6_PWM6_OFFSET 28 +#define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET) +#define MXC_CCM_CCGR6_PWM7_OFFSET 30 +#define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET) +/* The two does not exist on i.MX6SX */ +#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 +#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET) + +#define BM_ANADIG_PLL_SYS_LOCK 0x80000000 +#define BP_ANADIG_PLL_SYS_RSVD0 20 +#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000 +#define BF_ANADIG_PLL_SYS_RSVD0(v) \ + (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0) +#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000 +#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000 +#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000 +#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000 +#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000 +#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ + (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000 +#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000 +#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400 +#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200 +#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100 +#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080 +#define BP_ANADIG_PLL_SYS_DIV_SELECT 0 +#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F +#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ + (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT) + +#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 +#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17 +#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000 +#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \ + (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1) +#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 +#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 +#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 +#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ + (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) +#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 +#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 +#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 +#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 +#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 +#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 +#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 +#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020 +#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 +#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C +#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ + (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) +#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 +#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 +#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ + (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) + +#define BM_ANADIG_PLL_528_LOCK 0x80000000 +#define BP_ANADIG_PLL_528_RSVD1 19 +#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 +#define BF_ANADIG_PLL_528_RSVD1(v) \ + (((v) << 19) & BM_ANADIG_PLL_528_RSVD1) +#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000 +#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000 +#define BM_ANADIG_PLL_528_BYPASS 0x00010000 +#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000 +#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ + (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_PLL_528_ENABLE 0x00002000 +#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000 +#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400 +#define BM_ANADIG_PLL_528_HALF_CP 0x00000200 +#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100 +#define BM_ANADIG_PLL_528_HALF_LF 0x00000080 +#define BP_ANADIG_PLL_528_RSVD0 1 +#define BM_ANADIG_PLL_528_RSVD0 0x0000007E +#define BF_ANADIG_PLL_528_RSVD0(v) \ + (((v) << 1) & BM_ANADIG_PLL_528_RSVD0) +#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001 + +#define BP_ANADIG_PLL_528_SS_STOP 16 +#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 +#define BF_ANADIG_PLL_528_SS_STOP(v) \ + (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) +#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 +#define BP_ANADIG_PLL_528_SS_STEP 0 +#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF +#define BF_ANADIG_PLL_528_SS_STEP(v) \ + (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) + +#define BP_ANADIG_PLL_528_NUM_RSVD0 30 +#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0) +#define BP_ANADIG_PLL_528_NUM_A 0 +#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF +#define BF_ANADIG_PLL_528_NUM_A(v) \ + (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) + +#define BP_ANADIG_PLL_528_DENOM_RSVD0 30 +#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0) +#define BP_ANADIG_PLL_528_DENOM_B 0 +#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF +#define BF_ANADIG_PLL_528_DENOM_B(v) \ + (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) + +#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000 +#define BP_ANADIG_PLL_AUDIO_RSVD0 22 +#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000 +#define BF_ANADIG_PLL_AUDIO_RSVD0(v) \ + (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0) +#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000 +#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 +#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000 +#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ + (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) +#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000 +#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000 +#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000 +#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000 +#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ + (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000 +#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000 +#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400 +#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200 +#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100 +#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080 +#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 +#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F +#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ + (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) + +#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30 +#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0) +#define BP_ANADIG_PLL_AUDIO_NUM_A 0 +#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF +#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ + (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) + +#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30 +#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0) +#define BP_ANADIG_PLL_AUDIO_DENOM_B 0 +#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF +#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ + (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) + +#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000 +#define BP_ANADIG_PLL_VIDEO_RSVD0 22 +#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000 +#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ + (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) +#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 +#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19 +#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000 +#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \ + (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) +#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 +#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 +#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 +#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000 +#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ + (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000 +#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000 +#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400 +#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200 +#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100 +#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080 +#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 +#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F +#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ + (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) + +#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30 +#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0) +#define BP_ANADIG_PLL_VIDEO_NUM_A 0 +#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF +#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ + (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) + +#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30 +#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0) +#define BP_ANADIG_PLL_VIDEO_DENOM_B 0 +#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF +#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ + (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) + +#define BM_ANADIG_PLL_ENET_LOCK 0x80000000 +#define BP_ANADIG_PLL_ENET_RSVD1 21 +#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000 +#define BF_ANADIG_PLL_ENET_RSVD1(v) \ + (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) +#define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000 +#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 +#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 +#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 +#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000 +#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000 +#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000 +#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ + (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000 +#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000 +#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400 +#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200 +#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100 +#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080 +#define BP_ANADIG_PLL_ENET_RSVD0 2 +#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C +#define BF_ANADIG_PLL_ENET_RSVD0(v) \ + (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0) +#define BP_ANADIG_PLL_ENET_DIV_SELECT 0 +#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 +#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ + (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) + +/* ENET2 for i.MX6SX/UL */ +#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000 +#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C +#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \ + (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT) + +#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 +#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 +#define BP_ANADIG_PFD_480_PFD3_FRAC 24 +#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000 +#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ + (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC) +#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000 +#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000 +#define BP_ANADIG_PFD_480_PFD2_FRAC 16 +#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000 +#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ + (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC) +#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000 +#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000 +#define BP_ANADIG_PFD_480_PFD1_FRAC 8 +#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00 +#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ + (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC) +#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080 +#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040 +#define BP_ANADIG_PFD_480_PFD0_FRAC 0 +#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F +#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ + (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC) + +#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000 +#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000 +#define BP_ANADIG_PFD_528_PFD3_FRAC 24 +#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000 +#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ + (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC) +#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000 +#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000 +#define BP_ANADIG_PFD_528_PFD2_FRAC 16 +#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000 +#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ + (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC) +#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000 +#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000 +#define BP_ANADIG_PFD_528_PFD1_FRAC 8 +#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00 +#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ + (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC) +#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080 +#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040 +#define BP_ANADIG_PFD_528_PFD0_FRAC 0 +#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F +#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ + (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) + +#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 +#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x60 +#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT 4 + +#define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23) +#define BP_PMU_MISC2_AUDIO_DIV_MSB 23 + +#define BM_PMU_MISC2_AUDIO_DIV_LSB (1 << 15) +#define BP_PMU_MISC2_AUDIO_DIV_LSB 15 + +#define PMU_MISC2_AUDIO_DIV(v) \ + (((v & BM_PMU_MISC2_AUDIO_DIV_MSB) >> \ + (BP_PMU_MISC2_AUDIO_DIV_MSB - 1)) | \ + ((v & BM_PMU_MISC2_AUDIO_DIV_LSB) >> \ + BP_PMU_MISC2_AUDIO_DIV_LSB)) + +#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/gpio.h new file mode 100644 index 000000000..b39131993 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, + */ + + +#ifndef __ASM_ARCH_MX6_GPIO_H +#define __ASM_ARCH_MX6_GPIO_H + +#include + +#endif /* __ASM_ARCH_MX6_GPIO_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/imx-rdc.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/imx-rdc.h new file mode 100644 index 000000000..ecdd64d67 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/imx-rdc.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#ifndef __IMX_RDC_H__ +#define __IMX_RDC_H__ + +#if defined(CONFIG_MX6SX) +#include "mx6sx_rdc.h" +#else +#error "Please select cpu" +#endif /* CONFIG_MX6SX */ + +#endif /* __IMX_RDC_H__*/ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/imx-regs.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/imx-regs.h new file mode 100644 index 000000000..a8a5bf7a5 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -0,0 +1,972 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __ASM_ARCH_MX6_IMX_REGS_H__ +#define __ASM_ARCH_MX6_IMX_REGS_H__ + +#define ARCH_MXC + +#define ROMCP_ARB_BASE_ADDR 0x00000000 +#define ROMCP_ARB_END_ADDR 0x000FFFFF + +#ifdef CONFIG_MX6SL +#define GPU_2D_ARB_BASE_ADDR 0x02200000 +#define GPU_2D_ARB_END_ADDR 0x02203FFF +#define OPENVG_ARB_BASE_ADDR 0x02204000 +#define OPENVG_ARB_END_ADDR 0x02207FFF +#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#define CAAM_ARB_BASE_ADDR 0x00100000 +#define CAAM_ARB_END_ADDR 0x00107FFF +#define GPU_ARB_BASE_ADDR 0x01800000 +#define GPU_ARB_END_ADDR 0x01803FFF +#define APBH_DMA_ARB_BASE_ADDR 0x01804000 +#define APBH_DMA_ARB_END_ADDR 0x0180BFFF +#define M4_BOOTROM_BASE_ADDR 0x007F8000 + +#elif !defined(CONFIG_MX6SLL) +#define CAAM_ARB_BASE_ADDR 0x00100000 +#define CAAM_ARB_END_ADDR 0x00103FFF +#define APBH_DMA_ARB_BASE_ADDR 0x00110000 +#define APBH_DMA_ARB_END_ADDR 0x00117FFF +#define HDMI_ARB_BASE_ADDR 0x00120000 +#define HDMI_ARB_END_ADDR 0x00128FFF +#define GPU_3D_ARB_BASE_ADDR 0x00130000 +#define GPU_3D_ARB_END_ADDR 0x00133FFF +#define GPU_2D_ARB_BASE_ADDR 0x00134000 +#define GPU_2D_ARB_END_ADDR 0x00137FFF +#define DTCP_ARB_BASE_ADDR 0x00138000 +#define DTCP_ARB_END_ADDR 0x0013BFFF +#endif /* CONFIG_MX6SL */ + +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) + +/* GPV - PL301 configuration ports */ +#if (defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ + defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)) +#define GPV2_BASE_ADDR 0x00D00000 +#define GPV3_BASE_ADDR 0x00E00000 +#define GPV4_BASE_ADDR 0x00F00000 +#define GPV5_BASE_ADDR 0x01000000 +#define GPV6_BASE_ADDR 0x01100000 +#define PCIE_ARB_BASE_ADDR 0x08000000 +#define PCIE_ARB_END_ADDR 0x08FFFFFF + +#else +#define GPV2_BASE_ADDR 0x00200000 +#define GPV3_BASE_ADDR 0x00300000 +#define GPV4_BASE_ADDR 0x00800000 +#define PCIE_ARB_BASE_ADDR 0x01000000 +#define PCIE_ARB_END_ADDR 0x01FFFFFF +#endif + +#define IRAM_BASE_ADDR 0x00900000 +#define SCU_BASE_ADDR 0x00A00000 +#define IC_INTERFACES_BASE_ADDR 0x00A00100 +#define GLOBAL_TIMER_BASE_ADDR 0x00A00200 +#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 +#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 +#define L2_PL310_BASE 0x00A02000 +#define GPV0_BASE_ADDR 0x00B00000 +#define GPV1_BASE_ADDR 0x00C00000 + +#define AIPS1_ARB_BASE_ADDR 0x02000000 +#define AIPS1_ARB_END_ADDR 0x020FFFFF +#define AIPS2_ARB_BASE_ADDR 0x02100000 +#define AIPS2_ARB_END_ADDR 0x021FFFFF +/* AIPS3 only on i.MX6SX */ +#define AIPS3_ARB_BASE_ADDR 0x02200000 +#define AIPS3_ARB_END_ADDR 0x022FFFFF +#ifdef CONFIG_MX6SX +#define WEIM_ARB_BASE_ADDR 0x50000000 +#define WEIM_ARB_END_ADDR 0x57FFFFFF +#define QSPI0_AMBA_BASE 0x60000000 +#define QSPI0_AMBA_END 0x6FFFFFFF +#define QSPI1_AMBA_BASE 0x70000000 +#define QSPI1_AMBA_END 0x7FFFFFFF +#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#define WEIM_ARB_BASE_ADDR 0x50000000 +#define WEIM_ARB_END_ADDR 0x57FFFFFF +#define QSPI0_AMBA_BASE 0x60000000 +#define QSPI0_AMBA_END 0x6FFFFFFF +#elif !defined(CONFIG_MX6SLL) +#define SATA_ARB_BASE_ADDR 0x02200000 +#define SATA_ARB_END_ADDR 0x02203FFF +#define OPENVG_ARB_BASE_ADDR 0x02204000 +#define OPENVG_ARB_END_ADDR 0x02207FFF +#define HSI_ARB_BASE_ADDR 0x02208000 +#define HSI_ARB_END_ADDR 0x0220BFFF +#define IPU1_ARB_BASE_ADDR 0x02400000 +#define IPU1_ARB_END_ADDR 0x027FFFFF +#define IPU2_ARB_BASE_ADDR 0x02800000 +#define IPU2_ARB_END_ADDR 0x02BFFFFF +#define WEIM_ARB_BASE_ADDR 0x08000000 +#define WEIM_ARB_END_ADDR 0x0FFFFFFF +#endif + +#if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \ + defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#define MMDC0_ARB_BASE_ADDR 0x80000000 +#define MMDC0_ARB_END_ADDR 0xFFFFFFFF +#define MMDC1_ARB_BASE_ADDR 0xC0000000 +#define MMDC1_ARB_END_ADDR 0xFFFFFFFF +#else +#define MMDC0_ARB_BASE_ADDR 0x10000000 +#define MMDC0_ARB_END_ADDR 0x7FFFFFFF +#define MMDC1_ARB_BASE_ADDR 0x80000000 +#define MMDC1_ARB_END_ADDR 0xFFFFFFFF +#endif + +#ifndef CONFIG_MX6SX +#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR +#define IPU_SOC_OFFSET 0x00200000 +#endif + +/* Defines for Blocks connected via AIPS (SkyBlue) */ +#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR +#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR +#define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR +#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR +#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR +#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR + +#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) +#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) +#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) +#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) +#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) + +#define MX6SL_UART5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) +#define MX6SLL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) +#define MX6UL_UART7_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) +#define MX6SL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) +#define MX6SLL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) +#define MX6UL_UART8_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) +#define MX6SL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) +#define MX6SLL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) +#define MX6SL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) + +#ifndef CONFIG_MX6SX +#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) +#endif +#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) +#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) +#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) +#define UART8_BASE (ATZ1_BASE_ADDR + 0x24000) +#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) +#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) +#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) +#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) + +#ifndef CONFIG_MX6SX +#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) +#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) +#endif +#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) + +#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) +#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) +#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) +#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) +#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) +#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) +#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) +/* QOSC on i.MX6SLL */ +#define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) +#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) +#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) +#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) +#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) +#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) +#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) +#define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) +#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) +#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) +#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) +#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) +#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) +#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) +#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) +#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) +#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) +#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) +#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) +#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) +#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) +#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) +#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) +#define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) +#ifdef CONFIG_MX6SLL +#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) +#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#define PXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) +#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) +#define DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) +#elif defined(CONFIG_MX6SL) +#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) +#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) +#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#elif defined(CONFIG_MX6SX) +#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) +#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) +#define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) +#define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) +#define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) +#else +#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) +#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) +#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#endif + +#define MX6SL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) +#define MX6SLL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) + +#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) +#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) +#define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000) +#define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000) +#if defined(CONFIG_MX6UL) +#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) +#else +#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) +#endif +#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) + +#define CONFIG_SYS_FSL_SEC_OFFSET 0 +#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \ + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 +#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \ + CONFIG_SYS_FSL_JR0_OFFSET) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + +#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) +#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) + +#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) +#ifdef CONFIG_MX6SL +#define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) +#else +#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) +#endif + +#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) +#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) +#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) +#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) +#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) +#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) +#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) +#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) +#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) +/* i.MX6SL/SLL */ +#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) +#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) +#else +/* i.MX6SX */ +#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) +#endif +/* i.MX6DQ/SDL */ +#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) + +#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) +#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) +#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) +#ifdef CONFIG_MX6SLL +#define IOMUXC_GPR_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) +#define IOMUXC_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) +#endif +#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) +#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) +#define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) +#define MX6ULL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) +#ifdef CONFIG_MX6SX +#define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) +#else +#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) +#endif +#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) +#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#define SCTR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) +#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) +#define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) +#elif defined(CONFIG_MX6SX) +#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) +#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) +#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) +#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) +#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) +#else +#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) +#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) +#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) +#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) +#endif +#define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) +#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) +#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) +#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) +#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) +#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) +#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) +#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) +/* i.MX6SLL */ +#define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) + +#ifdef CONFIG_MX6SX +#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) +#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000) +#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000) +#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000) +#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000) +#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000) +#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000) +#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) +#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) +#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) +#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) +#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) +#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) +#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) +#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) +#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) +#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) +#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) +#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) +#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) +#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) +#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) +#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) +#define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) +#define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) +#define UART8_IPS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) +#define EPDC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) +#define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) +#define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) +#endif + +#define NOC_DDR_BASE_ADDR (GPV0_BASE_ADDR + 0xB0000) + +/* Only for i.MX6SX */ +#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) +#define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) +#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) + +#if !(defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ + defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL)) +#define IRAM_SIZE 0x00040000 +#else +#define IRAM_SIZE 0x00020000 +#endif +#define FEC_QUIRK_ENET_MAC + +#include +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include +#include + +/* only for i.MX6SX/UL */ +#define WDOG3_BASE_ADDR (((is_mx6ul() || is_mx6ull()) ? \ + MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)) +#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \ + MX6SLL_LCDIF_BASE_ADDR : \ + (is_cpu_type(MXC_CPU_MX6SL)) ? \ + MX6SL_LCDIF_BASE_ADDR : \ + ((is_cpu_type(MXC_CPU_MX6UL)) ? \ + MX6UL_LCDIF1_BASE_ADDR : \ + ((is_mx6ull()) ? \ + MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR))) + + +extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); + +#define SRC_SCR_CORE_1_RESET_OFFSET 14 +#define SRC_SCR_CORE_1_RESET_MASK (1< + +#define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \ + prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc) + +#ifdef CONFIG_MX6QDL +enum { +#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ + MX6_PAD_DECLARE(MX6Q_PAD_,name, pco, mc, mm, sio, si, pc), +#include "mx6q_pins.h" +#undef MX6_PAD_DECL +#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ + MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc), +#include "mx6dl_pins.h" +}; +#elif defined(CONFIG_MX6Q) +enum { +#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ + MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc), +#include "mx6q_pins.h" +}; +#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +enum { +#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ + MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc), +#include "mx6dl_pins.h" +}; +#elif defined(CONFIG_MX6SLL) +#include "mx6sll_pins.h" +#elif defined(CONFIG_MX6SL) +#include "mx6sl_pins.h" +#elif defined(CONFIG_MX6SX) +#include "mx6sx_pins.h" +#elif defined(CONFIG_MX6ULL) +#include "mx6ull_pins.h" +#elif defined(CONFIG_MX6UL) +#include "mx6ul_pins.h" +#else +#error "Please select cpu" +#endif /* CONFIG_MX6Q */ + +#endif /*__ASM_ARCH_MX6_PINS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6_plugin.S b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6_plugin.S new file mode 100644 index 000000000..7e61d22ca --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6_plugin.S @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#include + +#ifdef CONFIG_ROM_UNIFIED_SECTIONS +#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180 +#define ROM_VERSION_OFFSET 0x80 +#else +#define ROM_API_TABLE_BASE_ADDR_LEGACY 0xC0 +#define ROM_VERSION_OFFSET 0x48 +#endif +#define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15 0xC4 +#define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12 0xC4 +#define ROM_API_HWCNFG_SETUP_OFFSET 0x08 +#define ROM_VERSION_TO10 0x10 +#define ROM_VERSION_TO12 0x12 +#define ROM_VERSION_TO15 0x15 + +plugin_start: + + push {r0-r4, lr} + + imx6_ddr_setting + imx6_clock_gating + imx6_qos_setting + +/* + * The following is to fill in those arguments for this ROM function + * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data) + * This function is used to copy data from the storage media into DDR. + * start - Initial (possibly partial) image load address on entry. + * Final image load address on exit. + * bytes - Initial (possibly partial) image size on entry. + * Final image size on exit. + * boot_data - Initial @ref ivt Boot Data load address. + */ + adr r0, boot_data2 + adr r1, image_len2 + adr r2, boot_data2 + +#ifdef CONFIG_NOR_BOOT +#ifdef CONFIG_MX6SX + ldr r3, =ROM_VERSION_OFFSET + ldr r4, [r3] + cmp r4, #ROM_VERSION_TO10 + bgt before_calling_rom___pu_irom_hwcnfg_setup + ldr r3, =0x00900b00 + ldr r4, =0x50000000 + str r4, [r3, #0x5c] +#else + ldr r3, =0x00900800 + ldr r4, =0x08000000 + str r4, [r3, #0xc0] +#endif +#endif + +/* + * check the _pu_irom_api_table for the address + */ +before_calling_rom___pu_irom_hwcnfg_setup: + ldr r3, =ROM_VERSION_OFFSET + ldr r4, [r3] +#if defined(CONFIG_MX6SOLO) || defined(CONFIG_MX6DL) + ldr r3, =ROM_VERSION_TO12 + cmp r4, r3 + ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DL_TO12 + ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY +#elif defined(CONFIG_MX6Q) + ldr r3, =ROM_VERSION_TO15 + cmp r4, r3 + ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15 + ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY +#else + ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY +#endif + ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET] + blx r4 +after_calling_rom___pu_irom_hwcnfg_setup: + +/* + * ROM_API_HWCNFG_SETUP function enables MMU & Caches. + * Thus disable MMU & Caches. + */ + + mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 into r0*/ + ands r0, r0, #0x1 /* check if MMU is enabled */ + beq mmu_disable_notreq /* exit if MMU is already disabled */ + + /* Disable caches, MMU */ + mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 into r0 */ + bic r0, r0, #(1 << 2) /* disable D Cache */ + bic r0, r0, #0x1 /* clear bit 0 ; MMU off */ + + bic r0, r0, #(0x1 << 11) /* disable Z, branch prediction */ + bic r0, r0, #(0x1 << 1) /* disable A, Strict alignment */ + /* check enabled. */ + mcr p15, 0, r0, c1, c0, 0 /* write CP15 register 1 */ + mov r0, r0 + mov r0, r0 + mov r0, r0 + mov r0, r0 + +mmu_disable_notreq: + NOP + +/* To return to ROM from plugin, we need to fill in these argument. + * Here is what need to do: + * Need to construct the paramters for this function before return to ROM: + * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset) + */ + pop {r0-r4, lr} + push {r5} + ldr r5, boot_data2 + str r5, [r0] + ldr r5, image_len2 + str r5, [r1] + ldr r5, second_ivt_offset + str r5, [r2] + mov r0, #1 + pop {r5} + + /* return back to ROM code */ + bx lr + +/* make the following data right in the end of the output*/ +.ltorg + +#if (defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)) +#define FLASH_OFFSET 0x1000 +#else +#define FLASH_OFFSET 0x400 +#endif + +/* + * second_ivt_offset is the offset from the "second_ivt_header" to + * "image_copy_start", which involves FLASH_OFFSET, plus the first + * ivt_header, the plugin code size itself recorded by "ivt2_header" + */ + +second_ivt_offset: .long (ivt2_header + 0x2C + FLASH_OFFSET) + +/* + * The following is the second IVT header plus the second boot data + */ +ivt2_header: .long 0x0 +app2_code_jump_v: .long 0x0 +reserv3: .long 0x0 +dcd2_ptr: .long 0x0 +boot_data2_ptr: .long 0x0 +self_ptr2: .long 0x0 +app_code_csf2: .long 0x0 +reserv4: .long 0x0 +boot_data2: .long 0x0 +image_len2: .long 0x0 +plugin2: .long 0x0 diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h new file mode 100644 index 000000000..2b2821da2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Boundary Devices Inc. + */ +#ifndef __ASM_ARCH_MX6DLS_DDR_H__ +#define __ASM_ARCH_MX6DLS_DDR_H__ + +#ifndef CONFIG_MX6DL +#ifndef CONFIG_MX6S +#error "wrong CPU" +#endif +#endif + +#define MX6_IOM_DRAM_DQM0 0x020e0470 +#define MX6_IOM_DRAM_DQM1 0x020e0474 +#define MX6_IOM_DRAM_DQM2 0x020e0478 +#define MX6_IOM_DRAM_DQM3 0x020e047c +#define MX6_IOM_DRAM_DQM4 0x020e0480 +#define MX6_IOM_DRAM_DQM5 0x020e0484 +#define MX6_IOM_DRAM_DQM6 0x020e0488 +#define MX6_IOM_DRAM_DQM7 0x020e048c + +#define MX6_IOM_DRAM_CAS 0x020e0464 +#define MX6_IOM_DRAM_RAS 0x020e0490 +#define MX6_IOM_DRAM_RESET 0x020e0494 +#define MX6_IOM_DRAM_SDCLK_0 0x020e04ac +#define MX6_IOM_DRAM_SDCLK_1 0x020e04b0 +#define MX6_IOM_DRAM_SDBA2 0x020e04a0 +#define MX6_IOM_DRAM_SDCKE0 0x020e04a4 +#define MX6_IOM_DRAM_SDCKE1 0x020e04a8 +#define MX6_IOM_DRAM_SDODT0 0x020e04b4 +#define MX6_IOM_DRAM_SDODT1 0x020e04b8 + +#define MX6_IOM_DRAM_SDQS0 0x020e04bc +#define MX6_IOM_DRAM_SDQS1 0x020e04c0 +#define MX6_IOM_DRAM_SDQS2 0x020e04c4 +#define MX6_IOM_DRAM_SDQS3 0x020e04c8 +#define MX6_IOM_DRAM_SDQS4 0x020e04cc +#define MX6_IOM_DRAM_SDQS5 0x020e04d0 +#define MX6_IOM_DRAM_SDQS6 0x020e04d4 +#define MX6_IOM_DRAM_SDQS7 0x020e04d8 + +#define MX6_IOM_GRP_B0DS 0x020e0764 +#define MX6_IOM_GRP_B1DS 0x020e0770 +#define MX6_IOM_GRP_B2DS 0x020e0778 +#define MX6_IOM_GRP_B3DS 0x020e077c +#define MX6_IOM_GRP_B4DS 0x020e0780 +#define MX6_IOM_GRP_B5DS 0x020e0784 +#define MX6_IOM_GRP_B6DS 0x020e078c +#define MX6_IOM_GRP_B7DS 0x020e0748 +#define MX6_IOM_GRP_ADDDS 0x020e074c +#define MX6_IOM_DDRMODE_CTL 0x020e0750 +#define MX6_IOM_GRP_DDRPKE 0x020e0754 +#define MX6_IOM_GRP_DDRMODE 0x020e0760 +#define MX6_IOM_GRP_CTLDS 0x020e076c +#define MX6_IOM_GRP_DDR_TYPE 0x020e0774 + +#endif /*__ASM_ARCH_MX6S_DDR_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl_pins.h new file mode 100644 index 000000000..c207a752f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -0,0 +1,1079 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __ASM_ARCH_MX6_MX6DL_PINS_H__ +#define __ASM_ARCH_MX6_MX6DL_PINS_H__ + +MX6_PAD_DECL(CSI0_DAT10__IPU1_CSI0_DATA10, 0x0360, 0x004C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__AUD3_RXC, 0x0360, 0x004C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__ECSPI2_MISO, 0x0360, 0x004C, 2, 0x07F8, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__UART1_TX_DATA, 0x0360, 0x004C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__UART1_RX_DATA, 0x0360, 0x004C, 3, 0x08FC, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__GPIO5_IO28, 0x0360, 0x004C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__ARM_TRACE07, 0x0360, 0x004C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__IPU1_CSI0_DATA11, 0x0364, 0x0050, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__AUD3_RXFS, 0x0364, 0x0050, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__ECSPI2_SS0, 0x0364, 0x0050, 2, 0x0800, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__UART1_TX_DATA, 0x0364, 0x0050, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__UART1_RX_DATA, 0x0364, 0x0050, 3, 0x08FC, 1, 0) +MX6_PAD_DECL(CSI0_DAT11__GPIO5_IO29, 0x0364, 0x0050, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__ARM_TRACE08, 0x0364, 0x0050, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__IPU1_CSI0_DATA12, 0x0368, 0x0054, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__EIM_DATA08, 0x0368, 0x0054, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__UART4_TX_DATA, 0x0368, 0x0054, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__UART4_RX_DATA, 0x0368, 0x0054, 3, 0x0914, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__GPIO5_IO30, 0x0368, 0x0054, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__ARM_TRACE09, 0x0368, 0x0054, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__IPU1_CSI0_DATA13, 0x036C, 0x0058, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__EIM_DATA09, 0x036C, 0x0058, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__UART4_TX_DATA, 0x036C, 0x0058, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__UART4_RX_DATA, 0x036C, 0x0058, 3, 0x0914, 1, 0) +MX6_PAD_DECL(CSI0_DAT13__GPIO5_IO31, 0x036C, 0x0058, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__ARM_TRACE10, 0x036C, 0x0058, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__IPU1_CSI0_DATA14, 0x0370, 0x005C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__EIM_DATA10, 0x0370, 0x005C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__UART5_TX_DATA, 0x0370, 0x005C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__UART5_RX_DATA, 0x0370, 0x005C, 3, 0x091C, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__GPIO6_IO00, 0x0370, 0x005C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__ARM_TRACE11, 0x0370, 0x005C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__IPU1_CSI0_DATA15, 0x0374, 0x0060, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__EIM_DATA11, 0x0374, 0x0060, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__UART5_TX_DATA, 0x0374, 0x0060, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__UART5_RX_DATA, 0x0374, 0x0060, 3, 0x091C, 1, 0) +MX6_PAD_DECL(CSI0_DAT15__GPIO6_IO01, 0x0374, 0x0060, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__ARM_TRACE12, 0x0374, 0x0060, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__IPU1_CSI0_DATA16, 0x0378, 0x0064, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__EIM_DATA12, 0x0378, 0x0064, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__UART4_CTS_B, 0x0378, 0x0064, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__UART4_RTS_B, 0x0378, 0x0064, 3, 0x0910, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__GPIO6_IO02, 0x0378, 0x0064, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__ARM_TRACE13, 0x0378, 0x0064, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__IPU1_CSI0_DATA17, 0x037C, 0x0068, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__EIM_DATA13, 0x037C, 0x0068, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__UART4_CTS_B, 0x037C, 0x0068, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__UART4_RTS_B, 0x037C, 0x0068, 3, 0x0910, 1, 0) +MX6_PAD_DECL(CSI0_DAT17__GPIO6_IO03, 0x037C, 0x0068, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__ARM_TRACE14, 0x037C, 0x0068, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__IPU1_CSI0_DATA18, 0x0380, 0x006C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__EIM_DATA14, 0x0380, 0x006C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__UART5_CTS_B, 0x0380, 0x006C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__UART5_RTS_B, 0x0380, 0x006C, 3, 0x0918, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__GPIO6_IO04, 0x0380, 0x006C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__ARM_TRACE15, 0x0380, 0x006C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__IPU1_CSI0_DATA19, 0x0384, 0x0070, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__EIM_DATA15, 0x0384, 0x0070, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__UART5_CTS_B, 0x0384, 0x0070, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__UART5_RTS_B, 0x0384, 0x0070, 3, 0x0918, 1, 0) +MX6_PAD_DECL(CSI0_DAT19__GPIO6_IO05, 0x0384, 0x0070, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__IPU1_CSI0_DATA04, 0x0388, 0x0074, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__EIM_DATA02, 0x0388, 0x0074, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__ECSPI1_SCLK, 0x0388, 0x0074, 2, 0x07D8, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__KEY_COL5, 0x0388, 0x0074, 3, 0x08C0, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__AUD3_TXC, 0x0388, 0x0074, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__GPIO5_IO22, 0x0388, 0x0074, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__ARM_TRACE01, 0x0388, 0x0074, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__IPU1_CSI0_DATA05, 0x038C, 0x0078, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__EIM_DATA03, 0x038C, 0x0078, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__ECSPI1_MOSI, 0x038C, 0x0078, 2, 0x07E0, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__KEY_ROW5, 0x038C, 0x0078, 3, 0x08CC, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__AUD3_TXD, 0x038C, 0x0078, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__GPIO5_IO23, 0x038C, 0x0078, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__ARM_TRACE02, 0x038C, 0x0078, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__IPU1_CSI0_DATA06, 0x0390, 0x007C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__EIM_DATA04, 0x0390, 0x007C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__ECSPI1_MISO, 0x0390, 0x007C, 2, 0x07DC, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__KEY_COL6, 0x0390, 0x007C, 3, 0x08C4, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__AUD3_TXFS, 0x0390, 0x007C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__GPIO5_IO24, 0x0390, 0x007C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__ARM_TRACE03, 0x0390, 0x007C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__IPU1_CSI0_DATA07, 0x0394, 0x0080, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__EIM_DATA05, 0x0394, 0x0080, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__ECSPI1_SS0, 0x0394, 0x0080, 2, 0x07E4, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__KEY_ROW6, 0x0394, 0x0080, 3, 0x08D0, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__AUD3_RXD, 0x0394, 0x0080, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__GPIO5_IO25, 0x0394, 0x0080, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__ARM_TRACE04, 0x0394, 0x0080, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__IPU1_CSI0_DATA08, 0x0398, 0x0084, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__EIM_DATA06, 0x0398, 0x0084, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__ECSPI2_SCLK, 0x0398, 0x0084, 2, 0x07F4, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__KEY_COL7, 0x0398, 0x0084, 3, 0x08C8, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__I2C1_SDA, 0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__GPIO5_IO26, 0x0398, 0x0084, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__ARM_TRACE05, 0x0398, 0x0084, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__IPU1_CSI0_DATA09, 0x039C, 0x0088, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__EIM_DATA07, 0x039C, 0x0088, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__ECSPI2_MOSI, 0x039C, 0x0088, 2, 0x07FC, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__KEY_ROW7, 0x039C, 0x0088, 3, 0x08D4, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__I2C1_SCL, 0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__GPIO5_IO27, 0x039C, 0x0088, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__ARM_TRACE06, 0x039C, 0x0088, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__IPU1_CSI0_DATA_EN, 0x03A0, 0x008C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__EIM_DATA00, 0x03A0, 0x008C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__GPIO5_IO20, 0x03A0, 0x008C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__ARM_TRACE_CLK, 0x03A0, 0x008C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__IPU1_CSI0_HSYNC, 0x03A4, 0x0090, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__CCM_CLKO1, 0x03A4, 0x0090, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__GPIO5_IO19, 0x03A4, 0x0090, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__ARM_TRACE_CTL, 0x03A4, 0x0090, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK, 0x03A8, 0x0094, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__GPIO5_IO18, 0x03A8, 0x0094, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__ARM_EVENTO, 0x03A8, 0x0094, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__IPU1_CSI0_VSYNC, 0x03AC, 0x0098, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__EIM_DATA01, 0x03AC, 0x0098, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__GPIO5_IO21, 0x03AC, 0x0098, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__ARM_TRACE00, 0x03AC, 0x0098, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, 0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_DISP_CLK__LCD_CLK, 0x03B0, 0x009C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__GPIO4_IO16, 0x03B0, 0x009C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__LCD_WR_RWN, 0x03B0, 0x009C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__IPU1_DI0_PIN15, 0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN15__LCD_ENABLE, 0x03B4, 0x00A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__AUD6_TXC, 0x03B4, 0x00A0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__GPIO4_IO17, 0x03B4, 0x00A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__LCD_RD_E, 0x03B4, 0x00A0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__IPU1_DI0_PIN02, 0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN2__LCD_HSYNC, 0x03B8, 0x00A4, 1, 0x08D8, 0, 0) +MX6_PAD_DECL(DI0_PIN2__AUD6_TXD, 0x03B8, 0x00A4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__GPIO4_IO18, 0x03B8, 0x00A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__LCD_RS, 0x03B8, 0x00A4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__IPU1_DI0_PIN03, 0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN3__LCD_VSYNC, 0x03BC, 0x00A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__AUD6_TXFS, 0x03BC, 0x00A8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__GPIO4_IO19, 0x03BC, 0x00A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__LCD_CS, 0x03BC, 0x00A8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__IPU1_DI0_PIN04, 0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN4__LCD_BUSY, 0x03C0, 0x00AC, 1, 0x08D8, 1, 0) +MX6_PAD_DECL(DI0_PIN4__AUD6_RXD, 0x03C0, 0x00AC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__SD1_WP, 0x03C0, 0x00AC, 3, 0x092C, 0, 0) +MX6_PAD_DECL(DI0_PIN4__GPIO4_IO20, 0x03C0, 0x00AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__LCD_RESET, 0x03C0, 0x00AC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__IPU1_DISP0_DATA00, 0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT0__LCD_DATA00, 0x03C4, 0x00B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__ECSPI3_SCLK, 0x03C4, 0x00B0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__GPIO4_IO21, 0x03C4, 0x00B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01, 0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT1__LCD_DATA01, 0x03C8, 0x00B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI, 0x03C8, 0x00B4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22, 0x03C8, 0x00B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10, 0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT10__LCD_DATA10, 0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31, 0x03CC, 0x00B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11, 0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT11__LCD_DATA11, 0x03D0, 0x00BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT11__GPIO5_IO05, 0x03D0, 0x00BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT12__IPU1_DISP0_DATA12, 0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT12__LCD_DATA12, 0x03D4, 0x00C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT12__GPIO5_IO06, 0x03D4, 0x00C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__IPU1_DISP0_DATA13, 0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT13__LCD_DATA13, 0x03D8, 0x00C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__AUD5_RXFS, 0x03D8, 0x00C4, 3, 0x07BC, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__GPIO5_IO07, 0x03D8, 0x00C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__IPU1_DISP0_DATA14, 0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT14__LCD_DATA14, 0x03DC, 0x00C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__AUD5_RXC, 0x03DC, 0x00C8, 3, 0x07B8, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__GPIO5_IO08, 0x03DC, 0x00C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__IPU1_DISP0_DATA15, 0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT15__LCD_DATA15, 0x03E0, 0x00CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__ECSPI1_SS1, 0x03E0, 0x00CC, 2, 0x07E8, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__ECSPI2_SS1, 0x03E0, 0x00CC, 3, 0x0804, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__GPIO5_IO09, 0x03E0, 0x00CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__IPU1_DISP0_DATA16, 0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT16__LCD_DATA16, 0x03E4, 0x00D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__ECSPI2_MOSI, 0x03E4, 0x00D0, 2, 0x07FC, 1, 0) +MX6_PAD_DECL(DISP0_DAT16__AUD5_TXC, 0x03E4, 0x00D0, 3, 0x07C0, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__SDMA_EXT_EVENT0, 0x03E4, 0x00D0, 4, 0x08E8, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__GPIO5_IO10, 0x03E4, 0x00D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__IPU1_DISP0_DATA17, 0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT17__LCD_DATA17, 0x03E8, 0x00D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__ECSPI2_MISO, 0x03E8, 0x00D4, 2, 0x07F8, 1, 0) +MX6_PAD_DECL(DISP0_DAT17__AUD5_TXD, 0x03E8, 0x00D4, 3, 0x07B4, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__SDMA_EXT_EVENT1, 0x03E8, 0x00D4, 4, 0x08EC, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__GPIO5_IO11, 0x03E8, 0x00D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__IPU1_DISP0_DATA18, 0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT18__LCD_DATA18, 0x03EC, 0x00D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__ECSPI2_SS0, 0x03EC, 0x00D8, 2, 0x0800, 1, 0) +MX6_PAD_DECL(DISP0_DAT18__AUD5_TXFS, 0x03EC, 0x00D8, 3, 0x07C4, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__AUD4_RXFS, 0x03EC, 0x00D8, 4, 0x07A4, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__GPIO5_IO12, 0x03EC, 0x00D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__EIM_CS2_B, 0x03EC, 0x00D8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__IPU1_DISP0_DATA19, 0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT19__LCD_DATA19, 0x03F0, 0x00DC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__ECSPI2_SCLK, 0x03F0, 0x00DC, 2, 0x07F4, 1, 0) +MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD, 0x03F0, 0x00DC, 3, 0x07B0, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC, 0x03F0, 0x00DC, 4, 0x07A0, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13, 0x03F0, 0x00DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B, 0x03F0, 0x00DC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02, 0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT2__LCD_DATA02, 0x03F4, 0x00E0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO, 0x03F4, 0x00E0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23, 0x03F4, 0x00E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__IPU1_DISP0_DATA20, 0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT20__LCD_DATA20, 0x03F8, 0x00E4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__ECSPI1_SCLK, 0x03F8, 0x00E4, 2, 0x07D8, 1, 0) +MX6_PAD_DECL(DISP0_DAT20__AUD4_TXC, 0x03F8, 0x00E4, 3, 0x07A8, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__GPIO5_IO14, 0x03F8, 0x00E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__IPU1_DISP0_DATA21, 0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT21__LCD_DATA21, 0x03FC, 0x00E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__ECSPI1_MOSI, 0x03FC, 0x00E8, 2, 0x07E0, 1, 0) +MX6_PAD_DECL(DISP0_DAT21__AUD4_TXD, 0x03FC, 0x00E8, 3, 0x079C, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__GPIO5_IO15, 0x03FC, 0x00E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__IPU1_DISP0_DATA22, 0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT22__LCD_DATA22, 0x0400, 0x00EC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__ECSPI1_MISO, 0x0400, 0x00EC, 2, 0x07DC, 1, 0) +MX6_PAD_DECL(DISP0_DAT22__AUD4_TXFS, 0x0400, 0x00EC, 3, 0x07AC, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__GPIO5_IO16, 0x0400, 0x00EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__IPU1_DISP0_DATA23, 0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT23__LCD_DATA23, 0x0404, 0x00F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__ECSPI1_SS0, 0x0404, 0x00F0, 2, 0x07E4, 1, 0) +MX6_PAD_DECL(DISP0_DAT23__AUD4_RXD, 0x0404, 0x00F0, 3, 0x0798, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__GPIO5_IO17, 0x0404, 0x00F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__IPU1_DISP0_DATA03, 0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT3__LCD_DATA03, 0x0408, 0x00F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__ECSPI3_SS0, 0x0408, 0x00F4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__GPIO4_IO24, 0x0408, 0x00F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__IPU1_DISP0_DATA04, 0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT4__LCD_DATA04, 0x040C, 0x00F8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__ECSPI3_SS1, 0x040C, 0x00F8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__GPIO4_IO25, 0x040C, 0x00F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__IPU1_DISP0_DATA05, 0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT5__LCD_DATA05, 0x0410, 0x00FC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__ECSPI3_SS2, 0x0410, 0x00FC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__AUD6_RXFS, 0x0410, 0x00FC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__GPIO4_IO26, 0x0410, 0x00FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__IPU1_DISP0_DATA06, 0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT6__LCD_DATA06, 0x0414, 0x0100, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__ECSPI3_SS3, 0x0414, 0x0100, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__AUD6_RXC, 0x0414, 0x0100, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__GPIO4_IO27, 0x0414, 0x0100, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__IPU1_DISP0_DATA07, 0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT7__LCD_DATA07, 0x0418, 0x0104, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__ECSPI3_RDY, 0x0418, 0x0104, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__GPIO4_IO28, 0x0418, 0x0104, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__IPU1_DISP0_DATA08, 0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT8__LCD_DATA08, 0x041C, 0x0108, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__PWM1_OUT, 0x041C, 0x0108, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__WDOG1_B, 0x041C, 0x0108, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__GPIO4_IO29, 0x041C, 0x0108, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__IPU1_DISP0_DATA09, 0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT9__LCD_DATA09, 0x0420, 0x010C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__PWM2_OUT, 0x0420, 0x010C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__WDOG2_B, 0x0420, 0x010C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__GPIO4_IO30, 0x0420, 0x010C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__EIM_ADDR16, 0x04E0, 0x0110, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__IPU1_DI1_DISP_CLK, 0x04E0, 0x0110, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__IPU1_CSI1_PIXCLK, 0x04E0, 0x0110, 2, 0x08B8, 0, 0) +MX6_PAD_DECL(EIM_A16__GPIO2_IO22, 0x04E0, 0x0110, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__SRC_BOOT_CFG16, 0x04E0, 0x0110, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__EPDC_DATA00, 0x04E0, 0x0110, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__EIM_ADDR17, 0x04E4, 0x0114, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__IPU1_DISP1_DATA12, 0x04E4, 0x0114, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__IPU1_CSI1_DATA12, 0x04E4, 0x0114, 2, 0x0890, 0, 0) +MX6_PAD_DECL(EIM_A17__GPIO2_IO21, 0x04E4, 0x0114, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__SRC_BOOT_CFG17, 0x04E4, 0x0114, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__EPDC_PWR_STAT, 0x04E4, 0x0114, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__EIM_ADDR18, 0x04E8, 0x0118, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__IPU1_DISP1_DATA13, 0x04E8, 0x0118, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__IPU1_CSI1_DATA13, 0x04E8, 0x0118, 2, 0x0894, 0, 0) +MX6_PAD_DECL(EIM_A18__GPIO2_IO20, 0x04E8, 0x0118, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__SRC_BOOT_CFG18, 0x04E8, 0x0118, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__EPDC_PWR_CTRL0, 0x04E8, 0x0118, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__EIM_ADDR19, 0x04EC, 0x011C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__IPU1_DISP1_DATA14, 0x04EC, 0x011C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__IPU1_CSI1_DATA14, 0x04EC, 0x011C, 2, 0x0898, 0, 0) +MX6_PAD_DECL(EIM_A19__GPIO2_IO19, 0x04EC, 0x011C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__SRC_BOOT_CFG19, 0x04EC, 0x011C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__EPDC_PWR_CTRL1, 0x04EC, 0x011C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__EIM_ADDR20, 0x04F0, 0x0120, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__IPU1_DISP1_DATA15, 0x04F0, 0x0120, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__IPU1_CSI1_DATA15, 0x04F0, 0x0120, 2, 0x089C, 0, 0) +MX6_PAD_DECL(EIM_A20__GPIO2_IO18, 0x04F0, 0x0120, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__SRC_BOOT_CFG20, 0x04F0, 0x0120, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__EPDC_PWR_CTRL2, 0x04F0, 0x0120, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__EIM_ADDR21, 0x04F4, 0x0124, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__IPU1_DISP1_DATA16, 0x04F4, 0x0124, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__IPU1_CSI1_DATA16, 0x04F4, 0x0124, 2, 0x08A0, 0, 0) +MX6_PAD_DECL(EIM_A21__GPIO2_IO17, 0x04F4, 0x0124, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__SRC_BOOT_CFG21, 0x04F4, 0x0124, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__EPDC_GDCLK, 0x04F4, 0x0124, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__EIM_ADDR22, 0x04F8, 0x0128, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__IPU1_DISP1_DATA17, 0x04F8, 0x0128, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__IPU1_CSI1_DATA17, 0x04F8, 0x0128, 2, 0x08A4, 0, 0) +MX6_PAD_DECL(EIM_A22__GPIO2_IO16, 0x04F8, 0x0128, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__SRC_BOOT_CFG22, 0x04F8, 0x0128, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__EPDC_GDSP, 0x04F8, 0x0128, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__EIM_ADDR23, 0x04FC, 0x012C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_DISP1_DATA18, 0x04FC, 0x012C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_CSI1_DATA18, 0x04FC, 0x012C, 2, 0x08A8, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_SISG3, 0x04FC, 0x012C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__GPIO6_IO06, 0x04FC, 0x012C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__SRC_BOOT_CFG23, 0x04FC, 0x012C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__EPDC_GDOE, 0x04FC, 0x012C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__EIM_ADDR24, 0x0500, 0x0130, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_DISP1_DATA19, 0x0500, 0x0130, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_CSI1_DATA19, 0x0500, 0x0130, 2, 0x08AC, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_SISG2, 0x0500, 0x0130, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__GPIO5_IO04, 0x0500, 0x0130, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__SRC_BOOT_CFG24, 0x0500, 0x0130, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__EPDC_GDRL, 0x0500, 0x0130, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__EIM_ADDR25, 0x0504, 0x0134, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__ECSPI4_SS1, 0x0504, 0x0134, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__ECSPI2_RDY, 0x0504, 0x0134, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__IPU1_DI1_PIN12, 0x0504, 0x0134, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__IPU1_DI0_D1_CS, 0x0504, 0x0134, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__GPIO5_IO02, 0x0504, 0x0134, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__HDMI_TX_CEC_LINE, 0x0504, 0x0134, 6, 0x085C, 0, 0) +MX6_PAD_DECL(EIM_A25__EPDC_DATA15, 0x0504, 0x0134, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__EIM_ACLK_FREERUN, 0x0504, 0x0134, 9, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__EIM_BCLK, 0x0508, 0x0138, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__IPU1_DI1_PIN16, 0x0508, 0x0138, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__GPIO6_IO31, 0x0508, 0x0138, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__EPDC_SDCE9, 0x0508, 0x0138, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__EIM_CS0_B, 0x050C, 0x013C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__IPU1_DI1_PIN05, 0x050C, 0x013C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__ECSPI2_SCLK, 0x050C, 0x013C, 2, 0x07F4, 2, 0) +MX6_PAD_DECL(EIM_CS0__GPIO2_IO23, 0x050C, 0x013C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__EPDC_DATA06, 0x050C, 0x013C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__EIM_CS1_B, 0x0510, 0x0140, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__IPU1_DI1_PIN06, 0x0510, 0x0140, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__ECSPI2_MOSI, 0x0510, 0x0140, 2, 0x07FC, 2, 0) +MX6_PAD_DECL(EIM_CS1__GPIO2_IO24, 0x0510, 0x0140, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__EPDC_DATA08, 0x0510, 0x0140, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__EIM_DATA16, 0x0514, 0x0144, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__ECSPI1_SCLK, 0x0514, 0x0144, 1, 0x07D8, 2, 0) +MX6_PAD_DECL(EIM_D16__IPU1_DI0_PIN05, 0x0514, 0x0144, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__IPU1_CSI1_DATA18, 0x0514, 0x0144, 3, 0x08A8, 1, 0) +MX6_PAD_DECL(EIM_D16__HDMI_TX_DDC_SDA, 0x0514, 0x0144, 4, 0x0864, 0, 0) +MX6_PAD_DECL(EIM_D16__GPIO3_IO16, 0x0514, 0x0144, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__I2C2_SDA, 0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, 0) +MX6_PAD_DECL(EIM_D16__EPDC_DATA10, 0x0514, 0x0144, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__EIM_DATA17, 0x0518, 0x0148, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__ECSPI1_MISO, 0x0518, 0x0148, 1, 0x07DC, 2, 0) +MX6_PAD_DECL(EIM_D17__IPU1_DI0_PIN06, 0x0518, 0x0148, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__IPU1_CSI1_PIXCLK, 0x0518, 0x0148, 3, 0x08B8, 1, 0) +MX6_PAD_DECL(EIM_D17__DCIC1_OUT, 0x0518, 0x0148, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__GPIO3_IO17, 0x0518, 0x0148, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__I2C3_SCL, 0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, 0) +MX6_PAD_DECL(EIM_D17__EPDC_VCOM0, 0x0518, 0x0148, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__EIM_DATA18, 0x051C, 0x014C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__ECSPI1_MOSI, 0x051C, 0x014C, 1, 0x07E0, 2, 0) +MX6_PAD_DECL(EIM_D18__IPU1_DI0_PIN07, 0x051C, 0x014C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__IPU1_CSI1_DATA17, 0x051C, 0x014C, 3, 0x08A4, 1, 0) +MX6_PAD_DECL(EIM_D18__IPU1_DI1_D0_CS, 0x051C, 0x014C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__GPIO3_IO18, 0x051C, 0x014C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__I2C3_SDA, 0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0) +MX6_PAD_DECL(EIM_D18__EPDC_VCOM1, 0x051C, 0x014C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__EIM_DATA19, 0x0520, 0x0150, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__ECSPI1_SS1, 0x0520, 0x0150, 1, 0x07E8, 1, 0) +MX6_PAD_DECL(EIM_D19__IPU1_DI0_PIN08, 0x0520, 0x0150, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__IPU1_CSI1_DATA16, 0x0520, 0x0150, 3, 0x08A0, 1, 0) +MX6_PAD_DECL(EIM_D19__UART1_CTS_B, 0x0520, 0x0150, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__UART1_RTS_B, 0x0520, 0x0150, 4, 0x08F8, 0, 0) +MX6_PAD_DECL(EIM_D19__GPIO3_IO19, 0x0520, 0x0150, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__EPIT1_OUT, 0x0520, 0x0150, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__EPDC_DATA12, 0x0520, 0x0150, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__EIM_DATA20, 0x0524, 0x0154, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__ECSPI4_SS0, 0x0524, 0x0154, 1, 0x0808, 0, 0) +MX6_PAD_DECL(EIM_D20__IPU1_DI0_PIN16, 0x0524, 0x0154, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__IPU1_CSI1_DATA15, 0x0524, 0x0154, 3, 0x089C, 1, 0) +MX6_PAD_DECL(EIM_D20__UART1_CTS_B, 0x0524, 0x0154, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__UART1_RTS_B, 0x0524, 0x0154, 4, 0x08F8, 1, 0) +MX6_PAD_DECL(EIM_D20__GPIO3_IO20, 0x0524, 0x0154, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__EPIT2_OUT, 0x0524, 0x0154, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__EIM_DATA21, 0x0528, 0x0158, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__ECSPI4_SCLK, 0x0528, 0x0158, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__IPU1_DI0_PIN17, 0x0528, 0x0158, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__IPU1_CSI1_DATA11, 0x0528, 0x0158, 3, 0x088C, 0, 0) +MX6_PAD_DECL(EIM_D21__USB_OTG_OC, 0x0528, 0x0158, 4, 0x0920, 0, 0) +MX6_PAD_DECL(EIM_D21__GPIO3_IO21, 0x0528, 0x0158, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__I2C1_SCL, 0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0) +MX6_PAD_DECL(EIM_D21__SPDIF_IN, 0x0528, 0x0158, 7, 0x08F0, 0, 0) +MX6_PAD_DECL(EIM_D22__EIM_DATA22, 0x052C, 0x015C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__ECSPI4_MISO, 0x052C, 0x015C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__IPU1_DI0_PIN01, 0x052C, 0x015C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__IPU1_CSI1_DATA10, 0x052C, 0x015C, 3, 0x0888, 0, 0) +MX6_PAD_DECL(EIM_D22__USB_OTG_PWR, 0x052C, 0x015C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__GPIO3_IO22, 0x052C, 0x015C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__SPDIF_OUT, 0x052C, 0x015C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__EPDC_SDCE6, 0x052C, 0x015C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__EIM_DATA23, 0x0530, 0x0160, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI0_D0_CS, 0x0530, 0x0160, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__UART3_CTS_B, 0x0530, 0x0160, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__UART3_RTS_B, 0x0530, 0x0160, 2, 0x0908, 0, 0) +MX6_PAD_DECL(EIM_D23__UART1_DCD_B, 0x0530, 0x0160, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_CSI1_DATA_EN, 0x0530, 0x0160, 4, 0x08B0, 0, 0) +MX6_PAD_DECL(EIM_D23__GPIO3_IO23, 0x0530, 0x0160, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN02, 0x0530, 0x0160, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN14, 0x0530, 0x0160, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__EPDC_DATA11, 0x0530, 0x0160, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__EIM_DATA24, 0x0534, 0x0164, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI4_SS2, 0x0534, 0x0164, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__UART3_TX_DATA, 0x0534, 0x0164, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__UART3_RX_DATA, 0x0534, 0x0164, 2, 0x090C, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI1_SS2, 0x0534, 0x0164, 3, 0x07EC, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI2_SS2, 0x0534, 0x0164, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__GPIO3_IO24, 0x0534, 0x0164, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__AUD5_RXFS, 0x0534, 0x0164, 6, 0x07BC, 1, 0) +MX6_PAD_DECL(EIM_D24__UART1_DTR_B, 0x0534, 0x0164, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__EPDC_SDCE7, 0x0534, 0x0164, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__EIM_DATA25, 0x0538, 0x0168, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__ECSPI4_SS3, 0x0538, 0x0168, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__UART3_TX_DATA, 0x0538, 0x0168, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__UART3_RX_DATA, 0x0538, 0x0168, 2, 0x090C, 1, 0) +MX6_PAD_DECL(EIM_D25__ECSPI1_SS3, 0x0538, 0x0168, 3, 0x07F0, 0, 0) +MX6_PAD_DECL(EIM_D25__ECSPI2_SS3, 0x0538, 0x0168, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__GPIO3_IO25, 0x0538, 0x0168, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__AUD5_RXC, 0x0538, 0x0168, 6, 0x07B8, 1, 0) +MX6_PAD_DECL(EIM_D25__UART1_DSR_B, 0x0538, 0x0168, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__EPDC_SDCE8, 0x0538, 0x0168, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__EIM_DATA26, 0x053C, 0x016C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_DI1_PIN11, 0x053C, 0x016C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_CSI0_DATA01, 0x053C, 0x016C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_CSI1_DATA14, 0x053C, 0x016C, 3, 0x0898, 1, 0) +MX6_PAD_DECL(EIM_D26__UART2_TX_DATA, 0x053C, 0x016C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__UART2_RX_DATA, 0x053C, 0x016C, 4, 0x0904, 0, 0) +MX6_PAD_DECL(EIM_D26__GPIO3_IO26, 0x053C, 0x016C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_SISG2, 0x053C, 0x016C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_DISP1_DATA22, 0x053C, 0x016C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__EPDC_SDOED, 0x053C, 0x016C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__EIM_DATA27, 0x0540, 0x0170, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_DI1_PIN13, 0x0540, 0x0170, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_CSI0_DATA00, 0x0540, 0x0170, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_CSI1_DATA13, 0x0540, 0x0170, 3, 0x0894, 1, 0) +MX6_PAD_DECL(EIM_D27__UART2_TX_DATA, 0x0540, 0x0170, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__UART2_RX_DATA, 0x0540, 0x0170, 4, 0x0904, 1, 0) +MX6_PAD_DECL(EIM_D27__GPIO3_IO27, 0x0540, 0x0170, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_SISG3, 0x0540, 0x0170, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_DISP1_DATA23, 0x0540, 0x0170, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__EPDC_SDOE, 0x0540, 0x0170, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__EIM_DATA28, 0x0544, 0x0174, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__I2C1_SDA, 0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0) +MX6_PAD_DECL(EIM_D28__ECSPI4_MOSI, 0x0544, 0x0174, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_CSI1_DATA12, 0x0544, 0x0174, 3, 0x0890, 1, 0) +MX6_PAD_DECL(EIM_D28__UART2_DTE_RTS_B, 0x0544, 0x0174, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__UART2_DTE_CTS_B, 0x0544, 0x0174, 4, 0x0900, 0, 0) +MX6_PAD_DECL(EIM_D28__GPIO3_IO28, 0x0544, 0x0174, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_EXT_TRIG, 0x0544, 0x0174, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_DI0_PIN13, 0x0544, 0x0174, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__EPDC_PWR_CTRL3, 0x0544, 0x0174, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__EIM_DATA29, 0x0548, 0x0178, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_DI1_PIN15, 0x0548, 0x0178, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__ECSPI4_SS0, 0x0548, 0x0178, 2, 0x0808, 1, 0) +MX6_PAD_DECL(EIM_D29__UART2_CTS_B, 0x0548, 0x0178, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__UART2_RTS_B, 0x0548, 0x0178, 4, 0x0900, 1, 0) +MX6_PAD_DECL(EIM_D29__GPIO3_IO29, 0x0548, 0x0178, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_CSI1_VSYNC, 0x0548, 0x0178, 6, 0x08BC, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_DI0_PIN14, 0x0548, 0x0178, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__EPDC_PWR_WAKE, 0x0548, 0x0178, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__EIM_DATA30, 0x054C, 0x017C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_DISP1_DATA21, 0x054C, 0x017C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_DI0_PIN11, 0x054C, 0x017C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_CSI0_DATA03, 0x054C, 0x017C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__UART3_CTS_B, 0x054C, 0x017C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__UART3_RTS_B, 0x054C, 0x017C, 4, 0x0908, 1, 0) +MX6_PAD_DECL(EIM_D30__GPIO3_IO30, 0x054C, 0x017C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__USB_H1_OC, 0x054C, 0x017C, 6, 0x0924, 0, 0) +MX6_PAD_DECL(EIM_D30__EPDC_SDOEZ, 0x054C, 0x017C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__EIM_DATA31, 0x0550, 0x0180, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_DISP1_DATA20, 0x0550, 0x0180, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_DI0_PIN12, 0x0550, 0x0180, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_CSI0_DATA02, 0x0550, 0x0180, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__UART3_CTS_B, 0x0550, 0x0180, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__UART3_RTS_B, 0x0550, 0x0180, 4, 0x0908, 2, 0) +MX6_PAD_DECL(EIM_D31__GPIO3_IO31, 0x0550, 0x0180, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__USB_H1_PWR, 0x0550, 0x0180, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__EPDC_SDCLK_P, 0x0550, 0x0180, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__EIM_ACLK_FREERUN, 0x0550, 0x0180, 9, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__EIM_AD00, 0x0554, 0x0184, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__IPU1_DISP1_DATA09, 0x0554, 0x0184, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__IPU1_CSI1_DATA09, 0x0554, 0x0184, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__GPIO3_IO00, 0x0554, 0x0184, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__SRC_BOOT_CFG00, 0x0554, 0x0184, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__EPDC_SDCLK_N, 0x0554, 0x0184, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__EIM_AD01, 0x0558, 0x0188, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__IPU1_DISP1_DATA08, 0x0558, 0x0188, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__IPU1_CSI1_DATA08, 0x0558, 0x0188, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__GPIO3_IO01, 0x0558, 0x0188, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__SRC_BOOT_CFG01, 0x0558, 0x0188, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__EPDC_SDLE, 0x0558, 0x0188, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__EIM_AD10, 0x055C, 0x018C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__IPU1_DI1_PIN15, 0x055C, 0x018C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__IPU1_CSI1_DATA_EN, 0x055C, 0x018C, 2, 0x08B0, 1, 0) +MX6_PAD_DECL(EIM_DA10__GPIO3_IO10, 0x055C, 0x018C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__SRC_BOOT_CFG10, 0x055C, 0x018C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__EPDC_DATA01, 0x055C, 0x018C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__EIM_AD11, 0x0560, 0x0190, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__IPU1_DI1_PIN02, 0x0560, 0x0190, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__IPU1_CSI1_HSYNC, 0x0560, 0x0190, 2, 0x08B4, 0, 0) +MX6_PAD_DECL(EIM_DA11__GPIO3_IO11, 0x0560, 0x0190, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__SRC_BOOT_CFG11, 0x0560, 0x0190, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__EPDC_DATA03, 0x0560, 0x0190, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__EIM_AD12, 0x0564, 0x0194, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__IPU1_DI1_PIN03, 0x0564, 0x0194, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__IPU1_CSI1_VSYNC, 0x0564, 0x0194, 2, 0x08BC, 1, 0) +MX6_PAD_DECL(EIM_DA12__GPIO3_IO12, 0x0564, 0x0194, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__SRC_BOOT_CFG12, 0x0564, 0x0194, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__EPDC_DATA02, 0x0564, 0x0194, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__EIM_AD13, 0x0568, 0x0198, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__IPU1_DI1_D0_CS, 0x0568, 0x0198, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__GPIO3_IO13, 0x0568, 0x0198, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__SRC_BOOT_CFG13, 0x0568, 0x0198, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__EPDC_DATA13, 0x0568, 0x0198, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__EIM_AD14, 0x056C, 0x019C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__IPU1_DI1_D1_CS, 0x056C, 0x019C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__GPIO3_IO14, 0x056C, 0x019C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__SRC_BOOT_CFG14, 0x056C, 0x019C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__EPDC_DATA14, 0x056C, 0x019C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__EIM_AD15, 0x0570, 0x01A0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN01, 0x0570, 0x01A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN04, 0x0570, 0x01A0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__GPIO3_IO15, 0x0570, 0x01A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__SRC_BOOT_CFG15, 0x0570, 0x01A0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__EPDC_DATA09, 0x0570, 0x01A0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__EIM_AD02, 0x0574, 0x01A4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__IPU1_DISP1_DATA07, 0x0574, 0x01A4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__IPU1_CSI1_DATA07, 0x0574, 0x01A4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__GPIO3_IO02, 0x0574, 0x01A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__SRC_BOOT_CFG02, 0x0574, 0x01A4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__EPDC_BDR0, 0x0574, 0x01A4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__EIM_AD03, 0x0578, 0x01A8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__IPU1_DISP1_DATA06, 0x0578, 0x01A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__IPU1_CSI1_DATA06, 0x0578, 0x01A8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__GPIO3_IO03, 0x0578, 0x01A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__SRC_BOOT_CFG03, 0x0578, 0x01A8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__EPDC_BDR1, 0x0578, 0x01A8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__EIM_AD04, 0x057C, 0x01AC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__IPU1_DISP1_DATA05, 0x057C, 0x01AC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__IPU1_CSI1_DATA05, 0x057C, 0x01AC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__GPIO3_IO04, 0x057C, 0x01AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__SRC_BOOT_CFG04, 0x057C, 0x01AC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__EPDC_SDCE0, 0x057C, 0x01AC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__EIM_AD05, 0x0580, 0x01B0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__IPU1_DISP1_DATA04, 0x0580, 0x01B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__IPU1_CSI1_DATA04, 0x0580, 0x01B0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__GPIO3_IO05, 0x0580, 0x01B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__SRC_BOOT_CFG05, 0x0580, 0x01B0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__EPDC_SDCE1, 0x0580, 0x01B0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__EIM_AD06, 0x0584, 0x01B4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__IPU1_DISP1_DATA03, 0x0584, 0x01B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__IPU1_CSI1_DATA03, 0x0584, 0x01B4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__GPIO3_IO06, 0x0584, 0x01B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__SRC_BOOT_CFG06, 0x0584, 0x01B4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__EPDC_SDCE2, 0x0584, 0x01B4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__EIM_AD07, 0x0588, 0x01B8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__IPU1_DISP1_DATA02, 0x0588, 0x01B8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__IPU1_CSI1_DATA02, 0x0588, 0x01B8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__GPIO3_IO07, 0x0588, 0x01B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__SRC_BOOT_CFG07, 0x0588, 0x01B8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__EPDC_SDCE3, 0x0588, 0x01B8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__EIM_AD08, 0x058C, 0x01BC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__IPU1_DISP1_DATA01, 0x058C, 0x01BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__IPU1_CSI1_DATA01, 0x058C, 0x01BC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__GPIO3_IO08, 0x058C, 0x01BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__SRC_BOOT_CFG08, 0x058C, 0x01BC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__EPDC_SDCE4, 0x058C, 0x01BC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__EIM_AD09, 0x0590, 0x01C0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__IPU1_DISP1_DATA00, 0x0590, 0x01C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__IPU1_CSI1_DATA00, 0x0590, 0x01C0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__GPIO3_IO09, 0x0590, 0x01C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__SRC_BOOT_CFG09, 0x0590, 0x01C0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__EPDC_SDCE5, 0x0590, 0x01C0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__EIM_EB0_B, 0x0594, 0x01C4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__IPU1_DISP1_DATA11, 0x0594, 0x01C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__IPU1_CSI1_DATA11, 0x0594, 0x01C4, 2, 0x088C, 1, 0) +MX6_PAD_DECL(EIM_EB0__CCM_PMIC_READY, 0x0594, 0x01C4, 4, 0x07D4, 0, 0) +MX6_PAD_DECL(EIM_EB0__GPIO2_IO28, 0x0594, 0x01C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__SRC_BOOT_CFG27, 0x0594, 0x01C4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__EPDC_PWR_COM, 0x0594, 0x01C4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__EIM_EB1_B, 0x0598, 0x01C8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__IPU1_DISP1_DATA10, 0x0598, 0x01C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__IPU1_CSI1_DATA10, 0x0598, 0x01C8, 2, 0x0888, 1, 0) +MX6_PAD_DECL(EIM_EB1__GPIO2_IO29, 0x0598, 0x01C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__SRC_BOOT_CFG28, 0x0598, 0x01C8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__EPDC_SDSHR, 0x0598, 0x01C8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__EIM_EB2_B, 0x059C, 0x01CC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__ECSPI1_SS0, 0x059C, 0x01CC, 1, 0x07E4, 2, 0) +MX6_PAD_DECL(EIM_EB2__IPU1_CSI1_DATA19, 0x059C, 0x01CC, 3, 0x08AC, 1, 0) +MX6_PAD_DECL(EIM_EB2__HDMI_TX_DDC_SCL, 0x059C, 0x01CC, 4, 0x0860, 0, 0) +MX6_PAD_DECL(EIM_EB2__GPIO2_IO30, 0x059C, 0x01CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__I2C2_SCL, 0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, 0) +MX6_PAD_DECL(EIM_EB2__SRC_BOOT_CFG30, 0x059C, 0x01CC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__EPDC_DATA05, 0x059C, 0x01CC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__EIM_EB3_B, 0x05A0, 0x01D0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__ECSPI4_RDY, 0x05A0, 0x01D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__UART3_CTS_B, 0x05A0, 0x01D0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__UART3_RTS_B, 0x05A0, 0x01D0, 2, 0x0908, 3, 0) +MX6_PAD_DECL(EIM_EB3__UART1_RI_B, 0x05A0, 0x01D0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__IPU1_CSI1_HSYNC, 0x05A0, 0x01D0, 4, 0x08B4, 1, 0) +MX6_PAD_DECL(EIM_EB3__GPIO2_IO31, 0x05A0, 0x01D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__IPU1_DI1_PIN03, 0x05A0, 0x01D0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__SRC_BOOT_CFG31, 0x05A0, 0x01D0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__EPDC_SDCE0, 0x05A0, 0x01D0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__EIM_ACLK_FREERUN, 0x05A0, 0x01D0, 9, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__EIM_LBA_B, 0x05A4, 0x01D4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__IPU1_DI1_PIN17, 0x05A4, 0x01D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__ECSPI2_SS1, 0x05A4, 0x01D4, 2, 0x0804, 1, 0) +MX6_PAD_DECL(EIM_LBA__GPIO2_IO27, 0x05A4, 0x01D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__SRC_BOOT_CFG26, 0x05A4, 0x01D4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__EPDC_DATA04, 0x05A4, 0x01D4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__EIM_OE_B, 0x05A8, 0x01D8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__IPU1_DI1_PIN07, 0x05A8, 0x01D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__ECSPI2_MISO, 0x05A8, 0x01D8, 2, 0x07F8, 2, 0) +MX6_PAD_DECL(EIM_OE__GPIO2_IO25, 0x05A8, 0x01D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__EPDC_PWR_IRQ, 0x05A8, 0x01D8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__EIM_RW, 0x05AC, 0x01DC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__IPU1_DI1_PIN08, 0x05AC, 0x01DC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__ECSPI2_SS0, 0x05AC, 0x01DC, 2, 0x0800, 2, 0) +MX6_PAD_DECL(EIM_RW__GPIO2_IO26, 0x05AC, 0x01DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__SRC_BOOT_CFG29, 0x05AC, 0x01DC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__EPDC_DATA07, 0x05AC, 0x01DC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__EIM_WAIT_B, 0x05B0, 0x01E0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__EIM_DTACK_B, 0x05B0, 0x01E0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__GPIO5_IO00, 0x05B0, 0x01E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__SRC_BOOT_CFG25, 0x05B0, 0x01E0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__ENET_RX_EN, 0x05B4, 0x01E4, 1, 0x0828, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__ESAI_TX_CLK, 0x05B4, 0x01E4, 2, 0x0840, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__SPDIF_EXT_CLK, 0x05B4, 0x01E4, 3, 0x08F4, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__GPIO1_IO25, 0x05B4, 0x01E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__MLB_DATA, 0x05B8, 0x01E8, 0, 0x08E0, 0, 0) +MX6_PAD_DECL(ENET_MDC__ENET_MDC, 0x05B8, 0x01E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__ESAI_TX5_RX0, 0x05B8, 0x01E8, 2, 0x0858, 0, 0) +MX6_PAD_DECL(ENET_MDC__ENET_1588_EVENT1_IN, 0x05B8, 0x01E8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__GPIO1_IO31, 0x05B8, 0x01E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ENET_MDIO, 0x05BC, 0x01EC, 1, 0x0810, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK, 0x05BC, 0x01EC, 2, 0x083C, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT, 0x05BC, 0x01EC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22, 0x05BC, 0x01EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK, 0x05BC, 0x01EC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x05C0, 0x01F0, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS, 0x05C0, 0x01F0, 2, 0x082C, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23, 0x05C0, 0x01F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK, 0x05C0, 0x01F0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__USB_OTG_ID, 0x05C4, 0x01F4, 0, 0x0790, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__ENET_RX_ER, 0x05C4, 0x01F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__ESAI_RX_HF_CLK, 0x05C4, 0x01F4, 2, 0x0834, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__SPDIF_IN, 0x05C4, 0x01F4, 3, 0x08F0, 1, 0) +MX6_PAD_DECL(ENET_RX_ER__ENET_1588_EVENT2_OUT, 0x05C4, 0x01F4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__GPIO1_IO24, 0x05C4, 0x01F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD0__ENET_RX_DATA0, 0x05C8, 0x01F8, 1, 0x0818, 0, 0) +MX6_PAD_DECL(ENET_RXD0__ESAI_TX_HF_CLK, 0x05C8, 0x01F8, 2, 0x0838, 0, 0) +MX6_PAD_DECL(ENET_RXD0__SPDIF_OUT, 0x05C8, 0x01F8, 3, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD0__GPIO1_IO27, 0x05C8, 0x01F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD1__MLB_SIG, 0x05CC, 0x01FC, 0, 0x08E4, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ENET_RX_DATA1, 0x05CC, 0x01FC, 1, 0x081C, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ESAI_TX_FS, 0x05CC, 0x01FC, 2, 0x0830, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ENET_1588_EVENT3_OUT, 0x05CC, 0x01FC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD1__GPIO1_IO26, 0x05CC, 0x01FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__ENET_TX_EN, 0x05D0, 0x0200, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__ESAI_TX3_RX2, 0x05D0, 0x0200, 2, 0x0850, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__GPIO1_IO28, 0x05D0, 0x0200, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__I2C4_SCL, 0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, 0) +MX6_PAD_DECL(ENET_TXD0__ENET_TX_DATA0, 0x05D4, 0x0204, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD0__ESAI_TX4_RX1, 0x05D4, 0x0204, 2, 0x0854, 0, 0) +MX6_PAD_DECL(ENET_TXD0__GPIO1_IO30, 0x05D4, 0x0204, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__MLB_CLK, 0x05D8, 0x0208, 0, 0x08DC, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ENET_TX_DATA1, 0x05D8, 0x0208, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ESAI_TX2_RX3, 0x05D8, 0x0208, 2, 0x084C, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ENET_1588_EVENT0_IN, 0x05D8, 0x0208, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__GPIO1_IO29, 0x05D8, 0x0208, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__I2C4_SDA, 0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, 0) +MX6_PAD_DECL(GPIO_0__CCM_CLKO1, 0x05DC, 0x020C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__KEY_COL5, 0x05DC, 0x020C, 2, 0x08C0, 1, 0) +MX6_PAD_DECL(GPIO_0__ASRC_EXT_CLK, 0x05DC, 0x020C, 3, 0x0794, 0, 0) +MX6_PAD_DECL(GPIO_0__EPIT1_OUT, 0x05DC, 0x020C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__GPIO1_IO00, 0x05DC, 0x020C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__USB_H1_PWR, 0x05DC, 0x020C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__SNVS_VIO_5, 0x05DC, 0x020C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__ESAI_RX_CLK, 0x05E0, 0x0210, 0, 0x083C, 1, 0) +MX6_PAD_DECL(GPIO_1__WDOG2_B, 0x05E0, 0x0210, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__KEY_ROW5, 0x05E0, 0x0210, 2, 0x08CC, 1, 0) +MX6_PAD_DECL(GPIO_1__USB_OTG_ID, 0x05E0, 0x0210, 3, 0x0790, 1, 0) +MX6_PAD_DECL(GPIO_1__PWM2_OUT, 0x05E0, 0x0210, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__GPIO1_IO01, 0x05E0, 0x0210, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__SD1_CD_B, 0x05E0, 0x0210, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2, 0x05E4, 0x0214, 0, 0x0850, 1, 0) +MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x05E4, 0x0214, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x05E4, 0x0214, 2 | IOMUX_CONFIG_SION, 0x080C, 0, 0) +MX6_PAD_DECL(GPIO_16__SD1_LCTL, 0x05E4, 0x0214, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__SPDIF_IN, 0x05E4, 0x0214, 4, 0x08F0, 2, 0) +MX6_PAD_DECL(GPIO_16__GPIO7_IO11, 0x05E4, 0x0214, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__I2C3_SDA, 0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0) +MX6_PAD_DECL(GPIO_16__JTAG_DE_B, 0x05E4, 0x0214, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__ESAI_TX0, 0x05E8, 0x0218, 0, 0x0844, 0, 0) +MX6_PAD_DECL(GPIO_17__ENET_1588_EVENT3_IN, 0x05E8, 0x0218, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__CCM_PMIC_READY, 0x05E8, 0x0218, 2, 0x07D4, 1, 0) +MX6_PAD_DECL(GPIO_17__SDMA_EXT_EVENT0, 0x05E8, 0x0218, 3, 0x08E8, 1, 0) +MX6_PAD_DECL(GPIO_17__SPDIF_OUT, 0x05E8, 0x0218, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__GPIO7_IO12, 0x05E8, 0x0218, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__ESAI_TX1, 0x05EC, 0x021C, 0, 0x0848, 0, 0) +MX6_PAD_DECL(GPIO_18__ENET_RX_CLK, 0x05EC, 0x021C, 1, 0x0814, 0, 0) +MX6_PAD_DECL(GPIO_18__SD3_VSELECT, 0x05EC, 0x021C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__SDMA_EXT_EVENT1, 0x05EC, 0x021C, 3, 0x08EC, 1, 0) +MX6_PAD_DECL(GPIO_18__ASRC_EXT_CLK, 0x05EC, 0x021C, 4, 0x0794, 1, 0) +MX6_PAD_DECL(GPIO_18__GPIO7_IO13, 0x05EC, 0x021C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__SNVS_VIO_5_CTL, 0x05EC, 0x021C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__KEY_COL5, 0x05F0, 0x0220, 0, 0x08C0, 2, 0) +MX6_PAD_DECL(GPIO_19__ENET_1588_EVENT0_OUT, 0x05F0, 0x0220, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__SPDIF_OUT, 0x05F0, 0x0220, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__CCM_CLKO1, 0x05F0, 0x0220, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__ECSPI1_RDY, 0x05F0, 0x0220, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__GPIO4_IO05, 0x05F0, 0x0220, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__ENET_TX_ER, 0x05F0, 0x0220, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__ESAI_TX_FS, 0x05F4, 0x0224, 0, 0x0830, 1, 0) +MX6_PAD_DECL(GPIO_2__KEY_ROW6, 0x05F4, 0x0224, 2, 0x08D0, 1, 0) +MX6_PAD_DECL(GPIO_2__GPIO1_IO02, 0x05F4, 0x0224, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__SD2_WP, 0x05F4, 0x0224, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__MLB_DATA, 0x05F4, 0x0224, 7, 0x08E0, 1, 0) +MX6_PAD_DECL(GPIO_3__ESAI_RX_HF_CLK, 0x05F8, 0x0228, 0, 0x0834, 1, 0) +MX6_PAD_DECL(GPIO_3__I2C3_SCL, 0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, 0) +MX6_PAD_DECL(GPIO_3__XTALOSC_REF_CLK_24M, 0x05F8, 0x0228, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__CCM_CLKO2, 0x05F8, 0x0228, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__GPIO1_IO03, 0x05F8, 0x0228, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__USB_H1_OC, 0x05F8, 0x0228, 6, 0x0924, 1, 0) +MX6_PAD_DECL(GPIO_3__MLB_CLK, 0x05F8, 0x0228, 7, 0x08DC, 1, 0) +MX6_PAD_DECL(GPIO_4__ESAI_TX_HF_CLK, 0x05FC, 0x022C, 0, 0x0838, 1, 0) +MX6_PAD_DECL(GPIO_4__KEY_COL7, 0x05FC, 0x022C, 2, 0x08C8, 1, 0) +MX6_PAD_DECL(GPIO_4__GPIO1_IO04, 0x05FC, 0x022C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_4__SD2_CD_B, 0x05FC, 0x022C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__ESAI_TX2_RX3, 0x0600, 0x0230, 0, 0x084C, 1, 0) +MX6_PAD_DECL(GPIO_5__KEY_ROW7, 0x0600, 0x0230, 2, 0x08D4, 1, 0) +MX6_PAD_DECL(GPIO_5__CCM_CLKO1, 0x0600, 0x0230, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__GPIO1_IO05, 0x0600, 0x0230, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__I2C3_SCL, 0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0) +MX6_PAD_DECL(GPIO_5__ARM_EVENTI, 0x0600, 0x0230, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__ESAI_TX_CLK, 0x0604, 0x0234, 0, 0x0840, 1, 0) +MX6_PAD_DECL(GPIO_6__I2C3_SDA, 0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0) +MX6_PAD_DECL(GPIO_6__GPIO1_IO06, 0x0604, 0x0234, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__SD2_LCTL, 0x0604, 0x0234, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__MLB_SIG, 0x0604, 0x0234, 7, 0x08E4, 1, 0) +MX6_PAD_DECL(GPIO_7__ESAI_TX4_RX1, 0x0608, 0x0238, 0, 0x0854, 1, 0) +MX6_PAD_DECL(GPIO_7__EPIT1_OUT, 0x0608, 0x0238, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__FLEXCAN1_TX, 0x0608, 0x0238, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__UART2_TX_DATA, 0x0608, 0x0238, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__UART2_RX_DATA, 0x0608, 0x0238, 4, 0x0904, 2, 0) +MX6_PAD_DECL(GPIO_7__GPIO1_IO07, 0x0608, 0x0238, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__SPDIF_LOCK, 0x0608, 0x0238, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__USB_OTG_HOST_MODE, 0x0608, 0x0238, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__I2C4_SCL, 0x0608, 0x0238, 8 | IOMUX_CONFIG_SION, 0x0880, 1, 0) +MX6_PAD_DECL(GPIO_8__ESAI_TX5_RX0, 0x060C, 0x023C, 0, 0x0858, 1, 0) +MX6_PAD_DECL(GPIO_8__XTALOSC_REF_CLK_32K, 0x060C, 0x023C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__EPIT2_OUT, 0x060C, 0x023C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__FLEXCAN1_RX, 0x060C, 0x023C, 3, 0x07C8, 0, 0) +MX6_PAD_DECL(GPIO_8__UART2_TX_DATA, 0x060C, 0x023C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__UART2_RX_DATA, 0x060C, 0x023C, 4, 0x0904, 3, 0) +MX6_PAD_DECL(GPIO_8__GPIO1_IO08, 0x060C, 0x023C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK, 0x060C, 0x023C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE, 0x060C, 0x023C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__I2C4_SDA, 0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, 0) +MX6_PAD_DECL(GPIO_9__ESAI_RX_FS, 0x0610, 0x0240, 0, 0x082C, 1, 0) +MX6_PAD_DECL(GPIO_9__WDOG1_B, 0x0610, 0x0240, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__KEY_COL6, 0x0610, 0x0240, 2, 0x08C4, 1, 0) +MX6_PAD_DECL(GPIO_9__CCM_REF_EN_B, 0x0610, 0x0240, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__PWM1_OUT, 0x0610, 0x0240, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__GPIO1_IO09, 0x0610, 0x0240, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__SD1_WP, 0x0610, 0x0240, 6, 0x092C, 1, 0) +MX6_PAD_DECL(KEY_COL0__ECSPI1_SCLK, 0x062C, 0x0244, 0, 0x07D8, 3, 0) +MX6_PAD_DECL(KEY_COL0__ENET_RX_DATA3, 0x062C, 0x0244, 1, 0x0824, 0, 0) +MX6_PAD_DECL(KEY_COL0__AUD5_TXC, 0x062C, 0x0244, 2, 0x07C0, 1, 0) +MX6_PAD_DECL(KEY_COL0__KEY_COL0, 0x062C, 0x0244, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__UART4_TX_DATA, 0x062C, 0x0244, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__UART4_RX_DATA, 0x062C, 0x0244, 4, 0x0914, 2, 0) +MX6_PAD_DECL(KEY_COL0__GPIO4_IO06, 0x062C, 0x0244, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__DCIC1_OUT, 0x062C, 0x0244, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__ECSPI1_MISO, 0x0630, 0x0248, 0, 0x07DC, 3, 0) +MX6_PAD_DECL(KEY_COL1__ENET_MDIO, 0x0630, 0x0248, 1, 0x0810, 1, 0) +MX6_PAD_DECL(KEY_COL1__AUD5_TXFS, 0x0630, 0x0248, 2, 0x07C4, 1, 0) +MX6_PAD_DECL(KEY_COL1__KEY_COL1, 0x0630, 0x0248, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__UART5_TX_DATA, 0x0630, 0x0248, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__UART5_RX_DATA, 0x0630, 0x0248, 4, 0x091C, 2, 0) +MX6_PAD_DECL(KEY_COL1__GPIO4_IO08, 0x0630, 0x0248, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__SD1_VSELECT, 0x0630, 0x0248, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__ECSPI1_SS1, 0x0634, 0x024C, 0, 0x07E8, 2, 0) +MX6_PAD_DECL(KEY_COL2__ENET_RX_DATA2, 0x0634, 0x024C, 1, 0x0820, 0, 0) +MX6_PAD_DECL(KEY_COL2__FLEXCAN1_TX, 0x0634, 0x024C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__KEY_COL2, 0x0634, 0x024C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__ENET_MDC, 0x0634, 0x024C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__GPIO4_IO10, 0x0634, 0x024C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__USB_H1_PWR_CTL_WAKE, 0x0634, 0x024C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__ECSPI1_SS3, 0x0638, 0x0250, 0, 0x07F0, 1, 0) +MX6_PAD_DECL(KEY_COL3__ENET_CRS, 0x0638, 0x0250, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__HDMI_TX_DDC_SCL, 0x0638, 0x0250, 2, 0x0860, 1, 0) +MX6_PAD_DECL(KEY_COL3__KEY_COL3, 0x0638, 0x0250, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__I2C2_SCL, 0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0) +MX6_PAD_DECL(KEY_COL3__GPIO4_IO12, 0x0638, 0x0250, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__SPDIF_IN, 0x0638, 0x0250, 6, 0x08F0, 3, 0) +MX6_PAD_DECL(KEY_COL4__FLEXCAN2_TX, 0x063C, 0x0254, 0, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__IPU1_SISG4, 0x063C, 0x0254, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__USB_OTG_OC, 0x063C, 0x0254, 2, 0x0920, 1, 0) +MX6_PAD_DECL(KEY_COL4__KEY_COL4, 0x063C, 0x0254, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__UART5_CTS_B, 0x063C, 0x0254, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__UART5_RTS_B, 0x063C, 0x0254, 4, 0x0918, 2, 0) +MX6_PAD_DECL(KEY_COL4__GPIO4_IO14, 0x063C, 0x0254, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__ECSPI1_MOSI, 0x0640, 0x0258, 0, 0x07E0, 3, 0) +MX6_PAD_DECL(KEY_ROW0__ENET_TX_DATA3, 0x0640, 0x0258, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__AUD5_TXD, 0x0640, 0x0258, 2, 0x07B4, 1, 0) +MX6_PAD_DECL(KEY_ROW0__KEY_ROW0, 0x0640, 0x0258, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__UART4_TX_DATA, 0x0640, 0x0258, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__UART4_RX_DATA, 0x0640, 0x0258, 4, 0x0914, 3, 0) +MX6_PAD_DECL(KEY_ROW0__GPIO4_IO07, 0x0640, 0x0258, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__DCIC2_OUT, 0x0640, 0x0258, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__ECSPI1_SS0, 0x0644, 0x025C, 0, 0x07E4, 3, 0) +MX6_PAD_DECL(KEY_ROW1__ENET_COL, 0x0644, 0x025C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__AUD5_RXD, 0x0644, 0x025C, 2, 0x07B0, 1, 0) +MX6_PAD_DECL(KEY_ROW1__KEY_ROW1, 0x0644, 0x025C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__UART5_TX_DATA, 0x0644, 0x025C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__UART5_RX_DATA, 0x0644, 0x025C, 4, 0x091C, 3, 0) +MX6_PAD_DECL(KEY_ROW1__GPIO4_IO09, 0x0644, 0x025C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__SD2_VSELECT, 0x0644, 0x025C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__ECSPI1_SS2, 0x0648, 0x0260, 0, 0x07EC, 1, 0) +MX6_PAD_DECL(KEY_ROW2__ENET_TX_DATA2, 0x0648, 0x0260, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__FLEXCAN1_RX, 0x0648, 0x0260, 2, 0x07C8, 1, 0) +MX6_PAD_DECL(KEY_ROW2__KEY_ROW2, 0x0648, 0x0260, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__SD2_VSELECT, 0x0648, 0x0260, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__GPIO4_IO11, 0x0648, 0x0260, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__HDMI_TX_CEC_LINE, 0x0648, 0x0260, 6, 0x085C, 1, 0) +MX6_PAD_DECL(KEY_ROW3__ASRC_EXT_CLK, 0x064C, 0x0264, 1, 0x0794, 2, 0) +MX6_PAD_DECL(KEY_ROW3__HDMI_TX_DDC_SDA, 0x064C, 0x0264, 2, 0x0864, 1, 0) +MX6_PAD_DECL(KEY_ROW3__KEY_ROW3, 0x064C, 0x0264, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW3__I2C2_SDA, 0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0) +MX6_PAD_DECL(KEY_ROW3__GPIO4_IO13, 0x064C, 0x0264, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW3__SD1_VSELECT, 0x064C, 0x0264, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__FLEXCAN2_RX, 0x0650, 0x0268, 0, 0x07CC, 0, 0) +MX6_PAD_DECL(KEY_ROW4__IPU1_SISG5, 0x0650, 0x0268, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__USB_OTG_PWR, 0x0650, 0x0268, 2, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__KEY_ROW4, 0x0650, 0x0268, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__UART5_CTS_B, 0x0650, 0x0268, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__UART5_RTS_B, 0x0650, 0x0268, 4, 0x0918, 3, 0) +MX6_PAD_DECL(KEY_ROW4__GPIO4_IO15, 0x0650, 0x0268, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__NAND_ALE, 0x0654, 0x026C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__SD4_RESET, 0x0654, 0x026C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__GPIO6_IO08, 0x0654, 0x026C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__NAND_CLE, 0x0658, 0x0270, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__GPIO6_IO07, 0x0658, 0x0270, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS0__NAND_CE0_B, 0x065C, 0x0274, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS0__GPIO6_IO11, 0x065C, 0x0274, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__NAND_CE1_B, 0x0660, 0x0278, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__SD4_VSELECT, 0x0660, 0x0278, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__SD3_VSELECT, 0x0660, 0x0278, 2, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__GPIO6_IO14, 0x0660, 0x0278, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__NAND_CE2_B, 0x0664, 0x027C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__IPU1_SISG0, 0x0664, 0x027C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__ESAI_TX0, 0x0664, 0x027C, 2, 0x0844, 1, 0) +MX6_PAD_DECL(NANDF_CS2__EIM_CRE, 0x0664, 0x027C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__CCM_CLKO2, 0x0664, 0x027C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__GPIO6_IO15, 0x0664, 0x027C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__NAND_CE3_B, 0x0668, 0x0280, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__IPU1_SISG1, 0x0668, 0x0280, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__ESAI_TX1, 0x0668, 0x0280, 2, 0x0848, 1, 0) +MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26, 0x0668, 0x0280, 3, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16, 0x0668, 0x0280, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__I2C4_SDA, 0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, 0) +MX6_PAD_DECL(NANDF_D0__NAND_DATA00, 0x066C, 0x0284, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__SD1_DATA4, 0x066C, 0x0284, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__GPIO2_IO00, 0x066C, 0x0284, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__NAND_DATA01, 0x0670, 0x0288, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__SD1_DATA5, 0x0670, 0x0288, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__GPIO2_IO01, 0x0670, 0x0288, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__NAND_DATA02, 0x0674, 0x028C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__SD1_DATA6, 0x0674, 0x028C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__GPIO2_IO02, 0x0674, 0x028C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__NAND_DATA03, 0x0678, 0x0290, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__SD1_DATA7, 0x0678, 0x0290, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__GPIO2_IO03, 0x0678, 0x0290, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__NAND_DATA04, 0x067C, 0x0294, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__SD2_DATA4, 0x067C, 0x0294, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__GPIO2_IO04, 0x067C, 0x0294, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__NAND_DATA05, 0x0680, 0x0298, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__SD2_DATA5, 0x0680, 0x0298, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__GPIO2_IO05, 0x0680, 0x0298, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__NAND_DATA06, 0x0684, 0x029C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__SD2_DATA6, 0x0684, 0x029C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__GPIO2_IO06, 0x0684, 0x029C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__NAND_DATA07, 0x0688, 0x02A0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__SD2_DATA7, 0x0688, 0x02A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__GPIO2_IO07, 0x0688, 0x02A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__NAND_READY_B, 0x068C, 0x02A4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__GPIO6_IO10, 0x068C, 0x02A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__NAND_WP_B, 0x0690, 0x02A8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__GPIO6_IO09, 0x0690, 0x02A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__I2C4_SCL, 0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0) +MX6_PAD_DECL(RGMII_RD0__HSI_RX_READY, 0x0694, 0x02AC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD0__RGMII_RD0, 0x0694, 0x02AC, 1, 0x0818, 1, 0) +MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25, 0x0694, 0x02AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG, 0x0698, 0x02B0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD1__RGMII_RD1, 0x0698, 0x02B0, 1, 0x081C, 1, 0) +MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27, 0x0698, 0x02B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD2__HSI_TX_DATA, 0x069C, 0x02B4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD2__RGMII_RD2, 0x069C, 0x02B4, 1, 0x0820, 1, 0) +MX6_PAD_DECL(RGMII_RD2__GPIO6_IO28, 0x069C, 0x02B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD3__HSI_TX_WAKE, 0x06A0, 0x02B8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD3__RGMII_RD3, 0x06A0, 0x02B8, 1, 0x0824, 1, 0) +MX6_PAD_DECL(RGMII_RD3__GPIO6_IO29, 0x06A0, 0x02B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__USB_H3_DATA, 0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__RGMII_RX_CTL, 0x06A4, 0x02BC, 1, 0x0828, 1, 0) +MX6_PAD_DECL(RGMII_RX_CTL__GPIO6_IO24, 0x06A4, 0x02BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RXC__USBOH3_H3_STROBE, 0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RXC__USB_H3_STROBE, 0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP) +MX6_PAD_DECL(RGMII_RXC__RGMII_RXC, 0x06A8, 0x02C0, 1, 0x0814, 1, 0) +MX6_PAD_DECL(RGMII_RXC__GPIO6_IO30, 0x06A8, 0x02C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__HSI_TX_READY, 0x06AC, 0x02C4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__RGMII_TD0, 0x06AC, 0x02C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__GPIO6_IO20, 0x06AC, 0x02C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__HSI_RX_FLAG, 0x06B0, 0x02C8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__RGMII_TD1, 0x06B0, 0x02C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__GPIO6_IO21, 0x06B0, 0x02C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__HSI_RX_DATA, 0x06B4, 0x02CC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__RGMII_TD2, 0x06B4, 0x02CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__GPIO6_IO22, 0x06B4, 0x02CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__HSI_RX_WAKE, 0x06B8, 0x02D0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__RGMII_TD3, 0x06B8, 0x02D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__GPIO6_IO23, 0x06B8, 0x02D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__USBOH3_H2_STROBE, 0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE, 0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP) +MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL, 0x06BC, 0x02D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26, 0x06BC, 0x02D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x06BC, 0x02D4, 7 | IOMUX_CONFIG_SION, 0x080C, 1, 0) +MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA, 0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__RGMII_TXC, 0x06C0, 0x02D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK, 0x06C0, 0x02D8, 2, 0x08F4, 1, 0) +MX6_PAD_DECL(RGMII_TXC__GPIO6_IO19, 0x06C0, 0x02D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__XTALOSC_REF_CLK_24M, 0x06C0, 0x02D8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__SD1_CLK, 0x06C4, 0x02DC, 0, 0x0928, 1, 0) +MX6_PAD_DECL(SD1_CLK__GPT_CLKIN, 0x06C4, 0x02DC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__GPIO1_IO20, 0x06C4, 0x02DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__PWM4_OUT, 0x06C8, 0x02E0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1, 0x06C8, 0x02E0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__GPIO1_IO18, 0x06C8, 0x02E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__SD1_DATA0, 0x06CC, 0x02E4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__GPT_CAPTURE1, 0x06CC, 0x02E4, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__GPIO1_IO16, 0x06CC, 0x02E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__SD1_DATA1, 0x06D0, 0x02E8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__PWM3_OUT, 0x06D0, 0x02E8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__GPT_CAPTURE2, 0x06D0, 0x02E8, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__GPIO1_IO17, 0x06D0, 0x02E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__SD1_DATA2, 0x06D4, 0x02EC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__GPT_COMPARE2, 0x06D4, 0x02EC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__PWM2_OUT, 0x06D4, 0x02EC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__WDOG1_B, 0x06D4, 0x02EC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__GPIO1_IO19, 0x06D4, 0x02EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__WDOG1_RESET_B_DEB, 0x06D4, 0x02EC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__SD1_DATA3, 0x06D8, 0x02F0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__GPT_COMPARE3, 0x06D8, 0x02F0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__PWM1_OUT, 0x06D8, 0x02F0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__WDOG2_B, 0x06D8, 0x02F0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21, 0x06D8, 0x02F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB, 0x06D8, 0x02F0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CLK__SD2_CLK, 0x06DC, 0x02F4, 0, 0x0930, 1, 0) +MX6_PAD_DECL(SD2_CLK__KEY_COL5, 0x06DC, 0x02F4, 2, 0x08C0, 3, 0) +MX6_PAD_DECL(SD2_CLK__AUD4_RXFS, 0x06DC, 0x02F4, 3, 0x07A4, 1, 0) +MX6_PAD_DECL(SD2_CLK__GPIO1_IO10, 0x06DC, 0x02F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CMD__KEY_ROW5, 0x06E0, 0x02F8, 2, 0x08CC, 2, 0) +MX6_PAD_DECL(SD2_CMD__AUD4_RXC, 0x06E0, 0x02F8, 3, 0x07A0, 1, 0) +MX6_PAD_DECL(SD2_CMD__GPIO1_IO11, 0x06E0, 0x02F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__SD2_DATA0, 0x06E4, 0x02FC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__AUD4_RXD, 0x06E4, 0x02FC, 3, 0x0798, 1, 0) +MX6_PAD_DECL(SD2_DAT0__KEY_ROW7, 0x06E4, 0x02FC, 4, 0x08D4, 2, 0) +MX6_PAD_DECL(SD2_DAT0__GPIO1_IO15, 0x06E4, 0x02FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__DCIC2_OUT, 0x06E4, 0x02FC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__SD2_DATA1, 0x06E8, 0x0300, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__EIM_CS2_B, 0x06E8, 0x0300, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__AUD4_TXFS, 0x06E8, 0x0300, 3, 0x07AC, 1, 0) +MX6_PAD_DECL(SD2_DAT1__KEY_COL7, 0x06E8, 0x0300, 4, 0x08C8, 2, 0) +MX6_PAD_DECL(SD2_DAT1__GPIO1_IO14, 0x06E8, 0x0300, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__SD2_DATA2, 0x06EC, 0x0304, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__EIM_CS3_B, 0x06EC, 0x0304, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__AUD4_TXD, 0x06EC, 0x0304, 3, 0x079C, 1, 0) +MX6_PAD_DECL(SD2_DAT2__KEY_ROW6, 0x06EC, 0x0304, 4, 0x08D0, 2, 0) +MX6_PAD_DECL(SD2_DAT2__GPIO1_IO13, 0x06EC, 0x0304, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__SD2_DATA3, 0x06F0, 0x0308, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__KEY_COL6, 0x06F0, 0x0308, 2, 0x08C4, 2, 0) +MX6_PAD_DECL(SD2_DAT3__AUD4_TXC, 0x06F0, 0x0308, 3, 0x07A8, 1, 0) +MX6_PAD_DECL(SD2_DAT3__GPIO1_IO12, 0x06F0, 0x0308, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__SD3_CLK, 0x06F4, 0x030C, 0, 0x0934, 1, 0) +MX6_PAD_DECL(SD3_CLK__UART2_CTS_B, 0x06F4, 0x030C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__UART2_RTS_B, 0x06F4, 0x030C, 1, 0x0900, 2, 0) +MX6_PAD_DECL(SD3_CLK__FLEXCAN1_RX, 0x06F4, 0x030C, 2, 0x07C8, 2, 0) +MX6_PAD_DECL(SD3_CLK__GPIO7_IO03, 0x06F4, 0x030C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__UART2_CTS_B, 0x06F8, 0x0310, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__UART2_RTS_B, 0x06F8, 0x0310, 1, 0x0900, 3, 0) +MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX, 0x06F8, 0x0310, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__GPIO7_IO02, 0x06F8, 0x0310, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__SD3_DATA0, 0x06FC, 0x0314, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__UART1_CTS_B, 0x06FC, 0x0314, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__UART1_RTS_B, 0x06FC, 0x0314, 1, 0x08F8, 2, 0) +MX6_PAD_DECL(SD3_DAT0__FLEXCAN2_TX, 0x06FC, 0x0314, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__GPIO7_IO04, 0x06FC, 0x0314, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__SD3_DATA1, 0x0700, 0x0318, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__UART1_CTS_B, 0x0700, 0x0318, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__UART1_RTS_B, 0x0700, 0x0318, 1, 0x08F8, 3, 0) +MX6_PAD_DECL(SD3_DAT1__FLEXCAN2_RX, 0x0700, 0x0318, 2, 0x07CC, 1, 0) +MX6_PAD_DECL(SD3_DAT1__GPIO7_IO05, 0x0700, 0x0318, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT2__SD3_DATA2, 0x0704, 0x031C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT2__GPIO7_IO06, 0x0704, 0x031C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__SD3_DATA3, 0x0708, 0x0320, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__UART3_CTS_B, 0x0708, 0x0320, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__UART3_RTS_B, 0x0708, 0x0320, 1, 0x0908, 4, 0) +MX6_PAD_DECL(SD3_DAT3__GPIO7_IO07, 0x0708, 0x0320, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__SD3_DATA4, 0x070C, 0x0324, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA, 0x070C, 0x0324, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA, 0x070C, 0x0324, 1, 0x0904, 4, 0) +MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01, 0x070C, 0x0324, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__SD3_DATA5, 0x0710, 0x0328, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__UART2_TX_DATA, 0x0710, 0x0328, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__UART2_RX_DATA, 0x0710, 0x0328, 1, 0x0904, 5, 0) +MX6_PAD_DECL(SD3_DAT5__GPIO7_IO00, 0x0710, 0x0328, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__SD3_DATA6, 0x0714, 0x032C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__UART1_TX_DATA, 0x0714, 0x032C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__UART1_RX_DATA, 0x0714, 0x032C, 1, 0x08FC, 2, 0) +MX6_PAD_DECL(SD3_DAT6__GPIO6_IO18, 0x0714, 0x032C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__SD3_DATA7, 0x0718, 0x0330, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__UART1_TX_DATA, 0x0718, 0x0330, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__UART1_RX_DATA, 0x0718, 0x0330, 1, 0x08FC, 3, 0) +MX6_PAD_DECL(SD3_DAT7__GPIO6_IO17, 0x0718, 0x0330, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__SD3_RESET, 0x071C, 0x0334, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__UART3_CTS_B, 0x071C, 0x0334, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__UART3_RTS_B, 0x071C, 0x0334, 1, 0x0908, 5, 0) +MX6_PAD_DECL(SD3_RST__GPIO7_IO08, 0x071C, 0x0334, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__SD4_CLK, 0x0720, 0x0338, 0, 0x0938, 1, 0) +MX6_PAD_DECL(SD4_CLK__NAND_WE_B, 0x0720, 0x0338, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__UART3_TX_DATA, 0x0720, 0x0338, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__UART3_RX_DATA, 0x0720, 0x0338, 2, 0x090C, 2, 0) +MX6_PAD_DECL(SD4_CLK__GPIO7_IO10, 0x0720, 0x0338, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__NAND_RE_B, 0x0724, 0x033C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA, 0x0724, 0x033C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA, 0x0724, 0x033C, 2, 0x090C, 3, 0) +MX6_PAD_DECL(SD4_CMD__GPIO7_IO09, 0x0724, 0x033C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__SD4_DATA0, 0x0728, 0x0340, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__NAND_DQS, 0x0728, 0x0340, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__GPIO2_IO08, 0x0728, 0x0340, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__SD4_DATA1, 0x072C, 0x0344, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__PWM3_OUT, 0x072C, 0x0344, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__GPIO2_IO09, 0x072C, 0x0344, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__SD4_DATA2, 0x0730, 0x0348, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__PWM4_OUT, 0x0730, 0x0348, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__GPIO2_IO10, 0x0730, 0x0348, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT3__SD4_DATA3, 0x0734, 0x034C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT3__GPIO2_IO11, 0x0734, 0x034C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__SD4_DATA4, 0x0738, 0x0350, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__UART2_TX_DATA, 0x0738, 0x0350, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__UART2_RX_DATA, 0x0738, 0x0350, 2, 0x0904, 6, 0) +MX6_PAD_DECL(SD4_DAT4__GPIO2_IO12, 0x0738, 0x0350, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__SD4_DATA5, 0x073C, 0x0354, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__UART2_CTS_B, 0x073C, 0x0354, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__UART2_RTS_B, 0x073C, 0x0354, 2, 0x0900, 4, 0) +MX6_PAD_DECL(SD4_DAT5__GPIO2_IO13, 0x073C, 0x0354, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__SD4_DATA6, 0x0740, 0x0358, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__UART2_CTS_B, 0x0740, 0x0358, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__UART2_RTS_B, 0x0740, 0x0358, 2, 0x0900, 5, 0) +MX6_PAD_DECL(SD4_DAT6__GPIO2_IO14, 0x0740, 0x0358, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__SD4_DATA7, 0x0744, 0x035C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__UART2_TX_DATA, 0x0744, 0x035C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__UART2_RX_DATA, 0x0744, 0x035C, 2, 0x0904, 7, 0) +MX6_PAD_DECL(SD4_DAT7__GPIO2_IO15, 0x0744, 0x035C, 5, 0x0000, 0, 0) + +#endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q-ddr.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q-ddr.h new file mode 100644 index 000000000..c76a92020 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q-ddr.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Boundary Devices Inc. + */ +#ifndef __ASM_ARCH_MX6Q_DDR_H__ +#define __ASM_ARCH_MX6Q_DDR_H__ + +#ifndef CONFIG_MX6Q +#error "wrong CPU" +#endif + +#define MX6_IOM_DRAM_DQM0 0x020e05ac +#define MX6_IOM_DRAM_DQM1 0x020e05b4 +#define MX6_IOM_DRAM_DQM2 0x020e0528 +#define MX6_IOM_DRAM_DQM3 0x020e0520 +#define MX6_IOM_DRAM_DQM4 0x020e0514 +#define MX6_IOM_DRAM_DQM5 0x020e0510 +#define MX6_IOM_DRAM_DQM6 0x020e05bc +#define MX6_IOM_DRAM_DQM7 0x020e05c4 + +#define MX6_IOM_DRAM_CAS 0x020e056c +#define MX6_IOM_DRAM_RAS 0x020e0578 +#define MX6_IOM_DRAM_RESET 0x020e057c +#define MX6_IOM_DRAM_SDCLK_0 0x020e0588 +#define MX6_IOM_DRAM_SDCLK_1 0x020e0594 +#define MX6_IOM_DRAM_SDBA2 0x020e058c +#define MX6_IOM_DRAM_SDCKE0 0x020e0590 +#define MX6_IOM_DRAM_SDCKE1 0x020e0598 +#define MX6_IOM_DRAM_SDODT0 0x020e059c +#define MX6_IOM_DRAM_SDODT1 0x020e05a0 + +#define MX6_IOM_DRAM_SDQS0 0x020e05a8 +#define MX6_IOM_DRAM_SDQS1 0x020e05b0 +#define MX6_IOM_DRAM_SDQS2 0x020e0524 +#define MX6_IOM_DRAM_SDQS3 0x020e051c +#define MX6_IOM_DRAM_SDQS4 0x020e0518 +#define MX6_IOM_DRAM_SDQS5 0x020e050c +#define MX6_IOM_DRAM_SDQS6 0x020e05b8 +#define MX6_IOM_DRAM_SDQS7 0x020e05c0 + +#define MX6_IOM_GRP_B0DS 0x020e0784 +#define MX6_IOM_GRP_B1DS 0x020e0788 +#define MX6_IOM_GRP_B2DS 0x020e0794 +#define MX6_IOM_GRP_B3DS 0x020e079c +#define MX6_IOM_GRP_B4DS 0x020e07a0 +#define MX6_IOM_GRP_B5DS 0x020e07a4 +#define MX6_IOM_GRP_B6DS 0x020e07a8 +#define MX6_IOM_GRP_B7DS 0x020e0748 +#define MX6_IOM_GRP_ADDDS 0x020e074c +#define MX6_IOM_DDRMODE_CTL 0x020e0750 +#define MX6_IOM_GRP_DDRPKE 0x020e0758 +#define MX6_IOM_GRP_DDRMODE 0x020e0774 +#define MX6_IOM_GRP_CTLDS 0x020e078c +#define MX6_IOM_GRP_DDR_TYPE 0x020e0798 + +#endif /*__ASM_ARCH_MX6Q_DDR_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q_pins.h new file mode 100644 index 000000000..dce13d07f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q_pins.h @@ -0,0 +1,1035 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * Auto Generate file, please don't edit it + */ + +#ifndef __ASM_ARCH_MX6_MX6Q_PINS_H__ +#define __ASM_ARCH_MX6_MX6Q_PINS_H__ + +MX6_PAD_DECL(SD2_DAT1__SD2_DATA1, 0x0360, 0x004C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__ECSPI5_SS0, 0x0360, 0x004C, 1, 0x0834, 0, 0) +MX6_PAD_DECL(SD2_DAT1__EIM_CS2_B, 0x0360, 0x004C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__AUD4_TXFS, 0x0360, 0x004C, 3, 0x07C8, 0, 0) +MX6_PAD_DECL(SD2_DAT1__KEY_COL7, 0x0360, 0x004C, 4, 0x08F0, 0, 0) +MX6_PAD_DECL(SD2_DAT1__GPIO1_IO14, 0x0360, 0x004C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__SD2_DATA2, 0x0364, 0x0050, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__ECSPI5_SS1, 0x0364, 0x0050, 1, 0x0838, 0, 0) +MX6_PAD_DECL(SD2_DAT2__EIM_CS3_B, 0x0364, 0x0050, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__AUD4_TXD, 0x0364, 0x0050, 3, 0x07B8, 0, 0) +MX6_PAD_DECL(SD2_DAT2__KEY_ROW6, 0x0364, 0x0050, 4, 0x08F8, 0, 0) +MX6_PAD_DECL(SD2_DAT2__GPIO1_IO13, 0x0364, 0x0050, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__SD2_DATA0, 0x0368, 0x0054, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__ECSPI5_MISO, 0x0368, 0x0054, 1, 0x082C, 0, 0) +MX6_PAD_DECL(SD2_DAT0__AUD4_RXD, 0x0368, 0x0054, 3, 0x07B4, 0, 0) +MX6_PAD_DECL(SD2_DAT0__KEY_ROW7, 0x0368, 0x0054, 4, 0x08FC, 0, 0) +MX6_PAD_DECL(SD2_DAT0__GPIO1_IO15, 0x0368, 0x0054, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__DCIC2_OUT, 0x0368, 0x0054, 6, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA, 0x036C, 0x0058, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__RGMII_TXC, 0x036C, 0x0058, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK, 0x036C, 0x0058, 2, 0x0918, 0, 0) +MX6_PAD_DECL(RGMII_TXC__GPIO6_IO19, 0x036C, 0x0058, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__XTALOSC_REF_CLK_24M, 0x036C, 0x0058, 7, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__HSI_TX_READY, 0x0370, 0x005C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__RGMII_TD0, 0x0370, 0x005C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__GPIO6_IO20, 0x0370, 0x005C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__HSI_RX_FLAG, 0x0374, 0x0060, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__RGMII_TD1, 0x0374, 0x0060, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__GPIO6_IO21, 0x0374, 0x0060, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__HSI_RX_DATA, 0x0378, 0x0064, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__RGMII_TD2, 0x0378, 0x0064, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__GPIO6_IO22, 0x0378, 0x0064, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__HSI_RX_WAKE, 0x037C, 0x0068, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__RGMII_TD3, 0x037C, 0x0068, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__GPIO6_IO23, 0x037C, 0x0068, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__USB_H3_DATA, 0x0380, 0x006C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__RGMII_RX_CTL, 0x0380, 0x006C, 1, 0x0858, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__GPIO6_IO24, 0x0380, 0x006C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD0__HSI_RX_READY, 0x0384, 0x0070, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD0__RGMII_RD0, 0x0384, 0x0070, 1, 0x0848, 0, 0) +MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25, 0x0384, 0x0070, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE, 0x0388, 0x0074, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26, 0x0388, 0x0074, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x0388, 0x0074, 7 | IOMUX_CONFIG_SION, 0x083C, 0, 0) +MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG, 0x038C, 0x0078, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD1__RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0, 0) +MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27, 0x038C, 0x0078, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD2__HSI_TX_DATA, 0x0390, 0x007C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD2__RGMII_RD2, 0x0390, 0x007C, 1, 0x0850, 0, 0) +MX6_PAD_DECL(RGMII_RD2__GPIO6_IO28, 0x0390, 0x007C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD3__HSI_TX_WAKE, 0x0394, 0x0080, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD3__RGMII_RD3, 0x0394, 0x0080, 1, 0x0854, 0, 0) +MX6_PAD_DECL(RGMII_RD3__GPIO6_IO29, 0x0394, 0x0080, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RXC__USB_H3_STROBE, 0x0398, 0x0084, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RXC__RGMII_RXC, 0x0398, 0x0084, 1, 0x0844, 0, 0) +MX6_PAD_DECL(RGMII_RXC__GPIO6_IO30, 0x0398, 0x0084, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__EIM_ADDR25, 0x039C, 0x0088, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__ECSPI4_SS1, 0x039C, 0x0088, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__ECSPI2_RDY, 0x039C, 0x0088, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__IPU1_DI1_PIN12, 0x039C, 0x0088, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__IPU1_DI0_D1_CS, 0x039C, 0x0088, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__GPIO5_IO02, 0x039C, 0x0088, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__HDMI_TX_CEC_LINE, 0x039C, 0x0088, 6, 0x088C, 0, 0) +MX6_PAD_DECL(EIM_EB2__EIM_EB2_B, 0x03A0, 0x008C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__ECSPI1_SS0, 0x03A0, 0x008C, 1, 0x0800, 0, 0) +MX6_PAD_DECL(EIM_EB2__IPU2_CSI1_DATA19, 0x03A0, 0x008C, 3, 0x08D4, 0, 0) +MX6_PAD_DECL(EIM_EB2__HDMI_TX_DDC_SCL, 0x03A0, 0x008C, 4, 0x0890, 0, 0) +MX6_PAD_DECL(EIM_EB2__GPIO2_IO30, 0x03A0, 0x008C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__I2C2_SCL, 0x03A0, 0x008C, 22, 0x08A0, 0, 0) +MX6_PAD_DECL(EIM_EB2__SRC_BOOT_CFG30, 0x03A0, 0x008C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__EIM_DATA16, 0x03A4, 0x0090, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__ECSPI1_SCLK, 0x03A4, 0x0090, 1, 0x07F4, 0, 0) +MX6_PAD_DECL(EIM_D16__IPU1_DI0_PIN05, 0x03A4, 0x0090, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__IPU2_CSI1_DATA18, 0x03A4, 0x0090, 3, 0x08D0, 0, 0) +MX6_PAD_DECL(EIM_D16__HDMI_TX_DDC_SDA, 0x03A4, 0x0090, 4, 0x0894, 0, 0) +MX6_PAD_DECL(EIM_D16__GPIO3_IO16, 0x03A4, 0x0090, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__I2C2_SDA, 0x03A4, 0x0090, 22, 0x08A4, 0, 0) +MX6_PAD_DECL(EIM_D17__EIM_DATA17, 0x03A8, 0x0094, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__ECSPI1_MISO, 0x03A8, 0x0094, 1, 0x07F8, 0, 0) +MX6_PAD_DECL(EIM_D17__IPU1_DI0_PIN06, 0x03A8, 0x0094, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__IPU2_CSI1_PIXCLK, 0x03A8, 0x0094, 3, 0x08E0, 0, 0) +MX6_PAD_DECL(EIM_D17__DCIC1_OUT, 0x03A8, 0x0094, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__GPIO3_IO17, 0x03A8, 0x0094, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__I2C3_SCL, 0x03A8, 0x0094, 22, 0x08A8, 0, 0) +MX6_PAD_DECL(EIM_D18__EIM_DATA18, 0x03AC, 0x0098, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__ECSPI1_MOSI, 0x03AC, 0x0098, 1, 0x07FC, 0, 0) +MX6_PAD_DECL(EIM_D18__IPU1_DI0_PIN07, 0x03AC, 0x0098, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__IPU2_CSI1_DATA17, 0x03AC, 0x0098, 3, 0x08CC, 0, 0) +MX6_PAD_DECL(EIM_D18__IPU1_DI1_D0_CS, 0x03AC, 0x0098, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__GPIO3_IO18, 0x03AC, 0x0098, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__I2C3_SDA, 0x03AC, 0x0098, 22, 0x08AC, 0, 0) +MX6_PAD_DECL(EIM_D19__EIM_DATA19, 0x03B0, 0x009C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__ECSPI1_SS1, 0x03B0, 0x009C, 1, 0x0804, 0, 0) +MX6_PAD_DECL(EIM_D19__IPU1_DI0_PIN08, 0x03B0, 0x009C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__IPU2_CSI1_DATA16, 0x03B0, 0x009C, 3, 0x08C8, 0, 0) +MX6_PAD_DECL(EIM_D19__UART1_CTS_B, 0x03B0, 0x009C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__UART1_RTS_B, 0x03B0, 0x009C, 4, 0x091C, 0, 0) +MX6_PAD_DECL(EIM_D19__GPIO3_IO19, 0x03B0, 0x009C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__EPIT1_OUT, 0x03B0, 0x009C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__EIM_DATA20, 0x03B4, 0x00A0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__ECSPI4_SS0, 0x03B4, 0x00A0, 1, 0x0824, 0, 0) +MX6_PAD_DECL(EIM_D20__IPU1_DI0_PIN16, 0x03B4, 0x00A0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__IPU2_CSI1_DATA15, 0x03B4, 0x00A0, 3, 0x08C4, 0, 0) +MX6_PAD_DECL(EIM_D20__UART1_CTS_B, 0x03B4, 0x00A0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__UART1_RTS_B, 0x03B4, 0x00A0, 4, 0x091C, 1, 0) +MX6_PAD_DECL(EIM_D20__GPIO3_IO20, 0x03B4, 0x00A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__EPIT2_OUT, 0x03B4, 0x00A0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__EIM_DATA21, 0x03B8, 0x00A4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__ECSPI4_SCLK, 0x03B8, 0x00A4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__IPU1_DI0_PIN17, 0x03B8, 0x00A4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__IPU2_CSI1_DATA11, 0x03B8, 0x00A4, 3, 0x08B4, 0, 0) +MX6_PAD_DECL(EIM_D21__USB_OTG_OC, 0x03B8, 0x00A4, 4, 0x0944, 0, 0) +MX6_PAD_DECL(EIM_D21__GPIO3_IO21, 0x03B8, 0x00A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__I2C1_SCL, 0x03B8, 0x00A4, 22, 0x0898, 0, 0) +MX6_PAD_DECL(EIM_D21__SPDIF_IN, 0x03B8, 0x00A4, 7, 0x0914, 0, 0) +MX6_PAD_DECL(EIM_D22__EIM_DATA22, 0x03BC, 0x00A8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__ECSPI4_MISO, 0x03BC, 0x00A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__IPU1_DI0_PIN01, 0x03BC, 0x00A8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__IPU2_CSI1_DATA10, 0x03BC, 0x00A8, 3, 0x08B0, 0, 0) +MX6_PAD_DECL(EIM_D22__USB_OTG_PWR, 0x03BC, 0x00A8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__GPIO3_IO22, 0x03BC, 0x00A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__SPDIF_OUT, 0x03BC, 0x00A8, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__EIM_DATA23, 0x03C0, 0x00AC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI0_D0_CS, 0x03C0, 0x00AC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__UART3_CTS_B, 0x03C0, 0x00AC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__UART3_RTS_B, 0x03C0, 0x00AC, 2, 0x092C, 0, 0) +MX6_PAD_DECL(EIM_D23__UART1_DCD_B, 0x03C0, 0x00AC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU2_CSI1_DATA_EN, 0x03C0, 0x00AC, 4, 0x08D8, 0, 0) +MX6_PAD_DECL(EIM_D23__GPIO3_IO23, 0x03C0, 0x00AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN02, 0x03C0, 0x00AC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN14, 0x03C0, 0x00AC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__EIM_EB3_B, 0x03C4, 0x00B0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__ECSPI4_RDY, 0x03C4, 0x00B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__UART3_CTS_B, 0x03C4, 0x00B0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__UART3_RTS_B, 0x03C4, 0x00B0, 2, 0x092C, 1, 0) +MX6_PAD_DECL(EIM_EB3__UART1_RI_B, 0x03C4, 0x00B0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__IPU2_CSI1_HSYNC, 0x03C4, 0x00B0, 4, 0x08DC, 0, 0) +MX6_PAD_DECL(EIM_EB3__GPIO2_IO31, 0x03C4, 0x00B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__IPU1_DI1_PIN03, 0x03C4, 0x00B0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__SRC_BOOT_CFG31, 0x03C4, 0x00B0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__EIM_DATA24, 0x03C8, 0x00B4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI4_SS2, 0x03C8, 0x00B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__UART3_TX_DATA, 0x03C8, 0x00B4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__UART3_RX_DATA, 0x03C8, 0x00B4, 2, 0x0930, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI1_SS2, 0x03C8, 0x00B4, 3, 0x0808, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI2_SS2, 0x03C8, 0x00B4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__GPIO3_IO24, 0x03C8, 0x00B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__AUD5_RXFS, 0x03C8, 0x00B4, 6, 0x07D8, 0, 0) +MX6_PAD_DECL(EIM_D24__UART1_DTR_B, 0x03C8, 0x00B4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__EIM_DATA25, 0x03CC, 0x00B8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__ECSPI4_SS3, 0x03CC, 0x00B8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__UART3_TX_DATA, 0x03CC, 0x00B8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__UART3_RX_DATA, 0x03CC, 0x00B8, 2, 0x0930, 1, 0) +MX6_PAD_DECL(EIM_D25__ECSPI1_SS3, 0x03CC, 0x00B8, 3, 0x080C, 0, 0) +MX6_PAD_DECL(EIM_D25__ECSPI2_SS3, 0x03CC, 0x00B8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__GPIO3_IO25, 0x03CC, 0x00B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__AUD5_RXC, 0x03CC, 0x00B8, 6, 0x07D4, 0, 0) +MX6_PAD_DECL(EIM_D25__UART1_DSR_B, 0x03CC, 0x00B8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__EIM_DATA26, 0x03D0, 0x00BC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_DI1_PIN11, 0x03D0, 0x00BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_CSI0_DATA01, 0x03D0, 0x00BC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU2_CSI1_DATA14, 0x03D0, 0x00BC, 3, 0x08C0, 0, 0) +MX6_PAD_DECL(EIM_D26__UART2_TX_DATA, 0x03D0, 0x00BC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__UART2_RX_DATA, 0x03D0, 0x00BC, 4, 0x0928, 0, 0) +MX6_PAD_DECL(EIM_D26__GPIO3_IO26, 0x03D0, 0x00BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_SISG2, 0x03D0, 0x00BC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_DISP1_DATA22, 0x03D0, 0x00BC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__EIM_DATA27, 0x03D4, 0x00C0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_DI1_PIN13, 0x03D4, 0x00C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_CSI0_DATA00, 0x03D4, 0x00C0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU2_CSI1_DATA13, 0x03D4, 0x00C0, 3, 0x08BC, 0, 0) +MX6_PAD_DECL(EIM_D27__UART2_TX_DATA, 0x03D4, 0x00C0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__UART2_RX_DATA, 0x03D4, 0x00C0, 4, 0x0928, 1, 0) +MX6_PAD_DECL(EIM_D27__GPIO3_IO27, 0x03D4, 0x00C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_SISG3, 0x03D4, 0x00C0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_DISP1_DATA23, 0x03D4, 0x00C0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__EIM_DATA28, 0x03D8, 0x00C4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__I2C1_SDA, 0x03D8, 0x00C4, 17, 0x089C, 0, 0) +MX6_PAD_DECL(EIM_D28__ECSPI4_MOSI, 0x03D8, 0x00C4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU2_CSI1_DATA12, 0x03D8, 0x00C4, 3, 0x08B8, 0, 0) +MX6_PAD_DECL(EIM_D28__UART2_DTE_CTS_B, 0x03D8, 0x00C4, 4, 0x0924, 0, 0) +MX6_PAD_DECL(EIM_D28__UART2_DTE_RTS_B, 0x03D8, 0x00C4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__GPIO3_IO28, 0x03D8, 0x00C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_EXT_TRIG, 0x03D8, 0x00C4, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_DI0_PIN13, 0x03D8, 0x00C4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__EIM_DATA29, 0x03DC, 0x00C8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_DI1_PIN15, 0x03DC, 0x00C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__ECSPI4_SS0, 0x03DC, 0x00C8, 2, 0x0824, 1, 0) +MX6_PAD_DECL(EIM_D29__UART2_CTS_B, 0x03DC, 0x00C8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__UART2_RTS_B, 0x03DC, 0x00C8, 4, 0x0924, 1, 0) +MX6_PAD_DECL(EIM_D29__GPIO3_IO29, 0x03DC, 0x00C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU2_CSI1_VSYNC, 0x03DC, 0x00C8, 6, 0x08E4, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_DI0_PIN14, 0x03DC, 0x00C8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__EIM_DATA30, 0x03E0, 0x00CC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_DISP1_DATA21, 0x03E0, 0x00CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_DI0_PIN11, 0x03E0, 0x00CC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_CSI0_DATA03, 0x03E0, 0x00CC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__UART3_CTS_B, 0x03E0, 0x00CC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__UART3_RTS_B, 0x03E0, 0x00CC, 4, 0x092C, 2, 0) +MX6_PAD_DECL(EIM_D30__GPIO3_IO30, 0x03E0, 0x00CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__USB_H1_OC, 0x03E0, 0x00CC, 6, 0x0948, 0, 0) +MX6_PAD_DECL(EIM_D31__EIM_DATA31, 0x03E4, 0x00D0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_DISP1_DATA20, 0x03E4, 0x00D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_DI0_PIN12, 0x03E4, 0x00D0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_CSI0_DATA02, 0x03E4, 0x00D0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__UART3_CTS_B, 0x03E4, 0x00D0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__UART3_RTS_B, 0x03E4, 0x00D0, 4, 0x092C, 3, 0) +MX6_PAD_DECL(EIM_D31__GPIO3_IO31, 0x03E4, 0x00D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__USB_H1_PWR, 0x03E4, 0x00D0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__EIM_ADDR24, 0x03E8, 0x00D4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_DISP1_DATA19, 0x03E8, 0x00D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU2_CSI1_DATA19, 0x03E8, 0x00D4, 2, 0x08D4, 1, 0) +MX6_PAD_DECL(EIM_A24__IPU2_SISG2, 0x03E8, 0x00D4, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_SISG2, 0x03E8, 0x00D4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__GPIO5_IO04, 0x03E8, 0x00D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__SRC_BOOT_CFG24, 0x03E8, 0x00D4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__EIM_ADDR23, 0x03EC, 0x00D8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_DISP1_DATA18, 0x03EC, 0x00D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU2_CSI1_DATA18, 0x03EC, 0x00D8, 2, 0x08D0, 1, 0) +MX6_PAD_DECL(EIM_A23__IPU2_SISG3, 0x03EC, 0x00D8, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_SISG3, 0x03EC, 0x00D8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__GPIO6_IO06, 0x03EC, 0x00D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__SRC_BOOT_CFG23, 0x03EC, 0x00D8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__EIM_ADDR22, 0x03F0, 0x00DC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__IPU1_DISP1_DATA17, 0x03F0, 0x00DC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__IPU2_CSI1_DATA17, 0x03F0, 0x00DC, 2, 0x08CC, 1, 0) +MX6_PAD_DECL(EIM_A22__GPIO2_IO16, 0x03F0, 0x00DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__SRC_BOOT_CFG22, 0x03F0, 0x00DC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__EIM_ADDR21, 0x03F4, 0x00E0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__IPU1_DISP1_DATA16, 0x03F4, 0x00E0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__IPU2_CSI1_DATA16, 0x03F4, 0x00E0, 2, 0x08C8, 1, 0) +MX6_PAD_DECL(EIM_A21__GPIO2_IO17, 0x03F4, 0x00E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__SRC_BOOT_CFG21, 0x03F4, 0x00E0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__EIM_ADDR20, 0x03F8, 0x00E4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__IPU1_DISP1_DATA15, 0x03F8, 0x00E4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__IPU2_CSI1_DATA15, 0x03F8, 0x00E4, 2, 0x08C4, 1, 0) +MX6_PAD_DECL(EIM_A20__GPIO2_IO18, 0x03F8, 0x00E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__SRC_BOOT_CFG20, 0x03F8, 0x00E4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__EIM_ADDR19, 0x03FC, 0x00E8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__IPU1_DISP1_DATA14, 0x03FC, 0x00E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__IPU2_CSI1_DATA14, 0x03FC, 0x00E8, 2, 0x08C0, 1, 0) +MX6_PAD_DECL(EIM_A19__GPIO2_IO19, 0x03FC, 0x00E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__SRC_BOOT_CFG19, 0x03FC, 0x00E8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__EIM_ADDR18, 0x0400, 0x00EC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__IPU1_DISP1_DATA13, 0x0400, 0x00EC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__IPU2_CSI1_DATA13, 0x0400, 0x00EC, 2, 0x08BC, 1, 0) +MX6_PAD_DECL(EIM_A18__GPIO2_IO20, 0x0400, 0x00EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__SRC_BOOT_CFG18, 0x0400, 0x00EC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__EIM_ADDR17, 0x0404, 0x00F0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__IPU1_DISP1_DATA12, 0x0404, 0x00F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__IPU2_CSI1_DATA12, 0x0404, 0x00F0, 2, 0x08B8, 1, 0) +MX6_PAD_DECL(EIM_A17__GPIO2_IO21, 0x0404, 0x00F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__SRC_BOOT_CFG17, 0x0404, 0x00F0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__EIM_ADDR16, 0x0408, 0x00F4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__IPU1_DI1_DISP_CLK, 0x0408, 0x00F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__IPU2_CSI1_PIXCLK, 0x0408, 0x00F4, 2, 0x08E0, 1, 0) +MX6_PAD_DECL(EIM_A16__GPIO2_IO22, 0x0408, 0x00F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__SRC_BOOT_CFG16, 0x0408, 0x00F4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__EIM_CS0_B, 0x040C, 0x00F8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__IPU1_DI1_PIN05, 0x040C, 0x00F8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__ECSPI2_SCLK, 0x040C, 0x00F8, 2, 0x0810, 0, 0) +MX6_PAD_DECL(EIM_CS0__GPIO2_IO23, 0x040C, 0x00F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__EIM_CS1_B, 0x0410, 0x00FC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__IPU1_DI1_PIN06, 0x0410, 0x00FC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__ECSPI2_MOSI, 0x0410, 0x00FC, 2, 0x0818, 0, 0) +MX6_PAD_DECL(EIM_CS1__GPIO2_IO24, 0x0410, 0x00FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__EIM_OE_B, 0x0414, 0x0100, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__IPU1_DI1_PIN07, 0x0414, 0x0100, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__ECSPI2_MISO, 0x0414, 0x0100, 2, 0x0814, 0, 0) +MX6_PAD_DECL(EIM_OE__GPIO2_IO25, 0x0414, 0x0100, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__EIM_RW, 0x0418, 0x0104, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__IPU1_DI1_PIN08, 0x0418, 0x0104, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__ECSPI2_SS0, 0x0418, 0x0104, 2, 0x081C, 0, 0) +MX6_PAD_DECL(EIM_RW__GPIO2_IO26, 0x0418, 0x0104, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__SRC_BOOT_CFG29, 0x0418, 0x0104, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__EIM_LBA_B, 0x041C, 0x0108, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__IPU1_DI1_PIN17, 0x041C, 0x0108, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__ECSPI2_SS1, 0x041C, 0x0108, 2, 0x0820, 0, 0) +MX6_PAD_DECL(EIM_LBA__GPIO2_IO27, 0x041C, 0x0108, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__SRC_BOOT_CFG26, 0x041C, 0x0108, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__EIM_EB0_B, 0x0420, 0x010C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__IPU1_DISP1_DATA11, 0x0420, 0x010C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__IPU2_CSI1_DATA11, 0x0420, 0x010C, 2, 0x08B4, 1, 0) +MX6_PAD_DECL(EIM_EB0__CCM_PMIC_READY, 0x0420, 0x010C, 4, 0x07F0, 0, 0) +MX6_PAD_DECL(EIM_EB0__GPIO2_IO28, 0x0420, 0x010C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__SRC_BOOT_CFG27, 0x0420, 0x010C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__EIM_EB1_B, 0x0424, 0x0110, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__IPU1_DISP1_DATA10, 0x0424, 0x0110, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__IPU2_CSI1_DATA10, 0x0424, 0x0110, 2, 0x08B0, 1, 0) +MX6_PAD_DECL(EIM_EB1__GPIO2_IO29, 0x0424, 0x0110, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__SRC_BOOT_CFG28, 0x0424, 0x0110, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__EIM_AD00, 0x0428, 0x0114, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__IPU1_DISP1_DATA09, 0x0428, 0x0114, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__IPU2_CSI1_DATA09, 0x0428, 0x0114, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__GPIO3_IO00, 0x0428, 0x0114, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__SRC_BOOT_CFG00, 0x0428, 0x0114, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__EIM_AD01, 0x042C, 0x0118, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__IPU1_DISP1_DATA08, 0x042C, 0x0118, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__IPU2_CSI1_DATA08, 0x042C, 0x0118, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__GPIO3_IO01, 0x042C, 0x0118, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__SRC_BOOT_CFG01, 0x042C, 0x0118, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__EIM_AD02, 0x0430, 0x011C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__IPU1_DISP1_DATA07, 0x0430, 0x011C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__IPU2_CSI1_DATA07, 0x0430, 0x011C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__GPIO3_IO02, 0x0430, 0x011C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__SRC_BOOT_CFG02, 0x0430, 0x011C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__EIM_AD03, 0x0434, 0x0120, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__IPU1_DISP1_DATA06, 0x0434, 0x0120, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__IPU2_CSI1_DATA06, 0x0434, 0x0120, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__GPIO3_IO03, 0x0434, 0x0120, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__SRC_BOOT_CFG03, 0x0434, 0x0120, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__EIM_AD04, 0x0438, 0x0124, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__IPU1_DISP1_DATA05, 0x0438, 0x0124, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__IPU2_CSI1_DATA05, 0x0438, 0x0124, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__GPIO3_IO04, 0x0438, 0x0124, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__SRC_BOOT_CFG04, 0x0438, 0x0124, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__EIM_AD05, 0x043C, 0x0128, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__IPU1_DISP1_DATA04, 0x043C, 0x0128, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__IPU2_CSI1_DATA04, 0x043C, 0x0128, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__GPIO3_IO05, 0x043C, 0x0128, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__SRC_BOOT_CFG05, 0x043C, 0x0128, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__EIM_AD06, 0x0440, 0x012C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__IPU1_DISP1_DATA03, 0x0440, 0x012C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__IPU2_CSI1_DATA03, 0x0440, 0x012C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__GPIO3_IO06, 0x0440, 0x012C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__SRC_BOOT_CFG06, 0x0440, 0x012C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__EIM_AD07, 0x0444, 0x0130, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__IPU1_DISP1_DATA02, 0x0444, 0x0130, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__IPU2_CSI1_DATA02, 0x0444, 0x0130, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__GPIO3_IO07, 0x0444, 0x0130, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__SRC_BOOT_CFG07, 0x0444, 0x0130, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__EIM_AD08, 0x0448, 0x0134, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__IPU1_DISP1_DATA01, 0x0448, 0x0134, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__IPU2_CSI1_DATA01, 0x0448, 0x0134, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__GPIO3_IO08, 0x0448, 0x0134, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__SRC_BOOT_CFG08, 0x0448, 0x0134, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__EIM_AD09, 0x044C, 0x0138, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__IPU1_DISP1_DATA00, 0x044C, 0x0138, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__IPU2_CSI1_DATA00, 0x044C, 0x0138, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__GPIO3_IO09, 0x044C, 0x0138, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__SRC_BOOT_CFG09, 0x044C, 0x0138, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__EIM_AD10, 0x0450, 0x013C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__IPU1_DI1_PIN15, 0x0450, 0x013C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__IPU2_CSI1_DATA_EN, 0x0450, 0x013C, 2, 0x08D8, 1, 0) +MX6_PAD_DECL(EIM_DA10__GPIO3_IO10, 0x0450, 0x013C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__SRC_BOOT_CFG10, 0x0450, 0x013C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__EIM_AD11, 0x0454, 0x0140, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__IPU1_DI1_PIN02, 0x0454, 0x0140, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__IPU2_CSI1_HSYNC, 0x0454, 0x0140, 2, 0x08DC, 1, 0) +MX6_PAD_DECL(EIM_DA11__GPIO3_IO11, 0x0454, 0x0140, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__SRC_BOOT_CFG11, 0x0454, 0x0140, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__EIM_AD12, 0x0458, 0x0144, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__IPU1_DI1_PIN03, 0x0458, 0x0144, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__IPU2_CSI1_VSYNC, 0x0458, 0x0144, 2, 0x08E4, 1, 0) +MX6_PAD_DECL(EIM_DA12__GPIO3_IO12, 0x0458, 0x0144, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__SRC_BOOT_CFG12, 0x0458, 0x0144, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__EIM_AD13, 0x045C, 0x0148, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__IPU1_DI1_D0_CS, 0x045C, 0x0148, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__GPIO3_IO13, 0x045C, 0x0148, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__SRC_BOOT_CFG13, 0x045C, 0x0148, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__EIM_AD14, 0x0460, 0x014C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__IPU1_DI1_D1_CS, 0x0460, 0x014C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__GPIO3_IO14, 0x0460, 0x014C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__SRC_BOOT_CFG14, 0x0460, 0x014C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__EIM_AD15, 0x0464, 0x0150, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN01, 0x0464, 0x0150, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN04, 0x0464, 0x0150, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__GPIO3_IO15, 0x0464, 0x0150, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__SRC_BOOT_CFG15, 0x0464, 0x0150, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__EIM_WAIT_B, 0x0468, 0x0154, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__EIM_DTACK_B, 0x0468, 0x0154, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__GPIO5_IO00, 0x0468, 0x0154, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__SRC_BOOT_CFG25, 0x0468, 0x0154, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__EIM_BCLK, 0x046C, 0x0158, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__IPU1_DI1_PIN16, 0x046C, 0x0158, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__GPIO6_IO31, 0x046C, 0x0158, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, 0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_DISP_CLK__IPU2_DI0_DISP_CLK, 0x0470, 0x015C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__GPIO4_IO16, 0x0470, 0x015C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__IPU1_DI0_PIN15, 0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN15__IPU2_DI0_PIN15, 0x0474, 0x0160, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__AUD6_TXC, 0x0474, 0x0160, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__GPIO4_IO17, 0x0474, 0x0160, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__IPU1_DI0_PIN02, 0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN2__IPU2_DI0_PIN02, 0x0478, 0x0164, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__AUD6_TXD, 0x0478, 0x0164, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__GPIO4_IO18, 0x0478, 0x0164, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__IPU1_DI0_PIN03, 0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN3__IPU2_DI0_PIN03, 0x047C, 0x0168, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__AUD6_TXFS, 0x047C, 0x0168, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__GPIO4_IO19, 0x047C, 0x0168, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__IPU1_DI0_PIN04, 0x0480, 0x016C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__IPU2_DI0_PIN04, 0x0480, 0x016C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__AUD6_RXD, 0x0480, 0x016C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__SD1_WP, 0x0480, 0x016C, 3, 0x094C, 0, 0) +MX6_PAD_DECL(DI0_PIN4__GPIO4_IO20, 0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT0__IPU1_DISP0_DATA00, 0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT0__IPU2_DISP0_DATA00, 0x0484, 0x0170, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__ECSPI3_SCLK, 0x0484, 0x0170, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__GPIO4_IO21, 0x0484, 0x0170, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01, 0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT1__IPU2_DISP0_DATA01, 0x0488, 0x0174, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI, 0x0488, 0x0174, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22, 0x0488, 0x0174, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02, 0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT2__IPU2_DISP0_DATA02, 0x048C, 0x0178, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO, 0x048C, 0x0178, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23, 0x048C, 0x0178, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__IPU1_DISP0_DATA03, 0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT3__IPU2_DISP0_DATA03, 0x0490, 0x017C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__ECSPI3_SS0, 0x0490, 0x017C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__GPIO4_IO24, 0x0490, 0x017C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__IPU1_DISP0_DATA04, 0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT4__IPU2_DISP0_DATA04, 0x0494, 0x0180, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__ECSPI3_SS1, 0x0494, 0x0180, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__GPIO4_IO25, 0x0494, 0x0180, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__IPU1_DISP0_DATA05, 0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT5__IPU2_DISP0_DATA05, 0x0498, 0x0184, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__ECSPI3_SS2, 0x0498, 0x0184, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__AUD6_RXFS, 0x0498, 0x0184, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__GPIO4_IO26, 0x0498, 0x0184, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__IPU1_DISP0_DATA06, 0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT6__IPU2_DISP0_DATA06, 0x049C, 0x0188, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__ECSPI3_SS3, 0x049C, 0x0188, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__AUD6_RXC, 0x049C, 0x0188, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__GPIO4_IO27, 0x049C, 0x0188, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__IPU1_DISP0_DATA07, 0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT7__IPU2_DISP0_DATA07, 0x04A0, 0x018C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__ECSPI3_RDY, 0x04A0, 0x018C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__GPIO4_IO28, 0x04A0, 0x018C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__IPU1_DISP0_DATA08, 0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT8__IPU2_DISP0_DATA08, 0x04A4, 0x0190, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__PWM1_OUT, 0x04A4, 0x0190, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__WDOG1_B, 0x04A4, 0x0190, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__GPIO4_IO29, 0x04A4, 0x0190, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__IPU1_DISP0_DATA09, 0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT9__IPU2_DISP0_DATA09, 0x04A8, 0x0194, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__PWM2_OUT, 0x04A8, 0x0194, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__WDOG2_B, 0x04A8, 0x0194, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__GPIO4_IO30, 0x04A8, 0x0194, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10, 0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT10__IPU2_DISP0_DATA10, 0x04AC, 0x0198, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31, 0x04AC, 0x0198, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11, 0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT11__IPU2_DISP0_DATA11, 0x04B0, 0x019C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT11__GPIO5_IO05, 0x04B0, 0x019C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT12__IPU1_DISP0_DATA12, 0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT12__IPU2_DISP0_DATA12, 0x04B4, 0x01A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT12__GPIO5_IO06, 0x04B4, 0x01A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__IPU1_DISP0_DATA13, 0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT13__IPU2_DISP0_DATA13, 0x04B8, 0x01A4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__AUD5_RXFS, 0x04B8, 0x01A4, 3, 0x07D8, 1, 0) +MX6_PAD_DECL(DISP0_DAT13__GPIO5_IO07, 0x04B8, 0x01A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__IPU1_DISP0_DATA14, 0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT14__IPU2_DISP0_DATA14, 0x04BC, 0x01A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__AUD5_RXC, 0x04BC, 0x01A8, 3, 0x07D4, 1, 0) +MX6_PAD_DECL(DISP0_DAT14__GPIO5_IO08, 0x04BC, 0x01A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__IPU1_DISP0_DATA15, 0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT15__IPU2_DISP0_DATA15, 0x04C0, 0x01AC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__ECSPI1_SS1, 0x04C0, 0x01AC, 2, 0x0804, 1, 0) +MX6_PAD_DECL(DISP0_DAT15__ECSPI2_SS1, 0x04C0, 0x01AC, 3, 0x0820, 1, 0) +MX6_PAD_DECL(DISP0_DAT15__GPIO5_IO09, 0x04C0, 0x01AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__IPU1_DISP0_DATA16, 0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT16__IPU2_DISP0_DATA16, 0x04C4, 0x01B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__ECSPI2_MOSI, 0x04C4, 0x01B0, 2, 0x0818, 1, 0) +MX6_PAD_DECL(DISP0_DAT16__AUD5_TXC, 0x04C4, 0x01B0, 3, 0x07DC, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__SDMA_EXT_EVENT0, 0x04C4, 0x01B0, 4, 0x090C, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__GPIO5_IO10, 0x04C4, 0x01B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__IPU1_DISP0_DATA17, 0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT17__IPU2_DISP0_DATA17, 0x04C8, 0x01B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__ECSPI2_MISO, 0x04C8, 0x01B4, 2, 0x0814, 1, 0) +MX6_PAD_DECL(DISP0_DAT17__AUD5_TXD, 0x04C8, 0x01B4, 3, 0x07D0, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__SDMA_EXT_EVENT1, 0x04C8, 0x01B4, 4, 0x0910, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__GPIO5_IO11, 0x04C8, 0x01B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__IPU1_DISP0_DATA18, 0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT18__IPU2_DISP0_DATA18, 0x04CC, 0x01B8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__ECSPI2_SS0, 0x04CC, 0x01B8, 2, 0x081C, 1, 0) +MX6_PAD_DECL(DISP0_DAT18__AUD5_TXFS, 0x04CC, 0x01B8, 3, 0x07E0, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__AUD4_RXFS, 0x04CC, 0x01B8, 4, 0x07C0, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__GPIO5_IO12, 0x04CC, 0x01B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__EIM_CS2_B, 0x04CC, 0x01B8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__IPU1_DISP0_DATA19, 0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT19__IPU2_DISP0_DATA19, 0x04D0, 0x01BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__ECSPI2_SCLK, 0x04D0, 0x01BC, 2, 0x0810, 1, 0) +MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD, 0x04D0, 0x01BC, 3, 0x07CC, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC, 0x04D0, 0x01BC, 4, 0x07BC, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13, 0x04D0, 0x01BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B, 0x04D0, 0x01BC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__IPU1_DISP0_DATA20, 0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT20__IPU2_DISP0_DATA20, 0x04D4, 0x01C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__ECSPI1_SCLK, 0x04D4, 0x01C0, 2, 0x07F4, 1, 0) +MX6_PAD_DECL(DISP0_DAT20__AUD4_TXC, 0x04D4, 0x01C0, 3, 0x07C4, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__GPIO5_IO14, 0x04D4, 0x01C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__IPU1_DISP0_DATA21, 0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT21__IPU2_DISP0_DATA21, 0x04D8, 0x01C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__ECSPI1_MOSI, 0x04D8, 0x01C4, 2, 0x07FC, 1, 0) +MX6_PAD_DECL(DISP0_DAT21__AUD4_TXD, 0x04D8, 0x01C4, 3, 0x07B8, 1, 0) +MX6_PAD_DECL(DISP0_DAT21__GPIO5_IO15, 0x04D8, 0x01C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__IPU1_DISP0_DATA22, 0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT22__IPU2_DISP0_DATA22, 0x04DC, 0x01C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__ECSPI1_MISO, 0x04DC, 0x01C8, 2, 0x07F8, 1, 0) +MX6_PAD_DECL(DISP0_DAT22__AUD4_TXFS, 0x04DC, 0x01C8, 3, 0x07C8, 1, 0) +MX6_PAD_DECL(DISP0_DAT22__GPIO5_IO16, 0x04DC, 0x01C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__IPU1_DISP0_DATA23, 0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT23__IPU2_DISP0_DATA23, 0x04E0, 0x01CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__ECSPI1_SS0, 0x04E0, 0x01CC, 2, 0x0800, 1, 0) +MX6_PAD_DECL(DISP0_DAT23__AUD4_RXD, 0x04E0, 0x01CC, 3, 0x07B4, 1, 0) +MX6_PAD_DECL(DISP0_DAT23__GPIO5_IO17, 0x04E0, 0x01CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ENET_MDIO, 0x04E4, 0x01D0, 1, 0x0840, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK, 0x04E4, 0x01D0, 2, 0x086C, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT, 0x04E4, 0x01D0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22, 0x04E4, 0x01D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK, 0x04E4, 0x01D0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x04E8, 0x01D4, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS, 0x04E8, 0x01D4, 2, 0x085C, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23, 0x04E8, 0x01D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__USB_OTG_ID, 0x04EC, 0x01D8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__ENET_RX_ER, 0x04EC, 0x01D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__ESAI_RX_HF_CLK, 0x04EC, 0x01D8, 2, 0x0864, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__SPDIF_IN, 0x04EC, 0x01D8, 3, 0x0914, 1, 0) +MX6_PAD_DECL(ENET_RX_ER__ENET_1588_EVENT2_OUT, 0x04EC, 0x01D8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__GPIO1_IO24, 0x04EC, 0x01D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__ENET_RX_EN, 0x04F0, 0x01DC, 1, 0x0858, 1, 0) +MX6_PAD_DECL(ENET_CRS_DV__ESAI_TX_CLK, 0x04F0, 0x01DC, 2, 0x0870, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__SPDIF_EXT_CLK, 0x04F0, 0x01DC, 3, 0x0918, 1, 0) +MX6_PAD_DECL(ENET_CRS_DV__GPIO1_IO25, 0x04F0, 0x01DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD1__MLB_SIG, 0x04F4, 0x01E0, 0, 0x0908, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ENET_RX_DATA1, 0x04F4, 0x01E0, 1, 0x084C, 1, 0) +MX6_PAD_DECL(ENET_RXD1__ESAI_TX_FS, 0x04F4, 0x01E0, 2, 0x0860, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ENET_1588_EVENT3_OUT, 0x04F4, 0x01E0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD1__GPIO1_IO26, 0x04F4, 0x01E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD0__ENET_RX_DATA0, 0x04F8, 0x01E4, 1, 0x0848, 1, 0) +MX6_PAD_DECL(ENET_RXD0__ESAI_TX_HF_CLK, 0x04F8, 0x01E4, 2, 0x0868, 0, 0) +MX6_PAD_DECL(ENET_RXD0__SPDIF_OUT, 0x04F8, 0x01E4, 3, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD0__GPIO1_IO27, 0x04F8, 0x01E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__ENET_TX_EN, 0x04FC, 0x01E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__ESAI_TX3_RX2, 0x04FC, 0x01E8, 2, 0x0880, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__GPIO1_IO28, 0x04FC, 0x01E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__MLB_CLK, 0x0500, 0x01EC, 0, 0x0900, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ENET_TX_DATA1, 0x0500, 0x01EC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ESAI_TX2_RX3, 0x0500, 0x01EC, 2, 0x087C, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ENET_1588_EVENT0_IN, 0x0500, 0x01EC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__GPIO1_IO29, 0x0500, 0x01EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD0__ENET_TX_DATA0, 0x0504, 0x01F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD0__ESAI_TX4_RX1, 0x0504, 0x01F0, 2, 0x0884, 0, 0) +MX6_PAD_DECL(ENET_TXD0__GPIO1_IO30, 0x0504, 0x01F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__MLB_DATA, 0x0508, 0x01F4, 0, 0x0904, 0, 0) +MX6_PAD_DECL(ENET_MDC__ENET_MDC, 0x0508, 0x01F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__ESAI_TX5_RX0, 0x0508, 0x01F4, 2, 0x0888, 0, 0) +MX6_PAD_DECL(ENET_MDC__ENET_1588_EVENT1_IN, 0x0508, 0x01F4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__GPIO1_IO31, 0x0508, 0x01F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__ECSPI1_SCLK, 0x05C8, 0x01F8, 0, 0x07F4, 2, 0) +MX6_PAD_DECL(KEY_COL0__ENET_RX_DATA3, 0x05C8, 0x01F8, 1, 0x0854, 1, 0) +MX6_PAD_DECL(KEY_COL0__AUD5_TXC, 0x05C8, 0x01F8, 2, 0x07DC, 1, 0) +MX6_PAD_DECL(KEY_COL0__KEY_COL0, 0x05C8, 0x01F8, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__UART4_TX_DATA, 0x05C8, 0x01F8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__UART4_RX_DATA, 0x05C8, 0x01F8, 4, 0x0938, 0, 0) +MX6_PAD_DECL(KEY_COL0__GPIO4_IO06, 0x05C8, 0x01F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__DCIC1_OUT, 0x05C8, 0x01F8, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__ECSPI1_MOSI, 0x05CC, 0x01FC, 0, 0x07FC, 2, 0) +MX6_PAD_DECL(KEY_ROW0__ENET_TX_DATA3, 0x05CC, 0x01FC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__AUD5_TXD, 0x05CC, 0x01FC, 2, 0x07D0, 1, 0) +MX6_PAD_DECL(KEY_ROW0__KEY_ROW0, 0x05CC, 0x01FC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__UART4_TX_DATA, 0x05CC, 0x01FC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__UART4_RX_DATA, 0x05CC, 0x01FC, 4, 0x0938, 1, 0) +MX6_PAD_DECL(KEY_ROW0__GPIO4_IO07, 0x05CC, 0x01FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__DCIC2_OUT, 0x05CC, 0x01FC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__ECSPI1_MISO, 0x05D0, 0x0200, 0, 0x07F8, 2, 0) +MX6_PAD_DECL(KEY_COL1__ENET_MDIO, 0x05D0, 0x0200, 1, 0x0840, 1, 0) +MX6_PAD_DECL(KEY_COL1__AUD5_TXFS, 0x05D0, 0x0200, 2, 0x07E0, 1, 0) +MX6_PAD_DECL(KEY_COL1__KEY_COL1, 0x05D0, 0x0200, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__UART5_TX_DATA, 0x05D0, 0x0200, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__UART5_RX_DATA, 0x05D0, 0x0200, 4, 0x0940, 0, 0) +MX6_PAD_DECL(KEY_COL1__GPIO4_IO08, 0x05D0, 0x0200, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__SD1_VSELECT, 0x05D0, 0x0200, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__ECSPI1_SS0, 0x05D4, 0x0204, 0, 0x0800, 2, 0) +MX6_PAD_DECL(KEY_ROW1__ENET_COL, 0x05D4, 0x0204, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__AUD5_RXD, 0x05D4, 0x0204, 2, 0x07CC, 1, 0) +MX6_PAD_DECL(KEY_ROW1__KEY_ROW1, 0x05D4, 0x0204, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__UART5_TX_DATA, 0x05D4, 0x0204, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__UART5_RX_DATA, 0x05D4, 0x0204, 4, 0x0940, 1, 0) +MX6_PAD_DECL(KEY_ROW1__GPIO4_IO09, 0x05D4, 0x0204, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__SD2_VSELECT, 0x05D4, 0x0204, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__ECSPI1_SS1, 0x05D8, 0x0208, 0, 0x0804, 2, 0) +MX6_PAD_DECL(KEY_COL2__ENET_RX_DATA2, 0x05D8, 0x0208, 1, 0x0850, 1, 0) +MX6_PAD_DECL(KEY_COL2__FLEXCAN1_TX, 0x05D8, 0x0208, 2, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__KEY_COL2, 0x05D8, 0x0208, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__ENET_MDC, 0x05D8, 0x0208, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__GPIO4_IO10, 0x05D8, 0x0208, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__USB_H1_PWR_CTL_WAKE, 0x05D8, 0x0208, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__ECSPI1_SS2, 0x05DC, 0x020C, 0, 0x0808, 1, 0) +MX6_PAD_DECL(KEY_ROW2__ENET_TX_DATA2, 0x05DC, 0x020C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__FLEXCAN1_RX, 0x05DC, 0x020C, 2, 0x07E4, 0, 0) +MX6_PAD_DECL(KEY_ROW2__KEY_ROW2, 0x05DC, 0x020C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__SD2_VSELECT, 0x05DC, 0x020C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__GPIO4_IO11, 0x05DC, 0x020C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__HDMI_TX_CEC_LINE, 0x05DC, 0x020C, 6, 0x088C, 1, 0) +MX6_PAD_DECL(KEY_COL3__ECSPI1_SS3, 0x05E0, 0x0210, 0, 0x080C, 1, 0) +MX6_PAD_DECL(KEY_COL3__ENET_CRS, 0x05E0, 0x0210, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__HDMI_TX_DDC_SCL, 0x05E0, 0x0210, 2, 0x0890, 1, 0) +MX6_PAD_DECL(KEY_COL3__KEY_COL3, 0x05E0, 0x0210, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__I2C2_SCL, 0x05E0, 0x0210, 20, 0x08A0, 1, 0) +MX6_PAD_DECL(KEY_COL3__GPIO4_IO12, 0x05E0, 0x0210, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__SPDIF_IN, 0x05E0, 0x0210, 6, 0x0914, 2, 0) +MX6_PAD_DECL(KEY_ROW3__ASRC_EXT_CLK, 0x05E4, 0x0214, 1, 0x07B0, 0, 0) +MX6_PAD_DECL(KEY_ROW3__HDMI_TX_DDC_SDA, 0x05E4, 0x0214, 2, 0x0894, 1, 0) +MX6_PAD_DECL(KEY_ROW3__KEY_ROW3, 0x05E4, 0x0214, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW3__I2C2_SDA, 0x05E4, 0x0214, 20, 0x08A4, 1, 0) +MX6_PAD_DECL(KEY_ROW3__GPIO4_IO13, 0x05E4, 0x0214, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW3__SD1_VSELECT, 0x05E4, 0x0214, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__FLEXCAN2_TX, 0x05E8, 0x0218, 0, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__IPU1_SISG4, 0x05E8, 0x0218, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__USB_OTG_OC, 0x05E8, 0x0218, 2, 0x0944, 1, 0) +MX6_PAD_DECL(KEY_COL4__KEY_COL4, 0x05E8, 0x0218, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__UART5_CTS_B, 0x05E8, 0x0218, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__UART5_RTS_B, 0x05E8, 0x0218, 4, 0x093C, 0, 0) +MX6_PAD_DECL(KEY_COL4__GPIO4_IO14, 0x05E8, 0x0218, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__FLEXCAN2_RX, 0x05EC, 0x021C, 0, 0x07E8, 0, 0) +MX6_PAD_DECL(KEY_ROW4__IPU1_SISG5, 0x05EC, 0x021C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__USB_OTG_PWR, 0x05EC, 0x021C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__KEY_ROW4, 0x05EC, 0x021C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__UART5_CTS_B, 0x05EC, 0x021C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__UART5_RTS_B, 0x05EC, 0x021C, 4, 0x093C, 1, 0) +MX6_PAD_DECL(KEY_ROW4__GPIO4_IO15, 0x05EC, 0x021C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__CCM_CLKO1, 0x05F0, 0x0220, 0, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__KEY_COL5, 0x05F0, 0x0220, 2, 0x08E8, 0, 0) +MX6_PAD_DECL(GPIO_0__ASRC_EXT_CLK, 0x05F0, 0x0220, 3, 0x07B0, 1, 0) +MX6_PAD_DECL(GPIO_0__EPIT1_OUT, 0x05F0, 0x0220, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__GPIO1_IO00, 0x05F0, 0x0220, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__USB_H1_PWR, 0x05F0, 0x0220, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__SNVS_VIO_5, 0x05F0, 0x0220, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__ESAI_RX_CLK, 0x05F4, 0x0224, 0, 0x086C, 1, 0) +MX6_PAD_DECL(GPIO_1__WDOG2_B, 0x05F4, 0x0224, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__KEY_ROW5, 0x05F4, 0x0224, 2, 0x08F4, 0, 0) +MX6_PAD_DECL(GPIO_1__USB_OTG_ID, 0x05F4, 0x0224, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__PWM2_OUT, 0x05F4, 0x0224, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__GPIO1_IO01, 0x05F4, 0x0224, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__SD1_CD_B, 0x05F4, 0x0224, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__ESAI_RX_FS, 0x05F8, 0x0228, 0, 0x085C, 1, 0) +MX6_PAD_DECL(GPIO_9__WDOG1_B, 0x05F8, 0x0228, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__KEY_COL6, 0x05F8, 0x0228, 2, 0x08EC, 0, 0) +MX6_PAD_DECL(GPIO_9__CCM_REF_EN_B, 0x05F8, 0x0228, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__PWM1_OUT, 0x05F8, 0x0228, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__GPIO1_IO09, 0x05F8, 0x0228, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__SD1_WP, 0x05F8, 0x0228, 6, 0x094C, 1, 0) +MX6_PAD_DECL(GPIO_3__ESAI_RX_HF_CLK, 0x05FC, 0x022C, 0, 0x0864, 1, 0) +MX6_PAD_DECL(GPIO_3__I2C3_SCL, 0x05FC, 0x022C, 18, 0x08A8, 1, 0) +MX6_PAD_DECL(GPIO_3__XTALOSC_REF_CLK_24M, 0x05FC, 0x022C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__CCM_CLKO2, 0x05FC, 0x022C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__GPIO1_IO03, 0x05FC, 0x022C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__USB_H1_OC, 0x05FC, 0x022C, 6, 0x0948, 1, 0) +MX6_PAD_DECL(GPIO_3__MLB_CLK, 0x05FC, 0x022C, 7, 0x0900, 1, 0) +MX6_PAD_DECL(GPIO_6__ESAI_TX_CLK, 0x0600, 0x0230, 0, 0x0870, 1, 0) +MX6_PAD_DECL(GPIO_6__I2C3_SDA, 0x0600, 0x0230, 18, 0x08AC, 1, 0) +MX6_PAD_DECL(GPIO_6__GPIO1_IO06, 0x0600, 0x0230, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__SD2_LCTL, 0x0600, 0x0230, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__MLB_SIG, 0x0600, 0x0230, 7, 0x0908, 1, 0) +MX6_PAD_DECL(GPIO_2__ESAI_TX_FS, 0x0604, 0x0234, 0, 0x0860, 1, 0) +MX6_PAD_DECL(GPIO_2__KEY_ROW6, 0x0604, 0x0234, 2, 0x08F8, 1, 0) +MX6_PAD_DECL(GPIO_2__GPIO1_IO02, 0x0604, 0x0234, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__SD2_WP, 0x0604, 0x0234, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__MLB_DATA, 0x0604, 0x0234, 7, 0x0904, 1, 0) +MX6_PAD_DECL(GPIO_4__ESAI_TX_HF_CLK, 0x0608, 0x0238, 0, 0x0868, 1, 0) +MX6_PAD_DECL(GPIO_4__KEY_COL7, 0x0608, 0x0238, 2, 0x08F0, 1, 0) +MX6_PAD_DECL(GPIO_4__GPIO1_IO04, 0x0608, 0x0238, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_4__SD2_CD_B, 0x0608, 0x0238, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__ESAI_TX2_RX3, 0x060C, 0x023C, 0, 0x087C, 1, 0) +MX6_PAD_DECL(GPIO_5__KEY_ROW7, 0x060C, 0x023C, 2, 0x08FC, 1, 0) +MX6_PAD_DECL(GPIO_5__CCM_CLKO1, 0x060C, 0x023C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__GPIO1_IO05, 0x060C, 0x023C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__I2C3_SCL, 0x060C, 0x023C, 22, 0x08A8, 2, 0) +MX6_PAD_DECL(GPIO_5__ARM_EVENTI, 0x060C, 0x023C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__ESAI_TX4_RX1, 0x0610, 0x0240, 0, 0x0884, 1, 0) +MX6_PAD_DECL(GPIO_7__ECSPI5_RDY, 0x0610, 0x0240, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__EPIT1_OUT, 0x0610, 0x0240, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__FLEXCAN1_TX, 0x0610, 0x0240, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__UART2_TX_DATA, 0x0610, 0x0240, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__UART2_RX_DATA, 0x0610, 0x0240, 4, 0x0928, 2, 0) +MX6_PAD_DECL(GPIO_7__GPIO1_IO07, 0x0610, 0x0240, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__SPDIF_LOCK, 0x0610, 0x0240, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__USB_OTG_HOST_MODE, 0x0610, 0x0240, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__ESAI_TX5_RX0, 0x0614, 0x0244, 0, 0x0888, 1, 0) +MX6_PAD_DECL(GPIO_8__XTALOSC_REF_CLK_32K, 0x0614, 0x0244, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__EPIT2_OUT, 0x0614, 0x0244, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__FLEXCAN1_RX, 0x0614, 0x0244, 3, 0x07E4, 1, 0) +MX6_PAD_DECL(GPIO_8__UART2_TX_DATA, 0x0614, 0x0244, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__UART2_RX_DATA, 0x0614, 0x0244, 4, 0x0928, 3, 0) +MX6_PAD_DECL(GPIO_8__GPIO1_IO08, 0x0614, 0x0244, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK, 0x0614, 0x0244, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE, 0x0614, 0x0244, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2, 0x0618, 0x0248, 0, 0x0880, 1, 0) +MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x0618, 0x0248, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x0618, 0x0248, 2 | IOMUX_CONFIG_SION, 0x083C, 1, 0) +MX6_PAD_DECL(GPIO_16__SD1_LCTL, 0x0618, 0x0248, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__SPDIF_IN, 0x0618, 0x0248, 4, 0x0914, 3, 0) +MX6_PAD_DECL(GPIO_16__GPIO7_IO11, 0x0618, 0x0248, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__I2C3_SDA, 0x0618, 0x0248, 22, 0x08AC, 2, 0) +MX6_PAD_DECL(GPIO_16__JTAG_DE_B, 0x0618, 0x0248, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__ESAI_TX0, 0x061C, 0x024C, 0, 0x0874, 0, 0) +MX6_PAD_DECL(GPIO_17__ENET_1588_EVENT3_IN, 0x061C, 0x024C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__CCM_PMIC_READY, 0x061C, 0x024C, 2, 0x07F0, 1, 0) +MX6_PAD_DECL(GPIO_17__SDMA_EXT_EVENT0, 0x061C, 0x024C, 3, 0x090C, 1, 0) +MX6_PAD_DECL(GPIO_17__SPDIF_OUT, 0x061C, 0x024C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__GPIO7_IO12, 0x061C, 0x024C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__ESAI_TX1, 0x0620, 0x0250, 0, 0x0878, 0, 0) +MX6_PAD_DECL(GPIO_18__ENET_RX_CLK, 0x0620, 0x0250, 1, 0x0844, 1, 0) +MX6_PAD_DECL(GPIO_18__SD3_VSELECT, 0x0620, 0x0250, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__SDMA_EXT_EVENT1, 0x0620, 0x0250, 3, 0x0910, 1, 0) +MX6_PAD_DECL(GPIO_18__ASRC_EXT_CLK, 0x0620, 0x0250, 4, 0x07B0, 2, 0) +MX6_PAD_DECL(GPIO_18__GPIO7_IO13, 0x0620, 0x0250, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__SNVS_VIO_5_CTL, 0x0620, 0x0250, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__KEY_COL5, 0x0624, 0x0254, 0, 0x08E8, 1, 0) +MX6_PAD_DECL(GPIO_19__ENET_1588_EVENT0_OUT, 0x0624, 0x0254, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__SPDIF_OUT, 0x0624, 0x0254, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__CCM_CLKO1, 0x0624, 0x0254, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__ECSPI1_RDY, 0x0624, 0x0254, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__GPIO4_IO05, 0x0624, 0x0254, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__ENET_TX_ER, 0x0624, 0x0254, 6, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK, 0x0628, 0x0258, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__GPIO5_IO18, 0x0628, 0x0258, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__ARM_EVENTO, 0x0628, 0x0258, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__IPU1_CSI0_HSYNC, 0x062C, 0x025C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__CCM_CLKO1, 0x062C, 0x025C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__GPIO5_IO19, 0x062C, 0x025C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__ARM_TRACE_CTL, 0x062C, 0x025C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__IPU1_CSI0_DATA_EN, 0x0630, 0x0260, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__EIM_DATA00, 0x0630, 0x0260, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__GPIO5_IO20, 0x0630, 0x0260, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__ARM_TRACE_CLK, 0x0630, 0x0260, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__IPU1_CSI0_VSYNC, 0x0634, 0x0264, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__EIM_DATA01, 0x0634, 0x0264, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__GPIO5_IO21, 0x0634, 0x0264, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__ARM_TRACE00, 0x0634, 0x0264, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__IPU1_CSI0_DATA04, 0x0638, 0x0268, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__EIM_DATA02, 0x0638, 0x0268, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__ECSPI1_SCLK, 0x0638, 0x0268, 2, 0x07F4, 3, 0) +MX6_PAD_DECL(CSI0_DAT4__KEY_COL5, 0x0638, 0x0268, 3, 0x08E8, 2, 0) +MX6_PAD_DECL(CSI0_DAT4__AUD3_TXC, 0x0638, 0x0268, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__GPIO5_IO22, 0x0638, 0x0268, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__ARM_TRACE01, 0x0638, 0x0268, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__IPU1_CSI0_DATA05, 0x063C, 0x026C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__EIM_DATA03, 0x063C, 0x026C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__ECSPI1_MOSI, 0x063C, 0x026C, 2, 0x07FC, 3, 0) +MX6_PAD_DECL(CSI0_DAT5__KEY_ROW5, 0x063C, 0x026C, 3, 0x08F4, 1, 0) +MX6_PAD_DECL(CSI0_DAT5__AUD3_TXD, 0x063C, 0x026C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__GPIO5_IO23, 0x063C, 0x026C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__ARM_TRACE02, 0x063C, 0x026C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__IPU1_CSI0_DATA06, 0x0640, 0x0270, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__EIM_DATA04, 0x0640, 0x0270, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__ECSPI1_MISO, 0x0640, 0x0270, 2, 0x07F8, 3, 0) +MX6_PAD_DECL(CSI0_DAT6__KEY_COL6, 0x0640, 0x0270, 3, 0x08EC, 1, 0) +MX6_PAD_DECL(CSI0_DAT6__AUD3_TXFS, 0x0640, 0x0270, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__GPIO5_IO24, 0x0640, 0x0270, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__ARM_TRACE03, 0x0640, 0x0270, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__IPU1_CSI0_DATA07, 0x0644, 0x0274, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__EIM_DATA05, 0x0644, 0x0274, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__ECSPI1_SS0, 0x0644, 0x0274, 2, 0x0800, 3, 0) +MX6_PAD_DECL(CSI0_DAT7__KEY_ROW6, 0x0644, 0x0274, 3, 0x08F8, 2, 0) +MX6_PAD_DECL(CSI0_DAT7__AUD3_RXD, 0x0644, 0x0274, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__GPIO5_IO25, 0x0644, 0x0274, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__ARM_TRACE04, 0x0644, 0x0274, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__IPU1_CSI0_DATA08, 0x0648, 0x0278, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__EIM_DATA06, 0x0648, 0x0278, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__ECSPI2_SCLK, 0x0648, 0x0278, 2, 0x0810, 2, 0) +MX6_PAD_DECL(CSI0_DAT8__KEY_COL7, 0x0648, 0x0278, 3, 0x08F0, 2, 0) +MX6_PAD_DECL(CSI0_DAT8__I2C1_SDA, 0x0648, 0x0278, 20, 0x089C, 1, 0) +MX6_PAD_DECL(CSI0_DAT8__GPIO5_IO26, 0x0648, 0x0278, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__ARM_TRACE05, 0x0648, 0x0278, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__IPU1_CSI0_DATA09, 0x064C, 0x027C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__EIM_DATA07, 0x064C, 0x027C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__ECSPI2_MOSI, 0x064C, 0x027C, 2, 0x0818, 2, 0) +MX6_PAD_DECL(CSI0_DAT9__KEY_ROW7, 0x064C, 0x027C, 3, 0x08FC, 2, 0) +MX6_PAD_DECL(CSI0_DAT9__I2C1_SCL, 0x064C, 0x027C, 20, 0x0898, 1, 0) +MX6_PAD_DECL(CSI0_DAT9__GPIO5_IO27, 0x064C, 0x027C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__ARM_TRACE06, 0x064C, 0x027C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__IPU1_CSI0_DATA10, 0x0650, 0x0280, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__AUD3_RXC, 0x0650, 0x0280, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__ECSPI2_MISO, 0x0650, 0x0280, 2, 0x0814, 2, 0) +MX6_PAD_DECL(CSI0_DAT10__UART1_TX_DATA, 0x0650, 0x0280, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__UART1_RX_DATA, 0x0650, 0x0280, 3, 0x0920, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__GPIO5_IO28, 0x0650, 0x0280, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__ARM_TRACE07, 0x0650, 0x0280, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__IPU1_CSI0_DATA11, 0x0654, 0x0284, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__AUD3_RXFS, 0x0654, 0x0284, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__ECSPI2_SS0, 0x0654, 0x0284, 2, 0x081C, 2, 0) +MX6_PAD_DECL(CSI0_DAT11__UART1_TX_DATA, 0x0654, 0x0284, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__UART1_RX_DATA, 0x0654, 0x0284, 3, 0x0920, 1, 0) +MX6_PAD_DECL(CSI0_DAT11__GPIO5_IO29, 0x0654, 0x0284, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__ARM_TRACE08, 0x0654, 0x0284, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__IPU1_CSI0_DATA12, 0x0658, 0x0288, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__EIM_DATA08, 0x0658, 0x0288, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__UART4_TX_DATA, 0x0658, 0x0288, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__UART4_RX_DATA, 0x0658, 0x0288, 3, 0x0938, 2, 0) +MX6_PAD_DECL(CSI0_DAT12__GPIO5_IO30, 0x0658, 0x0288, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__ARM_TRACE09, 0x0658, 0x0288, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__IPU1_CSI0_DATA13, 0x065C, 0x028C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__EIM_DATA09, 0x065C, 0x028C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__UART4_TX_DATA, 0x065C, 0x028C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__UART4_RX_DATA, 0x065C, 0x028C, 3, 0x0938, 3, 0) +MX6_PAD_DECL(CSI0_DAT13__GPIO5_IO31, 0x065C, 0x028C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__ARM_TRACE10, 0x065C, 0x028C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__IPU1_CSI0_DATA14, 0x0660, 0x0290, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__EIM_DATA10, 0x0660, 0x0290, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__UART5_TX_DATA, 0x0660, 0x0290, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__UART5_RX_DATA, 0x0660, 0x0290, 3, 0x0940, 2, 0) +MX6_PAD_DECL(CSI0_DAT14__GPIO6_IO00, 0x0660, 0x0290, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__ARM_TRACE11, 0x0660, 0x0290, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__IPU1_CSI0_DATA15, 0x0664, 0x0294, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__EIM_DATA11, 0x0664, 0x0294, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__UART5_TX_DATA, 0x0664, 0x0294, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__UART5_RX_DATA, 0x0664, 0x0294, 3, 0x0940, 3, 0) +MX6_PAD_DECL(CSI0_DAT15__GPIO6_IO01, 0x0664, 0x0294, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__ARM_TRACE12, 0x0664, 0x0294, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__IPU1_CSI0_DATA16, 0x0668, 0x0298, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__EIM_DATA12, 0x0668, 0x0298, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__UART4_CTS_B, 0x0668, 0x0298, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__UART4_RTS_B, 0x0668, 0x0298, 3, 0x0934, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__GPIO6_IO02, 0x0668, 0x0298, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__ARM_TRACE13, 0x0668, 0x0298, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__IPU1_CSI0_DATA17, 0x066C, 0x029C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__EIM_DATA13, 0x066C, 0x029C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__UART4_CTS_B, 0x066C, 0x029C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__UART4_RTS_B, 0x066C, 0x029C, 3, 0x0934, 1, 0) +MX6_PAD_DECL(CSI0_DAT17__GPIO6_IO03, 0x066C, 0x029C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__ARM_TRACE14, 0x066C, 0x029C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__IPU1_CSI0_DATA18, 0x0670, 0x02A0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__EIM_DATA14, 0x0670, 0x02A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__UART5_CTS_B, 0x0670, 0x02A0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__UART5_RTS_B, 0x0670, 0x02A0, 3, 0x093C, 2, 0) +MX6_PAD_DECL(CSI0_DAT18__GPIO6_IO04, 0x0670, 0x02A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__ARM_TRACE15, 0x0670, 0x02A0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__IPU1_CSI0_DATA19, 0x0674, 0x02A4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__EIM_DATA15, 0x0674, 0x02A4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__UART5_CTS_B, 0x0674, 0x02A4, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__UART5_RTS_B, 0x0674, 0x02A4, 3, 0x093C, 3, 0) +MX6_PAD_DECL(CSI0_DAT19__GPIO6_IO05, 0x0674, 0x02A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__SD3_DATA7, 0x0690, 0x02A8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__UART1_TX_DATA, 0x0690, 0x02A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__UART1_RX_DATA, 0x0690, 0x02A8, 1, 0x0920, 2, 0) +MX6_PAD_DECL(SD3_DAT7__GPIO6_IO17, 0x0690, 0x02A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__SD3_DATA6, 0x0694, 0x02AC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__UART1_TX_DATA, 0x0694, 0x02AC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__UART1_RX_DATA, 0x0694, 0x02AC, 1, 0x0920, 3, 0) +MX6_PAD_DECL(SD3_DAT6__GPIO6_IO18, 0x0694, 0x02AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__SD3_DATA5, 0x0698, 0x02B0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__UART2_TX_DATA, 0x0698, 0x02B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__UART2_RX_DATA, 0x0698, 0x02B0, 1, 0x0928, 4, 0) +MX6_PAD_DECL(SD3_DAT5__GPIO7_IO00, 0x0698, 0x02B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__SD3_DATA4, 0x069C, 0x02B4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA, 0x069C, 0x02B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA, 0x069C, 0x02B4, 1, 0x0928, 5, 0) +MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01, 0x069C, 0x02B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__UART2_CTS_B, 0x06A0, 0x02B8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__UART2_RTS_B, 0x06A0, 0x02B8, 1, 0x0924, 2, 0) +MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX, 0x06A0, 0x02B8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__GPIO7_IO02, 0x06A0, 0x02B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__SD3_CLK, 0x06A4, 0x02BC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__UART2_CTS_B, 0x06A4, 0x02BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__UART2_RTS_B, 0x06A4, 0x02BC, 1, 0x0924, 3, 0) +MX6_PAD_DECL(SD3_CLK__FLEXCAN1_RX, 0x06A4, 0x02BC, 2, 0x07E4, 2, 0) +MX6_PAD_DECL(SD3_CLK__GPIO7_IO03, 0x06A4, 0x02BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__SD3_DATA0, 0x06A8, 0x02C0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__UART1_CTS_B, 0x06A8, 0x02C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__UART1_RTS_B, 0x06A8, 0x02C0, 1, 0x091C, 2, 0) +MX6_PAD_DECL(SD3_DAT0__FLEXCAN2_TX, 0x06A8, 0x02C0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__GPIO7_IO04, 0x06A8, 0x02C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__SD3_DATA1, 0x06AC, 0x02C4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__UART1_CTS_B, 0x06AC, 0x02C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__UART1_RTS_B, 0x06AC, 0x02C4, 1, 0x091C, 3, 0) +MX6_PAD_DECL(SD3_DAT1__FLEXCAN2_RX, 0x06AC, 0x02C4, 2, 0x07E8, 1, 0) +MX6_PAD_DECL(SD3_DAT1__GPIO7_IO05, 0x06AC, 0x02C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT2__SD3_DATA2, 0x06B0, 0x02C8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT2__GPIO7_IO06, 0x06B0, 0x02C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__SD3_DATA3, 0x06B4, 0x02CC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__UART3_CTS_B, 0x06B4, 0x02CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__UART3_RTS_B, 0x06B4, 0x02CC, 1, 0x092C, 4, 0) +MX6_PAD_DECL(SD3_DAT3__GPIO7_IO07, 0x06B4, 0x02CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__SD3_RESET, 0x06B8, 0x02D0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__UART3_CTS_B, 0x06B8, 0x02D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__UART3_RTS_B, 0x06B8, 0x02D0, 1, 0x092C, 5, 0) +MX6_PAD_DECL(SD3_RST__GPIO7_IO08, 0x06B8, 0x02D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__NAND_CLE, 0x06BC, 0x02D4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__IPU2_SISG4, 0x06BC, 0x02D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__GPIO6_IO07, 0x06BC, 0x02D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__NAND_ALE, 0x06C0, 0x02D8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__SD4_RESET, 0x06C0, 0x02D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__GPIO6_IO08, 0x06C0, 0x02D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__NAND_WP_B, 0x06C4, 0x02DC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__IPU2_SISG5, 0x06C4, 0x02DC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__GPIO6_IO09, 0x06C4, 0x02DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__NAND_READY_B, 0x06C8, 0x02E0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__IPU2_DI0_PIN01, 0x06C8, 0x02E0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__GPIO6_IO10, 0x06C8, 0x02E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS0__NAND_CE0_B, 0x06CC, 0x02E4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS0__GPIO6_IO11, 0x06CC, 0x02E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__NAND_CE1_B, 0x06D0, 0x02E8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__SD4_VSELECT, 0x06D0, 0x02E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__SD3_VSELECT, 0x06D0, 0x02E8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__GPIO6_IO14, 0x06D0, 0x02E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__NAND_CE2_B, 0x06D4, 0x02EC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__IPU1_SISG0, 0x06D4, 0x02EC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__ESAI_TX0, 0x06D4, 0x02EC, 2, 0x0874, 1, 0) +MX6_PAD_DECL(NANDF_CS2__EIM_CRE, 0x06D4, 0x02EC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__CCM_CLKO2, 0x06D4, 0x02EC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__GPIO6_IO15, 0x06D4, 0x02EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__IPU2_SISG0, 0x06D4, 0x02EC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__NAND_CE3_B, 0x06D8, 0x02F0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__IPU1_SISG1, 0x06D8, 0x02F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__ESAI_TX1, 0x06D8, 0x02F0, 2, 0x0878, 1, 0) +MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26, 0x06D8, 0x02F0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16, 0x06D8, 0x02F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__IPU2_SISG1, 0x06D8, 0x02F0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__NAND_RE_B, 0x06DC, 0x02F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA, 0x06DC, 0x02F4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA, 0x06DC, 0x02F4, 2, 0x0930, 2, 0) +MX6_PAD_DECL(SD4_CMD__GPIO7_IO09, 0x06DC, 0x02F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__SD4_CLK, 0x06E0, 0x02F8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__NAND_WE_B, 0x06E0, 0x02F8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__UART3_TX_DATA, 0x06E0, 0x02F8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__UART3_RX_DATA, 0x06E0, 0x02F8, 2, 0x0930, 3, 0) +MX6_PAD_DECL(SD4_CLK__GPIO7_IO10, 0x06E0, 0x02F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__NAND_DATA00, 0x06E4, 0x02FC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__SD1_DATA4, 0x06E4, 0x02FC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__GPIO2_IO00, 0x06E4, 0x02FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__NAND_DATA01, 0x06E8, 0x0300, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__SD1_DATA5, 0x06E8, 0x0300, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__GPIO2_IO01, 0x06E8, 0x0300, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__NAND_DATA02, 0x06EC, 0x0304, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__SD1_DATA6, 0x06EC, 0x0304, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__GPIO2_IO02, 0x06EC, 0x0304, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__NAND_DATA03, 0x06F0, 0x0308, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__SD1_DATA7, 0x06F0, 0x0308, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__GPIO2_IO03, 0x06F0, 0x0308, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__NAND_DATA04, 0x06F4, 0x030C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__SD2_DATA4, 0x06F4, 0x030C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__GPIO2_IO04, 0x06F4, 0x030C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__NAND_DATA05, 0x06F8, 0x0310, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__SD2_DATA5, 0x06F8, 0x0310, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__GPIO2_IO05, 0x06F8, 0x0310, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__NAND_DATA06, 0x06FC, 0x0314, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__SD2_DATA6, 0x06FC, 0x0314, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__GPIO2_IO06, 0x06FC, 0x0314, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__NAND_DATA07, 0x0700, 0x0318, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__SD2_DATA7, 0x0700, 0x0318, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__GPIO2_IO07, 0x0700, 0x0318, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__SD4_DATA0, 0x0704, 0x031C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__NAND_DQS, 0x0704, 0x031C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__GPIO2_IO08, 0x0704, 0x031C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__SD4_DATA1, 0x0708, 0x0320, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__PWM3_OUT, 0x0708, 0x0320, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__GPIO2_IO09, 0x0708, 0x0320, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__SD4_DATA2, 0x070C, 0x0324, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__PWM4_OUT, 0x070C, 0x0324, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__GPIO2_IO10, 0x070C, 0x0324, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT3__SD4_DATA3, 0x0710, 0x0328, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT3__GPIO2_IO11, 0x0710, 0x0328, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__SD4_DATA4, 0x0714, 0x032C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__UART2_TX_DATA, 0x0714, 0x032C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__UART2_RX_DATA, 0x0714, 0x032C, 2, 0x0928, 6, 0) +MX6_PAD_DECL(SD4_DAT4__GPIO2_IO12, 0x0714, 0x032C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__SD4_DATA5, 0x0718, 0x0330, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__UART2_CTS_B, 0x0718, 0x0330, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__UART2_RTS_B, 0x0718, 0x0330, 2, 0x0924, 4, 0) +MX6_PAD_DECL(SD4_DAT5__GPIO2_IO13, 0x0718, 0x0330, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__SD4_DATA6, 0x071C, 0x0334, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__UART2_CTS_B, 0x071C, 0x0334, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__UART2_RTS_B, 0x071C, 0x0334, 2, 0x0924, 5, 0) +MX6_PAD_DECL(SD4_DAT6__GPIO2_IO14, 0x071C, 0x0334, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__SD4_DATA7, 0x0720, 0x0338, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__UART2_TX_DATA, 0x0720, 0x0338, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__UART2_RX_DATA, 0x0720, 0x0338, 2, 0x0928, 7, 0) +MX6_PAD_DECL(SD4_DAT7__GPIO2_IO15, 0x0720, 0x0338, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__SD1_DATA1, 0x0724, 0x033C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__ECSPI5_SS0, 0x0724, 0x033C, 1, 0x0834, 1, 0) +MX6_PAD_DECL(SD1_DAT1__PWM3_OUT, 0x0724, 0x033C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__GPT_CAPTURE2, 0x0724, 0x033C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__GPIO1_IO17, 0x0724, 0x033C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__SD1_DATA0, 0x0728, 0x0340, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__ECSPI5_MISO, 0x0728, 0x0340, 1, 0x082C, 1, 0) +MX6_PAD_DECL(SD1_DAT0__GPT_CAPTURE1, 0x0728, 0x0340, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__GPIO1_IO16, 0x0728, 0x0340, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__SD1_DATA3, 0x072C, 0x0344, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__ECSPI5_SS2, 0x072C, 0x0344, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__GPT_COMPARE3, 0x072C, 0x0344, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__PWM1_OUT, 0x072C, 0x0344, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__WDOG2_B, 0x072C, 0x0344, 4, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21, 0x072C, 0x0344, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB, 0x072C, 0x0344, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__ECSPI5_MOSI, 0x0730, 0x0348, 1, 0x0830, 0, 0) +MX6_PAD_DECL(SD1_CMD__PWM4_OUT, 0x0730, 0x0348, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1, 0x0730, 0x0348, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__GPIO1_IO18, 0x0730, 0x0348, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__SD1_DATA2, 0x0734, 0x034C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__ECSPI5_SS1, 0x0734, 0x034C, 1, 0x0838, 1, 0) +MX6_PAD_DECL(SD1_DAT2__GPT_COMPARE2, 0x0734, 0x034C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__PWM2_OUT, 0x0734, 0x034C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__WDOG1_B, 0x0734, 0x034C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__GPIO1_IO19, 0x0734, 0x034C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__WDOG1_RESET_B_DEB, 0x0734, 0x034C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__SD1_CLK, 0x0738, 0x0350, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__ECSPI5_SCLK, 0x0738, 0x0350, 1, 0x0828, 0, 0) +MX6_PAD_DECL(SD1_CLK__GPT_CLKIN, 0x0738, 0x0350, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__GPIO1_IO20, 0x0738, 0x0350, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CLK__SD2_CLK, 0x073C, 0x0354, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CLK__ECSPI5_SCLK, 0x073C, 0x0354, 1, 0x0828, 1, 0) +MX6_PAD_DECL(SD2_CLK__KEY_COL5, 0x073C, 0x0354, 2, 0x08E8, 3, 0) +MX6_PAD_DECL(SD2_CLK__AUD4_RXFS, 0x073C, 0x0354, 3, 0x07C0, 1, 0) +MX6_PAD_DECL(SD2_CLK__GPIO1_IO10, 0x073C, 0x0354, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CMD__ECSPI5_MOSI, 0x0740, 0x0358, 1, 0x0830, 1, 0) +MX6_PAD_DECL(SD2_CMD__KEY_ROW5, 0x0740, 0x0358, 2, 0x08F4, 2, 0) +MX6_PAD_DECL(SD2_CMD__AUD4_RXC, 0x0740, 0x0358, 3, 0x07BC, 1, 0) +MX6_PAD_DECL(SD2_CMD__GPIO1_IO11, 0x0740, 0x0358, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__SD2_DATA3, 0x0744, 0x035C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__ECSPI5_SS3, 0x0744, 0x035C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__KEY_COL6, 0x0744, 0x035C, 2, 0x08EC, 2, 0) +MX6_PAD_DECL(SD2_DAT3__AUD4_TXC, 0x0744, 0x035C, 3, 0x07C4, 1, 0) +MX6_PAD_DECL(SD2_DAT3__GPIO1_IO12, 0x0744, 0x035C, 5, 0x0000, 0, 0) + +#endif /* __ASM_ARCH_MX6_MX6Q_PINS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h new file mode 100644 index 000000000..d397c8a06 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __ASM_ARCH_MX6SL_DDR_H__ +#define __ASM_ARCH_MX6SL_DDR_H__ + +#ifndef CONFIG_MX6SL +#error "wrong CPU" +#endif + +#define MX6_IOM_DRAM_CAS_B 0x020e0300 +#define MX6_IOM_DRAM_CS0_B 0x020e0304 +#define MX6_IOM_DRAM_CS1_B 0x020e0308 + +#define MX6_IOM_DRAM_DQM0 0x020e030c +#define MX6_IOM_DRAM_DQM1 0x020e0310 +#define MX6_IOM_DRAM_DQM2 0x020e0314 +#define MX6_IOM_DRAM_DQM3 0x020e0318 + +#define MX6_IOM_DRAM_RAS_B 0x020e031c +#define MX6_IOM_DRAM_RESET 0x020e0320 + +#define MX6_IOM_DRAM_SDBA0 0x020e0324 +#define MX6_IOM_DRAM_SDBA1 0x020e0328 +#define MX6_IOM_DRAM_SDBA2 0x020e032c + +#define MX6_IOM_DRAM_SDCKE0 0x020e0330 +#define MX6_IOM_DRAM_SDCKE1 0x020e0334 + +#define MX6_IOM_DRAM_SDCLK0_P 0x020e0338 + +#define MX6_IOM_DRAM_ODT0 0x020e033c +#define MX6_IOM_DRAM_ODT1 0x020e0340 + +#define MX6_IOM_DRAM_SDQS0_P 0x020e0344 +#define MX6_IOM_DRAM_SDQS1_P 0x020e0348 +#define MX6_IOM_DRAM_SDQS2_P 0x020e034c +#define MX6_IOM_DRAM_SDQS3_P 0x020e0350 + +#define MX6_IOM_DRAM_SDWE_B 0x020e0354 + +#endif /*__ASM_ARCH_MX6SL_DDR_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sl_pins.h new file mode 100644 index 000000000..01b14d73d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sl_pins.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __ASM_ARCH_MX6_MX6SL_PINS_H__ +#define __ASM_ARCH_MX6_MX6SL_PINS_H__ + +#include + +enum { + MX6_PAD_ECSPI1_MISO__ECSPI_MISO = IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, 0), + MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0), + MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0), + MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT4__USDHC1_DAT4 = IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT5__USDHC1_DAT5 = IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT5__GPIO_5_9 = IOMUX_PAD(0x0550, 0x0248, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT6__USDHC1_DAT6 = IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT7__USDHC1_DAT7 = IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0), + MX6_PAD_KEY_ROW7__GPIO_4_7 = IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT4__USDHC2_DAT4 = IOMUX_PAD(0X0574, 0X026C, 0, 0X0000, 0, 0), + MX6_PAD_SD2_DAT5__USDHC2_DAT5 = IOMUX_PAD(0X0578, 0X0270, 0, 0X0000, 0, 0), + MX6_PAD_SD2_DAT6__USDHC2_DAT6 = IOMUX_PAD(0X057C, 0X0274, 0, 0X0000, 0, 0), + MX6_PAD_SD2_DAT7__USDHC2_DAT7 = IOMUX_PAD(0X0580, 0X0278, 0, 0X0000, 0, 0), + MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0), + MX6_PAD_SD2_RST__USDHC2_RST = IOMUX_PAD(0x0584, 0x027C, 0, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, 0), + MX6_PAD_REF_CLK_32K__GPIO_3_22 = IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, 0), + MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0), + MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0), + + MX6_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x41c, 0x12c, 0, 0x000, 0, 0), + MX6_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x420, 0x130, 0, 0x6f4, 1, 0), + MX6_PAD_FEC_CRS_DV__FEC_RX_DV = IOMUX_PAD(0x418, 0x128, 0, 0x704, 1, 0), + MX6_PAD_FEC_RXD0__FEC_RX_DATA0 = IOMUX_PAD(0x42c, 0x13c, 0, 0x6f8, 0, 0), + MX6_PAD_FEC_RXD1__FEC_RX_DATA1 = IOMUX_PAD(0x430, 0x140, 0, 0x6fc, 1, 0), + MX6_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x438, 0x148, 0, 0x000, 0, 0), + MX6_PAD_FEC_TXD0__FEC_TX_DATA0 = IOMUX_PAD(0x43c, 0x14c, 0, 0x000, 0, 0), + MX6_PAD_FEC_TXD1__FEC_TX_DATA1 = IOMUX_PAD(0x440, 0x150, 0, 0x000, 0, 0), + MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0), + MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0), + MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0), + + MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0), + + MX6_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0), + MX6_PAD_I2C1_SDA__GPIO_3_13 = IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0), + MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0), + MX6_PAD_I2C1_SCL__GPIO_3_12 = IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0), +}; +#endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sll_pins.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sll_pins.h new file mode 100644 index 000000000..e4bd4ef89 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sll_pins.h @@ -0,0 +1,1018 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 - 2016 Freescale Semiconductor, Inc. + */ + +#ifndef __ASM_ARCH_IMX6SLL_PINS_H__ +#define __ASM_ARCH_IMX6SLL_PINS_H__ + +#include + +enum { + MX6_PAD_WDOG_B__WDOG1_B = IOMUX_PAD(0x02DC, 0x0014, 0, 0x0000, 0, 0), + MX6_PAD_WDOG_B__WDOG1_RESET_B_DEB = IOMUX_PAD(0x02DC, 0x0014, 1, 0x0000, 0, 0), + MX6_PAD_WDOG_B__UART5_RI_B = IOMUX_PAD(0x02DC, 0x0014, 2, 0x0000, 0, 0), + MX6_PAD_WDOG_B__GPIO3_IO18 = IOMUX_PAD(0x02DC, 0x0014, 5, 0x0000, 0, 0), + + MX6_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x02E0, 0x0018, 0, 0x0000, 0, 0), + MX6_PAD_REF_CLK_24M__I2C3_SCL = IOMUX_PAD(0x02E0, 0x0018, IOMUX_CONFIG_SION | 1, 0x068C, 0, 0), + MX6_PAD_REF_CLK_24M__PWM3_OUT = IOMUX_PAD(0x02E0, 0x0018, 2, 0x0000, 0, 0), + MX6_PAD_REF_CLK_24M__USB_OTG2_ID = IOMUX_PAD(0x02E0, 0x0018, 3, 0x0560, 0, 0), + MX6_PAD_REF_CLK_24M__CCM_PMIC_READY = IOMUX_PAD(0x02E0, 0x0018, 4, 0x05AC, 0, 0), + MX6_PAD_REF_CLK_24M__GPIO3_IO21 = IOMUX_PAD(0x02E0, 0x0018, 5, 0x0000, 0, 0), + MX6_PAD_REF_CLK_24M__SD3_WP = IOMUX_PAD(0x02E0, 0x0018, 6, 0x0794, 0, 0), + + MX6_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x02E4, 0x001C, 0, 0x0000, 0, 0), + MX6_PAD_REF_CLK_32K__I2C3_SDA = IOMUX_PAD(0x02E4, 0x001C, IOMUX_CONFIG_SION | 1, 0x0690, 0, 0), + MX6_PAD_REF_CLK_32K__PWM4_OUT = IOMUX_PAD(0x02E4, 0x001C, 2, 0x0000, 0, 0), + MX6_PAD_REF_CLK_32K__USB_OTG1_ID = IOMUX_PAD(0x02E4, 0x001C, 3, 0x055C, 0, 0), + MX6_PAD_REF_CLK_32K__SD1_LCTL = IOMUX_PAD(0x02E4, 0x001C, 4, 0x0000, 0, 0), + MX6_PAD_REF_CLK_32K__GPIO3_IO22 = IOMUX_PAD(0x02E4, 0x001C, 5, 0x0000, 0, 0), + MX6_PAD_REF_CLK_32K__SD3_CD_B = IOMUX_PAD(0x02E4, 0x001C, 6, 0x0780, 0, 0), + + MX6_PAD_PWM1__PWM1_OUT = IOMUX_PAD(0x02E8, 0x0020, 0, 0x0000, 0, 0), + MX6_PAD_PWM1__CCM_CLKO = IOMUX_PAD(0x02E8, 0x0020, 1, 0x0000, 0, 0), + MX6_PAD_PWM1__AUDIO_CLK_OUT = IOMUX_PAD(0x02E8, 0x0020, 2, 0x0000, 0, 0), + MX6_PAD_PWM1__CSI_MCLK = IOMUX_PAD(0x02E8, 0x0020, 4, 0x0000, 0, 0), + MX6_PAD_PWM1__GPIO3_IO23 = IOMUX_PAD(0x02E8, 0x0020, 5, 0x0000, 0, 0), + MX6_PAD_PWM1__EPIT1_OUT = IOMUX_PAD(0x02E8, 0x0020, 6, 0x0000, 0, 0), + + MX6_PAD_KEY_COL0__KEY_COL0 = IOMUX_PAD(0x02EC, 0x0024, 0, 0x06A0, 0, 0), + MX6_PAD_KEY_COL0__I2C2_SCL = IOMUX_PAD(0x02EC, 0x0024, IOMUX_CONFIG_SION | 1, 0x0684, 0, 0), + MX6_PAD_KEY_COL0__LCD_DATA00 = IOMUX_PAD(0x02EC, 0x0024, 2, 0x06D8, 0, 0), + MX6_PAD_KEY_COL0__SD1_CD_B = IOMUX_PAD(0x02EC, 0x0024, 4, 0x0770, 1, 0), + MX6_PAD_KEY_COL0__GPIO3_IO24 = IOMUX_PAD(0x02EC, 0x0024, 5, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW0__KEY_ROW0 = IOMUX_PAD(0x02F0, 0x0028, 0, 0x06C0, 0, 0), + MX6_PAD_KEY_ROW0__I2C2_SDA = IOMUX_PAD(0x02F0, 0x0028, IOMUX_CONFIG_SION | 1, 0x0688, 0, 0), + MX6_PAD_KEY_ROW0__LCD_DATA01 = IOMUX_PAD(0x02F0, 0x0028, 2, 0x06DC, 0, 0), + MX6_PAD_KEY_ROW0__SD1_WP = IOMUX_PAD(0x02F0, 0x0028, 4, 0x0774, 1, 0), + MX6_PAD_KEY_ROW0__GPIO3_IO25 = IOMUX_PAD(0x02F0, 0x0028, 5, 0x0000, 0, 0), + + MX6_PAD_KEY_COL1__KEY_COL1 = IOMUX_PAD(0x02F4, 0x002C, 0, 0x06A4, 0, 0), + MX6_PAD_KEY_COL1__ECSPI4_MOSI = IOMUX_PAD(0x02F4, 0x002C, 1, 0x0658, 1, 0), + MX6_PAD_KEY_COL1__LCD_DATA02 = IOMUX_PAD(0x02F4, 0x002C, 2, 0x06E0, 0, 0), + MX6_PAD_KEY_COL1__SD3_DATA4 = IOMUX_PAD(0x02F4, 0x002C, 4, 0x0784, 0, 0), + MX6_PAD_KEY_COL1__GPIO3_IO26 = IOMUX_PAD(0x02F4, 0x002C, 5, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW1__KEY_ROW1 = IOMUX_PAD(0x02F8, 0x0030, 0, 0x06C4, 0, 0), + MX6_PAD_KEY_ROW1__ECSPI4_MISO = IOMUX_PAD(0x02F8, 0x0030, 1, 0x0654, 1, 0), + MX6_PAD_KEY_ROW1__LCD_DATA03 = IOMUX_PAD(0x02F8, 0x0030, 2, 0x06E4, 0, 0), + MX6_PAD_KEY_ROW1__CSI_FIELD = IOMUX_PAD(0x02F8, 0x0030, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__SD3_DATA5 = IOMUX_PAD(0x02F8, 0x0030, 4, 0x0788, 0, 0), + MX6_PAD_KEY_ROW1__GPIO3_IO27 = IOMUX_PAD(0x02F8, 0x0030, 5, 0x0000, 0, 0), + + MX6_PAD_KEY_COL2__KEY_COL2 = IOMUX_PAD(0x02FC, 0x0034, 0, 0x06A8, 0, 0), + MX6_PAD_KEY_COL2__ECSPI4_SS0 = IOMUX_PAD(0x02FC, 0x0034, 1, 0x065C, 1, 0), + MX6_PAD_KEY_COL2__LCD_DATA04 = IOMUX_PAD(0x02FC, 0x0034, 2, 0x06E8, 0, 0), + MX6_PAD_KEY_COL2__CSI_DATA12 = IOMUX_PAD(0x02FC, 0x0034, 3, 0x05B8, 1, 0), + MX6_PAD_KEY_COL2__SD3_DATA6 = IOMUX_PAD(0x02FC, 0x0034, 4, 0x078C, 0, 0), + MX6_PAD_KEY_COL2__GPIO3_IO28 = IOMUX_PAD(0x02FC, 0x0034, 5, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW2__KEY_ROW2 = IOMUX_PAD(0x0300, 0x0038, 0, 0x06C8, 0, 0), + MX6_PAD_KEY_ROW2__ECSPI4_SCLK = IOMUX_PAD(0x0300, 0x0038, 1, 0x0650, 1, 0), + MX6_PAD_KEY_ROW2__LCD_DATA05 = IOMUX_PAD(0x0300, 0x0038, 2, 0x06EC, 0, 0), + MX6_PAD_KEY_ROW2__CSI_DATA13 = IOMUX_PAD(0x0300, 0x0038, 3, 0x05BC, 1, 0), + MX6_PAD_KEY_ROW2__SD3_DATA7 = IOMUX_PAD(0x0300, 0x0038, 4, 0x0790, 0, 0), + MX6_PAD_KEY_ROW2__GPIO3_IO29 = IOMUX_PAD(0x0300, 0x0038, 5, 0x0000, 0, 0), + + MX6_PAD_KEY_COL3__KEY_COL3 = IOMUX_PAD(0x0304, 0x003C, 0, 0x06AC, 0, 0), + MX6_PAD_KEY_COL3__AUD6_RXFS = IOMUX_PAD(0x0304, 0x003C, 1, 0x05A0, 1, 0), + MX6_PAD_KEY_COL3__LCD_DATA06 = IOMUX_PAD(0x0304, 0x003C, 2, 0x06F0, 0, 0), + MX6_PAD_KEY_COL3__CSI_DATA14 = IOMUX_PAD(0x0304, 0x003C, 3, 0x05C0, 1, 0), + MX6_PAD_KEY_COL3__GPIO3_IO30 = IOMUX_PAD(0x0304, 0x003C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__SD1_RESET = IOMUX_PAD(0x0304, 0x003C, 6, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW3__KEY_ROW3 = IOMUX_PAD(0x0308, 0x0040, 0, 0x06CC, 1, 0), + MX6_PAD_KEY_ROW3__AUD6_RXC = IOMUX_PAD(0x0308, 0x0040, 1, 0x059C, 1, 0), + MX6_PAD_KEY_ROW3__LCD_DATA07 = IOMUX_PAD(0x0308, 0x0040, 2, 0x06F4, 1, 0), + MX6_PAD_KEY_ROW3__CSI_DATA15 = IOMUX_PAD(0x0308, 0x0040, 3, 0x05C4, 2, 0), + MX6_PAD_KEY_ROW3__GPIO3_IO31 = IOMUX_PAD(0x0308, 0x0040, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__SD1_VSELECT = IOMUX_PAD(0x0308, 0x0040, 6, 0x0000, 0, 0), + + MX6_PAD_KEY_COL4__KEY_COL4 = IOMUX_PAD(0x030C, 0x0044, 0, 0x06B0, 1, 0), + MX6_PAD_KEY_COL4__AUD6_RXD = IOMUX_PAD(0x030C, 0x0044, 1, 0x0594, 1, 0), + MX6_PAD_KEY_COL4__LCD_DATA08 = IOMUX_PAD(0x030C, 0x0044, 2, 0x06F8, 1, 0), + MX6_PAD_KEY_COL4__CSI_DATA16 = IOMUX_PAD(0x030C, 0x0044, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__GPIO4_IO00 = IOMUX_PAD(0x030C, 0x0044, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__USB_OTG1_PWR = IOMUX_PAD(0x030C, 0x0044, 6, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW4__KEY_ROW4 = IOMUX_PAD(0x0310, 0x0048, 0, 0x06D0, 1, 0), + MX6_PAD_KEY_ROW4__AUD6_TXC = IOMUX_PAD(0x0310, 0x0048, 1, 0x05A4, 1, 0), + MX6_PAD_KEY_ROW4__LCD_DATA09 = IOMUX_PAD(0x0310, 0x0048, 2, 0x06FC, 1, 0), + MX6_PAD_KEY_ROW4__CSI_DATA17 = IOMUX_PAD(0x0310, 0x0048, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__GPIO4_IO01 = IOMUX_PAD(0x0310, 0x0048, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__USB_OTG1_OC = IOMUX_PAD(0x0310, 0x0048, 6, 0x076C, 2, 0), + + MX6_PAD_KEY_COL5__KEY_COL5 = IOMUX_PAD(0x0314, 0x004C, 0, 0x0694, 1, 0), + MX6_PAD_KEY_COL5__AUD6_TXFS = IOMUX_PAD(0x0314, 0x004C, 1, 0x05A8, 1, 0), + MX6_PAD_KEY_COL5__LCD_DATA10 = IOMUX_PAD(0x0314, 0x004C, 2, 0x0700, 0, 0), + MX6_PAD_KEY_COL5__CSI_DATA18 = IOMUX_PAD(0x0314, 0x004C, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL5__GPIO4_IO02 = IOMUX_PAD(0x0314, 0x004C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL5__USB_OTG2_PWR = IOMUX_PAD(0x0314, 0x004C, 6, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW5__KEY_ROW5 = IOMUX_PAD(0x0318, 0x0050, 0, 0x06B4, 2, 0), + MX6_PAD_KEY_ROW5__AUD6_TXD = IOMUX_PAD(0x0318, 0x0050, 1, 0x0598, 1, 0), + MX6_PAD_KEY_ROW5__LCD_DATA11 = IOMUX_PAD(0x0318, 0x0050, 2, 0x0704, 1, 0), + MX6_PAD_KEY_ROW5__CSI_DATA19 = IOMUX_PAD(0x0318, 0x0050, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW5__GPIO4_IO03 = IOMUX_PAD(0x0318, 0x0050, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW5__USB_OTG2_OC = IOMUX_PAD(0x0318, 0x0050, 6, 0x0768, 3, 0), + + MX6_PAD_KEY_COL6__KEY_COL6 = IOMUX_PAD(0x031C, 0x0054, 0, 0x0698, 2, 0), + MX6_PAD_KEY_COL6__UART4_DCE_RX = IOMUX_PAD(0x031C, 0x0054, 1, 0x075C, 2, 0), + MX6_PAD_KEY_COL6__UART4_DTE_TX = IOMUX_PAD(0x031C, 0x0054, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL6__LCD_DATA12 = IOMUX_PAD(0x031C, 0x0054, 2, 0x0708, 1, 0), + MX6_PAD_KEY_COL6__CSI_DATA20 = IOMUX_PAD(0x031C, 0x0054, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL6__GPIO4_IO04 = IOMUX_PAD(0x031C, 0x0054, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL6__SD3_RESET = IOMUX_PAD(0x031C, 0x0054, 6, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW6__KEY_ROW6 = IOMUX_PAD(0x0320, 0x0058, 0, 0x06B8, 2, 0), + MX6_PAD_KEY_ROW6__UART4_DCE_TX = IOMUX_PAD(0x0320, 0x0058, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW6__UART4_DTE_RX = IOMUX_PAD(0x0320, 0x0058, 1, 0x075C, 3, 0), + MX6_PAD_KEY_ROW6__LCD_DATA13 = IOMUX_PAD(0x0320, 0x0058, 2, 0x070C, 1, 0), + MX6_PAD_KEY_ROW6__CSI_DATA21 = IOMUX_PAD(0x0320, 0x0058, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW6__GPIO4_IO05 = IOMUX_PAD(0x0320, 0x0058, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW6__SD3_VSELECT = IOMUX_PAD(0x0320, 0x0058, 6, 0x0000, 0, 0), + + MX6_PAD_KEY_COL7__KEY_COL7 = IOMUX_PAD(0x0324, 0x005C, 0, 0x069C, 2, 0), + MX6_PAD_KEY_COL7__UART4_DCE_RTS = IOMUX_PAD(0x0324, 0x005C, 1, 0x0758, 2, 0), + MX6_PAD_KEY_COL7__UART4_DTE_CTS = IOMUX_PAD(0x0324, 0x005C, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL7__LCD_DATA14 = IOMUX_PAD(0x0324, 0x005C, 2, 0x0710, 1, 0), + MX6_PAD_KEY_COL7__CSI_DATA22 = IOMUX_PAD(0x0324, 0x005C, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL7__GPIO4_IO06 = IOMUX_PAD(0x0324, 0x005C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL7__SD1_WP = IOMUX_PAD(0x0324, 0x005C, 6, 0x0774, 3, 0), + + MX6_PAD_KEY_ROW7__KEY_ROW7 = IOMUX_PAD(0x0328, 0x0060, 0, 0x06BC, 2, 0), + MX6_PAD_KEY_ROW7__UART4_DCE_CTS = IOMUX_PAD(0x0328, 0x0060, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW7__UART4_DTE_RTS = IOMUX_PAD(0x0328, 0x0060, 1, 0x0758, 3, 0), + MX6_PAD_KEY_ROW7__LCD_DATA15 = IOMUX_PAD(0x0328, 0x0060, 2, 0x0714, 1, 0), + MX6_PAD_KEY_ROW7__CSI_DATA23 = IOMUX_PAD(0x0328, 0x0060, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW7__GPIO4_IO07 = IOMUX_PAD(0x0328, 0x0060, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW7__SD1_CD_B = IOMUX_PAD(0x0328, 0x0060, 6, 0x0770, 3, 0), + + MX6_PAD_EPDC_DATA00__EPDC_DATA00 = IOMUX_PAD(0x032C, 0x0064, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA00__ECSPI4_MOSI = IOMUX_PAD(0x032C, 0x0064, 1, 0x0658, 2, 0), + MX6_PAD_EPDC_DATA00__LCD_DATA24 = IOMUX_PAD(0x032C, 0x0064, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA00__CSI_DATA00 = IOMUX_PAD(0x032C, 0x0064, 3, 0x05C8, 2, 0), + MX6_PAD_EPDC_DATA00__GPIO1_IO07 = IOMUX_PAD(0x032C, 0x0064, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA01__EPDC_DATA01 = IOMUX_PAD(0x0330, 0x0068, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA01__ECSPI4_MISO = IOMUX_PAD(0x0330, 0x0068, 1, 0x0654, 2, 0), + MX6_PAD_EPDC_DATA01__LCD_DATA25 = IOMUX_PAD(0x0330, 0x0068, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA01__CSI_DATA01 = IOMUX_PAD(0x0330, 0x0068, 3, 0x05CC, 2, 0), + MX6_PAD_EPDC_DATA01__GPIO1_IO08 = IOMUX_PAD(0x0330, 0x0068, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA02__EPDC_DATA02 = IOMUX_PAD(0x0334, 0x006C, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA02__ECSPI4_SS0 = IOMUX_PAD(0x0334, 0x006C, 1, 0x065C, 2, 0), + MX6_PAD_EPDC_DATA02__LCD_DATA26 = IOMUX_PAD(0x0334, 0x006C, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA02__CSI_DATA02 = IOMUX_PAD(0x0334, 0x006C, 3, 0x05D0, 2, 0), + MX6_PAD_EPDC_DATA02__GPIO1_IO09 = IOMUX_PAD(0x0334, 0x006C, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA03__EPDC_DATA03 = IOMUX_PAD(0x0338, 0x0070, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA03__ECSPI4_SCLK = IOMUX_PAD(0x0338, 0x0070, 1, 0x0650, 2, 0), + MX6_PAD_EPDC_DATA03__LCD_DATA27 = IOMUX_PAD(0x0338, 0x0070, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA03__CSI_DATA03 = IOMUX_PAD(0x0338, 0x0070, 3, 0x05D4, 2, 0), + MX6_PAD_EPDC_DATA03__GPIO1_IO10 = IOMUX_PAD(0x0338, 0x0070, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA04__EPDC_DATA04 = IOMUX_PAD(0x033C, 0x0074, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA04__ECSPI4_SS1 = IOMUX_PAD(0x033C, 0x0074, 1, 0x0660, 1, 0), + MX6_PAD_EPDC_DATA04__LCD_DATA28 = IOMUX_PAD(0x033C, 0x0074, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA04__CSI_DATA04 = IOMUX_PAD(0x033C, 0x0074, 3, 0x05D8, 2, 0), + MX6_PAD_EPDC_DATA04__GPIO1_IO11 = IOMUX_PAD(0x033C, 0x0074, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA05__EPDC_DATA05 = IOMUX_PAD(0x0340, 0x0078, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA05__ECSPI4_SS2 = IOMUX_PAD(0x0340, 0x0078, 1, 0x0664, 1, 0), + MX6_PAD_EPDC_DATA05__LCD_DATA29 = IOMUX_PAD(0x0340, 0x0078, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA05__CSI_DATA05 = IOMUX_PAD(0x0340, 0x0078, 3, 0x05DC, 2, 0), + MX6_PAD_EPDC_DATA05__GPIO1_IO12 = IOMUX_PAD(0x0340, 0x0078, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA06__EPDC_DATA06 = IOMUX_PAD(0x0344, 0x007C, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA06__ECSPI4_SS3 = IOMUX_PAD(0x0344, 0x007C, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA06__LCD_DATA30 = IOMUX_PAD(0x0344, 0x007C, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA06__CSI_DATA06 = IOMUX_PAD(0x0344, 0x007C, 3, 0x05E0, 2, 0), + MX6_PAD_EPDC_DATA06__GPIO1_IO13 = IOMUX_PAD(0x0344, 0x007C, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA07__EPDC_DATA07 = IOMUX_PAD(0x0348, 0x0080, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA07__ECSPI4_RDY = IOMUX_PAD(0x0348, 0x0080, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA07__LCD_DATA31 = IOMUX_PAD(0x0348, 0x0080, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA07__CSI_DATA07 = IOMUX_PAD(0x0348, 0x0080, 3, 0x05E4, 2, 0), + MX6_PAD_EPDC_DATA07__GPIO1_IO14 = IOMUX_PAD(0x0348, 0x0080, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA08__EPDC_DATA08 = IOMUX_PAD(0x034C, 0x0084, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA08__ECSPI3_MOSI = IOMUX_PAD(0x034C, 0x0084, 1, 0x063C, 2, 0), + MX6_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 = IOMUX_PAD(0x034C, 0x0084, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA08__GPIO1_IO15 = IOMUX_PAD(0x034C, 0x0084, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA09__EPDC_DATA09 = IOMUX_PAD(0x0350, 0x0088, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA09__ECSPI3_MISO = IOMUX_PAD(0x0350, 0x0088, 1, 0x0638, 2, 0), + MX6_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 = IOMUX_PAD(0x0350, 0x0088, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA09__GPIO1_IO16 = IOMUX_PAD(0x0350, 0x0088, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA10__EPDC_DATA10 = IOMUX_PAD(0x0354, 0x008C, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA10__ECSPI3_SS0 = IOMUX_PAD(0x0354, 0x008C, 1, 0x0648, 2, 0), + MX6_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 = IOMUX_PAD(0x0354, 0x008C, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA10__GPIO1_IO17 = IOMUX_PAD(0x0354, 0x008C, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA11__EPDC_DATA11 = IOMUX_PAD(0x0358, 0x0090, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA11__ECSPI3_SCLK = IOMUX_PAD(0x0358, 0x0090, 1, 0x0630, 2, 0), + MX6_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 = IOMUX_PAD(0x0358, 0x0090, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA11__GPIO1_IO18 = IOMUX_PAD(0x0358, 0x0090, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA12__EPDC_DATA12 = IOMUX_PAD(0x035C, 0x0094, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA12__UART2_DCE_RX = IOMUX_PAD(0x035C, 0x0094, 1, 0x074C, 4, 0), + MX6_PAD_EPDC_DATA12__UART2_DTE_TX = IOMUX_PAD(0x035C, 0x0094, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA12__EPDC_PWR_COM = IOMUX_PAD(0x035C, 0x0094, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA12__GPIO1_IO19 = IOMUX_PAD(0x035C, 0x0094, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA12__ECSPI3_SS1 = IOMUX_PAD(0x035C, 0x0094, 6, 0x064C, 1, 0), + + MX6_PAD_EPDC_DATA13__EPDC_DATA13 = IOMUX_PAD(0x0360, 0x0098, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA13__UART2_DCE_TX = IOMUX_PAD(0x0360, 0x0098, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA13__UART2_DTE_RX = IOMUX_PAD(0x0360, 0x0098, 1, 0x074C, 5, 0), + MX6_PAD_EPDC_DATA13__EPDC_PWR_IRQ = IOMUX_PAD(0x0360, 0x0098, 2, 0x0668, 0, 0), + MX6_PAD_EPDC_DATA13__GPIO1_IO20 = IOMUX_PAD(0x0360, 0x0098, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA13__ECSPI3_SS2 = IOMUX_PAD(0x0360, 0x0098, 6, 0x0640, 1, 0), + + MX6_PAD_EPDC_DATA14__EPDC_DATA14 = IOMUX_PAD(0x0364, 0x009C, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA14__UART2_DCE_RTS = IOMUX_PAD(0x0364, 0x009C, 1, 0x0748, 4, 0), + MX6_PAD_EPDC_DATA14__UART2_DTE_CTS = IOMUX_PAD(0x0364, 0x009C, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA14__EPDC_PWR_STAT = IOMUX_PAD(0x0364, 0x009C, 2, 0x066C, 0, 0), + MX6_PAD_EPDC_DATA14__GPIO1_IO21 = IOMUX_PAD(0x0364, 0x009C, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA14__ECSPI3_SS3 = IOMUX_PAD(0x0364, 0x009C, 6, 0x0644, 1, 0), + + MX6_PAD_EPDC_DATA15__EPDC_DATA15 = IOMUX_PAD(0x0368, 0x00A0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA15__UART2_DCE_CTS = IOMUX_PAD(0x0368, 0x00A0, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA15__UART2_DTE_RTS = IOMUX_PAD(0x0368, 0x00A0, 1, 0x0748, 5, 0), + MX6_PAD_EPDC_DATA15__EPDC_PWR_WAKE = IOMUX_PAD(0x0368, 0x00A0, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA15__GPIO1_IO22 = IOMUX_PAD(0x0368, 0x00A0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA15__ECSPI3_RDY = IOMUX_PAD(0x0368, 0x00A0, 6, 0x0634, 1, 0), + + MX6_PAD_EPDC_SDCLK__EPDC_SDCLK_P = IOMUX_PAD(0x036C, 0x00A4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCLK__ECSPI2_MOSI = IOMUX_PAD(0x036C, 0x00A4, 1, 0x0624, 2, 0), + MX6_PAD_EPDC_SDCLK__I2C2_SCL = IOMUX_PAD(0x036C, 0x00A4, IOMUX_CONFIG_SION | 2, 0x0684, 2, 0), + MX6_PAD_EPDC_SDCLK__CSI_DATA08 = IOMUX_PAD(0x036C, 0x00A4, 3, 0x05E8, 2, 0), + MX6_PAD_EPDC_SDCLK__GPIO1_IO23 = IOMUX_PAD(0x036C, 0x00A4, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_SDLE__EPDC_SDLE = IOMUX_PAD(0x0370, 0x00A8, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDLE__ECSPI2_MISO = IOMUX_PAD(0x0370, 0x00A8, 1, 0x0620, 2, 0), + MX6_PAD_EPDC_SDLE__I2C2_SDA = IOMUX_PAD(0x0370, 0x00A8, IOMUX_CONFIG_SION | 2, 0x0688, 2, 0), + MX6_PAD_EPDC_SDLE__CSI_DATA09 = IOMUX_PAD(0x0370, 0x00A8, 3, 0x05EC, 2, 0), + MX6_PAD_EPDC_SDLE__GPIO1_IO24 = IOMUX_PAD(0x0370, 0x00A8, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_SDOE__EPDC_SDOE = IOMUX_PAD(0x0374, 0x00AC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDOE__ECSPI2_SS0 = IOMUX_PAD(0x0374, 0x00AC, 1, 0x0628, 1, 0), + MX6_PAD_EPDC_SDOE__CSI_DATA10 = IOMUX_PAD(0x0374, 0x00AC, 3, 0x05B0, 2, 0), + MX6_PAD_EPDC_SDOE__GPIO1_IO25 = IOMUX_PAD(0x0374, 0x00AC, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_SDSHR__EPDC_SDSHR = IOMUX_PAD(0x0378, 0x00B0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDSHR__ECSPI2_SCLK = IOMUX_PAD(0x0378, 0x00B0, 1, 0x061C, 2, 0), + MX6_PAD_EPDC_SDSHR__EPDC_SDCE4 = IOMUX_PAD(0x0378, 0x00B0, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_SDSHR__CSI_DATA11 = IOMUX_PAD(0x0378, 0x00B0, 3, 0x05B4, 2, 0), + MX6_PAD_EPDC_SDSHR__GPIO1_IO26 = IOMUX_PAD(0x0378, 0x00B0, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_SDCE0__EPDC_SDCE0 = IOMUX_PAD(0x037C, 0x00B4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE0__ECSPI2_SS1 = IOMUX_PAD(0x037C, 0x00B4, 1, 0x062C, 1, 0), + MX6_PAD_EPDC_SDCE0__PWM3_OUT = IOMUX_PAD(0x037C, 0x00B4, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE0__GPIO1_IO27 = IOMUX_PAD(0x037C, 0x00B4, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_SDCE1__EPDC_SDCE1 = IOMUX_PAD(0x0380, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE1__WDOG2_B = IOMUX_PAD(0x0380, 0x00B8, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE1__PWM4_OUT = IOMUX_PAD(0x0380, 0x00B8, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE1__GPIO1_IO28 = IOMUX_PAD(0x0380, 0x00B8, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_SDCE2__EPDC_SDCE2 = IOMUX_PAD(0x0384, 0x00BC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE2__I2C3_SCL = IOMUX_PAD(0x0384, 0x00BC, IOMUX_CONFIG_SION | 1, 0x068C, 2, 0), + MX6_PAD_EPDC_SDCE2__PWM1_OUT = IOMUX_PAD(0x0384, 0x00BC, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE2__GPIO1_IO29 = IOMUX_PAD(0x0384, 0x00BC, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_SDCE3__EPDC_SDCE3 = IOMUX_PAD(0x0388, 0x00C0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE3__I2C3_SDA = IOMUX_PAD(0x0388, 0x00C0, IOMUX_CONFIG_SION | 1, 0x0690, 2, 0), + MX6_PAD_EPDC_SDCE3__PWM2_OUT = IOMUX_PAD(0x0388, 0x00C0, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE3__GPIO1_IO30 = IOMUX_PAD(0x0388, 0x00C0, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_GDCLK__EPDC_GDCLK = IOMUX_PAD(0x038C, 0x00C4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDCLK__ECSPI2_SS2 = IOMUX_PAD(0x038C, 0x00C4, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_GDCLK__CSI_PIXCLK = IOMUX_PAD(0x038C, 0x00C4, 3, 0x05F4, 2, 0), + MX6_PAD_EPDC_GDCLK__GPIO1_IO31 = IOMUX_PAD(0x038C, 0x00C4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDCLK__SD2_RESET = IOMUX_PAD(0x038C, 0x00C4, 6, 0x0000, 0, 0), + + MX6_PAD_EPDC_GDOE__EPDC_GDOE = IOMUX_PAD(0x0390, 0x00C8, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDOE__ECSPI2_SS3 = IOMUX_PAD(0x0390, 0x00C8, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_GDOE__CSI_HSYNC = IOMUX_PAD(0x0390, 0x00C8, 3, 0x05F0, 2, 0), + MX6_PAD_EPDC_GDOE__GPIO2_IO00 = IOMUX_PAD(0x0390, 0x00C8, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDOE__SD2_VSELECT = IOMUX_PAD(0x0390, 0x00C8, 6, 0x0000, 0, 0), + + MX6_PAD_EPDC_GDRL__EPDC_GDRL = IOMUX_PAD(0x0394, 0x00CC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDRL__ECSPI2_RDY = IOMUX_PAD(0x0394, 0x00CC, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_GDRL__CSI_MCLK = IOMUX_PAD(0x0394, 0x00CC, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_GDRL__GPIO2_IO01 = IOMUX_PAD(0x0394, 0x00CC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDRL__SD2_WP = IOMUX_PAD(0x0394, 0x00CC, 6, 0x077C, 2, 0), + + MX6_PAD_EPDC_GDSP__EPDC_GDSP = IOMUX_PAD(0x0398, 0x00D0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDSP__PWM4_OUT = IOMUX_PAD(0x0398, 0x00D0, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_GDSP__CSI_VSYNC = IOMUX_PAD(0x0398, 0x00D0, 3, 0x05F8, 2, 0), + MX6_PAD_EPDC_GDSP__GPIO2_IO02 = IOMUX_PAD(0x0398, 0x00D0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDSP__SD2_CD_B = IOMUX_PAD(0x0398, 0x00D0, 6, 0x0778, 2, 0), + + MX6_PAD_EPDC_VCOM0__EPDC_VCOM0 = IOMUX_PAD(0x039C, 0x00D4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM0__AUD5_RXFS = IOMUX_PAD(0x039C, 0x00D4, 1, 0x0588, 1, 0), + MX6_PAD_EPDC_VCOM0__UART3_DCE_RX = IOMUX_PAD(0x039C, 0x00D4, 2, 0x0754, 4, 0), + MX6_PAD_EPDC_VCOM0__UART3_DTE_TX = IOMUX_PAD(0x039C, 0x00D4, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM0__GPIO2_IO03 = IOMUX_PAD(0x039C, 0x00D4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM0__EPDC_SDCE5 = IOMUX_PAD(0x039C, 0x00D4, 6, 0x0000, 0, 0), + + MX6_PAD_EPDC_VCOM1__EPDC_VCOM1 = IOMUX_PAD(0x03A0, 0x00D8, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM1__AUD5_RXD = IOMUX_PAD(0x03A0, 0x00D8, 1, 0x057C, 1, 0), + MX6_PAD_EPDC_VCOM1__UART3_DCE_TX = IOMUX_PAD(0x03A0, 0x00D8, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM1__UART3_DTE_RX = IOMUX_PAD(0x03A0, 0x00D8, 2, 0x0754, 5, 0), + MX6_PAD_EPDC_VCOM1__GPIO2_IO04 = IOMUX_PAD(0x03A0, 0x00D8, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM1__EPDC_SDCE6 = IOMUX_PAD(0x03A0, 0x00D8, 6, 0x0000, 0, 0), + + MX6_PAD_EPDC_BDR0__EPDC_BDR0 = IOMUX_PAD(0x03A4, 0x00DC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR0__UART3_DCE_RTS = IOMUX_PAD(0x03A4, 0x00DC, 2, 0x0750, 2, 0), + MX6_PAD_EPDC_BDR0__UART3_DTE_CTS = IOMUX_PAD(0x03A4, 0x00DC, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR0__GPIO2_IO05 = IOMUX_PAD(0x03A4, 0x00DC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR0__EPDC_SDCE7 = IOMUX_PAD(0x03A4, 0x00DC, 6, 0x0000, 0, 0), + + MX6_PAD_EPDC_BDR1__EPDC_BDR1 = IOMUX_PAD(0x03A8, 0x00E0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR1__UART3_DCE_CTS = IOMUX_PAD(0x03A8, 0x00E0, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR1__UART3_DTE_RTS = IOMUX_PAD(0x03A8, 0x00E0, 2, 0x0750, 3, 0), + MX6_PAD_EPDC_BDR1__GPIO2_IO06 = IOMUX_PAD(0x03A8, 0x00E0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR1__EPDC_SDCE8 = IOMUX_PAD(0x03A8, 0x00E0, 6, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0 = IOMUX_PAD(0x03AC, 0x00E4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_CTRL0__AUD5_RXC = IOMUX_PAD(0x03AC, 0x00E4, 1, 0x0584, 1, 0), + MX6_PAD_EPDC_PWR_CTRL0__LCD_DATA16 = IOMUX_PAD(0x03AC, 0x00E4, 2, 0x0718, 1, 0), + MX6_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 = IOMUX_PAD(0x03AC, 0x00E4, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1 = IOMUX_PAD(0x03B0, 0x00E8, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_CTRL1__AUD5_TXFS = IOMUX_PAD(0x03B0, 0x00E8, 1, 0x0590, 1, 0), + MX6_PAD_EPDC_PWR_CTRL1__LCD_DATA17 = IOMUX_PAD(0x03B0, 0x00E8, 2, 0x071C, 1, 0), + MX6_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 = IOMUX_PAD(0x03B0, 0x00E8, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2 = IOMUX_PAD(0x03B4, 0x00EC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_CTRL2__AUD5_TXD = IOMUX_PAD(0x03B4, 0x00EC, 1, 0x0580, 1, 0), + MX6_PAD_EPDC_PWR_CTRL2__LCD_DATA18 = IOMUX_PAD(0x03B4, 0x00EC, 2, 0x0720, 1, 0), + MX6_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 = IOMUX_PAD(0x03B4, 0x00EC, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3 = IOMUX_PAD(0x03B8, 0x00F0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_CTRL3__AUD5_TXC = IOMUX_PAD(0x03B8, 0x00F0, 1, 0x058C, 1, 0), + MX6_PAD_EPDC_PWR_CTRL3__LCD_DATA19 = IOMUX_PAD(0x03B8, 0x00F0, 2, 0x0724, 1, 0), + MX6_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 = IOMUX_PAD(0x03B8, 0x00F0, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWR_COM__EPDC_PWR_COM = IOMUX_PAD(0x03BC, 0x00F4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_COM__LCD_DATA20 = IOMUX_PAD(0x03BC, 0x00F4, 2, 0x0728, 1, 0), + MX6_PAD_EPDC_PWR_COM__USB_OTG1_ID = IOMUX_PAD(0x03BC, 0x00F4, 4, 0x055C, 4, 0), + MX6_PAD_EPDC_PWR_COM__GPIO2_IO11 = IOMUX_PAD(0x03BC, 0x00F4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_COM__SD3_RESET = IOMUX_PAD(0x03BC, 0x00F4, 6, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ = IOMUX_PAD(0x03C0, 0x00F8, 0, 0x0668, 1, 0), + MX6_PAD_EPDC_PWR_IRQ__LCD_DATA21 = IOMUX_PAD(0x03C0, 0x00F8, 2, 0x072C, 1, 0), + MX6_PAD_EPDC_PWR_IRQ__USB_OTG2_ID = IOMUX_PAD(0x03C0, 0x00F8, 4, 0x0560, 3, 0), + MX6_PAD_EPDC_PWR_IRQ__GPIO2_IO12 = IOMUX_PAD(0x03C0, 0x00F8, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_IRQ__SD3_VSELECT = IOMUX_PAD(0x03C0, 0x00F8, 6, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT = IOMUX_PAD(0x03C4, 0x00FC, 0, 0x066C, 1, 0), + MX6_PAD_EPDC_PWR_STAT__LCD_DATA22 = IOMUX_PAD(0x03C4, 0x00FC, 2, 0x0730, 1, 0), + MX6_PAD_EPDC_PWR_STAT__ARM_EVENTI = IOMUX_PAD(0x03C4, 0x00FC, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_STAT__GPIO2_IO13 = IOMUX_PAD(0x03C4, 0x00FC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_STAT__SD3_WP = IOMUX_PAD(0x03C4, 0x00FC, 6, 0x0794, 2, 0), + + MX6_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE = IOMUX_PAD(0x03C8, 0x0100, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_WAKE__LCD_DATA23 = IOMUX_PAD(0x03C8, 0x0100, 2, 0x0734, 1, 0), + MX6_PAD_EPDC_PWR_WAKE__ARM_EVENTO = IOMUX_PAD(0x03C8, 0x0100, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_WAKE__GPIO2_IO14 = IOMUX_PAD(0x03C8, 0x0100, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_WAKE__SD3_CD_B = IOMUX_PAD(0x03C8, 0x0100, 6, 0x0780, 2, 0), + + MX6_PAD_LCD_CLK__LCD_CLK = IOMUX_PAD(0x03CC, 0x0104, 0, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__LCD_WR_RWN = IOMUX_PAD(0x03CC, 0x0104, 2, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__PWM4_OUT = IOMUX_PAD(0x03CC, 0x0104, 4, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__GPIO2_IO15 = IOMUX_PAD(0x03CC, 0x0104, 5, 0x0000, 0, 0), + + MX6_PAD_LCD_ENABLE__LCD_ENABLE = IOMUX_PAD(0x03D0, 0x0108, 0, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__LCD_RD_E = IOMUX_PAD(0x03D0, 0x0108, 2, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__UART2_DCE_RX = IOMUX_PAD(0x03D0, 0x0108, 4, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__UART2_DTE_TX = IOMUX_PAD(0x03D0, 0x0108, 4, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__GPIO2_IO16 = IOMUX_PAD(0x03D0, 0x0108, 5, 0x0000, 0, 0), + + MX6_PAD_LCD_HSYNC__LCD_HSYNC = IOMUX_PAD(0x03D4, 0x010C, 0, 0x06D4, 0, 0), + MX6_PAD_LCD_HSYNC__LCD_CS = IOMUX_PAD(0x03D4, 0x010C, 2, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__UART2_DCE_TX = IOMUX_PAD(0x03D4, 0x010C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__UART2_DTE_RX = IOMUX_PAD(0x03D4, 0x010C, 4, 0x074C, 1, 0), + MX6_PAD_LCD_HSYNC__GPIO2_IO17 = IOMUX_PAD(0x03D4, 0x010C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__ARM_TRACE_CLK = IOMUX_PAD(0x03D4, 0x010C, 6, 0x0000, 0, 0), + + MX6_PAD_LCD_VSYNC__LCD_VSYNC = IOMUX_PAD(0x03D8, 0x0110, 0, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__LCD_RS = IOMUX_PAD(0x03D8, 0x0110, 2, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__UART2_DCE_RTS = IOMUX_PAD(0x03D8, 0x0110, 4, 0x0748, 0, 0), + MX6_PAD_LCD_VSYNC__UART2_DTE_CTS = IOMUX_PAD(0x03D8, 0x0110, 4, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__GPIO2_IO18 = IOMUX_PAD(0x03D8, 0x0110, 5, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__ARM_TRACE_CTL = IOMUX_PAD(0x03D8, 0x0110, 6, 0x0000, 0, 0), + + MX6_PAD_LCD_RESET__LCD_RESET = IOMUX_PAD(0x03DC, 0x0114, 0, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__LCD_BUSY = IOMUX_PAD(0x03DC, 0x0114, 2, 0x06D4, 1, 0), + MX6_PAD_LCD_RESET__UART2_DCE_CTS = IOMUX_PAD(0x03DC, 0x0114, 4, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__UART2_DTE_RTS = IOMUX_PAD(0x03DC, 0x0114, 4, 0x0748, 1, 0), + MX6_PAD_LCD_RESET__GPIO2_IO19 = IOMUX_PAD(0x03DC, 0x0114, 5, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__CCM_PMIC_READY = IOMUX_PAD(0x03DC, 0x0114, 6, 0x05AC, 2, 0), + + MX6_PAD_LCD_DATA00__LCD_DATA00 = IOMUX_PAD(0x03E0, 0x0118, 0, 0x06D8, 1, 0), + MX6_PAD_LCD_DATA00__ECSPI1_MOSI = IOMUX_PAD(0x03E0, 0x0118, 1, 0x0608, 0, 0), + MX6_PAD_LCD_DATA00__USB_OTG2_ID = IOMUX_PAD(0x03E0, 0x0118, 2, 0x0560, 2, 0), + MX6_PAD_LCD_DATA00__PWM1_OUT = IOMUX_PAD(0x03E0, 0x0118, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__UART5_DTR_B = IOMUX_PAD(0x03E0, 0x0118, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__GPIO2_IO20 = IOMUX_PAD(0x03E0, 0x0118, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__ARM_TRACE00 = IOMUX_PAD(0x03E0, 0x0118, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__SRC_BOOT_CFG00 = IOMUX_PAD(0x03E0, 0x0118, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA01__LCD_DATA01 = IOMUX_PAD(0x03E4, 0x011C, 0, 0x06DC, 1, 0), + MX6_PAD_LCD_DATA01__ECSPI1_MISO = IOMUX_PAD(0x03E4, 0x011C, 1, 0x0604, 0, 0), + MX6_PAD_LCD_DATA01__USB_OTG1_ID = IOMUX_PAD(0x03E4, 0x011C, 2, 0x055C, 3, 0), + MX6_PAD_LCD_DATA01__PWM2_OUT = IOMUX_PAD(0x03E4, 0x011C, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__AUD4_RXFS = IOMUX_PAD(0x03E4, 0x011C, 4, 0x0570, 0, 0), + MX6_PAD_LCD_DATA01__GPIO2_IO21 = IOMUX_PAD(0x03E4, 0x011C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__ARM_TRACE01 = IOMUX_PAD(0x03E4, 0x011C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__SRC_BOOT_CFG01 = IOMUX_PAD(0x03E4, 0x011C, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA02__LCD_DATA02 = IOMUX_PAD(0x03E8, 0x0120, 0, 0x06E0, 1, 0), + MX6_PAD_LCD_DATA02__ECSPI1_SS0 = IOMUX_PAD(0x03E8, 0x0120, 1, 0x0614, 0, 0), + MX6_PAD_LCD_DATA02__EPIT2_OUT = IOMUX_PAD(0x03E8, 0x0120, 2, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__PWM3_OUT = IOMUX_PAD(0x03E8, 0x0120, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__AUD4_RXC = IOMUX_PAD(0x03E8, 0x0120, 4, 0x056C, 0, 0), + MX6_PAD_LCD_DATA02__GPIO2_IO22 = IOMUX_PAD(0x03E8, 0x0120, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__ARM_TRACE02 = IOMUX_PAD(0x03E8, 0x0120, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__SRC_BOOT_CFG02 = IOMUX_PAD(0x03E8, 0x0120, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA03__LCD_DATA03 = IOMUX_PAD(0x03EC, 0x0124, 0, 0x06E4, 1, 0), + MX6_PAD_LCD_DATA03__ECSPI1_SCLK = IOMUX_PAD(0x03EC, 0x0124, 1, 0x05FC, 0, 0), + MX6_PAD_LCD_DATA03__UART5_DSR_B = IOMUX_PAD(0x03EC, 0x0124, 2, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__PWM4_OUT = IOMUX_PAD(0x03EC, 0x0124, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__AUD4_RXD = IOMUX_PAD(0x03EC, 0x0124, 4, 0x0564, 0, 0), + MX6_PAD_LCD_DATA03__GPIO2_IO23 = IOMUX_PAD(0x03EC, 0x0124, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__ARM_TRACE03 = IOMUX_PAD(0x03EC, 0x0124, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__SRC_BOOT_CFG03 = IOMUX_PAD(0x03EC, 0x0124, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA04__LCD_DATA04 = IOMUX_PAD(0x03F0, 0x0128, 0, 0x06E8, 1, 0), + MX6_PAD_LCD_DATA04__ECSPI1_SS1 = IOMUX_PAD(0x03F0, 0x0128, 1, 0x060C, 1, 0), + MX6_PAD_LCD_DATA04__CSI_VSYNC = IOMUX_PAD(0x03F0, 0x0128, 2, 0x05F8, 0, 0), + MX6_PAD_LCD_DATA04__WDOG2_RESET_B_DEB = IOMUX_PAD(0x03F0, 0x0128, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__AUD4_TXC = IOMUX_PAD(0x03F0, 0x0128, 4, 0x0574, 0, 0), + MX6_PAD_LCD_DATA04__GPIO2_IO24 = IOMUX_PAD(0x03F0, 0x0128, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__ARM_TRACE04 = IOMUX_PAD(0x03F0, 0x0128, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__SRC_BOOT_CFG04 = IOMUX_PAD(0x03F0, 0x0128, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA05__LCD_DATA05 = IOMUX_PAD(0x03F4, 0x012C, 0, 0x06EC, 1, 0), + MX6_PAD_LCD_DATA05__ECSPI1_SS2 = IOMUX_PAD(0x03F4, 0x012C, 1, 0x0610, 1, 0), + MX6_PAD_LCD_DATA05__CSI_HSYNC = IOMUX_PAD(0x03F4, 0x012C, 2, 0x05F0, 0, 0), + MX6_PAD_LCD_DATA05__AUD4_TXFS = IOMUX_PAD(0x03F4, 0x012C, 4, 0x0578, 0, 0), + MX6_PAD_LCD_DATA05__GPIO2_IO25 = IOMUX_PAD(0x03F4, 0x012C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__ARM_TRACE05 = IOMUX_PAD(0x03F4, 0x012C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__SRC_BOOT_CFG05 = IOMUX_PAD(0x03F4, 0x012C, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA06__LCD_DATA06 = IOMUX_PAD(0x03F8, 0x0130, 0, 0x06F0, 1, 0), + MX6_PAD_LCD_DATA06__ECSPI1_SS3 = IOMUX_PAD(0x03F8, 0x0130, 1, 0x0618, 0, 0), + MX6_PAD_LCD_DATA06__CSI_PIXCLK = IOMUX_PAD(0x03F8, 0x0130, 2, 0x05F4, 0, 0), + MX6_PAD_LCD_DATA06__AUD4_TXD = IOMUX_PAD(0x03F8, 0x0130, 4, 0x0568, 0, 0), + MX6_PAD_LCD_DATA06__GPIO2_IO26 = IOMUX_PAD(0x03F8, 0x0130, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__ARM_TRACE06 = IOMUX_PAD(0x03F8, 0x0130, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__SRC_BOOT_CFG06 = IOMUX_PAD(0x03F8, 0x0130, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA07__LCD_DATA07 = IOMUX_PAD(0x03FC, 0x0134, 0, 0x06F4, 0, 0), + MX6_PAD_LCD_DATA07__ECSPI1_RDY = IOMUX_PAD(0x03FC, 0x0134, 1, 0x0600, 0, 0), + MX6_PAD_LCD_DATA07__CSI_MCLK = IOMUX_PAD(0x03FC, 0x0134, 2, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__AUDIO_CLK_OUT = IOMUX_PAD(0x03FC, 0x0134, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__GPIO2_IO27 = IOMUX_PAD(0x03FC, 0x0134, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__ARM_TRACE07 = IOMUX_PAD(0x03FC, 0x0134, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__SRC_BOOT_CFG07 = IOMUX_PAD(0x03FC, 0x0134, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA08__LCD_DATA08 = IOMUX_PAD(0x0400, 0x0138, 0, 0x06F8, 0, 0), + MX6_PAD_LCD_DATA08__KEY_COL0 = IOMUX_PAD(0x0400, 0x0138, 1, 0x06A0, 1, 0), + MX6_PAD_LCD_DATA08__CSI_DATA09 = IOMUX_PAD(0x0400, 0x0138, 2, 0x05EC, 0, 0), + MX6_PAD_LCD_DATA08__ECSPI2_SCLK = IOMUX_PAD(0x0400, 0x0138, 4, 0x061C, 0, 0), + MX6_PAD_LCD_DATA08__GPIO2_IO28 = IOMUX_PAD(0x0400, 0x0138, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__ARM_TRACE08 = IOMUX_PAD(0x0400, 0x0138, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__SRC_BOOT_CFG08 = IOMUX_PAD(0x0400, 0x0138, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA09__LCD_DATA09 = IOMUX_PAD(0x0404, 0x013C, 0, 0x06FC, 0, 0), + MX6_PAD_LCD_DATA09__KEY_ROW0 = IOMUX_PAD(0x0404, 0x013C, 1, 0x06C0, 1, 0), + MX6_PAD_LCD_DATA09__CSI_DATA08 = IOMUX_PAD(0x0404, 0x013C, 2, 0x05E8, 0, 0), + MX6_PAD_LCD_DATA09__ECSPI2_MOSI = IOMUX_PAD(0x0404, 0x013C, 4, 0x0624, 0, 0), + MX6_PAD_LCD_DATA09__GPIO2_IO29 = IOMUX_PAD(0x0404, 0x013C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__ARM_TRACE09 = IOMUX_PAD(0x0404, 0x013C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__SRC_BOOT_CFG09 = IOMUX_PAD(0x0404, 0x013C, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA10__LCD_DATA10 = IOMUX_PAD(0x0408, 0x0140, 0, 0x0700, 1, 0), + MX6_PAD_LCD_DATA10__KEY_COL1 = IOMUX_PAD(0x0408, 0x0140, 1, 0x06A4, 1, 0), + MX6_PAD_LCD_DATA10__CSI_DATA07 = IOMUX_PAD(0x0408, 0x0140, 2, 0x05E4, 0, 0), + MX6_PAD_LCD_DATA10__ECSPI2_MISO = IOMUX_PAD(0x0408, 0x0140, 4, 0x0620, 0, 0), + MX6_PAD_LCD_DATA10__GPIO2_IO30 = IOMUX_PAD(0x0408, 0x0140, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__ARM_TRACE10 = IOMUX_PAD(0x0408, 0x0140, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x0408, 0x0140, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA11__LCD_DATA11 = IOMUX_PAD(0x040C, 0x0144, 0, 0x0704, 0, 0), + MX6_PAD_LCD_DATA11__KEY_ROW1 = IOMUX_PAD(0x040C, 0x0144, 1, 0x06C4, 1, 0), + MX6_PAD_LCD_DATA11__CSI_DATA06 = IOMUX_PAD(0x040C, 0x0144, 2, 0x05E0, 0, 0), + MX6_PAD_LCD_DATA11__ECSPI2_SS1 = IOMUX_PAD(0x040C, 0x0144, 4, 0x062C, 0, 0), + MX6_PAD_LCD_DATA11__GPIO2_IO31 = IOMUX_PAD(0x040C, 0x0144, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__ARM_TRACE11 = IOMUX_PAD(0x040C, 0x0144, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x040C, 0x0144, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA12__LCD_DATA12 = IOMUX_PAD(0x0410, 0x0148, 0, 0x0708, 0, 0), + MX6_PAD_LCD_DATA12__KEY_COL2 = IOMUX_PAD(0x0410, 0x0148, 1, 0x06A8, 1, 0), + MX6_PAD_LCD_DATA12__CSI_DATA05 = IOMUX_PAD(0x0410, 0x0148, 2, 0x05DC, 0, 0), + MX6_PAD_LCD_DATA12__UART5_DCE_RTS = IOMUX_PAD(0x0410, 0x0148, 4, 0x0760, 0, 0), + MX6_PAD_LCD_DATA12__UART5_DTE_CTS = IOMUX_PAD(0x0410, 0x0148, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__GPIO3_IO00 = IOMUX_PAD(0x0410, 0x0148, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__ARM_TRACE12 = IOMUX_PAD(0x0410, 0x0148, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0410, 0x0148, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA13__LCD_DATA13 = IOMUX_PAD(0x0414, 0x014C, 0, 0x070C, 0, 0), + MX6_PAD_LCD_DATA13__KEY_ROW2 = IOMUX_PAD(0x0414, 0x014C, 1, 0x06C8, 1, 0), + MX6_PAD_LCD_DATA13__CSI_DATA04 = IOMUX_PAD(0x0414, 0x014C, 2, 0x05D8, 0, 0), + MX6_PAD_LCD_DATA13__UART5_DCE_CTS = IOMUX_PAD(0x0414, 0x014C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__UART5_DTE_RTS = IOMUX_PAD(0x0414, 0x014C, 4, 0x0760, 1, 0), + MX6_PAD_LCD_DATA13__GPIO3_IO01 = IOMUX_PAD(0x0414, 0x014C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__ARM_TRACE13 = IOMUX_PAD(0x0414, 0x014C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x0414, 0x014C, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA14__LCD_DATA14 = IOMUX_PAD(0x0418, 0x0150, 0, 0x0710, 0, 0), + MX6_PAD_LCD_DATA14__KEY_COL3 = IOMUX_PAD(0x0418, 0x0150, 1, 0x06AC, 1, 0), + MX6_PAD_LCD_DATA14__CSI_DATA03 = IOMUX_PAD(0x0418, 0x0150, 2, 0x05D4, 0, 0), + MX6_PAD_LCD_DATA14__UART5_DCE_RX = IOMUX_PAD(0x0418, 0x0150, 4, 0x0764, 0, 0), + MX6_PAD_LCD_DATA14__UART5_DTE_TX = IOMUX_PAD(0x0418, 0x0150, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__GPIO3_IO02 = IOMUX_PAD(0x0418, 0x0150, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__ARM_TRACE14 = IOMUX_PAD(0x0418, 0x0150, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x0418, 0x0150, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA15__LCD_DATA15 = IOMUX_PAD(0x041C, 0x0154, 0, 0x0714, 0, 0), + MX6_PAD_LCD_DATA15__KEY_ROW3 = IOMUX_PAD(0x041C, 0x0154, 1, 0x06CC, 0, 0), + MX6_PAD_LCD_DATA15__CSI_DATA02 = IOMUX_PAD(0x041C, 0x0154, 2, 0x05D0, 0, 0), + MX6_PAD_LCD_DATA15__UART5_DCE_TX = IOMUX_PAD(0x041C, 0x0154, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__UART5_DTE_RX = IOMUX_PAD(0x041C, 0x0154, 4, 0x0764, 1, 0), + MX6_PAD_LCD_DATA15__GPIO3_IO03 = IOMUX_PAD(0x041C, 0x0154, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__ARM_TRACE15 = IOMUX_PAD(0x041C, 0x0154, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x041C, 0x0154, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA16__LCD_DATA16 = IOMUX_PAD(0x0420, 0x0158, 0, 0x0718, 0, 0), + MX6_PAD_LCD_DATA16__KEY_COL4 = IOMUX_PAD(0x0420, 0x0158, 1, 0x06B0, 0, 0), + MX6_PAD_LCD_DATA16__CSI_DATA01 = IOMUX_PAD(0x0420, 0x0158, 2, 0x05CC, 0, 0), + MX6_PAD_LCD_DATA16__I2C2_SCL = IOMUX_PAD(0x0420, 0x0158, IOMUX_CONFIG_SION | 4, 0x0684, 1, 0), + MX6_PAD_LCD_DATA16__GPIO3_IO04 = IOMUX_PAD(0x0420, 0x0158, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__SRC_BOOT_CFG24 = IOMUX_PAD(0x0420, 0x0158, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA17__LCD_DATA17 = IOMUX_PAD(0x0424, 0x015C, 0, 0x071C, 0, 0), + MX6_PAD_LCD_DATA17__KEY_ROW4 = IOMUX_PAD(0x0424, 0x015C, 1, 0x06D0, 0, 0), + MX6_PAD_LCD_DATA17__CSI_DATA00 = IOMUX_PAD(0x0424, 0x015C, 2, 0x05C8, 0, 0), + MX6_PAD_LCD_DATA17__I2C2_SDA = IOMUX_PAD(0x0424, 0x015C, IOMUX_CONFIG_SION | 4, 0x0688, 1, 0), + MX6_PAD_LCD_DATA17__GPIO3_IO05 = IOMUX_PAD(0x0424, 0x015C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__SRC_BOOT_CFG25 = IOMUX_PAD(0x0424, 0x015C, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA18__LCD_DATA18 = IOMUX_PAD(0x0428, 0x0160, 0, 0x0720, 0, 0), + MX6_PAD_LCD_DATA18__KEY_COL5 = IOMUX_PAD(0x0428, 0x0160, 1, 0x0694, 2, 0), + MX6_PAD_LCD_DATA18__CSI_DATA15 = IOMUX_PAD(0x0428, 0x0160, 2, 0x05C4, 1, 0), + MX6_PAD_LCD_DATA18__GPT_CAPTURE1 = IOMUX_PAD(0x0428, 0x0160, 4, 0x0670, 1, 0), + MX6_PAD_LCD_DATA18__GPIO3_IO06 = IOMUX_PAD(0x0428, 0x0160, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__SRC_BOOT_CFG26 = IOMUX_PAD(0x0428, 0x0160, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA19__LCD_DATA19 = IOMUX_PAD(0x042C, 0x0164, 0, 0x0724, 0, 0), + MX6_PAD_LCD_DATA19__KEY_ROW5 = IOMUX_PAD(0x042C, 0x0164, 1, 0x06B4, 1, 0), + MX6_PAD_LCD_DATA19__CSI_DATA14 = IOMUX_PAD(0x042C, 0x0164, 2, 0x05C0, 2, 0), + MX6_PAD_LCD_DATA19__GPT_CAPTURE2 = IOMUX_PAD(0x042C, 0x0164, 4, 0x0674, 1, 0), + MX6_PAD_LCD_DATA19__GPIO3_IO07 = IOMUX_PAD(0x042C, 0x0164, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__SRC_BOOT_CFG27 = IOMUX_PAD(0x042C, 0x0164, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA20__LCD_DATA20 = IOMUX_PAD(0x0430, 0x0168, 0, 0x0728, 0, 0), + MX6_PAD_LCD_DATA20__KEY_COL6 = IOMUX_PAD(0x0430, 0x0168, 1, 0x0698, 1, 0), + MX6_PAD_LCD_DATA20__CSI_DATA13 = IOMUX_PAD(0x0430, 0x0168, 2, 0x05BC, 2, 0), + MX6_PAD_LCD_DATA20__GPT_COMPARE1 = IOMUX_PAD(0x0430, 0x0168, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__GPIO3_IO08 = IOMUX_PAD(0x0430, 0x0168, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__SRC_BOOT_CFG28 = IOMUX_PAD(0x0430, 0x0168, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA21__LCD_DATA21 = IOMUX_PAD(0x0434, 0x016C, 0, 0x072C, 0, 0), + MX6_PAD_LCD_DATA21__KEY_ROW6 = IOMUX_PAD(0x0434, 0x016C, 1, 0x06B8, 1, 0), + MX6_PAD_LCD_DATA21__CSI_DATA12 = IOMUX_PAD(0x0434, 0x016C, 2, 0x05B8, 2, 0), + MX6_PAD_LCD_DATA21__GPT_COMPARE2 = IOMUX_PAD(0x0434, 0x016C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__GPIO3_IO09 = IOMUX_PAD(0x0434, 0x016C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__SRC_BOOT_CFG29 = IOMUX_PAD(0x0434, 0x016C, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA22__LCD_DATA22 = IOMUX_PAD(0x0438, 0x0170, 0, 0x0730, 0, 0), + MX6_PAD_LCD_DATA22__KEY_COL7 = IOMUX_PAD(0x0438, 0x0170, 1, 0x069C, 1, 0), + MX6_PAD_LCD_DATA22__CSI_DATA11 = IOMUX_PAD(0x0438, 0x0170, 2, 0x05B4, 1, 0), + MX6_PAD_LCD_DATA22__GPT_COMPARE3 = IOMUX_PAD(0x0438, 0x0170, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__GPIO3_IO10 = IOMUX_PAD(0x0438, 0x0170, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__SRC_BOOT_CFG30 = IOMUX_PAD(0x0438, 0x0170, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA23__LCD_DATA23 = IOMUX_PAD(0x043C, 0x0174, 0, 0x0734, 0, 0), + MX6_PAD_LCD_DATA23__KEY_ROW7 = IOMUX_PAD(0x043C, 0x0174, 1, 0x06BC, 1, 0), + MX6_PAD_LCD_DATA23__CSI_DATA10 = IOMUX_PAD(0x043C, 0x0174, 2, 0x05B0, 1, 0), + MX6_PAD_LCD_DATA23__GPT_CLKIN = IOMUX_PAD(0x043C, 0x0174, 4, 0x0678, 1, 0), + MX6_PAD_LCD_DATA23__GPIO3_IO11 = IOMUX_PAD(0x043C, 0x0174, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__SRC_BOOT_CFG31 = IOMUX_PAD(0x043C, 0x0174, 7, 0x0000, 0, 0), + + MX6_PAD_AUD_RXFS__AUD3_RXFS = IOMUX_PAD(0x0440, 0x0178, 0, 0x0000, 0, 0), + MX6_PAD_AUD_RXFS__I2C1_SCL = IOMUX_PAD(0x0440, 0x0178, IOMUX_CONFIG_SION | 1, 0x067C, 1, 0), + MX6_PAD_AUD_RXFS__UART3_DCE_RX = IOMUX_PAD(0x0440, 0x0178, 2, 0x0754, 0, 0), + MX6_PAD_AUD_RXFS__UART3_DTE_TX = IOMUX_PAD(0x0440, 0x0178, 2, 0x0000, 0, 0), + MX6_PAD_AUD_RXFS__I2C3_SCL = IOMUX_PAD(0x0440, 0x0178, IOMUX_CONFIG_SION | 4, 0x068C, 1, 0), + MX6_PAD_AUD_RXFS__GPIO1_IO00 = IOMUX_PAD(0x0440, 0x0178, 5, 0x0000, 0, 0), + MX6_PAD_AUD_RXFS__ECSPI3_SS0 = IOMUX_PAD(0x0440, 0x0178, 6, 0x0648, 0, 0), + MX6_PAD_AUD_RXFS__MBIST_BEND = IOMUX_PAD(0x0440, 0x0178, 7, 0x0000, 0, 0), + + MX6_PAD_AUD_RXC__AUD3_RXC = IOMUX_PAD(0x0444, 0x017C, 0, 0x0000, 0, 0), + MX6_PAD_AUD_RXC__I2C1_SDA = IOMUX_PAD(0x0444, 0x017C, IOMUX_CONFIG_SION | 1, 0x0680, 1, 0), + MX6_PAD_AUD_RXC__UART3_DCE_TX = IOMUX_PAD(0x0444, 0x017C, 2, 0x0000, 0, 0), + MX6_PAD_AUD_RXC__UART3_DTE_RX = IOMUX_PAD(0x0444, 0x017C, 2, 0x0754, 1, 0), + MX6_PAD_AUD_RXC__I2C3_SDA = IOMUX_PAD(0x0444, 0x017C, IOMUX_CONFIG_SION | 4, 0x0690, 1, 0), + MX6_PAD_AUD_RXC__GPIO1_IO01 = IOMUX_PAD(0x0444, 0x017C, 5, 0x0000, 0, 0), + MX6_PAD_AUD_RXC__ECSPI3_SS1 = IOMUX_PAD(0x0444, 0x017C, 6, 0x064C, 0, 0), + + MX6_PAD_AUD_RXD__AUD3_RXD = IOMUX_PAD(0x0448, 0x0180, 0, 0x0000, 0, 0), + MX6_PAD_AUD_RXD__ECSPI3_MOSI = IOMUX_PAD(0x0448, 0x0180, 1, 0x063C, 0, 0), + MX6_PAD_AUD_RXD__UART4_DCE_RX = IOMUX_PAD(0x0448, 0x0180, 2, 0x075C, 0, 0), + MX6_PAD_AUD_RXD__UART4_DTE_TX = IOMUX_PAD(0x0448, 0x0180, 2, 0x0000, 0, 0), + MX6_PAD_AUD_RXD__SD1_LCTL = IOMUX_PAD(0x0448, 0x0180, 4, 0x0000, 0, 0), + MX6_PAD_AUD_RXD__GPIO1_IO02 = IOMUX_PAD(0x0448, 0x0180, 5, 0x0000, 0, 0), + + MX6_PAD_AUD_TXC__AUD3_TXC = IOMUX_PAD(0x044C, 0x0184, 0, 0x0000, 0, 0), + MX6_PAD_AUD_TXC__ECSPI3_MISO = IOMUX_PAD(0x044C, 0x0184, 1, 0x0638, 0, 0), + MX6_PAD_AUD_TXC__UART4_DCE_TX = IOMUX_PAD(0x044C, 0x0184, 2, 0x0000, 0, 0), + MX6_PAD_AUD_TXC__UART4_DTE_RX = IOMUX_PAD(0x044C, 0x0184, 2, 0x075C, 1, 0), + MX6_PAD_AUD_TXC__SD2_LCTL = IOMUX_PAD(0x044C, 0x0184, 4, 0x0000, 0, 0), + MX6_PAD_AUD_TXC__GPIO1_IO03 = IOMUX_PAD(0x044C, 0x0184, 5, 0x0000, 0, 0), + + MX6_PAD_AUD_TXFS__AUD3_TXFS = IOMUX_PAD(0x0450, 0x0188, 0, 0x0000, 0, 0), + MX6_PAD_AUD_TXFS__PWM3_OUT = IOMUX_PAD(0x0450, 0x0188, 1, 0x0000, 0, 0), + MX6_PAD_AUD_TXFS__UART4_DCE_RTS = IOMUX_PAD(0x0450, 0x0188, 2, 0x0758, 0, 0), + MX6_PAD_AUD_TXFS__UART4_DTE_CTS = IOMUX_PAD(0x0450, 0x0188, 2, 0x0000, 0, 0), + MX6_PAD_AUD_TXFS__SD3_LCTL = IOMUX_PAD(0x0450, 0x0188, 4, 0x0000, 0, 0), + MX6_PAD_AUD_TXFS__GPIO1_IO04 = IOMUX_PAD(0x0450, 0x0188, 5, 0x0000, 0, 0), + + MX6_PAD_AUD_TXD__AUD3_TXD = IOMUX_PAD(0x0454, 0x018C, 0, 0x0000, 0, 0), + MX6_PAD_AUD_TXD__ECSPI3_SCLK = IOMUX_PAD(0x0454, 0x018C, 1, 0x0630, 0, 0), + MX6_PAD_AUD_TXD__UART4_DCE_CTS = IOMUX_PAD(0x0454, 0x018C, 2, 0x0000, 0, 0), + MX6_PAD_AUD_TXD__UART4_DTE_RTS = IOMUX_PAD(0x0454, 0x018C, 2, 0x0758, 1, 0), + MX6_PAD_AUD_TXD__GPIO1_IO05 = IOMUX_PAD(0x0454, 0x018C, 5, 0x0000, 0, 0), + + MX6_PAD_AUD_MCLK__AUDIO_CLK_OUT = IOMUX_PAD(0x0458, 0x0190, 0, 0x0000, 0, 0), + MX6_PAD_AUD_MCLK__PWM4_OUT = IOMUX_PAD(0x0458, 0x0190, 1, 0x0000, 0, 0), + MX6_PAD_AUD_MCLK__ECSPI3_RDY = IOMUX_PAD(0x0458, 0x0190, 2, 0x0634, 0, 0), + MX6_PAD_AUD_MCLK__WDOG2_RESET_B_DEB = IOMUX_PAD(0x0458, 0x0190, 4, 0x0000, 0, 0), + MX6_PAD_AUD_MCLK__GPIO1_IO06 = IOMUX_PAD(0x0458, 0x0190, 5, 0x0000, 0, 0), + MX6_PAD_AUD_MCLK__SPDIF_EXT_CLK = IOMUX_PAD(0x0458, 0x0190, 6, 0x073C, 1, 0), + + MX6_PAD_UART1_RXD__UART1_DCE_RX = IOMUX_PAD(0x045C, 0x0194, 0, 0x0744, 0, 0), + + MX6_PAD_UART1_RXD__UART1_DTE_TX = IOMUX_PAD(0x045C, 0x0194, 0, 0x0000, 0, 0), + MX6_PAD_UART1_RXD__PWM1_OUT = IOMUX_PAD(0x045C, 0x0194, 1, 0x0000, 0, 0), + MX6_PAD_UART1_RXD__UART4_DCE_RX = IOMUX_PAD(0x045C, 0x0194, 2, 0x075C, 4, 0), + MX6_PAD_UART1_RXD__UART4_DTE_TX = IOMUX_PAD(0x045C, 0x0194, 2, 0x0000, 0, 0), + MX6_PAD_UART1_RXD__UART5_DCE_RX = IOMUX_PAD(0x045C, 0x0194, 4, 0x0764, 6, 0), + MX6_PAD_UART1_RXD__UART5_DTE_TX = IOMUX_PAD(0x045C, 0x0194, 4, 0x0000, 0, 0), + MX6_PAD_UART1_RXD__GPIO3_IO16 = IOMUX_PAD(0x045C, 0x0194, 5, 0x0000, 0, 0), + + MX6_PAD_UART1_TXD__UART1_DCE_TX = IOMUX_PAD(0x0460, 0x0198, 0, 0x0000, 0, 0), + + MX6_PAD_UART1_TXD__UART1_DTE_RX = IOMUX_PAD(0x0460, 0x0198, 0, 0x0744, 1, 0), + MX6_PAD_UART1_TXD__PWM2_OUT = IOMUX_PAD(0x0460, 0x0198, 1, 0x0000, 0, 0), + MX6_PAD_UART1_TXD__UART4_DCE_TX = IOMUX_PAD(0x0460, 0x0198, 2, 0x0000, 0, 0), + MX6_PAD_UART1_TXD__UART4_DTE_RX = IOMUX_PAD(0x0460, 0x0198, 2, 0x075C, 5, 0), + MX6_PAD_UART1_TXD__UART5_DCE_TX = IOMUX_PAD(0x0460, 0x0198, 4, 0x0000, 0, 0), + MX6_PAD_UART1_TXD__UART5_DTE_RX = IOMUX_PAD(0x0460, 0x0198, 4, 0x0764, 7, 0), + MX6_PAD_UART1_TXD__GPIO3_IO17 = IOMUX_PAD(0x0460, 0x0198, 5, 0x0000, 0, 0), + MX6_PAD_UART1_TXD__UART5_DCD_B = IOMUX_PAD(0x0460, 0x0198, 7, 0x0000, 0, 0), + + MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x0464, 0x019C, IOMUX_CONFIG_SION | 0, 0x067C, 0, 0), + MX6_PAD_I2C1_SCL__UART1_DCE_RTS = IOMUX_PAD(0x0464, 0x019C, 1, 0x0740, 0, 0), + MX6_PAD_I2C1_SCL__UART1_DTE_CTS = IOMUX_PAD(0x0464, 0x019C, 1, 0x0000, 0, 0), + MX6_PAD_I2C1_SCL__ECSPI3_SS2 = IOMUX_PAD(0x0464, 0x019C, 2, 0x0640, 0, 0), + MX6_PAD_I2C1_SCL__SD3_RESET = IOMUX_PAD(0x0464, 0x019C, 4, 0x0000, 0, 0), + MX6_PAD_I2C1_SCL__GPIO3_IO12 = IOMUX_PAD(0x0464, 0x019C, 5, 0x0000, 0, 0), + MX6_PAD_I2C1_SCL__ECSPI1_SS1 = IOMUX_PAD(0x0464, 0x019C, 6, 0x060C, 0, 0), + + MX6_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0468, 0x01A0, IOMUX_CONFIG_SION | 0, 0x0680, 0, 0), + MX6_PAD_I2C1_SDA__UART1_DCE_CTS = IOMUX_PAD(0x0468, 0x01A0, 1, 0x0000, 0, 0), + MX6_PAD_I2C1_SDA__UART1_DTE_RTS = IOMUX_PAD(0x0468, 0x01A0, 1, 0x0740, 1, 0), + MX6_PAD_I2C1_SDA__ECSPI3_SS3 = IOMUX_PAD(0x0468, 0x01A0, 2, 0x0644, 0, 0), + MX6_PAD_I2C1_SDA__SD3_VSELECT = IOMUX_PAD(0x0468, 0x01A0, 4, 0x0000, 0, 0), + MX6_PAD_I2C1_SDA__GPIO3_IO13 = IOMUX_PAD(0x0468, 0x01A0, 5, 0x0000, 0, 0), + MX6_PAD_I2C1_SDA__ECSPI1_SS2 = IOMUX_PAD(0x0468, 0x01A0, 6, 0x0610, 0, 0), + + MX6_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x046C, 0x01A4, IOMUX_CONFIG_SION | 0, 0x0684, 3, 0), + MX6_PAD_I2C2_SCL__AUD4_RXFS = IOMUX_PAD(0x046C, 0x01A4, 1, 0x0570, 2, 0), + MX6_PAD_I2C2_SCL__SPDIF_IN = IOMUX_PAD(0x046C, 0x01A4, 2, 0x0738, 2, 0), + MX6_PAD_I2C2_SCL__SD3_WP = IOMUX_PAD(0x046C, 0x01A4, 4, 0x0794, 3, 0), + MX6_PAD_I2C2_SCL__GPIO3_IO14 = IOMUX_PAD(0x046C, 0x01A4, 5, 0x0000, 0, 0), + MX6_PAD_I2C2_SCL__ECSPI1_RDY = IOMUX_PAD(0x046C, 0x01A4, 6, 0x0600, 1, 0), + + MX6_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0470, 0x01A8, IOMUX_CONFIG_SION | 0, 0x0688, 3, 0), + MX6_PAD_I2C2_SDA__AUD4_RXC = IOMUX_PAD(0x0470, 0x01A8, 1, 0x056C, 2, 0), + MX6_PAD_I2C2_SDA__SPDIF_OUT = IOMUX_PAD(0x0470, 0x01A8, 2, 0x0000, 0, 0), + MX6_PAD_I2C2_SDA__SD3_CD_B = IOMUX_PAD(0x0470, 0x01A8, 4, 0x0780, 3, 0), + MX6_PAD_I2C2_SDA__GPIO3_IO15 = IOMUX_PAD(0x0470, 0x01A8, 5, 0x0000, 0, 0), + + MX6_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x0474, 0x01AC, 0, 0x05FC, 1, 0), + MX6_PAD_ECSPI1_SCLK__AUD4_TXD = IOMUX_PAD(0x0474, 0x01AC, 1, 0x0568, 1, 0), + MX6_PAD_ECSPI1_SCLK__UART5_DCE_RX = IOMUX_PAD(0x0474, 0x01AC, 2, 0x0764, 2, 0), + MX6_PAD_ECSPI1_SCLK__UART5_DTE_TX = IOMUX_PAD(0x0474, 0x01AC, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SCLK__EPDC_VCOM0 = IOMUX_PAD(0x0474, 0x01AC, 3, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SCLK__SD2_RESET = IOMUX_PAD(0x0474, 0x01AC, 4, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SCLK__GPIO4_IO08 = IOMUX_PAD(0x0474, 0x01AC, 5, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SCLK__USB_OTG2_OC = IOMUX_PAD(0x0474, 0x01AC, 6, 0x0768, 1, 0), + + MX6_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0478, 0x01B0, 0, 0x0608, 1, 0), + MX6_PAD_ECSPI1_MOSI__AUD4_TXC = IOMUX_PAD(0x0478, 0x01B0, 1, 0x0574, 1, 0), + MX6_PAD_ECSPI1_MOSI__UART5_DCE_TX = IOMUX_PAD(0x0478, 0x01B0, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MOSI__UART5_DTE_RX = IOMUX_PAD(0x0478, 0x01B0, 2, 0x0764, 3, 0), + MX6_PAD_ECSPI1_MOSI__EPDC_VCOM1 = IOMUX_PAD(0x0478, 0x01B0, 3, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MOSI__SD2_VSELECT = IOMUX_PAD(0x0478, 0x01B0, 4, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MOSI__GPIO4_IO09 = IOMUX_PAD(0x0478, 0x01B0, 5, 0x0000, 0, 0), + + MX6_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x047C, 0x01B4, 0, 0x0604, 1, 0), + MX6_PAD_ECSPI1_MISO__AUD4_TXFS = IOMUX_PAD(0x047C, 0x01B4, 1, 0x0578, 1, 0), + MX6_PAD_ECSPI1_MISO__UART5_DCE_RTS = IOMUX_PAD(0x047C, 0x01B4, 2, 0x0760, 2, 0), + MX6_PAD_ECSPI1_MISO__UART5_DTE_CTS = IOMUX_PAD(0x047C, 0x01B4, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MISO__EPDC_BDR0 = IOMUX_PAD(0x047C, 0x01B4, 3, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MISO__SD2_WP = IOMUX_PAD(0x047C, 0x01B4, 4, 0x077C, 0, 0), + MX6_PAD_ECSPI1_MISO__GPIO4_IO10 = IOMUX_PAD(0x047C, 0x01B4, 5, 0x0000, 0, 0), + + MX6_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x0480, 0x01B8, 0, 0x0614, 1, 0), + MX6_PAD_ECSPI1_SS0__AUD4_RXD = IOMUX_PAD(0x0480, 0x01B8, 1, 0x0564, 1, 0), + MX6_PAD_ECSPI1_SS0__UART5_DCE_CTS = IOMUX_PAD(0x0480, 0x01B8, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SS0__UART5_DTE_RTS = IOMUX_PAD(0x0480, 0x01B8, 2, 0x0760, 3, 0), + MX6_PAD_ECSPI1_SS0__EPDC_BDR1 = IOMUX_PAD(0x0480, 0x01B8, 3, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SS0__SD2_CD_B = IOMUX_PAD(0x0480, 0x01B8, 4, 0x0778, 0, 0), + MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0480, 0x01B8, 5, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SS0__USB_OTG2_PWR = IOMUX_PAD(0x0480, 0x01B8, 6, 0x0000, 0, 0), + + MX6_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x0484, 0x01BC, 0, 0x061C, 1, 0), + MX6_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK = IOMUX_PAD(0x0484, 0x01BC, 1, 0x073C, 2, 0), + MX6_PAD_ECSPI2_SCLK__UART3_DCE_RX = IOMUX_PAD(0x0484, 0x01BC, 2, 0x0754, 2, 0), + MX6_PAD_ECSPI2_SCLK__UART3_DTE_TX = IOMUX_PAD(0x0484, 0x01BC, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI2_SCLK__CSI_PIXCLK = IOMUX_PAD(0x0484, 0x01BC, 3, 0x05F4, 1, 0), + MX6_PAD_ECSPI2_SCLK__SD1_RESET = IOMUX_PAD(0x0484, 0x01BC, 4, 0x0000, 0, 0), + MX6_PAD_ECSPI2_SCLK__GPIO4_IO12 = IOMUX_PAD(0x0484, 0x01BC, 5, 0x0000, 0, 0), + MX6_PAD_ECSPI2_SCLK__USB_OTG2_OC = IOMUX_PAD(0x0484, 0x01BC, 6, 0x0768, 2, 0), + + MX6_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0488, 0x01C0, 0, 0x0624, 1, 0), + MX6_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0488, 0x01C0, 1, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MOSI__UART3_DCE_TX = IOMUX_PAD(0x0488, 0x01C0, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MOSI__UART3_DTE_RX = IOMUX_PAD(0x0488, 0x01C0, 2, 0x0754, 3, 0), + MX6_PAD_ECSPI2_MOSI__CSI_HSYNC = IOMUX_PAD(0x0488, 0x01C0, 3, 0x05F0, 1, 0), + MX6_PAD_ECSPI2_MOSI__SD1_VSELECT = IOMUX_PAD(0x0488, 0x01C0, 4, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MOSI__GPIO4_IO13 = IOMUX_PAD(0x0488, 0x01C0, 5, 0x0000, 0, 0), + + MX6_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x048C, 0x01C4, 0, 0x0620, 1, 0), + MX6_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 = IOMUX_PAD(0x048C, 0x01C4, 1, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MISO__UART3_DCE_RTS = IOMUX_PAD(0x048C, 0x01C4, 2, 0x0750, 0, 0), + MX6_PAD_ECSPI2_MISO__UART3_DTE_CTS = IOMUX_PAD(0x048C, 0x01C4, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MISO__CSI_MCLK = IOMUX_PAD(0x048C, 0x01C4, 3, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MISO__SD1_WP = IOMUX_PAD(0x048C, 0x01C4, 4, 0x0774, 2, 0), + MX6_PAD_ECSPI2_MISO__GPIO4_IO14 = IOMUX_PAD(0x048C, 0x01C4, 5, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MISO__USB_OTG1_OC = IOMUX_PAD(0x048C, 0x01C4, 6, 0x076C, 1, 0), + + MX6_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x0490, 0x01C8, 0, 0x0628, 0, 0), + MX6_PAD_ECSPI2_SS0__ECSPI1_SS3 = IOMUX_PAD(0x0490, 0x01C8, 1, 0x0618, 1, 0), + MX6_PAD_ECSPI2_SS0__UART3_DCE_CTS = IOMUX_PAD(0x0490, 0x01C8, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI2_SS0__UART3_DTE_RTS = IOMUX_PAD(0x0490, 0x01C8, 2, 0x0750, 1, 0), + MX6_PAD_ECSPI2_SS0__CSI_VSYNC = IOMUX_PAD(0x0490, 0x01C8, 3, 0x05F8, 1, 0), + MX6_PAD_ECSPI2_SS0__SD1_CD_B = IOMUX_PAD(0x0490, 0x01C8, 4, 0x0770, 2, 0), + MX6_PAD_ECSPI2_SS0__GPIO4_IO15 = IOMUX_PAD(0x0490, 0x01C8, 5, 0x0000, 0, 0), + MX6_PAD_ECSPI2_SS0__USB_OTG1_PWR = IOMUX_PAD(0x0490, 0x01C8, 6, 0x0000, 0, 0), + + MX6_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x0494, 0x01CC, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__KEY_COL0 = IOMUX_PAD(0x0494, 0x01CC, 2, 0x06A0, 2, 0), + MX6_PAD_SD1_CLK__EPDC_SDCE4 = IOMUX_PAD(0x0494, 0x01CC, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPIO5_IO15 = IOMUX_PAD(0x0494, 0x01CC, 5, 0x0000, 0, 0), + + MX6_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x0498, 0x01D0, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__KEY_ROW0 = IOMUX_PAD(0x0498, 0x01D0, 2, 0x06C0, 2, 0), + MX6_PAD_SD1_CMD__EPDC_SDCE5 = IOMUX_PAD(0x0498, 0x01D0, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPIO5_IO14 = IOMUX_PAD(0x0498, 0x01D0, 5, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x049C, 0x01D4, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__KEY_COL1 = IOMUX_PAD(0x049C, 0x01D4, 2, 0x06A4, 2, 0), + MX6_PAD_SD1_DATA0__EPDC_SDCE6 = IOMUX_PAD(0x049C, 0x01D4, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__GPIO5_IO11 = IOMUX_PAD(0x049C, 0x01D4, 5, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x04A0, 0x01D8, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__KEY_ROW1 = IOMUX_PAD(0x04A0, 0x01D8, 2, 0x06C4, 2, 0), + MX6_PAD_SD1_DATA1__EPDC_SDCE7 = IOMUX_PAD(0x04A0, 0x01D8, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__GPIO5_IO08 = IOMUX_PAD(0x04A0, 0x01D8, 5, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x04A4, 0x01DC, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__KEY_COL2 = IOMUX_PAD(0x04A4, 0x01DC, 2, 0x06A8, 2, 0), + MX6_PAD_SD1_DATA2__EPDC_SDCE8 = IOMUX_PAD(0x04A4, 0x01DC, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__GPIO5_IO13 = IOMUX_PAD(0x04A4, 0x01DC, 5, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x04A8, 0x01E0, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__KEY_ROW2 = IOMUX_PAD(0x04A8, 0x01E0, 2, 0x06C8, 2, 0), + MX6_PAD_SD1_DATA3__EPDC_SDCE9 = IOMUX_PAD(0x04A8, 0x01E0, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__GPIO5_IO06 = IOMUX_PAD(0x04A8, 0x01E0, 5, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA4__SD1_DATA4 = IOMUX_PAD(0x04AC, 0x01E4, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA4__KEY_COL3 = IOMUX_PAD(0x04AC, 0x01E4, 2, 0x06AC, 2, 0), + MX6_PAD_SD1_DATA4__EPDC_SDCLK_N = IOMUX_PAD(0x04AC, 0x01E4, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA4__UART4_DCE_RX = IOMUX_PAD(0x04AC, 0x01E4, 4, 0x075C, 6, 0), + MX6_PAD_SD1_DATA4__UART4_DTE_TX = IOMUX_PAD(0x04AC, 0x01E4, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA4__GPIO5_IO12 = IOMUX_PAD(0x04AC, 0x01E4, 5, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA5__SD1_DATA5 = IOMUX_PAD(0x04B0, 0x01E8, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA5__KEY_ROW3 = IOMUX_PAD(0x04B0, 0x01E8, 2, 0x06CC, 2, 0), + MX6_PAD_SD1_DATA5__EPDC_SDOED = IOMUX_PAD(0x04B0, 0x01E8, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA5__UART4_DCE_TX = IOMUX_PAD(0x04B0, 0x01E8, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA5__UART4_DTE_RX = IOMUX_PAD(0x04B0, 0x01E8, 4, 0x075C, 7, 0), + MX6_PAD_SD1_DATA5__GPIO5_IO09 = IOMUX_PAD(0x04B0, 0x01E8, 5, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA6__SD1_DATA6 = IOMUX_PAD(0x04B4, 0x01EC, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA6__KEY_COL4 = IOMUX_PAD(0x04B4, 0x01EC, 2, 0x06B0, 2, 0), + MX6_PAD_SD1_DATA6__EPDC_SDOEZ = IOMUX_PAD(0x04B4, 0x01EC, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA6__UART4_DCE_RTS = IOMUX_PAD(0x04B4, 0x01EC, 4, 0x0758, 4, 0), + MX6_PAD_SD1_DATA6__UART4_DTE_CTS = IOMUX_PAD(0x04B4, 0x01EC, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA6__GPIO5_IO07 = IOMUX_PAD(0x04B4, 0x01EC, 5, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA7__SD1_DATA7 = IOMUX_PAD(0x04B8, 0x01F0, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA7__KEY_ROW4 = IOMUX_PAD(0x04B8, 0x01F0, 2, 0x06D0, 2, 0), + MX6_PAD_SD1_DATA7__CCM_PMIC_READY = IOMUX_PAD(0x04B8, 0x01F0, 3, 0x05AC, 3, 0), + MX6_PAD_SD1_DATA7__UART4_DCE_CTS = IOMUX_PAD(0x04B8, 0x01F0, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA7__UART4_DTE_RTS = IOMUX_PAD(0x04B8, 0x01F0, 4, 0x0758, 5, 0), + MX6_PAD_SD1_DATA7__GPIO5_IO10 = IOMUX_PAD(0x04B8, 0x01F0, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_RESET__SD2_RESET = IOMUX_PAD(0x04BC, 0x01F4, 0, 0x0000, 0, 0), + MX6_PAD_SD2_RESET__WDOG2_B = IOMUX_PAD(0x04BC, 0x01F4, 2, 0x0000, 0, 0), + MX6_PAD_SD2_RESET__SPDIF_OUT = IOMUX_PAD(0x04BC, 0x01F4, 3, 0x0000, 0, 0), + MX6_PAD_SD2_RESET__CSI_MCLK = IOMUX_PAD(0x04BC, 0x01F4, 4, 0x0000, 0, 0), + MX6_PAD_SD2_RESET__GPIO4_IO27 = IOMUX_PAD(0x04BC, 0x01F4, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x04C0, 0x01F8, 0, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__AUD4_RXFS = IOMUX_PAD(0x04C0, 0x01F8, 1, 0x0570, 1, 0), + MX6_PAD_SD2_CLK__ECSPI3_SCLK = IOMUX_PAD(0x04C0, 0x01F8, 2, 0x0630, 1, 0), + MX6_PAD_SD2_CLK__CSI_DATA00 = IOMUX_PAD(0x04C0, 0x01F8, 3, 0x05C8, 1, 0), + MX6_PAD_SD2_CLK__GPIO5_IO05 = IOMUX_PAD(0x04C0, 0x01F8, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x04C4, 0x01FC, 0, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__AUD4_RXC = IOMUX_PAD(0x04C4, 0x01FC, 1, 0x056C, 1, 0), + MX6_PAD_SD2_CMD__ECSPI3_SS0 = IOMUX_PAD(0x04C4, 0x01FC, 2, 0x0648, 1, 0), + MX6_PAD_SD2_CMD__CSI_DATA01 = IOMUX_PAD(0x04C4, 0x01FC, 3, 0x05CC, 1, 0), + MX6_PAD_SD2_CMD__EPIT1_OUT = IOMUX_PAD(0x04C4, 0x01FC, 4, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__GPIO5_IO04 = IOMUX_PAD(0x04C4, 0x01FC, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x04C8, 0x0200, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA0__AUD4_RXD = IOMUX_PAD(0x04C8, 0x0200, 1, 0x0564, 2, 0), + MX6_PAD_SD2_DATA0__ECSPI3_MOSI = IOMUX_PAD(0x04C8, 0x0200, 2, 0x063C, 1, 0), + MX6_PAD_SD2_DATA0__CSI_DATA02 = IOMUX_PAD(0x04C8, 0x0200, 3, 0x05D0, 1, 0), + MX6_PAD_SD2_DATA0__UART5_DCE_RTS = IOMUX_PAD(0x04C8, 0x0200, 4, 0x0760, 4, 0), + MX6_PAD_SD2_DATA0__UART5_DTE_CTS = IOMUX_PAD(0x04C8, 0x0200, 4, 0x0000, 0, 0), + MX6_PAD_SD2_DATA0__GPIO5_IO01 = IOMUX_PAD(0x04C8, 0x0200, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x04CC, 0x0204, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA1__AUD4_TXC = IOMUX_PAD(0x04CC, 0x0204, 1, 0x0574, 2, 0), + MX6_PAD_SD2_DATA1__ECSPI3_MISO = IOMUX_PAD(0x04CC, 0x0204, 2, 0x0638, 1, 0), + MX6_PAD_SD2_DATA1__CSI_DATA03 = IOMUX_PAD(0x04CC, 0x0204, 3, 0x05D4, 1, 0), + MX6_PAD_SD2_DATA1__UART5_DCE_CTS = IOMUX_PAD(0x04CC, 0x0204, 4, 0x0000, 0, 0), + MX6_PAD_SD2_DATA1__UART5_DTE_RTS = IOMUX_PAD(0x04CC, 0x0204, 4, 0x0760, 5, 0), + MX6_PAD_SD2_DATA1__GPIO4_IO30 = IOMUX_PAD(0x04CC, 0x0204, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x04D0, 0x0208, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA2__AUD4_TXFS = IOMUX_PAD(0x04D0, 0x0208, 1, 0x0578, 2, 0), + MX6_PAD_SD2_DATA2__CSI_DATA04 = IOMUX_PAD(0x04D0, 0x0208, 3, 0x05D8, 1, 0), + MX6_PAD_SD2_DATA2__UART5_DCE_RX = IOMUX_PAD(0x04D0, 0x0208, 4, 0x0764, 4, 0), + MX6_PAD_SD2_DATA2__UART5_DTE_TX = IOMUX_PAD(0x04D0, 0x0208, 4, 0x0000, 0, 0), + MX6_PAD_SD2_DATA2__GPIO5_IO03 = IOMUX_PAD(0x04D0, 0x0208, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x04D4, 0x020C, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA3__AUD4_TXD = IOMUX_PAD(0x04D4, 0x020C, 1, 0x0568, 2, 0), + MX6_PAD_SD2_DATA3__CSI_DATA05 = IOMUX_PAD(0x04D4, 0x020C, 3, 0x05DC, 1, 0), + MX6_PAD_SD2_DATA3__UART5_DCE_TX = IOMUX_PAD(0x04D4, 0x020C, 4, 0x0000, 0, 0), + MX6_PAD_SD2_DATA3__UART5_DTE_RX = IOMUX_PAD(0x04D4, 0x020C, 4, 0x0764, 5, 0), + MX6_PAD_SD2_DATA3__GPIO4_IO28 = IOMUX_PAD(0x04D4, 0x020C, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA4__SD2_DATA4 = IOMUX_PAD(0x04D8, 0x0210, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA4__SD3_DATA4 = IOMUX_PAD(0x04D8, 0x0210, 1, 0x0784, 1, 0), + MX6_PAD_SD2_DATA4__UART2_DCE_RX = IOMUX_PAD(0x04D8, 0x0210, 2, 0x074C, 2, 0), + MX6_PAD_SD2_DATA4__UART2_DTE_TX = IOMUX_PAD(0x04D8, 0x0210, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DATA4__CSI_DATA06 = IOMUX_PAD(0x04D8, 0x0210, 3, 0x05E0, 1, 0), + MX6_PAD_SD2_DATA4__SPDIF_OUT = IOMUX_PAD(0x04D8, 0x0210, 4, 0x0000, 0, 0), + MX6_PAD_SD2_DATA4__GPIO5_IO02 = IOMUX_PAD(0x04D8, 0x0210, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA5__SD2_DATA5 = IOMUX_PAD(0x04DC, 0x0214, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA5__SD3_DATA5 = IOMUX_PAD(0x04DC, 0x0214, 1, 0x0788, 1, 0), + MX6_PAD_SD2_DATA5__UART2_DCE_TX = IOMUX_PAD(0x04DC, 0x0214, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DATA5__UART2_DTE_RX = IOMUX_PAD(0x04DC, 0x0214, 2, 0x074C, 3, 0), + MX6_PAD_SD2_DATA5__CSI_DATA07 = IOMUX_PAD(0x04DC, 0x0214, 3, 0x05E4, 1, 0), + MX6_PAD_SD2_DATA5__SPDIF_IN = IOMUX_PAD(0x04DC, 0x0214, 4, 0x0738, 1, 0), + MX6_PAD_SD2_DATA5__GPIO4_IO31 = IOMUX_PAD(0x04DC, 0x0214, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA6__SD2_DATA6 = IOMUX_PAD(0x04E0, 0x0218, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA6__SD3_DATA6 = IOMUX_PAD(0x04E0, 0x0218, 1, 0x078C, 1, 0), + MX6_PAD_SD2_DATA6__UART2_DCE_RTS = IOMUX_PAD(0x04E0, 0x0218, 2, 0x0748, 2, 0), + MX6_PAD_SD2_DATA6__UART2_DTE_CTS = IOMUX_PAD(0x04E0, 0x0218, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DATA6__CSI_DATA08 = IOMUX_PAD(0x04E0, 0x0218, 3, 0x05E8, 1, 0), + MX6_PAD_SD2_DATA6__SD2_WP = IOMUX_PAD(0x04E0, 0x0218, 4, 0x077C, 1, 0), + MX6_PAD_SD2_DATA6__GPIO4_IO29 = IOMUX_PAD(0x04E0, 0x0218, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA7__SD2_DATA7 = IOMUX_PAD(0x04E4, 0x021C, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA7__SD3_DATA7 = IOMUX_PAD(0x04E4, 0x021C, 1, 0x0790, 1, 0), + MX6_PAD_SD2_DATA7__UART2_DCE_CTS = IOMUX_PAD(0x04E4, 0x021C, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DATA7__UART2_DTE_RTS = IOMUX_PAD(0x04E4, 0x021C, 2, 0x0748, 3, 0), + MX6_PAD_SD2_DATA7__CSI_DATA09 = IOMUX_PAD(0x04E4, 0x021C, 3, 0x05EC, 1, 0), + MX6_PAD_SD2_DATA7__SD2_CD_B = IOMUX_PAD(0x04E4, 0x021C, 4, 0x0778, 1, 0), + MX6_PAD_SD2_DATA7__GPIO5_IO00 = IOMUX_PAD(0x04E4, 0x021C, 5, 0x0000, 0, 0), + + MX6_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x04E8, 0x0220, 0, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__AUD5_RXFS = IOMUX_PAD(0x04E8, 0x0220, 1, 0x0588, 0, 0), + MX6_PAD_SD3_CLK__KEY_COL5 = IOMUX_PAD(0x04E8, 0x0220, 2, 0x0694, 0, 0), + MX6_PAD_SD3_CLK__CSI_DATA10 = IOMUX_PAD(0x04E8, 0x0220, 3, 0x05B0, 0, 0), + MX6_PAD_SD3_CLK__WDOG1_RESET_B_DEB = IOMUX_PAD(0x04E8, 0x0220, 4, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__GPIO5_IO18 = IOMUX_PAD(0x04E8, 0x0220, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__USB_OTG1_PWR = IOMUX_PAD(0x04E8, 0x0220, 6, 0x0000, 0, 0), + + MX6_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x04EC, 0x0224, 0, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__AUD5_RXC = IOMUX_PAD(0x04EC, 0x0224, 1, 0x0584, 0, 0), + MX6_PAD_SD3_CMD__KEY_ROW5 = IOMUX_PAD(0x04EC, 0x0224, 2, 0x06B4, 0, 0), + MX6_PAD_SD3_CMD__CSI_DATA11 = IOMUX_PAD(0x04EC, 0x0224, 3, 0x05B4, 0, 0), + MX6_PAD_SD3_CMD__USB_OTG2_ID = IOMUX_PAD(0x04EC, 0x0224, 4, 0x0560, 1, 0), + MX6_PAD_SD3_CMD__GPIO5_IO21 = IOMUX_PAD(0x04EC, 0x0224, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__USB_OTG2_PWR = IOMUX_PAD(0x04EC, 0x0224, 6, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA0__SD3_DATA0 = IOMUX_PAD(0x04F0, 0x0228, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA0__AUD5_RXD = IOMUX_PAD(0x04F0, 0x0228, 1, 0x057C, 0, 0), + MX6_PAD_SD3_DATA0__KEY_COL6 = IOMUX_PAD(0x04F0, 0x0228, 2, 0x0698, 0, 0), + MX6_PAD_SD3_DATA0__CSI_DATA12 = IOMUX_PAD(0x04F0, 0x0228, 3, 0x05B8, 0, 0), + MX6_PAD_SD3_DATA0__USB_OTG1_ID = IOMUX_PAD(0x04F0, 0x0228, 4, 0x055C, 1, 0), + MX6_PAD_SD3_DATA0__GPIO5_IO19 = IOMUX_PAD(0x04F0, 0x0228, 5, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA1__SD3_DATA1 = IOMUX_PAD(0x04F4, 0x022C, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__AUD5_TXC = IOMUX_PAD(0x04F4, 0x022C, 1, 0x058C, 0, 0), + MX6_PAD_SD3_DATA1__KEY_ROW6 = IOMUX_PAD(0x04F4, 0x022C, 2, 0x06B8, 0, 0), + MX6_PAD_SD3_DATA1__CSI_DATA13 = IOMUX_PAD(0x04F4, 0x022C, 3, 0x05BC, 0, 0), + MX6_PAD_SD3_DATA1__SD1_VSELECT = IOMUX_PAD(0x04F4, 0x022C, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__GPIO5_IO20 = IOMUX_PAD(0x04F4, 0x022C, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__JTAG_DE_B = IOMUX_PAD(0x04F4, 0x022C, 6, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA2__SD3_DATA2 = IOMUX_PAD(0x04F8, 0x0230, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA2__AUD5_TXFS = IOMUX_PAD(0x04F8, 0x0230, 1, 0x0590, 0, 0), + MX6_PAD_SD3_DATA2__KEY_COL7 = IOMUX_PAD(0x04F8, 0x0230, 2, 0x069C, 0, 0), + MX6_PAD_SD3_DATA2__CSI_DATA14 = IOMUX_PAD(0x04F8, 0x0230, 3, 0x05C0, 0, 0), + MX6_PAD_SD3_DATA2__EPIT1_OUT = IOMUX_PAD(0x04F8, 0x0230, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA2__GPIO5_IO16 = IOMUX_PAD(0x04F8, 0x0230, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA2__USB_OTG2_OC = IOMUX_PAD(0x04F8, 0x0230, 6, 0x0768, 0, 0), + + MX6_PAD_SD3_DATA3__SD3_DATA3 = IOMUX_PAD(0x04FC, 0x0234, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA3__AUD5_TXD = IOMUX_PAD(0x04FC, 0x0234, 1, 0x0580, 0, 0), + MX6_PAD_SD3_DATA3__KEY_ROW7 = IOMUX_PAD(0x04FC, 0x0234, 2, 0x06BC, 0, 0), + MX6_PAD_SD3_DATA3__CSI_DATA15 = IOMUX_PAD(0x04FC, 0x0234, 3, 0x05C4, 0, 0), + MX6_PAD_SD3_DATA3__EPIT2_OUT = IOMUX_PAD(0x04FC, 0x0234, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA3__GPIO5_IO17 = IOMUX_PAD(0x04FC, 0x0234, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA3__USB_OTG1_OC = IOMUX_PAD(0x04FC, 0x0234, 6, 0x076C, 0, 0), + + MX6_PAD_GPIO4_IO20__SD1_STROBE = IOMUX_PAD(0x0500, 0x0238, 0, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO20__AUD6_RXFS = IOMUX_PAD(0x0500, 0x0238, 2, 0x05A0, 0, 0), + MX6_PAD_GPIO4_IO20__ECSPI4_SS0 = IOMUX_PAD(0x0500, 0x0238, 3, 0x065C, 0, 0), + MX6_PAD_GPIO4_IO20__GPT_CAPTURE1 = IOMUX_PAD(0x0500, 0x0238, 4, 0x0670, 0, 0), + MX6_PAD_GPIO4_IO20__GPIO4_IO20 = IOMUX_PAD(0x0500, 0x0238, 5, 0x0000, 0, 0), + + MX6_PAD_GPIO4_IO21__SD2_STROBE = IOMUX_PAD(0x0504, 0x023C, 0, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO21__AUD6_RXC = IOMUX_PAD(0x0504, 0x023C, 2, 0x059C, 0, 0), + MX6_PAD_GPIO4_IO21__ECSPI4_SCLK = IOMUX_PAD(0x0504, 0x023C, 3, 0x0650, 0, 0), + MX6_PAD_GPIO4_IO21__GPT_CAPTURE2 = IOMUX_PAD(0x0504, 0x023C, 4, 0x0674, 0, 0), + MX6_PAD_GPIO4_IO21__GPIO4_IO21 = IOMUX_PAD(0x0504, 0x023C, 5, 0x0000, 0, 0), + + MX6_PAD_GPIO4_IO19__SD3_STROBE = IOMUX_PAD(0x0508, 0x0240, 0, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO19__AUD6_RXD = IOMUX_PAD(0x0508, 0x0240, 2, 0x0594, 0, 0), + MX6_PAD_GPIO4_IO19__ECSPI4_MOSI = IOMUX_PAD(0x0508, 0x0240, 3, 0x0658, 0, 0), + MX6_PAD_GPIO4_IO19__GPT_COMPARE1 = IOMUX_PAD(0x0508, 0x0240, 4, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO19__GPIO4_IO19 = IOMUX_PAD(0x0508, 0x0240, 5, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO25__AUD6_TXC = IOMUX_PAD(0x050C, 0x0244, 2, 0x05A4, 0, 0), + MX6_PAD_GPIO4_IO25__ECSPI4_MISO = IOMUX_PAD(0x050C, 0x0244, 3, 0x0654, 0, 0), + MX6_PAD_GPIO4_IO25__GPT_COMPARE2 = IOMUX_PAD(0x050C, 0x0244, 4, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO25__GPIO4_IO25 = IOMUX_PAD(0x050C, 0x0244, 5, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO18__AUD6_TXFS = IOMUX_PAD(0x0510, 0x0248, 2, 0x05A8, 0, 0), + MX6_PAD_GPIO4_IO18__ECSPI4_SS1 = IOMUX_PAD(0x0510, 0x0248, 3, 0x0660, 0, 0), + MX6_PAD_GPIO4_IO18__GPT_COMPARE3 = IOMUX_PAD(0x0510, 0x0248, 4, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO18__GPIO4_IO18 = IOMUX_PAD(0x0510, 0x0248, 5, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO24__AUD6_TXD = IOMUX_PAD(0x0514, 0x024C, 2, 0x0598, 0, 0), + MX6_PAD_GPIO4_IO24__ECSPI4_SS2 = IOMUX_PAD(0x0514, 0x024C, 3, 0x0664, 0, 0), + MX6_PAD_GPIO4_IO24__GPT_CLKIN = IOMUX_PAD(0x0514, 0x024C, 4, 0x0678, 0, 0), + MX6_PAD_GPIO4_IO24__GPIO4_IO24 = IOMUX_PAD(0x0514, 0x024C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO23__AUDIO_CLK_OUT = IOMUX_PAD(0x0518, 0x0250, 2, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO23__SD1_RESET = IOMUX_PAD(0x0518, 0x0250, 3, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO23__SD3_RESET = IOMUX_PAD(0x0518, 0x0250, 4, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO23__GPIO4_IO23 = IOMUX_PAD(0x0518, 0x0250, 5, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO17__USB_OTG1_ID = IOMUX_PAD(0x051C, 0x0254, 2, 0x055C, 2, 0), + MX6_PAD_GPIO4_IO17__SD1_VSELECT = IOMUX_PAD(0x051C, 0x0254, 3, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO17__SD3_VSELECT = IOMUX_PAD(0x051C, 0x0254, 4, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO17__GPIO4_IO17 = IOMUX_PAD(0x051C, 0x0254, 5, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO22__SPDIF_IN = IOMUX_PAD(0x0520, 0x0258, 2, 0x0738, 0, 0), + MX6_PAD_GPIO4_IO22__SD1_WP = IOMUX_PAD(0x0520, 0x0258, 3, 0x0774, 0, 0), + MX6_PAD_GPIO4_IO22__SD3_WP = IOMUX_PAD(0x0520, 0x0258, 4, 0x0794, 1, 0), + MX6_PAD_GPIO4_IO22__GPIO4_IO22 = IOMUX_PAD(0x0520, 0x0258, 5, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO16__SPDIF_OUT = IOMUX_PAD(0x0524, 0x025C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO16__SD1_CD_B = IOMUX_PAD(0x0524, 0x025C, 3, 0x0770, 0, 0), + MX6_PAD_GPIO4_IO16__SD3_CD_B = IOMUX_PAD(0x0524, 0x025C, 4, 0x0780, 1, 0), + MX6_PAD_GPIO4_IO16__GPIO4_IO16 = IOMUX_PAD(0x0524, 0x025C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO26__WDOG1_B = IOMUX_PAD(0x0528, 0x0260, 2, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO26__PWM4_OUT = IOMUX_PAD(0x0528, 0x0260, 3, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO26__CCM_PMIC_READY = IOMUX_PAD(0x0528, 0x0260, 4, 0x05AC, 1, 0), + MX6_PAD_GPIO4_IO26__GPIO4_IO26 = IOMUX_PAD(0x0528, 0x0260, 5, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO26__SPDIF_EXT_CLK = IOMUX_PAD(0x0528, 0x0260, 6, 0x073C, 0, 0), +}; +#endif /* __ASM_ARCH_IMX6SLL_PINS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h new file mode 100644 index 000000000..5ad93ede3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __ASM_ARCH_MX6SX_DDR_H__ +#define __ASM_ARCH_MX6SX_DDR_H__ + +#ifndef CONFIG_MX6SX +#error "wrong CPU" +#endif + +#define MX6_IOM_DRAM_DQM0 0x020e02ec +#define MX6_IOM_DRAM_DQM1 0x020e02f0 +#define MX6_IOM_DRAM_DQM2 0x020e02f4 +#define MX6_IOM_DRAM_DQM3 0x020e02f8 + +#define MX6_IOM_DRAM_RAS 0x020e02fc +#define MX6_IOM_DRAM_CAS 0x020e0300 +#define MX6_IOM_DRAM_SDODT0 0x020e0310 +#define MX6_IOM_DRAM_SDODT1 0x020e0314 +#define MX6_IOM_DRAM_SDBA2 0x020e0320 +#define MX6_IOM_DRAM_SDCKE0 0x020e0324 +#define MX6_IOM_DRAM_SDCKE1 0x020e0328 +#define MX6_IOM_DRAM_SDCLK_0 0x020e032c +#define MX6_IOM_DRAM_RESET 0x020e0340 + +#define MX6_IOM_DRAM_SDQS0 0x020e0330 +#define MX6_IOM_DRAM_SDQS1 0x020e0334 +#define MX6_IOM_DRAM_SDQS2 0x020e0338 +#define MX6_IOM_DRAM_SDQS3 0x020e033c + +#define MX6_IOM_GRP_ADDDS 0x020e05f4 +#define MX6_IOM_DDRMODE_CTL 0x020e05f8 +#define MX6_IOM_GRP_DDRPKE 0x020e05fc +#define MX6_IOM_GRP_DDRMODE 0x020e0608 +#define MX6_IOM_GRP_B0DS 0x020e060c +#define MX6_IOM_GRP_B1DS 0x020e0610 +#define MX6_IOM_GRP_CTLDS 0x020e0614 +#define MX6_IOM_GRP_DDR_TYPE 0x020e0618 +#define MX6_IOM_GRP_B2DS 0x020e061c +#define MX6_IOM_GRP_B3DS 0x020e0620 + +#endif /*__ASM_ARCH_MX6SX_DDR_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sx_pins.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sx_pins.h new file mode 100644 index 000000000..a18e08f65 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sx_pins.h @@ -0,0 +1,1674 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __ASM_ARCH_MX6_MX6_PINS_H__ +#define __ASM_ARCH_MX6_MX6_PINS_H__ + +#include + +enum { + MX6_PAD_GPIO1_IO00__I2C1_SCL = IOMUX_PAD(0x035C, 0x0014, IOMUX_CONFIG_SION | 0, 0x07A8, 1, 0), + MX6_PAD_GPIO1_IO00__USDHC1_VSELECT = IOMUX_PAD(0x035C, 0x0014, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__SPDIF_LOCK = IOMUX_PAD(0x035C, 0x0014, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__CCM_WAIT = IOMUX_PAD(0x035C, 0x0014, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__WDOG1_WDOG_ANY = IOMUX_PAD(0x035C, 0x0014, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__GPIO1_IO_0 = IOMUX_PAD(0x035C, 0x0014, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 = IOMUX_PAD(0x035C, 0x0014, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__PHY_DTB_1 = IOMUX_PAD(0x035C, 0x0014, 7, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO01__I2C1_SDA = IOMUX_PAD(0x0360, 0x0018, IOMUX_CONFIG_SION | 0, 0x07AC, 1, 0), + MX6_PAD_GPIO1_IO01__USDHC1_RESET_B = IOMUX_PAD(0x0360, 0x0018, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__SPDIF_SR_CLK = IOMUX_PAD(0x0360, 0x0018, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__CCM_STOP = IOMUX_PAD(0x0360, 0x0018, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__WDOG3_WDOG_B = IOMUX_PAD(0x0360, 0x0018, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__GPIO1_IO_1 = IOMUX_PAD(0x0360, 0x0018, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__SNVS_HP_WRAPPER_VIO_5_CTL = IOMUX_PAD(0x0360, 0x0018, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__PHY_DTB_0 = IOMUX_PAD(0x0360, 0x0018, 7, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO02__I2C2_SCL = IOMUX_PAD(0x0364, 0x001C, IOMUX_CONFIG_SION | 0, 0x07B0, 1, 0), + MX6_PAD_GPIO1_IO02__USDHC1_CD_B = IOMUX_PAD(0x0364, 0x001C, 1, 0x0864, 1, 0), + MX6_PAD_GPIO1_IO02__CSI2_MCLK = IOMUX_PAD(0x0364, 0x001C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__CCM_DI0_EXT_CLK = IOMUX_PAD(0x0364, 0x001C, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x0364, 0x001C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__GPIO1_IO_2 = IOMUX_PAD(0x0364, 0x001C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__CCM_REF_EN_B = IOMUX_PAD(0x0364, 0x001C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__PHY_TDI = IOMUX_PAD(0x0364, 0x001C, 7, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO03__I2C2_SDA = IOMUX_PAD(0x0368, 0x0020, IOMUX_CONFIG_SION | 0, 0x07B4, 1, 0), + MX6_PAD_GPIO1_IO03__USDHC1_WP = IOMUX_PAD(0x0368, 0x0020, 1, 0x0868, 1, 0), + MX6_PAD_GPIO1_IO03__ENET1_REF_CLK_25M = IOMUX_PAD(0x0368, 0x0020, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__CCM_DI1_EXT_CLK = IOMUX_PAD(0x0368, 0x0020, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__WDOG2_WDOG_B = IOMUX_PAD(0x0368, 0x0020, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__GPIO1_IO_3 = IOMUX_PAD(0x0368, 0x0020, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__CCM_PLL3_BYP = IOMUX_PAD(0x0368, 0x0020, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__PHY_TCK = IOMUX_PAD(0x0368, 0x0020, 7, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO04__UART1_TX = IOMUX_PAD(0x036C, 0x0024, 0, 0x0830, 0, 0), + MX6_PAD_GPIO1_IO04__USDHC2_RESET_B = IOMUX_PAD(0x036C, 0x0024, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__ENET1_MDC = IOMUX_PAD(0x036C, 0x0024, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__OSC32K_32K_OUT = IOMUX_PAD(0x036C, 0x0024, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__ENET2_REF_CLK2 = IOMUX_PAD(0x036C, 0x0024, 4, 0x076C, 0, 0), + MX6_PAD_GPIO1_IO04__GPIO1_IO_4 = IOMUX_PAD(0x036C, 0x0024, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__CCM_PLL2_BYP = IOMUX_PAD(0x036C, 0x0024, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__PHY_TMS = IOMUX_PAD(0x036C, 0x0024, 7, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO05__UART1_RX = IOMUX_PAD(0x0370, 0x0028, 0, 0x0830, 1, 0), + MX6_PAD_GPIO1_IO05__USDHC2_VSELECT = IOMUX_PAD(0x0370, 0x0028, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__ENET1_MDIO = IOMUX_PAD(0x0370, 0x0028, 2, 0x0764, 0, 0), + MX6_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x0370, 0x0028, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__ENET1_REF_CLK1 = IOMUX_PAD(0x0370, 0x0028, 4, 0x0760, 0, 0), + MX6_PAD_GPIO1_IO05__GPIO1_IO_5 = IOMUX_PAD(0x0370, 0x0028, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__SRC_TESTER_ACK = IOMUX_PAD(0x0370, 0x0028, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__PHY_TDO = IOMUX_PAD(0x0370, 0x0028, 7, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO06__UART2_TX = IOMUX_PAD(0x0374, 0x002C, 0, 0x0838, 0, 0), + MX6_PAD_GPIO1_IO06__USDHC2_CD_B = IOMUX_PAD(0x0374, 0x002C, 1, 0x086C, 1, 0), + MX6_PAD_GPIO1_IO06__ENET2_MDC = IOMUX_PAD(0x0374, 0x002C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__CSI1_MCLK = IOMUX_PAD(0x0374, 0x002C, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__UART1_RTS_B = IOMUX_PAD(0x0374, 0x002C, 4, 0x082C, 0, 0), + MX6_PAD_GPIO1_IO06__GPIO1_IO_6 = IOMUX_PAD(0x0374, 0x002C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__SRC_ANY_PU_RESET = IOMUX_PAD(0x0374, 0x002C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED = IOMUX_PAD(0x0374, 0x002C, 7, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO07__UART2_RX = IOMUX_PAD(0x0378, 0x0030, 0, 0x0838, 1, 0), + MX6_PAD_GPIO1_IO07__USDHC2_WP = IOMUX_PAD(0x0378, 0x0030, 1, 0x0870, 1, 0), + MX6_PAD_GPIO1_IO07__ENET2_MDIO = IOMUX_PAD(0x0378, 0x0030, 2, 0x0770, 0, 0), + MX6_PAD_GPIO1_IO07__AUDMUX_MCLK = IOMUX_PAD(0x0378, 0x0030, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__UART1_CTS_B = IOMUX_PAD(0x0378, 0x0030, 4, 0x082C, 1, 0), + MX6_PAD_GPIO1_IO07__GPIO1_IO_7 = IOMUX_PAD(0x0378, 0x0030, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__SRC_EARLY_RESET = IOMUX_PAD(0x0378, 0x0030, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__DCIC2_OUT = IOMUX_PAD(0x0378, 0x0030, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__VDEC_DEBUG_44 = IOMUX_PAD(0x0378, 0x0030, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO08__USB_OTG1_OC = IOMUX_PAD(0x037C, 0x0034, 0, 0x0860, 0, 0), + MX6_PAD_GPIO1_IO08__WDOG1_WDOG_B = IOMUX_PAD(0x037C, 0x0034, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x037C, 0x0034, 2, 0x081C, 0, 0), + MX6_PAD_GPIO1_IO08__CCM_PMIC_RDY = IOMUX_PAD(0x037C, 0x0034, 3, 0x069C, 1, 0), + MX6_PAD_GPIO1_IO08__UART2_RTS_B = IOMUX_PAD(0x037C, 0x0034, 4, 0x0834, 0, 0), + MX6_PAD_GPIO1_IO08__GPIO1_IO_8 = IOMUX_PAD(0x037C, 0x0034, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__SRC_SYSTEM_RESET = IOMUX_PAD(0x037C, 0x0034, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__DCIC1_OUT = IOMUX_PAD(0x037C, 0x0034, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__VDEC_DEBUG_43 = IOMUX_PAD(0x037C, 0x0034, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR = IOMUX_PAD(0x0380, 0x0038, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__WDOG2_WDOG_B = IOMUX_PAD(0x0380, 0x0038, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x0380, 0x0038, 2, 0x0820, 0, 0), + MX6_PAD_GPIO1_IO09__CCM_OUT0 = IOMUX_PAD(0x0380, 0x0038, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__UART2_CTS_B = IOMUX_PAD(0x0380, 0x0038, 4, 0x0834, 1, 0), + MX6_PAD_GPIO1_IO09__GPIO1_IO_9 = IOMUX_PAD(0x0380, 0x0038, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__SRC_INT_BOOT = IOMUX_PAD(0x0380, 0x0038, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 = IOMUX_PAD(0x0380, 0x0038, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__VDEC_DEBUG_42 = IOMUX_PAD(0x0380, 0x0038, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID = IOMUX_PAD(0x0384, 0x003C, 0, 0x0624, 0, 0), + MX6_PAD_GPIO1_IO10__SPDIF_EXT_CLK = IOMUX_PAD(0x0384, 0x003C, 1, 0x0828, 0, 0), + MX6_PAD_GPIO1_IO10__PWM1_OUT = IOMUX_PAD(0x0384, 0x003C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO10__CCM_OUT1 = IOMUX_PAD(0x0384, 0x003C, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO10__CSI1_FIELD = IOMUX_PAD(0x0384, 0x003C, 4, 0x070C, 1, 0), + MX6_PAD_GPIO1_IO10__GPIO1_IO_10 = IOMUX_PAD(0x0384, 0x003C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO10__CSU_CSU_INT_DEB = IOMUX_PAD(0x0384, 0x003C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO10__OBSERVE_MUX_OUT_3 = IOMUX_PAD(0x0384, 0x003C, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO10__VDEC_DEBUG_41 = IOMUX_PAD(0x0384, 0x003C, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO11__USB_OTG2_OC = IOMUX_PAD(0x0388, 0x0040, 0, 0x085C, 0, 0), + MX6_PAD_GPIO1_IO11__SPDIF_IN = IOMUX_PAD(0x0388, 0x0040, 1, 0x0824, 2, 0), + MX6_PAD_GPIO1_IO11__PWM2_OUT = IOMUX_PAD(0x0388, 0x0040, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO11__CCM_CLKO1 = IOMUX_PAD(0x0388, 0x0040, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO11__MLB_DATA = IOMUX_PAD(0x0388, 0x0040, 4, 0x07EC, 0, 0), + MX6_PAD_GPIO1_IO11__GPIO1_IO_11 = IOMUX_PAD(0x0388, 0x0040, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO11__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x0388, 0x0040, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO11__OBSERVE_MUX_OUT_2 = IOMUX_PAD(0x0388, 0x0040, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO11__VDEC_DEBUG_40 = IOMUX_PAD(0x0388, 0x0040, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO12__USB_OTG2_PWR = IOMUX_PAD(0x038C, 0x0044, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO12__SPDIF_OUT = IOMUX_PAD(0x038C, 0x0044, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO12__PWM3_OUT = IOMUX_PAD(0x038C, 0x0044, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO12__CCM_CLKO2 = IOMUX_PAD(0x038C, 0x0044, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO12__MLB_CLK = IOMUX_PAD(0x038C, 0x0044, 4, 0x07E8, 0, 0), + MX6_PAD_GPIO1_IO12__GPIO1_IO_12 = IOMUX_PAD(0x038C, 0x0044, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x038C, 0x0044, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO12__OBSERVE_MUX_OUT_1 = IOMUX_PAD(0x038C, 0x0044, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO12__VDEC_DEBUG_39 = IOMUX_PAD(0x038C, 0x0044, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO13__WDOG1_WDOG_ANY = IOMUX_PAD(0x0390, 0x0048, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO13__ANATOP_OTG2_ID = IOMUX_PAD(0x0390, 0x0048, 1, 0x0628, 0, 0), + MX6_PAD_GPIO1_IO13__PWM4_OUT = IOMUX_PAD(0x0390, 0x0048, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO13__CCM_OUT2 = IOMUX_PAD(0x0390, 0x0048, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO13__MLB_SIG = IOMUX_PAD(0x0390, 0x0048, 4, 0x07F0, 0, 0), + MX6_PAD_GPIO1_IO13__GPIO1_IO_13 = IOMUX_PAD(0x0390, 0x0048, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x0390, 0x0048, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO13__OBSERVE_MUX_OUT_0 = IOMUX_PAD(0x0390, 0x0048, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO13__VDEC_DEBUG_38 = IOMUX_PAD(0x0390, 0x0048, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA00__CSI1_DATA_2 = IOMUX_PAD(0x0394, 0x004C, 0, 0x06A8, 0, 0), + MX6_PAD_CSI_DATA00__ESAI_TX_CLK = IOMUX_PAD(0x0394, 0x004C, 1, 0x078C, 1, 0), + MX6_PAD_CSI_DATA00__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0394, 0x004C, 2, 0x0684, 1, 0), + MX6_PAD_CSI_DATA00__I2C1_SCL = IOMUX_PAD(0x0394, 0x004C, IOMUX_CONFIG_SION | 3, 0x07A8, 0, 0), + MX6_PAD_CSI_DATA00__UART6_RI_B = IOMUX_PAD(0x0394, 0x004C, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__GPIO1_IO_14 = IOMUX_PAD(0x0394, 0x004C, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__WEIM_DATA_23 = IOMUX_PAD(0x0394, 0x004C, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__SAI1_TX_BCLK = IOMUX_PAD(0x0394, 0x004C, 7, 0x0800, 0, 0), + MX6_PAD_CSI_DATA00__VADC_DATA_4 = IOMUX_PAD(0x0394, 0x004C, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__MMDC_DEBUG_37 = IOMUX_PAD(0x0394, 0x004C, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA01__CSI1_DATA_3 = IOMUX_PAD(0x0398, 0x0050, 0, 0x06AC, 0, 0), + MX6_PAD_CSI_DATA01__ESAI_TX_FS = IOMUX_PAD(0x0398, 0x0050, 1, 0x077C, 1, 0), + MX6_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x0398, 0x0050, 2, 0x0688, 1, 0), + MX6_PAD_CSI_DATA01__I2C1_SDA = IOMUX_PAD(0x0398, 0x0050, IOMUX_CONFIG_SION | 3, 0x07AC, 0, 0), + MX6_PAD_CSI_DATA01__UART6_DSR_B = IOMUX_PAD(0x0398, 0x0050, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__GPIO1_IO_15 = IOMUX_PAD(0x0398, 0x0050, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__WEIM_DATA_22 = IOMUX_PAD(0x0398, 0x0050, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__SAI1_TX_SYNC = IOMUX_PAD(0x0398, 0x0050, 7, 0x0804, 0, 0), + MX6_PAD_CSI_DATA01__VADC_DATA_5 = IOMUX_PAD(0x0398, 0x0050, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__MMDC_DEBUG_38 = IOMUX_PAD(0x0398, 0x0050, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA02__CSI1_DATA_4 = IOMUX_PAD(0x039C, 0x0054, 0, 0x06B0, 0, 0), + MX6_PAD_CSI_DATA02__ESAI_RX_CLK = IOMUX_PAD(0x039C, 0x0054, 1, 0x0788, 1, 0), + MX6_PAD_CSI_DATA02__AUDMUX_AUD6_RXC = IOMUX_PAD(0x039C, 0x0054, 2, 0x067C, 1, 0), + MX6_PAD_CSI_DATA02__KPP_COL_5 = IOMUX_PAD(0x039C, 0x0054, 3, 0x07C8, 0, 0), + MX6_PAD_CSI_DATA02__UART6_DTR_B = IOMUX_PAD(0x039C, 0x0054, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__GPIO1_IO_16 = IOMUX_PAD(0x039C, 0x0054, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__WEIM_DATA_21 = IOMUX_PAD(0x039C, 0x0054, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__SAI1_RX_BCLK = IOMUX_PAD(0x039C, 0x0054, 7, 0x07F4, 0, 0), + MX6_PAD_CSI_DATA02__VADC_DATA_6 = IOMUX_PAD(0x039C, 0x0054, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__MMDC_DEBUG_39 = IOMUX_PAD(0x039C, 0x0054, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA03__CSI1_DATA_5 = IOMUX_PAD(0x03A0, 0x0058, 0, 0x06B4, 0, 0), + MX6_PAD_CSI_DATA03__ESAI_RX_FS = IOMUX_PAD(0x03A0, 0x0058, 1, 0x0778, 1, 0), + MX6_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x03A0, 0x0058, 2, 0x0680, 1, 0), + MX6_PAD_CSI_DATA03__KPP_ROW_5 = IOMUX_PAD(0x03A0, 0x0058, 3, 0x07D4, 0, 0), + MX6_PAD_CSI_DATA03__UART6_DCD_B = IOMUX_PAD(0x03A0, 0x0058, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__GPIO1_IO_17 = IOMUX_PAD(0x03A0, 0x0058, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__WEIM_DATA_20 = IOMUX_PAD(0x03A0, 0x0058, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__SAI1_RX_SYNC = IOMUX_PAD(0x03A0, 0x0058, 7, 0x07FC, 0, 0), + MX6_PAD_CSI_DATA03__VADC_DATA_7 = IOMUX_PAD(0x03A0, 0x0058, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__MMDC_DEBUG_40 = IOMUX_PAD(0x03A0, 0x0058, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA04__CSI1_DATA_6 = IOMUX_PAD(0x03A4, 0x005C, 0, 0x06B8, 0, 0), + MX6_PAD_CSI_DATA04__ESAI_TX1 = IOMUX_PAD(0x03A4, 0x005C, 1, 0x0794, 1, 0), + MX6_PAD_CSI_DATA04__SPDIF_OUT = IOMUX_PAD(0x03A4, 0x005C, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__KPP_COL_6 = IOMUX_PAD(0x03A4, 0x005C, 3, 0x07CC, 0, 0), + MX6_PAD_CSI_DATA04__UART6_RX = IOMUX_PAD(0x03A4, 0x005C, 4, 0x0858, 0, 0), + MX6_PAD_CSI_DATA04__GPIO1_IO_18 = IOMUX_PAD(0x03A4, 0x005C, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__WEIM_DATA_19 = IOMUX_PAD(0x03A4, 0x005C, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__PWM5_OUT = IOMUX_PAD(0x03A4, 0x005C, 7, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__VADC_DATA_8 = IOMUX_PAD(0x03A4, 0x005C, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__MMDC_DEBUG_41 = IOMUX_PAD(0x03A4, 0x005C, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA05__CSI1_DATA_7 = IOMUX_PAD(0x03A8, 0x0060, 0, 0x06BC, 0, 0), + MX6_PAD_CSI_DATA05__ESAI_TX4_RX1 = IOMUX_PAD(0x03A8, 0x0060, 1, 0x07A0, 1, 0), + MX6_PAD_CSI_DATA05__SPDIF_IN = IOMUX_PAD(0x03A8, 0x0060, 2, 0x0824, 1, 0), + MX6_PAD_CSI_DATA05__KPP_ROW_6 = IOMUX_PAD(0x03A8, 0x0060, 3, 0x07D8, 0, 0), + MX6_PAD_CSI_DATA05__UART6_TX = IOMUX_PAD(0x03A8, 0x0060, 4, 0x0858, 1, 0), + MX6_PAD_CSI_DATA05__GPIO1_IO_19 = IOMUX_PAD(0x03A8, 0x0060, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__WEIM_DATA_18 = IOMUX_PAD(0x03A8, 0x0060, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__PWM6_OUT = IOMUX_PAD(0x03A8, 0x0060, 7, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__VADC_DATA_9 = IOMUX_PAD(0x03A8, 0x0060, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__MMDC_DEBUG_42 = IOMUX_PAD(0x03A8, 0x0060, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA06__CSI1_DATA_8 = IOMUX_PAD(0x03AC, 0x0064, 0, 0x06C0, 0, 0), + MX6_PAD_CSI_DATA06__ESAI_TX2_RX3 = IOMUX_PAD(0x03AC, 0x0064, 1, 0x0798, 1, 0), + MX6_PAD_CSI_DATA06__I2C4_SCL = IOMUX_PAD(0x03AC, 0x0064, IOMUX_CONFIG_SION | 2, 0x07C0, 2, 0), + MX6_PAD_CSI_DATA06__KPP_COL_7 = IOMUX_PAD(0x03AC, 0x0064, 3, 0x07D0, 0, 0), + MX6_PAD_CSI_DATA06__UART6_RTS_B = IOMUX_PAD(0x03AC, 0x0064, 4, 0x0854, 0, 0), + MX6_PAD_CSI_DATA06__GPIO1_IO_20 = IOMUX_PAD(0x03AC, 0x0064, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__WEIM_DATA_17 = IOMUX_PAD(0x03AC, 0x0064, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__DCIC2_OUT = IOMUX_PAD(0x03AC, 0x0064, 7, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__VADC_DATA_10 = IOMUX_PAD(0x03AC, 0x0064, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__MMDC_DEBUG_43 = IOMUX_PAD(0x03AC, 0x0064, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA07__CSI1_DATA_9 = IOMUX_PAD(0x03B0, 0x0068, 0, 0x06C4, 0, 0), + MX6_PAD_CSI_DATA07__ESAI_TX3_RX2 = IOMUX_PAD(0x03B0, 0x0068, 1, 0x079C, 1, 0), + MX6_PAD_CSI_DATA07__I2C4_SDA = IOMUX_PAD(0x03B0, 0x0068, IOMUX_CONFIG_SION | 2, 0x07C4, 2, 0), + MX6_PAD_CSI_DATA07__KPP_ROW_7 = IOMUX_PAD(0x03B0, 0x0068, 3, 0x07DC, 0, 0), + MX6_PAD_CSI_DATA07__UART6_CTS_B = IOMUX_PAD(0x03B0, 0x0068, 4, 0x0854, 1, 0), + MX6_PAD_CSI_DATA07__GPIO1_IO_21 = IOMUX_PAD(0x03B0, 0x0068, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__WEIM_DATA_16 = IOMUX_PAD(0x03B0, 0x0068, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__DCIC1_OUT = IOMUX_PAD(0x03B0, 0x0068, 7, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__VADC_DATA_11 = IOMUX_PAD(0x03B0, 0x0068, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__MMDC_DEBUG_44 = IOMUX_PAD(0x03B0, 0x0068, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_HSYNC__CSI1_HSYNC = IOMUX_PAD(0x03B4, 0x006C, 0, 0x0700, 0, 0), + MX6_PAD_CSI_HSYNC__ESAI_TX0 = IOMUX_PAD(0x03B4, 0x006C, 1, 0x0790, 1, 0), + MX6_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD = IOMUX_PAD(0x03B4, 0x006C, 2, 0x0678, 1, 0), + MX6_PAD_CSI_HSYNC__UART4_RTS_B = IOMUX_PAD(0x03B4, 0x006C, 3, 0x0844, 2, 0), + MX6_PAD_CSI_HSYNC__MQS_LEFT = IOMUX_PAD(0x03B4, 0x006C, 4, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__GPIO1_IO_22 = IOMUX_PAD(0x03B4, 0x006C, 5, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__WEIM_DATA_25 = IOMUX_PAD(0x03B4, 0x006C, 6, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__SAI1_TX_DATA_0 = IOMUX_PAD(0x03B4, 0x006C, 7, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__VADC_DATA_2 = IOMUX_PAD(0x03B4, 0x006C, 8, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__MMDC_DEBUG_35 = IOMUX_PAD(0x03B4, 0x006C, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_MCLK__CSI1_MCLK = IOMUX_PAD(0x03B8, 0x0070, 0, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__ESAI_TX_HF_CLK = IOMUX_PAD(0x03B8, 0x0070, 1, 0x0784, 1, 0), + MX6_PAD_CSI_MCLK__OSC32K_32K_OUT = IOMUX_PAD(0x03B8, 0x0070, 2, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__UART4_RX = IOMUX_PAD(0x03B8, 0x0070, 3, 0x0848, 2, 0), + MX6_PAD_CSI_MCLK__ANATOP_32K_OUT = IOMUX_PAD(0x03B8, 0x0070, 4, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__GPIO1_IO_23 = IOMUX_PAD(0x03B8, 0x0070, 5, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__WEIM_DATA_26 = IOMUX_PAD(0x03B8, 0x0070, 6, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__CSI1_FIELD = IOMUX_PAD(0x03B8, 0x0070, 7, 0x070C, 0, 0), + MX6_PAD_CSI_MCLK__VADC_DATA_1 = IOMUX_PAD(0x03B8, 0x0070, 8, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__MMDC_DEBUG_34 = IOMUX_PAD(0x03B8, 0x0070, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_PIXCLK__CSI1_PIXCLK = IOMUX_PAD(0x03BC, 0x0074, 0, 0x0704, 0, 0), + MX6_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK = IOMUX_PAD(0x03BC, 0x0074, 1, 0x0780, 1, 0), + MX6_PAD_CSI_PIXCLK__AUDMUX_MCLK = IOMUX_PAD(0x03BC, 0x0074, 2, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__UART4_TX = IOMUX_PAD(0x03BC, 0x0074, 3, 0x0848, 3, 0), + MX6_PAD_CSI_PIXCLK__ANATOP_24M_OUT = IOMUX_PAD(0x03BC, 0x0074, 4, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__GPIO1_IO_24 = IOMUX_PAD(0x03BC, 0x0074, 5, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__WEIM_DATA_27 = IOMUX_PAD(0x03BC, 0x0074, 6, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK = IOMUX_PAD(0x03BC, 0x0074, 7, 0x0784, 2, 0), + MX6_PAD_CSI_PIXCLK__VADC_CLK = IOMUX_PAD(0x03BC, 0x0074, 8, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__MMDC_DEBUG_33 = IOMUX_PAD(0x03BC, 0x0074, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_VSYNC__CSI1_VSYNC = IOMUX_PAD(0x03C0, 0x0078, 0, 0x0708, 0, 0), + MX6_PAD_CSI_VSYNC__ESAI_TX5_RX0 = IOMUX_PAD(0x03C0, 0x0078, 1, 0x07A4, 1, 0), + MX6_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD = IOMUX_PAD(0x03C0, 0x0078, 2, 0x0674, 1, 0), + MX6_PAD_CSI_VSYNC__UART4_CTS_B = IOMUX_PAD(0x03C0, 0x0078, 3, 0x0844, 3, 0), + MX6_PAD_CSI_VSYNC__MQS_RIGHT = IOMUX_PAD(0x03C0, 0x0078, 4, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__GPIO1_IO_25 = IOMUX_PAD(0x03C0, 0x0078, 5, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__WEIM_DATA_24 = IOMUX_PAD(0x03C0, 0x0078, 6, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__SAI1_RX_DATA_0 = IOMUX_PAD(0x03C0, 0x0078, 7, 0x07F8, 0, 0), + MX6_PAD_CSI_VSYNC__VADC_DATA_3 = IOMUX_PAD(0x03C0, 0x0078, 8, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__MMDC_DEBUG_36 = IOMUX_PAD(0x03C0, 0x0078, 9, 0x0000, 0, 0), + + MX6_PAD_ENET1_COL__ENET1_COL = IOMUX_PAD(0x03C4, 0x007C, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_COL__ENET2_MDC = IOMUX_PAD(0x03C4, 0x007C, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_COL__AUDMUX_AUD4_TXC = IOMUX_PAD(0x03C4, 0x007C, 2, 0x0654, 1, 0), + MX6_PAD_ENET1_COL__UART1_RI_B = IOMUX_PAD(0x03C4, 0x007C, 3, 0x0000, 0, 0), + MX6_PAD_ENET1_COL__SPDIF_EXT_CLK = IOMUX_PAD(0x03C4, 0x007C, 4, 0x0828, 1, 0), + MX6_PAD_ENET1_COL__GPIO2_IO_0 = IOMUX_PAD(0x03C4, 0x007C, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_COL__CSI2_DATA_23 = IOMUX_PAD(0x03C4, 0x007C, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_COL__LCDIF2_DATA_16 = IOMUX_PAD(0x03C4, 0x007C, 7, 0x0000, 0, 0), + MX6_PAD_ENET1_COL__VDEC_DEBUG_37 = IOMUX_PAD(0x03C4, 0x007C, 8, 0x0000, 0, 0), + MX6_PAD_ENET1_COL__PCIE_CTRL_DEBUG_31 = IOMUX_PAD(0x03C4, 0x007C, 9, 0x0000, 0, 0), + + MX6_PAD_ENET1_CRS__ENET1_CRS = IOMUX_PAD(0x03C8, 0x0080, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_CRS__ENET2_MDIO = IOMUX_PAD(0x03C8, 0x0080, 1, 0x0770, 1, 0), + MX6_PAD_ENET1_CRS__AUDMUX_AUD4_TXD = IOMUX_PAD(0x03C8, 0x0080, 2, 0x0648, 1, 0), + MX6_PAD_ENET1_CRS__UART1_DCD_B = IOMUX_PAD(0x03C8, 0x0080, 3, 0x0000, 0, 0), + MX6_PAD_ENET1_CRS__SPDIF_LOCK = IOMUX_PAD(0x03C8, 0x0080, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_CRS__GPIO2_IO_1 = IOMUX_PAD(0x03C8, 0x0080, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_CRS__CSI2_DATA_22 = IOMUX_PAD(0x03C8, 0x0080, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_CRS__LCDIF2_DATA_17 = IOMUX_PAD(0x03C8, 0x0080, 7, 0x0000, 0, 0), + MX6_PAD_ENET1_CRS__VDEC_DEBUG_36 = IOMUX_PAD(0x03C8, 0x0080, 8, 0x0000, 0, 0), + MX6_PAD_ENET1_CRS__PCIE_CTRL_DEBUG_30 = IOMUX_PAD(0x03C8, 0x0080, 9, 0x0000, 0, 0), + + MX6_PAD_ENET1_MDC__ENET1_MDC = IOMUX_PAD(0x03CC, 0x0084, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_MDC__ENET2_MDC = IOMUX_PAD(0x03CC, 0x0084, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x03CC, 0x0084, 2, 0x0638, 1, 0), + MX6_PAD_ENET1_MDC__ANATOP_24M_OUT = IOMUX_PAD(0x03CC, 0x0084, 3, 0x0000, 0, 0), + MX6_PAD_ENET1_MDC__EPIT2_OUT = IOMUX_PAD(0x03CC, 0x0084, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_MDC__GPIO2_IO_2 = IOMUX_PAD(0x03CC, 0x0084, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_MDC__USB_OTG1_PWR = IOMUX_PAD(0x03CC, 0x0084, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_MDC__PWM7_OUT = IOMUX_PAD(0x03CC, 0x0084, 7, 0x0000, 0, 0), + + MX6_PAD_ENET1_MDIO__ENET1_MDIO = IOMUX_PAD(0x03D0, 0x0088, 0, 0x0764, 1, 0), + MX6_PAD_ENET1_MDIO__ENET2_MDIO = IOMUX_PAD(0x03D0, 0x0088, 1, 0x0770, 2, 0), + MX6_PAD_ENET1_MDIO__AUDMUX_MCLK = IOMUX_PAD(0x03D0, 0x0088, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_MDIO__OSC32K_32K_OUT = IOMUX_PAD(0x03D0, 0x0088, 3, 0x0000, 0, 0), + MX6_PAD_ENET1_MDIO__EPIT1_OUT = IOMUX_PAD(0x03D0, 0x0088, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_MDIO__GPIO2_IO_3 = IOMUX_PAD(0x03D0, 0x0088, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_MDIO__USB_OTG1_OC = IOMUX_PAD(0x03D0, 0x0088, 6, 0x0860, 1, 0), + MX6_PAD_ENET1_MDIO__PWM8_OUT = IOMUX_PAD(0x03D0, 0x0088, 7, 0x0000, 0, 0), + + MX6_PAD_ENET1_RX_CLK__ENET1_RX_CLK = IOMUX_PAD(0x03D4, 0x008C, 0, 0x0768, 0, 0), + MX6_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M = IOMUX_PAD(0x03D4, 0x008C, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x03D4, 0x008C, 2, 0x0658, 1, 0), + MX6_PAD_ENET1_RX_CLK__UART1_DSR_B = IOMUX_PAD(0x03D4, 0x008C, 3, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_CLK__SPDIF_OUT = IOMUX_PAD(0x03D4, 0x008C, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_CLK__GPIO2_IO_4 = IOMUX_PAD(0x03D4, 0x008C, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_CLK__CSI2_DATA_21 = IOMUX_PAD(0x03D4, 0x008C, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_CLK__LCDIF2_DATA_18 = IOMUX_PAD(0x03D4, 0x008C, 7, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 = IOMUX_PAD(0x03D4, 0x008C, 8, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 = IOMUX_PAD(0x03D4, 0x008C, 9, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK = IOMUX_PAD(0x03D8, 0x0090, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 = IOMUX_PAD(0x03D8, 0x0090, 1, 0x0760, 1, 0), + MX6_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD = IOMUX_PAD(0x03D8, 0x0090, 2, 0x0644, 1, 0), + MX6_PAD_ENET1_TX_CLK__UART1_DTR_B = IOMUX_PAD(0x03D8, 0x0090, 3, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__SPDIF_SR_CLK = IOMUX_PAD(0x03D8, 0x0090, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__GPIO2_IO_5 = IOMUX_PAD(0x03D8, 0x0090, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__CSI2_DATA_20 = IOMUX_PAD(0x03D8, 0x0090, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__LCDIF2_DATA_19 = IOMUX_PAD(0x03D8, 0x0090, 7, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__VDEC_DEBUG_34 = IOMUX_PAD(0x03D8, 0x0090, 8, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__PCIE_CTRL_DEBUG_28 = IOMUX_PAD(0x03D8, 0x0090, 9, 0x0000, 0, 0), + + MX6_PAD_ENET2_COL__ENET2_COL = IOMUX_PAD(0x03DC, 0x0094, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_COL__ENET1_MDC = IOMUX_PAD(0x03DC, 0x0094, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_COL__AUDMUX_AUD4_RXC = IOMUX_PAD(0x03DC, 0x0094, 2, 0x064C, 1, 0), + MX6_PAD_ENET2_COL__UART1_RX = IOMUX_PAD(0x03DC, 0x0094, 3, 0x0830, 2, 0), + MX6_PAD_ENET2_COL__SPDIF_IN = IOMUX_PAD(0x03DC, 0x0094, 4, 0x0824, 3, 0), + MX6_PAD_ENET2_COL__GPIO2_IO_6 = IOMUX_PAD(0x03DC, 0x0094, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_COL__ANATOP_OTG1_ID = IOMUX_PAD(0x03DC, 0x0094, 6, 0x0624, 1, 0), + MX6_PAD_ENET2_COL__LCDIF2_DATA_20 = IOMUX_PAD(0x03DC, 0x0094, 7, 0x0000, 0, 0), + MX6_PAD_ENET2_COL__VDEC_DEBUG_33 = IOMUX_PAD(0x03DC, 0x0094, 8, 0x0000, 0, 0), + MX6_PAD_ENET2_COL__PCIE_CTRL_DEBUG_27 = IOMUX_PAD(0x03DC, 0x0094, 9, 0x0000, 0, 0), + + MX6_PAD_ENET2_CRS__ENET2_CRS = IOMUX_PAD(0x03E0, 0x0098, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_CRS__ENET1_MDIO = IOMUX_PAD(0x03E0, 0x0098, 1, 0x0764, 2, 0), + MX6_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x03E0, 0x0098, 2, 0x0650, 1, 0), + MX6_PAD_ENET2_CRS__UART1_TX = IOMUX_PAD(0x03E0, 0x0098, 3, 0x0830, 3, 0), + MX6_PAD_ENET2_CRS__MLB_SIG = IOMUX_PAD(0x03E0, 0x0098, 4, 0x07F0, 1, 0), + MX6_PAD_ENET2_CRS__GPIO2_IO_7 = IOMUX_PAD(0x03E0, 0x0098, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_CRS__ANATOP_OTG2_ID = IOMUX_PAD(0x03E0, 0x0098, 6, 0x0628, 1, 0), + MX6_PAD_ENET2_CRS__LCDIF2_DATA_21 = IOMUX_PAD(0x03E0, 0x0098, 7, 0x0000, 0, 0), + MX6_PAD_ENET2_CRS__VDEC_DEBUG_32 = IOMUX_PAD(0x03E0, 0x0098, 8, 0x0000, 0, 0), + MX6_PAD_ENET2_CRS__PCIE_CTRL_DEBUG_26 = IOMUX_PAD(0x03E0, 0x0098, 9, 0x0000, 0, 0), + + MX6_PAD_ENET2_RX_CLK__ENET2_RX_CLK = IOMUX_PAD(0x03E4, 0x009C, 0, 0x0774, 0, 0), + MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M = IOMUX_PAD(0x03E4, 0x009C, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_CLK__I2C3_SCL = IOMUX_PAD(0x03E4, 0x009C, IOMUX_CONFIG_SION | 2, 0x07B8, 1, 0), + MX6_PAD_ENET2_RX_CLK__UART1_RTS_B = IOMUX_PAD(0x03E4, 0x009C, 3, 0x082C, 2, 0), + MX6_PAD_ENET2_RX_CLK__MLB_DATA = IOMUX_PAD(0x03E4, 0x009C, 4, 0x07EC, 1, 0), + MX6_PAD_ENET2_RX_CLK__GPIO2_IO_8 = IOMUX_PAD(0x03E4, 0x009C, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_CLK__USB_OTG2_OC = IOMUX_PAD(0x03E4, 0x009C, 6, 0x085C, 1, 0), + MX6_PAD_ENET2_RX_CLK__LCDIF2_DATA_22 = IOMUX_PAD(0x03E4, 0x009C, 7, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_CLK__VDEC_DEBUG_31 = IOMUX_PAD(0x03E4, 0x009C, 8, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_CLK__PCIE_CTRL_DEBUG_25 = IOMUX_PAD(0x03E4, 0x009C, 9, 0x0000, 0, 0), + + MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK = IOMUX_PAD(0x03E8, 0x00A0, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 = IOMUX_PAD(0x03E8, 0x00A0, 1, 0x076C, 1, 0), + MX6_PAD_ENET2_TX_CLK__I2C3_SDA = IOMUX_PAD(0x03E8, 0x00A0, IOMUX_CONFIG_SION | 2, 0x07BC, 1, 0), + MX6_PAD_ENET2_TX_CLK__UART1_CTS_B = IOMUX_PAD(0x03E8, 0x00A0, 3, 0x082C, 3, 0), + MX6_PAD_ENET2_TX_CLK__MLB_CLK = IOMUX_PAD(0x03E8, 0x00A0, 4, 0x07E8, 1, 0), + MX6_PAD_ENET2_TX_CLK__GPIO2_IO_9 = IOMUX_PAD(0x03E8, 0x00A0, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__USB_OTG2_PWR = IOMUX_PAD(0x03E8, 0x00A0, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__LCDIF2_DATA_23 = IOMUX_PAD(0x03E8, 0x00A0, 7, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__VDEC_DEBUG_30 = IOMUX_PAD(0x03E8, 0x00A0, 8, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24 = IOMUX_PAD(0x03E8, 0x00A0, 9, 0x0000, 0, 0), + + MX6_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x03EC, 0x00A4, 0, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__USDHC3_CD_B = IOMUX_PAD(0x03EC, 0x00A4, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__UART6_RTS_B = IOMUX_PAD(0x03EC, 0x00A4, 2, 0x0854, 2, 0), + MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x03EC, 0x00A4, 3, 0x0710, 0, 0), + MX6_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x03EC, 0x00A4, 4, 0x066C, 0, 0), + MX6_PAD_KEY_COL0__GPIO2_IO_10 = IOMUX_PAD(0x03EC, 0x00A4, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x03EC, 0x00A4, 6, 0x0820, 1, 0), + MX6_PAD_KEY_COL0__SAI2_TX_BCLK = IOMUX_PAD(0x03EC, 0x00A4, 7, 0x0814, 0, 0), + MX6_PAD_KEY_COL0__VADC_DATA_0 = IOMUX_PAD(0x03EC, 0x00A4, 8, 0x0000, 0, 0), + + MX6_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x03F0, 0x00A8, 0, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__USDHC3_RESET_B = IOMUX_PAD(0x03F0, 0x00A8, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__UART6_TX = IOMUX_PAD(0x03F0, 0x00A8, 2, 0x0858, 2, 0), + MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x03F0, 0x00A8, 3, 0x0714, 0, 0), + MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x03F0, 0x00A8, 4, 0x0670, 0, 0), + MX6_PAD_KEY_COL1__GPIO2_IO_11 = IOMUX_PAD(0x03F0, 0x00A8, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__USDHC3_RESET = IOMUX_PAD(0x03F0, 0x00A8, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__SAI2_TX_SYNC = IOMUX_PAD(0x03F0, 0x00A8, 7, 0x0818, 0, 0), + + MX6_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x03F4, 0x00AC, 0, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__USDHC4_CD_B = IOMUX_PAD(0x03F4, 0x00AC, 1, 0x0874, 1, 0), + MX6_PAD_KEY_COL2__UART5_RTS_B = IOMUX_PAD(0x03F4, 0x00AC, 2, 0x084C, 2, 0), + MX6_PAD_KEY_COL2__CAN1_TX = IOMUX_PAD(0x03F4, 0x00AC, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__CANFD_TX1 = IOMUX_PAD(0x03F4, 0x00AC, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__GPIO2_IO_12 = IOMUX_PAD(0x03F4, 0x00AC, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__WEIM_DATA_30 = IOMUX_PAD(0x03F4, 0x00AC, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__ECSPI1_RDY = IOMUX_PAD(0x03F4, 0x00AC, 7, 0x0000, 0, 0), + + MX6_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x03F8, 0x00B0, 0, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__USDHC4_LCTL = IOMUX_PAD(0x03F8, 0x00B0, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__UART5_TX = IOMUX_PAD(0x03F8, 0x00B0, 2, 0x0850, 2, 0), + MX6_PAD_KEY_COL3__CAN2_TX = IOMUX_PAD(0x03F8, 0x00B0, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__CANFD_TX2 = IOMUX_PAD(0x03F8, 0x00B0, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__GPIO2_IO_13 = IOMUX_PAD(0x03F8, 0x00B0, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__WEIM_DATA_28 = IOMUX_PAD(0x03F8, 0x00B0, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__ECSPI1_SS2 = IOMUX_PAD(0x03F8, 0x00B0, 7, 0x0000, 0, 0), + + MX6_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x03FC, 0x00B4, 0, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__ENET2_MDC = IOMUX_PAD(0x03FC, 0x00B4, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__I2C3_SCL = IOMUX_PAD(0x03FC, 0x00B4, IOMUX_CONFIG_SION | 2, 0x07B8, 2, 0), + MX6_PAD_KEY_COL4__USDHC2_LCTL = IOMUX_PAD(0x03FC, 0x00B4, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03FC, 0x00B4, 4, 0x0664, 0, 0), + MX6_PAD_KEY_COL4__GPIO2_IO_14 = IOMUX_PAD(0x03FC, 0x00B4, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__WEIM_CRE = IOMUX_PAD(0x03FC, 0x00B4, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__SAI2_RX_BCLK = IOMUX_PAD(0x03FC, 0x00B4, 7, 0x0808, 0, 0), + + MX6_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x0400, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__USDHC3_WP = IOMUX_PAD(0x0400, 0x00B8, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__UART6_CTS_B = IOMUX_PAD(0x0400, 0x00B8, 2, 0x0854, 3, 0), + MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x0400, 0x00B8, 3, 0x0718, 0, 0), + MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x0400, 0x00B8, 4, 0x0660, 0, 0), + MX6_PAD_KEY_ROW0__GPIO2_IO_15 = IOMUX_PAD(0x0400, 0x00B8, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x0400, 0x00B8, 6, 0x081C, 1, 0), + MX6_PAD_KEY_ROW0__SAI2_TX_DATA_0 = IOMUX_PAD(0x0400, 0x00B8, 7, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__GPU_IDLE = IOMUX_PAD(0x0400, 0x00B8, 8, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x0404, 0x00BC, 0, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__USDHC4_VSELECT = IOMUX_PAD(0x0404, 0x00BC, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__UART6_RX = IOMUX_PAD(0x0404, 0x00BC, 2, 0x0858, 3, 0), + MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x0404, 0x00BC, 3, 0x071C, 0, 0), + MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x0404, 0x00BC, 4, 0x065C, 0, 0), + MX6_PAD_KEY_ROW1__GPIO2_IO_16 = IOMUX_PAD(0x0404, 0x00BC, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__WEIM_DATA_31 = IOMUX_PAD(0x0404, 0x00BC, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__SAI2_RX_DATA_0 = IOMUX_PAD(0x0404, 0x00BC, 7, 0x080C, 0, 0), + MX6_PAD_KEY_ROW1__M4_NMI = IOMUX_PAD(0x0404, 0x00BC, 8, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x0408, 0x00C0, 0, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__USDHC4_WP = IOMUX_PAD(0x0408, 0x00C0, 1, 0x0878, 1, 0), + MX6_PAD_KEY_ROW2__UART5_CTS_B = IOMUX_PAD(0x0408, 0x00C0, 2, 0x084C, 3, 0), + MX6_PAD_KEY_ROW2__CAN1_RX = IOMUX_PAD(0x0408, 0x00C0, 3, 0x068C, 1, 0), + MX6_PAD_KEY_ROW2__CANFD_RX1 = IOMUX_PAD(0x0408, 0x00C0, 4, 0x0694, 1, 0), + MX6_PAD_KEY_ROW2__GPIO2_IO_17 = IOMUX_PAD(0x0408, 0x00C0, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__WEIM_DATA_29 = IOMUX_PAD(0x0408, 0x00C0, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__ECSPI1_SS3 = IOMUX_PAD(0x0408, 0x00C0, 7, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x040C, 0x00C4, 0, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__USDHC3_LCTL = IOMUX_PAD(0x040C, 0x00C4, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__UART5_RX = IOMUX_PAD(0x040C, 0x00C4, 2, 0x0850, 3, 0), + MX6_PAD_KEY_ROW3__CAN2_RX = IOMUX_PAD(0x040C, 0x00C4, 3, 0x0690, 1, 0), + MX6_PAD_KEY_ROW3__CANFD_RX2 = IOMUX_PAD(0x040C, 0x00C4, 4, 0x0698, 1, 0), + MX6_PAD_KEY_ROW3__GPIO2_IO_18 = IOMUX_PAD(0x040C, 0x00C4, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__WEIM_DTACK_B = IOMUX_PAD(0x040C, 0x00C4, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__ECSPI1_SS1 = IOMUX_PAD(0x040C, 0x00C4, 7, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x0410, 0x00C8, 0, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__ENET2_MDIO = IOMUX_PAD(0x0410, 0x00C8, 1, 0x0770, 3, 0), + MX6_PAD_KEY_ROW4__I2C3_SDA = IOMUX_PAD(0x0410, 0x00C8, IOMUX_CONFIG_SION | 2, 0x07BC, 2, 0), + MX6_PAD_KEY_ROW4__USDHC1_LCTL = IOMUX_PAD(0x0410, 0x00C8, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0410, 0x00C8, 4, 0x0668, 0, 0), + MX6_PAD_KEY_ROW4__GPIO2_IO_19 = IOMUX_PAD(0x0410, 0x00C8, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__WEIM_ACLK_FREERUN = IOMUX_PAD(0x0410, 0x00C8, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__SAI2_RX_SYNC = IOMUX_PAD(0x0410, 0x00C8, 7, 0x0810, 0, 0), + + MX6_PAD_LCD1_CLK__LCDIF1_CLK = IOMUX_PAD(0x0414, 0x00CC, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_CLK__LCDIF1_WR_RWN = IOMUX_PAD(0x0414, 0x00CC, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_CLK__AUDMUX_AUD3_RXC = IOMUX_PAD(0x0414, 0x00CC, 2, 0x0634, 1, 0), + MX6_PAD_LCD1_CLK__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x0414, 0x00CC, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_CLK__CSI1_DATA_16 = IOMUX_PAD(0x0414, 0x00CC, 4, 0x06DC, 0, 0), + MX6_PAD_LCD1_CLK__GPIO3_IO_0 = IOMUX_PAD(0x0414, 0x00CC, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_CLK__USDHC1_WP = IOMUX_PAD(0x0414, 0x00CC, 6, 0x0868, 0, 0), + MX6_PAD_LCD1_CLK__SIM_M_HADDR_16 = IOMUX_PAD(0x0414, 0x00CC, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_CLK__VADC_TEST_0 = IOMUX_PAD(0x0414, 0x00CC, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_CLK__MMDC_DEBUG_0 = IOMUX_PAD(0x0414, 0x00CC, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 = IOMUX_PAD(0x0418, 0x00D0, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA00__WEIM_CS1_B = IOMUX_PAD(0x0418, 0x00D0, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA00__M4_TRACE_0 = IOMUX_PAD(0x0418, 0x00D0, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA00__KITTEN_TRACE_0 = IOMUX_PAD(0x0418, 0x00D0, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA00__CSI1_DATA_20 = IOMUX_PAD(0x0418, 0x00D0, 4, 0x06EC, 0, 0), + MX6_PAD_LCD1_DATA00__GPIO3_IO_1 = IOMUX_PAD(0x0418, 0x00D0, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA00__SRC_BT_CFG_0 = IOMUX_PAD(0x0418, 0x00D0, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA00__SIM_M_HADDR_21 = IOMUX_PAD(0x0418, 0x00D0, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA00__VADC_TEST_5 = IOMUX_PAD(0x0418, 0x00D0, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA00__MMDC_DEBUG_5 = IOMUX_PAD(0x0418, 0x00D0, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 = IOMUX_PAD(0x041C, 0x00D4, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA01__WEIM_CS2_B = IOMUX_PAD(0x041C, 0x00D4, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA01__M4_TRACE_1 = IOMUX_PAD(0x041C, 0x00D4, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA01__KITTEN_TRACE_1 = IOMUX_PAD(0x041C, 0x00D4, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA01__CSI1_DATA_21 = IOMUX_PAD(0x041C, 0x00D4, 4, 0x06F0, 0, 0), + MX6_PAD_LCD1_DATA01__GPIO3_IO_2 = IOMUX_PAD(0x041C, 0x00D4, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA01__SRC_BT_CFG_1 = IOMUX_PAD(0x041C, 0x00D4, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA01__SIM_M_HADDR_22 = IOMUX_PAD(0x041C, 0x00D4, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA01__VADC_TEST_6 = IOMUX_PAD(0x041C, 0x00D4, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA01__MMDC_DEBUG_6 = IOMUX_PAD(0x041C, 0x00D4, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 = IOMUX_PAD(0x0420, 0x00D8, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA02__WEIM_CS3_B = IOMUX_PAD(0x0420, 0x00D8, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA02__M4_TRACE_2 = IOMUX_PAD(0x0420, 0x00D8, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA02__KITTEN_TRACE_2 = IOMUX_PAD(0x0420, 0x00D8, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA02__CSI1_DATA_22 = IOMUX_PAD(0x0420, 0x00D8, 4, 0x06F4, 0, 0), + MX6_PAD_LCD1_DATA02__GPIO3_IO_3 = IOMUX_PAD(0x0420, 0x00D8, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA02__SRC_BT_CFG_2 = IOMUX_PAD(0x0420, 0x00D8, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA02__SIM_M_HADDR_23 = IOMUX_PAD(0x0420, 0x00D8, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA02__VADC_TEST_7 = IOMUX_PAD(0x0420, 0x00D8, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA02__MMDC_DEBUG_7 = IOMUX_PAD(0x0420, 0x00D8, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 = IOMUX_PAD(0x0424, 0x00DC, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA03__WEIM_ADDR_24 = IOMUX_PAD(0x0424, 0x00DC, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA03__M4_TRACE_3 = IOMUX_PAD(0x0424, 0x00DC, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA03__KITTEN_TRACE_3 = IOMUX_PAD(0x0424, 0x00DC, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA03__CSI1_DATA_23 = IOMUX_PAD(0x0424, 0x00DC, 4, 0x06F8, 0, 0), + MX6_PAD_LCD1_DATA03__GPIO3_IO_4 = IOMUX_PAD(0x0424, 0x00DC, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA03__SRC_BT_CFG_3 = IOMUX_PAD(0x0424, 0x00DC, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA03__SIM_M_HADDR_24 = IOMUX_PAD(0x0424, 0x00DC, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA03__VADC_TEST_8 = IOMUX_PAD(0x0424, 0x00DC, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA03__MMDC_DEBUG_8 = IOMUX_PAD(0x0424, 0x00DC, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 = IOMUX_PAD(0x0428, 0x00E0, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA04__WEIM_ADDR_25 = IOMUX_PAD(0x0428, 0x00E0, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA04__KITTEN_TRACE_4 = IOMUX_PAD(0x0428, 0x00E0, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA04__CSI1_VSYNC = IOMUX_PAD(0x0428, 0x00E0, 4, 0x0708, 1, 0), + MX6_PAD_LCD1_DATA04__GPIO3_IO_5 = IOMUX_PAD(0x0428, 0x00E0, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA04__SRC_BT_CFG_4 = IOMUX_PAD(0x0428, 0x00E0, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA04__SIM_M_HADDR_25 = IOMUX_PAD(0x0428, 0x00E0, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA04__VADC_TEST_9 = IOMUX_PAD(0x0428, 0x00E0, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA04__MMDC_DEBUG_9 = IOMUX_PAD(0x0428, 0x00E0, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 = IOMUX_PAD(0x042C, 0x00E4, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA05__WEIM_ADDR_26 = IOMUX_PAD(0x042C, 0x00E4, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA05__KITTEN_TRACE_5 = IOMUX_PAD(0x042C, 0x00E4, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA05__CSI1_HSYNC = IOMUX_PAD(0x042C, 0x00E4, 4, 0x0700, 1, 0), + MX6_PAD_LCD1_DATA05__GPIO3_IO_6 = IOMUX_PAD(0x042C, 0x00E4, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA05__SRC_BT_CFG_5 = IOMUX_PAD(0x042C, 0x00E4, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA05__SIM_M_HADDR_26 = IOMUX_PAD(0x042C, 0x00E4, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA05__VADC_TEST_10 = IOMUX_PAD(0x042C, 0x00E4, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA05__MMDC_DEBUG_10 = IOMUX_PAD(0x042C, 0x00E4, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 = IOMUX_PAD(0x0430, 0x00E8, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA06__WEIM_EB_B_2 = IOMUX_PAD(0x0430, 0x00E8, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA06__KITTEN_TRACE_6 = IOMUX_PAD(0x0430, 0x00E8, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA06__CSI1_PIXCLK = IOMUX_PAD(0x0430, 0x00E8, 4, 0x0704, 1, 0), + MX6_PAD_LCD1_DATA06__GPIO3_IO_7 = IOMUX_PAD(0x0430, 0x00E8, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA06__SRC_BT_CFG_6 = IOMUX_PAD(0x0430, 0x00E8, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA06__SIM_M_HADDR_27 = IOMUX_PAD(0x0430, 0x00E8, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA06__VADC_TEST_11 = IOMUX_PAD(0x0430, 0x00E8, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA06__MMDC_DEBUG_11 = IOMUX_PAD(0x0430, 0x00E8, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 = IOMUX_PAD(0x0434, 0x00EC, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA07__WEIM_EB_B_3 = IOMUX_PAD(0x0434, 0x00EC, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA07__KITTEN_TRACE_7 = IOMUX_PAD(0x0434, 0x00EC, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA07__CSI1_MCLK = IOMUX_PAD(0x0434, 0x00EC, 4, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA07__GPIO3_IO_8 = IOMUX_PAD(0x0434, 0x00EC, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA07__SRC_BT_CFG_7 = IOMUX_PAD(0x0434, 0x00EC, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA07__SIM_M_HADDR_28 = IOMUX_PAD(0x0434, 0x00EC, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA07__VADC_TEST_12 = IOMUX_PAD(0x0434, 0x00EC, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA07__MMDC_DEBUG_12 = IOMUX_PAD(0x0434, 0x00EC, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 = IOMUX_PAD(0x0438, 0x00F0, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA08__WEIM_AD_8 = IOMUX_PAD(0x0438, 0x00F0, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA08__KITTEN_TRACE_8 = IOMUX_PAD(0x0438, 0x00F0, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA08__CSI1_DATA_9 = IOMUX_PAD(0x0438, 0x00F0, 4, 0x06C4, 1, 0), + MX6_PAD_LCD1_DATA08__GPIO3_IO_9 = IOMUX_PAD(0x0438, 0x00F0, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA08__SRC_BT_CFG_8 = IOMUX_PAD(0x0438, 0x00F0, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA08__SIM_M_HADDR_29 = IOMUX_PAD(0x0438, 0x00F0, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA08__VADC_TEST_13 = IOMUX_PAD(0x0438, 0x00F0, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA08__MMDC_DEBUG_13 = IOMUX_PAD(0x0438, 0x00F0, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 = IOMUX_PAD(0x043C, 0x00F4, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA09__WEIM_AD_9 = IOMUX_PAD(0x043C, 0x00F4, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA09__KITTEN_TRACE_9 = IOMUX_PAD(0x043C, 0x00F4, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA09__CSI1_DATA_8 = IOMUX_PAD(0x043C, 0x00F4, 4, 0x06C0, 1, 0), + MX6_PAD_LCD1_DATA09__GPIO3_IO_10 = IOMUX_PAD(0x043C, 0x00F4, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA09__SRC_BT_CFG_9 = IOMUX_PAD(0x043C, 0x00F4, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA09__SIM_M_HADDR_30 = IOMUX_PAD(0x043C, 0x00F4, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA09__VADC_TEST_14 = IOMUX_PAD(0x043C, 0x00F4, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA09__MMDC_DEBUG_14 = IOMUX_PAD(0x043C, 0x00F4, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 = IOMUX_PAD(0x0440, 0x00F8, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA10__WEIM_AD_10 = IOMUX_PAD(0x0440, 0x00F8, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA10__KITTEN_TRACE_10 = IOMUX_PAD(0x0440, 0x00F8, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA10__CSI1_DATA_7 = IOMUX_PAD(0x0440, 0x00F8, 4, 0x06BC, 1, 0), + MX6_PAD_LCD1_DATA10__GPIO3_IO_11 = IOMUX_PAD(0x0440, 0x00F8, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA10__SRC_BT_CFG_10 = IOMUX_PAD(0x0440, 0x00F8, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA10__SIM_M_HADDR_31 = IOMUX_PAD(0x0440, 0x00F8, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA10__VADC_TEST_15 = IOMUX_PAD(0x0440, 0x00F8, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA10__MMDC_DEBUG_15 = IOMUX_PAD(0x0440, 0x00F8, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 = IOMUX_PAD(0x0444, 0x00FC, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA11__WEIM_AD_11 = IOMUX_PAD(0x0444, 0x00FC, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA11__KITTEN_TRACE_11 = IOMUX_PAD(0x0444, 0x00FC, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA11__CSI1_DATA_6 = IOMUX_PAD(0x0444, 0x00FC, 4, 0x06B8, 1, 0), + MX6_PAD_LCD1_DATA11__GPIO3_IO_12 = IOMUX_PAD(0x0444, 0x00FC, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA11__SRC_BT_CFG_11 = IOMUX_PAD(0x0444, 0x00FC, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA11__SIM_M_HBURST_0 = IOMUX_PAD(0x0444, 0x00FC, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA11__VADC_TEST_16 = IOMUX_PAD(0x0444, 0x00FC, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA11__MMDC_DEBUG_16 = IOMUX_PAD(0x0444, 0x00FC, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 = IOMUX_PAD(0x0448, 0x0100, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA12__WEIM_AD_12 = IOMUX_PAD(0x0448, 0x0100, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA12__KITTEN_TRACE_12 = IOMUX_PAD(0x0448, 0x0100, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA12__CSI1_DATA_5 = IOMUX_PAD(0x0448, 0x0100, 4, 0x06B4, 1, 0), + MX6_PAD_LCD1_DATA12__GPIO3_IO_13 = IOMUX_PAD(0x0448, 0x0100, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA12__SRC_BT_CFG_12 = IOMUX_PAD(0x0448, 0x0100, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA12__SIM_M_HBURST_1 = IOMUX_PAD(0x0448, 0x0100, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA12__VADC_TEST_17 = IOMUX_PAD(0x0448, 0x0100, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA12__MMDC_DEBUG_17 = IOMUX_PAD(0x0448, 0x0100, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 = IOMUX_PAD(0x044C, 0x0104, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA13__WEIM_AD_13 = IOMUX_PAD(0x044C, 0x0104, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA13__KITTEN_TRACE_13 = IOMUX_PAD(0x044C, 0x0104, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA13__CSI1_DATA_4 = IOMUX_PAD(0x044C, 0x0104, 4, 0x06B0, 1, 0), + MX6_PAD_LCD1_DATA13__GPIO3_IO_14 = IOMUX_PAD(0x044C, 0x0104, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA13__SRC_BT_CFG_13 = IOMUX_PAD(0x044C, 0x0104, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA13__SIM_M_HBURST_2 = IOMUX_PAD(0x044C, 0x0104, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA13__VADC_TEST_18 = IOMUX_PAD(0x044C, 0x0104, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA13__MMDC_DEBUG_18 = IOMUX_PAD(0x044C, 0x0104, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 = IOMUX_PAD(0x0450, 0x0108, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA14__WEIM_AD_14 = IOMUX_PAD(0x0450, 0x0108, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA14__KITTEN_TRACE_14 = IOMUX_PAD(0x0450, 0x0108, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA14__CSI1_DATA_3 = IOMUX_PAD(0x0450, 0x0108, 4, 0x06AC, 1, 0), + MX6_PAD_LCD1_DATA14__GPIO3_IO_15 = IOMUX_PAD(0x0450, 0x0108, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA14__SRC_BT_CFG_14 = IOMUX_PAD(0x0450, 0x0108, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA14__SIM_M_HMASTLOCK = IOMUX_PAD(0x0450, 0x0108, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA14__VADC_TEST_19 = IOMUX_PAD(0x0450, 0x0108, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA14__MMDC_DEBUG_19 = IOMUX_PAD(0x0450, 0x0108, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 = IOMUX_PAD(0x0454, 0x010C, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA15__WEIM_AD_15 = IOMUX_PAD(0x0454, 0x010C, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA15__KITTEN_TRACE_15 = IOMUX_PAD(0x0454, 0x010C, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA15__CSI1_DATA_2 = IOMUX_PAD(0x0454, 0x010C, 4, 0x06A8, 1, 0), + MX6_PAD_LCD1_DATA15__GPIO3_IO_16 = IOMUX_PAD(0x0454, 0x010C, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA15__SRC_BT_CFG_15 = IOMUX_PAD(0x0454, 0x010C, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA15__SIM_M_HPROT_0 = IOMUX_PAD(0x0454, 0x010C, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA15__VDEC_DEBUG_0 = IOMUX_PAD(0x0454, 0x010C, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA15__MMDC_DEBUG_20 = IOMUX_PAD(0x0454, 0x010C, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 = IOMUX_PAD(0x0458, 0x0110, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA16__WEIM_ADDR_16 = IOMUX_PAD(0x0458, 0x0110, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA16__M4_TRACE_CLK = IOMUX_PAD(0x0458, 0x0110, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA16__KITTEN_TRACE_CLK = IOMUX_PAD(0x0458, 0x0110, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA16__CSI1_DATA_1 = IOMUX_PAD(0x0458, 0x0110, 4, 0x06A4, 0, 0), + MX6_PAD_LCD1_DATA16__GPIO3_IO_17 = IOMUX_PAD(0x0458, 0x0110, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA16__SRC_BT_CFG_24 = IOMUX_PAD(0x0458, 0x0110, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA16__SIM_M_HPROT_1 = IOMUX_PAD(0x0458, 0x0110, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA16__VDEC_DEBUG_1 = IOMUX_PAD(0x0458, 0x0110, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA16__MMDC_DEBUG_21 = IOMUX_PAD(0x0458, 0x0110, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 = IOMUX_PAD(0x045C, 0x0114, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA17__WEIM_ADDR_17 = IOMUX_PAD(0x045C, 0x0114, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA17__KITTEN_TRACE_CTL = IOMUX_PAD(0x045C, 0x0114, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA17__CSI1_DATA_0 = IOMUX_PAD(0x045C, 0x0114, 4, 0x06A0, 0, 0), + MX6_PAD_LCD1_DATA17__GPIO3_IO_18 = IOMUX_PAD(0x045C, 0x0114, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA17__SRC_BT_CFG_25 = IOMUX_PAD(0x045C, 0x0114, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA17__SIM_M_HPROT_2 = IOMUX_PAD(0x045C, 0x0114, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA17__VDEC_DEBUG_2 = IOMUX_PAD(0x045C, 0x0114, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA17__MMDC_DEBUG_22 = IOMUX_PAD(0x045C, 0x0114, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 = IOMUX_PAD(0x0460, 0x0118, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA18__WEIM_ADDR_18 = IOMUX_PAD(0x0460, 0x0118, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA18__M4_EVENTO = IOMUX_PAD(0x0460, 0x0118, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA18__KITTEN_EVENTO = IOMUX_PAD(0x0460, 0x0118, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA18__CSI1_DATA_15 = IOMUX_PAD(0x0460, 0x0118, 4, 0x06D8, 0, 0), + MX6_PAD_LCD1_DATA18__GPIO3_IO_19 = IOMUX_PAD(0x0460, 0x0118, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA18__SRC_BT_CFG_26 = IOMUX_PAD(0x0460, 0x0118, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA18__SIM_M_HPROT_3 = IOMUX_PAD(0x0460, 0x0118, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA18__VDEC_DEBUG_3 = IOMUX_PAD(0x0460, 0x0118, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA18__MMDC_DEBUG_23 = IOMUX_PAD(0x0460, 0x0118, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 = IOMUX_PAD(0x0464, 0x011C, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA19__WEIM_ADDR_19 = IOMUX_PAD(0x0464, 0x011C, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA19__M4_TRACE_SWO = IOMUX_PAD(0x0464, 0x011C, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA19__CSI1_DATA_14 = IOMUX_PAD(0x0464, 0x011C, 4, 0x06D4, 0, 0), + MX6_PAD_LCD1_DATA19__GPIO3_IO_20 = IOMUX_PAD(0x0464, 0x011C, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA19__SRC_BT_CFG_27 = IOMUX_PAD(0x0464, 0x011C, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA19__SIM_M_HREADYOUT = IOMUX_PAD(0x0464, 0x011C, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA19__VDEC_DEBUG_4 = IOMUX_PAD(0x0464, 0x011C, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA19__MMDC_DEBUG_24 = IOMUX_PAD(0x0464, 0x011C, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 = IOMUX_PAD(0x0468, 0x0120, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA20__WEIM_ADDR_20 = IOMUX_PAD(0x0468, 0x0120, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA20__PWM8_OUT = IOMUX_PAD(0x0468, 0x0120, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA20__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x0468, 0x0120, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA20__CSI1_DATA_13 = IOMUX_PAD(0x0468, 0x0120, 4, 0x06D0, 0, 0), + MX6_PAD_LCD1_DATA20__GPIO3_IO_21 = IOMUX_PAD(0x0468, 0x0120, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA20__SRC_BT_CFG_28 = IOMUX_PAD(0x0468, 0x0120, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA20__SIM_M_HRESP = IOMUX_PAD(0x0468, 0x0120, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA20__VDEC_DEBUG_5 = IOMUX_PAD(0x0468, 0x0120, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA20__MMDC_DEBUG_25 = IOMUX_PAD(0x0468, 0x0120, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 = IOMUX_PAD(0x046C, 0x0124, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA21__WEIM_ADDR_21 = IOMUX_PAD(0x046C, 0x0124, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA21__PWM7_OUT = IOMUX_PAD(0x046C, 0x0124, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA21__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x046C, 0x0124, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA21__CSI1_DATA_12 = IOMUX_PAD(0x046C, 0x0124, 4, 0x06CC, 0, 0), + MX6_PAD_LCD1_DATA21__GPIO3_IO_22 = IOMUX_PAD(0x046C, 0x0124, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA21__SRC_BT_CFG_29 = IOMUX_PAD(0x046C, 0x0124, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA21__SIM_M_HSIZE_0 = IOMUX_PAD(0x046C, 0x0124, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA21__VDEC_DEBUG_6 = IOMUX_PAD(0x046C, 0x0124, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA21__MMDC_DEBUG_26 = IOMUX_PAD(0x046C, 0x0124, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 = IOMUX_PAD(0x0470, 0x0128, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA22__WEIM_ADDR_22 = IOMUX_PAD(0x0470, 0x0128, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA22__PWM6_OUT = IOMUX_PAD(0x0470, 0x0128, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA22__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x0470, 0x0128, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA22__CSI1_DATA_11 = IOMUX_PAD(0x0470, 0x0128, 4, 0x06C8, 0, 0), + MX6_PAD_LCD1_DATA22__GPIO3_IO_23 = IOMUX_PAD(0x0470, 0x0128, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA22__SRC_BT_CFG_30 = IOMUX_PAD(0x0470, 0x0128, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA22__SIM_M_HSIZE_1 = IOMUX_PAD(0x0470, 0x0128, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA22__VDEC_DEBUG_7 = IOMUX_PAD(0x0470, 0x0128, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA22__MMDC_DEBUG_27 = IOMUX_PAD(0x0470, 0x0128, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 = IOMUX_PAD(0x0474, 0x012C, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA23__WEIM_ADDR_23 = IOMUX_PAD(0x0474, 0x012C, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA23__PWM5_OUT = IOMUX_PAD(0x0474, 0x012C, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA23__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x0474, 0x012C, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA23__CSI1_DATA_10 = IOMUX_PAD(0x0474, 0x012C, 4, 0x06FC, 0, 0), + MX6_PAD_LCD1_DATA23__GPIO3_IO_24 = IOMUX_PAD(0x0474, 0x012C, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA23__SRC_BT_CFG_31 = IOMUX_PAD(0x0474, 0x012C, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA23__SIM_M_HSIZE_2 = IOMUX_PAD(0x0474, 0x012C, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA23__VDEC_DEBUG_8 = IOMUX_PAD(0x0474, 0x012C, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA23__MMDC_DEBUG_28 = IOMUX_PAD(0x0474, 0x012C, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE = IOMUX_PAD(0x0478, 0x0130, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_ENABLE__LCDIF1_RD_E = IOMUX_PAD(0x0478, 0x0130, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0478, 0x0130, 2, 0x063C, 1, 0), + MX6_PAD_LCD1_ENABLE__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x0478, 0x0130, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_ENABLE__CSI1_DATA_17 = IOMUX_PAD(0x0478, 0x0130, 4, 0x06E0, 0, 0), + MX6_PAD_LCD1_ENABLE__GPIO3_IO_25 = IOMUX_PAD(0x0478, 0x0130, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_ENABLE__USDHC1_CD_B = IOMUX_PAD(0x0478, 0x0130, 6, 0x0864, 0, 0), + MX6_PAD_LCD1_ENABLE__SIM_M_HADDR_17 = IOMUX_PAD(0x0478, 0x0130, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_ENABLE__VADC_TEST_1 = IOMUX_PAD(0x0478, 0x0130, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_ENABLE__MMDC_DEBUG_1 = IOMUX_PAD(0x0478, 0x0130, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC = IOMUX_PAD(0x047C, 0x0134, 0, 0x07E0, 0, 0), + MX6_PAD_LCD1_HSYNC__LCDIF1_RS = IOMUX_PAD(0x047C, 0x0134, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD = IOMUX_PAD(0x047C, 0x0134, 2, 0x0630, 1, 0), + MX6_PAD_LCD1_HSYNC__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x047C, 0x0134, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_HSYNC__CSI1_DATA_18 = IOMUX_PAD(0x047C, 0x0134, 4, 0x06E4, 0, 0), + MX6_PAD_LCD1_HSYNC__GPIO3_IO_26 = IOMUX_PAD(0x047C, 0x0134, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_HSYNC__USDHC2_WP = IOMUX_PAD(0x047C, 0x0134, 6, 0x0870, 0, 0), + MX6_PAD_LCD1_HSYNC__SIM_M_HADDR_18 = IOMUX_PAD(0x047C, 0x0134, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_HSYNC__VADC_TEST_2 = IOMUX_PAD(0x047C, 0x0134, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_HSYNC__MMDC_DEBUG_2 = IOMUX_PAD(0x047C, 0x0134, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_RESET__LCDIF1_RESET = IOMUX_PAD(0x0480, 0x0138, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_RESET__LCDIF1_CS = IOMUX_PAD(0x0480, 0x0138, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_RESET__AUDMUX_AUD3_RXD = IOMUX_PAD(0x0480, 0x0138, 2, 0x062C, 1, 0), + MX6_PAD_LCD1_RESET__KITTEN_EVENTI = IOMUX_PAD(0x0480, 0x0138, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_RESET__M4_EVENTI = IOMUX_PAD(0x0480, 0x0138, 4, 0x0000, 0, 0), + MX6_PAD_LCD1_RESET__GPIO3_IO_27 = IOMUX_PAD(0x0480, 0x0138, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_RESET__CCM_PMIC_RDY = IOMUX_PAD(0x0480, 0x0138, 6, 0x069C, 0, 0), + MX6_PAD_LCD1_RESET__SIM_M_HADDR_20 = IOMUX_PAD(0x0480, 0x0138, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_RESET__VADC_TEST_4 = IOMUX_PAD(0x0480, 0x0138, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_RESET__MMDC_DEBUG_4 = IOMUX_PAD(0x0480, 0x0138, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC = IOMUX_PAD(0x0484, 0x013C, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_VSYNC__LCDIF1_BUSY = IOMUX_PAD(0x0484, 0x013C, 1, 0x07E0, 1, 0), + MX6_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x0484, 0x013C, 2, 0x0640, 1, 0), + MX6_PAD_LCD1_VSYNC__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x0484, 0x013C, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_VSYNC__CSI1_DATA_19 = IOMUX_PAD(0x0484, 0x013C, 4, 0x06E8, 0, 0), + MX6_PAD_LCD1_VSYNC__GPIO3_IO_28 = IOMUX_PAD(0x0484, 0x013C, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_VSYNC__USDHC2_CD_B = IOMUX_PAD(0x0484, 0x013C, 6, 0x086C, 0, 0), + MX6_PAD_LCD1_VSYNC__SIM_M_HADDR_19 = IOMUX_PAD(0x0484, 0x013C, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_VSYNC__VADC_TEST_3 = IOMUX_PAD(0x0484, 0x013C, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_VSYNC__MMDC_DEBUG_3 = IOMUX_PAD(0x0484, 0x013C, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x0488, 0x0140, 0, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__I2C3_SDA = IOMUX_PAD(0x0488, 0x0140, IOMUX_CONFIG_SION | 1, 0x07BC, 0, 0), + MX6_PAD_NAND_ALE__QSPI2_A_SS0_B = IOMUX_PAD(0x0488, 0x0140, 2, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__ECSPI2_SS0 = IOMUX_PAD(0x0488, 0x0140, 3, 0x072C, 0, 0), + MX6_PAD_NAND_ALE__ESAI_TX3_RX2 = IOMUX_PAD(0x0488, 0x0140, 4, 0x079C, 0, 0), + MX6_PAD_NAND_ALE__GPIO4_IO_0 = IOMUX_PAD(0x0488, 0x0140, 5, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__WEIM_CS0_B = IOMUX_PAD(0x0488, 0x0140, 6, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__TPSMP_HDATA_0 = IOMUX_PAD(0x0488, 0x0140, 7, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__ANATOP_USBPHY1_TSTI_TX_EN = IOMUX_PAD(0x0488, 0x0140, 8, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0488, 0x0140, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x048C, 0x0144, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__USDHC2_VSELECT = IOMUX_PAD(0x048C, 0x0144, 1, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 = IOMUX_PAD(0x048C, 0x0144, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__AUDMUX_AUD4_TXC = IOMUX_PAD(0x048C, 0x0144, 3, 0x0654, 0, 0), + MX6_PAD_NAND_CE0_B__ESAI_TX_CLK = IOMUX_PAD(0x048C, 0x0144, 4, 0x078C, 0, 0), + MX6_PAD_NAND_CE0_B__GPIO4_IO_1 = IOMUX_PAD(0x048C, 0x0144, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__WEIM_LBA_B = IOMUX_PAD(0x048C, 0x0144, 6, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__TPSMP_HDATA_3 = IOMUX_PAD(0x048C, 0x0144, 7, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__ANATOP_USBPHY1_TSTI_TX_HIZ = IOMUX_PAD(0x048C, 0x0144, 8, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x048C, 0x0144, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0490, 0x0148, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__USDHC3_RESET_B = IOMUX_PAD(0x0490, 0x0148, 1, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 = IOMUX_PAD(0x0490, 0x0148, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__AUDMUX_AUD4_TXD = IOMUX_PAD(0x0490, 0x0148, 3, 0x0648, 0, 0), + MX6_PAD_NAND_CE1_B__ESAI_TX0 = IOMUX_PAD(0x0490, 0x0148, 4, 0x0790, 0, 0), + MX6_PAD_NAND_CE1_B__GPIO4_IO_2 = IOMUX_PAD(0x0490, 0x0148, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__WEIM_OE = IOMUX_PAD(0x0490, 0x0148, 6, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__TPSMP_HDATA_4 = IOMUX_PAD(0x0490, 0x0148, 7, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__ANATOP_USBPHY1_TSTI_TX_LS_MODE = IOMUX_PAD(0x0490, 0x0148, 8, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0490, 0x0148, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0494, 0x014C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__I2C3_SCL = IOMUX_PAD(0x0494, 0x014C, IOMUX_CONFIG_SION | 1, 0x07B8, 0, 0), + MX6_PAD_NAND_CLE__QSPI2_A_SCLK = IOMUX_PAD(0x0494, 0x014C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__ECSPI2_SCLK = IOMUX_PAD(0x0494, 0x014C, 3, 0x0720, 0, 0), + MX6_PAD_NAND_CLE__ESAI_TX2_RX3 = IOMUX_PAD(0x0494, 0x014C, 4, 0x0798, 0, 0), + MX6_PAD_NAND_CLE__GPIO4_IO_3 = IOMUX_PAD(0x0494, 0x014C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__WEIM_BCLK = IOMUX_PAD(0x0494, 0x014C, 6, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__TPSMP_CLK = IOMUX_PAD(0x0494, 0x014C, 7, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__ANATOP_USBPHY1_TSTI_TX_DP = IOMUX_PAD(0x0494, 0x014C, 8, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0494, 0x014C, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0498, 0x0150, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__USDHC1_DATA4 = IOMUX_PAD(0x0498, 0x0150, 1, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 = IOMUX_PAD(0x0498, 0x0150, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__ECSPI5_MISO = IOMUX_PAD(0x0498, 0x0150, 3, 0x0754, 0, 0), + MX6_PAD_NAND_DATA00__ESAI_RX_CLK = IOMUX_PAD(0x0498, 0x0150, 4, 0x0788, 0, 0), + MX6_PAD_NAND_DATA00__GPIO4_IO_4 = IOMUX_PAD(0x0498, 0x0150, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__WEIM_AD_0 = IOMUX_PAD(0x0498, 0x0150, 6, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__TPSMP_HDATA_7 = IOMUX_PAD(0x0498, 0x0150, 7, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__ANATOP_USBPHY1_TSTO_RX_DISCON_DET = IOMUX_PAD(0x0498, 0x0150, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__SDMA_DEBUG_EVT_CHN_LINES_5 = IOMUX_PAD(0x0498, 0x0150, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x049C, 0x0154, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__USDHC1_DATA5 = IOMUX_PAD(0x049C, 0x0154, 1, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 = IOMUX_PAD(0x049C, 0x0154, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__ECSPI5_MOSI = IOMUX_PAD(0x049C, 0x0154, 3, 0x0758, 0, 0), + MX6_PAD_NAND_DATA01__ESAI_RX_FS = IOMUX_PAD(0x049C, 0x0154, 4, 0x0778, 0, 0), + MX6_PAD_NAND_DATA01__GPIO4_IO_5 = IOMUX_PAD(0x049C, 0x0154, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__WEIM_AD_1 = IOMUX_PAD(0x049C, 0x0154, 6, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__TPSMP_HDATA_8 = IOMUX_PAD(0x049C, 0x0154, 7, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__ANATOP_USBPHY1_TSTO_RX_HS_RXD = IOMUX_PAD(0x049C, 0x0154, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__SDMA_DEBUG_EVT_CHN_LINES_4 = IOMUX_PAD(0x049C, 0x0154, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x04A0, 0x0158, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__USDHC1_DATA6 = IOMUX_PAD(0x04A0, 0x0158, 1, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__QSPI2_B_SCLK = IOMUX_PAD(0x04A0, 0x0158, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__ECSPI5_SCLK = IOMUX_PAD(0x04A0, 0x0158, 3, 0x0750, 0, 0), + MX6_PAD_NAND_DATA02__ESAI_TX_HF_CLK = IOMUX_PAD(0x04A0, 0x0158, 4, 0x0784, 0, 0), + MX6_PAD_NAND_DATA02__GPIO4_IO_6 = IOMUX_PAD(0x04A0, 0x0158, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__WEIM_AD_2 = IOMUX_PAD(0x04A0, 0x0158, 6, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__TPSMP_HDATA_9 = IOMUX_PAD(0x04A0, 0x0158, 7, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV = IOMUX_PAD(0x04A0, 0x0158, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__SDMA_DEBUG_EVT_CHN_LINES_3 = IOMUX_PAD(0x04A0, 0x0158, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x04A4, 0x015C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__USDHC1_DATA7 = IOMUX_PAD(0x04A4, 0x015C, 1, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B = IOMUX_PAD(0x04A4, 0x015C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__ECSPI5_SS0 = IOMUX_PAD(0x04A4, 0x015C, 3, 0x075C, 0, 0), + MX6_PAD_NAND_DATA03__ESAI_RX_HF_CLK = IOMUX_PAD(0x04A4, 0x015C, 4, 0x0780, 0, 0), + MX6_PAD_NAND_DATA03__GPIO4_IO_7 = IOMUX_PAD(0x04A4, 0x015C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__WEIM_AD_3 = IOMUX_PAD(0x04A4, 0x015C, 6, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__TPSMP_HDATA_10 = IOMUX_PAD(0x04A4, 0x015C, 7, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__ANATOP_USBPHY1_TSTO_RX_SQUELCH = IOMUX_PAD(0x04A4, 0x015C, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__SDMA_DEBUG_EVT_CHN_LINES_6 = IOMUX_PAD(0x04A4, 0x015C, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x04A8, 0x0160, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x04A8, 0x0160, 1, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__QSPI2_B_SS1_B = IOMUX_PAD(0x04A8, 0x0160, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__UART3_RTS_B = IOMUX_PAD(0x04A8, 0x0160, 3, 0x083C, 0, 0), + MX6_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x04A8, 0x0160, 4, 0x0650, 0, 0), + MX6_PAD_NAND_DATA04__GPIO4_IO_8 = IOMUX_PAD(0x04A8, 0x0160, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__WEIM_AD_4 = IOMUX_PAD(0x04A8, 0x0160, 6, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__TPSMP_HDATA_11 = IOMUX_PAD(0x04A8, 0x0160, 7, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__ANATOP_USBPHY2_TSTO_RX_SQUELCH = IOMUX_PAD(0x04A8, 0x0160, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__SDMA_DEBUG_CORE_STATE_0 = IOMUX_PAD(0x04A8, 0x0160, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x04AC, 0x0164, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x04AC, 0x0164, 1, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__QSPI2_B_DQS = IOMUX_PAD(0x04AC, 0x0164, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__UART3_CTS_B = IOMUX_PAD(0x04AC, 0x0164, 3, 0x083C, 1, 0), + MX6_PAD_NAND_DATA05__AUDMUX_AUD4_RXC = IOMUX_PAD(0x04AC, 0x0164, 4, 0x064C, 0, 0), + MX6_PAD_NAND_DATA05__GPIO4_IO_9 = IOMUX_PAD(0x04AC, 0x0164, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__WEIM_AD_5 = IOMUX_PAD(0x04AC, 0x0164, 6, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__TPSMP_HDATA_12 = IOMUX_PAD(0x04AC, 0x0164, 7, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__ANATOP_USBPHY2_TSTO_RX_DISCON_DET = IOMUX_PAD(0x04AC, 0x0164, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__SDMA_DEBUG_CORE_STATE_1 = IOMUX_PAD(0x04AC, 0x0164, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x04B0, 0x0168, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x04B0, 0x0168, 1, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__QSPI2_A_SS1_B = IOMUX_PAD(0x04B0, 0x0168, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__UART3_RX = IOMUX_PAD(0x04B0, 0x0168, 3, 0x0840, 0, 0), + MX6_PAD_NAND_DATA06__PWM3_OUT = IOMUX_PAD(0x04B0, 0x0168, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__GPIO4_IO_10 = IOMUX_PAD(0x04B0, 0x0168, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__WEIM_AD_6 = IOMUX_PAD(0x04B0, 0x0168, 6, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__TPSMP_HDATA_13 = IOMUX_PAD(0x04B0, 0x0168, 7, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__ANATOP_USBPHY2_TSTO_RX_FS_RXD = IOMUX_PAD(0x04B0, 0x0168, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__SDMA_DEBUG_CORE_STATE_2 = IOMUX_PAD(0x04B0, 0x0168, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x04B4, 0x016C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x04B4, 0x016C, 1, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__QSPI2_A_DQS = IOMUX_PAD(0x04B4, 0x016C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__UART3_TX = IOMUX_PAD(0x04B4, 0x016C, 3, 0x0840, 1, 0), + MX6_PAD_NAND_DATA07__PWM4_OUT = IOMUX_PAD(0x04B4, 0x016C, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__GPIO4_IO_11 = IOMUX_PAD(0x04B4, 0x016C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__WEIM_AD_7 = IOMUX_PAD(0x04B4, 0x016C, 6, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__TPSMP_HDATA_14 = IOMUX_PAD(0x04B4, 0x016C, 7, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__ANATOP_USBPHY1_TSTO_RX_FS_RXD = IOMUX_PAD(0x04B4, 0x016C, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__SDMA_DEBUG_CORE_STATE_3 = IOMUX_PAD(0x04B4, 0x016C, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x04B8, 0x0170, 0, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__USDHC2_RESET_B = IOMUX_PAD(0x04B8, 0x0170, 1, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 = IOMUX_PAD(0x04B8, 0x0170, 2, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x04B8, 0x0170, 3, 0x0658, 0, 0), + MX6_PAD_NAND_RE_B__ESAI_TX_FS = IOMUX_PAD(0x04B8, 0x0170, 4, 0x077C, 0, 0), + MX6_PAD_NAND_RE_B__GPIO4_IO_12 = IOMUX_PAD(0x04B8, 0x0170, 5, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__WEIM_RW = IOMUX_PAD(0x04B8, 0x0170, 6, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__TPSMP_HDATA_5 = IOMUX_PAD(0x04B8, 0x0170, 7, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__ANATOP_USBPHY2_TSTO_RX_HS_RXD = IOMUX_PAD(0x04B8, 0x0170, 8, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x04B8, 0x0170, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x04BC, 0x0174, 0, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__USDHC1_VSELECT = IOMUX_PAD(0x04BC, 0x0174, 1, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 = IOMUX_PAD(0x04BC, 0x0174, 2, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__ECSPI2_MISO = IOMUX_PAD(0x04BC, 0x0174, 3, 0x0724, 0, 0), + MX6_PAD_NAND_READY_B__ESAI_TX1 = IOMUX_PAD(0x04BC, 0x0174, 4, 0x0794, 0, 0), + MX6_PAD_NAND_READY_B__GPIO4_IO_13 = IOMUX_PAD(0x04BC, 0x0174, 5, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__WEIM_EB_B_1 = IOMUX_PAD(0x04BC, 0x0174, 6, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__TPSMP_HDATA_2 = IOMUX_PAD(0x04BC, 0x0174, 7, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__ANATOP_USBPHY1_TSTI_TX_DN = IOMUX_PAD(0x04BC, 0x0174, 8, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x04BC, 0x0174, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x04C0, 0x0178, 0, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__USDHC4_VSELECT = IOMUX_PAD(0x04C0, 0x0178, 1, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 = IOMUX_PAD(0x04C0, 0x0178, 2, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__AUDMUX_AUD4_RXD = IOMUX_PAD(0x04C0, 0x0178, 3, 0x0644, 0, 0), + MX6_PAD_NAND_WE_B__ESAI_TX5_RX0 = IOMUX_PAD(0x04C0, 0x0178, 4, 0x07A4, 0, 0), + MX6_PAD_NAND_WE_B__GPIO4_IO_14 = IOMUX_PAD(0x04C0, 0x0178, 5, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__WEIM_WAIT = IOMUX_PAD(0x04C0, 0x0178, 6, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__TPSMP_HDATA_6 = IOMUX_PAD(0x04C0, 0x0178, 7, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV = IOMUX_PAD(0x04C0, 0x0178, 8, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x04C0, 0x0178, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x04C4, 0x017C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__USDHC1_RESET_B = IOMUX_PAD(0x04C4, 0x017C, 1, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 = IOMUX_PAD(0x04C4, 0x017C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x017C, 3, 0x0728, 0, 0), + MX6_PAD_NAND_WP_B__ESAI_TX4_RX1 = IOMUX_PAD(0x04C4, 0x017C, 4, 0x07A0, 0, 0), + MX6_PAD_NAND_WP_B__GPIO4_IO_15 = IOMUX_PAD(0x04C4, 0x017C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__WEIM_EB_B_0 = IOMUX_PAD(0x04C4, 0x017C, 6, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__TPSMP_HDATA_1 = IOMUX_PAD(0x04C4, 0x017C, 7, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__ANATOP_USBPHY1_TSTI_TX_HS_MODE = IOMUX_PAD(0x04C4, 0x017C, 8, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x04C4, 0x017C, 9, 0x0000, 0, 0), + + MX6_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 = IOMUX_PAD(0x04C8, 0x0180, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA0__USB_OTG2_OC = IOMUX_PAD(0x04C8, 0x0180, 1, 0x085C, 2, 0), + MX6_PAD_QSPI1A_DATA0__ECSPI1_MOSI = IOMUX_PAD(0x04C8, 0x0180, 2, 0x0718, 1, 0), + MX6_PAD_QSPI1A_DATA0__ESAI_TX4_RX1 = IOMUX_PAD(0x04C8, 0x0180, 3, 0x07A0, 2, 0), + MX6_PAD_QSPI1A_DATA0__CSI1_DATA_14 = IOMUX_PAD(0x04C8, 0x0180, 4, 0x06D4, 1, 0), + MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 = IOMUX_PAD(0x04C8, 0x0180, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA0__WEIM_DATA_6 = IOMUX_PAD(0x04C8, 0x0180, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA0__SIM_M_HADDR_3 = IOMUX_PAD(0x04C8, 0x0180, 7, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA0__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x04C8, 0x0180, 9, 0x0000, 0, 0), + + MX6_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 = IOMUX_PAD(0x04CC, 0x0184, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID = IOMUX_PAD(0x04CC, 0x0184, 1, 0x0624, 2, 0), + MX6_PAD_QSPI1A_DATA1__ECSPI1_MISO = IOMUX_PAD(0x04CC, 0x0184, 2, 0x0714, 1, 0), + MX6_PAD_QSPI1A_DATA1__ESAI_TX1 = IOMUX_PAD(0x04CC, 0x0184, 3, 0x0794, 2, 0), + MX6_PAD_QSPI1A_DATA1__CSI1_DATA_13 = IOMUX_PAD(0x04CC, 0x0184, 4, 0x06D0, 1, 0), + MX6_PAD_QSPI1A_DATA1__GPIO4_IO_17 = IOMUX_PAD(0x04CC, 0x0184, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA1__WEIM_DATA_5 = IOMUX_PAD(0x04CC, 0x0184, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA1__SIM_M_HADDR_4 = IOMUX_PAD(0x04CC, 0x0184, 7, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA1__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x04CC, 0x0184, 9, 0x0000, 0, 0), + + MX6_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 = IOMUX_PAD(0x04D0, 0x0188, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA2__USB_OTG1_PWR = IOMUX_PAD(0x04D0, 0x0188, 1, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA2__ECSPI5_SS1 = IOMUX_PAD(0x04D0, 0x0188, 2, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA2__ESAI_TX_CLK = IOMUX_PAD(0x04D0, 0x0188, 3, 0x078C, 2, 0), + MX6_PAD_QSPI1A_DATA2__CSI1_DATA_12 = IOMUX_PAD(0x04D0, 0x0188, 4, 0x06CC, 1, 0), + MX6_PAD_QSPI1A_DATA2__GPIO4_IO_18 = IOMUX_PAD(0x04D0, 0x0188, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA2__WEIM_DATA_4 = IOMUX_PAD(0x04D0, 0x0188, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA2__SIM_M_HADDR_6 = IOMUX_PAD(0x04D0, 0x0188, 7, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA2__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x04D0, 0x0188, 9, 0x0000, 0, 0), + + MX6_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 = IOMUX_PAD(0x04D4, 0x018C, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA3__USB_OTG1_OC = IOMUX_PAD(0x04D4, 0x018C, 1, 0x0860, 2, 0), + MX6_PAD_QSPI1A_DATA3__ECSPI5_SS2 = IOMUX_PAD(0x04D4, 0x018C, 2, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA3__ESAI_TX0 = IOMUX_PAD(0x04D4, 0x018C, 3, 0x0790, 2, 0), + MX6_PAD_QSPI1A_DATA3__CSI1_DATA_11 = IOMUX_PAD(0x04D4, 0x018C, 4, 0x06C8, 1, 0), + MX6_PAD_QSPI1A_DATA3__GPIO4_IO_19 = IOMUX_PAD(0x04D4, 0x018C, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA3__WEIM_DATA_3 = IOMUX_PAD(0x04D4, 0x018C, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA3__SIM_M_HADDR_7 = IOMUX_PAD(0x04D4, 0x018C, 7, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA3__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x04D4, 0x018C, 9, 0x0000, 0, 0), + + MX6_PAD_QSPI1A_DQS__QSPI1_A_DQS = IOMUX_PAD(0x04D8, 0x0190, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DQS__CAN2_TX = IOMUX_PAD(0x04D8, 0x0190, 1, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DQS__CANFD_TX2 = IOMUX_PAD(0x04D8, 0x0190, 2, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DQS__ECSPI5_MOSI = IOMUX_PAD(0x04D8, 0x0190, 3, 0x0758, 1, 0), + MX6_PAD_QSPI1A_DQS__CSI1_DATA_15 = IOMUX_PAD(0x04D8, 0x0190, 4, 0x06D8, 1, 0), + MX6_PAD_QSPI1A_DQS__GPIO4_IO_20 = IOMUX_PAD(0x04D8, 0x0190, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DQS__WEIM_DATA_7 = IOMUX_PAD(0x04D8, 0x0190, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DQS__SIM_M_HADDR_13 = IOMUX_PAD(0x04D8, 0x0190, 7, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DQS__SDMA_DEBUG_BUS_DEVICE_4 = IOMUX_PAD(0x04D8, 0x0190, 9, 0x0000, 0, 0), + + MX6_PAD_QSPI1A_SCLK__QSPI1_A_SCLK = IOMUX_PAD(0x04DC, 0x0194, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID = IOMUX_PAD(0x04DC, 0x0194, 1, 0x0628, 2, 0), + MX6_PAD_QSPI1A_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x04DC, 0x0194, 2, 0x0710, 1, 0), + MX6_PAD_QSPI1A_SCLK__ESAI_TX2_RX3 = IOMUX_PAD(0x04DC, 0x0194, 3, 0x0798, 2, 0), + MX6_PAD_QSPI1A_SCLK__CSI1_DATA_1 = IOMUX_PAD(0x04DC, 0x0194, 4, 0x06A4, 1, 0), + MX6_PAD_QSPI1A_SCLK__GPIO4_IO_21 = IOMUX_PAD(0x04DC, 0x0194, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SCLK__WEIM_DATA_0 = IOMUX_PAD(0x04DC, 0x0194, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SCLK__SIM_M_HADDR_0 = IOMUX_PAD(0x04DC, 0x0194, 7, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SCLK__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x04DC, 0x0194, 9, 0x0000, 0, 0), + + MX6_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B = IOMUX_PAD(0x04E0, 0x0198, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SS0_B__USB_OTG2_PWR = IOMUX_PAD(0x04E0, 0x0198, 1, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SS0_B__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x0198, 2, 0x071C, 1, 0), + MX6_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2 = IOMUX_PAD(0x04E0, 0x0198, 3, 0x079C, 2, 0), + MX6_PAD_QSPI1A_SS0_B__CSI1_DATA_0 = IOMUX_PAD(0x04E0, 0x0198, 4, 0x06A0, 1, 0), + MX6_PAD_QSPI1A_SS0_B__GPIO4_IO_22 = IOMUX_PAD(0x04E0, 0x0198, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SS0_B__WEIM_DATA_1 = IOMUX_PAD(0x04E0, 0x0198, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SS0_B__SIM_M_HADDR_1 = IOMUX_PAD(0x04E0, 0x0198, 7, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SS0_B__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x04E0, 0x0198, 9, 0x0000, 0, 0), + + MX6_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B = IOMUX_PAD(0x04E4, 0x019C, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SS1_B__CAN1_RX = IOMUX_PAD(0x04E4, 0x019C, 1, 0x068C, 2, 0), + MX6_PAD_QSPI1A_SS1_B__CANFD_RX1 = IOMUX_PAD(0x04E4, 0x019C, 2, 0x0694, 2, 0), + MX6_PAD_QSPI1A_SS1_B__ECSPI5_MISO = IOMUX_PAD(0x04E4, 0x019C, 3, 0x0754, 1, 0), + MX6_PAD_QSPI1A_SS1_B__CSI1_DATA_10 = IOMUX_PAD(0x04E4, 0x019C, 4, 0x06FC, 1, 0), + MX6_PAD_QSPI1A_SS1_B__GPIO4_IO_23 = IOMUX_PAD(0x04E4, 0x019C, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SS1_B__WEIM_DATA_2 = IOMUX_PAD(0x04E4, 0x019C, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 = IOMUX_PAD(0x04E4, 0x019C, 7, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x04E4, 0x019C, 9, 0x0000, 0, 0), + + MX6_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 = IOMUX_PAD(0x04E8, 0x01A0, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA0__UART3_CTS_B = IOMUX_PAD(0x04E8, 0x01A0, 1, 0x083C, 4, 0), + MX6_PAD_QSPI1B_DATA0__ECSPI3_MOSI = IOMUX_PAD(0x04E8, 0x01A0, 2, 0x0738, 1, 0), + MX6_PAD_QSPI1B_DATA0__ESAI_RX_FS = IOMUX_PAD(0x04E8, 0x01A0, 3, 0x0778, 2, 0), + MX6_PAD_QSPI1B_DATA0__CSI1_DATA_22 = IOMUX_PAD(0x04E8, 0x01A0, 4, 0x06F4, 1, 0), + MX6_PAD_QSPI1B_DATA0__GPIO4_IO_24 = IOMUX_PAD(0x04E8, 0x01A0, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA0__WEIM_DATA_14 = IOMUX_PAD(0x04E8, 0x01A0, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 = IOMUX_PAD(0x04E8, 0x01A0, 7, 0x0000, 0, 0), + + MX6_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 = IOMUX_PAD(0x04EC, 0x01A4, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA1__UART3_RTS_B = IOMUX_PAD(0x04EC, 0x01A4, 1, 0x083C, 5, 0), + MX6_PAD_QSPI1B_DATA1__ECSPI3_MISO = IOMUX_PAD(0x04EC, 0x01A4, 2, 0x0734, 1, 0), + MX6_PAD_QSPI1B_DATA1__ESAI_RX_CLK = IOMUX_PAD(0x04EC, 0x01A4, 3, 0x0788, 2, 0), + MX6_PAD_QSPI1B_DATA1__CSI1_DATA_21 = IOMUX_PAD(0x04EC, 0x01A4, 4, 0x06F0, 1, 0), + MX6_PAD_QSPI1B_DATA1__GPIO4_IO_25 = IOMUX_PAD(0x04EC, 0x01A4, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA1__WEIM_DATA_13 = IOMUX_PAD(0x04EC, 0x01A4, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA1__SIM_M_HADDR_8 = IOMUX_PAD(0x04EC, 0x01A4, 7, 0x0000, 0, 0), + + MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 = IOMUX_PAD(0x04F0, 0x01A8, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA2__I2C2_SDA = IOMUX_PAD(0x04F0, 0x01A8, IOMUX_CONFIG_SION | 1, 0x07B4, 2, 0), + MX6_PAD_QSPI1B_DATA2__ECSPI5_RDY = IOMUX_PAD(0x04F0, 0x01A8, 2, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 = IOMUX_PAD(0x04F0, 0x01A8, 3, 0x07A4, 2, 0), + MX6_PAD_QSPI1B_DATA2__CSI1_DATA_20 = IOMUX_PAD(0x04F0, 0x01A8, 4, 0x06EC, 1, 0), + MX6_PAD_QSPI1B_DATA2__GPIO4_IO_26 = IOMUX_PAD(0x04F0, 0x01A8, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA2__WEIM_DATA_12 = IOMUX_PAD(0x04F0, 0x01A8, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA2__SIM_M_HADDR_5 = IOMUX_PAD(0x04F0, 0x01A8, 7, 0x0000, 0, 0), + + MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 = IOMUX_PAD(0x04F4, 0x01AC, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA3__I2C2_SCL = IOMUX_PAD(0x04F4, 0x01AC, IOMUX_CONFIG_SION | 1, 0x07B0, 2, 0), + MX6_PAD_QSPI1B_DATA3__ECSPI5_SS3 = IOMUX_PAD(0x04F4, 0x01AC, 2, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA3__ESAI_TX_FS = IOMUX_PAD(0x04F4, 0x01AC, 3, 0x077C, 2, 0), + MX6_PAD_QSPI1B_DATA3__CSI1_DATA_19 = IOMUX_PAD(0x04F4, 0x01AC, 4, 0x06E8, 1, 0), + MX6_PAD_QSPI1B_DATA3__GPIO4_IO_27 = IOMUX_PAD(0x04F4, 0x01AC, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA3__WEIM_DATA_11 = IOMUX_PAD(0x04F4, 0x01AC, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA3__SIM_M_HADDR_2 = IOMUX_PAD(0x04F4, 0x01AC, 7, 0x0000, 0, 0), + + MX6_PAD_QSPI1B_DQS__QSPI1_B_DQS = IOMUX_PAD(0x04F8, 0x01B0, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DQS__CAN1_TX = IOMUX_PAD(0x04F8, 0x01B0, 1, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DQS__CANFD_TX1 = IOMUX_PAD(0x04F8, 0x01B0, 2, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DQS__ECSPI5_SS0 = IOMUX_PAD(0x04F8, 0x01B0, 3, 0x075C, 1, 0), + MX6_PAD_QSPI1B_DQS__CSI1_DATA_23 = IOMUX_PAD(0x04F8, 0x01B0, 4, 0x06F8, 1, 0), + MX6_PAD_QSPI1B_DQS__GPIO4_IO_28 = IOMUX_PAD(0x04F8, 0x01B0, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DQS__WEIM_DATA_15 = IOMUX_PAD(0x04F8, 0x01B0, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DQS__SIM_M_HADDR_15 = IOMUX_PAD(0x04F8, 0x01B0, 7, 0x0000, 0, 0), + + MX6_PAD_QSPI1B_SCLK__QSPI1_B_SCLK = IOMUX_PAD(0x04FC, 0x01B4, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1B_SCLK__UART3_RX = IOMUX_PAD(0x04FC, 0x01B4, 1, 0x0840, 4, 0), + MX6_PAD_QSPI1B_SCLK__ECSPI3_SCLK = IOMUX_PAD(0x04FC, 0x01B4, 2, 0x0730, 1, 0), + MX6_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK = IOMUX_PAD(0x04FC, 0x01B4, 3, 0x0780, 2, 0), + MX6_PAD_QSPI1B_SCLK__CSI1_DATA_16 = IOMUX_PAD(0x04FC, 0x01B4, 4, 0x06DC, 1, 0), + MX6_PAD_QSPI1B_SCLK__GPIO4_IO_29 = IOMUX_PAD(0x04FC, 0x01B4, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1B_SCLK__WEIM_DATA_8 = IOMUX_PAD(0x04FC, 0x01B4, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1B_SCLK__SIM_M_HADDR_11 = IOMUX_PAD(0x04FC, 0x01B4, 7, 0x0000, 0, 0), + + MX6_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B = IOMUX_PAD(0x0500, 0x01B8, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1B_SS0_B__UART3_TX = IOMUX_PAD(0x0500, 0x01B8, 1, 0x0840, 5, 0), + MX6_PAD_QSPI1B_SS0_B__ECSPI3_SS0 = IOMUX_PAD(0x0500, 0x01B8, 2, 0x073C, 1, 0), + MX6_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK = IOMUX_PAD(0x0500, 0x01B8, 3, 0x0784, 3, 0), + MX6_PAD_QSPI1B_SS0_B__CSI1_DATA_17 = IOMUX_PAD(0x0500, 0x01B8, 4, 0x06E0, 1, 0), + MX6_PAD_QSPI1B_SS0_B__GPIO4_IO_30 = IOMUX_PAD(0x0500, 0x01B8, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1B_SS0_B__WEIM_DATA_9 = IOMUX_PAD(0x0500, 0x01B8, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1B_SS0_B__SIM_M_HADDR_10 = IOMUX_PAD(0x0500, 0x01B8, 7, 0x0000, 0, 0), + + MX6_PAD_QSPI1B_SS1_B__QSPI1_B_SS1_B = IOMUX_PAD(0x0504, 0x01BC, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1B_SS1_B__CAN2_RX = IOMUX_PAD(0x0504, 0x01BC, 1, 0x0690, 2, 0), + MX6_PAD_QSPI1B_SS1_B__CANFD_RX2 = IOMUX_PAD(0x0504, 0x01BC, 2, 0x0698, 2, 0), + MX6_PAD_QSPI1B_SS1_B__ECSPI5_SCLK = IOMUX_PAD(0x0504, 0x01BC, 3, 0x0750, 1, 0), + MX6_PAD_QSPI1B_SS1_B__CSI1_DATA_18 = IOMUX_PAD(0x0504, 0x01BC, 4, 0x06E4, 1, 0), + MX6_PAD_QSPI1B_SS1_B__GPIO4_IO_31 = IOMUX_PAD(0x0504, 0x01BC, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1B_SS1_B__WEIM_DATA_10 = IOMUX_PAD(0x0504, 0x01BC, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1B_SS1_B__SIM_M_HADDR_14 = IOMUX_PAD(0x0504, 0x01BC, 7, 0x0000, 0, 0), + + MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 = IOMUX_PAD(0x0508, 0x01C0, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD0__GPIO5_IO_0 = IOMUX_PAD(0x0508, 0x01C0, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD0__CSI2_DATA_10 = IOMUX_PAD(0x0508, 0x01C0, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD0__ANATOP_TESTI_0 = IOMUX_PAD(0x0508, 0x01C0, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD0__RAWNAND_TESTER_TRIGGER = IOMUX_PAD(0x0508, 0x01C0, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD0__PCIE_CTRL_DEBUG_0 = IOMUX_PAD(0x0508, 0x01C0, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 = IOMUX_PAD(0x050C, 0x01C4, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD1__GPIO5_IO_1 = IOMUX_PAD(0x050C, 0x01C4, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD1__CSI2_DATA_11 = IOMUX_PAD(0x050C, 0x01C4, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD1__ANATOP_TESTI_1 = IOMUX_PAD(0x050C, 0x01C4, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD1__USDHC1_TESTER_TRIGGER = IOMUX_PAD(0x050C, 0x01C4, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD1__PCIE_CTRL_DEBUG_1 = IOMUX_PAD(0x050C, 0x01C4, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 = IOMUX_PAD(0x0510, 0x01C8, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD2__GPIO5_IO_2 = IOMUX_PAD(0x0510, 0x01C8, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD2__CSI2_DATA_12 = IOMUX_PAD(0x0510, 0x01C8, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD2__ANATOP_TESTI_2 = IOMUX_PAD(0x0510, 0x01C8, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD2__USDHC2_TESTER_TRIGGER = IOMUX_PAD(0x0510, 0x01C8, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD2__PCIE_CTRL_DEBUG_2 = IOMUX_PAD(0x0510, 0x01C8, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 = IOMUX_PAD(0x0514, 0x01CC, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD3__GPIO5_IO_3 = IOMUX_PAD(0x0514, 0x01CC, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD3__CSI2_DATA_13 = IOMUX_PAD(0x0514, 0x01CC, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD3__ANATOP_TESTI_3 = IOMUX_PAD(0x0514, 0x01CC, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD3__USDHC3_TESTER_TRIGGER = IOMUX_PAD(0x0514, 0x01CC, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD3__PCIE_CTRL_DEBUG_3 = IOMUX_PAD(0x0514, 0x01CC, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN = IOMUX_PAD(0x0518, 0x01D0, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_RX_CTL__GPIO5_IO_4 = IOMUX_PAD(0x0518, 0x01D0, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_RX_CTL__CSI2_DATA_14 = IOMUX_PAD(0x0518, 0x01D0, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_RX_CTL__ANATOP_TESTO_0 = IOMUX_PAD(0x0518, 0x01D0, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_RX_CTL__USDHC4_TESTER_TRIGGER = IOMUX_PAD(0x0518, 0x01D0, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_RX_CTL__PCIE_CTRL_DEBUG_4 = IOMUX_PAD(0x0518, 0x01D0, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_RXC__ENET1_RX_CLK = IOMUX_PAD(0x051C, 0x01D4, 0, 0x0768, 1, 0), + MX6_PAD_RGMII1_RXC__ENET1_RX_ER = IOMUX_PAD(0x051C, 0x01D4, 1, 0x0000, 0, 0), + MX6_PAD_RGMII1_RXC__GPIO5_IO_5 = IOMUX_PAD(0x051C, 0x01D4, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_RXC__CSI2_DATA_15 = IOMUX_PAD(0x051C, 0x01D4, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_RXC__ANATOP_TESTO_1 = IOMUX_PAD(0x051C, 0x01D4, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_RXC__ECSPI1_TESTER_TRIGGER = IOMUX_PAD(0x051C, 0x01D4, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_RXC__PCIE_CTRL_DEBUG_5 = IOMUX_PAD(0x051C, 0x01D4, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 = IOMUX_PAD(0x0520, 0x01D8, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD0__SAI2_RX_SYNC = IOMUX_PAD(0x0520, 0x01D8, 2, 0x0810, 1, 0), + MX6_PAD_RGMII1_TD0__GPIO5_IO_6 = IOMUX_PAD(0x0520, 0x01D8, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD0__CSI2_DATA_16 = IOMUX_PAD(0x0520, 0x01D8, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD0__ANATOP_TESTO_2 = IOMUX_PAD(0x0520, 0x01D8, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD0__ECSPI2_TESTER_TRIGGER = IOMUX_PAD(0x0520, 0x01D8, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD0__PCIE_CTRL_DEBUG_6 = IOMUX_PAD(0x0520, 0x01D8, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 = IOMUX_PAD(0x0524, 0x01DC, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD1__SAI2_RX_BCLK = IOMUX_PAD(0x0524, 0x01DC, 2, 0x0808, 1, 0), + MX6_PAD_RGMII1_TD1__GPIO5_IO_7 = IOMUX_PAD(0x0524, 0x01DC, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD1__CSI2_DATA_17 = IOMUX_PAD(0x0524, 0x01DC, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD1__ANATOP_TESTO_3 = IOMUX_PAD(0x0524, 0x01DC, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD1__ECSPI3_TESTER_TRIGGER = IOMUX_PAD(0x0524, 0x01DC, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD1__PCIE_CTRL_DEBUG_7 = IOMUX_PAD(0x0524, 0x01DC, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 = IOMUX_PAD(0x0528, 0x01E0, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD2__SAI2_TX_SYNC = IOMUX_PAD(0x0528, 0x01E0, 2, 0x0818, 1, 0), + MX6_PAD_RGMII1_TD2__GPIO5_IO_8 = IOMUX_PAD(0x0528, 0x01E0, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD2__CSI2_DATA_18 = IOMUX_PAD(0x0528, 0x01E0, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD2__ANATOP_TESTO_4 = IOMUX_PAD(0x0528, 0x01E0, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD2__ECSPI4_TESTER_TRIGGER = IOMUX_PAD(0x0528, 0x01E0, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD2__PCIE_CTRL_DEBUG_8 = IOMUX_PAD(0x0528, 0x01E0, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 = IOMUX_PAD(0x052C, 0x01E4, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD3__SAI2_TX_BCLK = IOMUX_PAD(0x052C, 0x01E4, 2, 0x0814, 1, 0), + MX6_PAD_RGMII1_TD3__GPIO5_IO_9 = IOMUX_PAD(0x052C, 0x01E4, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD3__CSI2_DATA_19 = IOMUX_PAD(0x052C, 0x01E4, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD3__ANATOP_TESTO_5 = IOMUX_PAD(0x052C, 0x01E4, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD3__ECSPI5_TESTER_TRIGGER = IOMUX_PAD(0x052C, 0x01E4, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD3__PCIE_CTRL_DEBUG_9 = IOMUX_PAD(0x052C, 0x01E4, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN = IOMUX_PAD(0x0530, 0x01E8, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0 = IOMUX_PAD(0x0530, 0x01E8, 2, 0x080C, 1, 0), + MX6_PAD_RGMII1_TX_CTL__GPIO5_IO_10 = IOMUX_PAD(0x0530, 0x01E8, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_TX_CTL__CSI2_DATA_0 = IOMUX_PAD(0x0530, 0x01E8, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_TX_CTL__ANATOP_TESTO_6 = IOMUX_PAD(0x0530, 0x01E8, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_TX_CTL__QSPI1_TESTER_TRIGGER = IOMUX_PAD(0x0530, 0x01E8, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_TX_CTL__PCIE_CTRL_DEBUG_10 = IOMUX_PAD(0x0530, 0x01E8, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC = IOMUX_PAD(0x0534, 0x01EC, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_TXC__ENET1_TX_ER = IOMUX_PAD(0x0534, 0x01EC, 1, 0x0000, 0, 0), + MX6_PAD_RGMII1_TXC__SAI2_TX_DATA_0 = IOMUX_PAD(0x0534, 0x01EC, 2, 0x0000, 0, 0), + MX6_PAD_RGMII1_TXC__GPIO5_IO_11 = IOMUX_PAD(0x0534, 0x01EC, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_TXC__CSI2_DATA_1 = IOMUX_PAD(0x0534, 0x01EC, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_TXC__ANATOP_TESTO_7 = IOMUX_PAD(0x0534, 0x01EC, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_TXC__QSPI2_TESTER_TRIGGER = IOMUX_PAD(0x0534, 0x01EC, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_TXC__PCIE_CTRL_DEBUG_11 = IOMUX_PAD(0x0534, 0x01EC, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 = IOMUX_PAD(0x0538, 0x01F0, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD0__PWM4_OUT = IOMUX_PAD(0x0538, 0x01F0, 2, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD0__GPIO5_IO_12 = IOMUX_PAD(0x0538, 0x01F0, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD0__CSI2_DATA_2 = IOMUX_PAD(0x0538, 0x01F0, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD0__ANATOP_TESTO_8 = IOMUX_PAD(0x0538, 0x01F0, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD0__VDEC_DEBUG_18 = IOMUX_PAD(0x0538, 0x01F0, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD0__PCIE_CTRL_DEBUG_12 = IOMUX_PAD(0x0538, 0x01F0, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 = IOMUX_PAD(0x053C, 0x01F4, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD1__PWM3_OUT = IOMUX_PAD(0x053C, 0x01F4, 2, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD1__GPIO5_IO_13 = IOMUX_PAD(0x053C, 0x01F4, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD1__CSI2_DATA_3 = IOMUX_PAD(0x053C, 0x01F4, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD1__ANATOP_TESTO_9 = IOMUX_PAD(0x053C, 0x01F4, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD1__VDEC_DEBUG_19 = IOMUX_PAD(0x053C, 0x01F4, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD1__PCIE_CTRL_DEBUG_13 = IOMUX_PAD(0x053C, 0x01F4, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 = IOMUX_PAD(0x0540, 0x01F8, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD2__PWM2_OUT = IOMUX_PAD(0x0540, 0x01F8, 2, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD2__GPIO5_IO_14 = IOMUX_PAD(0x0540, 0x01F8, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD2__CSI2_DATA_4 = IOMUX_PAD(0x0540, 0x01F8, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD2__ANATOP_TESTO_10 = IOMUX_PAD(0x0540, 0x01F8, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD2__VDEC_DEBUG_20 = IOMUX_PAD(0x0540, 0x01F8, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD2__PCIE_CTRL_DEBUG_14 = IOMUX_PAD(0x0540, 0x01F8, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 = IOMUX_PAD(0x0544, 0x01FC, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD3__PWM1_OUT = IOMUX_PAD(0x0544, 0x01FC, 2, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD3__GPIO5_IO_15 = IOMUX_PAD(0x0544, 0x01FC, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD3__CSI2_DATA_5 = IOMUX_PAD(0x0544, 0x01FC, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD3__ANATOP_TESTO_11 = IOMUX_PAD(0x0544, 0x01FC, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD3__VDEC_DEBUG_21 = IOMUX_PAD(0x0544, 0x01FC, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD3__PCIE_CTRL_DEBUG_15 = IOMUX_PAD(0x0544, 0x01FC, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN = IOMUX_PAD(0x0548, 0x0200, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_RX_CTL__GPIO5_IO_16 = IOMUX_PAD(0x0548, 0x0200, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_RX_CTL__CSI2_DATA_6 = IOMUX_PAD(0x0548, 0x0200, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_RX_CTL__ANATOP_TESTO_12 = IOMUX_PAD(0x0548, 0x0200, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_RX_CTL__VDEC_DEBUG_22 = IOMUX_PAD(0x0548, 0x0200, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_RX_CTL__PCIE_CTRL_DEBUG_16 = IOMUX_PAD(0x0548, 0x0200, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_RXC__ENET2_RX_CLK = IOMUX_PAD(0x054C, 0x0204, 0, 0x0774, 1, 0), + MX6_PAD_RGMII2_RXC__ENET2_RX_ER = IOMUX_PAD(0x054C, 0x0204, 1, 0x0000, 0, 0), + MX6_PAD_RGMII2_RXC__GPIO5_IO_17 = IOMUX_PAD(0x054C, 0x0204, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_RXC__CSI2_DATA_7 = IOMUX_PAD(0x054C, 0x0204, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_RXC__ANATOP_TESTO_13 = IOMUX_PAD(0x054C, 0x0204, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_RXC__VDEC_DEBUG_23 = IOMUX_PAD(0x054C, 0x0204, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_RXC__PCIE_CTRL_DEBUG_17 = IOMUX_PAD(0x054C, 0x0204, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 = IOMUX_PAD(0x0550, 0x0208, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD0__SAI1_RX_SYNC = IOMUX_PAD(0x0550, 0x0208, 2, 0x07FC, 1, 0), + MX6_PAD_RGMII2_TD0__PWM8_OUT = IOMUX_PAD(0x0550, 0x0208, 3, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD0__GPIO5_IO_18 = IOMUX_PAD(0x0550, 0x0208, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD0__CSI2_DATA_8 = IOMUX_PAD(0x0550, 0x0208, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD0__ANATOP_TESTO_14 = IOMUX_PAD(0x0550, 0x0208, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD0__VDEC_DEBUG_24 = IOMUX_PAD(0x0550, 0x0208, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD0__PCIE_CTRL_DEBUG_18 = IOMUX_PAD(0x0550, 0x0208, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 = IOMUX_PAD(0x0554, 0x020C, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD1__SAI1_RX_BCLK = IOMUX_PAD(0x0554, 0x020C, 2, 0x07F4, 1, 0), + MX6_PAD_RGMII2_TD1__PWM7_OUT = IOMUX_PAD(0x0554, 0x020C, 3, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD1__GPIO5_IO_19 = IOMUX_PAD(0x0554, 0x020C, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD1__CSI2_DATA_9 = IOMUX_PAD(0x0554, 0x020C, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD1__ANATOP_TESTO_15 = IOMUX_PAD(0x0554, 0x020C, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD1__VDEC_DEBUG_25 = IOMUX_PAD(0x0554, 0x020C, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD1__PCIE_CTRL_DEBUG_19 = IOMUX_PAD(0x0554, 0x020C, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 = IOMUX_PAD(0x0558, 0x0210, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD2__SAI1_TX_SYNC = IOMUX_PAD(0x0558, 0x0210, 2, 0x0804, 1, 0), + MX6_PAD_RGMII2_TD2__PWM6_OUT = IOMUX_PAD(0x0558, 0x0210, 3, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD2__GPIO5_IO_20 = IOMUX_PAD(0x0558, 0x0210, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD2__CSI2_VSYNC = IOMUX_PAD(0x0558, 0x0210, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD2__SJC_FAIL = IOMUX_PAD(0x0558, 0x0210, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD2__VDEC_DEBUG_26 = IOMUX_PAD(0x0558, 0x0210, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD2__PCIE_CTRL_DEBUG_20 = IOMUX_PAD(0x0558, 0x0210, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 = IOMUX_PAD(0x055C, 0x0214, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD3__SAI1_TX_BCLK = IOMUX_PAD(0x055C, 0x0214, 2, 0x0800, 1, 0), + MX6_PAD_RGMII2_TD3__PWM5_OUT = IOMUX_PAD(0x055C, 0x0214, 3, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD3__GPIO5_IO_21 = IOMUX_PAD(0x055C, 0x0214, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD3__CSI2_HSYNC = IOMUX_PAD(0x055C, 0x0214, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD3__SJC_JTAG_ACT = IOMUX_PAD(0x055C, 0x0214, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD3__VDEC_DEBUG_27 = IOMUX_PAD(0x055C, 0x0214, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD3__PCIE_CTRL_DEBUG_21 = IOMUX_PAD(0x055C, 0x0214, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN = IOMUX_PAD(0x0560, 0x0218, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0 = IOMUX_PAD(0x0560, 0x0218, 2, 0x07F8, 1, 0), + MX6_PAD_RGMII2_TX_CTL__GPIO5_IO_22 = IOMUX_PAD(0x0560, 0x0218, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_TX_CTL__CSI2_FIELD = IOMUX_PAD(0x0560, 0x0218, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_TX_CTL__SJC_DE_B = IOMUX_PAD(0x0560, 0x0218, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_TX_CTL__VDEC_DEBUG_28 = IOMUX_PAD(0x0560, 0x0218, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_TX_CTL__PCIE_CTRL_DEBUG_22 = IOMUX_PAD(0x0560, 0x0218, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC = IOMUX_PAD(0x0564, 0x021C, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_TXC__ENET2_TX_ER = IOMUX_PAD(0x0564, 0x021C, 1, 0x0000, 0, 0), + MX6_PAD_RGMII2_TXC__SAI1_TX_DATA_0 = IOMUX_PAD(0x0564, 0x021C, 2, 0x0000, 0, 0), + MX6_PAD_RGMII2_TXC__GPIO5_IO_23 = IOMUX_PAD(0x0564, 0x021C, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_TXC__CSI2_PIXCLK = IOMUX_PAD(0x0564, 0x021C, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_TXC__SJC_DONE = IOMUX_PAD(0x0564, 0x021C, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_TXC__VDEC_DEBUG_29 = IOMUX_PAD(0x0564, 0x021C, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_TXC__PCIE_CTRL_DEBUG_23 = IOMUX_PAD(0x0564, 0x021C, 9, 0x0000, 0, 0), + + MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0568, 0x0220, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0568, 0x0220, 1, 0x0668, 1, 0), + MX6_PAD_SD1_CLK__WDOG2_WDOG_B = IOMUX_PAD(0x0568, 0x0220, 2, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPT_CLK = IOMUX_PAD(0x0568, 0x0220, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x0568, 0x0220, 4, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPIO6_IO_0 = IOMUX_PAD(0x0568, 0x0220, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x0568, 0x0220, 6, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__CCM_OUT1 = IOMUX_PAD(0x0568, 0x0220, 7, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__VADC_ADC_PROC_CLK = IOMUX_PAD(0x0568, 0x0220, 8, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__MMDC_DEBUG_45 = IOMUX_PAD(0x0568, 0x0220, 9, 0x0000, 0, 0), + + MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x056C, 0x0224, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__AUDMUX_AUD5_RXC = IOMUX_PAD(0x056C, 0x0224, 1, 0x0664, 1, 0), + MX6_PAD_SD1_CMD__WDOG1_WDOG_B = IOMUX_PAD(0x056C, 0x0224, 2, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPT_COMPARE1 = IOMUX_PAD(0x056C, 0x0224, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x056C, 0x0224, 4, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPIO6_IO_1 = IOMUX_PAD(0x056C, 0x0224, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x056C, 0x0224, 6, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__CCM_CLKO1 = IOMUX_PAD(0x056C, 0x0224, 7, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__VADC_EXT_SYSCLK = IOMUX_PAD(0x056C, 0x0224, 8, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__MMDC_DEBUG_46 = IOMUX_PAD(0x056C, 0x0224, 9, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0570, 0x0228, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__AUDMUX_AUD5_RXD = IOMUX_PAD(0x0570, 0x0228, 1, 0x065C, 1, 0), + MX6_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS = IOMUX_PAD(0x0570, 0x0228, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__GPT_CAPTURE1 = IOMUX_PAD(0x0570, 0x0228, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__UART2_RX = IOMUX_PAD(0x0570, 0x0228, 4, 0x0838, 2, 0), + MX6_PAD_SD1_DATA0__GPIO6_IO_2 = IOMUX_PAD(0x0570, 0x0228, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0570, 0x0228, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__CCM_OUT2 = IOMUX_PAD(0x0570, 0x0228, 7, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__VADC_CLAMP_UP = IOMUX_PAD(0x0570, 0x0228, 8, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__MMDC_DEBUG_48 = IOMUX_PAD(0x0570, 0x0228, 9, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0574, 0x022C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__AUDMUX_AUD5_TXC = IOMUX_PAD(0x0574, 0x022C, 1, 0x066C, 1, 0), + MX6_PAD_SD1_DATA1__PWM4_OUT = IOMUX_PAD(0x0574, 0x022C, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__GPT_CAPTURE2 = IOMUX_PAD(0x0574, 0x022C, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__UART2_TX = IOMUX_PAD(0x0574, 0x022C, 4, 0x0838, 3, 0), + MX6_PAD_SD1_DATA1__GPIO6_IO_3 = IOMUX_PAD(0x0574, 0x022C, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0574, 0x022C, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__CCM_CLKO2 = IOMUX_PAD(0x0574, 0x022C, 7, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__VADC_CLAMP_DOWN = IOMUX_PAD(0x0574, 0x022C, 8, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__MMDC_DEBUG_47 = IOMUX_PAD(0x0574, 0x022C, 9, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0578, 0x0230, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x0578, 0x0230, 1, 0x0670, 1, 0), + MX6_PAD_SD1_DATA2__PWM3_OUT = IOMUX_PAD(0x0578, 0x0230, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__GPT_COMPARE2 = IOMUX_PAD(0x0578, 0x0230, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__UART2_CTS_B = IOMUX_PAD(0x0578, 0x0230, 4, 0x0834, 2, 0), + MX6_PAD_SD1_DATA2__GPIO6_IO_4 = IOMUX_PAD(0x0578, 0x0230, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__ECSPI4_RDY = IOMUX_PAD(0x0578, 0x0230, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__CCM_OUT0 = IOMUX_PAD(0x0578, 0x0230, 7, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__VADC_EXT_PD_N = IOMUX_PAD(0x0578, 0x0230, 8, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x057C, 0x0234, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__AUDMUX_AUD5_TXD = IOMUX_PAD(0x057C, 0x0234, 1, 0x0660, 1, 0), + MX6_PAD_SD1_DATA3__AUDMUX_AUD5_RXD = IOMUX_PAD(0x057C, 0x0234, 2, 0x065C, 2, 0), + MX6_PAD_SD1_DATA3__GPT_COMPARE3 = IOMUX_PAD(0x057C, 0x0234, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__UART2_RTS_B = IOMUX_PAD(0x057C, 0x0234, 4, 0x0834, 3, 0), + MX6_PAD_SD1_DATA3__GPIO6_IO_5 = IOMUX_PAD(0x057C, 0x0234, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__ECSPI4_SS1 = IOMUX_PAD(0x057C, 0x0234, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__CCM_PMIC_RDY = IOMUX_PAD(0x057C, 0x0234, 7, 0x069C, 2, 0), + MX6_PAD_SD1_DATA3__VADC_RST_N = IOMUX_PAD(0x057C, 0x0234, 8, 0x0000, 0, 0), + + MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x0580, 0x0238, 0, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0580, 0x0238, 1, 0x0680, 2, 0), + MX6_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x0580, 0x0238, 2, 0x07C8, 1, 0), + MX6_PAD_SD2_CLK__ECSPI4_SCLK = IOMUX_PAD(0x0580, 0x0238, 3, 0x0740, 1, 0), + MX6_PAD_SD2_CLK__MLB_SIG = IOMUX_PAD(0x0580, 0x0238, 4, 0x07F0, 2, 0), + MX6_PAD_SD2_CLK__GPIO6_IO_6 = IOMUX_PAD(0x0580, 0x0238, 5, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__MQS_RIGHT = IOMUX_PAD(0x0580, 0x0238, 6, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__WDOG1_WDOG_ANY = IOMUX_PAD(0x0580, 0x0238, 7, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__VADC_CLAMP_CURRENT_5 = IOMUX_PAD(0x0580, 0x0238, 8, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__MMDC_DEBUG_29 = IOMUX_PAD(0x0580, 0x0238, 9, 0x0000, 0, 0), + + MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0584, 0x023C, 0, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__AUDMUX_AUD6_RXC = IOMUX_PAD(0x0584, 0x023C, 1, 0x067C, 2, 0), + MX6_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x0584, 0x023C, 2, 0x07D4, 1, 0), + MX6_PAD_SD2_CMD__ECSPI4_MOSI = IOMUX_PAD(0x0584, 0x023C, 3, 0x0748, 1, 0), + MX6_PAD_SD2_CMD__MLB_CLK = IOMUX_PAD(0x0584, 0x023C, 4, 0x07E8, 2, 0), + MX6_PAD_SD2_CMD__GPIO6_IO_7 = IOMUX_PAD(0x0584, 0x023C, 5, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__MQS_LEFT = IOMUX_PAD(0x0584, 0x023C, 6, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__WDOG3_WDOG_B = IOMUX_PAD(0x0584, 0x023C, 7, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__VADC_CLAMP_CURRENT_4 = IOMUX_PAD(0x0584, 0x023C, 8, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__MMDC_DEBUG_30 = IOMUX_PAD(0x0584, 0x023C, 9, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0588, 0x0240, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA0__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0588, 0x0240, 1, 0x0674, 2, 0), + MX6_PAD_SD2_DATA0__KPP_ROW_7 = IOMUX_PAD(0x0588, 0x0240, 2, 0x07DC, 1, 0), + MX6_PAD_SD2_DATA0__PWM1_OUT = IOMUX_PAD(0x0588, 0x0240, 3, 0x0000, 0, 0), + MX6_PAD_SD2_DATA0__I2C4_SDA = IOMUX_PAD(0x0588, 0x0240, IOMUX_CONFIG_SION | 4, 0x07C4, 3, 0), + MX6_PAD_SD2_DATA0__GPIO6_IO_8 = IOMUX_PAD(0x0588, 0x0240, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DATA0__ECSPI4_SS3 = IOMUX_PAD(0x0588, 0x0240, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DATA0__UART4_RX = IOMUX_PAD(0x0588, 0x0240, 7, 0x0848, 4, 0), + MX6_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0 = IOMUX_PAD(0x0588, 0x0240, 8, 0x0000, 0, 0), + MX6_PAD_SD2_DATA0__MMDC_DEBUG_50 = IOMUX_PAD(0x0588, 0x0240, 9, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x058C, 0x0244, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA1__AUDMUX_AUD6_TXC = IOMUX_PAD(0x058C, 0x0244, 1, 0x0684, 2, 0), + MX6_PAD_SD2_DATA1__KPP_COL_7 = IOMUX_PAD(0x058C, 0x0244, 2, 0x07D0, 1, 0), + MX6_PAD_SD2_DATA1__PWM2_OUT = IOMUX_PAD(0x058C, 0x0244, 3, 0x0000, 0, 0), + MX6_PAD_SD2_DATA1__I2C4_SCL = IOMUX_PAD(0x058C, 0x0244, IOMUX_CONFIG_SION | 4, 0x07C0, 3, 0), + MX6_PAD_SD2_DATA1__GPIO6_IO_9 = IOMUX_PAD(0x058C, 0x0244, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DATA1__ECSPI4_SS2 = IOMUX_PAD(0x058C, 0x0244, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DATA1__UART4_TX = IOMUX_PAD(0x058C, 0x0244, 7, 0x0848, 5, 0), + MX6_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1 = IOMUX_PAD(0x058C, 0x0244, 8, 0x0000, 0, 0), + MX6_PAD_SD2_DATA1__MMDC_DEBUG_49 = IOMUX_PAD(0x058C, 0x0244, 9, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x0590, 0x0248, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x0590, 0x0248, 1, 0x0688, 2, 0), + MX6_PAD_SD2_DATA2__KPP_ROW_6 = IOMUX_PAD(0x0590, 0x0248, 2, 0x07D8, 1, 0), + MX6_PAD_SD2_DATA2__ECSPI4_SS0 = IOMUX_PAD(0x0590, 0x0248, 3, 0x074C, 1, 0), + MX6_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x0590, 0x0248, 4, 0x081C, 2, 0), + MX6_PAD_SD2_DATA2__GPIO6_IO_10 = IOMUX_PAD(0x0590, 0x0248, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DATA2__SPDIF_OUT = IOMUX_PAD(0x0590, 0x0248, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DATA2__UART6_RX = IOMUX_PAD(0x0590, 0x0248, 7, 0x0858, 4, 0), + MX6_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2 = IOMUX_PAD(0x0590, 0x0248, 8, 0x0000, 0, 0), + MX6_PAD_SD2_DATA2__MMDC_DEBUG_32 = IOMUX_PAD(0x0590, 0x0248, 9, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0594, 0x024C, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA3__AUDMUX_AUD6_TXD = IOMUX_PAD(0x0594, 0x024C, 1, 0x0678, 2, 0), + MX6_PAD_SD2_DATA3__KPP_COL_6 = IOMUX_PAD(0x0594, 0x024C, 2, 0x07CC, 1, 0), + MX6_PAD_SD2_DATA3__ECSPI4_MISO = IOMUX_PAD(0x0594, 0x024C, 3, 0x0744, 1, 0), + MX6_PAD_SD2_DATA3__MLB_DATA = IOMUX_PAD(0x0594, 0x024C, 4, 0x07EC, 2, 0), + MX6_PAD_SD2_DATA3__GPIO6_IO_11 = IOMUX_PAD(0x0594, 0x024C, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DATA3__SPDIF_IN = IOMUX_PAD(0x0594, 0x024C, 6, 0x0824, 4, 0), + MX6_PAD_SD2_DATA3__UART6_TX = IOMUX_PAD(0x0594, 0x024C, 7, 0x0858, 5, 0), + MX6_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 = IOMUX_PAD(0x0594, 0x024C, 8, 0x0000, 0, 0), + MX6_PAD_SD2_DATA3__MMDC_DEBUG_31 = IOMUX_PAD(0x0594, 0x024C, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0598, 0x0250, 0, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__UART4_CTS_B = IOMUX_PAD(0x0598, 0x0250, 1, 0x0844, 0, 0), + MX6_PAD_SD3_CLK__ECSPI4_SCLK = IOMUX_PAD(0x0598, 0x0250, 2, 0x0740, 0, 0), + MX6_PAD_SD3_CLK__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0598, 0x0250, 3, 0x0680, 0, 0), + MX6_PAD_SD3_CLK__LCDIF2_VSYNC = IOMUX_PAD(0x0598, 0x0250, 4, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__GPIO7_IO_0 = IOMUX_PAD(0x0598, 0x0250, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__LCDIF2_BUSY = IOMUX_PAD(0x0598, 0x0250, 6, 0x07E4, 0, 0), + MX6_PAD_SD3_CLK__TPSMP_HDATA_29 = IOMUX_PAD(0x0598, 0x0250, 7, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x0598, 0x0250, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x059C, 0x0254, 0, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__UART4_TX = IOMUX_PAD(0x059C, 0x0254, 1, 0x0848, 0, 0), + MX6_PAD_SD3_CMD__ECSPI4_MOSI = IOMUX_PAD(0x059C, 0x0254, 2, 0x0748, 0, 0), + MX6_PAD_SD3_CMD__AUDMUX_AUD6_RXC = IOMUX_PAD(0x059C, 0x0254, 3, 0x067C, 0, 0), + MX6_PAD_SD3_CMD__LCDIF2_HSYNC = IOMUX_PAD(0x059C, 0x0254, 4, 0x07E4, 1, 0), + MX6_PAD_SD3_CMD__GPIO7_IO_1 = IOMUX_PAD(0x059C, 0x0254, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__LCDIF2_RS = IOMUX_PAD(0x059C, 0x0254, 6, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__TPSMP_HDATA_28 = IOMUX_PAD(0x059C, 0x0254, 7, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x059C, 0x0254, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA0__USDHC3_DATA0 = IOMUX_PAD(0x05A0, 0x0258, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA0__I2C4_SCL = IOMUX_PAD(0x05A0, 0x0258, IOMUX_CONFIG_SION | 1, 0x07C0, 0, 0), + MX6_PAD_SD3_DATA0__ECSPI2_SS1 = IOMUX_PAD(0x05A0, 0x0258, 2, 0x0000, 0, 0), + MX6_PAD_SD3_DATA0__AUDMUX_AUD6_RXD = IOMUX_PAD(0x05A0, 0x0258, 3, 0x0674, 0, 0), + MX6_PAD_SD3_DATA0__LCDIF2_DATA_1 = IOMUX_PAD(0x05A0, 0x0258, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA0__GPIO7_IO_2 = IOMUX_PAD(0x05A0, 0x0258, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA0__DCIC1_OUT = IOMUX_PAD(0x05A0, 0x0258, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DATA0__TPSMP_HDATA_30 = IOMUX_PAD(0x05A0, 0x0258, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DATA0__GPU_DEBUG_0 = IOMUX_PAD(0x05A0, 0x0258, 8, 0x0000, 0, 0), + MX6_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0 = IOMUX_PAD(0x05A0, 0x0258, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA1__USDHC3_DATA1 = IOMUX_PAD(0x05A4, 0x025C, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__I2C4_SDA = IOMUX_PAD(0x05A4, 0x025C, IOMUX_CONFIG_SION | 1, 0x07C4, 0, 0), + MX6_PAD_SD3_DATA1__ECSPI2_SS2 = IOMUX_PAD(0x05A4, 0x025C, 2, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__AUDMUX_AUD6_TXC = IOMUX_PAD(0x05A4, 0x025C, 3, 0x0684, 0, 0), + MX6_PAD_SD3_DATA1__LCDIF2_DATA_0 = IOMUX_PAD(0x05A4, 0x025C, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__GPIO7_IO_3 = IOMUX_PAD(0x05A4, 0x025C, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__DCIC2_OUT = IOMUX_PAD(0x05A4, 0x025C, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__TPSMP_HDATA_31 = IOMUX_PAD(0x05A4, 0x025C, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__GPU_DEBUG_1 = IOMUX_PAD(0x05A4, 0x025C, 8, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 = IOMUX_PAD(0x05A4, 0x025C, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA2__USDHC3_DATA2 = IOMUX_PAD(0x05A8, 0x0260, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA2__UART4_RTS_B = IOMUX_PAD(0x05A8, 0x0260, 1, 0x0844, 1, 0), + MX6_PAD_SD3_DATA2__ECSPI4_SS0 = IOMUX_PAD(0x05A8, 0x0260, 2, 0x074C, 0, 0), + MX6_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x05A8, 0x0260, 3, 0x0688, 0, 0), + MX6_PAD_SD3_DATA2__LCDIF2_CLK = IOMUX_PAD(0x05A8, 0x0260, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA2__GPIO7_IO_4 = IOMUX_PAD(0x05A8, 0x0260, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA2__LCDIF2_WR_RWN = IOMUX_PAD(0x05A8, 0x0260, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DATA2__TPSMP_HDATA_26 = IOMUX_PAD(0x05A8, 0x0260, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DATA2__GPU_DEBUG_2 = IOMUX_PAD(0x05A8, 0x0260, 8, 0x0000, 0, 0), + MX6_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x05A8, 0x0260, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA3__USDHC3_DATA3 = IOMUX_PAD(0x05AC, 0x0264, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA3__UART4_RX = IOMUX_PAD(0x05AC, 0x0264, 1, 0x0848, 1, 0), + MX6_PAD_SD3_DATA3__ECSPI4_MISO = IOMUX_PAD(0x05AC, 0x0264, 2, 0x0744, 0, 0), + MX6_PAD_SD3_DATA3__AUDMUX_AUD6_TXD = IOMUX_PAD(0x05AC, 0x0264, 3, 0x0678, 0, 0), + MX6_PAD_SD3_DATA3__LCDIF2_ENABLE = IOMUX_PAD(0x05AC, 0x0264, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA3__GPIO7_IO_5 = IOMUX_PAD(0x05AC, 0x0264, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA3__LCDIF2_RD_E = IOMUX_PAD(0x05AC, 0x0264, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DATA3__TPSMP_HDATA_27 = IOMUX_PAD(0x05AC, 0x0264, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DATA3__GPU_DEBUG_3 = IOMUX_PAD(0x05AC, 0x0264, 8, 0x0000, 0, 0), + MX6_PAD_SD3_DATA3__SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x05AC, 0x0264, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA4__USDHC3_DATA4 = IOMUX_PAD(0x05B0, 0x0268, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA4__CAN2_RX = IOMUX_PAD(0x05B0, 0x0268, 1, 0x0690, 0, 0), + MX6_PAD_SD3_DATA4__CANFD_RX2 = IOMUX_PAD(0x05B0, 0x0268, 2, 0x0698, 0, 0), + MX6_PAD_SD3_DATA4__UART3_RX = IOMUX_PAD(0x05B0, 0x0268, 3, 0x0840, 2, 0), + MX6_PAD_SD3_DATA4__LCDIF2_DATA_3 = IOMUX_PAD(0x05B0, 0x0268, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA4__GPIO7_IO_6 = IOMUX_PAD(0x05B0, 0x0268, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x05B0, 0x0268, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DATA4__TPSMP_HTRANS_1 = IOMUX_PAD(0x05B0, 0x0268, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DATA4__GPU_DEBUG_4 = IOMUX_PAD(0x05B0, 0x0268, 8, 0x0000, 0, 0), + MX6_PAD_SD3_DATA4__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x05B0, 0x0268, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA5__USDHC3_DATA5 = IOMUX_PAD(0x05B4, 0x026C, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA5__CAN1_TX = IOMUX_PAD(0x05B4, 0x026C, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DATA5__CANFD_TX1 = IOMUX_PAD(0x05B4, 0x026C, 2, 0x0000, 0, 0), + MX6_PAD_SD3_DATA5__UART3_TX = IOMUX_PAD(0x05B4, 0x026C, 3, 0x0840, 3, 0), + MX6_PAD_SD3_DATA5__LCDIF2_DATA_2 = IOMUX_PAD(0x05B4, 0x026C, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA5__GPIO7_IO_7 = IOMUX_PAD(0x05B4, 0x026C, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x05B4, 0x026C, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DATA5__SIM_M_HWRITE = IOMUX_PAD(0x05B4, 0x026C, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DATA5__GPU_DEBUG_5 = IOMUX_PAD(0x05B4, 0x026C, 8, 0x0000, 0, 0), + MX6_PAD_SD3_DATA5__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x05B4, 0x026C, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA6__USDHC3_DATA6 = IOMUX_PAD(0x05B8, 0x0270, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA6__CAN2_TX = IOMUX_PAD(0x05B8, 0x0270, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DATA6__CANFD_TX2 = IOMUX_PAD(0x05B8, 0x0270, 2, 0x0000, 0, 0), + MX6_PAD_SD3_DATA6__UART3_RTS_B = IOMUX_PAD(0x05B8, 0x0270, 3, 0x083C, 2, 0), + MX6_PAD_SD3_DATA6__LCDIF2_DATA_4 = IOMUX_PAD(0x05B8, 0x0270, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA6__GPIO7_IO_8 = IOMUX_PAD(0x05B8, 0x0270, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x05B8, 0x0270, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DATA6__TPSMP_HTRANS_0 = IOMUX_PAD(0x05B8, 0x0270, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DATA6__GPU_DEBUG_7 = IOMUX_PAD(0x05B8, 0x0270, 8, 0x0000, 0, 0), + MX6_PAD_SD3_DATA6__SDMA_DEBUG_EVT_CHN_LINES_7 = IOMUX_PAD(0x05B8, 0x0270, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA7__USDHC3_DATA7 = IOMUX_PAD(0x05BC, 0x0274, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA7__CAN1_RX = IOMUX_PAD(0x05BC, 0x0274, 1, 0x068C, 0, 0), + MX6_PAD_SD3_DATA7__CANFD_RX1 = IOMUX_PAD(0x05BC, 0x0274, 2, 0x0694, 0, 0), + MX6_PAD_SD3_DATA7__UART3_CTS_B = IOMUX_PAD(0x05BC, 0x0274, 3, 0x083C, 3, 0), + MX6_PAD_SD3_DATA7__LCDIF2_DATA_5 = IOMUX_PAD(0x05BC, 0x0274, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA7__GPIO7_IO_9 = IOMUX_PAD(0x05BC, 0x0274, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x05BC, 0x0274, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DATA7__TPSMP_HDATA_DIR = IOMUX_PAD(0x05BC, 0x0274, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DATA7__GPU_DEBUG_6 = IOMUX_PAD(0x05BC, 0x0274, 8, 0x0000, 0, 0), + MX6_PAD_SD3_DATA7__SDMA_DEBUG_EVT_CHN_LINES_2 = IOMUX_PAD(0x05BC, 0x0274, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x05C0, 0x0278, 0, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__RAWNAND_DATA15 = IOMUX_PAD(0x05C0, 0x0278, 1, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__ECSPI2_MISO = IOMUX_PAD(0x05C0, 0x0278, 2, 0x0724, 1, 0), + MX6_PAD_SD4_CLK__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x05C0, 0x0278, 3, 0x0638, 0, 0), + MX6_PAD_SD4_CLK__LCDIF2_DATA_13 = IOMUX_PAD(0x05C0, 0x0278, 4, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__GPIO6_IO_12 = IOMUX_PAD(0x05C0, 0x0278, 5, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__ECSPI3_SS2 = IOMUX_PAD(0x05C0, 0x0278, 6, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__TPSMP_HDATA_20 = IOMUX_PAD(0x05C0, 0x0278, 7, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__VDEC_DEBUG_12 = IOMUX_PAD(0x05C0, 0x0278, 8, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x05C0, 0x0278, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x05C4, 0x027C, 0, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__RAWNAND_DATA14 = IOMUX_PAD(0x05C4, 0x027C, 1, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__ECSPI2_MOSI = IOMUX_PAD(0x05C4, 0x027C, 2, 0x0728, 1, 0), + MX6_PAD_SD4_CMD__AUDMUX_AUD3_RXC = IOMUX_PAD(0x05C4, 0x027C, 3, 0x0634, 0, 0), + MX6_PAD_SD4_CMD__LCDIF2_DATA_14 = IOMUX_PAD(0x05C4, 0x027C, 4, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__GPIO6_IO_13 = IOMUX_PAD(0x05C4, 0x027C, 5, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__ECSPI3_SS1 = IOMUX_PAD(0x05C4, 0x027C, 6, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__TPSMP_HDATA_19 = IOMUX_PAD(0x05C4, 0x027C, 7, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__VDEC_DEBUG_11 = IOMUX_PAD(0x05C4, 0x027C, 8, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__SDMA_DEBUG_CORE_RUN = IOMUX_PAD(0x05C4, 0x027C, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_DATA0__USDHC4_DATA0 = IOMUX_PAD(0x05C8, 0x0280, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DATA0__RAWNAND_DATA10 = IOMUX_PAD(0x05C8, 0x0280, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DATA0__ECSPI2_SS0 = IOMUX_PAD(0x05C8, 0x0280, 2, 0x072C, 1, 0), + MX6_PAD_SD4_DATA0__AUDMUX_AUD3_RXD = IOMUX_PAD(0x05C8, 0x0280, 3, 0x062C, 0, 0), + MX6_PAD_SD4_DATA0__LCDIF2_DATA_12 = IOMUX_PAD(0x05C8, 0x0280, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DATA0__GPIO6_IO_14 = IOMUX_PAD(0x05C8, 0x0280, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DATA0__ECSPI3_SS3 = IOMUX_PAD(0x05C8, 0x0280, 6, 0x0000, 0, 0), + MX6_PAD_SD4_DATA0__TPSMP_HDATA_21 = IOMUX_PAD(0x05C8, 0x0280, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DATA0__VDEC_DEBUG_13 = IOMUX_PAD(0x05C8, 0x0280, 8, 0x0000, 0, 0), + MX6_PAD_SD4_DATA0__SDMA_DEBUG_MODE = IOMUX_PAD(0x05C8, 0x0280, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_DATA1__USDHC4_DATA1 = IOMUX_PAD(0x05CC, 0x0284, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DATA1__RAWNAND_DATA11 = IOMUX_PAD(0x05CC, 0x0284, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DATA1__ECSPI2_SCLK = IOMUX_PAD(0x05CC, 0x0284, 2, 0x0720, 1, 0), + MX6_PAD_SD4_DATA1__AUDMUX_AUD3_TXC = IOMUX_PAD(0x05CC, 0x0284, 3, 0x063C, 0, 0), + MX6_PAD_SD4_DATA1__LCDIF2_DATA_11 = IOMUX_PAD(0x05CC, 0x0284, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DATA1__GPIO6_IO_15 = IOMUX_PAD(0x05CC, 0x0284, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DATA1__ECSPI3_RDY = IOMUX_PAD(0x05CC, 0x0284, 6, 0x0000, 0, 0), + MX6_PAD_SD4_DATA1__TPSMP_HDATA_22 = IOMUX_PAD(0x05CC, 0x0284, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DATA1__VDEC_DEBUG_14 = IOMUX_PAD(0x05CC, 0x0284, 8, 0x0000, 0, 0), + MX6_PAD_SD4_DATA1__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x05CC, 0x0284, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_DATA2__USDHC4_DATA2 = IOMUX_PAD(0x05D0, 0x0288, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DATA2__RAWNAND_DATA12 = IOMUX_PAD(0x05D0, 0x0288, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DATA2__I2C2_SDA = IOMUX_PAD(0x05D0, 0x0288, IOMUX_CONFIG_SION | 2, 0x07B4, 0, 0), + MX6_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x05D0, 0x0288, 3, 0x0640, 0, 0), + MX6_PAD_SD4_DATA2__LCDIF2_DATA_10 = IOMUX_PAD(0x05D0, 0x0288, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DATA2__GPIO6_IO_16 = IOMUX_PAD(0x05D0, 0x0288, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DATA2__ECSPI2_SS3 = IOMUX_PAD(0x05D0, 0x0288, 6, 0x0000, 0, 0), + MX6_PAD_SD4_DATA2__TPSMP_HDATA_23 = IOMUX_PAD(0x05D0, 0x0288, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DATA2__VDEC_DEBUG_15 = IOMUX_PAD(0x05D0, 0x0288, 8, 0x0000, 0, 0), + MX6_PAD_SD4_DATA2__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x05D0, 0x0288, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_DATA3__USDHC4_DATA3 = IOMUX_PAD(0x05D4, 0x028C, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DATA3__RAWNAND_DATA13 = IOMUX_PAD(0x05D4, 0x028C, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DATA3__I2C2_SCL = IOMUX_PAD(0x05D4, 0x028C, IOMUX_CONFIG_SION | 2, 0x07B0, 0, 0), + MX6_PAD_SD4_DATA3__AUDMUX_AUD3_TXD = IOMUX_PAD(0x05D4, 0x028C, 3, 0x0630, 0, 0), + MX6_PAD_SD4_DATA3__LCDIF2_DATA_9 = IOMUX_PAD(0x05D4, 0x028C, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DATA3__GPIO6_IO_17 = IOMUX_PAD(0x05D4, 0x028C, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DATA3__ECSPI2_RDY = IOMUX_PAD(0x05D4, 0x028C, 6, 0x0000, 0, 0), + MX6_PAD_SD4_DATA3__TPSMP_HDATA_24 = IOMUX_PAD(0x05D4, 0x028C, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DATA3__VDEC_DEBUG_16 = IOMUX_PAD(0x05D4, 0x028C, 8, 0x0000, 0, 0), + MX6_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x05D4, 0x028C, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_DATA4__USDHC4_DATA4 = IOMUX_PAD(0x05D8, 0x0290, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DATA4__RAWNAND_DATA09 = IOMUX_PAD(0x05D8, 0x0290, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DATA4__UART5_RX = IOMUX_PAD(0x05D8, 0x0290, 2, 0x0850, 0, 0), + MX6_PAD_SD4_DATA4__ECSPI3_SCLK = IOMUX_PAD(0x05D8, 0x0290, 3, 0x0730, 0, 0), + MX6_PAD_SD4_DATA4__LCDIF2_DATA_8 = IOMUX_PAD(0x05D8, 0x0290, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DATA4__GPIO6_IO_18 = IOMUX_PAD(0x05D8, 0x0290, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DATA4__SPDIF_OUT = IOMUX_PAD(0x05D8, 0x0290, 6, 0x0000, 0, 0), + MX6_PAD_SD4_DATA4__TPSMP_HDATA_16 = IOMUX_PAD(0x05D8, 0x0290, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DATA4__USB_OTG_HOST_MODE = IOMUX_PAD(0x05D8, 0x0290, 8, 0x0000, 0, 0), + MX6_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x05D8, 0x0290, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_DATA5__USDHC4_DATA5 = IOMUX_PAD(0x05DC, 0x0294, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DATA5__RAWNAND_CE2_B = IOMUX_PAD(0x05DC, 0x0294, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DATA5__UART5_TX = IOMUX_PAD(0x05DC, 0x0294, 2, 0x0850, 1, 0), + MX6_PAD_SD4_DATA5__ECSPI3_MOSI = IOMUX_PAD(0x05DC, 0x0294, 3, 0x0738, 0, 0), + MX6_PAD_SD4_DATA5__LCDIF2_DATA_7 = IOMUX_PAD(0x05DC, 0x0294, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DATA5__GPIO6_IO_19 = IOMUX_PAD(0x05DC, 0x0294, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DATA5__SPDIF_IN = IOMUX_PAD(0x05DC, 0x0294, 6, 0x0824, 0, 0), + MX6_PAD_SD4_DATA5__TPSMP_HDATA_17 = IOMUX_PAD(0x05DC, 0x0294, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DATA5__VDEC_DEBUG_9 = IOMUX_PAD(0x05DC, 0x0294, 8, 0x0000, 0, 0), + MX6_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x05DC, 0x0294, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_DATA6__USDHC4_DATA6 = IOMUX_PAD(0x05E0, 0x0298, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DATA6__RAWNAND_CE3_B = IOMUX_PAD(0x05E0, 0x0298, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DATA6__UART5_RTS_B = IOMUX_PAD(0x05E0, 0x0298, 2, 0x084C, 0, 0), + MX6_PAD_SD4_DATA6__ECSPI3_MISO = IOMUX_PAD(0x05E0, 0x0298, 3, 0x0734, 0, 0), + MX6_PAD_SD4_DATA6__LCDIF2_DATA_6 = IOMUX_PAD(0x05E0, 0x0298, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DATA6__GPIO6_IO_20 = IOMUX_PAD(0x05E0, 0x0298, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DATA6__USDHC4_WP = IOMUX_PAD(0x05E0, 0x0298, 6, 0x0878, 0, 0), + MX6_PAD_SD4_DATA6__TPSMP_HDATA_18 = IOMUX_PAD(0x05E0, 0x0298, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DATA6__VDEC_DEBUG_10 = IOMUX_PAD(0x05E0, 0x0298, 8, 0x0000, 0, 0), + MX6_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x05E0, 0x0298, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_DATA7__USDHC4_DATA7 = IOMUX_PAD(0x05E4, 0x029C, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DATA7__RAWNAND_DATA08 = IOMUX_PAD(0x05E4, 0x029C, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DATA7__UART5_CTS_B = IOMUX_PAD(0x05E4, 0x029C, 2, 0x084C, 1, 0), + MX6_PAD_SD4_DATA7__ECSPI3_SS0 = IOMUX_PAD(0x05E4, 0x029C, 3, 0x073C, 0, 0), + MX6_PAD_SD4_DATA7__LCDIF2_DATA_15 = IOMUX_PAD(0x05E4, 0x029C, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DATA7__GPIO6_IO_21 = IOMUX_PAD(0x05E4, 0x029C, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DATA7__USDHC4_CD_B = IOMUX_PAD(0x05E4, 0x029C, 6, 0x0874, 0, 0), + MX6_PAD_SD4_DATA7__TPSMP_HDATA_15 = IOMUX_PAD(0x05E4, 0x029C, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DATA7__USB_OTG_PWR_WAKE = IOMUX_PAD(0x05E4, 0x029C, 8, 0x0000, 0, 0), + MX6_PAD_SD4_DATA7__SDMA_DEBUG_YIELD = IOMUX_PAD(0x05E4, 0x029C, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_RESET_B__USDHC4_RESET_B = IOMUX_PAD(0x05E8, 0x02A0, 0, 0x0000, 0, 0), + MX6_PAD_SD4_RESET_B__RAWNAND_DQS = IOMUX_PAD(0x05E8, 0x02A0, 1, 0x0000, 0, 0), + MX6_PAD_SD4_RESET_B__USDHC4_RESET = IOMUX_PAD(0x05E8, 0x02A0, 2, 0x0000, 0, 0), + MX6_PAD_SD4_RESET_B__AUDMUX_MCLK = IOMUX_PAD(0x05E8, 0x02A0, 3, 0x0000, 0, 0), + MX6_PAD_SD4_RESET_B__LCDIF2_RESET = IOMUX_PAD(0x05E8, 0x02A0, 4, 0x0000, 0, 0), + MX6_PAD_SD4_RESET_B__GPIO6_IO_22 = IOMUX_PAD(0x05E8, 0x02A0, 5, 0x0000, 0, 0), + MX6_PAD_SD4_RESET_B__LCDIF2_CS = IOMUX_PAD(0x05E8, 0x02A0, 6, 0x0000, 0, 0), + MX6_PAD_SD4_RESET_B__TPSMP_HDATA_25 = IOMUX_PAD(0x05E8, 0x02A0, 7, 0x0000, 0, 0), + MX6_PAD_SD4_RESET_B__VDEC_DEBUG_17 = IOMUX_PAD(0x05E8, 0x02A0, 8, 0x0000, 0, 0), + MX6_PAD_SD4_RESET_B__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x05E8, 0x02A0, 9, 0x0000, 0, 0), + + MX6_PAD_USB_H_DATA__USB_H_DATA = IOMUX_PAD(0x05EC, 0x02A4, 0, 0x0000, 0, 0), + MX6_PAD_USB_H_DATA__PWM2_OUT = IOMUX_PAD(0x05EC, 0x02A4, 1, 0x0000, 0, 0), + MX6_PAD_USB_H_DATA__ANATOP_24M_OUT = IOMUX_PAD(0x05EC, 0x02A4, 2, 0x0000, 0, 0), + MX6_PAD_USB_H_DATA__I2C4_SDA = IOMUX_PAD(0x05EC, 0x02A4, IOMUX_CONFIG_SION | 3, 0x07C4, 1, 0), + MX6_PAD_USB_H_DATA__WDOG3_WDOG_B = IOMUX_PAD(0x05EC, 0x02A4, 4, 0x0000, 0, 0), + MX6_PAD_USB_H_DATA__GPIO7_IO_10 = IOMUX_PAD(0x05EC, 0x02A4, 5, 0x0000, 0, 0), + + MX6_PAD_USB_H_STROBE__USB_H_STROBE = IOMUX_PAD(0x05F0, 0x02A8, 0, 0x0000, 0, 0), + MX6_PAD_USB_H_STROBE__PWM1_OUT = IOMUX_PAD(0x05F0, 0x02A8, 1, 0x0000, 0, 0), + MX6_PAD_USB_H_STROBE__ANATOP_32K_OUT = IOMUX_PAD(0x05F0, 0x02A8, 2, 0x0000, 0, 0), + MX6_PAD_USB_H_STROBE__I2C4_SCL = IOMUX_PAD(0x05F0, 0x02A8, IOMUX_CONFIG_SION | 3, 0x07C0, 1, 0), + MX6_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x05F0, 0x02A8, 4, 0x0000, 0, 0), + MX6_PAD_USB_H_STROBE__GPIO7_IO_11 = IOMUX_PAD(0x05F0, 0x02A8, 5, 0x0000, 0, 0), +}; +#endif /* __ASM_ARCH_MX6_ MX6_PINS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h new file mode 100644 index 000000000..7ff201612 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __MX6SX_RDC_H__ +#define __MX6SX_RDC_H__ + +#define RDC_SEMA_PROC_ID 2 /* The processor ID for main CPU */ + +enum { + RDC_PER_PWM1 = 0, + RDC_PER_PWM2, + RDC_PER_PWM3, + RDC_PER_PWM4, + RDC_PER_CAN1, + RDC_PER_CAN2, + RDC_PER_GPT, + RDC_PER_GPIO1, + RDC_PER_GPIO2, + RDC_PER_GPIO3, + RDC_PER_GPIO4, + RDC_PER_GPIO5, + RDC_PER_GPIO6, + RDC_PER_GPIO7, + RDC_PER_KPP, + RDC_PER_WDOG1, + RDC_PER_WODG2, + RDC_PER_CCM, + RDC_PER_ANATOPDIG, + RDC_PER_SNVSHP, + RDC_PER_EPIT1, + RDC_PER_EPIT2, + RDC_PER_SRC, + RDC_PER_GPC, + RDC_PER_IOMUXC, + RDC_PER_IOMUXCGPR, + RDC_PER_CANFD1, + RDC_PER_SDMA, + RDC_PER_CANFD2, + RDC_PER_SEMA1, + RDC_PER_SEMA2, + RDC_PER_RDC, + RDC_PER_AIPSTZ1_GE1, + RDC_PER_AIPSTZ2_GE2, + RDC_PER_USBO2H_PL301, + RDC_PER_USBO2H_USB, + RDC_PER_ENET1, + RDC_PER_MLB25, + RDC_PER_USDHC1, + RDC_PER_USDHC2, + RDC_PER_USDHC3, + RDC_PER_USDHC4, + RDC_PER_I2C1, + RDC_PER_I2C2, + RDC_PER_I2C3, + RDC_PER_ROMCP, + RDC_PER_MMDC, + RDC_PER_ENET2, + RDC_PER_EIM, + RDC_PER_OCOTP, + RDC_PER_CSU, + RDC_PER_PERFMON1, + RDC_PER_PERFMON2, + RDC_PER_AXIMON, + RDC_PER_TZASC1, + RDC_PER_SAI1, + RDC_PER_AUDMUX, + RDC_PER_SAI2, + RDC_PER_QSPI1, + RDC_PER_QSPI2, + RDC_PER_UART2, + RDC_PER_UART3, + RDC_PER_UART4, + RDC_PER_UART5, + RDC_PER_I2C4, + RDC_PER_QOSC, + RDC_PER_CAAM, + RDC_PER_DAP, + RDC_PER_ADC1, + RDC_PER_ADC2, + RDC_PER_WDOG3, + RDC_PER_ECSPI5, + RDC_PER_SEMA4, + RDC_PER_MUPORT1, + RDC_PER_CANFD_CPU, + RDC_PER_MUPORT2, + RDC_PER_UART6, + RDC_PER_PWM5, + RDC_PER_PWM6, + RDC_PER_PWM7, + RDC_PER_PWM8, + RDC_PER_AIPSTZ3_GE0, + RDC_PER_AIPSTZ3_GE1, + RDC_PER_RESERVED1, + RDC_PER_SPDIF, + RDC_PER_ECSPI1, + RDC_PER_ECSPI2, + RDC_PER_ECSPI3, + RDC_PER_ECSPI4, + RDC_PER_RESERVED2, + RDC_PER_RESERVED3, + RDC_PER_UART1, + RDC_PER_ESAI, + RDC_PER_SSI1, + RDC_PER_SSI2, + RDC_PER_SSI3, + RDC_PER_ASRC, + RDC_PER_RESERVED4, + RDC_PER_SPBA_MA, + RDC_PER_GIS, + RDC_PER_DCIC1, + RDC_PER_DCIC2, + RDC_PER_CSI1, + RDC_PER_PXP, + RDC_PER_CSI2, + RDC_PER_LCDIF1, + RDC_PER_LCDIF2, + RDC_PER_VADC, + RDC_PER_VDEC, + RDC_PER_SPBA_DISPLAYMIX, +}; + +enum { + RDC_MA_A9_L2CACHE = 0, + RDC_MA_M4, + RDC_MA_GPU, + RDC_MA_CSI1, + RDC_MA_CSI2, + RDC_MA_LCDIF1, + RDC_MA_LCDIF2, + RDC_MA_PXP, + RDC_MA_PCIE_CTRL, + RDC_MA_DAP, + RDC_MA_CAAM, + RDC_MA_SDMA_PERI, + RDC_MA_SDMA_BURST, + RDC_MA_APBHDMA, + RDC_MA_RAWNAND, + RDC_MA_USDHC1, + RDC_MA_USDHC2, + RDC_MA_USDHC3, + RDC_MA_USDHC4, + RDC_MA_USB, + RDC_MA_MLB, + RDC_MA_TEST, + RDC_MA_ENET1_TX, + RDC_MA_ENET1_RX, + RDC_MA_ENET2_TX, + RDC_MA_ENET2_RX, + RDC_MA_SDMA, +}; + +#endif /* __MX6SX_RDC_H__*/ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h new file mode 100644 index 000000000..99779588b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __ASM_ARCH_MX6UL_DDR_H__ +#define __ASM_ARCH_MX6UL_DDR_H__ + +#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#error "wrong CPU" +#endif + +#define MX6_IOM_DRAM_DQM0 0x020e0244 +#define MX6_IOM_DRAM_DQM1 0x020e0248 + +#define MX6_IOM_DRAM_RAS 0x020e024c +#define MX6_IOM_DRAM_CAS 0x020e0250 +#define MX6_IOM_DRAM_CS0 0x020e0254 +#define MX6_IOM_DRAM_CS1 0x020e0258 +#define MX6_IOM_DRAM_SDWE_B 0x020e025c +#define MX6_IOM_DRAM_SDODT0 0x020e0260 +#define MX6_IOM_DRAM_SDODT1 0x020e0264 +#define MX6_IOM_DRAM_SDBA0 0x020e0268 +#define MX6_IOM_DRAM_SDBA1 0x020e026c +#define MX6_IOM_DRAM_SDBA2 0x020e0270 +#define MX6_IOM_DRAM_SDCKE0 0x020e0274 +#define MX6_IOM_DRAM_SDCKE1 0x020e0278 +#define MX6_IOM_DRAM_SDCLK_0 0x020e027c +#define MX6_IOM_DRAM_SDQS0 0x020e0280 +#define MX6_IOM_DRAM_SDQS1 0x020e0284 +#define MX6_IOM_DRAM_RESET 0x020e0288 + +#define MX6_IOM_GRP_ADDDS 0x020e0490 +#define MX6_IOM_DDRMODE_CTL 0x020e0494 +#define MX6_IOM_GRP_B0DS 0x020e0498 +#define MX6_IOM_GRP_DDRPK 0x020e049c +#define MX6_IOM_GRP_CTLDS 0x020e04a0 +#define MX6_IOM_GRP_B1DS 0x020e04a4 +#define MX6_IOM_GRP_DDRHYS 0x020e04a8 +#define MX6_IOM_GRP_DDRPKE 0x020e04ac +#define MX6_IOM_GRP_DDRMODE 0x020e04b0 +#define MX6_IOM_GRP_DDR_TYPE 0x020e04b4 + +#endif /*__ASM_ARCH_MX6SX_DDR_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6ul_pins.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6ul_pins.h new file mode 100644 index 000000000..031b4a0a8 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6ul_pins.h @@ -0,0 +1,1064 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __ASM_ARCH_IMX6UL_PINS_H__ +#define __ASM_ARCH_IMX6UL_PINS_H__ + +#include + +enum { + + MX6_PAD_BOOT_MODE0__GPIO5_IO10 = IOMUX_PAD(0x02A0, 0x0014, 5, 0x0000, 0, 0), + MX6_PAD_BOOT_MODE1__GPIO5_IO11 = IOMUX_PAD(0x02A4, 0x0018, 5, 0x0000, 0, 0), + /* + * The TAMPER Pin can be used for GPIO, which depends on + * fusemap TAMPER_PIN_DISABLE[1:0] settings. + */ + MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 = IOMUX_PAD(0x02A8, 0x001C, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 = IOMUX_PAD(0x02AC, 0x0020, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 = IOMUX_PAD(0x02B0, 0x0024, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 = IOMUX_PAD(0x02B4, 0x0028, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 = IOMUX_PAD(0x02B8, 0x002C, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 = IOMUX_PAD(0x02BC, 0x0030, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 = IOMUX_PAD(0x02C0, 0x0034, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 = IOMUX_PAD(0x02C4, 0x0038, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 = IOMUX_PAD(0x02C8, 0x003C, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 = IOMUX_PAD(0x02CC, 0x0040, 5, 0x0000, 0, 0), + + MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x02D0, 0x0044, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__GPT2_CLK = IOMUX_PAD(0x02D0, 0x0044, 1, 0x05A0, 0, 0), + MX6_PAD_JTAG_MOD__SPDIF_OUT = IOMUX_PAD(0x02D0, 0x0044, 2, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__ENET1_REF_CLK_25M = IOMUX_PAD(0x02D0, 0x0044, 3, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__CCM_PMIC_RDY = IOMUX_PAD(0x02D0, 0x0044, 4, 0x04C0, 0, 0), + MX6_PAD_JTAG_MOD__GPIO1_IO10 = IOMUX_PAD(0x02D0, 0x0044, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__SDMA_EXT_EVENT00 = IOMUX_PAD(0x02D0, 0x0044, 6, 0x0610, 0, 0), + + MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x02D4, 0x0048, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__GPT2_CAPTURE1 = IOMUX_PAD(0x02D4, 0x0048, 1, 0x0598, 0, 0), + MX6_PAD_JTAG_TMS__SAI2_MCLK = IOMUX_PAD(0x02D4, 0x0048, 2, 0x05F0, 0, 0), + MX6_PAD_JTAG_TMS__CCM_CLKO1 = IOMUX_PAD(0x02D4, 0x0048, 3, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__CCM_WAIT = IOMUX_PAD(0x02D4, 0x0048, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__GPIO1_IO11 = IOMUX_PAD(0x02D4, 0x0048, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__SDMA_EXT_EVENT01 = IOMUX_PAD(0x02D4, 0x0048, 6, 0x0614, 0, 0), + MX6_PAD_JTAG_TMS__EPIT1_OUT = IOMUX_PAD(0x02D4, 0x0048, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x02D8, 0x004C, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__GPT2_CAPTURE2 = IOMUX_PAD(0x02D8, 0x004C, 1, 0x059C, 0, 0), + MX6_PAD_JTAG_TDO__SAI2_TX_SYNC = IOMUX_PAD(0x02D8, 0x004C, 2, 0x05FC, 0, 0), + MX6_PAD_JTAG_TDO__CCM_CLKO2 = IOMUX_PAD(0x02D8, 0x004C, 3, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__CCM_STOP = IOMUX_PAD(0x02D8, 0x004C, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__GPIO1_IO12 = IOMUX_PAD(0x02D8, 0x004C, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__MQS_RIGHT = IOMUX_PAD(0x02D8, 0x004C, 6, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__EPIT2_OUT = IOMUX_PAD(0x02D8, 0x004C, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x02DC, 0x0050, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__GPT2_COMPARE1 = IOMUX_PAD(0x02DC, 0x0050, 1, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__SAI2_TX_BCLK = IOMUX_PAD(0x02DC, 0x0050, 2, 0x05F8, 0, 0), + MX6_PAD_JTAG_TDI__PWM6_OUT = IOMUX_PAD(0x02DC, 0x0050, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__GPIO1_IO13 = IOMUX_PAD(0x02DC, 0x0050, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__MQS_LEFT = IOMUX_PAD(0x02DC, 0x0050, 6, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__SIM1_POWER_FAIL = IOMUX_PAD(0x02DC, 0x0050, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x02E0, 0x0054, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__GPT2_COMPARE2 = IOMUX_PAD(0x02E0, 0x0054, 1, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__SAI2_RX_DATA = IOMUX_PAD(0x02E0, 0x0054, 2, 0x05F4, 0, 0), + MX6_PAD_JTAG_TCK__PWM7_OUT = IOMUX_PAD(0x02E0, 0x0054, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__GPIO1_IO14 = IOMUX_PAD(0x02E0, 0x0054, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__SIM2_POWER_FAIL = IOMUX_PAD(0x02E0, 0x0054, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TRST_B__SJC_TRSTB = IOMUX_PAD(0x02E4, 0x0058, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__GPT2_COMPARE3 = IOMUX_PAD(0x02E4, 0x0058, 1, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__SAI2_TX_DATA = IOMUX_PAD(0x02E4, 0x0058, 2, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__PWM8_OUT = IOMUX_PAD(0x02E4, 0x0058, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__GPIO1_IO15 = IOMUX_PAD(0x02E4, 0x0058, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x02E4, 0x0058, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO00__I2C2_SCL = IOMUX_PAD(0x02E8, 0x005C, IOMUX_CONFIG_SION | 0, 0x05AC, 1, 0), + MX6_PAD_GPIO1_IO00__GPT1_CAPTURE1 = IOMUX_PAD(0x02E8, 0x005C, 1, 0x058C, 0, 0), + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID = IOMUX_PAD(0x02E8, 0x005C, 2, 0x04B8, 0, 0), + MX6_PAD_GPIO1_IO00__ENET1_REF_CLK1 = IOMUX_PAD(0x02E8, 0x005C, 3, 0x0574, 0, 0), + MX6_PAD_GPIO1_IO00__MQS_RIGHT = IOMUX_PAD(0x02E8, 0x005C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__GPIO1_IO00 = IOMUX_PAD(0x02E8, 0x005C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02E8, 0x005C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__SRC_SYSTEM_RESET = IOMUX_PAD(0x02E8, 0x005C, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__WDOG3_WDOG_B = IOMUX_PAD(0x02E8, 0x005C, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO01__I2C2_SDA = IOMUX_PAD(0x02EC, 0x0060, IOMUX_CONFIG_SION | 0, 0x05B0, 1, 0), + MX6_PAD_GPIO1_IO01__GPT1_COMPARE1 = IOMUX_PAD(0x02EC, 0x0060, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__USB_OTG1_OC = IOMUX_PAD(0x02EC, 0x0060, 2, 0x0664, 0, 0), + MX6_PAD_GPIO1_IO01__ENET2_REF_CLK2 = IOMUX_PAD(0x02EC, 0x0060, 3, 0x057C, 0, 0), + MX6_PAD_GPIO1_IO01__MQS_LEFT = IOMUX_PAD(0x02EC, 0x0060, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__GPIO1_IO01 = IOMUX_PAD(0x02EC, 0x0060, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02EC, 0x0060, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__SRC_EARLY_RESET = IOMUX_PAD(0x02EC, 0x0060, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__WDOG1_WDOG_B = IOMUX_PAD(0x02EC, 0x0060, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO02__I2C1_SCL = IOMUX_PAD(0x02F0, 0x0064, IOMUX_CONFIG_SION | 0, 0x05A4, 0, 0), + MX6_PAD_GPIO1_IO02__GPT1_COMPARE2 = IOMUX_PAD(0x02F0, 0x0064, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__USB_OTG2_PWR = IOMUX_PAD(0x02F0, 0x0064, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__ENET1_REF_CLK_25M = IOMUX_PAD(0x02F0, 0x0064, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__USDHC1_WP = IOMUX_PAD(0x02F0, 0x0064, 4, 0x066C, 0, 0), + MX6_PAD_GPIO1_IO02__GPIO1_IO02 = IOMUX_PAD(0x02F0, 0x0064, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 = IOMUX_PAD(0x02F0, 0x0064, 6, 0x0610, 1, 0), + MX6_PAD_GPIO1_IO02__SRC_ANY_PU_RESET = IOMUX_PAD(0x02F0, 0x0064, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__UART1_DCE_TX = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__UART1_DTE_RX = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0624, 0, 0), + + MX6_PAD_GPIO1_IO03__I2C1_SDA = IOMUX_PAD(0x02F4, 0x0068, IOMUX_CONFIG_SION | 0, 0x05A8, 1, 0), + MX6_PAD_GPIO1_IO03__GPT1_COMPARE3 = IOMUX_PAD(0x02F4, 0x0068, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__USB_OTG2_OC = IOMUX_PAD(0x02F4, 0x0068, 2, 0x0660, 0, 0), + MX6_PAD_GPIO1_IO03__USDHC1_CD_B = IOMUX_PAD(0x02F4, 0x0068, 4, 0x0668, 0, 0), + MX6_PAD_GPIO1_IO03__GPIO1_IO03 = IOMUX_PAD(0x02F4, 0x0068, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK = IOMUX_PAD(0x02F4, 0x0068, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__SRC_TESTER_ACK = IOMUX_PAD(0x02F4, 0x0068, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__UART1_DCE_RX = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0624, 1, 0), + MX6_PAD_GPIO1_IO03__UART1_DTE_TX = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO04__ENET1_REF_CLK1 = IOMUX_PAD(0x02F8, 0x006C, 0, 0x0574, 1, 0), + MX6_PAD_GPIO1_IO04__PWM3_OUT = IOMUX_PAD(0x02F8, 0x006C, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__USB_OTG1_PWR = IOMUX_PAD(0x02F8, 0x006C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__USDHC1_RESET_B = IOMUX_PAD(0x02F8, 0x006C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__GPIO1_IO04 = IOMUX_PAD(0x02F8, 0x006C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x02F8, 0x006C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__UART5_DCE_TX = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__UART5_DTE_RX = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0644, 2, 0), + + MX6_PAD_GPIO1_IO05__ENET2_REF_CLK2 = IOMUX_PAD(0x02FC, 0x0070, 0, 0x057C, 1, 0), + MX6_PAD_GPIO1_IO05__PWM4_OUT = IOMUX_PAD(0x02FC, 0x0070, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID = IOMUX_PAD(0x02FC, 0x0070, 2, 0x04BC, 0, 0), + MX6_PAD_GPIO1_IO05__CSI_FIELD = IOMUX_PAD(0x02FC, 0x0070, 3, 0x0530, 0, 0), + MX6_PAD_GPIO1_IO05__USDHC1_VSELECT = IOMUX_PAD(0x02FC, 0x0070, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__GPIO1_IO05 = IOMUX_PAD(0x02FC, 0x0070, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x02FC, 0x0070, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__UART5_DCE_RX = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0644, 3, 0), + MX6_PAD_GPIO1_IO05__UART5_DTE_TX = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO06__ENET1_MDIO = IOMUX_PAD(0x0300, 0x0074, 0, 0x0578, 0, 0), + MX6_PAD_GPIO1_IO06__ENET2_MDIO = IOMUX_PAD(0x0300, 0x0074, 1, 0x0580, 0, 0), + MX6_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE = IOMUX_PAD(0x0300, 0x0074, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__CSI_MCLK = IOMUX_PAD(0x0300, 0x0074, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__USDHC2_WP = IOMUX_PAD(0x0300, 0x0074, 4, 0x069C, 0, 0), + MX6_PAD_GPIO1_IO06__GPIO1_IO06 = IOMUX_PAD(0x0300, 0x0074, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__CCM_WAIT = IOMUX_PAD(0x0300, 0x0074, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__CCM_REF_EN_B = IOMUX_PAD(0x0300, 0x0074, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__UART1_DCE_CTS = IOMUX_PAD(0x0300, 0x0074, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__UART1_DTE_RTS = IOMUX_PAD(0x0300, 0x0074, 8, 0x0620, 0, 0), + + MX6_PAD_GPIO1_IO07__ENET1_MDC = IOMUX_PAD(0x0304, 0x0078, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__ENET2_MDC = IOMUX_PAD(0x0304, 0x0078, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__USB_OTG_HOST_MODE = IOMUX_PAD(0x0304, 0x0078, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__CSI_PIXCLK = IOMUX_PAD(0x0304, 0x0078, 3, 0x0528, 0, 0), + MX6_PAD_GPIO1_IO07__USDHC2_CD_B = IOMUX_PAD(0x0304, 0x0078, 4, 0x0674, 1, 0), + MX6_PAD_GPIO1_IO07__GPIO1_IO07 = IOMUX_PAD(0x0304, 0x0078, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__CCM_STOP = IOMUX_PAD(0x0304, 0x0078, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__UART1_DCE_RTS = IOMUX_PAD(0x0304, 0x0078, 8, 0x0620, 1, 0), + MX6_PAD_GPIO1_IO07__UART1_DTE_CTS = IOMUX_PAD(0x0304, 0x0078, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x0308, 0x007C, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__WDOG1_WDOG_B = IOMUX_PAD(0x0308, 0x007C, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__SPDIF_OUT = IOMUX_PAD(0x0308, 0x007C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__CSI_VSYNC = IOMUX_PAD(0x0308, 0x007C, 3, 0x052C, 1, 0), + MX6_PAD_GPIO1_IO08__USDHC2_VSELECT = IOMUX_PAD(0x0308, 0x007C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__GPIO1_IO08 = IOMUX_PAD(0x0308, 0x007C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__CCM_PMIC_RDY = IOMUX_PAD(0x0308, 0x007C, 6, 0x04C0, 1, 0), + MX6_PAD_GPIO1_IO08__UART5_DCE_RTS = IOMUX_PAD(0x0308, 0x007C, 8, 0x0640, 1, 0), + MX6_PAD_GPIO1_IO08__UART5_DTE_CTS = IOMUX_PAD(0x0308, 0x007C, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x030C, 0x0080, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__WDOG1_WDOG_ANY = IOMUX_PAD(0x030C, 0x0080, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__SPDIF_IN = IOMUX_PAD(0x030C, 0x0080, 2, 0x0618, 0, 0), + MX6_PAD_GPIO1_IO09__CSI_HSYNC = IOMUX_PAD(0x030C, 0x0080, 3, 0x0524, 1, 0), + MX6_PAD_GPIO1_IO09__USDHC2_RESET_B = IOMUX_PAD(0x030C, 0x0080, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__GPIO1_IO09 = IOMUX_PAD(0x030C, 0x0080, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__USDHC1_RESET_B = IOMUX_PAD(0x030C, 0x0080, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__UART5_DCE_CTS = IOMUX_PAD(0x030C, 0x0080, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__UART5_DTE_RTS = IOMUX_PAD(0x030C, 0x0080, 8, 0x0640, 2, 0), + + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX = IOMUX_PAD(0x0310, 0x0084, 0, 0x0000, 0, 0), + + MX6_PAD_UART1_TX_DATA__UART1_DTE_RX = IOMUX_PAD(0x0310, 0x0084, 0, 0x0624, 2, 0), + MX6_PAD_UART1_TX_DATA__ENET1_RDATA02 = IOMUX_PAD(0x0310, 0x0084, 1, 0x0000, 0, 0), + MX6_PAD_UART1_TX_DATA__I2C3_SCL = IOMUX_PAD(0x0310, 0x0084, IOMUX_CONFIG_SION | 2, 0x05B4, 0, 0), + MX6_PAD_UART1_TX_DATA__CSI_DATA02 = IOMUX_PAD(0x0310, 0x0084, 3, 0x04C4, 1, 0), + MX6_PAD_UART1_TX_DATA__GPT1_COMPARE1 = IOMUX_PAD(0x0310, 0x0084, 4, 0x0000, 0, 0), + MX6_PAD_UART1_TX_DATA__GPIO1_IO16 = IOMUX_PAD(0x0310, 0x0084, 5, 0x0000, 0, 0), + MX6_PAD_UART1_TX_DATA__SPDIF_OUT = IOMUX_PAD(0x0310, 0x0084, 8, 0x0000, 0, 0), + + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0314, 0x0088, 0, 0x0624, 3, 0), + + MX6_PAD_UART1_RX_DATA__UART1_DTE_TX = IOMUX_PAD(0x0314, 0x0088, 0, 0x0000, 0, 0), + MX6_PAD_UART1_RX_DATA__ENET1_RDATA03 = IOMUX_PAD(0x0314, 0x0088, 1, 0x0000, 0, 0), + MX6_PAD_UART1_RX_DATA__I2C3_SDA = IOMUX_PAD(0x0314, 0x0088, IOMUX_CONFIG_SION | 2, 0x05B8, 0, 0), + MX6_PAD_UART1_RX_DATA__CSI_DATA03 = IOMUX_PAD(0x0314, 0x0088, 3, 0x04C8, 1, 0), + MX6_PAD_UART1_RX_DATA__GPT1_CLK = IOMUX_PAD(0x0314, 0x0088, 4, 0x0594, 0, 0), + MX6_PAD_UART1_RX_DATA__GPIO1_IO17 = IOMUX_PAD(0x0314, 0x0088, 5, 0x0000, 0, 0), + MX6_PAD_UART1_RX_DATA__SPDIF_IN = IOMUX_PAD(0x0314, 0x0088, 8, 0x0618, 1, 0), + + MX6_PAD_UART1_CTS_B__UART1_DCE_CTS = IOMUX_PAD(0x0318, 0x008C, 0, 0x0000, 0, 0), + + MX6_PAD_UART1_CTS_B__UART1_DTE_RTS = IOMUX_PAD(0x0318, 0x008C, 0, 0x0620, 2, 0), + MX6_PAD_UART1_CTS_B__ENET1_RX_CLK = IOMUX_PAD(0x0318, 0x008C, 1, 0x0000, 0, 0), + MX6_PAD_UART1_CTS_B__USDHC1_WP = IOMUX_PAD(0x0318, 0x008C, 2, 0x066C, 1, 0), + MX6_PAD_UART1_CTS_B__CSI_DATA04 = IOMUX_PAD(0x0318, 0x008C, 3, 0x04D8, 0, 0), + MX6_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x0318, 0x008C, 4, 0x0000, 0, 0), + MX6_PAD_UART1_CTS_B__GPIO1_IO18 = IOMUX_PAD(0x0318, 0x008C, 5, 0x0000, 0, 0), + MX6_PAD_UART1_CTS_B__USDHC2_WP = IOMUX_PAD(0x0318, 0x008C, 8, 0x069C, 1, 0), + + MX6_PAD_UART1_RTS_B__UART1_DCE_RTS = IOMUX_PAD(0x031C, 0x0090, 0, 0x0620, 3, 0), + + MX6_PAD_UART1_RTS_B__UART1_DTE_CTS = IOMUX_PAD(0x031C, 0x0090, 0, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__ENET1_TX_ER = IOMUX_PAD(0x031C, 0x0090, 1, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__USDHC1_CD_B = IOMUX_PAD(0x031C, 0x0090, 2, 0x0668, 1, 0), + MX6_PAD_UART1_RTS_B__CSI_DATA05 = IOMUX_PAD(0x031C, 0x0090, 3, 0x04CC, 1, 0), + MX6_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x031C, 0x0090, 4, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__GPIO1_IO19 = IOMUX_PAD(0x031C, 0x0090, 5, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__USDHC2_CD_B = IOMUX_PAD(0x031C, 0x0090, 8, 0x0674, 2, 0), + + MX6_PAD_UART2_TX_DATA__UART2_DCE_TX = IOMUX_PAD(0x0320, 0x0094, 0, 0x0000, 0, 0), + + MX6_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x0320, 0x0094, 0, 0x062C, 0, 0), + MX6_PAD_UART2_TX_DATA__ENET1_TDATA02 = IOMUX_PAD(0x0320, 0x0094, 1, 0x0000, 0, 0), + MX6_PAD_UART2_TX_DATA__I2C4_SCL = IOMUX_PAD(0x0320, 0x0094, IOMUX_CONFIG_SION | 2, 0x05BC, 0, 0), + MX6_PAD_UART2_TX_DATA__CSI_DATA06 = IOMUX_PAD(0x0320, 0x0094, 3, 0x04DC, 0, 0), + MX6_PAD_UART2_TX_DATA__GPT1_CAPTURE1 = IOMUX_PAD(0x0320, 0x0094, 4, 0x058C, 1, 0), + MX6_PAD_UART2_TX_DATA__GPIO1_IO20 = IOMUX_PAD(0x0320, 0x0094, 5, 0x0000, 0, 0), + MX6_PAD_UART2_TX_DATA__ECSPI3_SS0 = IOMUX_PAD(0x0320, 0x0094, 8, 0x0560, 0, 0), + + MX6_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x0324, 0x0098, 0, 0x062C, 1, 0), + + MX6_PAD_UART2_RX_DATA__UART2_DTE_TX = IOMUX_PAD(0x0324, 0x0098, 0, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__ENET1_TDATA03 = IOMUX_PAD(0x0324, 0x0098, 1, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__I2C4_SDA = IOMUX_PAD(0x0324, 0x0098, IOMUX_CONFIG_SION | 2, 0x05C0, 0, 0), + MX6_PAD_UART2_RX_DATA__CSI_DATA07 = IOMUX_PAD(0x0324, 0x0098, 3, 0x04E0, 0, 0), + MX6_PAD_UART2_RX_DATA__GPT1_CAPTURE2 = IOMUX_PAD(0x0324, 0x0098, 4, 0x0590, 0, 0), + MX6_PAD_UART2_RX_DATA__GPIO1_IO21 = IOMUX_PAD(0x0324, 0x0098, 5, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__SJC_DONE = IOMUX_PAD(0x0324, 0x0098, 7, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__ECSPI3_SCLK = IOMUX_PAD(0x0324, 0x0098, 8, 0x0554, 0, 0), + + MX6_PAD_UART2_CTS_B__UART2_DCE_CTS = IOMUX_PAD(0x0328, 0x009C, 0, 0x0000, 0, 0), + + MX6_PAD_UART2_CTS_B__UART2_DTE_RTS = IOMUX_PAD(0x0328, 0x009C, 0, 0x0628, 0, 0), + MX6_PAD_UART2_CTS_B__ENET1_CRS = IOMUX_PAD(0x0328, 0x009C, 1, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__FLEXCAN2_TX = IOMUX_PAD(0x0328, 0x009C, 2, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__CSI_DATA08 = IOMUX_PAD(0x0328, 0x009C, 3, 0x04E4, 0, 0), + MX6_PAD_UART2_CTS_B__GPT1_COMPARE2 = IOMUX_PAD(0x0328, 0x009C, 4, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__GPIO1_IO22 = IOMUX_PAD(0x0328, 0x009C, 5, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__SJC_DE_B = IOMUX_PAD(0x0328, 0x009C, 7, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__ECSPI3_MOSI = IOMUX_PAD(0x0328, 0x009C, 8, 0x055C, 0, 0), + + MX6_PAD_UART2_RTS_B__UART2_DCE_RTS = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0628, 1, 0), + + MX6_PAD_UART2_RTS_B__UART2_DTE_CTS = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__ENET1_COL = IOMUX_PAD(0x032C, 0x00A0, 1, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__FLEXCAN2_RX = IOMUX_PAD(0x032C, 0x00A0, 2, 0x0588, 0, 0), + MX6_PAD_UART2_RTS_B__CSI_DATA09 = IOMUX_PAD(0x032C, 0x00A0, 3, 0x04E8, 0, 0), + MX6_PAD_UART2_RTS_B__GPT1_COMPARE3 = IOMUX_PAD(0x032C, 0x00A0, 4, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__GPIO1_IO23 = IOMUX_PAD(0x032C, 0x00A0, 5, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__SJC_FAIL = IOMUX_PAD(0x032C, 0x00A0, 7, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__ECSPI3_MISO = IOMUX_PAD(0x032C, 0x00A0, 8, 0x0558, 0, 0), + + MX6_PAD_UART3_TX_DATA__UART3_DCE_TX = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0000, 0, 0), + + MX6_PAD_UART3_TX_DATA__UART3_DTE_RX = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0634, 0, 0), + MX6_PAD_UART3_TX_DATA__ENET2_RDATA02 = IOMUX_PAD(0x0330, 0x00A4, 1, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__SIM1_PORT0_PD = IOMUX_PAD(0x0330, 0x00A4, 2, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__CSI_DATA01 = IOMUX_PAD(0x0330, 0x00A4, 3, 0x04D4, 0, 0), + MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__UART2_DTE_RTS = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0628, 2, 0), + MX6_PAD_UART3_TX_DATA__GPIO1_IO24 = IOMUX_PAD(0x0330, 0x00A4, 5, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__SJC_JTAG_ACT = IOMUX_PAD(0x0330, 0x00A4, 7, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__ANATOP_OTG1_ID = IOMUX_PAD(0x0330, 0x00A4, 8, 0x04B8, 1, 0), + + MX6_PAD_UART3_RX_DATA__UART3_DCE_RX = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0634, 1, 0), + + MX6_PAD_UART3_RX_DATA__UART3_DTE_TX = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__ENET2_RDATA03 = IOMUX_PAD(0x0334, 0x00A8, 1, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__SIM2_PORT0_PD = IOMUX_PAD(0x0334, 0x00A8, 2, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__CSI_DATA00 = IOMUX_PAD(0x0334, 0x00A8, 3, 0x04D0, 0, 0), + MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0628, 3, 0), + MX6_PAD_UART3_RX_DATA__UART2_DTE_CTS = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__GPIO1_IO25 = IOMUX_PAD(0x0334, 0x00A8, 5, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__EPIT1_OUT = IOMUX_PAD(0x0334, 0x00A8, 8, 0x0000, 0, 0), + + MX6_PAD_UART3_CTS_B__UART3_DCE_CTS = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0000, 0, 0), + + MX6_PAD_UART3_CTS_B__UART3_DTE_RTS = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0630, 0, 0), + MX6_PAD_UART3_CTS_B__ENET2_RX_CLK = IOMUX_PAD(0x0338, 0x00AC, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__FLEXCAN1_TX = IOMUX_PAD(0x0338, 0x00AC, 2, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__CSI_DATA10 = IOMUX_PAD(0x0338, 0x00AC, 3, 0x04EC, 0, 0), + MX6_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0338, 0x00AC, 4, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__GPIO1_IO26 = IOMUX_PAD(0x0338, 0x00AC, 5, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__EPIT2_OUT = IOMUX_PAD(0x0338, 0x00AC, 8, 0x0000, 0, 0), + + MX6_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0630, 1, 0), + + MX6_PAD_UART3_RTS_B__UART3_DTE_CTS = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__ENET2_TX_ER = IOMUX_PAD(0x033C, 0x00B0, 1, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__FLEXCAN1_RX = IOMUX_PAD(0x033C, 0x00B0, 2, 0x0584, 0, 0), + MX6_PAD_UART3_RTS_B__CSI_DATA11 = IOMUX_PAD(0x033C, 0x00B0, 3, 0x04F0, 0, 0), + MX6_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x033C, 0x00B0, 4, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__GPIO1_IO27 = IOMUX_PAD(0x033C, 0x00B0, 5, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__WDOG1_WDOG_B = IOMUX_PAD(0x033C, 0x00B0, 8, 0x0000, 0, 0), + + MX6_PAD_UART4_TX_DATA__UART4_DCE_TX = IOMUX_PAD(0x0340, 0x00B4, 0, 0x0000, 0, 0), + + MX6_PAD_UART4_TX_DATA__UART4_DTE_RX = IOMUX_PAD(0x0340, 0x00B4, 0, 0x063C, 0, 0), + MX6_PAD_UART4_TX_DATA__ENET2_TDATA02 = IOMUX_PAD(0x0340, 0x00B4, 1, 0x0000, 0, 0), + MX6_PAD_UART4_TX_DATA__I2C1_SCL = IOMUX_PAD(0x0340, 0x00B4, IOMUX_CONFIG_SION | 2, 0x05A4, 1, 0), + MX6_PAD_UART4_TX_DATA__CSI_DATA12 = IOMUX_PAD(0x0340, 0x00B4, 3, 0x04F4, 0, 0), + MX6_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 = IOMUX_PAD(0x0340, 0x00B4, 4, 0x0000, 0, 0), + MX6_PAD_UART4_TX_DATA__GPIO1_IO28 = IOMUX_PAD(0x0340, 0x00B4, 5, 0x0000, 0, 0), + MX6_PAD_UART4_TX_DATA__ECSPI2_SCLK = IOMUX_PAD(0x0340, 0x00B4, 8, 0x0544, 1, 0), + + MX6_PAD_UART4_RX_DATA__UART4_DCE_RX = IOMUX_PAD(0x0344, 0x00B8, 0, 0x063C, 1, 0), + + MX6_PAD_UART4_RX_DATA__UART4_DTE_TX = IOMUX_PAD(0x0344, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__ENET2_TDATA03 = IOMUX_PAD(0x0344, 0x00B8, 1, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__I2C1_SDA = IOMUX_PAD(0x0344, 0x00B8, IOMUX_CONFIG_SION | 2, 0x05A8, 2, 0), + MX6_PAD_UART4_RX_DATA__CSI_DATA13 = IOMUX_PAD(0x0344, 0x00B8, 3, 0x04F8, 0, 0), + MX6_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 = IOMUX_PAD(0x0344, 0x00B8, 4, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__GPIO1_IO29 = IOMUX_PAD(0x0344, 0x00B8, 5, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__ECSPI2_SS0 = IOMUX_PAD(0x0344, 0x00B8, 8, 0x0550, 1, 0), + MX6_PAD_UART5_TX_DATA__GPIO1_IO30 = IOMUX_PAD(0x0348, 0x00BC, 5, 0x0000, 0, 0), + MX6_PAD_UART5_TX_DATA__ECSPI2_MOSI = IOMUX_PAD(0x0348, 0x00BC, 8, 0x054C, 0, 0), + + MX6_PAD_UART5_TX_DATA__UART5_DCE_TX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0000, 0, 0), + + MX6_PAD_UART5_TX_DATA__UART5_DTE_RX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0644, 4, 0), + MX6_PAD_UART5_TX_DATA__ENET2_CRS = IOMUX_PAD(0x0348, 0x00BC, 1, 0x0000, 0, 0), + MX6_PAD_UART5_TX_DATA__I2C2_SCL = IOMUX_PAD(0x0348, 0x00BC, IOMUX_CONFIG_SION | 2, 0x05AC, 2, 0), + MX6_PAD_UART5_TX_DATA__CSI_DATA14 = IOMUX_PAD(0x0348, 0x00BC, 3, 0x04FC, 0, 0), + MX6_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 = IOMUX_PAD(0x0348, 0x00BC, 4, 0x0000, 0, 0), + + MX6_PAD_UART5_RX_DATA__UART5_DCE_RX = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0644, 5, 0), + + MX6_PAD_UART5_RX_DATA__UART5_DTE_TX = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__ENET2_COL = IOMUX_PAD(0x034C, 0x00C0, 1, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__I2C2_SDA = IOMUX_PAD(0x034C, 0x00C0, IOMUX_CONFIG_SION | 2, 0x05B0, 2, 0), + MX6_PAD_UART5_RX_DATA__CSI_DATA15 = IOMUX_PAD(0x034C, 0x00C0, 3, 0x0500, 0, 0), + MX6_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB = IOMUX_PAD(0x034C, 0x00C0, 4, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__GPIO1_IO31 = IOMUX_PAD(0x034C, 0x00C0, 5, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__ECSPI2_MISO = IOMUX_PAD(0x034C, 0x00C0, 8, 0x0548, 1, 0), + + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 = IOMUX_PAD(0x0350, 0x00C4, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__UART4_DCE_RTS = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0638, 0, 0), + MX6_PAD_ENET1_RX_DATA0__UART4_DTE_CTS = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__PWM1_OUT = IOMUX_PAD(0x0350, 0x00C4, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__CSI_DATA16 = IOMUX_PAD(0x0350, 0x00C4, 3, 0x0504, 0, 0), + MX6_PAD_ENET1_RX_DATA0__FLEXCAN1_TX = IOMUX_PAD(0x0350, 0x00C4, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 = IOMUX_PAD(0x0350, 0x00C4, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__KPP_ROW00 = IOMUX_PAD(0x0350, 0x00C4, 6, 0x05D0, 0, 0), + MX6_PAD_ENET1_RX_DATA0__USDHC1_LCTL = IOMUX_PAD(0x0350, 0x00C4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 = IOMUX_PAD(0x0354, 0x00C8, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__UART4_DCE_CTS = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__UART4_DTE_RTS = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0638, 1, 0), + MX6_PAD_ENET1_RX_DATA1__PWM2_OUT = IOMUX_PAD(0x0354, 0x00C8, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__CSI_DATA17 = IOMUX_PAD(0x0354, 0x00C8, 3, 0x0508, 0, 0), + MX6_PAD_ENET1_RX_DATA1__FLEXCAN1_RX = IOMUX_PAD(0x0354, 0x00C8, 4, 0x0584, 1, 0), + MX6_PAD_ENET1_RX_DATA1__GPIO2_IO01 = IOMUX_PAD(0x0354, 0x00C8, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__KPP_COL00 = IOMUX_PAD(0x0354, 0x00C8, 6, 0x05C4, 0, 0), + MX6_PAD_ENET1_RX_DATA1__USDHC2_LCTL = IOMUX_PAD(0x0354, 0x00C8, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN = IOMUX_PAD(0x0358, 0x00CC, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 3, 0), + MX6_PAD_ENET1_RX_EN__UART5_DTE_CTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__CSI_DATA18 = IOMUX_PAD(0x0358, 0x00CC, 3, 0x050C, 0, 0), + MX6_PAD_ENET1_RX_EN__FLEXCAN2_TX = IOMUX_PAD(0x0358, 0x00CC, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__GPIO2_IO02 = IOMUX_PAD(0x0358, 0x00CC, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__KPP_ROW01 = IOMUX_PAD(0x0358, 0x00CC, 6, 0x05D4, 0, 0), + MX6_PAD_ENET1_RX_EN__USDHC1_VSELECT = IOMUX_PAD(0x0358, 0x00CC, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 = IOMUX_PAD(0x035C, 0x00D0, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA0__UART5_DCE_CTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 4, 0), + MX6_PAD_ENET1_TX_DATA0__CSI_DATA19 = IOMUX_PAD(0x035C, 0x00D0, 3, 0x0510, 0, 0), + MX6_PAD_ENET1_TX_DATA0__FLEXCAN2_RX = IOMUX_PAD(0x035C, 0x00D0, 4, 0x0588, 1, 0), + MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03 = IOMUX_PAD(0x035C, 0x00D0, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA0__KPP_COL01 = IOMUX_PAD(0x035C, 0x00D0, 6, 0x05C8, 0, 0), + MX6_PAD_ENET1_TX_DATA0__USDHC2_VSELECT = IOMUX_PAD(0x035C, 0x00D0, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 = IOMUX_PAD(0x0360, 0x00D4, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__UART6_DCE_CTS = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__UART6_DTE_RTS = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0648, 2, 0), + MX6_PAD_ENET1_TX_DATA1__PWM5_OUT = IOMUX_PAD(0x0360, 0x00D4, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__CSI_DATA20 = IOMUX_PAD(0x0360, 0x00D4, 3, 0x0514, 0, 0), + MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO = IOMUX_PAD(0x0360, 0x00D4, 4, 0x0580, 1, 0), + MX6_PAD_ENET1_TX_DATA1__GPIO2_IO04 = IOMUX_PAD(0x0360, 0x00D4, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__KPP_ROW02 = IOMUX_PAD(0x0360, 0x00D4, 6, 0x05D8, 0, 0), + MX6_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0360, 0x00D4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN = IOMUX_PAD(0x0364, 0x00D8, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__UART6_DCE_RTS = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0648, 3, 0), + MX6_PAD_ENET1_TX_EN__UART6_DTE_CTS = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__PWM6_OUT = IOMUX_PAD(0x0364, 0x00D8, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__CSI_DATA21 = IOMUX_PAD(0x0364, 0x00D8, 3, 0x0518, 0, 0), + MX6_PAD_ENET1_TX_EN__ENET2_MDC = IOMUX_PAD(0x0364, 0x00D8, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__GPIO2_IO05 = IOMUX_PAD(0x0364, 0x00D8, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__KPP_COL02 = IOMUX_PAD(0x0364, 0x00D8, 6, 0x05CC, 0, 0), + MX6_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x0364, 0x00D8, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK = IOMUX_PAD(0x0368, 0x00DC, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__UART7_DCE_CTS = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__UART7_DTE_RTS = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0650, 0, 0), + MX6_PAD_ENET1_TX_CLK__PWM7_OUT = IOMUX_PAD(0x0368, 0x00DC, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__CSI_DATA22 = IOMUX_PAD(0x0368, 0x00DC, 3, 0x051C, 0, 0), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 = IOMUX_PAD(0x0368, 0x00DC, IOMUX_CONFIG_SION | 4, 0x0574, 2, 0), + MX6_PAD_ENET1_TX_CLK__GPIO2_IO06 = IOMUX_PAD(0x0368, 0x00DC, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__KPP_ROW03 = IOMUX_PAD(0x0368, 0x00DC, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__GPT1_CLK = IOMUX_PAD(0x0368, 0x00DC, 8, 0x0594, 1, 0), + + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER = IOMUX_PAD(0x036C, 0x00E0, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__UART7_DCE_RTS = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0650, 1, 0), + MX6_PAD_ENET1_RX_ER__UART7_DTE_CTS = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__PWM8_OUT = IOMUX_PAD(0x036C, 0x00E0, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__CSI_DATA23 = IOMUX_PAD(0x036C, 0x00E0, 3, 0x0520, 0, 0), + MX6_PAD_ENET1_RX_ER__EIM_CRE = IOMUX_PAD(0x036C, 0x00E0, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__GPIO2_IO07 = IOMUX_PAD(0x036C, 0x00E0, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__KPP_COL03 = IOMUX_PAD(0x036C, 0x00E0, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__GPT1_CAPTURE2 = IOMUX_PAD(0x036C, 0x00E0, 8, 0x0590, 1, 0), + + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 = IOMUX_PAD(0x0370, 0x00E4, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__UART6_DCE_TX = IOMUX_PAD(0x0370, 0x00E4, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__UART6_DTE_RX = IOMUX_PAD(0x0370, 0x00E4, 1, 0x064C, 1, 0), + MX6_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD = IOMUX_PAD(0x0370, 0x00E4, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__I2C3_SCL = IOMUX_PAD(0x0370, 0x00E4, IOMUX_CONFIG_SION | 3, 0x05B4, 1, 0), + MX6_PAD_ENET2_RX_DATA0__ENET1_MDIO = IOMUX_PAD(0x0370, 0x00E4, 4, 0x0578, 1, 0), + MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08 = IOMUX_PAD(0x0370, 0x00E4, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__KPP_ROW04 = IOMUX_PAD(0x0370, 0x00E4, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__USB_OTG1_PWR = IOMUX_PAD(0x0370, 0x00E4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 = IOMUX_PAD(0x0374, 0x00E8, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__UART6_DCE_RX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x064C, 2, 0), + MX6_PAD_ENET2_RX_DATA1__UART6_DTE_TX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK = IOMUX_PAD(0x0374, 0x00E8, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__I2C3_SDA = IOMUX_PAD(0x0374, 0x00E8, IOMUX_CONFIG_SION | 3, 0x05B8, 1, 0), + MX6_PAD_ENET2_RX_DATA1__ENET1_MDC = IOMUX_PAD(0x0374, 0x00E8, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09 = IOMUX_PAD(0x0374, 0x00E8, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__KPP_COL04 = IOMUX_PAD(0x0374, 0x00E8, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__USB_OTG1_OC = IOMUX_PAD(0x0374, 0x00E8, 8, 0x0664, 1, 0), + + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN = IOMUX_PAD(0x0378, 0x00EC, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__UART7_DCE_TX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__UART7_DTE_RX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0654, 0, 0), + MX6_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B = IOMUX_PAD(0x0378, 0x00EC, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__I2C4_SCL = IOMUX_PAD(0x0378, 0x00EC, IOMUX_CONFIG_SION | 3, 0x05BC, 1, 0), + MX6_PAD_ENET2_RX_EN__EIM_ADDR26 = IOMUX_PAD(0x0378, 0x00EC, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__GPIO2_IO10 = IOMUX_PAD(0x0378, 0x00EC, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__KPP_ROW05 = IOMUX_PAD(0x0378, 0x00EC, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M = IOMUX_PAD(0x0378, 0x00EC, 8, 0x0000, 0, 0), + + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 = IOMUX_PAD(0x037C, 0x00F0, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0654, 1, 0), + MX6_PAD_ENET2_TX_DATA0__UART7_DTE_TX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN = IOMUX_PAD(0x037C, 0x00F0, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__I2C4_SDA = IOMUX_PAD(0x037C, 0x00F0, IOMUX_CONFIG_SION | 3, 0x05C0, 1, 0), + MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02 = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11 = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__KPP_COL05 = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0), + + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__UART8_DTE_RX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x065C, 0, 0), + MX6_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD = IOMUX_PAD(0x0380, 0x00F4, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__ECSPI4_SCLK = IOMUX_PAD(0x0380, 0x00F4, 3, 0x0564, 0, 0), + MX6_PAD_ENET2_TX_DATA1__EIM_EB_B03 = IOMUX_PAD(0x0380, 0x00F4, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12 = IOMUX_PAD(0x0380, 0x00F4, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__KPP_ROW06 = IOMUX_PAD(0x0380, 0x00F4, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0380, 0x00F4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN = IOMUX_PAD(0x0384, 0x00F8, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__UART8_DCE_RX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x065C, 1, 0), + MX6_PAD_ENET2_TX_EN__UART8_DTE_TX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__SIM2_PORT0_CLK = IOMUX_PAD(0x0384, 0x00F8, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__ECSPI4_MOSI = IOMUX_PAD(0x0384, 0x00F8, 3, 0x056C, 0, 0), + MX6_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN = IOMUX_PAD(0x0384, 0x00F8, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__GPIO2_IO13 = IOMUX_PAD(0x0384, 0x00F8, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__KPP_COL06 = IOMUX_PAD(0x0384, 0x00F8, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__USB_OTG2_OC = IOMUX_PAD(0x0384, 0x00F8, 8, 0x0660, 1, 0), + + MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__UART8_DTE_RTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0658, 0, 0), + MX6_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B = IOMUX_PAD(0x0388, 0x00FC, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__ECSPI4_MISO = IOMUX_PAD(0x0388, 0x00FC, 3, 0x0568, 0, 0), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 4, 0x057C, 2, 0), + MX6_PAD_ENET2_TX_CLK__GPIO2_IO14 = IOMUX_PAD(0x0388, 0x00FC, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__KPP_ROW07 = IOMUX_PAD(0x0388, 0x00FC, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID = IOMUX_PAD(0x0388, 0x00FC, 8, 0x04BC, 1, 0), + + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER = IOMUX_PAD(0x038C, 0x0100, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0658, 1, 0), + MX6_PAD_ENET2_RX_ER__UART8_DTE_CTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN = IOMUX_PAD(0x038C, 0x0100, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__ECSPI4_SS0 = IOMUX_PAD(0x038C, 0x0100, 3, 0x0570, 0, 0), + MX6_PAD_ENET2_RX_ER__EIM_ADDR25 = IOMUX_PAD(0x038C, 0x0100, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__GPIO2_IO15 = IOMUX_PAD(0x038C, 0x0100, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__KPP_COL07 = IOMUX_PAD(0x038C, 0x0100, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY = IOMUX_PAD(0x038C, 0x0100, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_CLK__LCDIF_CLK = IOMUX_PAD(0x0390, 0x0104, 0, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__LCDIF_WR_RWN = IOMUX_PAD(0x0390, 0x0104, 1, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__UART4_DCE_TX = IOMUX_PAD(0x0390, 0x0104, 2, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__UART4_DTE_RX = IOMUX_PAD(0x0390, 0x0104, 2, 0x063C, 2, 0), + MX6_PAD_LCD_CLK__SAI3_MCLK = IOMUX_PAD(0x0390, 0x0104, 3, 0x0600, 0, 0), + MX6_PAD_LCD_CLK__EIM_CS2_B = IOMUX_PAD(0x0390, 0x0104, 4, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__GPIO3_IO00 = IOMUX_PAD(0x0390, 0x0104, 5, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0390, 0x0104, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE = IOMUX_PAD(0x0394, 0x0108, 0, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__LCDIF_RD_E = IOMUX_PAD(0x0394, 0x0108, 1, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__UART4_DCE_RX = IOMUX_PAD(0x0394, 0x0108, 2, 0x063C, 3, 0), + MX6_PAD_LCD_ENABLE__UART4_DTE_TX = IOMUX_PAD(0x0394, 0x0108, 2, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__SAI3_TX_SYNC = IOMUX_PAD(0x0394, 0x0108, 3, 0x060C, 0, 0), + MX6_PAD_LCD_ENABLE__EIM_CS3_B = IOMUX_PAD(0x0394, 0x0108, 4, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__GPIO3_IO01 = IOMUX_PAD(0x0394, 0x0108, 5, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__ECSPI2_RDY = IOMUX_PAD(0x0394, 0x0108, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC = IOMUX_PAD(0x0398, 0x010C, 0, 0x05DC, 0, 0), + MX6_PAD_LCD_HSYNC__LCDIF_RS = IOMUX_PAD(0x0398, 0x010C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__UART4_DCE_CTS = IOMUX_PAD(0x0398, 0x010C, 2, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__UART4_DTE_RTS = IOMUX_PAD(0x0398, 0x010C, 2, 0x0638, 2, 0), + MX6_PAD_LCD_HSYNC__SAI3_TX_BCLK = IOMUX_PAD(0x0398, 0x010C, 3, 0x0608, 0, 0), + MX6_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x0398, 0x010C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__GPIO3_IO02 = IOMUX_PAD(0x0398, 0x010C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__ECSPI2_SS1 = IOMUX_PAD(0x0398, 0x010C, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC = IOMUX_PAD(0x039C, 0x0110, 0, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__LCDIF_BUSY = IOMUX_PAD(0x039C, 0x0110, 1, 0x05DC, 1, 0), + MX6_PAD_LCD_VSYNC__UART4_DCE_RTS = IOMUX_PAD(0x039C, 0x0110, 2, 0x0638, 3, 0), + MX6_PAD_LCD_VSYNC__UART4_DTE_CTS = IOMUX_PAD(0x039C, 0x0110, 2, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__SAI3_RX_DATA = IOMUX_PAD(0x039C, 0x0110, 3, 0x0604, 0, 0), + MX6_PAD_LCD_VSYNC__WDOG2_WDOG_B = IOMUX_PAD(0x039C, 0x0110, 4, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__GPIO3_IO03 = IOMUX_PAD(0x039C, 0x0110, 5, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__ECSPI2_SS2 = IOMUX_PAD(0x039C, 0x0110, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_RESET__LCDIF_RESET = IOMUX_PAD(0x03A0, 0x0114, 0, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__LCDIF_CS = IOMUX_PAD(0x03A0, 0x0114, 1, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__CA7_MX6UL_EVENTI = IOMUX_PAD(0x03A0, 0x0114, 2, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__SAI3_TX_DATA = IOMUX_PAD(0x03A0, 0x0114, 3, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__WDOG1_WDOG_ANY = IOMUX_PAD(0x03A0, 0x0114, 4, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__GPIO3_IO04 = IOMUX_PAD(0x03A0, 0x0114, 5, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__ECSPI2_SS3 = IOMUX_PAD(0x03A0, 0x0114, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA00__LCDIF_DATA00 = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__PWM1_OUT = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x03A4, 0x0118, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__I2C3_SDA = IOMUX_PAD(0x03A4, 0x0118, IOMUX_CONFIG_SION | 4, 0x05B8, 2, 0), + MX6_PAD_LCD_DATA00__GPIO3_IO05 = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__SRC_BT_CFG00 = IOMUX_PAD(0x03A4, 0x0118, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__SAI1_MCLK = IOMUX_PAD(0x03A4, 0x0118, 8, 0x05E0, 1, 0), + + MX6_PAD_LCD_DATA01__LCDIF_DATA01 = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__PWM2_OUT = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x03A8, 0x011C, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__I2C3_SCL = IOMUX_PAD(0x03A8, 0x011C, IOMUX_CONFIG_SION | 4, 0x05B4, 2, 0), + MX6_PAD_LCD_DATA01__GPIO3_IO06 = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__SRC_BT_CFG01 = IOMUX_PAD(0x03A8, 0x011C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__SAI1_TX_SYNC = IOMUX_PAD(0x03A8, 0x011C, 8, 0x05EC, 0, 0), + + MX6_PAD_LCD_DATA02__LCDIF_DATA02 = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__PWM3_OUT = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x03AC, 0x0120, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__I2C4_SDA = IOMUX_PAD(0x03AC, 0x0120, IOMUX_CONFIG_SION | 4, 0x05C0, 2, 0), + MX6_PAD_LCD_DATA02__GPIO3_IO07 = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__SRC_BT_CFG02 = IOMUX_PAD(0x03AC, 0x0120, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__SAI1_TX_BCLK = IOMUX_PAD(0x03AC, 0x0120, 8, 0x05E8, 0, 0), + + MX6_PAD_LCD_DATA03__LCDIF_DATA03 = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__PWM4_OUT = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x03B0, 0x0124, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__I2C4_SCL = IOMUX_PAD(0x03B0, 0x0124, IOMUX_CONFIG_SION | 4, 0x05BC, 2, 0), + MX6_PAD_LCD_DATA03__GPIO3_IO08 = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__SRC_BT_CFG03 = IOMUX_PAD(0x03B0, 0x0124, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__SAI1_RX_DATA = IOMUX_PAD(0x03B0, 0x0124, 8, 0x05E4, 0, 0), + + MX6_PAD_LCD_DATA04__LCDIF_DATA04 = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__UART8_DCE_CTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__UART8_DTE_RTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0658, 2, 0), + MX6_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x03B4, 0x0128, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__SPDIF_SR_CLK = IOMUX_PAD(0x03B4, 0x0128, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__GPIO3_IO09 = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__SRC_BT_CFG04 = IOMUX_PAD(0x03B4, 0x0128, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__SAI1_TX_DATA = IOMUX_PAD(0x03B4, 0x0128, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA05__LCDIF_DATA05 = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__UART8_DCE_RTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0), + MX6_PAD_LCD_DATA05__UART8_DTE_CTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x03B8, 0x012C, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__SPDIF_OUT = IOMUX_PAD(0x03B8, 0x012C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__SRC_BT_CFG05 = IOMUX_PAD(0x03B8, 0x012C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__ECSPI1_SS1 = IOMUX_PAD(0x03B8, 0x012C, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA06__LCDIF_DATA06 = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__UART7_DCE_CTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__UART7_DTE_RTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0650, 2, 0), + MX6_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x03BC, 0x0130, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__SPDIF_LOCK = IOMUX_PAD(0x03BC, 0x0130, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__SRC_BT_CFG06 = IOMUX_PAD(0x03BC, 0x0130, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__ECSPI1_SS2 = IOMUX_PAD(0x03BC, 0x0130, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA07__LCDIF_DATA07 = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__UART7_DCE_RTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0), + MX6_PAD_LCD_DATA07__UART7_DTE_CTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x03C0, 0x0134, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__SPDIF_EXT_CLK = IOMUX_PAD(0x03C0, 0x0134, 4, 0x061C, 0, 0), + MX6_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__SRC_BT_CFG07 = IOMUX_PAD(0x03C0, 0x0134, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__ECSPI1_SS3 = IOMUX_PAD(0x03C0, 0x0134, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA08__LCDIF_DATA08 = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__SPDIF_IN = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0), + MX6_PAD_LCD_DATA08__CSI_DATA16 = IOMUX_PAD(0x03C4, 0x0138, 3, 0x0504, 1, 0), + MX6_PAD_LCD_DATA08__EIM_DATA00 = IOMUX_PAD(0x03C4, 0x0138, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__GPIO3_IO13 = IOMUX_PAD(0x03C4, 0x0138, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__SRC_BT_CFG08 = IOMUX_PAD(0x03C4, 0x0138, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__FLEXCAN1_TX = IOMUX_PAD(0x03C4, 0x0138, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA09__LCDIF_DATA09 = IOMUX_PAD(0x03C8, 0x013C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__SAI3_MCLK = IOMUX_PAD(0x03C8, 0x013C, 1, 0x0600, 1, 0), + MX6_PAD_LCD_DATA09__CSI_DATA17 = IOMUX_PAD(0x03C8, 0x013C, 3, 0x0508, 1, 0), + MX6_PAD_LCD_DATA09__EIM_DATA01 = IOMUX_PAD(0x03C8, 0x013C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__GPIO3_IO14 = IOMUX_PAD(0x03C8, 0x013C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__SRC_BT_CFG09 = IOMUX_PAD(0x03C8, 0x013C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__FLEXCAN1_RX = IOMUX_PAD(0x03C8, 0x013C, 8, 0x0584, 2, 0), + + MX6_PAD_LCD_DATA10__LCDIF_DATA10 = IOMUX_PAD(0x03CC, 0x0140, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__SAI3_RX_SYNC = IOMUX_PAD(0x03CC, 0x0140, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__CSI_DATA18 = IOMUX_PAD(0x03CC, 0x0140, 3, 0x050C, 1, 0), + MX6_PAD_LCD_DATA10__EIM_DATA02 = IOMUX_PAD(0x03CC, 0x0140, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__GPIO3_IO15 = IOMUX_PAD(0x03CC, 0x0140, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__SRC_BT_CFG10 = IOMUX_PAD(0x03CC, 0x0140, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__FLEXCAN2_TX = IOMUX_PAD(0x03CC, 0x0140, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA11__LCDIF_DATA11 = IOMUX_PAD(0x03D0, 0x0144, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__SAI3_RX_BCLK = IOMUX_PAD(0x03D0, 0x0144, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__CSI_DATA19 = IOMUX_PAD(0x03D0, 0x0144, 3, 0x0510, 1, 0), + MX6_PAD_LCD_DATA11__EIM_DATA03 = IOMUX_PAD(0x03D0, 0x0144, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__GPIO3_IO16 = IOMUX_PAD(0x03D0, 0x0144, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__SRC_BT_CFG11 = IOMUX_PAD(0x03D0, 0x0144, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__FLEXCAN2_RX = IOMUX_PAD(0x03D0, 0x0144, 8, 0x0588, 2, 0), + + MX6_PAD_LCD_DATA12__LCDIF_DATA12 = IOMUX_PAD(0x03D4, 0x0148, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__SAI3_TX_SYNC = IOMUX_PAD(0x03D4, 0x0148, 1, 0x060C, 1, 0), + MX6_PAD_LCD_DATA12__CSI_DATA20 = IOMUX_PAD(0x03D4, 0x0148, 3, 0x0514, 1, 0), + MX6_PAD_LCD_DATA12__EIM_DATA04 = IOMUX_PAD(0x03D4, 0x0148, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__GPIO3_IO17 = IOMUX_PAD(0x03D4, 0x0148, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__SRC_BT_CFG12 = IOMUX_PAD(0x03D4, 0x0148, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__ECSPI1_RDY = IOMUX_PAD(0x03D4, 0x0148, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA13__LCDIF_DATA13 = IOMUX_PAD(0x03D8, 0x014C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__SAI3_TX_BCLK = IOMUX_PAD(0x03D8, 0x014C, 1, 0x0608, 1, 0), + MX6_PAD_LCD_DATA13__CSI_DATA21 = IOMUX_PAD(0x03D8, 0x014C, 3, 0x0518, 1, 0), + MX6_PAD_LCD_DATA13__EIM_DATA05 = IOMUX_PAD(0x03D8, 0x014C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__GPIO3_IO18 = IOMUX_PAD(0x03D8, 0x014C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__SRC_BT_CFG13 = IOMUX_PAD(0x03D8, 0x014C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__USDHC2_RESET_B = IOMUX_PAD(0x03D8, 0x014C, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA14__LCDIF_DATA14 = IOMUX_PAD(0x03DC, 0x0150, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__SAI3_RX_DATA = IOMUX_PAD(0x03DC, 0x0150, 1, 0x0604, 1, 0), + MX6_PAD_LCD_DATA14__CSI_DATA22 = IOMUX_PAD(0x03DC, 0x0150, 3, 0x051C, 1, 0), + MX6_PAD_LCD_DATA14__EIM_DATA06 = IOMUX_PAD(0x03DC, 0x0150, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__SRC_BT_CFG14 = IOMUX_PAD(0x03DC, 0x0150, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__USDHC2_DATA4 = IOMUX_PAD(0x03DC, 0x0150, 8, 0x068C, 0, 0), + + MX6_PAD_LCD_DATA15__LCDIF_DATA15 = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__SAI3_TX_DATA = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__CSI_DATA23 = IOMUX_PAD(0x03E0, 0x0154, 3, 0x0520, 1, 0), + MX6_PAD_LCD_DATA15__EIM_DATA07 = IOMUX_PAD(0x03E0, 0x0154, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__SRC_BT_CFG15 = IOMUX_PAD(0x03E0, 0x0154, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__USDHC2_DATA5 = IOMUX_PAD(0x03E0, 0x0154, 8, 0x0690, 0, 0), + + MX6_PAD_LCD_DATA16__LCDIF_DATA16 = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__UART7_DCE_TX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__UART7_DTE_RX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0654, 2, 0), + MX6_PAD_LCD_DATA16__CSI_DATA01 = IOMUX_PAD(0x03E4, 0x0158, 3, 0x04D4, 1, 0), + MX6_PAD_LCD_DATA16__EIM_DATA08 = IOMUX_PAD(0x03E4, 0x0158, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__SRC_BT_CFG24 = IOMUX_PAD(0x03E4, 0x0158, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__USDHC2_DATA6 = IOMUX_PAD(0x03E4, 0x0158, 8, 0x0694, 0, 0), + + MX6_PAD_LCD_DATA17__LCDIF_DATA17 = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0), + MX6_PAD_LCD_DATA17__UART7_DTE_TX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__CSI_DATA00 = IOMUX_PAD(0x03E8, 0x015C, 3, 0x04D0, 1, 0), + MX6_PAD_LCD_DATA17__EIM_DATA09 = IOMUX_PAD(0x03E8, 0x015C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__SRC_BT_CFG25 = IOMUX_PAD(0x03E8, 0x015C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__USDHC2_DATA7 = IOMUX_PAD(0x03E8, 0x015C, 8, 0x0698, 0, 0), + + MX6_PAD_LCD_DATA18__LCDIF_DATA18 = IOMUX_PAD(0x03EC, 0x0160, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__PWM5_OUT = IOMUX_PAD(0x03EC, 0x0160, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__CA7_MX6UL_EVENTO = IOMUX_PAD(0x03EC, 0x0160, 2, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__CSI_DATA10 = IOMUX_PAD(0x03EC, 0x0160, 3, 0x04EC, 1, 0), + MX6_PAD_LCD_DATA18__EIM_DATA10 = IOMUX_PAD(0x03EC, 0x0160, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__GPIO3_IO23 = IOMUX_PAD(0x03EC, 0x0160, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__SRC_BT_CFG26 = IOMUX_PAD(0x03EC, 0x0160, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__USDHC2_CMD = IOMUX_PAD(0x03EC, 0x0160, 8, 0x0678, 1, 0), + MX6_PAD_LCD_DATA19__EIM_DATA11 = IOMUX_PAD(0x03F0, 0x0164, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__GPIO3_IO24 = IOMUX_PAD(0x03F0, 0x0164, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__SRC_BT_CFG27 = IOMUX_PAD(0x03F0, 0x0164, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__USDHC2_CLK = IOMUX_PAD(0x03F0, 0x0164, 8, 0x0670, 1, 0), + + MX6_PAD_LCD_DATA19__LCDIF_DATA19 = IOMUX_PAD(0x03F0, 0x0164, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__PWM6_OUT = IOMUX_PAD(0x03F0, 0x0164, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__WDOG1_WDOG_ANY = IOMUX_PAD(0x03F0, 0x0164, 2, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__CSI_DATA11 = IOMUX_PAD(0x03F0, 0x0164, 3, 0x04F0, 1, 0), + MX6_PAD_LCD_DATA20__EIM_DATA12 = IOMUX_PAD(0x03F4, 0x0168, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__GPIO3_IO25 = IOMUX_PAD(0x03F4, 0x0168, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__SRC_BT_CFG28 = IOMUX_PAD(0x03F4, 0x0168, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__USDHC2_DATA0 = IOMUX_PAD(0x03F4, 0x0168, 8, 0x067C, 1, 0), + + MX6_PAD_LCD_DATA20__LCDIF_DATA20 = IOMUX_PAD(0x03F4, 0x0168, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__UART8_DCE_TX = IOMUX_PAD(0x03F4, 0x0168, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__UART8_DTE_RX = IOMUX_PAD(0x03F4, 0x0168, 1, 0x065C, 2, 0), + MX6_PAD_LCD_DATA20__ECSPI1_SCLK = IOMUX_PAD(0x03F4, 0x0168, 2, 0x0534, 0, 0), + MX6_PAD_LCD_DATA20__CSI_DATA12 = IOMUX_PAD(0x03F4, 0x0168, 3, 0x04F4, 1, 0), + + MX6_PAD_LCD_DATA21__LCDIF_DATA21 = IOMUX_PAD(0x03F8, 0x016C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__UART8_DCE_RX = IOMUX_PAD(0x03F8, 0x016C, 1, 0x065C, 3, 0), + MX6_PAD_LCD_DATA21__UART8_DTE_TX = IOMUX_PAD(0x03F8, 0x016C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__ECSPI1_SS0 = IOMUX_PAD(0x03F8, 0x016C, 2, 0x0540, 0, 0), + MX6_PAD_LCD_DATA21__CSI_DATA13 = IOMUX_PAD(0x03F8, 0x016C, 3, 0x04F8, 1, 0), + MX6_PAD_LCD_DATA21__EIM_DATA13 = IOMUX_PAD(0x03F8, 0x016C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__GPIO3_IO26 = IOMUX_PAD(0x03F8, 0x016C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__SRC_BT_CFG29 = IOMUX_PAD(0x03F8, 0x016C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__USDHC2_DATA1 = IOMUX_PAD(0x03F8, 0x016C, 8, 0x0680, 1, 0), + + MX6_PAD_LCD_DATA22__LCDIF_DATA22 = IOMUX_PAD(0x03FC, 0x0170, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__MQS_RIGHT = IOMUX_PAD(0x03FC, 0x0170, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__ECSPI1_MOSI = IOMUX_PAD(0x03FC, 0x0170, 2, 0x053C, 0, 0), + MX6_PAD_LCD_DATA22__CSI_DATA14 = IOMUX_PAD(0x03FC, 0x0170, 3, 0x04FC, 1, 0), + MX6_PAD_LCD_DATA22__EIM_DATA14 = IOMUX_PAD(0x03FC, 0x0170, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__GPIO3_IO27 = IOMUX_PAD(0x03FC, 0x0170, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__SRC_BT_CFG30 = IOMUX_PAD(0x03FC, 0x0170, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__USDHC2_DATA2 = IOMUX_PAD(0x03FC, 0x0170, 8, 0x0684, 0, 0), + + MX6_PAD_LCD_DATA23__LCDIF_DATA23 = IOMUX_PAD(0x0400, 0x0174, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__MQS_LEFT = IOMUX_PAD(0x0400, 0x0174, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__ECSPI1_MISO = IOMUX_PAD(0x0400, 0x0174, 2, 0x0538, 0, 0), + MX6_PAD_LCD_DATA23__CSI_DATA15 = IOMUX_PAD(0x0400, 0x0174, 3, 0x0500, 1, 0), + MX6_PAD_LCD_DATA23__EIM_DATA15 = IOMUX_PAD(0x0400, 0x0174, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__GPIO3_IO28 = IOMUX_PAD(0x0400, 0x0174, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__SRC_BT_CFG31 = IOMUX_PAD(0x0400, 0x0174, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__USDHC2_DATA3 = IOMUX_PAD(0x0400, 0x0174, 8, 0x0688, 1, 0), + + MX6_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0404, 0x0178, 0, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__USDHC2_CLK = IOMUX_PAD(0x0404, 0x0178, 1, 0x0670, 2, 0), + MX6_PAD_NAND_RE_B__QSPI_B_SCLK = IOMUX_PAD(0x0404, 0x0178, 2, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__KPP_ROW00 = IOMUX_PAD(0x0404, 0x0178, 3, 0x05D0, 1, 0), + MX6_PAD_NAND_RE_B__EIM_EB_B00 = IOMUX_PAD(0x0404, 0x0178, 4, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__GPIO4_IO00 = IOMUX_PAD(0x0404, 0x0178, 5, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__ECSPI3_SS2 = IOMUX_PAD(0x0404, 0x0178, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x0408, 0x017C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__USDHC2_CMD = IOMUX_PAD(0x0408, 0x017C, 1, 0x0678, 2, 0), + MX6_PAD_NAND_WE_B__QSPI_B_SS0_B = IOMUX_PAD(0x0408, 0x017C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__KPP_COL00 = IOMUX_PAD(0x0408, 0x017C, 3, 0x05C4, 1, 0), + MX6_PAD_NAND_WE_B__EIM_EB_B01 = IOMUX_PAD(0x0408, 0x017C, 4, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__GPIO4_IO01 = IOMUX_PAD(0x0408, 0x017C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__ECSPI3_SS3 = IOMUX_PAD(0x0408, 0x017C, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x040C, 0x0180, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 = IOMUX_PAD(0x040C, 0x0180, 1, 0x067C, 2, 0), + MX6_PAD_NAND_DATA00__QSPI_B_SS1_B = IOMUX_PAD(0x040C, 0x0180, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__KPP_ROW01 = IOMUX_PAD(0x040C, 0x0180, 3, 0x05D4, 1, 0), + MX6_PAD_NAND_DATA00__EIM_AD08 = IOMUX_PAD(0x040C, 0x0180, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__GPIO4_IO02 = IOMUX_PAD(0x040C, 0x0180, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__ECSPI4_RDY = IOMUX_PAD(0x040C, 0x0180, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0410, 0x0184, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 = IOMUX_PAD(0x0410, 0x0184, 1, 0x0680, 2, 0), + MX6_PAD_NAND_DATA01__QSPI_B_DQS = IOMUX_PAD(0x0410, 0x0184, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__KPP_COL01 = IOMUX_PAD(0x0410, 0x0184, 3, 0x05C8, 1, 0), + MX6_PAD_NAND_DATA01__EIM_AD09 = IOMUX_PAD(0x0410, 0x0184, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__GPIO4_IO03 = IOMUX_PAD(0x0410, 0x0184, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__ECSPI4_SS1 = IOMUX_PAD(0x0410, 0x0184, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x0414, 0x0188, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 = IOMUX_PAD(0x0414, 0x0188, 1, 0x0684, 1, 0), + MX6_PAD_NAND_DATA02__QSPI_B_DATA00 = IOMUX_PAD(0x0414, 0x0188, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__KPP_ROW02 = IOMUX_PAD(0x0414, 0x0188, 3, 0x05D8, 1, 0), + MX6_PAD_NAND_DATA02__EIM_AD10 = IOMUX_PAD(0x0414, 0x0188, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__GPIO4_IO04 = IOMUX_PAD(0x0414, 0x0188, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__ECSPI4_SS2 = IOMUX_PAD(0x0414, 0x0188, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0418, 0x018C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 = IOMUX_PAD(0x0418, 0x018C, 1, 0x0688, 2, 0), + MX6_PAD_NAND_DATA03__QSPI_B_DATA01 = IOMUX_PAD(0x0418, 0x018C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__KPP_COL02 = IOMUX_PAD(0x0418, 0x018C, 3, 0x05CC, 1, 0), + MX6_PAD_NAND_DATA03__EIM_AD11 = IOMUX_PAD(0x0418, 0x018C, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__GPIO4_IO05 = IOMUX_PAD(0x0418, 0x018C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__ECSPI4_SS3 = IOMUX_PAD(0x0418, 0x018C, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x041C, 0x0190, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x041C, 0x0190, 1, 0x068C, 1, 0), + MX6_PAD_NAND_DATA04__QSPI_B_DATA02 = IOMUX_PAD(0x041C, 0x0190, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__ECSPI4_SCLK = IOMUX_PAD(0x041C, 0x0190, 3, 0x0564, 1, 0), + MX6_PAD_NAND_DATA04__EIM_AD12 = IOMUX_PAD(0x041C, 0x0190, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__GPIO4_IO06 = IOMUX_PAD(0x041C, 0x0190, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__UART2_DCE_TX = IOMUX_PAD(0x041C, 0x0190, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__UART2_DTE_RX = IOMUX_PAD(0x041C, 0x0190, 8, 0x062C, 2, 0), + + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0420, 0x0194, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x0420, 0x0194, 1, 0x0690, 1, 0), + MX6_PAD_NAND_DATA05__QSPI_B_DATA03 = IOMUX_PAD(0x0420, 0x0194, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__ECSPI4_MOSI = IOMUX_PAD(0x0420, 0x0194, 3, 0x056C, 1, 0), + MX6_PAD_NAND_DATA05__EIM_AD13 = IOMUX_PAD(0x0420, 0x0194, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__GPIO4_IO07 = IOMUX_PAD(0x0420, 0x0194, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__UART2_DCE_RX = IOMUX_PAD(0x0420, 0x0194, 8, 0x062C, 3, 0), + MX6_PAD_NAND_DATA05__UART2_DTE_TX = IOMUX_PAD(0x0420, 0x0194, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x0424, 0x0198, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x0424, 0x0198, 1, 0x0694, 1, 0), + MX6_PAD_NAND_DATA06__SAI2_RX_BCLK = IOMUX_PAD(0x0424, 0x0198, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__ECSPI4_MISO = IOMUX_PAD(0x0424, 0x0198, 3, 0x0568, 1, 0), + MX6_PAD_NAND_DATA06__EIM_AD14 = IOMUX_PAD(0x0424, 0x0198, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__GPIO4_IO08 = IOMUX_PAD(0x0424, 0x0198, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__UART2_DCE_CTS = IOMUX_PAD(0x0424, 0x0198, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__UART2_DTE_RTS = IOMUX_PAD(0x0424, 0x0198, 8, 0x0628, 4, 0), + + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0428, 0x019C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x0428, 0x019C, 1, 0x0698, 1, 0), + MX6_PAD_NAND_DATA07__QSPI_A_SS1_B = IOMUX_PAD(0x0428, 0x019C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__ECSPI4_SS0 = IOMUX_PAD(0x0428, 0x019C, 3, 0x0570, 1, 0), + MX6_PAD_NAND_DATA07__EIM_AD15 = IOMUX_PAD(0x0428, 0x019C, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__GPIO4_IO09 = IOMUX_PAD(0x0428, 0x019C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__UART2_DCE_RTS = IOMUX_PAD(0x0428, 0x019C, 8, 0x0628, 5, 0), + MX6_PAD_NAND_DATA07__UART2_DTE_CTS = IOMUX_PAD(0x0428, 0x019C, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x042C, 0x01A0, 0, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__USDHC2_RESET_B = IOMUX_PAD(0x042C, 0x01A0, 1, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__QSPI_A_DQS = IOMUX_PAD(0x042C, 0x01A0, 2, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__PWM3_OUT = IOMUX_PAD(0x042C, 0x01A0, 3, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__EIM_ADDR17 = IOMUX_PAD(0x042C, 0x01A0, 4, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__GPIO4_IO10 = IOMUX_PAD(0x042C, 0x01A0, 5, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__ECSPI3_SS1 = IOMUX_PAD(0x042C, 0x01A0, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x0430, 0x01A4, 0, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__USDHC1_RESET_B = IOMUX_PAD(0x0430, 0x01A4, 1, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__QSPI_A_SCLK = IOMUX_PAD(0x0430, 0x01A4, 2, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__PWM4_OUT = IOMUX_PAD(0x0430, 0x01A4, 3, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__EIM_BCLK = IOMUX_PAD(0x0430, 0x01A4, 4, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__GPIO4_IO11 = IOMUX_PAD(0x0430, 0x01A4, 5, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__ECSPI3_RDY = IOMUX_PAD(0x0430, 0x01A4, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x0434, 0x01A8, 0, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__USDHC1_DATA4 = IOMUX_PAD(0x0434, 0x01A8, 1, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 = IOMUX_PAD(0x0434, 0x01A8, 2, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__ECSPI3_SS0 = IOMUX_PAD(0x0434, 0x01A8, 3, 0x0560, 1, 0), + MX6_PAD_NAND_READY_B__EIM_CS1_B = IOMUX_PAD(0x0434, 0x01A8, 4, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__GPIO4_IO12 = IOMUX_PAD(0x0434, 0x01A8, 5, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__UART3_DCE_TX = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__UART3_DTE_RX = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0634, 2, 0), + + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0438, 0x01AC, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 = IOMUX_PAD(0x0438, 0x01AC, 1, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 = IOMUX_PAD(0x0438, 0x01AC, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__ECSPI3_SCLK = IOMUX_PAD(0x0438, 0x01AC, 3, 0x0554, 1, 0), + MX6_PAD_NAND_CE0_B__EIM_DTACK_B = IOMUX_PAD(0x0438, 0x01AC, 4, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__GPIO4_IO13 = IOMUX_PAD(0x0438, 0x01AC, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__UART3_DCE_RX = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0634, 3, 0), + MX6_PAD_NAND_CE0_B__UART3_DTE_TX = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x043C, 0x01B0, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 = IOMUX_PAD(0x043C, 0x01B0, 1, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 = IOMUX_PAD(0x043C, 0x01B0, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__ECSPI3_MOSI = IOMUX_PAD(0x043C, 0x01B0, 3, 0x055C, 1, 0), + MX6_PAD_NAND_CE1_B__EIM_ADDR18 = IOMUX_PAD(0x043C, 0x01B0, 4, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__GPIO4_IO14 = IOMUX_PAD(0x043C, 0x01B0, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__UART3_DCE_CTS = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__UART3_DTE_RTS = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0630, 2, 0), + + MX6_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0440, 0x01B4, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__USDHC1_DATA7 = IOMUX_PAD(0x0440, 0x01B4, 1, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__QSPI_A_DATA03 = IOMUX_PAD(0x0440, 0x01B4, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__ECSPI3_MISO = IOMUX_PAD(0x0440, 0x01B4, 3, 0x0558, 1, 0), + MX6_PAD_NAND_CLE__EIM_ADDR16 = IOMUX_PAD(0x0440, 0x01B4, 4, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__GPIO4_IO15 = IOMUX_PAD(0x0440, 0x01B4, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__UART3_DCE_RTS = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0630, 3, 0), + MX6_PAD_NAND_CLE__UART3_DTE_CTS = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0444, 0x01B8, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__CSI_FIELD = IOMUX_PAD(0x0444, 0x01B8, 1, 0x0530, 1, 0), + MX6_PAD_NAND_DQS__QSPI_A_SS0_B = IOMUX_PAD(0x0444, 0x01B8, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__PWM5_OUT = IOMUX_PAD(0x0444, 0x01B8, 3, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__EIM_WAIT = IOMUX_PAD(0x0444, 0x01B8, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__GPIO4_IO16 = IOMUX_PAD(0x0444, 0x01B8, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__SDMA_EXT_EVENT01 = IOMUX_PAD(0x0444, 0x01B8, 6, 0x0614, 1, 0), + MX6_PAD_NAND_DQS__SPDIF_EXT_CLK = IOMUX_PAD(0x0444, 0x01B8, 8, 0x061C, 1, 0), + + MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0448, 0x01BC, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPT2_COMPARE1 = IOMUX_PAD(0x0448, 0x01BC, 1, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__SAI2_RX_SYNC = IOMUX_PAD(0x0448, 0x01BC, 2, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__SPDIF_OUT = IOMUX_PAD(0x0448, 0x01BC, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__EIM_ADDR19 = IOMUX_PAD(0x0448, 0x01BC, 4, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPIO2_IO16 = IOMUX_PAD(0x0448, 0x01BC, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__SDMA_EXT_EVENT00 = IOMUX_PAD(0x0448, 0x01BC, 6, 0x0610, 2, 0), + MX6_PAD_SD1_CMD__USB_OTG1_PWR = IOMUX_PAD(0x0448, 0x01BC, 8, 0x0000, 0, 0), + + MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x044C, 0x01C0, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPT2_COMPARE2 = IOMUX_PAD(0x044C, 0x01C0, 1, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__SAI2_MCLK = IOMUX_PAD(0x044C, 0x01C0, 2, 0x05F0, 1, 0), + MX6_PAD_SD1_CLK__SPDIF_IN = IOMUX_PAD(0x044C, 0x01C0, 3, 0x0618, 3, 0), + MX6_PAD_SD1_CLK__EIM_ADDR20 = IOMUX_PAD(0x044C, 0x01C0, 4, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPIO2_IO17 = IOMUX_PAD(0x044C, 0x01C0, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__USB_OTG1_OC = IOMUX_PAD(0x044C, 0x01C0, 8, 0x0664, 2, 0), + + MX6_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0450, 0x01C4, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__GPT2_COMPARE3 = IOMUX_PAD(0x0450, 0x01C4, 1, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__SAI2_TX_SYNC = IOMUX_PAD(0x0450, 0x01C4, 2, 0x05FC, 1, 0), + MX6_PAD_SD1_DATA0__FLEXCAN1_TX = IOMUX_PAD(0x0450, 0x01C4, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__EIM_ADDR21 = IOMUX_PAD(0x0450, 0x01C4, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__GPIO2_IO18 = IOMUX_PAD(0x0450, 0x01C4, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID = IOMUX_PAD(0x0450, 0x01C4, 8, 0x04B8, 2, 0), + + MX6_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0454, 0x01C8, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__GPT2_CLK = IOMUX_PAD(0x0454, 0x01C8, 1, 0x05A0, 1, 0), + MX6_PAD_SD1_DATA1__SAI2_TX_BCLK = IOMUX_PAD(0x0454, 0x01C8, 2, 0x05F8, 1, 0), + MX6_PAD_SD1_DATA1__FLEXCAN1_RX = IOMUX_PAD(0x0454, 0x01C8, 3, 0x0584, 3, 0), + MX6_PAD_SD1_DATA1__EIM_ADDR22 = IOMUX_PAD(0x0454, 0x01C8, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__GPIO2_IO19 = IOMUX_PAD(0x0454, 0x01C8, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0454, 0x01C8, 8, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0458, 0x01CC, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__GPT2_CAPTURE1 = IOMUX_PAD(0x0458, 0x01CC, 1, 0x0598, 1, 0), + MX6_PAD_SD1_DATA2__SAI2_RX_DATA = IOMUX_PAD(0x0458, 0x01CC, 2, 0x05F4, 1, 0), + MX6_PAD_SD1_DATA2__FLEXCAN2_TX = IOMUX_PAD(0x0458, 0x01CC, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__EIM_ADDR23 = IOMUX_PAD(0x0458, 0x01CC, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__GPIO2_IO20 = IOMUX_PAD(0x0458, 0x01CC, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__CCM_CLKO1 = IOMUX_PAD(0x0458, 0x01CC, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__USB_OTG2_OC = IOMUX_PAD(0x0458, 0x01CC, 8, 0x0660, 2, 0), + + MX6_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x045C, 0x01D0, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__GPT2_CAPTURE2 = IOMUX_PAD(0x045C, 0x01D0, 1, 0x059C, 1, 0), + MX6_PAD_SD1_DATA3__SAI2_TX_DATA = IOMUX_PAD(0x045C, 0x01D0, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__FLEXCAN2_RX = IOMUX_PAD(0x045C, 0x01D0, 3, 0x0588, 3, 0), + MX6_PAD_SD1_DATA3__EIM_ADDR24 = IOMUX_PAD(0x045C, 0x01D0, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__GPIO2_IO21 = IOMUX_PAD(0x045C, 0x01D0, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__CCM_CLKO2 = IOMUX_PAD(0x045C, 0x01D0, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID = IOMUX_PAD(0x045C, 0x01D0, 8, 0x04BC, 2, 0), + + MX6_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x0460, 0x01D4, 0, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__USDHC2_CD_B = IOMUX_PAD(0x0460, 0x01D4, 1, 0x0674, 0, 0), + MX6_PAD_CSI_MCLK__RAWNAND_CE2_B = IOMUX_PAD(0x0460, 0x01D4, 2, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__I2C1_SDA = IOMUX_PAD(0x0460, 0x01D4, IOMUX_CONFIG_SION | 3, 0x05A8, 0, 0), + MX6_PAD_CSI_MCLK__EIM_CS0_B = IOMUX_PAD(0x0460, 0x01D4, 4, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__GPIO4_IO17 = IOMUX_PAD(0x0460, 0x01D4, 5, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL = IOMUX_PAD(0x0460, 0x01D4, 6, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__UART6_DCE_TX = IOMUX_PAD(0x0460, 0x01D4, 8, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__UART6_DTE_RX = IOMUX_PAD(0x0460, 0x01D4, 8, 0x064C, 0, 0), + + MX6_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x0464, 0x01D8, 0, 0x0528, 1, 0), + MX6_PAD_CSI_PIXCLK__USDHC2_WP = IOMUX_PAD(0x0464, 0x01D8, 1, 0x069C, 2, 0), + MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B = IOMUX_PAD(0x0464, 0x01D8, 2, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__I2C1_SCL = IOMUX_PAD(0x0464, 0x01D8, IOMUX_CONFIG_SION | 3, 0x05A4, 2, 0), + MX6_PAD_CSI_PIXCLK__EIM_OE = IOMUX_PAD(0x0464, 0x01D8, 4, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__GPIO4_IO18 = IOMUX_PAD(0x0464, 0x01D8, 5, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 = IOMUX_PAD(0x0464, 0x01D8, 6, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__UART6_DCE_RX = IOMUX_PAD(0x0464, 0x01D8, 8, 0x064C, 3, 0), + MX6_PAD_CSI_PIXCLK__UART6_DTE_TX = IOMUX_PAD(0x0464, 0x01D8, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x0468, 0x01DC, 0, 0x052C, 0, 0), + MX6_PAD_CSI_VSYNC__USDHC2_CLK = IOMUX_PAD(0x0468, 0x01DC, 1, 0x0670, 0, 0), + MX6_PAD_CSI_VSYNC__SIM1_PORT1_CLK = IOMUX_PAD(0x0468, 0x01DC, 2, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__I2C2_SDA = IOMUX_PAD(0x0468, 0x01DC, IOMUX_CONFIG_SION | 3, 0x05B0, 0, 0), + MX6_PAD_CSI_VSYNC__EIM_RW = IOMUX_PAD(0x0468, 0x01DC, 4, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__GPIO4_IO19 = IOMUX_PAD(0x0468, 0x01DC, 5, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__PWM7_OUT = IOMUX_PAD(0x0468, 0x01DC, 6, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__UART6_DCE_RTS = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0648, 0, 0), + MX6_PAD_CSI_VSYNC__UART6_DTE_CTS = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x046C, 0x01E0, 0, 0x0524, 0, 0), + MX6_PAD_CSI_HSYNC__USDHC2_CMD = IOMUX_PAD(0x046C, 0x01E0, 1, 0x0678, 0, 0), + MX6_PAD_CSI_HSYNC__SIM1_PORT1_PD = IOMUX_PAD(0x046C, 0x01E0, 2, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__I2C2_SCL = IOMUX_PAD(0x046C, 0x01E0, IOMUX_CONFIG_SION | 3, 0x05AC, 0, 0), + MX6_PAD_CSI_HSYNC__EIM_LBA_B = IOMUX_PAD(0x046C, 0x01E0, 4, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__GPIO4_IO20 = IOMUX_PAD(0x046C, 0x01E0, 5, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__PWM8_OUT = IOMUX_PAD(0x046C, 0x01E0, 6, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__UART6_DCE_CTS = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__UART6_DTE_RTS = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0648, 1, 0), + + MX6_PAD_CSI_DATA00__CSI_DATA02 = IOMUX_PAD(0x0470, 0x01E4, 0, 0x04C4, 0, 0), + MX6_PAD_CSI_DATA00__USDHC2_DATA0 = IOMUX_PAD(0x0470, 0x01E4, 1, 0x067C, 0, 0), + MX6_PAD_CSI_DATA00__SIM1_PORT1_RST_B = IOMUX_PAD(0x0470, 0x01E4, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__ECSPI2_SCLK = IOMUX_PAD(0x0470, 0x01E4, 3, 0x0544, 0, 0), + MX6_PAD_CSI_DATA00__EIM_AD00 = IOMUX_PAD(0x0470, 0x01E4, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__GPIO4_IO21 = IOMUX_PAD(0x0470, 0x01E4, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__SRC_INT_BOOT = IOMUX_PAD(0x0470, 0x01E4, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__UART5_DCE_TX = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__UART5_DTE_RX = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0644, 0, 0), + + MX6_PAD_CSI_DATA01__CSI_DATA03 = IOMUX_PAD(0x0474, 0x01E8, 0, 0x04C8, 0, 0), + MX6_PAD_CSI_DATA01__USDHC2_DATA1 = IOMUX_PAD(0x0474, 0x01E8, 1, 0x0680, 0, 0), + MX6_PAD_CSI_DATA01__SIM1_PORT1_SVEN = IOMUX_PAD(0x0474, 0x01E8, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__ECSPI2_SS0 = IOMUX_PAD(0x0474, 0x01E8, 3, 0x0550, 0, 0), + MX6_PAD_CSI_DATA01__EIM_AD01 = IOMUX_PAD(0x0474, 0x01E8, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__GPIO4_IO22 = IOMUX_PAD(0x0474, 0x01E8, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__SAI1_MCLK = IOMUX_PAD(0x0474, 0x01E8, 6, 0x05E0, 0, 0), + MX6_PAD_CSI_DATA01__UART5_DCE_RX = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0644, 1, 0), + MX6_PAD_CSI_DATA01__UART5_DTE_TX = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA02__CSI_DATA04 = IOMUX_PAD(0x0478, 0x01EC, 0, 0x04D8, 1, 0), + MX6_PAD_CSI_DATA02__USDHC2_DATA2 = IOMUX_PAD(0x0478, 0x01EC, 1, 0x0684, 2, 0), + MX6_PAD_CSI_DATA02__SIM1_PORT1_TRXD = IOMUX_PAD(0x0478, 0x01EC, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__ECSPI2_MOSI = IOMUX_PAD(0x0478, 0x01EC, 3, 0x054C, 1, 0), + MX6_PAD_CSI_DATA02__EIM_AD02 = IOMUX_PAD(0x0478, 0x01EC, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__GPIO4_IO23 = IOMUX_PAD(0x0478, 0x01EC, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__SAI1_RX_SYNC = IOMUX_PAD(0x0478, 0x01EC, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__UART5_DCE_RTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0640, 5, 0), + MX6_PAD_CSI_DATA02__UART5_DTE_CTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA03__CSI_DATA05 = IOMUX_PAD(0x047C, 0x01F0, 0, 0x04CC, 0, 0), + MX6_PAD_CSI_DATA03__USDHC2_DATA3 = IOMUX_PAD(0x047C, 0x01F0, 1, 0x0688, 0, 0), + MX6_PAD_CSI_DATA03__SIM2_PORT1_PD = IOMUX_PAD(0x047C, 0x01F0, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__ECSPI2_MISO = IOMUX_PAD(0x047C, 0x01F0, 3, 0x0548, 0, 0), + MX6_PAD_CSI_DATA03__EIM_AD03 = IOMUX_PAD(0x047C, 0x01F0, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__GPIO4_IO24 = IOMUX_PAD(0x047C, 0x01F0, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__SAI1_RX_BCLK = IOMUX_PAD(0x047C, 0x01F0, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__UART5_DCE_CTS = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__UART5_DTE_RTS = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0640, 0, 0), + + MX6_PAD_CSI_DATA04__CSI_DATA06 = IOMUX_PAD(0x0480, 0x01F4, 0, 0x04DC, 1, 0), + MX6_PAD_CSI_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x0480, 0x01F4, 1, 0x068C, 2, 0), + MX6_PAD_CSI_DATA04__SIM2_PORT1_CLK = IOMUX_PAD(0x0480, 0x01F4, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__ECSPI1_SCLK = IOMUX_PAD(0x0480, 0x01F4, 3, 0x0534, 1, 0), + MX6_PAD_CSI_DATA04__EIM_AD04 = IOMUX_PAD(0x0480, 0x01F4, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__GPIO4_IO25 = IOMUX_PAD(0x0480, 0x01F4, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__SAI1_TX_SYNC = IOMUX_PAD(0x0480, 0x01F4, 6, 0x05EC, 1, 0), + MX6_PAD_CSI_DATA04__USDHC1_WP = IOMUX_PAD(0x0480, 0x01F4, 8, 0x066C, 2, 0), + + MX6_PAD_CSI_DATA05__CSI_DATA07 = IOMUX_PAD(0x0484, 0x01F8, 0, 0x04E0, 1, 0), + MX6_PAD_CSI_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x0484, 0x01F8, 1, 0x0690, 2, 0), + MX6_PAD_CSI_DATA05__SIM2_PORT1_RST_B = IOMUX_PAD(0x0484, 0x01F8, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__ECSPI1_SS0 = IOMUX_PAD(0x0484, 0x01F8, 3, 0x0540, 1, 0), + MX6_PAD_CSI_DATA05__EIM_AD05 = IOMUX_PAD(0x0484, 0x01F8, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__GPIO4_IO26 = IOMUX_PAD(0x0484, 0x01F8, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__SAI1_TX_BCLK = IOMUX_PAD(0x0484, 0x01F8, 6, 0x05E8, 1, 0), + MX6_PAD_CSI_DATA05__USDHC1_CD_B = IOMUX_PAD(0x0484, 0x01F8, 8, 0x0668, 2, 0), + + MX6_PAD_CSI_DATA06__CSI_DATA08 = IOMUX_PAD(0x0488, 0x01FC, 0, 0x04E4, 1, 0), + MX6_PAD_CSI_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x0488, 0x01FC, 1, 0x0694, 2, 0), + MX6_PAD_CSI_DATA06__SIM2_PORT1_SVEN = IOMUX_PAD(0x0488, 0x01FC, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__ECSPI1_MOSI = IOMUX_PAD(0x0488, 0x01FC, 3, 0x053C, 1, 0), + MX6_PAD_CSI_DATA06__EIM_AD06 = IOMUX_PAD(0x0488, 0x01FC, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__GPIO4_IO27 = IOMUX_PAD(0x0488, 0x01FC, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__SAI1_RX_DATA = IOMUX_PAD(0x0488, 0x01FC, 6, 0x05E4, 1, 0), + MX6_PAD_CSI_DATA06__USDHC1_RESET_B = IOMUX_PAD(0x0488, 0x01FC, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA07__CSI_DATA09 = IOMUX_PAD(0x048C, 0x0200, 0, 0x04E8, 1, 0), + MX6_PAD_CSI_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x048C, 0x0200, 1, 0x0698, 2, 0), + MX6_PAD_CSI_DATA07__SIM2_PORT1_TRXD = IOMUX_PAD(0x048C, 0x0200, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__ECSPI1_MISO = IOMUX_PAD(0x048C, 0x0200, 3, 0x0538, 1, 0), + MX6_PAD_CSI_DATA07__EIM_AD07 = IOMUX_PAD(0x048C, 0x0200, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__GPIO4_IO28 = IOMUX_PAD(0x048C, 0x0200, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__SAI1_TX_DATA = IOMUX_PAD(0x048C, 0x0200, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__USDHC1_VSELECT = IOMUX_PAD(0x048C, 0x0200, 8, 0x0000, 0, 0), +}; +#endif /* __ASM_ARCH_IMX6UL_PINS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6ull_pins.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6ull_pins.h new file mode 100644 index 000000000..842d0caa6 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6ull_pins.h @@ -0,0 +1,1064 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#ifndef __ASM_ARCH_IMX6ULL_PINS_H__ +#define __ASM_ARCH_IMX6ULL_PINS_H__ + +#include + +enum { + MX6_PAD_BOOT_MODE0__GPIO5_IO10 = IOMUX_PAD(0x0044, 0x0000, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_BOOT_MODE1__GPIO5_IO11 = IOMUX_PAD(0x0048, 0x0004, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + + /* + * The TAMPER Pin can be used for GPIO, which depends on + * TAMPER_PIN_DISABLE[1:0] settings. + */ + MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 = IOMUX_PAD(0x004C, 0x0008, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 = IOMUX_PAD(0x0050, 0x000C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 = IOMUX_PAD(0x0054, 0x0010, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 = IOMUX_PAD(0x0058, 0x0014, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 = IOMUX_PAD(0x005C, 0x0018, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 = IOMUX_PAD(0x0060, 0x001C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 = IOMUX_PAD(0x0064, 0x0020, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 = IOMUX_PAD(0x0068, 0x0024, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 = IOMUX_PAD(0x006C, 0x0028, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 = IOMUX_PAD(0x0070, 0x002C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + + MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x02D0, 0x0044, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__GPT2_CLK = IOMUX_PAD(0x02D0, 0x0044, 1, 0x05A0, 0, 0), + MX6_PAD_JTAG_MOD__SPDIF_OUT = IOMUX_PAD(0x02D0, 0x0044, 2, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__ENET1_REF_CLK_25M = IOMUX_PAD(0x02D0, 0x0044, 3, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__CCM_PMIC_RDY = IOMUX_PAD(0x02D0, 0x0044, 4, 0x04C0, 0, 0), + MX6_PAD_JTAG_MOD__GPIO1_IO10 = IOMUX_PAD(0x02D0, 0x0044, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__SDMA_EXT_EVENT00 = IOMUX_PAD(0x02D0, 0x0044, 6, 0x0610, 0, 0), + + MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x02D4, 0x0048, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__GPT2_CAPTURE1 = IOMUX_PAD(0x02D4, 0x0048, 1, 0x0598, 0, 0), + MX6_PAD_JTAG_TMS__SAI2_MCLK = IOMUX_PAD(0x02D4, 0x0048, 2, 0x05F0, 0, 0), + MX6_PAD_JTAG_TMS__CCM_CLKO1 = IOMUX_PAD(0x02D4, 0x0048, 3, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__CCM_WAIT = IOMUX_PAD(0x02D4, 0x0048, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__GPIO1_IO11 = IOMUX_PAD(0x02D4, 0x0048, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__SDMA_EXT_EVENT01 = IOMUX_PAD(0x02D4, 0x0048, 6, 0x0614, 0, 0), + MX6_PAD_JTAG_TMS__EPIT1_OUT = IOMUX_PAD(0x02D4, 0x0048, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x02D8, 0x004C, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__GPT2_CAPTURE2 = IOMUX_PAD(0x02D8, 0x004C, 1, 0x059C, 0, 0), + MX6_PAD_JTAG_TDO__SAI2_TX_SYNC = IOMUX_PAD(0x02D8, 0x004C, 2, 0x05FC, 0, 0), + MX6_PAD_JTAG_TDO__CCM_CLKO2 = IOMUX_PAD(0x02D8, 0x004C, 3, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__CCM_STOP = IOMUX_PAD(0x02D8, 0x004C, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__GPIO1_IO12 = IOMUX_PAD(0x02D8, 0x004C, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__MQS_RIGHT = IOMUX_PAD(0x02D8, 0x004C, 6, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__EPIT2_OUT = IOMUX_PAD(0x02D8, 0x004C, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x02DC, 0x0050, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__GPT2_COMPARE1 = IOMUX_PAD(0x02DC, 0x0050, 1, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__SAI2_TX_BCLK = IOMUX_PAD(0x02DC, 0x0050, 2, 0x05F8, 0, 0), + MX6_PAD_JTAG_TDI__PWM6_OUT = IOMUX_PAD(0x02DC, 0x0050, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__GPIO1_IO13 = IOMUX_PAD(0x02DC, 0x0050, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__MQS_LEFT = IOMUX_PAD(0x02DC, 0x0050, 6, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__SIM1_POWER_FAIL = IOMUX_PAD(0x02DC, 0x0050, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x02E0, 0x0054, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__GPT2_COMPARE2 = IOMUX_PAD(0x02E0, 0x0054, 1, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__SAI2_RX_DATA = IOMUX_PAD(0x02E0, 0x0054, 2, 0x05F4, 0, 0), + MX6_PAD_JTAG_TCK__PWM7_OUT = IOMUX_PAD(0x02E0, 0x0054, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__GPIO1_IO14 = IOMUX_PAD(0x02E0, 0x0054, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__SIM2_POWER_FAIL = IOMUX_PAD(0x02E0, 0x0054, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TRST_B__SJC_TRSTB = IOMUX_PAD(0x02E4, 0x0058, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__GPT2_COMPARE3 = IOMUX_PAD(0x02E4, 0x0058, 1, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__SAI2_TX_DATA = IOMUX_PAD(0x02E4, 0x0058, 2, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__PWM8_OUT = IOMUX_PAD(0x02E4, 0x0058, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__GPIO1_IO15 = IOMUX_PAD(0x02E4, 0x0058, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x02E4, 0x0058, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO00__I2C2_SCL = IOMUX_PAD(0x02E8, 0x005C, IOMUX_CONFIG_SION | 0, 0x05AC, 1, 0), + MX6_PAD_GPIO1_IO00__GPT1_CAPTURE1 = IOMUX_PAD(0x02E8, 0x005C, 1, 0x058C, 0, 0), + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID = IOMUX_PAD(0x02E8, 0x005C, 2, 0x04B8, 0, 0), + MX6_PAD_GPIO1_IO00__ENET1_REF_CLK1 = IOMUX_PAD(0x02E8, 0x005C, 3, 0x0574, 0, 0), + MX6_PAD_GPIO1_IO00__MQS_RIGHT = IOMUX_PAD(0x02E8, 0x005C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__GPIO1_IO00 = IOMUX_PAD(0x02E8, 0x005C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02E8, 0x005C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__SRC_SYSTEM_RESET = IOMUX_PAD(0x02E8, 0x005C, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__WDOG3_WDOG_B = IOMUX_PAD(0x02E8, 0x005C, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO01__I2C2_SDA = IOMUX_PAD(0x02EC, 0x0060, IOMUX_CONFIG_SION | 0, 0x05B0, 1, 0), + MX6_PAD_GPIO1_IO01__GPT1_COMPARE1 = IOMUX_PAD(0x02EC, 0x0060, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__USB_OTG1_OC = IOMUX_PAD(0x02EC, 0x0060, 2, 0x0664, 0, 0), + MX6_PAD_GPIO1_IO01__ENET2_REF_CLK2 = IOMUX_PAD(0x02EC, 0x0060, 3, 0x057C, 0, 0), + MX6_PAD_GPIO1_IO01__MQS_LEFT = IOMUX_PAD(0x02EC, 0x0060, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__GPIO1_IO01 = IOMUX_PAD(0x02EC, 0x0060, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02EC, 0x0060, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__SRC_EARLY_RESET = IOMUX_PAD(0x02EC, 0x0060, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__WDOG1_WDOG_B = IOMUX_PAD(0x02EC, 0x0060, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO02__I2C1_SCL = IOMUX_PAD(0x02F0, 0x0064, IOMUX_CONFIG_SION | 0, 0x05A4, 0, 0), + MX6_PAD_GPIO1_IO02__GPT1_COMPARE2 = IOMUX_PAD(0x02F0, 0x0064, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__USB_OTG2_PWR = IOMUX_PAD(0x02F0, 0x0064, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__ENET1_REF_CLK_25M = IOMUX_PAD(0x02F0, 0x0064, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__USDHC1_WP = IOMUX_PAD(0x02F0, 0x0064, 4, 0x066C, 0, 0), + MX6_PAD_GPIO1_IO02__GPIO1_IO02 = IOMUX_PAD(0x02F0, 0x0064, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 = IOMUX_PAD(0x02F0, 0x0064, 6, 0x0610, 1, 0), + MX6_PAD_GPIO1_IO02__SRC_ANY_PU_RESET = IOMUX_PAD(0x02F0, 0x0064, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__UART1_DCE_TX = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__UART1_DTE_RX = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0624, 0, 0), + + MX6_PAD_GPIO1_IO03__I2C1_SDA = IOMUX_PAD(0x02F4, 0x0068, IOMUX_CONFIG_SION | 0, 0x05A8, 1, 0), + MX6_PAD_GPIO1_IO03__GPT1_COMPARE3 = IOMUX_PAD(0x02F4, 0x0068, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__USB_OTG2_OC = IOMUX_PAD(0x02F4, 0x0068, 2, 0x0660, 0, 0), + MX6_PAD_GPIO1_IO03__USDHC1_CD_B = IOMUX_PAD(0x02F4, 0x0068, 4, 0x0668, 0, 0), + MX6_PAD_GPIO1_IO03__GPIO1_IO03 = IOMUX_PAD(0x02F4, 0x0068, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK = IOMUX_PAD(0x02F4, 0x0068, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__SRC_TESTER_ACK = IOMUX_PAD(0x02F4, 0x0068, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__UART1_DCE_RX = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0624, 1, 0), + MX6_PAD_GPIO1_IO03__UART1_DTE_TX = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO04__ENET1_REF_CLK1 = IOMUX_PAD(0x02F8, 0x006C, 0, 0x0574, 1, 0), + MX6_PAD_GPIO1_IO04__PWM3_OUT = IOMUX_PAD(0x02F8, 0x006C, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__USB_OTG1_PWR = IOMUX_PAD(0x02F8, 0x006C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__USDHC1_RESET_B = IOMUX_PAD(0x02F8, 0x006C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__GPIO1_IO04 = IOMUX_PAD(0x02F8, 0x006C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x02F8, 0x006C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__UART5_DCE_TX = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__UART5_DTE_RX = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0644, 2, 0), + + MX6_PAD_GPIO1_IO05__ENET2_REF_CLK2 = IOMUX_PAD(0x02FC, 0x0070, 0, 0x057C, 1, 0), + MX6_PAD_GPIO1_IO05__PWM4_OUT = IOMUX_PAD(0x02FC, 0x0070, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID = IOMUX_PAD(0x02FC, 0x0070, 2, 0x04BC, 0, 0), + MX6_PAD_GPIO1_IO05__CSI_FIELD = IOMUX_PAD(0x02FC, 0x0070, 3, 0x0530, 0, 0), + MX6_PAD_GPIO1_IO05__USDHC1_VSELECT = IOMUX_PAD(0x02FC, 0x0070, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__GPIO1_IO05 = IOMUX_PAD(0x02FC, 0x0070, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x02FC, 0x0070, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__UART5_DCE_RX = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0644, 3, 0), + MX6_PAD_GPIO1_IO05__UART5_DTE_TX = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO06__ENET1_MDIO = IOMUX_PAD(0x0300, 0x0074, 0, 0x0578, 0, 0), + MX6_PAD_GPIO1_IO06__ENET2_MDIO = IOMUX_PAD(0x0300, 0x0074, 1, 0x0580, 0, 0), + MX6_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE = IOMUX_PAD(0x0300, 0x0074, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__CSI_MCLK = IOMUX_PAD(0x0300, 0x0074, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__USDHC2_WP = IOMUX_PAD(0x0300, 0x0074, 4, 0x069C, 0, 0), + MX6_PAD_GPIO1_IO06__GPIO1_IO06 = IOMUX_PAD(0x0300, 0x0074, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__CCM_WAIT = IOMUX_PAD(0x0300, 0x0074, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__CCM_REF_EN_B = IOMUX_PAD(0x0300, 0x0074, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__UART1_DCE_CTS = IOMUX_PAD(0x0300, 0x0074, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__UART1_DTE_RTS = IOMUX_PAD(0x0300, 0x0074, 8, 0x0620, 0, 0), + + MX6_PAD_GPIO1_IO07__ENET1_MDC = IOMUX_PAD(0x0304, 0x0078, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__ENET2_MDC = IOMUX_PAD(0x0304, 0x0078, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__USB_OTG_HOST_MODE = IOMUX_PAD(0x0304, 0x0078, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__CSI_PIXCLK = IOMUX_PAD(0x0304, 0x0078, 3, 0x0528, 0, 0), + MX6_PAD_GPIO1_IO07__USDHC2_CD_B = IOMUX_PAD(0x0304, 0x0078, 4, 0x0674, 1, 0), + MX6_PAD_GPIO1_IO07__GPIO1_IO07 = IOMUX_PAD(0x0304, 0x0078, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__CCM_STOP = IOMUX_PAD(0x0304, 0x0078, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__UART1_DCE_RTS = IOMUX_PAD(0x0304, 0x0078, 8, 0x0620, 1, 0), + MX6_PAD_GPIO1_IO07__UART1_DTE_CTS = IOMUX_PAD(0x0304, 0x0078, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x0308, 0x007C, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__WDOG1_WDOG_B = IOMUX_PAD(0x0308, 0x007C, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__SPDIF_OUT = IOMUX_PAD(0x0308, 0x007C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__CSI_VSYNC = IOMUX_PAD(0x0308, 0x007C, 3, 0x052C, 1, 0), + MX6_PAD_GPIO1_IO08__USDHC2_VSELECT = IOMUX_PAD(0x0308, 0x007C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__GPIO1_IO08 = IOMUX_PAD(0x0308, 0x007C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__CCM_PMIC_RDY = IOMUX_PAD(0x0308, 0x007C, 6, 0x04C0, 1, 0), + MX6_PAD_GPIO1_IO08__UART5_DCE_RTS = IOMUX_PAD(0x0308, 0x007C, 8, 0x0640, 1, 0), + MX6_PAD_GPIO1_IO08__UART5_DTE_CTS = IOMUX_PAD(0x0308, 0x007C, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x030C, 0x0080, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__WDOG1_WDOG_ANY = IOMUX_PAD(0x030C, 0x0080, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__SPDIF_IN = IOMUX_PAD(0x030C, 0x0080, 2, 0x0618, 0, 0), + MX6_PAD_GPIO1_IO09__CSI_HSYNC = IOMUX_PAD(0x030C, 0x0080, 3, 0x0524, 1, 0), + MX6_PAD_GPIO1_IO09__USDHC2_RESET_B = IOMUX_PAD(0x030C, 0x0080, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__GPIO1_IO09 = IOMUX_PAD(0x030C, 0x0080, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__USDHC1_RESET_B = IOMUX_PAD(0x030C, 0x0080, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__UART5_DCE_CTS = IOMUX_PAD(0x030C, 0x0080, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__UART5_DTE_RTS = IOMUX_PAD(0x030C, 0x0080, 8, 0x0640, 2, 0), + + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX = IOMUX_PAD(0x0310, 0x0084, 0, 0x0000, 0, 0), + + MX6_PAD_UART1_TX_DATA__UART1_DTE_RX = IOMUX_PAD(0x0310, 0x0084, 0, 0x0624, 2, 0), + MX6_PAD_UART1_TX_DATA__ENET1_RDATA02 = IOMUX_PAD(0x0310, 0x0084, 1, 0x0000, 0, 0), + MX6_PAD_UART1_TX_DATA__I2C3_SCL = IOMUX_PAD(0x0310, 0x0084, IOMUX_CONFIG_SION | 2, 0x05B4, 0, 0), + MX6_PAD_UART1_TX_DATA__CSI_DATA02 = IOMUX_PAD(0x0310, 0x0084, 3, 0x04C4, 1, 0), + MX6_PAD_UART1_TX_DATA__GPT1_COMPARE1 = IOMUX_PAD(0x0310, 0x0084, 4, 0x0000, 0, 0), + MX6_PAD_UART1_TX_DATA__GPIO1_IO16 = IOMUX_PAD(0x0310, 0x0084, 5, 0x0000, 0, 0), + MX6_PAD_UART1_TX_DATA__SPDIF_OUT = IOMUX_PAD(0x0310, 0x0084, 8, 0x0000, 0, 0), + + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0314, 0x0088, 0, 0x0624, 3, 0), + + MX6_PAD_UART1_RX_DATA__UART1_DTE_TX = IOMUX_PAD(0x0314, 0x0088, 0, 0x0000, 0, 0), + MX6_PAD_UART1_RX_DATA__ENET1_RDATA03 = IOMUX_PAD(0x0314, 0x0088, 1, 0x0000, 0, 0), + MX6_PAD_UART1_RX_DATA__I2C3_SDA = IOMUX_PAD(0x0314, 0x0088, IOMUX_CONFIG_SION | 2, 0x05B8, 0, 0), + MX6_PAD_UART1_RX_DATA__CSI_DATA03 = IOMUX_PAD(0x0314, 0x0088, 3, 0x04C8, 1, 0), + MX6_PAD_UART1_RX_DATA__GPT1_CLK = IOMUX_PAD(0x0314, 0x0088, 4, 0x0594, 0, 0), + MX6_PAD_UART1_RX_DATA__GPIO1_IO17 = IOMUX_PAD(0x0314, 0x0088, 5, 0x0000, 0, 0), + MX6_PAD_UART1_RX_DATA__SPDIF_IN = IOMUX_PAD(0x0314, 0x0088, 8, 0x0618, 1, 0), + + MX6_PAD_UART1_CTS_B__UART1_DCE_CTS = IOMUX_PAD(0x0318, 0x008C, 0, 0x0000, 0, 0), + + MX6_PAD_UART1_CTS_B__UART1_DTE_RTS = IOMUX_PAD(0x0318, 0x008C, 0, 0x0620, 2, 0), + MX6_PAD_UART1_CTS_B__ENET1_RX_CLK = IOMUX_PAD(0x0318, 0x008C, 1, 0x0000, 0, 0), + MX6_PAD_UART1_CTS_B__USDHC1_WP = IOMUX_PAD(0x0318, 0x008C, 2, 0x066C, 1, 0), + MX6_PAD_UART1_CTS_B__CSI_DATA04 = IOMUX_PAD(0x0318, 0x008C, 3, 0x04D8, 0, 0), + MX6_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x0318, 0x008C, 4, 0x0000, 0, 0), + MX6_PAD_UART1_CTS_B__GPIO1_IO18 = IOMUX_PAD(0x0318, 0x008C, 5, 0x0000, 0, 0), + MX6_PAD_UART1_CTS_B__USDHC2_WP = IOMUX_PAD(0x0318, 0x008C, 8, 0x069C, 1, 0), + + MX6_PAD_UART1_RTS_B__UART1_DCE_RTS = IOMUX_PAD(0x031C, 0x0090, 0, 0x0620, 3, 0), + + MX6_PAD_UART1_RTS_B__UART1_DTE_CTS = IOMUX_PAD(0x031C, 0x0090, 0, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__ENET1_TX_ER = IOMUX_PAD(0x031C, 0x0090, 1, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__USDHC1_CD_B = IOMUX_PAD(0x031C, 0x0090, 2, 0x0668, 1, 0), + MX6_PAD_UART1_RTS_B__CSI_DATA05 = IOMUX_PAD(0x031C, 0x0090, 3, 0x04CC, 1, 0), + MX6_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x031C, 0x0090, 4, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__GPIO1_IO19 = IOMUX_PAD(0x031C, 0x0090, 5, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__USDHC2_CD_B = IOMUX_PAD(0x031C, 0x0090, 8, 0x0674, 2, 0), + + MX6_PAD_UART2_TX_DATA__UART2_DCE_TX = IOMUX_PAD(0x0320, 0x0094, 0, 0x0000, 0, 0), + + MX6_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x0320, 0x0094, 0, 0x062C, 0, 0), + MX6_PAD_UART2_TX_DATA__ENET1_TDATA02 = IOMUX_PAD(0x0320, 0x0094, 1, 0x0000, 0, 0), + MX6_PAD_UART2_TX_DATA__I2C4_SCL = IOMUX_PAD(0x0320, 0x0094, IOMUX_CONFIG_SION | 2, 0x05BC, 0, 0), + MX6_PAD_UART2_TX_DATA__CSI_DATA06 = IOMUX_PAD(0x0320, 0x0094, 3, 0x04DC, 0, 0), + MX6_PAD_UART2_TX_DATA__GPT1_CAPTURE1 = IOMUX_PAD(0x0320, 0x0094, 4, 0x058C, 1, 0), + MX6_PAD_UART2_TX_DATA__GPIO1_IO20 = IOMUX_PAD(0x0320, 0x0094, 5, 0x0000, 0, 0), + MX6_PAD_UART2_TX_DATA__ECSPI3_SS0 = IOMUX_PAD(0x0320, 0x0094, 8, 0x0560, 0, 0), + + MX6_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x0324, 0x0098, 0, 0x062C, 1, 0), + + MX6_PAD_UART2_RX_DATA__UART2_DTE_TX = IOMUX_PAD(0x0324, 0x0098, 0, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__ENET1_TDATA03 = IOMUX_PAD(0x0324, 0x0098, 1, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__I2C4_SDA = IOMUX_PAD(0x0324, 0x0098, IOMUX_CONFIG_SION | 2, 0x05C0, 0, 0), + MX6_PAD_UART2_RX_DATA__CSI_DATA07 = IOMUX_PAD(0x0324, 0x0098, 3, 0x04E0, 0, 0), + MX6_PAD_UART2_RX_DATA__GPT1_CAPTURE2 = IOMUX_PAD(0x0324, 0x0098, 4, 0x0590, 0, 0), + MX6_PAD_UART2_RX_DATA__GPIO1_IO21 = IOMUX_PAD(0x0324, 0x0098, 5, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__SJC_DONE = IOMUX_PAD(0x0324, 0x0098, 7, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__ECSPI3_SCLK = IOMUX_PAD(0x0324, 0x0098, 8, 0x0554, 0, 0), + + MX6_PAD_UART2_CTS_B__UART2_DCE_CTS = IOMUX_PAD(0x0328, 0x009C, 0, 0x0000, 0, 0), + + MX6_PAD_UART2_CTS_B__UART2_DTE_RTS = IOMUX_PAD(0x0328, 0x009C, 0, 0x0628, 0, 0), + MX6_PAD_UART2_CTS_B__ENET1_CRS = IOMUX_PAD(0x0328, 0x009C, 1, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__FLEXCAN2_TX = IOMUX_PAD(0x0328, 0x009C, 2, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__CSI_DATA08 = IOMUX_PAD(0x0328, 0x009C, 3, 0x04E4, 0, 0), + MX6_PAD_UART2_CTS_B__GPT1_COMPARE2 = IOMUX_PAD(0x0328, 0x009C, 4, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__GPIO1_IO22 = IOMUX_PAD(0x0328, 0x009C, 5, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__SJC_DE_B = IOMUX_PAD(0x0328, 0x009C, 7, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__ECSPI3_MOSI = IOMUX_PAD(0x0328, 0x009C, 8, 0x055C, 0, 0), + + MX6_PAD_UART2_RTS_B__UART2_DCE_RTS = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0628, 1, 0), + + MX6_PAD_UART2_RTS_B__UART2_DTE_CTS = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__ENET1_COL = IOMUX_PAD(0x032C, 0x00A0, 1, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__FLEXCAN2_RX = IOMUX_PAD(0x032C, 0x00A0, 2, 0x0588, 0, 0), + MX6_PAD_UART2_RTS_B__CSI_DATA09 = IOMUX_PAD(0x032C, 0x00A0, 3, 0x04E8, 0, 0), + MX6_PAD_UART2_RTS_B__GPT1_COMPARE3 = IOMUX_PAD(0x032C, 0x00A0, 4, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__GPIO1_IO23 = IOMUX_PAD(0x032C, 0x00A0, 5, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__SJC_FAIL = IOMUX_PAD(0x032C, 0x00A0, 7, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__ECSPI3_MISO = IOMUX_PAD(0x032C, 0x00A0, 8, 0x0558, 0, 0), + + MX6_PAD_UART3_TX_DATA__UART3_DCE_TX = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0000, 0, 0), + + MX6_PAD_UART3_TX_DATA__UART3_DTE_RX = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0634, 0, 0), + MX6_PAD_UART3_TX_DATA__ENET2_RDATA02 = IOMUX_PAD(0x0330, 0x00A4, 1, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__SIM1_PORT0_PD = IOMUX_PAD(0x0330, 0x00A4, 2, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__CSI_DATA01 = IOMUX_PAD(0x0330, 0x00A4, 3, 0x04D4, 0, 0), + MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__UART2_DTE_RTS = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0628, 2, 0), + MX6_PAD_UART3_TX_DATA__GPIO1_IO24 = IOMUX_PAD(0x0330, 0x00A4, 5, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__SJC_JTAG_ACT = IOMUX_PAD(0x0330, 0x00A4, 7, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__ANATOP_OTG1_ID = IOMUX_PAD(0x0330, 0x00A4, 8, 0x04B8, 1, 0), + + MX6_PAD_UART3_RX_DATA__UART3_DCE_RX = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0634, 1, 0), + + MX6_PAD_UART3_RX_DATA__UART3_DTE_TX = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__ENET2_RDATA03 = IOMUX_PAD(0x0334, 0x00A8, 1, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__SIM2_PORT0_PD = IOMUX_PAD(0x0334, 0x00A8, 2, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__CSI_DATA00 = IOMUX_PAD(0x0334, 0x00A8, 3, 0x04D0, 0, 0), + MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0628, 3, 0), + MX6_PAD_UART3_RX_DATA__UART2_DTE_CTS = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__GPIO1_IO25 = IOMUX_PAD(0x0334, 0x00A8, 5, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__EPIT1_OUT = IOMUX_PAD(0x0334, 0x00A8, 8, 0x0000, 0, 0), + + MX6_PAD_UART3_CTS_B__UART3_DCE_CTS = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0000, 0, 0), + + MX6_PAD_UART3_CTS_B__UART3_DTE_RTS = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0630, 0, 0), + MX6_PAD_UART3_CTS_B__ENET2_RX_CLK = IOMUX_PAD(0x0338, 0x00AC, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__FLEXCAN1_TX = IOMUX_PAD(0x0338, 0x00AC, 2, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__CSI_DATA10 = IOMUX_PAD(0x0338, 0x00AC, 3, 0x04EC, 0, 0), + MX6_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0338, 0x00AC, 4, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__GPIO1_IO26 = IOMUX_PAD(0x0338, 0x00AC, 5, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__EPIT2_OUT = IOMUX_PAD(0x0338, 0x00AC, 8, 0x0000, 0, 0), + + MX6_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0630, 1, 0), + + MX6_PAD_UART3_RTS_B__UART3_DTE_CTS = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__ENET2_TX_ER = IOMUX_PAD(0x033C, 0x00B0, 1, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__FLEXCAN1_RX = IOMUX_PAD(0x033C, 0x00B0, 2, 0x0584, 0, 0), + MX6_PAD_UART3_RTS_B__CSI_DATA11 = IOMUX_PAD(0x033C, 0x00B0, 3, 0x04F0, 0, 0), + MX6_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x033C, 0x00B0, 4, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__GPIO1_IO27 = IOMUX_PAD(0x033C, 0x00B0, 5, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__WDOG1_WDOG_B = IOMUX_PAD(0x033C, 0x00B0, 8, 0x0000, 0, 0), + + MX6_PAD_UART4_TX_DATA__UART4_DCE_TX = IOMUX_PAD(0x0340, 0x00B4, 0, 0x0000, 0, 0), + + MX6_PAD_UART4_TX_DATA__UART4_DTE_RX = IOMUX_PAD(0x0340, 0x00B4, 0, 0x063C, 0, 0), + MX6_PAD_UART4_TX_DATA__ENET2_TDATA02 = IOMUX_PAD(0x0340, 0x00B4, 1, 0x0000, 0, 0), + MX6_PAD_UART4_TX_DATA__I2C1_SCL = IOMUX_PAD(0x0340, 0x00B4, IOMUX_CONFIG_SION | 2, 0x05A4, 1, 0), + MX6_PAD_UART4_TX_DATA__CSI_DATA12 = IOMUX_PAD(0x0340, 0x00B4, 3, 0x04F4, 0, 0), + MX6_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 = IOMUX_PAD(0x0340, 0x00B4, 4, 0x0000, 0, 0), + MX6_PAD_UART4_TX_DATA__GPIO1_IO28 = IOMUX_PAD(0x0340, 0x00B4, 5, 0x0000, 0, 0), + MX6_PAD_UART4_TX_DATA__ECSPI2_SCLK = IOMUX_PAD(0x0340, 0x00B4, 8, 0x0544, 1, 0), + + MX6_PAD_UART4_RX_DATA__UART4_DCE_RX = IOMUX_PAD(0x0344, 0x00B8, 0, 0x063C, 1, 0), + + MX6_PAD_UART4_RX_DATA__UART4_DTE_TX = IOMUX_PAD(0x0344, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__ENET2_TDATA03 = IOMUX_PAD(0x0344, 0x00B8, 1, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__I2C1_SDA = IOMUX_PAD(0x0344, 0x00B8, IOMUX_CONFIG_SION | 2, 0x05A8, 2, 0), + MX6_PAD_UART4_RX_DATA__CSI_DATA13 = IOMUX_PAD(0x0344, 0x00B8, 3, 0x04F8, 0, 0), + MX6_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 = IOMUX_PAD(0x0344, 0x00B8, 4, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__GPIO1_IO29 = IOMUX_PAD(0x0344, 0x00B8, 5, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__ECSPI2_SS0 = IOMUX_PAD(0x0344, 0x00B8, 8, 0x0550, 1, 0), + MX6_PAD_UART5_TX_DATA__GPIO1_IO30 = IOMUX_PAD(0x0348, 0x00BC, 5, 0x0000, 0, 0), + MX6_PAD_UART5_TX_DATA__ECSPI2_MOSI = IOMUX_PAD(0x0348, 0x00BC, 8, 0x054C, 0, 0), + + MX6_PAD_UART5_TX_DATA__UART5_DCE_TX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0000, 0, 0), + + MX6_PAD_UART5_TX_DATA__UART5_DTE_RX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0644, 6, 0), + MX6_PAD_UART5_TX_DATA__ENET2_CRS = IOMUX_PAD(0x0348, 0x00BC, 1, 0x0000, 0, 0), + MX6_PAD_UART5_TX_DATA__I2C2_SCL = IOMUX_PAD(0x0348, 0x00BC, IOMUX_CONFIG_SION | 2, 0x05AC, 2, 0), + MX6_PAD_UART5_TX_DATA__CSI_DATA14 = IOMUX_PAD(0x0348, 0x00BC, 3, 0x04FC, 0, 0), + MX6_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 = IOMUX_PAD(0x0348, 0x00BC, 4, 0x0000, 0, 0), + + MX6_PAD_UART5_RX_DATA__UART5_DCE_RX = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0644, 7, 0), + + MX6_PAD_UART5_RX_DATA__UART5_DTE_TX = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__ENET2_COL = IOMUX_PAD(0x034C, 0x00C0, 1, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__I2C2_SDA = IOMUX_PAD(0x034C, 0x00C0, IOMUX_CONFIG_SION | 2, 0x05B0, 2, 0), + MX6_PAD_UART5_RX_DATA__CSI_DATA15 = IOMUX_PAD(0x034C, 0x00C0, 3, 0x0500, 0, 0), + MX6_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB = IOMUX_PAD(0x034C, 0x00C0, 4, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__GPIO1_IO31 = IOMUX_PAD(0x034C, 0x00C0, 5, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__ECSPI2_MISO = IOMUX_PAD(0x034C, 0x00C0, 8, 0x0548, 1, 0), + + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 = IOMUX_PAD(0x0350, 0x00C4, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__UART4_DCE_RTS = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0638, 0, 0), + MX6_PAD_ENET1_RX_DATA0__UART4_DTE_CTS = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__PWM1_OUT = IOMUX_PAD(0x0350, 0x00C4, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__CSI_DATA16 = IOMUX_PAD(0x0350, 0x00C4, 3, 0x0504, 0, 0), + MX6_PAD_ENET1_RX_DATA0__FLEXCAN1_TX = IOMUX_PAD(0x0350, 0x00C4, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 = IOMUX_PAD(0x0350, 0x00C4, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__KPP_ROW00 = IOMUX_PAD(0x0350, 0x00C4, 6, 0x05D0, 0, 0), + MX6_PAD_ENET1_RX_DATA0__USDHC1_LCTL = IOMUX_PAD(0x0350, 0x00C4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 = IOMUX_PAD(0x0354, 0x00C8, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__UART4_DCE_CTS = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__UART4_DTE_RTS = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0638, 1, 0), + MX6_PAD_ENET1_RX_DATA1__PWM2_OUT = IOMUX_PAD(0x0354, 0x00C8, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__CSI_DATA17 = IOMUX_PAD(0x0354, 0x00C8, 3, 0x0508, 0, 0), + MX6_PAD_ENET1_RX_DATA1__FLEXCAN1_RX = IOMUX_PAD(0x0354, 0x00C8, 4, 0x0584, 1, 0), + MX6_PAD_ENET1_RX_DATA1__GPIO2_IO01 = IOMUX_PAD(0x0354, 0x00C8, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__KPP_COL00 = IOMUX_PAD(0x0354, 0x00C8, 6, 0x05C4, 0, 0), + MX6_PAD_ENET1_RX_DATA1__USDHC2_LCTL = IOMUX_PAD(0x0354, 0x00C8, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN = IOMUX_PAD(0x0358, 0x00CC, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 5, 0), + MX6_PAD_ENET1_RX_EN__UART5_DTE_CTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__CSI_DATA18 = IOMUX_PAD(0x0358, 0x00CC, 3, 0x050C, 0, 0), + MX6_PAD_ENET1_RX_EN__FLEXCAN2_TX = IOMUX_PAD(0x0358, 0x00CC, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__GPIO2_IO02 = IOMUX_PAD(0x0358, 0x00CC, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__KPP_ROW01 = IOMUX_PAD(0x0358, 0x00CC, 6, 0x05D4, 0, 0), + MX6_PAD_ENET1_RX_EN__USDHC1_VSELECT = IOMUX_PAD(0x0358, 0x00CC, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 = IOMUX_PAD(0x035C, 0x00D0, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA0__UART5_DCE_CTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 6, 0), + MX6_PAD_ENET1_TX_DATA0__CSI_DATA19 = IOMUX_PAD(0x035C, 0x00D0, 3, 0x0510, 0, 0), + MX6_PAD_ENET1_TX_DATA0__FLEXCAN2_RX = IOMUX_PAD(0x035C, 0x00D0, 4, 0x0588, 1, 0), + MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03 = IOMUX_PAD(0x035C, 0x00D0, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA0__KPP_COL01 = IOMUX_PAD(0x035C, 0x00D0, 6, 0x05C8, 0, 0), + MX6_PAD_ENET1_TX_DATA0__USDHC2_VSELECT = IOMUX_PAD(0x035C, 0x00D0, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 = IOMUX_PAD(0x0360, 0x00D4, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__UART6_DCE_CTS = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__UART6_DTE_RTS = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0648, 2, 0), + MX6_PAD_ENET1_TX_DATA1__PWM5_OUT = IOMUX_PAD(0x0360, 0x00D4, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__CSI_DATA20 = IOMUX_PAD(0x0360, 0x00D4, 3, 0x0514, 0, 0), + MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO = IOMUX_PAD(0x0360, 0x00D4, 4, 0x0580, 1, 0), + MX6_PAD_ENET1_TX_DATA1__GPIO2_IO04 = IOMUX_PAD(0x0360, 0x00D4, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__KPP_ROW02 = IOMUX_PAD(0x0360, 0x00D4, 6, 0x05D8, 0, 0), + MX6_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0360, 0x00D4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN = IOMUX_PAD(0x0364, 0x00D8, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__UART6_DCE_RTS = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0648, 3, 0), + MX6_PAD_ENET1_TX_EN__UART6_DTE_CTS = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__PWM6_OUT = IOMUX_PAD(0x0364, 0x00D8, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__CSI_DATA21 = IOMUX_PAD(0x0364, 0x00D8, 3, 0x0518, 0, 0), + MX6_PAD_ENET1_TX_EN__ENET2_MDC = IOMUX_PAD(0x0364, 0x00D8, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__GPIO2_IO05 = IOMUX_PAD(0x0364, 0x00D8, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__KPP_COL02 = IOMUX_PAD(0x0364, 0x00D8, 6, 0x05CC, 0, 0), + MX6_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x0364, 0x00D8, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK = IOMUX_PAD(0x0368, 0x00DC, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__UART7_DCE_CTS = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__UART7_DTE_RTS = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0650, 0, 0), + MX6_PAD_ENET1_TX_CLK__PWM7_OUT = IOMUX_PAD(0x0368, 0x00DC, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__CSI_DATA22 = IOMUX_PAD(0x0368, 0x00DC, 3, 0x051C, 0, 0), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 = IOMUX_PAD(0x0368, 0x00DC, IOMUX_CONFIG_SION | 4, 0x0574, 2, 0), + MX6_PAD_ENET1_TX_CLK__GPIO2_IO06 = IOMUX_PAD(0x0368, 0x00DC, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__KPP_ROW03 = IOMUX_PAD(0x0368, 0x00DC, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__GPT1_CLK = IOMUX_PAD(0x0368, 0x00DC, 8, 0x0594, 1, 0), + + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER = IOMUX_PAD(0x036C, 0x00E0, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__UART7_DCE_RTS = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0650, 1, 0), + MX6_PAD_ENET1_RX_ER__UART7_DTE_CTS = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__PWM8_OUT = IOMUX_PAD(0x036C, 0x00E0, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__CSI_DATA23 = IOMUX_PAD(0x036C, 0x00E0, 3, 0x0520, 0, 0), + MX6_PAD_ENET1_RX_ER__EIM_CRE = IOMUX_PAD(0x036C, 0x00E0, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__GPIO2_IO07 = IOMUX_PAD(0x036C, 0x00E0, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__KPP_COL03 = IOMUX_PAD(0x036C, 0x00E0, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__GPT1_CAPTURE2 = IOMUX_PAD(0x036C, 0x00E0, 8, 0x0590, 1, 0), + + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 = IOMUX_PAD(0x0370, 0x00E4, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__UART6_DCE_TX = IOMUX_PAD(0x0370, 0x00E4, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__UART6_DTE_RX = IOMUX_PAD(0x0370, 0x00E4, 1, 0x064C, 1, 0), + MX6_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD = IOMUX_PAD(0x0370, 0x00E4, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__I2C3_SCL = IOMUX_PAD(0x0370, 0x00E4, IOMUX_CONFIG_SION | 3, 0x05B4, 1, 0), + MX6_PAD_ENET2_RX_DATA0__ENET1_MDIO = IOMUX_PAD(0x0370, 0x00E4, 4, 0x0578, 1, 0), + MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08 = IOMUX_PAD(0x0370, 0x00E4, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__KPP_ROW04 = IOMUX_PAD(0x0370, 0x00E4, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__USB_OTG1_PWR = IOMUX_PAD(0x0370, 0x00E4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 = IOMUX_PAD(0x0374, 0x00E8, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__UART6_DCE_RX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x064C, 2, 0), + MX6_PAD_ENET2_RX_DATA1__UART6_DTE_TX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK = IOMUX_PAD(0x0374, 0x00E8, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__I2C3_SDA = IOMUX_PAD(0x0374, 0x00E8, IOMUX_CONFIG_SION | 3, 0x05B8, 1, 0), + MX6_PAD_ENET2_RX_DATA1__ENET1_MDC = IOMUX_PAD(0x0374, 0x00E8, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09 = IOMUX_PAD(0x0374, 0x00E8, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__KPP_COL04 = IOMUX_PAD(0x0374, 0x00E8, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__USB_OTG1_OC = IOMUX_PAD(0x0374, 0x00E8, 8, 0x0664, 1, 0), + + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN = IOMUX_PAD(0x0378, 0x00EC, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__UART7_DCE_TX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__UART7_DTE_RX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0654, 0, 0), + MX6_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B = IOMUX_PAD(0x0378, 0x00EC, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__I2C4_SCL = IOMUX_PAD(0x0378, 0x00EC, IOMUX_CONFIG_SION | 3, 0x05BC, 1, 0), + MX6_PAD_ENET2_RX_EN__EIM_ADDR26 = IOMUX_PAD(0x0378, 0x00EC, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__GPIO2_IO10 = IOMUX_PAD(0x0378, 0x00EC, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__KPP_ROW05 = IOMUX_PAD(0x0378, 0x00EC, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M = IOMUX_PAD(0x0378, 0x00EC, 8, 0x0000, 0, 0), + + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 = IOMUX_PAD(0x037C, 0x00F0, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0654, 1, 0), + MX6_PAD_ENET2_TX_DATA0__UART7_DTE_TX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN = IOMUX_PAD(0x037C, 0x00F0, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__I2C4_SDA = IOMUX_PAD(0x037C, 0x00F0, IOMUX_CONFIG_SION | 3, 0x05C0, 1, 0), + MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02 = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11 = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__KPP_COL05 = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0), + + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__UART8_DTE_RX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x065C, 0, 0), + MX6_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD = IOMUX_PAD(0x0380, 0x00F4, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__ECSPI4_SCLK = IOMUX_PAD(0x0380, 0x00F4, 3, 0x0564, 0, 0), + MX6_PAD_ENET2_TX_DATA1__EIM_EB_B03 = IOMUX_PAD(0x0380, 0x00F4, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12 = IOMUX_PAD(0x0380, 0x00F4, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__KPP_ROW06 = IOMUX_PAD(0x0380, 0x00F4, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0380, 0x00F4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN = IOMUX_PAD(0x0384, 0x00F8, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__UART8_DCE_RX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x065C, 1, 0), + MX6_PAD_ENET2_TX_EN__UART8_DTE_TX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__SIM2_PORT0_CLK = IOMUX_PAD(0x0384, 0x00F8, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__ECSPI4_MOSI = IOMUX_PAD(0x0384, 0x00F8, 3, 0x056C, 0, 0), + MX6_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN = IOMUX_PAD(0x0384, 0x00F8, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__GPIO2_IO13 = IOMUX_PAD(0x0384, 0x00F8, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__KPP_COL06 = IOMUX_PAD(0x0384, 0x00F8, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__USB_OTG2_OC = IOMUX_PAD(0x0384, 0x00F8, 8, 0x0660, 1, 0), + + MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__UART8_DTE_RTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0658, 0, 0), + MX6_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B = IOMUX_PAD(0x0388, 0x00FC, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__ECSPI4_MISO = IOMUX_PAD(0x0388, 0x00FC, 3, 0x0568, 0, 0), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 4, 0x057C, 2, 0), + MX6_PAD_ENET2_TX_CLK__GPIO2_IO14 = IOMUX_PAD(0x0388, 0x00FC, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__KPP_ROW07 = IOMUX_PAD(0x0388, 0x00FC, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID = IOMUX_PAD(0x0388, 0x00FC, 8, 0x04BC, 1, 0), + + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER = IOMUX_PAD(0x038C, 0x0100, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0658, 1, 0), + MX6_PAD_ENET2_RX_ER__UART8_DTE_CTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN = IOMUX_PAD(0x038C, 0x0100, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__ECSPI4_SS0 = IOMUX_PAD(0x038C, 0x0100, 3, 0x0570, 0, 0), + MX6_PAD_ENET2_RX_ER__EIM_ADDR25 = IOMUX_PAD(0x038C, 0x0100, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__GPIO2_IO15 = IOMUX_PAD(0x038C, 0x0100, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__KPP_COL07 = IOMUX_PAD(0x038C, 0x0100, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY = IOMUX_PAD(0x038C, 0x0100, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_CLK__LCDIF_CLK = IOMUX_PAD(0x0390, 0x0104, 0, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__LCDIF_WR_RWN = IOMUX_PAD(0x0390, 0x0104, 1, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__UART4_DCE_TX = IOMUX_PAD(0x0390, 0x0104, 2, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__UART4_DTE_RX = IOMUX_PAD(0x0390, 0x0104, 2, 0x063C, 2, 0), + MX6_PAD_LCD_CLK__SAI3_MCLK = IOMUX_PAD(0x0390, 0x0104, 3, 0x0600, 0, 0), + MX6_PAD_LCD_CLK__EIM_CS2_B = IOMUX_PAD(0x0390, 0x0104, 4, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__GPIO3_IO00 = IOMUX_PAD(0x0390, 0x0104, 5, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0390, 0x0104, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE = IOMUX_PAD(0x0394, 0x0108, 0, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__LCDIF_RD_E = IOMUX_PAD(0x0394, 0x0108, 1, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__UART4_DCE_RX = IOMUX_PAD(0x0394, 0x0108, 2, 0x063C, 3, 0), + MX6_PAD_LCD_ENABLE__UART4_DTE_TX = IOMUX_PAD(0x0394, 0x0108, 2, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__SAI3_TX_SYNC = IOMUX_PAD(0x0394, 0x0108, 3, 0x060C, 0, 0), + MX6_PAD_LCD_ENABLE__EIM_CS3_B = IOMUX_PAD(0x0394, 0x0108, 4, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__GPIO3_IO01 = IOMUX_PAD(0x0394, 0x0108, 5, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__ECSPI2_RDY = IOMUX_PAD(0x0394, 0x0108, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC = IOMUX_PAD(0x0398, 0x010C, 0, 0x05DC, 0, 0), + MX6_PAD_LCD_HSYNC__LCDIF_RS = IOMUX_PAD(0x0398, 0x010C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__UART4_DCE_CTS = IOMUX_PAD(0x0398, 0x010C, 2, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__UART4_DTE_RTS = IOMUX_PAD(0x0398, 0x010C, 2, 0x0638, 2, 0), + MX6_PAD_LCD_HSYNC__SAI3_TX_BCLK = IOMUX_PAD(0x0398, 0x010C, 3, 0x0608, 0, 0), + MX6_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x0398, 0x010C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__GPIO3_IO02 = IOMUX_PAD(0x0398, 0x010C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__ECSPI2_SS1 = IOMUX_PAD(0x0398, 0x010C, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC = IOMUX_PAD(0x039C, 0x0110, 0, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__LCDIF_BUSY = IOMUX_PAD(0x039C, 0x0110, 1, 0x05DC, 1, 0), + MX6_PAD_LCD_VSYNC__UART4_DCE_RTS = IOMUX_PAD(0x039C, 0x0110, 2, 0x0638, 3, 0), + MX6_PAD_LCD_VSYNC__UART4_DTE_CTS = IOMUX_PAD(0x039C, 0x0110, 2, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__SAI3_RX_DATA = IOMUX_PAD(0x039C, 0x0110, 3, 0x0604, 0, 0), + MX6_PAD_LCD_VSYNC__WDOG2_WDOG_B = IOMUX_PAD(0x039C, 0x0110, 4, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__GPIO3_IO03 = IOMUX_PAD(0x039C, 0x0110, 5, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__ECSPI2_SS2 = IOMUX_PAD(0x039C, 0x0110, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_RESET__LCDIF_RESET = IOMUX_PAD(0x03A0, 0x0114, 0, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__LCDIF_CS = IOMUX_PAD(0x03A0, 0x0114, 1, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__CA7_MX6ULL_EVENTI = IOMUX_PAD(0x03A0, 0x0114, 2, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__SAI3_TX_DATA = IOMUX_PAD(0x03A0, 0x0114, 3, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__WDOG1_WDOG_ANY = IOMUX_PAD(0x03A0, 0x0114, 4, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__GPIO3_IO04 = IOMUX_PAD(0x03A0, 0x0114, 5, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__ECSPI2_SS3 = IOMUX_PAD(0x03A0, 0x0114, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA00__LCDIF_DATA00 = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__PWM1_OUT = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x03A4, 0x0118, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__I2C3_SDA = IOMUX_PAD(0x03A4, 0x0118, IOMUX_CONFIG_SION | 4, 0x05B8, 2, 0), + MX6_PAD_LCD_DATA00__GPIO3_IO05 = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__SRC_BT_CFG00 = IOMUX_PAD(0x03A4, 0x0118, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__SAI1_MCLK = IOMUX_PAD(0x03A4, 0x0118, 8, 0x05E0, 1, 0), + + MX6_PAD_LCD_DATA01__LCDIF_DATA01 = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__PWM2_OUT = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x03A8, 0x011C, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__I2C3_SCL = IOMUX_PAD(0x03A8, 0x011C, IOMUX_CONFIG_SION | 4, 0x05B4, 2, 0), + MX6_PAD_LCD_DATA01__GPIO3_IO06 = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__SRC_BT_CFG01 = IOMUX_PAD(0x03A8, 0x011C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__SAI1_TX_SYNC = IOMUX_PAD(0x03A8, 0x011C, 8, 0x05EC, 0, 0), + + MX6_PAD_LCD_DATA02__LCDIF_DATA02 = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__PWM3_OUT = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x03AC, 0x0120, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__I2C4_SDA = IOMUX_PAD(0x03AC, 0x0120, IOMUX_CONFIG_SION | 4, 0x05C0, 2, 0), + MX6_PAD_LCD_DATA02__GPIO3_IO07 = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__SRC_BT_CFG02 = IOMUX_PAD(0x03AC, 0x0120, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__SAI1_TX_BCLK = IOMUX_PAD(0x03AC, 0x0120, 8, 0x05E8, 0, 0), + + MX6_PAD_LCD_DATA03__LCDIF_DATA03 = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__PWM4_OUT = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x03B0, 0x0124, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__I2C4_SCL = IOMUX_PAD(0x03B0, 0x0124, IOMUX_CONFIG_SION | 4, 0x05BC, 2, 0), + MX6_PAD_LCD_DATA03__GPIO3_IO08 = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__SRC_BT_CFG03 = IOMUX_PAD(0x03B0, 0x0124, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__SAI1_RX_DATA = IOMUX_PAD(0x03B0, 0x0124, 8, 0x05E4, 0, 0), + + MX6_PAD_LCD_DATA04__LCDIF_DATA04 = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__UART8_DCE_CTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__UART8_DTE_RTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0658, 2, 0), + MX6_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x03B4, 0x0128, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__SPDIF_SR_CLK = IOMUX_PAD(0x03B4, 0x0128, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__GPIO3_IO09 = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__SRC_BT_CFG04 = IOMUX_PAD(0x03B4, 0x0128, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__SAI1_TX_DATA = IOMUX_PAD(0x03B4, 0x0128, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA05__LCDIF_DATA05 = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__UART8_DCE_RTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0), + MX6_PAD_LCD_DATA05__UART8_DTE_CTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x03B8, 0x012C, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__SPDIF_OUT = IOMUX_PAD(0x03B8, 0x012C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__SRC_BT_CFG05 = IOMUX_PAD(0x03B8, 0x012C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__ECSPI1_SS1 = IOMUX_PAD(0x03B8, 0x012C, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA06__LCDIF_DATA06 = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__UART7_DCE_CTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__UART7_DTE_RTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0650, 2, 0), + MX6_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x03BC, 0x0130, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__SPDIF_LOCK = IOMUX_PAD(0x03BC, 0x0130, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__SRC_BT_CFG06 = IOMUX_PAD(0x03BC, 0x0130, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__ECSPI1_SS2 = IOMUX_PAD(0x03BC, 0x0130, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA07__LCDIF_DATA07 = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__UART7_DCE_RTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0), + MX6_PAD_LCD_DATA07__UART7_DTE_CTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x03C0, 0x0134, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__SPDIF_EXT_CLK = IOMUX_PAD(0x03C0, 0x0134, 4, 0x061C, 0, 0), + MX6_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__SRC_BT_CFG07 = IOMUX_PAD(0x03C0, 0x0134, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__ECSPI1_SS3 = IOMUX_PAD(0x03C0, 0x0134, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA08__LCDIF_DATA08 = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__SPDIF_IN = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0), + MX6_PAD_LCD_DATA08__CSI_DATA16 = IOMUX_PAD(0x03C4, 0x0138, 3, 0x0504, 1, 0), + MX6_PAD_LCD_DATA08__EIM_DATA00 = IOMUX_PAD(0x03C4, 0x0138, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__GPIO3_IO13 = IOMUX_PAD(0x03C4, 0x0138, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__SRC_BT_CFG08 = IOMUX_PAD(0x03C4, 0x0138, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__FLEXCAN1_TX = IOMUX_PAD(0x03C4, 0x0138, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA09__LCDIF_DATA09 = IOMUX_PAD(0x03C8, 0x013C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__SAI3_MCLK = IOMUX_PAD(0x03C8, 0x013C, 1, 0x0600, 1, 0), + MX6_PAD_LCD_DATA09__CSI_DATA17 = IOMUX_PAD(0x03C8, 0x013C, 3, 0x0508, 1, 0), + MX6_PAD_LCD_DATA09__EIM_DATA01 = IOMUX_PAD(0x03C8, 0x013C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__GPIO3_IO14 = IOMUX_PAD(0x03C8, 0x013C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__SRC_BT_CFG09 = IOMUX_PAD(0x03C8, 0x013C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__FLEXCAN1_RX = IOMUX_PAD(0x03C8, 0x013C, 8, 0x0584, 2, 0), + + MX6_PAD_LCD_DATA10__LCDIF_DATA10 = IOMUX_PAD(0x03CC, 0x0140, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__SAI3_RX_SYNC = IOMUX_PAD(0x03CC, 0x0140, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__CSI_DATA18 = IOMUX_PAD(0x03CC, 0x0140, 3, 0x050C, 1, 0), + MX6_PAD_LCD_DATA10__EIM_DATA02 = IOMUX_PAD(0x03CC, 0x0140, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__GPIO3_IO15 = IOMUX_PAD(0x03CC, 0x0140, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__SRC_BT_CFG10 = IOMUX_PAD(0x03CC, 0x0140, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__FLEXCAN2_TX = IOMUX_PAD(0x03CC, 0x0140, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA11__LCDIF_DATA11 = IOMUX_PAD(0x03D0, 0x0144, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__SAI3_RX_BCLK = IOMUX_PAD(0x03D0, 0x0144, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__CSI_DATA19 = IOMUX_PAD(0x03D0, 0x0144, 3, 0x0510, 1, 0), + MX6_PAD_LCD_DATA11__EIM_DATA03 = IOMUX_PAD(0x03D0, 0x0144, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__GPIO3_IO16 = IOMUX_PAD(0x03D0, 0x0144, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__SRC_BT_CFG11 = IOMUX_PAD(0x03D0, 0x0144, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__FLEXCAN2_RX = IOMUX_PAD(0x03D0, 0x0144, 8, 0x0588, 2, 0), + + MX6_PAD_LCD_DATA12__LCDIF_DATA12 = IOMUX_PAD(0x03D4, 0x0148, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__SAI3_TX_SYNC = IOMUX_PAD(0x03D4, 0x0148, 1, 0x060C, 1, 0), + MX6_PAD_LCD_DATA12__CSI_DATA20 = IOMUX_PAD(0x03D4, 0x0148, 3, 0x0514, 1, 0), + MX6_PAD_LCD_DATA12__EIM_DATA04 = IOMUX_PAD(0x03D4, 0x0148, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__GPIO3_IO17 = IOMUX_PAD(0x03D4, 0x0148, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__SRC_BT_CFG12 = IOMUX_PAD(0x03D4, 0x0148, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__ECSPI1_RDY = IOMUX_PAD(0x03D4, 0x0148, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA13__LCDIF_DATA13 = IOMUX_PAD(0x03D8, 0x014C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__SAI3_TX_BCLK = IOMUX_PAD(0x03D8, 0x014C, 1, 0x0608, 1, 0), + MX6_PAD_LCD_DATA13__CSI_DATA21 = IOMUX_PAD(0x03D8, 0x014C, 3, 0x0518, 1, 0), + MX6_PAD_LCD_DATA13__EIM_DATA05 = IOMUX_PAD(0x03D8, 0x014C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__GPIO3_IO18 = IOMUX_PAD(0x03D8, 0x014C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__SRC_BT_CFG13 = IOMUX_PAD(0x03D8, 0x014C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__USDHC2_RESET_B = IOMUX_PAD(0x03D8, 0x014C, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA14__LCDIF_DATA14 = IOMUX_PAD(0x03DC, 0x0150, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__SAI3_RX_DATA = IOMUX_PAD(0x03DC, 0x0150, 1, 0x0604, 1, 0), + MX6_PAD_LCD_DATA14__CSI_DATA22 = IOMUX_PAD(0x03DC, 0x0150, 3, 0x051C, 1, 0), + MX6_PAD_LCD_DATA14__EIM_DATA06 = IOMUX_PAD(0x03DC, 0x0150, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__SRC_BT_CFG14 = IOMUX_PAD(0x03DC, 0x0150, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__USDHC2_DATA4 = IOMUX_PAD(0x03DC, 0x0150, 8, 0x068C, 0, 0), + + MX6_PAD_LCD_DATA15__LCDIF_DATA15 = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__SAI3_TX_DATA = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__CSI_DATA23 = IOMUX_PAD(0x03E0, 0x0154, 3, 0x0520, 1, 0), + MX6_PAD_LCD_DATA15__EIM_DATA07 = IOMUX_PAD(0x03E0, 0x0154, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__SRC_BT_CFG15 = IOMUX_PAD(0x03E0, 0x0154, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__USDHC2_DATA5 = IOMUX_PAD(0x03E0, 0x0154, 8, 0x0690, 0, 0), + + MX6_PAD_LCD_DATA16__LCDIF_DATA16 = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__UART7_DCE_TX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__UART7_DTE_RX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0654, 2, 0), + MX6_PAD_LCD_DATA16__CSI_DATA01 = IOMUX_PAD(0x03E4, 0x0158, 3, 0x04D4, 1, 0), + MX6_PAD_LCD_DATA16__EIM_DATA08 = IOMUX_PAD(0x03E4, 0x0158, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__SRC_BT_CFG24 = IOMUX_PAD(0x03E4, 0x0158, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__USDHC2_DATA6 = IOMUX_PAD(0x03E4, 0x0158, 8, 0x0694, 0, 0), + + MX6_PAD_LCD_DATA17__LCDIF_DATA17 = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0), + MX6_PAD_LCD_DATA17__UART7_DTE_TX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__CSI_DATA00 = IOMUX_PAD(0x03E8, 0x015C, 3, 0x04D0, 1, 0), + MX6_PAD_LCD_DATA17__EIM_DATA09 = IOMUX_PAD(0x03E8, 0x015C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__SRC_BT_CFG25 = IOMUX_PAD(0x03E8, 0x015C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__USDHC2_DATA7 = IOMUX_PAD(0x03E8, 0x015C, 8, 0x0698, 0, 0), + + MX6_PAD_LCD_DATA18__LCDIF_DATA18 = IOMUX_PAD(0x03EC, 0x0160, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__PWM5_OUT = IOMUX_PAD(0x03EC, 0x0160, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__CA7_MX6ULL_EVENTO = IOMUX_PAD(0x03EC, 0x0160, 2, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__CSI_DATA10 = IOMUX_PAD(0x03EC, 0x0160, 3, 0x04EC, 1, 0), + MX6_PAD_LCD_DATA18__EIM_DATA10 = IOMUX_PAD(0x03EC, 0x0160, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__GPIO3_IO23 = IOMUX_PAD(0x03EC, 0x0160, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__SRC_BT_CFG26 = IOMUX_PAD(0x03EC, 0x0160, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__USDHC2_CMD = IOMUX_PAD(0x03EC, 0x0160, 8, 0x0678, 1, 0), + MX6_PAD_LCD_DATA19__EIM_DATA11 = IOMUX_PAD(0x03F0, 0x0164, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__GPIO3_IO24 = IOMUX_PAD(0x03F0, 0x0164, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__SRC_BT_CFG27 = IOMUX_PAD(0x03F0, 0x0164, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__USDHC2_CLK = IOMUX_PAD(0x03F0, 0x0164, 8, 0x0670, 1, 0), + + MX6_PAD_LCD_DATA19__LCDIF_DATA19 = IOMUX_PAD(0x03F0, 0x0164, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__PWM6_OUT = IOMUX_PAD(0x03F0, 0x0164, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__WDOG1_WDOG_ANY = IOMUX_PAD(0x03F0, 0x0164, 2, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__CSI_DATA11 = IOMUX_PAD(0x03F0, 0x0164, 3, 0x04F0, 1, 0), + MX6_PAD_LCD_DATA20__EIM_DATA12 = IOMUX_PAD(0x03F4, 0x0168, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__GPIO3_IO25 = IOMUX_PAD(0x03F4, 0x0168, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__SRC_BT_CFG28 = IOMUX_PAD(0x03F4, 0x0168, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__USDHC2_DATA0 = IOMUX_PAD(0x03F4, 0x0168, 8, 0x067C, 1, 0), + + MX6_PAD_LCD_DATA20__LCDIF_DATA20 = IOMUX_PAD(0x03F4, 0x0168, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__UART8_DCE_TX = IOMUX_PAD(0x03F4, 0x0168, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__UART8_DTE_RX = IOMUX_PAD(0x03F4, 0x0168, 1, 0x065C, 2, 0), + MX6_PAD_LCD_DATA20__ECSPI1_SCLK = IOMUX_PAD(0x03F4, 0x0168, 2, 0x0534, 0, 0), + MX6_PAD_LCD_DATA20__CSI_DATA12 = IOMUX_PAD(0x03F4, 0x0168, 3, 0x04F4, 1, 0), + + MX6_PAD_LCD_DATA21__LCDIF_DATA21 = IOMUX_PAD(0x03F8, 0x016C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__UART8_DCE_RX = IOMUX_PAD(0x03F8, 0x016C, 1, 0x065C, 3, 0), + MX6_PAD_LCD_DATA21__UART8_DTE_TX = IOMUX_PAD(0x03F8, 0x016C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__ECSPI1_SS0 = IOMUX_PAD(0x03F8, 0x016C, 2, 0x0540, 0, 0), + MX6_PAD_LCD_DATA21__CSI_DATA13 = IOMUX_PAD(0x03F8, 0x016C, 3, 0x04F8, 1, 0), + MX6_PAD_LCD_DATA21__EIM_DATA13 = IOMUX_PAD(0x03F8, 0x016C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__GPIO3_IO26 = IOMUX_PAD(0x03F8, 0x016C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__SRC_BT_CFG29 = IOMUX_PAD(0x03F8, 0x016C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__USDHC2_DATA1 = IOMUX_PAD(0x03F8, 0x016C, 8, 0x0680, 1, 0), + + MX6_PAD_LCD_DATA22__LCDIF_DATA22 = IOMUX_PAD(0x03FC, 0x0170, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__MQS_RIGHT = IOMUX_PAD(0x03FC, 0x0170, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__ECSPI1_MOSI = IOMUX_PAD(0x03FC, 0x0170, 2, 0x053C, 0, 0), + MX6_PAD_LCD_DATA22__CSI_DATA14 = IOMUX_PAD(0x03FC, 0x0170, 3, 0x04FC, 1, 0), + MX6_PAD_LCD_DATA22__EIM_DATA14 = IOMUX_PAD(0x03FC, 0x0170, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__GPIO3_IO27 = IOMUX_PAD(0x03FC, 0x0170, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__SRC_BT_CFG30 = IOMUX_PAD(0x03FC, 0x0170, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__USDHC2_DATA2 = IOMUX_PAD(0x03FC, 0x0170, 8, 0x0684, 0, 0), + + MX6_PAD_LCD_DATA23__LCDIF_DATA23 = IOMUX_PAD(0x0400, 0x0174, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__MQS_LEFT = IOMUX_PAD(0x0400, 0x0174, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__ECSPI1_MISO = IOMUX_PAD(0x0400, 0x0174, 2, 0x0538, 0, 0), + MX6_PAD_LCD_DATA23__CSI_DATA15 = IOMUX_PAD(0x0400, 0x0174, 3, 0x0500, 1, 0), + MX6_PAD_LCD_DATA23__EIM_DATA15 = IOMUX_PAD(0x0400, 0x0174, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__GPIO3_IO28 = IOMUX_PAD(0x0400, 0x0174, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__SRC_BT_CFG31 = IOMUX_PAD(0x0400, 0x0174, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__USDHC2_DATA3 = IOMUX_PAD(0x0400, 0x0174, 8, 0x0688, 1, 0), + + MX6_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0404, 0x0178, 0, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__USDHC2_CLK = IOMUX_PAD(0x0404, 0x0178, 1, 0x0670, 2, 0), + MX6_PAD_NAND_RE_B__QSPI_B_SCLK = IOMUX_PAD(0x0404, 0x0178, 2, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__KPP_ROW00 = IOMUX_PAD(0x0404, 0x0178, 3, 0x05D0, 1, 0), + MX6_PAD_NAND_RE_B__EIM_EB_B00 = IOMUX_PAD(0x0404, 0x0178, 4, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__GPIO4_IO00 = IOMUX_PAD(0x0404, 0x0178, 5, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__ECSPI3_SS2 = IOMUX_PAD(0x0404, 0x0178, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x0408, 0x017C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__USDHC2_CMD = IOMUX_PAD(0x0408, 0x017C, 1, 0x0678, 2, 0), + MX6_PAD_NAND_WE_B__QSPI_B_SS0_B = IOMUX_PAD(0x0408, 0x017C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__KPP_COL00 = IOMUX_PAD(0x0408, 0x017C, 3, 0x05C4, 1, 0), + MX6_PAD_NAND_WE_B__EIM_EB_B01 = IOMUX_PAD(0x0408, 0x017C, 4, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__GPIO4_IO01 = IOMUX_PAD(0x0408, 0x017C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__ECSPI3_SS3 = IOMUX_PAD(0x0408, 0x017C, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x040C, 0x0180, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 = IOMUX_PAD(0x040C, 0x0180, 1, 0x067C, 2, 0), + MX6_PAD_NAND_DATA00__QSPI_B_SS1_B = IOMUX_PAD(0x040C, 0x0180, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__KPP_ROW01 = IOMUX_PAD(0x040C, 0x0180, 3, 0x05D4, 1, 0), + MX6_PAD_NAND_DATA00__EIM_AD08 = IOMUX_PAD(0x040C, 0x0180, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__GPIO4_IO02 = IOMUX_PAD(0x040C, 0x0180, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__ECSPI4_RDY = IOMUX_PAD(0x040C, 0x0180, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0410, 0x0184, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 = IOMUX_PAD(0x0410, 0x0184, 1, 0x0680, 2, 0), + MX6_PAD_NAND_DATA01__QSPI_B_DQS = IOMUX_PAD(0x0410, 0x0184, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__KPP_COL01 = IOMUX_PAD(0x0410, 0x0184, 3, 0x05C8, 1, 0), + MX6_PAD_NAND_DATA01__EIM_AD09 = IOMUX_PAD(0x0410, 0x0184, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__GPIO4_IO03 = IOMUX_PAD(0x0410, 0x0184, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__ECSPI4_SS1 = IOMUX_PAD(0x0410, 0x0184, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x0414, 0x0188, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 = IOMUX_PAD(0x0414, 0x0188, 1, 0x0684, 1, 0), + MX6_PAD_NAND_DATA02__QSPI_B_DATA00 = IOMUX_PAD(0x0414, 0x0188, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__KPP_ROW02 = IOMUX_PAD(0x0414, 0x0188, 3, 0x05D8, 1, 0), + MX6_PAD_NAND_DATA02__EIM_AD10 = IOMUX_PAD(0x0414, 0x0188, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__GPIO4_IO04 = IOMUX_PAD(0x0414, 0x0188, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__ECSPI4_SS2 = IOMUX_PAD(0x0414, 0x0188, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0418, 0x018C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 = IOMUX_PAD(0x0418, 0x018C, 1, 0x0688, 2, 0), + MX6_PAD_NAND_DATA03__QSPI_B_DATA01 = IOMUX_PAD(0x0418, 0x018C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__KPP_COL02 = IOMUX_PAD(0x0418, 0x018C, 3, 0x05CC, 1, 0), + MX6_PAD_NAND_DATA03__EIM_AD11 = IOMUX_PAD(0x0418, 0x018C, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__GPIO4_IO05 = IOMUX_PAD(0x0418, 0x018C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__ECSPI4_SS3 = IOMUX_PAD(0x0418, 0x018C, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x041C, 0x0190, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x041C, 0x0190, 1, 0x068C, 1, 0), + MX6_PAD_NAND_DATA04__QSPI_B_DATA02 = IOMUX_PAD(0x041C, 0x0190, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__ECSPI4_SCLK = IOMUX_PAD(0x041C, 0x0190, 3, 0x0564, 1, 0), + MX6_PAD_NAND_DATA04__EIM_AD12 = IOMUX_PAD(0x041C, 0x0190, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__GPIO4_IO06 = IOMUX_PAD(0x041C, 0x0190, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__UART2_DCE_TX = IOMUX_PAD(0x041C, 0x0190, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__UART2_DTE_RX = IOMUX_PAD(0x041C, 0x0190, 8, 0x062C, 2, 0), + + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0420, 0x0194, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x0420, 0x0194, 1, 0x0690, 1, 0), + MX6_PAD_NAND_DATA05__QSPI_B_DATA03 = IOMUX_PAD(0x0420, 0x0194, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__ECSPI4_MOSI = IOMUX_PAD(0x0420, 0x0194, 3, 0x056C, 1, 0), + MX6_PAD_NAND_DATA05__EIM_AD13 = IOMUX_PAD(0x0420, 0x0194, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__GPIO4_IO07 = IOMUX_PAD(0x0420, 0x0194, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__UART2_DCE_RX = IOMUX_PAD(0x0420, 0x0194, 8, 0x062C, 3, 0), + MX6_PAD_NAND_DATA05__UART2_DTE_TX = IOMUX_PAD(0x0420, 0x0194, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x0424, 0x0198, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x0424, 0x0198, 1, 0x0694, 1, 0), + MX6_PAD_NAND_DATA06__SAI2_RX_BCLK = IOMUX_PAD(0x0424, 0x0198, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__ECSPI4_MISO = IOMUX_PAD(0x0424, 0x0198, 3, 0x0568, 1, 0), + MX6_PAD_NAND_DATA06__EIM_AD14 = IOMUX_PAD(0x0424, 0x0198, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__GPIO4_IO08 = IOMUX_PAD(0x0424, 0x0198, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__UART2_DCE_CTS = IOMUX_PAD(0x0424, 0x0198, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__UART2_DTE_RTS = IOMUX_PAD(0x0424, 0x0198, 8, 0x0628, 4, 0), + + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0428, 0x019C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x0428, 0x019C, 1, 0x0698, 1, 0), + MX6_PAD_NAND_DATA07__QSPI_A_SS1_B = IOMUX_PAD(0x0428, 0x019C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__ECSPI4_SS0 = IOMUX_PAD(0x0428, 0x019C, 3, 0x0570, 1, 0), + MX6_PAD_NAND_DATA07__EIM_AD15 = IOMUX_PAD(0x0428, 0x019C, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__GPIO4_IO09 = IOMUX_PAD(0x0428, 0x019C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__UART2_DCE_RTS = IOMUX_PAD(0x0428, 0x019C, 8, 0x0628, 5, 0), + MX6_PAD_NAND_DATA07__UART2_DTE_CTS = IOMUX_PAD(0x0428, 0x019C, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x042C, 0x01A0, 0, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__USDHC2_RESET_B = IOMUX_PAD(0x042C, 0x01A0, 1, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__QSPI_A_DQS = IOMUX_PAD(0x042C, 0x01A0, 2, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__PWM3_OUT = IOMUX_PAD(0x042C, 0x01A0, 3, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__EIM_ADDR17 = IOMUX_PAD(0x042C, 0x01A0, 4, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__GPIO4_IO10 = IOMUX_PAD(0x042C, 0x01A0, 5, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__ECSPI3_SS1 = IOMUX_PAD(0x042C, 0x01A0, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x0430, 0x01A4, 0, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__USDHC1_RESET_B = IOMUX_PAD(0x0430, 0x01A4, 1, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__QSPI_A_SCLK = IOMUX_PAD(0x0430, 0x01A4, 2, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__PWM4_OUT = IOMUX_PAD(0x0430, 0x01A4, 3, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__EIM_BCLK = IOMUX_PAD(0x0430, 0x01A4, 4, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__GPIO4_IO11 = IOMUX_PAD(0x0430, 0x01A4, 5, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__ECSPI3_RDY = IOMUX_PAD(0x0430, 0x01A4, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x0434, 0x01A8, 0, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__USDHC1_DATA4 = IOMUX_PAD(0x0434, 0x01A8, 1, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 = IOMUX_PAD(0x0434, 0x01A8, 2, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__ECSPI3_SS0 = IOMUX_PAD(0x0434, 0x01A8, 3, 0x0560, 1, 0), + MX6_PAD_NAND_READY_B__EIM_CS1_B = IOMUX_PAD(0x0434, 0x01A8, 4, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__GPIO4_IO12 = IOMUX_PAD(0x0434, 0x01A8, 5, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__UART3_DCE_TX = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__UART3_DTE_RX = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0634, 2, 0), + + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0438, 0x01AC, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 = IOMUX_PAD(0x0438, 0x01AC, 1, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 = IOMUX_PAD(0x0438, 0x01AC, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__ECSPI3_SCLK = IOMUX_PAD(0x0438, 0x01AC, 3, 0x0554, 1, 0), + MX6_PAD_NAND_CE0_B__EIM_DTACK_B = IOMUX_PAD(0x0438, 0x01AC, 4, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__GPIO4_IO13 = IOMUX_PAD(0x0438, 0x01AC, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__UART3_DCE_RX = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0634, 3, 0), + MX6_PAD_NAND_CE0_B__UART3_DTE_TX = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x043C, 0x01B0, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 = IOMUX_PAD(0x043C, 0x01B0, 1, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 = IOMUX_PAD(0x043C, 0x01B0, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__ECSPI3_MOSI = IOMUX_PAD(0x043C, 0x01B0, 3, 0x055C, 1, 0), + MX6_PAD_NAND_CE1_B__EIM_ADDR18 = IOMUX_PAD(0x043C, 0x01B0, 4, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__GPIO4_IO14 = IOMUX_PAD(0x043C, 0x01B0, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__UART3_DCE_CTS = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__UART3_DTE_RTS = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0630, 2, 0), + + MX6_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0440, 0x01B4, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__USDHC1_DATA7 = IOMUX_PAD(0x0440, 0x01B4, 1, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__QSPI_A_DATA03 = IOMUX_PAD(0x0440, 0x01B4, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__ECSPI3_MISO = IOMUX_PAD(0x0440, 0x01B4, 3, 0x0558, 1, 0), + MX6_PAD_NAND_CLE__EIM_ADDR16 = IOMUX_PAD(0x0440, 0x01B4, 4, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__GPIO4_IO15 = IOMUX_PAD(0x0440, 0x01B4, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__UART3_DCE_RTS = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0630, 3, 0), + MX6_PAD_NAND_CLE__UART3_DTE_CTS = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0444, 0x01B8, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__CSI_FIELD = IOMUX_PAD(0x0444, 0x01B8, 1, 0x0530, 1, 0), + MX6_PAD_NAND_DQS__QSPI_A_SS0_B = IOMUX_PAD(0x0444, 0x01B8, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__PWM5_OUT = IOMUX_PAD(0x0444, 0x01B8, 3, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__EIM_WAIT = IOMUX_PAD(0x0444, 0x01B8, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__GPIO4_IO16 = IOMUX_PAD(0x0444, 0x01B8, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__SDMA_EXT_EVENT01 = IOMUX_PAD(0x0444, 0x01B8, 6, 0x0614, 1, 0), + MX6_PAD_NAND_DQS__SPDIF_EXT_CLK = IOMUX_PAD(0x0444, 0x01B8, 8, 0x061C, 1, 0), + + MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0448, 0x01BC, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPT2_COMPARE1 = IOMUX_PAD(0x0448, 0x01BC, 1, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__SAI2_RX_SYNC = IOMUX_PAD(0x0448, 0x01BC, 2, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__SPDIF_OUT = IOMUX_PAD(0x0448, 0x01BC, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__EIM_ADDR19 = IOMUX_PAD(0x0448, 0x01BC, 4, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPIO2_IO16 = IOMUX_PAD(0x0448, 0x01BC, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__SDMA_EXT_EVENT00 = IOMUX_PAD(0x0448, 0x01BC, 6, 0x0610, 2, 0), + MX6_PAD_SD1_CMD__USB_OTG1_PWR = IOMUX_PAD(0x0448, 0x01BC, 8, 0x0000, 0, 0), + + MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x044C, 0x01C0, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPT2_COMPARE2 = IOMUX_PAD(0x044C, 0x01C0, 1, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__SAI2_MCLK = IOMUX_PAD(0x044C, 0x01C0, 2, 0x05F0, 1, 0), + MX6_PAD_SD1_CLK__SPDIF_IN = IOMUX_PAD(0x044C, 0x01C0, 3, 0x0618, 3, 0), + MX6_PAD_SD1_CLK__EIM_ADDR20 = IOMUX_PAD(0x044C, 0x01C0, 4, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPIO2_IO17 = IOMUX_PAD(0x044C, 0x01C0, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__USB_OTG1_OC = IOMUX_PAD(0x044C, 0x01C0, 8, 0x0664, 2, 0), + + MX6_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0450, 0x01C4, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__GPT2_COMPARE3 = IOMUX_PAD(0x0450, 0x01C4, 1, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__SAI2_TX_SYNC = IOMUX_PAD(0x0450, 0x01C4, 2, 0x05FC, 1, 0), + MX6_PAD_SD1_DATA0__FLEXCAN1_TX = IOMUX_PAD(0x0450, 0x01C4, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__EIM_ADDR21 = IOMUX_PAD(0x0450, 0x01C4, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__GPIO2_IO18 = IOMUX_PAD(0x0450, 0x01C4, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID = IOMUX_PAD(0x0450, 0x01C4, 8, 0x04B8, 2, 0), + + MX6_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0454, 0x01C8, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__GPT2_CLK = IOMUX_PAD(0x0454, 0x01C8, 1, 0x05A0, 1, 0), + MX6_PAD_SD1_DATA1__SAI2_TX_BCLK = IOMUX_PAD(0x0454, 0x01C8, 2, 0x05F8, 1, 0), + MX6_PAD_SD1_DATA1__FLEXCAN1_RX = IOMUX_PAD(0x0454, 0x01C8, 3, 0x0584, 3, 0), + MX6_PAD_SD1_DATA1__EIM_ADDR22 = IOMUX_PAD(0x0454, 0x01C8, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__GPIO2_IO19 = IOMUX_PAD(0x0454, 0x01C8, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0454, 0x01C8, 8, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0458, 0x01CC, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__GPT2_CAPTURE1 = IOMUX_PAD(0x0458, 0x01CC, 1, 0x0598, 1, 0), + MX6_PAD_SD1_DATA2__SAI2_RX_DATA = IOMUX_PAD(0x0458, 0x01CC, 2, 0x05F4, 1, 0), + MX6_PAD_SD1_DATA2__FLEXCAN2_TX = IOMUX_PAD(0x0458, 0x01CC, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__EIM_ADDR23 = IOMUX_PAD(0x0458, 0x01CC, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__GPIO2_IO20 = IOMUX_PAD(0x0458, 0x01CC, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__CCM_CLKO1 = IOMUX_PAD(0x0458, 0x01CC, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__USB_OTG2_OC = IOMUX_PAD(0x0458, 0x01CC, 8, 0x0660, 2, 0), + + MX6_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x045C, 0x01D0, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__GPT2_CAPTURE2 = IOMUX_PAD(0x045C, 0x01D0, 1, 0x059C, 1, 0), + MX6_PAD_SD1_DATA3__SAI2_TX_DATA = IOMUX_PAD(0x045C, 0x01D0, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__FLEXCAN2_RX = IOMUX_PAD(0x045C, 0x01D0, 3, 0x0588, 3, 0), + MX6_PAD_SD1_DATA3__EIM_ADDR24 = IOMUX_PAD(0x045C, 0x01D0, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__GPIO2_IO21 = IOMUX_PAD(0x045C, 0x01D0, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__CCM_CLKO2 = IOMUX_PAD(0x045C, 0x01D0, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID = IOMUX_PAD(0x045C, 0x01D0, 8, 0x04BC, 2, 0), + + MX6_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x0460, 0x01D4, 0, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__USDHC2_CD_B = IOMUX_PAD(0x0460, 0x01D4, 1, 0x0674, 0, 0), + MX6_PAD_CSI_MCLK__RAWNAND_CE2_B = IOMUX_PAD(0x0460, 0x01D4, 2, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__I2C1_SDA = IOMUX_PAD(0x0460, 0x01D4, IOMUX_CONFIG_SION | 3, 0x05A8, 0, 0), + MX6_PAD_CSI_MCLK__EIM_CS0_B = IOMUX_PAD(0x0460, 0x01D4, 4, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__GPIO4_IO17 = IOMUX_PAD(0x0460, 0x01D4, 5, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL = IOMUX_PAD(0x0460, 0x01D4, 6, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__UART6_DCE_TX = IOMUX_PAD(0x0460, 0x01D4, 8, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__UART6_DTE_RX = IOMUX_PAD(0x0460, 0x01D4, 8, 0x064C, 0, 0), + + MX6_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x0464, 0x01D8, 0, 0x0528, 1, 0), + MX6_PAD_CSI_PIXCLK__USDHC2_WP = IOMUX_PAD(0x0464, 0x01D8, 1, 0x069C, 2, 0), + MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B = IOMUX_PAD(0x0464, 0x01D8, 2, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__I2C1_SCL = IOMUX_PAD(0x0464, 0x01D8, IOMUX_CONFIG_SION | 3, 0x05A4, 2, 0), + MX6_PAD_CSI_PIXCLK__EIM_OE = IOMUX_PAD(0x0464, 0x01D8, 4, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__GPIO4_IO18 = IOMUX_PAD(0x0464, 0x01D8, 5, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 = IOMUX_PAD(0x0464, 0x01D8, 6, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__UART6_DCE_RX = IOMUX_PAD(0x0464, 0x01D8, 8, 0x064C, 3, 0), + MX6_PAD_CSI_PIXCLK__UART6_DTE_TX = IOMUX_PAD(0x0464, 0x01D8, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x0468, 0x01DC, 0, 0x052C, 0, 0), + MX6_PAD_CSI_VSYNC__USDHC2_CLK = IOMUX_PAD(0x0468, 0x01DC, 1, 0x0670, 0, 0), + MX6_PAD_CSI_VSYNC__SIM1_PORT1_CLK = IOMUX_PAD(0x0468, 0x01DC, 2, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__I2C2_SDA = IOMUX_PAD(0x0468, 0x01DC, IOMUX_CONFIG_SION | 3, 0x05B0, 0, 0), + MX6_PAD_CSI_VSYNC__EIM_RW = IOMUX_PAD(0x0468, 0x01DC, 4, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__GPIO4_IO19 = IOMUX_PAD(0x0468, 0x01DC, 5, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__PWM7_OUT = IOMUX_PAD(0x0468, 0x01DC, 6, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__UART6_DCE_RTS = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0648, 0, 0), + MX6_PAD_CSI_VSYNC__UART6_DTE_CTS = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x046C, 0x01E0, 0, 0x0524, 0, 0), + MX6_PAD_CSI_HSYNC__USDHC2_CMD = IOMUX_PAD(0x046C, 0x01E0, 1, 0x0678, 0, 0), + MX6_PAD_CSI_HSYNC__SIM1_PORT1_PD = IOMUX_PAD(0x046C, 0x01E0, 2, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__I2C2_SCL = IOMUX_PAD(0x046C, 0x01E0, IOMUX_CONFIG_SION | 3, 0x05AC, 0, 0), + MX6_PAD_CSI_HSYNC__EIM_LBA_B = IOMUX_PAD(0x046C, 0x01E0, 4, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__GPIO4_IO20 = IOMUX_PAD(0x046C, 0x01E0, 5, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__PWM8_OUT = IOMUX_PAD(0x046C, 0x01E0, 6, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__UART6_DCE_CTS = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__UART6_DTE_RTS = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0648, 1, 0), + + MX6_PAD_CSI_DATA00__CSI_DATA02 = IOMUX_PAD(0x0470, 0x01E4, 0, 0x04C4, 0, 0), + MX6_PAD_CSI_DATA00__USDHC2_DATA0 = IOMUX_PAD(0x0470, 0x01E4, 1, 0x067C, 0, 0), + MX6_PAD_CSI_DATA00__SIM1_PORT1_RST_B = IOMUX_PAD(0x0470, 0x01E4, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__ECSPI2_SCLK = IOMUX_PAD(0x0470, 0x01E4, 3, 0x0544, 0, 0), + MX6_PAD_CSI_DATA00__EIM_AD00 = IOMUX_PAD(0x0470, 0x01E4, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__GPIO4_IO21 = IOMUX_PAD(0x0470, 0x01E4, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__SRC_INT_BOOT = IOMUX_PAD(0x0470, 0x01E4, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__UART5_DCE_TX = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__UART5_DTE_RX = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0644, 0, 0), + + MX6_PAD_CSI_DATA01__CSI_DATA03 = IOMUX_PAD(0x0474, 0x01E8, 0, 0x04C8, 0, 0), + MX6_PAD_CSI_DATA01__USDHC2_DATA1 = IOMUX_PAD(0x0474, 0x01E8, 1, 0x0680, 0, 0), + MX6_PAD_CSI_DATA01__SIM1_PORT1_SVEN = IOMUX_PAD(0x0474, 0x01E8, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__ECSPI2_SS0 = IOMUX_PAD(0x0474, 0x01E8, 3, 0x0550, 0, 0), + MX6_PAD_CSI_DATA01__EIM_AD01 = IOMUX_PAD(0x0474, 0x01E8, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__GPIO4_IO22 = IOMUX_PAD(0x0474, 0x01E8, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__SAI1_MCLK = IOMUX_PAD(0x0474, 0x01E8, 6, 0x05E0, 0, 0), + MX6_PAD_CSI_DATA01__UART5_DCE_RX = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0644, 1, 0), + MX6_PAD_CSI_DATA01__UART5_DTE_TX = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA02__CSI_DATA04 = IOMUX_PAD(0x0478, 0x01EC, 0, 0x04D8, 1, 0), + MX6_PAD_CSI_DATA02__USDHC2_DATA2 = IOMUX_PAD(0x0478, 0x01EC, 1, 0x0684, 2, 0), + MX6_PAD_CSI_DATA02__SIM1_PORT1_TRXD = IOMUX_PAD(0x0478, 0x01EC, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__ECSPI2_MOSI = IOMUX_PAD(0x0478, 0x01EC, 3, 0x054C, 1, 0), + MX6_PAD_CSI_DATA02__EIM_AD02 = IOMUX_PAD(0x0478, 0x01EC, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__GPIO4_IO23 = IOMUX_PAD(0x0478, 0x01EC, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__SAI1_RX_SYNC = IOMUX_PAD(0x0478, 0x01EC, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__UART5_DCE_RTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0640, 7, 0), + MX6_PAD_CSI_DATA02__UART5_DTE_CTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA03__CSI_DATA05 = IOMUX_PAD(0x047C, 0x01F0, 0, 0x04CC, 0, 0), + MX6_PAD_CSI_DATA03__USDHC2_DATA3 = IOMUX_PAD(0x047C, 0x01F0, 1, 0x0688, 0, 0), + MX6_PAD_CSI_DATA03__SIM2_PORT1_PD = IOMUX_PAD(0x047C, 0x01F0, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__ECSPI2_MISO = IOMUX_PAD(0x047C, 0x01F0, 3, 0x0548, 0, 0), + MX6_PAD_CSI_DATA03__EIM_AD03 = IOMUX_PAD(0x047C, 0x01F0, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__GPIO4_IO24 = IOMUX_PAD(0x047C, 0x01F0, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__SAI1_RX_BCLK = IOMUX_PAD(0x047C, 0x01F0, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__UART5_DCE_CTS = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__UART5_DTE_RTS = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0640, 0, 0), + + MX6_PAD_CSI_DATA04__CSI_DATA06 = IOMUX_PAD(0x0480, 0x01F4, 0, 0x04DC, 1, 0), + MX6_PAD_CSI_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x0480, 0x01F4, 1, 0x068C, 2, 0), + MX6_PAD_CSI_DATA04__SIM2_PORT1_CLK = IOMUX_PAD(0x0480, 0x01F4, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__ECSPI1_SCLK = IOMUX_PAD(0x0480, 0x01F4, 3, 0x0534, 1, 0), + MX6_PAD_CSI_DATA04__EIM_AD04 = IOMUX_PAD(0x0480, 0x01F4, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__GPIO4_IO25 = IOMUX_PAD(0x0480, 0x01F4, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__SAI1_TX_SYNC = IOMUX_PAD(0x0480, 0x01F4, 6, 0x05EC, 1, 0), + MX6_PAD_CSI_DATA04__USDHC1_WP = IOMUX_PAD(0x0480, 0x01F4, 8, 0x066C, 2, 0), + + MX6_PAD_CSI_DATA05__CSI_DATA07 = IOMUX_PAD(0x0484, 0x01F8, 0, 0x04E0, 1, 0), + MX6_PAD_CSI_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x0484, 0x01F8, 1, 0x0690, 2, 0), + MX6_PAD_CSI_DATA05__SIM2_PORT1_RST_B = IOMUX_PAD(0x0484, 0x01F8, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__ECSPI1_SS0 = IOMUX_PAD(0x0484, 0x01F8, 3, 0x0540, 1, 0), + MX6_PAD_CSI_DATA05__EIM_AD05 = IOMUX_PAD(0x0484, 0x01F8, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__GPIO4_IO26 = IOMUX_PAD(0x0484, 0x01F8, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__SAI1_TX_BCLK = IOMUX_PAD(0x0484, 0x01F8, 6, 0x05E8, 1, 0), + MX6_PAD_CSI_DATA05__USDHC1_CD_B = IOMUX_PAD(0x0484, 0x01F8, 8, 0x0668, 2, 0), + + MX6_PAD_CSI_DATA06__CSI_DATA08 = IOMUX_PAD(0x0488, 0x01FC, 0, 0x04E4, 1, 0), + MX6_PAD_CSI_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x0488, 0x01FC, 1, 0x0694, 2, 0), + MX6_PAD_CSI_DATA06__SIM2_PORT1_SVEN = IOMUX_PAD(0x0488, 0x01FC, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__ECSPI1_MOSI = IOMUX_PAD(0x0488, 0x01FC, 3, 0x053C, 1, 0), + MX6_PAD_CSI_DATA06__EIM_AD06 = IOMUX_PAD(0x0488, 0x01FC, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__GPIO4_IO27 = IOMUX_PAD(0x0488, 0x01FC, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__SAI1_RX_DATA = IOMUX_PAD(0x0488, 0x01FC, 6, 0x05E4, 1, 0), + MX6_PAD_CSI_DATA06__USDHC1_RESET_B = IOMUX_PAD(0x0488, 0x01FC, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA07__CSI_DATA09 = IOMUX_PAD(0x048C, 0x0200, 0, 0x04E8, 1, 0), + MX6_PAD_CSI_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x048C, 0x0200, 1, 0x0698, 2, 0), + MX6_PAD_CSI_DATA07__SIM2_PORT1_TRXD = IOMUX_PAD(0x048C, 0x0200, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__ECSPI1_MISO = IOMUX_PAD(0x048C, 0x0200, 3, 0x0538, 1, 0), + MX6_PAD_CSI_DATA07__EIM_AD07 = IOMUX_PAD(0x048C, 0x0200, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__GPIO4_IO28 = IOMUX_PAD(0x048C, 0x0200, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__SAI1_TX_DATA = IOMUX_PAD(0x048C, 0x0200, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__USDHC1_VSELECT = IOMUX_PAD(0x048C, 0x0200, 8, 0x0000, 0, 0), +}; +#endif /* __ASM_ARCH_IMX6ULL_PINS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/mxc_hdmi.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/mxc_hdmi.h new file mode 100644 index 000000000..71ad0e307 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/mxc_hdmi.h @@ -0,0 +1,1057 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + */ + +#ifndef __MXC_HDMI_H__ +#define __MXC_HDMI_H__ + +#ifdef CONFIG_IMX_HDMI +void imx_enable_hdmi_phy(void); +void imx_setup_hdmi(void); +#endif + +/* + * Hdmi controller registers + */ +struct hdmi_regs { + /*Identification Registers */ + u8 design_id; /* 0x000 */ + u8 revision_id; /* 0x001 */ + u8 product_id0; /* 0x002 */ + u8 product_id1; /* 0x003 */ + u8 config0_id; /* 0x004 */ + u8 config1_id; /* 0x005 */ + u8 config2_id; /* 0x006 */ + u8 config3_id; /* 0x007 */ + u8 reserved1[0xf8]; + /* Interrupt Registers */ + u8 ih_fc_stat0; /* 0x100 */ + u8 ih_fc_stat1; /* 0x101 */ + u8 ih_fc_stat2; /* 0x102 */ + u8 ih_as_stat0; /* 0x103 */ + u8 ih_phy_stat0; /* 0x104 */ + u8 ih_i2cm_stat0; /* 0x105 */ + u8 ih_cec_stat0; /* 0x106 */ + u8 ih_vp_stat0; /* 0x107 */ + u8 ih_i2cmphy_stat0; /* 0x108 */ + u8 ih_ahbdmaaud_stat0; /* 0x109 */ + u8 reserved2[0x76]; + u8 ih_mute_fc_stat0; /* 0x180 */ + u8 ih_mute_fc_stat1; /* 0x181 */ + u8 ih_mute_fc_stat2; /* 0x182 */ + u8 ih_mute_as_stat0; /* 0x183 */ + u8 ih_mute_phy_stat0; /* 0x184 */ + u8 ih_mute_i2cm_stat0; /* 0x185 */ + u8 ih_mute_cec_stat0; /* 0x186 */ + u8 ih_mute_vp_stat0; /* 0x187 */ + u8 ih_mute_i2cmphy_stat0; /* 0x188 */ + u8 ih_mute_ahbdmaaud_stat0; /* 0x189 */ + u8 reserved3[0x75]; + u8 ih_mute; /* 0x1ff */ + /* Video Sample Registers */ + u8 tx_invid0; /* 0x200 */ + u8 tx_instuffing; /* 0x201 */ + u8 tx_gydata0; /* 0x202 */ + u8 tx_gydata1; /* 0x203 */ + u8 tx_rcrdata0; /* 0x204 */ + u8 tx_rcrdata1; /* 0x205 */ + u8 tx_bcbdata0; /* 0x206 */ + u8 tx_bcbdata1; /* 0x207 */ + u8 reserved4[0x5f8]; + /* Video Packetizer Registers */ + u8 vp_status; /* 0x800 */ + u8 vp_pr_cd; /* 0x801 */ + u8 vp_stuff; /* 0x802 */ + u8 vp_remap; /* 0x803 */ + u8 vp_conf; /* 0x804 */ + u8 vp_stat; /* 0x805 */ + u8 vp_int; /* 0x806 */ + u8 vp_mask; /* 0x807 */ + u8 vp_pol; /* 0x808 */ + u8 reserved5[0x7f7]; + /* Frame Composer Registers */ + u8 fc_invidconf; /* 0x1000 */ + u8 fc_inhactv0; /* 0x1001 */ + u8 fc_inhactv1; /* 0x1002 */ + u8 fc_inhblank0; /* 0x1003 */ + u8 fc_inhblank1; /* 0x1004 */ + u8 fc_invactv0; /* 0x1005 */ + u8 fc_invactv1; /* 0x1006 */ + u8 fc_invblank; /* 0x1007 */ + u8 fc_hsyncindelay0; /* 0x1008 */ + u8 fc_hsyncindelay1; /* 0x1009 */ + u8 fc_hsyncinwidth0; /* 0x100a */ + u8 fc_hsyncinwidth1; /* 0x100b */ + u8 fc_vsyncindelay; /* 0x100c */ + u8 fc_vsyncinwidth; /* 0x100d */ + u8 fc_infreq0; /* 0x100e */ + u8 fc_infreq1; /* 0x100f */ + u8 fc_infreq2; /* 0x1010 */ + u8 fc_ctrldur; /* 0x1011 */ + u8 fc_exctrldur; /* 0x1012 */ + u8 fc_exctrlspac; /* 0x1013 */ + u8 fc_ch0pream; /* 0x1014 */ + u8 fc_ch1pream; /* 0x1015 */ + u8 fc_ch2pream; /* 0x1016 */ + u8 fc_aviconf3; /* 0x1017 */ + u8 fc_gcp; /* 0x1018 */ + u8 fc_aviconf0; /* 0x1019 */ + u8 fc_aviconf1; /* 0x101a */ + u8 fc_aviconf2; /* 0x101b */ + u8 fc_avivid; /* 0x101c */ + u8 fc_avietb0; /* 0x101d */ + u8 fc_avietb1; /* 0x101e */ + u8 fc_avisbb0; /* 0x101f */ + u8 fc_avisbb1; /* 0x1020 */ + u8 fc_avielb0; /* 0x1021 */ + u8 fc_avielb1; /* 0x1022 */ + u8 fc_avisrb0; /* 0x1023 */ + u8 fc_avisrb1; /* 0x1024 */ + u8 fc_audiconf0; /* 0x1025 */ + u8 fc_audiconf1; /* 0x1026 */ + u8 fc_audiconf2; /* 0x1027 */ + u8 fc_audiconf3; /* 0x1028 */ + u8 fc_vsdieeeid0; /* 0x1029 */ + u8 fc_vsdsize; /* 0x102a */ + u8 reserved6[5]; + u8 fc_vsdieeeid1; /* 0x1030 */ + u8 fc_vsdieeeid2; /* 0x1031 */ + u8 fc_vsdpayload0; /* 0x1032 */ + u8 fc_vsdpayload1; /* 0x1033 */ + u8 fc_vsdpayload2; /* 0x1034 */ + u8 fc_vsdpayload3; /* 0x1035 */ + u8 fc_vsdpayload4; /* 0x1036 */ + u8 fc_vsdpayload5; /* 0x1037 */ + u8 fc_vsdpayload6; /* 0x1038 */ + u8 fc_vsdpayload7; /* 0x1039 */ + u8 fc_vsdpayload8; /* 0x103a */ + u8 fc_vsdpayload9; /* 0x103b */ + u8 fc_vsdpayload10; /* 0x103c */ + u8 fc_vsdpayload11; /* 0x103d */ + u8 fc_vsdpayload12; /* 0x103e */ + u8 fc_vsdpayload13; /* 0x103f */ + u8 fc_vsdpayload14; /* 0x1040 */ + u8 fc_vsdpayload15; /* 0x1041 */ + u8 fc_vsdpayload16; /* 0x1042 */ + u8 fc_vsdpayload17; /* 0x1043 */ + u8 fc_vsdpayload18; /* 0x1044 */ + u8 fc_vsdpayload19; /* 0x1045 */ + u8 fc_vsdpayload20; /* 0x1046 */ + u8 fc_vsdpayload21; /* 0x1047 */ + u8 fc_vsdpayload22; /* 0x1048 */ + u8 fc_vsdpayload23; /* 0x1049 */ + u8 fc_spdvendorname0; /* 0x104a */ + u8 fc_spdvendorname1; /* 0x104b */ + u8 fc_spdvendorname2; /* 0x104c */ + u8 fc_spdvendorname3; /* 0x104d */ + u8 fc_spdvendorname4; /* 0x104e */ + u8 fc_spdvendorname5; /* 0x104f */ + u8 fc_spdvendorname6; /* 0x1050 */ + u8 fc_spdvendorname7; /* 0x1051 */ + u8 fc_sdpproductname0; /* 0x1052 */ + u8 fc_sdpproductname1; /* 0x1053 */ + u8 fc_sdpproductname2; /* 0x1054 */ + u8 fc_sdpproductname3; /* 0x1055 */ + u8 fc_sdpproductname4; /* 0x1056 */ + u8 fc_sdpproductname5; /* 0x1057 */ + u8 fc_sdpproductname6; /* 0x1058 */ + u8 fc_sdpproductname7; /* 0x1059 */ + u8 fc_sdpproductname8; /* 0x105a */ + u8 fc_sdpproductname9; /* 0x105b */ + u8 fc_sdpproductname10; /* 0x105c */ + u8 fc_sdpproductname11; /* 0x105d */ + u8 fc_sdpproductname12; /* 0x105e */ + u8 fc_sdpproductname13; /* 0x105f */ + u8 fc_sdpproductname14; /* 0x1060 */ + u8 fc_spdproductname15; /* 0x1061 */ + u8 fc_spddeviceinf; /* 0x1062 */ + u8 fc_audsconf; /* 0x1063 */ + u8 fc_audsstat; /* 0x1064 */ + u8 reserved7[0xb]; + u8 fc_datach0fill; /* 0x1070 */ + u8 fc_datach1fill; /* 0x1071 */ + u8 fc_datach2fill; /* 0x1072 */ + u8 fc_ctrlqhigh; /* 0x1073 */ + u8 fc_ctrlqlow; /* 0x1074 */ + u8 fc_acp0; /* 0x1075 */ + u8 fc_acp28; /* 0x1076 */ + u8 fc_acp27; /* 0x1077 */ + u8 fc_acp26; /* 0x1078 */ + u8 fc_acp25; /* 0x1079 */ + u8 fc_acp24; /* 0x107a */ + u8 fc_acp23; /* 0x107b */ + u8 fc_acp22; /* 0x107c */ + u8 fc_acp21; /* 0x107d */ + u8 fc_acp20; /* 0x107e */ + u8 fc_acp19; /* 0x107f */ + u8 fc_acp18; /* 0x1080 */ + u8 fc_acp17; /* 0x1081 */ + u8 fc_acp16; /* 0x1082 */ + u8 fc_acp15; /* 0x1083 */ + u8 fc_acp14; /* 0x1084 */ + u8 fc_acp13; /* 0x1085 */ + u8 fc_acp12; /* 0x1086 */ + u8 fc_acp11; /* 0x1087 */ + u8 fc_acp10; /* 0x1088 */ + u8 fc_acp9; /* 0x1089 */ + u8 fc_acp8; /* 0x108a */ + u8 fc_acp7; /* 0x108b */ + u8 fc_acp6; /* 0x108c */ + u8 fc_acp5; /* 0x108d */ + u8 fc_acp4; /* 0x108e */ + u8 fc_acp3; /* 0x108f */ + u8 fc_acp2; /* 0x1090 */ + u8 fc_acp1; /* 0x1091 */ + u8 fc_iscr1_0; /* 0x1092 */ + u8 fc_iscr1_16; /* 0x1093 */ + u8 fc_iscr1_15; /* 0x1094 */ + u8 fc_iscr1_14; /* 0x1095 */ + u8 fc_iscr1_13; /* 0x1096 */ + u8 fc_iscr1_12; /* 0x1097 */ + u8 fc_iscr1_11; /* 0x1098 */ + u8 fc_iscr1_10; /* 0x1099 */ + u8 fc_iscr1_9; /* 0x109a */ + u8 fc_iscr1_8; /* 0x109b */ + u8 fc_iscr1_7; /* 0x109c */ + u8 fc_iscr1_6; /* 0x109d */ + u8 fc_iscr1_5; /* 0x109e */ + u8 fc_iscr1_4; /* 0x109f */ + u8 fc_iscr1_3; /* 0x10a0 */ + u8 fc_iscr1_2; /* 0x10a1 */ + u8 fc_iscr1_1; /* 0x10a2 */ + u8 fc_iscr2_15; /* 0x10a3 */ + u8 fc_iscr2_14; /* 0x10a4 */ + u8 fc_iscr2_13; /* 0x10a5 */ + u8 fc_iscr2_12; /* 0x10a6 */ + u8 fc_iscr2_11; /* 0x10a7 */ + u8 fc_iscr2_10; /* 0x10a8 */ + u8 fc_iscr2_9; /* 0x10a9 */ + u8 fc_iscr2_8; /* 0x10aa */ + u8 fc_iscr2_7; /* 0x10ab */ + u8 fc_iscr2_6; /* 0x10ac */ + u8 fc_iscr2_5; /* 0x10ad */ + u8 fc_iscr2_4; /* 0x10ae */ + u8 fc_iscr2_3; /* 0x10af */ + u8 fc_iscr2_2; /* 0x10b0 */ + u8 fc_iscr2_1; /* 0x10b1 */ + u8 fc_iscr2_0; /* 0x10b2 */ + u8 fc_datauto0; /* 0x10b3 */ + u8 fc_datauto1; /* 0x10b4 */ + u8 fc_datauto2; /* 0x10b5 */ + u8 fc_datman; /* 0x10b6 */ + u8 fc_datauto3; /* 0x10b7 */ + u8 fc_rdrb0; /* 0x10b8 */ + u8 fc_rdrb1; /* 0x10b9 */ + u8 fc_rdrb2; /* 0x10ba */ + u8 fc_rdrb3; /* 0x10bb */ + u8 fc_rdrb4; /* 0x10bc */ + u8 fc_rdrb5; /* 0x10bd */ + u8 fc_rdrb6; /* 0x10be */ + u8 fc_rdrb7; /* 0x10bf */ + u8 reserved8[0x10]; + u8 fc_stat0; /* 0x10d0 */ + u8 fc_int0; /* 0x10d1 */ + u8 fc_mask0; /* 0x10d2 */ + u8 fc_pol0; /* 0x10d3 */ + u8 fc_stat1; /* 0x10d4 */ + u8 fc_int1; /* 0x10d5 */ + u8 fc_mask1; /* 0x10d6 */ + u8 fc_pol1; /* 0x10d7 */ + u8 fc_stat2; /* 0x10d8 */ + u8 fc_int2; /* 0x10d9 */ + u8 fc_mask2; /* 0x10da */ + u8 fc_pol2; /* 0x10db */ + u8 reserved9[0x4]; + u8 fc_prconf; /* 0x10e0 */ + u8 reserved10[0x1f]; + u8 fc_gmd_stat; /* 0x1100 */ + u8 fc_gmd_en; /* 0x1101 */ + u8 fc_gmd_up; /* 0x1102 */ + u8 fc_gmd_conf; /* 0x1103 */ + u8 fc_gmd_hb; /* 0x1104 */ + u8 fc_gmd_pb0; /* 0x1105 */ + u8 fc_gmd_pb1; /* 0x1106 */ + u8 fc_gmd_pb2; /* 0x1107 */ + u8 fc_gmd_pb3; /* 0x1108 */ + u8 fc_gmd_pb4; /* 0x1109 */ + u8 fc_gmd_pb5; /* 0x110a */ + u8 fc_gmd_pb6; /* 0x110b */ + u8 fc_gmd_pb7; /* 0x110c */ + u8 fc_gmd_pb8; /* 0x110d */ + u8 fc_gmd_pb9; /* 0x110e */ + u8 fc_gmd_pb10; /* 0x110f */ + u8 fc_gmd_pb11; /* 0x1110 */ + u8 fc_gmd_pb12; /* 0x1111 */ + u8 fc_gmd_pb13; /* 0x1112 */ + u8 fc_gmd_pb14; /* 0x1113 */ + u8 fc_gmd_pb15; /* 0x1114 */ + u8 fc_gmd_pb16; /* 0x1115 */ + u8 fc_gmd_pb17; /* 0x1116 */ + u8 fc_gmd_pb18; /* 0x1117 */ + u8 fc_gmd_pb19; /* 0x1118 */ + u8 fc_gmd_pb20; /* 0x1119 */ + u8 fc_gmd_pb21; /* 0x111a */ + u8 fc_gmd_pb22; /* 0x111b */ + u8 fc_gmd_pb23; /* 0x111c */ + u8 fc_gmd_pb24; /* 0x111d */ + u8 fc_gmd_pb25; /* 0x111e */ + u8 fc_gmd_pb26; /* 0x111f */ + u8 fc_gmd_pb27; /* 0x1120 */ + u8 reserved11[0xdf]; + u8 fc_dbgforce; /* 0x1200 */ + u8 fc_dbgaud0ch0; /* 0x1201 */ + u8 fc_dbgaud1ch0; /* 0x1202 */ + u8 fc_dbgaud2ch0; /* 0x1203 */ + u8 fc_dbgaud0ch1; /* 0x1204 */ + u8 fc_dbgaud1ch1; /* 0x1205 */ + u8 fc_dbgaud2ch1; /* 0x1206 */ + u8 fc_dbgaud0ch2; /* 0x1207 */ + u8 fc_dbgaud1ch2; /* 0x1208 */ + u8 fc_dbgaud2ch2; /* 0x1209 */ + u8 fc_dbgaud0ch3; /* 0x120a */ + u8 fc_dbgaud1ch3; /* 0x120b */ + u8 fc_dbgaud2ch3; /* 0x120c */ + u8 fc_dbgaud0ch4; /* 0x120d */ + u8 fc_dbgaud1ch4; /* 0x120e */ + u8 fc_dbgaud2ch4; /* 0x120f */ + u8 fc_dbgaud0ch5; /* 0x1210 */ + u8 fc_dbgaud1ch5; /* 0x1211 */ + u8 fc_dbgaud2ch5; /* 0x1212 */ + u8 fc_dbgaud0ch6; /* 0x1213 */ + u8 fc_dbgaud1ch6; /* 0x1214 */ + u8 fc_dbgaud2ch6; /* 0x1215 */ + u8 fc_dbgaud0ch7; /* 0x1216 */ + u8 fc_dbgaud1ch7; /* 0x1217 */ + u8 fc_dbgaud2ch7; /* 0x1218 */ + u8 fc_dbgtmds0; /* 0x1219 */ + u8 fc_dbgtmds1; /* 0x121a */ + u8 fc_dbgtmds2; /* 0x121b */ + u8 reserved12[0x1de4]; + /* Hdmi Source Phy Registers */ + u8 phy_conf0; /* 0x3000 */ + u8 phy_tst0; /* 0x3001 */ + u8 phy_tst1; /* 0x3002 */ + u8 phy_tst2; /* 0x3003 */ + u8 phy_stat0; /* 0x3004 */ + u8 phy_int0; /* 0x3005 */ + u8 phy_mask0; /* 0x3006 */ + u8 phy_pol0; /* 0x3007 */ + u8 reserved13[0x18]; + /* Hdmi Master Phy Registers */ + u8 phy_i2cm_slave_addr; /* 0x3020 */ + u8 phy_i2cm_address_addr; /* 0x3021 */ + u8 phy_i2cm_datao_1_addr; /* 0x3022 */ + u8 phy_i2cm_datao_0_addr; /* 0x3023 */ + u8 phy_i2cm_datai_1_addr; /* 0x3024 */ + u8 phy_i2cm_datai_0_addr; /* 0x3025 */ + u8 phy_i2cm_operation_addr; /* 0x3026 */ + u8 phy_i2cm_int_addr; /* 0x3027 */ + u8 phy_i2cm_ctlint_addr; /* 0x3028 */ + u8 phy_i2cm_div_addr; /* 0x3029 */ + u8 phy_i2cm_softrstz_addr; /* 0x302a */ + u8 phy_i2cm_ss_scl_hcnt_1_addr; /* 0x302b */ + u8 phy_i2cm_ss_scl_hcnt_0_addr; /* 0x302c */ + u8 phy_i2cm_ss_scl_lcnt_1_addr; /* 0x302d */ + u8 phy_i2cm_ss_scl_lcnt_0_addr; /* 0x302e */ + u8 phy_i2cm_fs_scl_hcnt_1_addr; /* 0x302f */ + u8 phy_i2cm_fs_scl_hcnt_0_addr; /* 0x3030 */ + u8 phy_i2cm_fs_scl_lcnt_1_addr; /* 0x3031 */ + u8 phy_i2cm_fs_scl_lcnt_0_addr; /* 0x3032 */ + u8 reserved14[0xcd]; + /* Audio Sampler Registers */ + u8 aud_conf0; /* 0x3100 */ + u8 aud_conf1; /* 0x3101 */ + u8 aud_int; /* 0x3102 */ + u8 aud_conf2; /* 0x3103 */ + u8 reserved15[0xfc]; + u8 aud_n1; /* 0x3200 */ + u8 aud_n2; /* 0x3201 */ + u8 aud_n3; /* 0x3202 */ + u8 aud_cts1; /* 0x3203 */ + u8 aud_cts2; /* 0x3204 */ + u8 aud_cts3; /* 0x3205 */ + u8 aud_inputclkfs; /* 0x3206 */ + u8 reserved16[0xfb]; + u8 aud_spdifint; /* 0x3302 */ + u8 reserved17[0xfd]; + u8 aud_conf0_hbr; /* 0x3400 */ + u8 aud_hbr_status; /* 0x3401 */ + u8 aud_hbr_int; /* 0x3402 */ + u8 aud_hbr_pol; /* 0x3403 */ + u8 aud_hbr_mask; /* 0x3404 */ + u8 reserved18[0xfb]; + /* + * Generic Parallel Audio Interface Registers + * Not used as GPAUD interface is not enabled in hw + */ + u8 gp_conf0; /* 0x3500 */ + u8 gp_conf1; /* 0x3501 */ + u8 gp_conf2; /* 0x3502 */ + u8 gp_stat; /* 0x3503 */ + u8 gp_int; /* 0x3504 */ + u8 gp_mask; /* 0x3505 */ + u8 gp_pol; /* 0x3506 */ + u8 reserved19[0xf9]; + /* Audio DMA Registers */ + u8 ahb_dma_conf0; /* 0x3600 */ + u8 ahb_dma_start; /* 0x3601 */ + u8 ahb_dma_stop; /* 0x3602 */ + u8 ahb_dma_thrsld; /* 0x3603 */ + u8 ahb_dma_straddr0; /* 0x3604 */ + u8 ahb_dma_straddr1; /* 0x3605 */ + u8 ahb_dma_straddr2; /* 0x3606 */ + u8 ahb_dma_straddr3; /* 0x3607 */ + u8 ahb_dma_stpaddr0; /* 0x3608 */ + u8 ahb_dma_stpaddr1; /* 0x3609 */ + u8 ahb_dma_stpaddr2; /* 0x360a */ + u8 ahb_dma_stpaddr3; /* 0x360b */ + u8 ahb_dma_bstaddr0; /* 0x360c */ + u8 ahb_dma_bstaddr1; /* 0x360d */ + u8 ahb_dma_bstaddr2; /* 0x360e */ + u8 ahb_dma_bstaddr3; /* 0x360f */ + u8 ahb_dma_mblength0; /* 0x3610 */ + u8 ahb_dma_mblength1; /* 0x3611 */ + u8 ahb_dma_stat; /* 0x3612 */ + u8 ahb_dma_int; /* 0x3613 */ + u8 ahb_dma_mask; /* 0x3614 */ + u8 ahb_dma_pol; /* 0x3615 */ + u8 ahb_dma_conf1; /* 0x3616 */ + u8 ahb_dma_buffstat; /* 0x3617 */ + u8 ahb_dma_buffint; /* 0x3618 */ + u8 ahb_dma_buffmask; /* 0x3619 */ + u8 ahb_dma_buffpol; /* 0x361a */ + u8 reserved20[0x9e5]; + /* Main Controller Registers */ + u8 mc_sfrdiv; /* 0x4000 */ + u8 mc_clkdis; /* 0x4001 */ + u8 mc_swrstz; /* 0x4002 */ + u8 mc_opctrl; /* 0x4003 */ + u8 mc_flowctrl; /* 0x4004 */ + u8 mc_phyrstz; /* 0x4005 */ + u8 mc_lockonclock; /* 0x4006 */ + u8 mc_heacphy_rst; /* 0x4007 */ + u8 reserved21[0xf8]; + /* Colorspace Converter Registers */ + u8 csc_cfg; /* 0x4100 */ + u8 csc_scale; /* 0x4101 */ + u8 csc_coef_a1_msb; /* 0x4102 */ + u8 csc_coef_a1_lsb; /* 0x4103 */ + u8 csc_coef_a2_msb; /* 0x4104 */ + u8 csc_coef_a2_lsb; /* 0x4105 */ + u8 csc_coef_a3_msb; /* 0x4106 */ + u8 csc_coef_a3_lsb; /* 0x4107 */ + u8 csc_coef_a4_msb; /* 0x4108 */ + u8 csc_coef_a4_lsb; /* 0x4109 */ + u8 csc_coef_b1_msb; /* 0x410a */ + u8 csc_coef_b1_lsb; /* 0x410b */ + u8 csc_coef_b2_msb; /* 0x410c */ + u8 csc_coef_b2_lsb; /* 0x410d */ + u8 csc_coef_b3_msb; /* 0x410e */ + u8 csc_coef_b3_lsb; /* 0x410f */ + u8 csc_coef_b4_msb; /* 0x4110 */ + u8 csc_coef_b4_lsb; /* 0x4111 */ + u8 csc_coef_c1_msb; /* 0x4112 */ + u8 csc_coef_c1_lsb; /* 0x4113 */ + u8 csc_coef_c2_msb; /* 0x4114 */ + u8 csc_coef_c2_lsb; /* 0x4115 */ + u8 csc_coef_c3_msb; /* 0x4116 */ + u8 csc_coef_c3_lsb; /* 0x4117 */ + u8 csc_coef_c4_msb; /* 0x4118 */ + u8 csc_coef_c4_lsb; /* 0x4119 */ + u8 reserved22[0xee6]; + /* HDCP Encryption Engine Registers */ + u8 a_hdcpcfg0; /* 0x5000 */ + u8 a_hdcpcfg1; /* 0x5001 */ + u8 a_hdcpobs0; /* 0x5002 */ + u8 a_hdcpobs1; /* 0x5003 */ + u8 a_hdcpobs2; /* 0x5004 */ + u8 a_hdcpobs3; /* 0x5005 */ + u8 a_apiintclr; /* 0x5006 */ + u8 a_apiintstat; /* 0x5007 */ + u8 a_apiintmsk; /* 0x5008 */ + u8 a_vidpolcfg; /* 0x5009 */ + u8 a_oesswcfg; /* 0x500a */ + u8 a_timer1setup0; /* 0x500b */ + u8 a_timer1setup1; /* 0x500c */ + u8 a_timer2setup0; /* 0x500d */ + u8 a_timer2setup1; /* 0x500e */ + u8 a_100mscfg; /* 0x500f */ + u8 a_2scfg0; /* 0x5010 */ + u8 a_2scfg1; /* 0x5011 */ + u8 a_5scfg0; /* 0x5012 */ + u8 a_5scfg1; /* 0x5013 */ + u8 a_srmverlsb; /* 0x5014 */ + u8 a_srmvermsb; /* 0x5015 */ + u8 a_srmctrl; /* 0x5016 */ + u8 a_sfrsetup; /* 0x5017 */ + u8 a_i2chsetup; /* 0x5018 */ + u8 a_intsetup; /* 0x5019 */ + u8 a_presetup; /* 0x501a */ + u8 reserved23[0x5]; + u8 a_srm_base; /* 0x5020 */ + u8 reserved24[0x2cdf]; + /* CEC Engine Registers */ + u8 cec_ctrl; /* 0x7d00 */ + u8 cec_stat; /* 0x7d01 */ + u8 cec_mask; /* 0x7d02 */ + u8 cec_polarity; /* 0x7d03 */ + u8 cec_int; /* 0x7d04 */ + u8 cec_addr_l; /* 0x7d05 */ + u8 cec_addr_h; /* 0x7d06 */ + u8 cec_tx_cnt; /* 0x7d07 */ + u8 cec_rx_cnt; /* 0x7d08 */ + u8 reserved25[0x7]; + u8 cec_tx_data0; /* 0x7d10 */ + u8 cec_tx_data1; /* 0x7d11 */ + u8 cec_tx_data2; /* 0x7d12 */ + u8 cec_tx_data3; /* 0x7d13 */ + u8 cec_tx_data4; /* 0x7d14 */ + u8 cec_tx_data5; /* 0x7d15 */ + u8 cec_tx_data6; /* 0x7d16 */ + u8 cec_tx_data7; /* 0x7d17 */ + u8 cec_tx_data8; /* 0x7d18 */ + u8 cec_tx_data9; /* 0x7d19 */ + u8 cec_tx_data10; /* 0x7d1a */ + u8 cec_tx_data11; /* 0x7d1b */ + u8 cec_tx_data12; /* 0x7d1c */ + u8 cec_tx_data13; /* 0x7d1d */ + u8 cec_tx_data14; /* 0x7d1e */ + u8 cec_tx_data15; /* 0x7d1f */ + u8 cec_rx_data0; /* 0x7d20 */ + u8 cec_rx_data1; /* 0x7d21 */ + u8 cec_rx_data2; /* 0x7d22 */ + u8 cec_rx_data3; /* 0x7d23 */ + u8 cec_rx_data4; /* 0x7d24 */ + u8 cec_rx_data5; /* 0x7d25 */ + u8 cec_rx_data6; /* 0x7d26 */ + u8 cec_rx_data7; /* 0x7d27 */ + u8 cec_rx_data8; /* 0x7d28 */ + u8 cec_rx_data9; /* 0x7d29 */ + u8 cec_rx_data10; /* 0x7d2a */ + u8 cec_rx_data11; /* 0x7d2b */ + u8 cec_rx_data12; /* 0x7d2c */ + u8 cec_rx_data13; /* 0x7d2d */ + u8 cec_rx_data14; /* 0x7d2e */ + u8 cec_rx_data15; /* 0x7d2f */ + u8 cec_lock; /* 0x7d30 */ + u8 cec_wkupctrl; /* 0x7d31 */ + u8 reserved26[0xce]; + /* I2C Master Registers (E-DDC) */ + u8 i2cm_slave; /* 0x7e00 */ + u8 i2cmess; /* 0x7e01 */ + u8 i2cm_datao; /* 0x7e02 */ + u8 i2cm_datai; /* 0x7e03 */ + u8 i2cm_operation; /* 0x7e04 */ + u8 i2cm_int; /* 0x7e05 */ + u8 i2cm_ctlint; /* 0x7e06 */ + u8 i2cm_div; /* 0x7e07 */ + u8 i2cm_segaddr; /* 0x7e08 */ + u8 i2cm_softrstz; /* 0x7e09 */ + u8 i2cm_segptr; /* 0x7e0a */ + u8 i2cm_ss_scl_hcnt_1_addr; /* 0x7e0b */ + u8 i2cm_ss_scl_hcnt_0_addr; /* 0x7e0c */ + u8 i2cm_ss_scl_lcnt_1_addr; /* 0x7e0d */ + u8 i2cm_ss_scl_lcnt_0_addr; /* 0x7e0e */ + u8 i2cm_fs_scl_hcnt_1_addr; /* 0x7e0f */ + u8 i2cm_fs_scl_hcnt_0_addr; /* 0x7e10 */ + u8 i2cm_fs_scl_lcnt_1_addr; /* 0x7e11 */ + u8 i2cm_fs_scl_lcnt_0_addr; /* 0x7e12 */ + u8 reserved27[0x1ed]; + /* Random Number Generator Registers (RNG) */ + u8 rng_base; /* 0x8000 */ +}; + +/* + * Register field definitions + */ +enum { +/* IH_FC_INT2 field values */ + HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03, + HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* IH_FC_STAT2 field values */ + HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03, + HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* IH_PHY_STAT0 field values */ + HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20, + HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10, + HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8, + HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4, + HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2, + HDMI_IH_PHY_STAT0_HPD = 0x1, + +/* IH_MUTE_I2CMPHY_STAT0 field values */ + HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2, + HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1, + +/* IH_AHBDMAAUD_STAT0 field values */ + HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20, + HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10, + HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08, + HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04, + HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02, + HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01, + +/* IH_MUTE_FC_STAT2 field values */ + HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03, + HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* IH_MUTE_AHBDMAAUD_STAT0 field values */ + HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20, + HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10, + HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08, + HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04, + HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02, + HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01, + +/* IH_MUTE field values */ + HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2, + HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1, + +/* TX_INVID0 field values */ + HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80, + HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80, + HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00, + HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F, + HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0, + +/* TX_INSTUFFING field values */ + HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4, + HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4, + HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0, + HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2, + HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2, + HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0, + HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1, + HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1, + HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0, + +/* VP_PR_CD field values */ + HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0, + HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4, + HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F, + HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0, + +/* VP_STUFF field values */ + HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20, + HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5, + HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10, + HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4, + HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8, + HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3, + HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4, + HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4, + HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0, + HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2, + HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2, + HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0, + HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1, + HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1, + HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0, + +/* VP_CONF field values */ + HDMI_VP_CONF_BYPASS_EN_MASK = 0x40, + HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40, + HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00, + HDMI_VP_CONF_PP_EN_ENMASK = 0x20, + HDMI_VP_CONF_PP_EN_ENABLE = 0x20, + HDMI_VP_CONF_PP_EN_DISABLE = 0x00, + HDMI_VP_CONF_PR_EN_MASK = 0x10, + HDMI_VP_CONF_PR_EN_ENABLE = 0x10, + HDMI_VP_CONF_PR_EN_DISABLE = 0x00, + HDMI_VP_CONF_YCC422_EN_MASK = 0x8, + HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8, + HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0, + HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4, + HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4, + HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0, + HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3, + HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3, + HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1, + HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0, + +/* VP_REMAP field values */ + HDMI_VP_REMAP_MASK = 0x3, + HDMI_VP_REMAP_YCC422_24bit = 0x2, + HDMI_VP_REMAP_YCC422_20bit = 0x1, + HDMI_VP_REMAP_YCC422_16bit = 0x0, + +/* FC_INVIDCONF field values */ + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80, + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80, + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8, + HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8, + HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0, + HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1, + HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1, + HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0, + +/* FC_AUDICONF0 field values */ + HDMI_FC_AUDICONF0_CC_OFFSET = 4, + HDMI_FC_AUDICONF0_CC_MASK = 0x70, + HDMI_FC_AUDICONF0_CT_OFFSET = 0, + HDMI_FC_AUDICONF0_CT_MASK = 0xF, + +/* FC_AUDICONF1 field values */ + HDMI_FC_AUDICONF1_SS_OFFSET = 3, + HDMI_FC_AUDICONF1_SS_MASK = 0x18, + HDMI_FC_AUDICONF1_SF_OFFSET = 0, + HDMI_FC_AUDICONF1_SF_MASK = 0x7, + +/* FC_AUDICONF3 field values */ + HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5, + HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60, + HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4, + HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10, + HDMI_FC_AUDICONF3_LSV_OFFSET = 0, + HDMI_FC_AUDICONF3_LSV_MASK = 0xF, + +/* FC_AUDSCHNLS0 field values */ + HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4, + HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30, + HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0, + HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01, + +/* FC_AUDSCHNLS3-6 field values */ + HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0, + HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f, + HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4, + HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0, + HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0, + HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f, + HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4, + HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0, + + HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0, + HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f, + HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4, + HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0, + HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0, + HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f, + HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4, + HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0, + +/* HDMI_FC_AUDSCHNLS7 field values */ + HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4, + HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30, + +/* HDMI_FC_AUDSCHNLS8 field values */ + HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0, + HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4, + HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f, + HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0, + +/* FC_AUDSCONF field values */ + HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0, + HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4, + HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1, + HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0, + HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1, + HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0, + +/* FC_STAT2 field values */ + HDMI_FC_STAT2_OVERFLOW_MASK = 0x03, + HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* FC_INT2 field values */ + HDMI_FC_INT2_OVERFLOW_MASK = 0x03, + HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* FC_MASK2 field values */ + HDMI_FC_MASK2_OVERFLOW_MASK = 0x03, + HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* FC_PRCONF field values */ + HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0, + HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4, + HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F, + HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0, + +/* FC_AVICONF0-FC_AVICONF3 field values */ + HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, + HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00, + HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01, + HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02, + HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40, + HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40, + HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00, + HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C, + HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00, + HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04, + HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08, + HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C, + HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30, + HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10, + HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20, + HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00, + + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20, + HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0, + HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00, + HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40, + HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80, + HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0, + + HDMI_FC_AVICONF2_SCALING_MASK = 0x03, + HDMI_FC_AVICONF2_SCALING_NONE = 0x00, + HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01, + HDMI_FC_AVICONF2_SCALING_VERT = 0x02, + HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03, + HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C, + HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00, + HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04, + HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40, + HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80, + HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00, + HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80, + + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03, + HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C, + HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, + HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, + +/* FC_DBGFORCE field values */ + HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10, + HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1, + +/* PHY_CONF0 field values */ + HDMI_PHY_CONF0_PDZ_MASK = 0x80, + HDMI_PHY_CONF0_PDZ_OFFSET = 7, + HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, + HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, + HDMI_PHY_CONF0_SPARECTRL = 0x20, + HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, + HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, + HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, + HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3, + HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4, + HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2, + HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2, + HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1, + HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1, + HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0, + +/* PHY_TST0 field values */ + HDMI_PHY_TST0_TSTCLR_MASK = 0x20, + HDMI_PHY_TST0_TSTCLR_OFFSET = 5, + HDMI_PHY_TST0_TSTEN_MASK = 0x10, + HDMI_PHY_TST0_TSTEN_OFFSET = 4, + HDMI_PHY_TST0_TSTCLK_MASK = 0x1, + HDMI_PHY_TST0_TSTCLK_OFFSET = 0, + +/* PHY_STAT0 field values */ + HDMI_PHY_RX_SENSE3 = 0x80, + HDMI_PHY_RX_SENSE2 = 0x40, + HDMI_PHY_RX_SENSE1 = 0x20, + HDMI_PHY_RX_SENSE0 = 0x10, + HDMI_PHY_HPD = 0x02, + HDMI_PHY_TX_PHY_LOCK = 0x01, + +/* Convenience macro RX_SENSE | HPD */ + HDMI_DVI_STAT = 0xF2, + +/* PHY_I2CM_SLAVE_ADDR field values */ + HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, + HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49, + +/* PHY_I2CM_OPERATION_ADDR field values */ + HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10, + HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1, + +/* HDMI_PHY_I2CM_INT_ADDR */ + HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08, + HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04, + +/* HDMI_PHY_I2CM_CTLINT_ADDR */ + HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80, + HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40, + HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08, + HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04, + +/* AUD_CTS3 field values */ + HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5, + HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0, + HDMI_AUD_CTS3_N_SHIFT_1 = 0, + HDMI_AUD_CTS3_N_SHIFT_16 = 0x20, + HDMI_AUD_CTS3_N_SHIFT_32 = 0x40, + HDMI_AUD_CTS3_N_SHIFT_64 = 0x60, + HDMI_AUD_CTS3_N_SHIFT_128 = 0x80, + HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0, + /* note that the CTS3 MANUAL bit has been removed + from our part. Can't set it, will read as 0. */ + HDMI_AUD_CTS3_CTS_MANUAL = 0x10, + HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f, + +/* AHB_DMA_CONF0 field values */ + HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7, + HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80, + HDMI_AHB_DMA_CONF0_HBR = 0x10, + HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3, + HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08, + HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1, + HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06, + HDMI_AHB_DMA_CONF0_INCR4 = 0x0, + HDMI_AHB_DMA_CONF0_INCR8 = 0x2, + HDMI_AHB_DMA_CONF0_INCR16 = 0x4, + HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1, + +/* HDMI_AHB_DMA_START field values */ + HDMI_AHB_DMA_START_START_OFFSET = 0, + HDMI_AHB_DMA_START_START_MASK = 0x01, + +/* HDMI_AHB_DMA_STOP field values */ + HDMI_AHB_DMA_STOP_STOP_OFFSET = 0, + HDMI_AHB_DMA_STOP_STOP_MASK = 0x01, + +/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */ + HDMI_AHB_DMA_DONE = 0x80, + HDMI_AHB_DMA_RETRY_SPLIT = 0x40, + HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20, + HDMI_AHB_DMA_ERROR = 0x10, + HDMI_AHB_DMA_FIFO_THREMPTY = 0x04, + HDMI_AHB_DMA_FIFO_FULL = 0x02, + HDMI_AHB_DMA_FIFO_EMPTY = 0x01, + +/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT, AHB_DMA_BUFFMASK, AHB_DMA_BUFFPOL field values */ + HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02, + HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01, + +/* MC_CLKDIS field values */ + HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40, + HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20, + HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10, + HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8, + HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4, + HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2, + HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, + +/* MC_SWRSTZ field values */ + HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, + +/* MC_FLOWCTRL field values */ + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1, + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1, + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0, + +/* MC_PHYRSTZ field values */ + HDMI_MC_PHYRSTZ_ASSERT = 0x0, + HDMI_MC_PHYRSTZ_DEASSERT = 0x1, + +/* MC_HEACPHY_RST field values */ + HDMI_MC_HEACPHY_RST_ASSERT = 0x1, + HDMI_MC_HEACPHY_RST_DEASSERT = 0x0, + +/* CSC_CFG field values */ + HDMI_CSC_CFG_INTMODE_MASK = 0x30, + HDMI_CSC_CFG_INTMODE_OFFSET = 4, + HDMI_CSC_CFG_INTMODE_DISABLE = 0x00, + HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10, + HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20, + HDMI_CSC_CFG_DECMODE_MASK = 0x3, + HDMI_CSC_CFG_DECMODE_OFFSET = 0, + HDMI_CSC_CFG_DECMODE_DISABLE = 0x0, + HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1, + HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2, + HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3, + +/* CSC_SCALE field values */ + HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70, + HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03, + +/* A_HDCPCFG0 field values */ + HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80, + HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80, + HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00, + HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40, + HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40, + HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00, + HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20, + HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20, + HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00, + HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10, + HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10, + HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00, + HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8, + HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8, + HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0, + HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4, + HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4, + HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0, + HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2, + HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2, + HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0, + HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1, + HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1, + HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0, + +/* A_HDCPCFG1 field values */ + HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8, + HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8, + HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0, + HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4, + HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4, + HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0, + HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2, + HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2, + HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0, + HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1, + HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0, + +/* A_VIDPOLCFG field values */ + HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60, + HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5, + HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10, + HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10, + HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0, + HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8, + HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8, + HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0, + HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2, + HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2, + HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0, +}; + +#endif /* __MXC_HDMI_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/opos6ul.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/opos6ul.h new file mode 100644 index 000000000..b55a54cf1 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/opos6ul.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Armadeus Systems + */ + +#ifndef __ARCH_ARM_MX6UL_OPOS6UL_H__ +#define __ARCH_ARM_MX6UL_OPOS6UL_H__ + +int opos6ul_board_late_init(void); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx6/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-mx6/sys_proto.h new file mode 100644 index 000000000..1e5fa1a75 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + */ + +#ifndef __SYS_PROTO_IMX6_ +#define __SYS_PROTO_IMX6_ + +#include +#include + +#define USBPHY_PWD 0x00000000 + +#define USBPHY_PWD_RXPWDRX (1 << 20) /* receiver block power down */ + +#define is_usbotg_phy_active(void) (!(readl(USB_PHY0_BASE_ADDR + USBPHY_PWD) & \ + USBPHY_PWD_RXPWDRX)) + +int imx6_pcie_toggle_power(void); +int imx6_pcie_toggle_reset(void); + +enum ldo_reg { + LDO_ARM, + LDO_SOC, + LDO_PU, +}; + +int set_ldo_voltage(enum ldo_reg ldo, u32 mv); + +/** + * iomuxc_set_rgmii_io_voltage - set voltage level of RGMII/USB pins + * + * @param io_vol - the voltage IO level of pins + */ +static inline void iomuxc_set_rgmii_io_voltage(int io_vol) +{ + __raw_writel(io_vol, IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII); +} + +#endif /* __SYS_PROTO_IMX6_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx7/clock.h b/roms/u-boot/arch/arm/include/asm/arch-mx7/clock.h new file mode 100644 index 000000000..48c7c3367 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx7/clock.h @@ -0,0 +1,364 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Author: + * Peng Fan + */ + +#ifndef _ASM_ARCH_CLOCK_H +#define _ASM_ARCH_CLOCK_H + +#include + +#ifdef CONFIG_SYS_MX7_HCLK +#define MXC_HCLK CONFIG_SYS_MX7_HCLK +#else +#define MXC_HCLK 24000000 +#endif + +#ifdef CONFIG_SYS_MX7_CLK32 +#define MXC_CLK32 CONFIG_SYS_MX7_CLK32 +#else +#define MXC_CLK32 32768 +#endif + +/* Mainly for compatible to imx common code. */ +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_UART_CLK, + MXC_CSPI_CLK, + MXC_AXI_CLK, + MXC_DDR_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, + MXC_I2C_CLK, +}; + +/* PLL supported by i.mx7d */ +enum pll_clocks { + PLL_CORE, /* Core PLL */ + PLL_SYS, /* System PLL*/ + PLL_ENET, /* Enet PLL */ + PLL_AUDIO, /* Audio PLL */ + PLL_VIDEO, /* Video PLL*/ + PLL_DDR, /* Dram PLL */ + PLL_USB, /* USB PLL, fixed at 480MHZ */ +}; + +/* clk src for clock root gen */ +enum clk_root_src { + OSC_24M_CLK, + + PLL_ARM_MAIN_800M_CLK, + + PLL_SYS_MAIN_480M_CLK, + PLL_SYS_MAIN_240M_CLK, + PLL_SYS_MAIN_120M_CLK, + PLL_SYS_PFD0_392M_CLK, + PLL_SYS_PFD0_196M_CLK, + PLL_SYS_PFD1_332M_CLK, + PLL_SYS_PFD1_166M_CLK, + PLL_SYS_PFD2_270M_CLK, + PLL_SYS_PFD2_135M_CLK, + PLL_SYS_PFD3_CLK, + PLL_SYS_PFD4_CLK, + PLL_SYS_PFD5_CLK, + PLL_SYS_PFD6_CLK, + PLL_SYS_PFD7_CLK, + + PLL_ENET_MAIN_500M_CLK, + PLL_ENET_MAIN_250M_CLK, + PLL_ENET_MAIN_125M_CLK, + PLL_ENET_MAIN_100M_CLK, + PLL_ENET_MAIN_50M_CLK, + PLL_ENET_MAIN_40M_CLK, + PLL_ENET_MAIN_25M_CLK, + + PLL_DRAM_MAIN_1066M_CLK, + PLL_DRAM_MAIN_533M_CLK, + + PLL_AUDIO_MAIN_CLK, + PLL_VIDEO_MAIN_CLK, + + PLL_USB_MAIN_480M_CLK, /* fixed at 480MHZ */ + + EXT_CLK_1, + EXT_CLK_2, + EXT_CLK_3, + EXT_CLK_4, + + REF_1M_CLK, + OSC_32K_CLK, +}; + +/* + * Clock root index + */ +enum clk_root_index { + ARM_A7_CLK_ROOT = 0, + ARM_M4_CLK_ROOT = 1, + ARM_M0_CLK_ROOT = 2, + MAIN_AXI_CLK_ROOT = 16, + DISP_AXI_CLK_ROOT = 17, + ENET_AXI_CLK_ROOT = 18, + NAND_USDHC_BUS_CLK_ROOT = 19, + AHB_CLK_ROOT = 32, + DRAM_PHYM_CLK_ROOT = 48, + DRAM_CLK_ROOT = 49, + DRAM_PHYM_ALT_CLK_ROOT = 64, + DRAM_ALT_CLK_ROOT = 65, + USB_HSIC_CLK_ROOT = 66, + PCIE_CTRL_CLK_ROOT = 67, + PCIE_PHY_CLK_ROOT = 68, + EPDC_PIXEL_CLK_ROOT = 69, + LCDIF_PIXEL_CLK_ROOT = 70, + MIPI_DSI_EXTSER_CLK_ROOT = 71, + MIPI_CSI_WARP_CLK_ROOT = 72, + MIPI_DPHY_REF_CLK_ROOT = 73, + SAI1_CLK_ROOT = 74, + SAI2_CLK_ROOT = 75, + SAI3_CLK_ROOT = 76, + SPDIF_CLK_ROOT = 77, + ENET1_REF_CLK_ROOT = 78, + ENET1_TIME_CLK_ROOT = 79, + ENET2_REF_CLK_ROOT = 80, + ENET2_TIME_CLK_ROOT = 81, + ENET_PHY_REF_CLK_ROOT = 82, + EIM_CLK_ROOT = 83, + NAND_CLK_ROOT = 84, + QSPI_CLK_ROOT = 85, + USDHC1_CLK_ROOT = 86, + USDHC2_CLK_ROOT = 87, + USDHC3_CLK_ROOT = 88, + CAN1_CLK_ROOT = 89, + CAN2_CLK_ROOT = 90, + I2C1_CLK_ROOT = 91, + I2C2_CLK_ROOT = 92, + I2C3_CLK_ROOT = 93, + I2C4_CLK_ROOT = 94, + UART1_CLK_ROOT = 95, + UART2_CLK_ROOT = 96, + UART3_CLK_ROOT = 97, + UART4_CLK_ROOT = 98, + UART5_CLK_ROOT = 99, + UART6_CLK_ROOT = 100, + UART7_CLK_ROOT = 101, + ECSPI1_CLK_ROOT = 102, + ECSPI2_CLK_ROOT = 103, + ECSPI3_CLK_ROOT = 104, + ECSPI4_CLK_ROOT = 105, + PWM1_CLK_ROOT = 106, + PWM2_CLK_ROOT = 107, + PWM3_CLK_ROOT = 108, + PWM4_CLK_ROOT = 109, + FLEXTIMER1_CLK_ROOT = 110, + FLEXTIMER2_CLK_ROOT = 111, + SIM1_CLK_ROOT = 112, + SIM2_CLK_ROOT = 113, + GPT1_CLK_ROOT = 114, + GPT2_CLK_ROOT = 115, + GPT3_CLK_ROOT = 116, + GPT4_CLK_ROOT = 117, + TRACE_CLK_ROOT = 118, + WDOG_CLK_ROOT = 119, + CSI_MCLK_CLK_ROOT = 120, + AUDIO_MCLK_CLK_ROOT = 121, + WRCLK_CLK_ROOT = 122, + IPP_DO_CLKO1 = 123, + IPP_DO_CLKO2 = 124, + + CLK_ROOT_MAX, +}; + +#if (CONFIG_CONS_INDEX == 0) +#define UART_CLK_ROOT UART1_CLK_ROOT +#elif (CONFIG_CONS_INDEX == 1) +#define UART_CLK_ROOT UART2_CLK_ROOT +#elif (CONFIG_CONS_INDEX == 2) +#define UART_CLK_ROOT UART3_CLK_ROOT +#elif (CONFIG_CONS_INDEX == 3) +#define UART_CLK_ROOT UART4_CLK_ROOT +#elif (CONFIG_CONS_INDEX == 4) +#define UART_CLK_ROOT UART5_CLK_ROOT +#elif (CONFIG_CONS_INDEX == 5) +#define UART_CLK_ROOT UART6_CLK_ROOT +#elif (CONFIG_CONS_INDEX == 6) +#define UART_CLK_ROOT UART7_CLK_ROOT +#else +#error "Invalid IMX UART ID for serial console is defined" +#endif + +struct clk_root_setting { + enum clk_root_index root; + u32 setting; +}; + +/* + * CCGR mapping + */ +enum clk_ccgr_index { + CCGR_CPU = 0, + CCGR_M4 = 1, + CCGR_SIM_MAIN = 4, + CCGR_SIM_DISPLAY = 5, + CCGR_SIM_ENET = 6, + CCGR_SIM_M = 7, + CCGR_SIM_S = 8, + CCGR_SIM_WAKEUP = 9, + CCGR_IPMUX1 = 10, + CCGR_IPMUX2 = 11, + CCGR_IPMUX3 = 12, + CCGR_ROM = 16, + CCGR_OCRAM = 17, + CCGR_OCRAM_S = 18, + CCGR_DRAM = 19, + CCGR_RAWNAND = 20, + CCGR_QSPI = 21, + CCGR_WEIM = 22, + CCGR_ADC = 32, + CCGR_ANATOP = 33, + CCGR_SCTR = 34, + CCGR_OCOTP = 35, + CCGR_CAAM = 36, + CCGR_SNVS = 37, + CCGR_RDC = 38, + CCGR_MU = 39, + CCGR_HS = 40, + CCGR_DVFS = 41, + CCGR_QOS = 42, + CCGR_QOS_DISPMIX = 43, + CCGR_QOS_MEGAMIX = 44, + CCGR_CSU = 45, + CCGR_DBGMON = 46, + CCGR_DEBUG = 47, + CCGR_TRACE = 48, + CCGR_SEC_DEBUG = 49, + CCGR_SEMA1 = 64, + CCGR_SEMA2 = 65, + CCGR_PERFMON1 = 68, + CCGR_PERFMON2 = 69, + CCGR_SDMA = 72, + CCGR_CSI = 73, + CCGR_EPDC = 74, + CCGR_LCDIF = 75, + CCGR_PXP = 76, + CCGR_PCIE = 96, + CCGR_MIPI_CSI = 100, + CCGR_MIPI_DSI = 101, + CCGR_MIPI_MEM_PHY = 102, + CCGR_USB_CTRL = 104, + CCGR_USB_HSIC = 105, + CCGR_USB_PHY1 = 106, + CCGR_USB_PHY2 = 107, + CCGR_USDHC1 = 108, + CCGR_USDHC2 = 109, + CCGR_USDHC3 = 110, + CCGR_ENET1 = 112, + CCGR_ENET2 = 113, + CCGR_CAN1 = 116, + CCGR_CAN2 = 117, + CCGR_ECSPI1 = 120, + CCGR_ECSPI2 = 121, + CCGR_ECSPI3 = 122, + CCGR_ECSPI4 = 123, + CCGR_GPT1 = 124, + CCGR_GPT2 = 125, + CCGR_GPT3 = 126, + CCGR_GPT4 = 127, + CCGR_FTM1 = 128, + CCGR_FTM2 = 129, + CCGR_PWM1 = 132, + CCGR_PWM2 = 133, + CCGR_PWM3 = 134, + CCGR_PWM4 = 135, + CCGR_I2C1 = 136, + CCGR_I2C2 = 137, + CCGR_I2C3 = 138, + CCGR_I2C4 = 139, + CCGR_SAI1 = 140, + CCGR_SAI2 = 141, + CCGR_SAI3 = 142, + CCGR_SIM1 = 144, + CCGR_SIM2 = 145, + CCGR_UART1 = 148, + CCGR_UART2 = 149, + CCGR_UART3 = 150, + CCGR_UART4 = 151, + CCGR_UART5 = 152, + CCGR_UART6 = 153, + CCGR_UART7 = 154, + CCGR_WDOG1 = 156, + CCGR_WDOG2 = 157, + CCGR_WDOG3 = 158, + CCGR_WDOG4 = 159, + CCGR_GPIO1 = 160, + CCGR_GPIO2 = 161, + CCGR_GPIO3 = 162, + CCGR_GPIO4 = 163, + CCGR_GPIO5 = 164, + CCGR_GPIO6 = 165, + CCGR_GPIO7 = 166, + CCGR_IOMUX = 168, + CCGR_IOMUX_LPSR = 169, + CCGR_KPP = 170, + + CCGR_SKIP, + CCGR_MAX, +}; + +/* Clock root channel */ +enum clk_root_type { + CCM_CORE_CHANNEL, + CCM_BUS_CHANNEL, + CCM_AHB_CHANNEL, + CCM_DRAM_PHYM_CHANNEL, + CCM_DRAM_CHANNEL, + CCM_IP_CHANNEL, +}; + +#include + +/* + * entry: the clock root index + * type: ccm channel + * src_mux: each entry corresponding to the clock src, detailed info in CCM RM + */ +struct clk_root_map { + enum clk_root_index entry; + enum clk_root_type type; + uint8_t src_mux[8]; +}; + +enum enet_freq { + ENET_25MHZ, + ENET_50MHZ, + ENET_125MHZ, +}; + +u32 get_root_clk(enum clk_root_index clock_id); +u32 mxc_get_clock(enum mxc_clock clk); +u32 imx_get_uartclk(void); +u32 imx_get_fecclk(void); +void clock_init(void); +#ifdef CONFIG_SYS_I2C_MXC +int enable_i2c_clk(unsigned char enable, unsigned i2c_num); +#endif +#ifdef CONFIG_FEC_MXC +int set_clk_enet(enum enet_freq type); +#endif +int set_clk_qspi(void); +int set_clk_nand(void); +#ifdef CONFIG_MXC_OCOTP +void enable_ocotp_clk(unsigned char enable); +#endif +void enable_usboh3_clk(unsigned char enable); +#ifdef CONFIG_IMX_HAB +void hab_caam_clock_enable(unsigned char enable); +#endif +void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq); +void enable_thermal_clk(void); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx7/clock_slice.h b/roms/u-boot/arch/arm/include/asm/arch-mx7/clock_slice.h new file mode 100644 index 000000000..9a7c1f823 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx7/clock_slice.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * Author: + * Peng Fan + */ + +#ifndef _ASM_ARCH_CLOCK_SLICE_H +#define _ASM_ARCH_CLOCK_SLICE_H + +enum root_pre_div { + CLK_ROOT_PRE_DIV1 = 0, + CLK_ROOT_PRE_DIV2, + CLK_ROOT_PRE_DIV3, + CLK_ROOT_PRE_DIV4, + CLK_ROOT_PRE_DIV5, + CLK_ROOT_PRE_DIV6, + CLK_ROOT_PRE_DIV7, + CLK_ROOT_PRE_DIV8, +}; + +enum root_post_div { + CLK_ROOT_POST_DIV1 = 0, + CLK_ROOT_POST_DIV2, + CLK_ROOT_POST_DIV3, + CLK_ROOT_POST_DIV4, + CLK_ROOT_POST_DIV5, + CLK_ROOT_POST_DIV6, + CLK_ROOT_POST_DIV7, + CLK_ROOT_POST_DIV8, + CLK_ROOT_POST_DIV9, + CLK_ROOT_POST_DIV10, + CLK_ROOT_POST_DIV11, + CLK_ROOT_POST_DIV12, + CLK_ROOT_POST_DIV13, + CLK_ROOT_POST_DIV14, + CLK_ROOT_POST_DIV15, + CLK_ROOT_POST_DIV16, + CLK_ROOT_POST_DIV17, + CLK_ROOT_POST_DIV18, + CLK_ROOT_POST_DIV19, + CLK_ROOT_POST_DIV20, + CLK_ROOT_POST_DIV21, + CLK_ROOT_POST_DIV22, + CLK_ROOT_POST_DIV23, + CLK_ROOT_POST_DIV24, + CLK_ROOT_POST_DIV25, + CLK_ROOT_POST_DIV26, + CLK_ROOT_POST_DIV27, + CLK_ROOT_POST_DIV28, + CLK_ROOT_POST_DIV29, + CLK_ROOT_POST_DIV30, + CLK_ROOT_POST_DIV31, + CLK_ROOT_POST_DIV32, + CLK_ROOT_POST_DIV33, + CLK_ROOT_POST_DIV34, + CLK_ROOT_POST_DIV35, + CLK_ROOT_POST_DIV36, + CLK_ROOT_POST_DIV37, + CLK_ROOT_POST_DIV38, + CLK_ROOT_POST_DIV39, + CLK_ROOT_POST_DIV40, + CLK_ROOT_POST_DIV41, + CLK_ROOT_POST_DIV42, + CLK_ROOT_POST_DIV43, + CLK_ROOT_POST_DIV44, + CLK_ROOT_POST_DIV45, + CLK_ROOT_POST_DIV46, + CLK_ROOT_POST_DIV47, + CLK_ROOT_POST_DIV48, + CLK_ROOT_POST_DIV49, + CLK_ROOT_POST_DIV50, + CLK_ROOT_POST_DIV51, + CLK_ROOT_POST_DIV52, + CLK_ROOT_POST_DIV53, + CLK_ROOT_POST_DIV54, + CLK_ROOT_POST_DIV55, + CLK_ROOT_POST_DIV56, + CLK_ROOT_POST_DIV57, + CLK_ROOT_POST_DIV58, + CLK_ROOT_POST_DIV59, + CLK_ROOT_POST_DIV60, + CLK_ROOT_POST_DIV61, + CLK_ROOT_POST_DIV62, + CLK_ROOT_POST_DIV63, + CLK_ROOT_POST_DIV64, +}; + +enum root_auto_div { + CLK_ROOT_AUTO_DIV1 = 0, + CLK_ROOT_AUTO_DIV2, + CLK_ROOT_AUTO_DIV4, + CLK_ROOT_AUTO_DIV8, + CLK_ROOT_AUTO_DIV16, +}; + +int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src); +int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src); +int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div); +int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div); +int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div); +int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div); +int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div, + int auto_en); +int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div, + int *auto_en); +int clock_get_target_val(enum clk_root_index clock_id, u32 *val); +int clock_set_target_val(enum clk_root_index clock_id, u32 val); +int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div, + enum root_post_div post_div, enum clk_root_src clock_src); +int clock_root_enabled(enum clk_root_index clock_id); + +int clock_enable(enum clk_ccgr_index index, bool enable); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx7/crm_regs.h b/roms/u-boot/arch/arm/include/asm/arch-mx7/crm_regs.h new file mode 100644 index 000000000..bfa68a9d2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx7/crm_regs.h @@ -0,0 +1,2817 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Author: + * Peng Fan + */ + +#ifndef __ARCH_ARM_MACH_MX7_CCM_REGS_H__ +#define __ARCH_ARM_MACH_MX7_CCM_REGS_H__ + +#include +#include + +#define CCM_GPR0_OFFSET 0x0 +#define CCM_OBSERVE0_OFFSET 0x0400 +#define CCM_SCTRL0_OFFSET 0x0800 +#define CCM_CCGR0_OFFSET 0x4000 +#define CCM_ROOT0_TARGET_OFFSET 0x8000 + +#ifndef __ASSEMBLY__ + +struct mxc_ccm_ccgr { + uint32_t ccgr; + uint32_t ccgr_set; + uint32_t ccgr_clr; + uint32_t ccgr_tog; +}; + +struct mxc_ccm_root_slice { + uint32_t target_root; + uint32_t target_root_set; + uint32_t target_root_clr; + uint32_t target_root_tog; + uint32_t reserved_0[4]; + uint32_t post; + uint32_t post_root_set; + uint32_t post_root_clr; + uint32_t post_root_tog; + uint32_t pre; + uint32_t pre_root_set; + uint32_t pre_root_clr; + uint32_t pre_root_tog; + uint32_t reserved_1[12]; + uint32_t access_ctrl; + uint32_t access_ctrl_root_set; + uint32_t access_ctrl_root_clr; + uint32_t access_ctrl_root_tog; +}; + +/** CCM - Peripheral register structure */ +struct mxc_ccm_reg { + uint32_t gpr0; + uint32_t gpr0_set; + uint32_t gpr0_clr; + uint32_t gpr0_tog; + uint32_t reserved_0[4092]; + struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */ + uint32_t reserved_1[3332]; + struct mxc_ccm_root_slice root[125]; /* offset 0x8000 */ + +}; + +struct mxc_ccm_anatop_reg { + uint32_t ctrl_24m; /* offset 0x0000 */ + uint32_t ctrl_24m_set; + uint32_t ctrl_24m_clr; + uint32_t ctrl_24m_tog; + uint32_t rcosc_config0; /* offset 0x0010 */ + uint32_t rcosc_config0_set; + uint32_t rcosc_config0_clr; + uint32_t rcosc_config0_tog; + uint32_t rcosc_config1; /* offset 0x0020 */ + uint32_t rcosc_config1_set; + uint32_t rcosc_config1_clr; + uint32_t rcosc_config1_tog; + uint32_t rcosc_config2; /* offset 0x0030 */ + uint32_t rcosc_config2_set; + uint32_t rcosc_config2_clr; + uint32_t rcosc_config2_tog; + uint8_t reserved_0[16]; + uint32_t osc_32k; /* offset 0x0050 */ + uint32_t osc_32k_set; + uint32_t osc_32k_clr; + uint32_t osc_32k_tog; + uint32_t pll_arm; /* offset 0x0060 */ + uint32_t pll_arm_set; + uint32_t pll_arm_clr; + uint32_t pll_arm_tog; + uint32_t pll_ddr; /* offset 0x0070 */ + uint32_t pll_ddr_set; + uint32_t pll_ddr_clr; + uint32_t pll_ddr_tog; + uint32_t pll_ddr_ss; /* offset 0x0080 */ + uint8_t reserved_1[12]; + uint32_t pll_ddr_num; /* offset 0x0090 */ + uint8_t reserved_2[12]; + uint32_t pll_ddr_denom; /* offset 0x00a0 */ + uint8_t reserved_3[12]; + uint32_t pll_480; /* offset 0x00b0 */ + uint32_t pll_480_set; + uint32_t pll_480_clr; + uint32_t pll_480_tog; + uint32_t pfd_480a; /* offset 0x00c0 */ + uint32_t pfd_480a_set; + uint32_t pfd_480a_clr; + uint32_t pfd_480a_tog; + uint32_t pfd_480b; /* offset 0x00d0 */ + uint32_t pfd_480b_set; + uint32_t pfd_480b_clr; + uint32_t pfd_480b_tog; + uint32_t pll_enet; /* offset 0x00e0 */ + uint32_t pll_enet_set; + uint32_t pll_enet_clr; + uint32_t pll_enet_tog; + uint32_t pll_audio; /* offset 0x00f0 */ + uint32_t pll_audio_set; + uint32_t pll_audio_clr; + uint32_t pll_audio_tog; + uint32_t pll_audio_ss; /* offset 0x0100 */ + uint8_t reserved_4[12]; + uint32_t pll_audio_num; /* offset 0x0110 */ + uint8_t reserved_5[12]; + uint32_t pll_audio_denom; /* offset 0x0120 */ + uint8_t reserved_6[12]; + uint32_t pll_video; /* offset 0x0130 */ + uint32_t pll_video_set; + uint32_t pll_video_clr; + uint32_t pll_video_tog; + uint32_t pll_video_ss; /* offset 0x0140 */ + uint8_t reserved_7[12]; + uint32_t pll_video_num; /* offset 0x0150 */ + uint8_t reserved_8[12]; + uint32_t pll_video_denom; /* offset 0x0160 */ + uint8_t reserved_9[12]; + uint32_t clk_misc0; /* offset 0x0170 */ + uint32_t clk_misc0_set; + uint32_t clk_misc0_clr; + uint32_t clk_misc0_tog; + uint32_t clk_rsvd; /* offset 0x0180 */ + uint8_t reserved_10[124]; + uint32_t reg_1p0a; /* offset 0x0200 */ + uint32_t reg_1p0a_set; + uint32_t reg_1p0a_clr; + uint32_t reg_1p0a_tog; + uint32_t reg_1p0d; /* offsest 0x0210 */ + uint32_t reg_1p0d_set; + uint32_t reg_1p0d_clr; + uint32_t reg_1p0d_tog; + uint32_t reg_hsic_1p2; /* offset 0x0220 */ + uint32_t reg_hsic_1p2_set; + uint32_t reg_hsic_1p2_clr; + uint32_t reg_hsic_1p2_tog; + uint32_t reg_lpsr_1p0; /* offset 0x0230 */ + uint32_t reg_lpsr_1p0_set; + uint32_t reg_lpsr_1p0_clr; + uint32_t reg_lpsr_1p0_tog; + uint32_t reg_3p0; /* offset 0x0240 */ + uint32_t reg_3p0_set; + uint32_t reg_3p0_clr; + uint32_t reg_3p0_tog; + uint32_t reg_snvs; /* offset 0x0250 */ + uint32_t reg_snvs_set; + uint32_t reg_snvs_clr; + uint32_t reg_snvs_tog; + uint32_t analog_debug_misc0; /* offset 0x0260 */ + uint32_t analog_debug_misc0_set; + uint32_t analog_debug_misc0_clr; + uint32_t analog_debug_misc0_tog; + uint32_t ref; /* offset 0x0270 */ + uint32_t ref_set; + uint32_t ref_clr; + uint32_t ref_tog; + uint8_t reserved_11[128]; + uint32_t tempsense0; /* offset 0x0300 */ + uint32_t tempsense0_set; + uint32_t tempsense0_clr; + uint32_t tempsense0_tog; + uint32_t tempsense1; /* offset 0x0310 */ + uint32_t tempsense1_set; + uint32_t tempsense1_clr; + uint32_t tempsense1_tog; + uint32_t tempsense_trim; /* offset 0x0320 */ + uint32_t tempsense_trim_set; + uint32_t tempsense_trim_clr; + uint32_t tempsense_trim_tog; + uint32_t lowpwr_ctrl; /* offset 0x0330 */ + uint32_t lowpwr_ctrl_set; + uint32_t lowpwr_ctrl_clr; + uint32_t lowpwr_ctrl_tog; + uint32_t snvs_tamper_offset_ctrl; /* offset 0x0340 */ + uint32_t snvs_tamper_offset_ctrl_set; + uint32_t snvs_tamper_offset_ctrl_clr; + uint32_t snvs_tamper_offset_ctrl_tog; + uint32_t snvs_tamper_pull_ctrl; /* offset 0x0350 */ + uint32_t snvs_tamper_pull_ctrl_set; + uint32_t snvs_tamper_pull_ctrl_clr; + uint32_t snvs_tamper_pull_ctrl_tog; + uint32_t snvs_test; /* offset 0x0360 */ + uint32_t snvs_test_set; + uint32_t snvs_test_clr; + uint32_t snvs_test_tog; + uint32_t snvs_tamper_trim_ctrl; /* offset 0x0370 */ + uint32_t snvs_tamper_trim_ctrl_set; + uint32_t snvs_tamper_trim_ctrl_ctrl; + uint32_t snvs_tamper_trim_ctrl_tog; + uint32_t snvs_misc_ctrl; /* offset 0x0380 */ + uint32_t snvs_misc_ctrl_set; + uint32_t snvs_misc_ctrl_clr; + uint32_t snvs_misc_ctrl_tog; + uint8_t reserved_12[112]; + uint32_t misc; /* offset 0x0400 */ + uint8_t reserved_13[252]; + uint32_t adc0; /* offset 0x0500 */ + uint8_t reserved_14[12]; + uint32_t adc1; /* offset 0x0510 */ + uint8_t reserved_15[748]; + uint32_t digprog; /* offset 0x0800 */ +}; +#endif + +#define ANADIG_CLK_MISC0_PFD_480_AUTOGATE_EN_MASK (0x01 << 17) + +#define ANADIG_PLL_LOCK 0x80000000 + +#define ANADIG_PLL_ARM_PWDN_MASK (0x01 << 12) +#define ANADIG_PLL_480_PWDN_MASK (0x01 << 12) +#define ANADIG_PLL_DDR_PWDN_MASK (0x01 << 20) +#define ANADIG_PLL_ENET_PWDN_MASK (0x01 << 5) +#define ANADIG_PLL_VIDEO_PWDN_MASK (0x01 << 12) + + +#define ANATOP_PFD480B_PFD4_FRAC_MASK 0x0000003f +#define ANATOP_PFD480B_PFD4_FRAC_320M_VAL 0x0000001B +#define ANATOP_PFD480B_PFD4_FRAC_392M_VAL 0x00000016 +#define ANATOP_PFD480B_PFD4_FRAC_432M_VAL 0x00000014 + +/* PLL_ARM Bit Fields */ +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK 0x7F +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_ARM_HALF_LF_MASK 0x80 +#define CCM_ANALOG_PLL_ARM_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_MASK 0x100 +#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_ARM_HALF_CP_MASK 0x200 +#define CCM_ANALOG_PLL_ARM_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_MASK 0x400 +#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_MASK 0x800 +#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK 0x1000 +#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_MASK 0x2000 +#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK 0xC000 +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_ARM_BYPASS_MASK 0x10000 +#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_ARM_LVDS_SEL_MASK 0x20000 +#define CCM_ANALOG_PLL_ARM_LVDS_SEL_SHIFT 17 +#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_MASK 0x40000 +#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_SHIFT 18 +#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK 0x80000 +#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT 19 +#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_MASK 0x100000 +#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_SHIFT 20 +#define CCM_ANALOG_PLL_ARM_RSVD0_MASK 0x7FE00000 +#define CCM_ANALOG_PLL_ARM_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_ARM_LOCK_MASK 0x80000000 +#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT 31 + +/* PLL_DDR Bit Fields */ +#define CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK 0x7F +#define CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_DDR_HALF_LF_MASK 0x80 +#define CCM_ANALOG_PLL_DDR_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_MASK 0x100 +#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_DDR_HALF_CP_MASK 0x200 +#define CCM_ANALOG_PLL_DDR_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_MASK 0x400 +#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_MASK 0x800 +#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK 0x1000 +#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_SHIFT 12 +#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_MASK 0x2000 +#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_MASK 0xC000 +#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_DDR_BYPASS_MASK 0x10000 +#define CCM_ANALOG_PLL_DDR_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_MASK 0x20000 +#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_MASK 0x40000 +#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_MASK 0x80000 +#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_SHIFT 19 +#define CCM_ANALOG_PLL_DDR_POWERDOWN_MASK 0x100000 +#define CCM_ANALOG_PLL_DDR_POWERDOWN_SHIFT 20 +#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_MASK 0x600000 +#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_SHIFT 21 +#define CCM_ANALOG_PLL_DDR_RSVD1_MASK 0x7F800000 +#define CCM_ANALOG_PLL_DDR_RSVD1_SHIFT 23 +#define CCM_ANALOG_PLL_DDR_LOCK_MASK 0x80000000 +#define CCM_ANALOG_PLL_DDR_LOCK_SHIFT 31 + +/* PLL_480 Bit Fields */ +#define CCM_ANALOG_PLL_480_DIV_SELECT_MASK 0x1 +#define CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_480_RSVD0_MASK 0xE +#define CCM_ANALOG_PLL_480_RSVD0_SHIFT 1 +#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK 0x10 +#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_SHIFT 4 +#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK 0x20 +#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_SHIFT 5 +#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK 0x40 +#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_SHIFT 6 +#define CCM_ANALOG_PLL_480_HALF_LF_MASK 0x80 +#define CCM_ANALOG_PLL_480_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_480_DOUBLE_LF_MASK 0x100 +#define CCM_ANALOG_PLL_480_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_480_HALF_CP_MASK 0x200 +#define CCM_ANALOG_PLL_480_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_480_DOUBLE_CP_MASK 0x400 +#define CCM_ANALOG_PLL_480_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_MASK 0x800 +#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_480_POWERDOWN_MASK 0x1000 +#define CCM_ANALOG_PLL_480_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_480_ENABLE_CLK_MASK 0x2000 +#define CCM_ANALOG_PLL_480_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_MASK 0xC000 +#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_480_BYPASS_MASK 0x10000 +#define CCM_ANALOG_PLL_480_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_MASK 0x20000 +#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_SHIFT 17 +#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_MASK 0x40000 +#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_SHIFT 18 +#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_MASK 0x80000 +#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_SHIFT 19 +#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_MASK 0x100000 +#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_SHIFT 20 +#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_MASK 0x200000 +#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_SHIFT 21 +#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_MASK 0x400000 +#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_SHIFT 22 +#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_MASK 0x800000 +#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_SHIFT 23 +#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_MASK 0x1000000 +#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_MASK 0x2000000 +#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_SHIFT 25 +#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK 0x4000000 +#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_SHIFT 26 +#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK 0x8000000 +#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_SHIFT 27 +#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK 0x10000000 +#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_SHIFT 28 +#define CCM_ANALOG_PLL_480_RSVD1_MASK 0x60000000 +#define CCM_ANALOG_PLL_480_RSVD1_SHIFT 29 +#define CCM_ANALOG_PLL_480_LOCK_MASK 0x80000000 +#define CCM_ANALOG_PLL_480_LOCK_SHIFT 31 + +/* PFD_480A Bit Fields */ +#define CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK 0x3F +#define CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT 0 +#define CCM_ANALOG_PFD_480A_PFD0_STABLE_MASK 0x40 +#define CCM_ANALOG_PFD_480A_PFD0_STABLE_SHIFT 6 +#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK 0x80 +#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_SHIFT 7 +#define CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK 0x3F00 +#define CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT 8 +#define CCM_ANALOG_PFD_480A_PFD1_STABLE_MASK 0x4000 +#define CCM_ANALOG_PFD_480A_PFD1_STABLE_SHIFT 14 +#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK 0x8000 +#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_SHIFT 15 +#define CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK 0x3F0000 +#define CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT 16 +#define CCM_ANALOG_PFD_480A_PFD2_STABLE_MASK 0x400000 +#define CCM_ANALOG_PFD_480A_PFD2_STABLE_SHIFT 22 +#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK 0x800000 +#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_SHIFT 23 +#define CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK 0x3F000000 +#define CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT 24 +#define CCM_ANALOG_PFD_480A_PFD3_STABLE_MASK 0x40000000 +#define CCM_ANALOG_PFD_480A_PFD3_STABLE_SHIFT 30 +#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK 0x80000000 +#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_SHIFT 31 +/* PFD_480B Bit Fields */ +#define CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK 0x3F +#define CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT 0 +#define CCM_ANALOG_PFD_480B_PFD4_STABLE_MASK 0x40 +#define CCM_ANALOG_PFD_480B_PFD4_STABLE_SHIFT 6 +#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK 0x80 +#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_SHIFT 7 +#define CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK 0x3F00 +#define CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT 8 +#define CCM_ANALOG_PFD_480B_PFD5_STABLE_MASK 0x4000 +#define CCM_ANALOG_PFD_480B_PFD5_STABLE_SHIFT 14 +#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK 0x8000 +#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_SHIFT 15 +#define CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK 0x3F0000 +#define CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT 16 +#define CCM_ANALOG_PFD_480B_PFD6_STABLE_MASK 0x400000 +#define CCM_ANALOG_PFD_480B_PFD6_STABLE_SHIFT 22 +#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK 0x800000 +#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_SHIFT 23 +#define CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK 0x3F000000 +#define CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT 24 +#define CCM_ANALOG_PFD_480B_PFD7_STABLE_MASK 0x40000000 +#define CCM_ANALOG_PFD_480B_PFD7_STABLE_SHIFT 30 +#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK 0x80000000 +#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_SHIFT 31 + +/* PLL_ENET Bit Fields */ +#define CCM_ANALOG_PLL_ENET_HALF_LF_MASK 0x1 +#define CCM_ANALOG_PLL_ENET_HALF_LF_SHIFT 0 +#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_MASK 0x2 +#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_SHIFT 1 +#define CCM_ANALOG_PLL_ENET_HALF_CP_MASK 0x4 +#define CCM_ANALOG_PLL_ENET_HALF_CP_SHIFT 2 +#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_MASK 0x8 +#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_SHIFT 3 +#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_MASK 0x10 +#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_SHIFT 4 +#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK 0x20 +#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT 5 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK 0x40 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_SHIFT 6 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK 0x80 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_SHIFT 7 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK 0x100 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_SHIFT 8 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK 0x200 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_SHIFT 9 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK 0x400 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_SHIFT 10 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK 0x800 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_SHIFT 11 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK 0x1000 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_SHIFT 12 +#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_MASK 0x2000 +#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_SHIFT 13 +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK 0xC000 +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_ENET_BYPASS_MASK 0x10000 +#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_MASK 0x20000 +#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK 0x40000 +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_ENET_RSVD1_MASK 0x7FF80000 +#define CCM_ANALOG_PLL_ENET_RSVD1_SHIFT 19 +#define CCM_ANALOG_PLL_ENET_LOCK_MASK 0x80000000 +#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT 31 + +/* PLL_AUDIO Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))< + +#endif /* __ASM_ARCH_MX7_GPIO_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx7/imx-rdc.h b/roms/u-boot/arch/arm/include/asm/arch-mx7/imx-rdc.h new file mode 100644 index 000000000..3512ddb66 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx7/imx-rdc.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#ifndef __IMX_RDC_H__ +#define __IMX_RDC_H__ + +#if defined(CONFIG_MX7D) +#include "mx7d_rdc.h" +#else +#error "Please select cpu" +#endif /* CONFIG_MX7D */ + +#endif /* __IMX_RDC_H__*/ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx7/imx-regs.h b/roms/u-boot/arch/arm/include/asm/arch-mx7/imx-regs.h new file mode 100644 index 000000000..5cab12f30 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -0,0 +1,1192 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __ASM_ARCH_MX7_IMX_REGS_H__ +#define __ASM_ARCH_MX7_IMX_REGS_H__ + +#define ARCH_MXC + +#define ROM_SW_INFO_ADDR 0x000001E8 +#define ROMCP_ARB_BASE_ADDR 0x00000000 +#define ROMCP_ARB_END_ADDR 0x00017FFF +#define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR +#define CAAM_ARB_BASE_ADDR 0x00100000 +#define CAAM_ARB_END_ADDR 0x00107FFF +#define GIC400_ARB_BASE_ADDR 0x31000000 +#define GIC400_ARB_END_ADDR 0x31007FFF +#define APBH_DMA_ARB_BASE_ADDR 0x33000000 +#define APBH_DMA_ARB_END_ADDR 0x33007FFF +#define M4_BOOTROM_BASE_ADDR 0x00180000 + +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) + +/* GPV - PL301 configuration ports */ +#define GPV0_BASE_ADDR 0x32000000 +#define GPV1_BASE_ADDR 0x32100000 +#define GPV2_BASE_ADDR 0x32200000 +#define GPV3_BASE_ADDR 0x32300000 +#define GPV4_BASE_ADDR 0x32400000 +#define GPV5_BASE_ADDR 0x32500000 +#define GPV6_BASE_ADDR 0x32600000 +#define GPV7_BASE_ADDR 0x32700000 + +#define OCRAM_ARB_BASE_ADDR 0x00900000 +#define OCRAM_ARB_END_ADDR 0x0091FFFF +#define OCRAM_EPDC_BASE_ADDR 0x00920000 +#define OCRAM_EPDC_END_ADDR 0x0093FFFF +#define OCRAM_PXP_BASE_ADDR 0x00940000 +#define OCRAM_PXP_END_ADDR 0x00947FFF +#define IRAM_BASE_ADDR OCRAM_ARB_BASE_ADDR +#define IRAM_SIZE 0x00020000 + +#define AIPS1_ARB_BASE_ADDR 0x30000000 +#define AIPS1_ARB_END_ADDR 0x303FFFFF +#define AIPS2_ARB_BASE_ADDR 0x30400000 +#define AIPS2_ARB_END_ADDR 0x307FFFFF +#define AIPS3_ARB_BASE_ADDR 0x30800000 +#define AIPS3_ARB_END_ADDR 0x30BFFFFF + +#define WEIM_ARB_BASE_ADDR 0x28000000 +#define WEIM_ARB_END_ADDR 0x2FFFFFFF + +#define QSPI0_ARB_BASE_ADDR 0x60000000 +#define QSPI0_ARB_END_ADDR 0x6FFFFFFF +#define PCIE_ARB_BASE_ADDR 0x40000000 +#define PCIE_ARB_END_ADDR 0x4FFFFFFF +#define PCIE_REG_BASE_ADDR 0x33800000 +#define PCIE_REG_END_ADDR 0x33803FFF + +#define MMDC0_ARB_BASE_ADDR 0x80000000 +#define MMDC0_ARB_END_ADDR 0xBFFFFFFF +#define MMDC1_ARB_BASE_ADDR 0xC0000000 +#define MMDC1_ARB_END_ADDR 0xFFFFFFFF + +/* Cortex-A9 MPCore private memory region */ +#define ARM_PERIPHBASE 0x31000000 +#define SCU_BASE_ADDR ARM_PERIPHBASE +#define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200) +#define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600) + + +/* Defines for Blocks connected via AIPS (SkyBlue) */ +#define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR +#define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR +#define AIPS_TZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR + +/* DAP base-address */ +#define ARM_IPS_BASE_ADDR AIPS1_ARB_BASE_ADDR + +/* AIPS_TZ#1- On Platform */ +#define AIPS1_ON_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x1F0000) +/* AIPS_TZ#1- Off Platform */ +#define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x200000) + +#define GPIO1_BASE_ADDR AIPS1_OFF_BASE_ADDR +#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x10000) +#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x20000) +#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x30000) +#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x40000) +#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x50000) +#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x60000) +#define IOMUXC_LPSR_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x70000) +#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x80000) +#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x90000) +#define WDOG3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xA0000) +#define WDOG4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xB0000) +#define IOMUXC_LPSR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xC0000) +#define GPT_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xD0000) +#define GPT1_BASE_ADDR GPT_IPS_BASE_ADDR +#define GPT2_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xE0000) +#define GPT3_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xF0000) +#define GPT4_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x100000) +#define ROMCP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x110000) +#define KPP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x120000) +#define IOMUXC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x130000) +#define IOMUXC_BASE_ADDR IOMUXC_IPS_BASE_ADDR +#define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x140000) +#define OCOTP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x150000) +#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x160000) +#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x170000) +#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x180000) +#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x190000) +#define GPC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1A0000) +#define SEMA41_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1B0000) +#define SEMA42_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1C0000) +#define RDC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1D0000) +#define CSU_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1E0000) + +/* AIPS_TZ#2- On Platform */ +#define AIPS2_ON_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x1F0000) +/* AIPS_TZ#2- Off Platform */ +#define AIPS2_OFF_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x200000) +#define ADC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x10000) +#define ADC2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x20000) +#define ECSPI4_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x30000) +#define FTM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x40000) +#define FTM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x50000) +#define PWM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x60000) +#define PWM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x70000) +#define PWM3_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x80000) +#define PWM4_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x90000) +#define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xA0000) +#define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xB0000) +#define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC0000) +#define PCIE_PHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xD0000) +#define EPDC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xF0000) +#define EPDC_BASE_ADDR EPDC_IPS_BASE_ADDR +#define EPXP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x100000) +#define CSI1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x110000) +#define ELCDIF1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x130000) +#define MIPI_CSI2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x150000) +#define MIPI_DSI_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x160000) +#define IP2APB_TZASC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x180000) +#define DDRPHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x190000) +#define DDRC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1A0000) +#define IP2APB_PERFMON1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1C0000) +#define IP2APB_PERFMON2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1D0000) +#define IP2APB_AXIMON_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1E0000) +#define QOSC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1F0000) + +/* AIPS_TZ#3 - Global enable (0) */ +#define ECSPI1_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x20000) +#define ECSPI2_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x30000) +#define ECSPI3_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x40000) +#define UART1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x60000) +#define UART3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x80000) +#define UART2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x90000) +#define SAI1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xA0000) +#define SAI2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xB0000) +#define SAI3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xC0000) +#define SPBA_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xF0000) +#define CAAM_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x100000) + +/* AIPS_TZ#3- On Platform */ +#define AIPS3_ON_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x1F0000) +/* AIPS_TZ#3- Off Platform */ +#define AIPS3_OFF_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x200000) +#define CAN1_IPS_BASE_ADDR AIPS3_OFF_BASE_ADDR +#define CAN2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x10000) +#define I2C1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x20000) +#define I2C2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x30000) +#define I2C3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x40000) +#define I2C4_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x50000) +#define UART4_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x60000) +#define UART5_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x70000) +#define UART6_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x80000) +#define UART7_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x90000) +#define MUCPU_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xA0000) +#define MUDSP_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xB0000) +#define HS_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xC0000) +#define USBOH2_PL301_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xD0000) +#define USBOTG1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x110000) +#define USBOTG2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x120000) +#define USBHSIC_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x130000) +#define USDHC1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x140000) +#define USDHC2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x150000) +#define USDHC3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x160000) +#define EMVSIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000) +#define EMVSIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000) +#define SIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000) +#define SIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000) +#define QSPI1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1B0000) +#define WEIM_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1C0000) +#define SDMA_PORT_IPS_HOST_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1D0000) +#define ENET_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1E0000) +#define ENET2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1F0000) + +#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR +#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR +#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR + +#define SDMA_IPS_HOST_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR +#define SDMA_IPS_HOST_IPS_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR + +#define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR +#define DEBUG_MONITOR_BASE_ADDR IP2APB_AXIMON_IPS_BASE_ADDR + +#define USB_BASE_ADDR USBOTG1_IPS_BASE_ADDR +#define SEMAPHORE1_BASE_ADDR SEMA41_IPS_BASE_ADDR +#define SEMAPHORE2_BASE_ADDR SEMA42_IPS_BASE_ADDR +#define RDC_BASE_ADDR RDC_IPS_BASE_ADDR + +#define FEC_QUIRK_ENET_MAC +#define SNVS_LPGPR 0x68 +#define CONFIG_SYS_FSL_SEC_OFFSET 0 +#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ + CONFIG_SYS_FSL_JR0_OFFSET) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include +#include +#include + +extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); + +/* System Reset Controller (SRC) */ +struct src { + u32 scr; + u32 a7rcr0; + u32 a7rcr1; + u32 m4rcr; + u32 reserved1; + u32 ercr; + u32 reserved2; + u32 hsicphy_rcr; + u32 usbophy1_rcr; + u32 usbophy2_rcr; + u32 mipiphy_rcr; + u32 pciephy_rcr; + u32 reserved3[10]; + u32 sbmr1; + u32 srsr; + u32 reserved4[2]; + u32 sisr; + u32 simr; + u32 sbmr2; + u32 gpr1; + u32 gpr2; + u32 gpr3; + u32 gpr4; + u32 gpr5; + u32 gpr6; + u32 gpr7; + u32 gpr8; + u32 gpr9; + u32 gpr10; + u32 reserved5[985]; + u32 ddrc_rcr; +}; + +#define src_base ((struct src *)SRC_BASE_ADDR) + +#define SRC_M4_REG_OFFSET 0xC +#define SRC_M4C_NON_SCLR_RST_OFFSET 0 +#define SRC_M4C_NON_SCLR_RST_MASK BIT(0) +#define SRC_M4_ENABLE_OFFSET 3 +#define SRC_M4_ENABLE_MASK BIT(3) + +#define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET 1 +#define SRC_DDRC_RCR_DDRC_CORE_RST_MASK (1 << 1) +#define SRC_DDRC_RCR_DDRC_PRST_MASK (1 << 0) + +/* GPR0 Bit Fields */ +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6 +#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (3 << 7) +#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_SHIFT 7 +/* GPR1 Bit Fields */ +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0 +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK 0x6u +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT 1 +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0(x) (((uint32_t)(((uint32_t)(x))< + */ + +#ifndef __ASM_ARCH_MX7_DDR_H__ +#define __ASM_ARCH_MX7_DDR_H__ + +#ifndef __ASSEMBLY__ +#include +#endif + +/* DDRC Registers (DDRC_IPS_BASE_ADDR) */ +struct ddrc { + u32 mstr; /* 0x0000 */ + u32 reserved1[0x18]; + u32 rfshtmg; /* 0x0064 */ + u32 reserved2[0x1a]; + u32 init0; /* 0x00d0 */ + u32 init1; /* 0x00d4 */ + u32 reserved3; + u32 init3; /* 0x00dc */ + u32 init4; /* 0x00e0 */ + u32 init5; /* 0x00e4 */ + u32 reserved4[0x03]; + u32 rankctl; /* 0x00f4 */ + u32 reserved5[0x02]; + u32 dramtmg0; /* 0x0100 */ + u32 dramtmg1; /* 0x0104 */ + u32 dramtmg2; /* 0x0108 */ + u32 dramtmg3; /* 0x010c */ + u32 dramtmg4; /* 0x0110 */ + u32 dramtmg5; /* 0x0114 */ + u32 reserved6[0x02]; + u32 dramtmg8; /* 0x0120 */ + u32 reserved7[0x17]; + u32 zqctl0; /* 0x0180 */ + u32 zqctl1; /* 0x0184 */ + u32 zqctl2; /* 0x0188 */ + u32 zqstat; /* 0x018c */ + u32 dfitmg0; /* 0x0190 */ + u32 dfitmg1; /* 0x0194 */ + u32 reserved9[0x02]; + u32 dfiupd0; /* 0x01a0 */ + u32 dfiupd1; /* 0x01a4 */ + u32 dfiupd2; /* 0x01a8 */ + u32 reserved10[0x15]; + u32 addrmap0; /* 0x0200 */ + u32 addrmap1; /* 0x0204 */ + u32 addrmap2; /* 0x0208 */ + u32 addrmap3; /* 0x020c */ + u32 addrmap4; /* 0x0210 */ + u32 addrmap5; /* 0x0214 */ + u32 addrmap6; /* 0x0218 */ + u32 reserved12[0x09]; + u32 odtcfg; /* 0x0240 */ + u32 odtmap; /* 0x0244 */ +}; + +/* DDRC_MSTR fields */ +#define MSTR_DATA_BUS_WIDTH_MASK 0x3 << 12 +#define MSTR_DATA_BUS_WIDTH_SHIFT 12 +#define MSTR_DATA_ACTIVE_RANKS_MASK 0xf << 24 +#define MSTR_DATA_ACTIVE_RANKS_SHIFT 24 +/* DDRC_ADDRMAP1 fields */ +#define ADDRMAP1_BANK_B0_MASK 0x1f << 0 +#define ADDRMAP1_BANK_B0_SHIFT 0 +#define ADDRMAP1_BANK_B1_MASK 0x1f << 8 +#define ADDRMAP1_BANK_B1_SHIFT 8 +#define ADDRMAP1_BANK_B2_MASK 0x1f << 16 +#define ADDRMAP1_BANK_B2_SHIFT 16 +/* DDRC_ADDRMAP2 fields */ +#define ADDRMAP2_COL_B2_MASK 0xF << 0 +#define ADDRMAP2_COL_B2_SHIFT 0 +#define ADDRMAP2_COL_B3_MASK 0xF << 8 +#define ADDRMAP2_COL_B3_SHIFT 8 +#define ADDRMAP2_COL_B4_MASK 0xF << 16 +#define ADDRMAP2_COL_B4_SHIFT 16 +#define ADDRMAP2_COL_B5_MASK 0xF << 24 +#define ADDRMAP2_COL_B5_SHIFT 24 +/* DDRC_ADDRMAP3 fields */ +#define ADDRMAP3_COL_B6_MASK 0xF << 0 +#define ADDRMAP3_COL_B6_SHIFT 0 +#define ADDRMAP3_COL_B7_MASK 0xF << 8 +#define ADDRMAP3_COL_B7_SHIFT 8 +#define ADDRMAP3_COL_B8_MASK 0xF << 16 +#define ADDRMAP3_COL_B8_SHIFT 16 +#define ADDRMAP3_COL_B9_MASK 0xF << 24 +#define ADDRMAP3_COL_B9_SHIFT 24 +/* DDRC_ADDRMAP4 fields */ +#define ADDRMAP4_COL_B10_MASK 0xF << 0 +#define ADDRMAP4_COL_B10_SHIFT 0 +#define ADDRMAP4_COL_B11_MASK 0xF << 8 +#define ADDRMAP4_COL_B11_SHIFT 8 +/* DDRC_ADDRMAP5 fields */ +#define ADDRMAP5_ROW_B0_MASK 0xF << 0 +#define ADDRMAP5_ROW_B0_SHIFT 0 +#define ADDRMAP5_ROW_B1_MASK 0xF << 8 +#define ADDRMAP5_ROW_B1_SHIFT 8 +#define ADDRMAP5_ROW_B2_10_MASK 0xF << 16 +#define ADDRMAP5_ROW_B2_10_SHIFT 16 +#define ADDRMAP5_ROW_B11_MASK 0xF << 24 +#define ADDRMAP5_ROW_B11_SHIFT 24 +/* DDRC_ADDRMAP6 fields */ +#define ADDRMAP6_ROW_B12_MASK 0xF << 0 +#define ADDRMAP6_ROW_B12_SHIFT 0 +#define ADDRMAP6_ROW_B13_MASK 0xF << 8 +#define ADDRMAP6_ROW_B13_SHIFT 8 +#define ADDRMAP6_ROW_B14_MASK 0xF << 16 +#define ADDRMAP6_ROW_B14_SHIFT 16 +#define ADDRMAP6_ROW_B15_MASK 0xF << 24 +#define ADDRMAP6_ROW_B15_SHIFT 24 + +/* DDRC_MP Registers */ +#define DDRC_MP_BASE_ADDR (DDRC_IPS_BASE_ADDR + 0x03fc) +struct ddrc_mp { + u32 reserved1[0x25]; + u32 pctrl_0; /* 0x0094 */ +}; + +/* DDR_PHY registers */ +struct ddr_phy { + u32 phy_con0; /* 0x0000 */ + u32 phy_con1; /* 0x0004 */ + u32 reserved1[0x02]; + u32 phy_con4; /* 0x0010 */ + u32 reserved2; + u32 offset_lp_con0; /* 0x0018 */ + u32 reserved3; + u32 offset_rd_con0; /* 0x0020 */ + u32 reserved4[0x03]; + u32 offset_wr_con0; /* 0x0030 */ + u32 reserved5[0x07]; + u32 cmd_sdll_con0; /* 0x0050 */ + u32 reserved6[0x06]; + u32 cmd_lvl_con0; /* 0x006c */ + u32 reserved7[0x02]; + u32 cmd_lvl_con3; /* 0x0078 */ + u32 cmd_deskew_con0; /* 0x007c */ + u32 cmd_deskew_con1; /* 0x0080 */ + u32 cmd_deskew_con2; /* 0x0084 */ + u32 cmd_deskew_con3; /* 0x0088 */ + u32 reserved8[0x02]; + u32 cmd_deskew_con4; /* 0x0094 */ + u32 reserved9; + u32 drvds_con0; /* 0x009c */ + u32 reserved10[0x04]; + u32 mdll_con0; /* 0x00b0 */ + u32 reserved11[0x03]; + u32 zq_con0; /* 0x00c0 */ +}; + +#define DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK BIT(24) + +#define MX7_CAL_VAL_MAX 5 +/* Calibration parameters */ +struct mx7_calibration { + int num_val; /* Number of calibration values */ + u32 values[MX7_CAL_VAL_MAX]; /* calibration values */ +}; + +void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val, + struct ddr_phy *ddr_phy_regs_val, + struct mx7_calibration *calib_param); + +#endif /*__ASM_ARCH_MX7_DDR_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx7/mx7-pins.h b/roms/u-boot/arch/arm/include/asm/arch-mx7/mx7-pins.h new file mode 100644 index 000000000..bc99a8646 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx7/mx7-pins.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ +#ifndef __ASM_ARCH_MX7_PINS_H__ +#define __ASM_ARCH_MX7_PINS_H__ + +#include + +#if defined(CONFIG_MX7D) +#include "mx7d_pins.h" +#elif defined(CONFIG_MX7S) +#include "mx7s_pins.h" +#else +#error "Please select cpu" +#endif /* CONFIG_MX7D */ + +#endif /*__ASM_ARCH_MX7_PINS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx7/mx7_plugin.S b/roms/u-boot/arch/arm/include/asm/arch-mx7/mx7_plugin.S new file mode 100644 index 000000000..c7a84e8ca --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx7/mx7_plugin.S @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#include + +#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180 +#define ROM_VERSION_OFFSET 0x80 +#define ROM_API_HWCNFG_SETUP_OFFSET 0x08 + +plugin_start: + + push {r0-r4, lr} + + imx7_ddr_setting + imx7_clock_gating + imx7_qos_setting + +/* + * Check if we are in USB serial download mode and immediately return to ROM + * Need to check USB CTRL clock firstly, then check the USBx_nASYNCLISTADDR + */ + ldr r0, =0x30384680 + ldr r1, [r0] + cmp r1, #0 + beq normal_boot + + ldr r0, =0x30B10158 + ldr r1, [r0] + cmp r1, #0 + beq normal_boot + + pop {r0-r4, lr} + bx lr + +normal_boot: + +/* + * The following is to fill in those arguments for this ROM function + * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data) + * This function is used to copy data from the storage media into DDR. + * start - Initial (possibly partial) image load address on entry. + * Final image load address on exit. + * bytes - Initial (possibly partial) image size on entry. + * Final image size on exit. + * boot_data - Initial @ref ivt Boot Data load address. + */ + adr r0, boot_data2 + adr r1, image_len2 + adr r2, boot_data2 + +/* + * check the _pu_irom_api_table for the address + */ +before_calling_rom___pu_irom_hwcnfg_setup: + ldr r3, =ROM_VERSION_OFFSET + ldr r4, [r3] + ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY + ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET] + blx r4 +after_calling_rom___pu_irom_hwcnfg_setup: + + +/* To return to ROM from plugin, we need to fill in these argument. + * Here is what need to do: + * Need to construct the paramters for this function before return to ROM: + * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset) + */ + pop {r0-r4, lr} + push {r5} + ldr r5, boot_data2 + str r5, [r0] + ldr r5, image_len2 + str r5, [r1] + ldr r5, second_ivt_offset + str r5, [r2] + mov r0, #1 + pop {r5} + + /* return back to ROM code */ + bx lr + +/* make the following data right in the end of the output*/ +.ltorg + +#define FLASH_OFFSET 0x400 + +/* + * second_ivt_offset is the offset from the "second_ivt_header" to + * "image_copy_start", which involves FLASH_OFFSET, plus the first + * ivt_header, the plugin code size itself recorded by "ivt2_header" + */ + +second_ivt_offset: .long (ivt2_header + 0x2C + FLASH_OFFSET) + +/* + * The following is the second IVT header plus the second boot data + */ +ivt2_header: .long 0x0 +app2_code_jump_v: .long 0x0 +reserv3: .long 0x0 +dcd2_ptr: .long 0x0 +boot_data2_ptr: .long 0x0 +self_ptr2: .long 0x0 +app_code_csf2: .long 0x0 +reserv4: .long 0x0 +boot_data2: .long 0x0 +image_len2: .long 0x0 +plugin2: .long 0x0 diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx7/mx7d_pins.h b/roms/u-boot/arch/arm/include/asm/arch-mx7/mx7d_pins.h new file mode 100644 index 000000000..d54680f17 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx7/mx7d_pins.h @@ -0,0 +1,1307 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __ASM_ARCH_IMX7D_PINS_H__ +#define __ASM_ARCH_IMX7D_PINS_H__ + +#include + +enum { + MX7D_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO00__PWM4_OUT = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO01__SAI1_MCLK = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO02__GPIO1_IO2 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO02__PWM2_OUT = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 2, 0x0564, 3, 0), + MX7D_PAD_GPIO1_IO02__SAI2_MCLK = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO02__CCM_CLKO1 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO02__USB_OTG1_ID = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 7, 0x0734, 3, 0), + + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO03__PWM3_OUT = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 2, 0x0570, 3, 0), + MX7D_PAD_GPIO1_IO03__SAI3_MCLK = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO03__CCM_CLKO2 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO03__USB_OTG2_ID = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 7, 0x0730, 3, 0), + + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO04__USB_OTG1_OC = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 1, 0x072C, 1, 0), + MX7D_PAD_GPIO1_IO04__FLEXTIMER_CH4 = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 2, 0x0594, 1, 0), + MX7D_PAD_GPIO1_IO04__UART5_CTS_B = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 3, 0x0710, 4, 0), + MX7D_PAD_GPIO1_IO04__I2C1_SCL = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05D4, 2, 0), + + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 2, 0x0598, 1, 0), + MX7D_PAD_GPIO1_IO05__UART5_RTS_B = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 3, 0x0710, 5, 0), + MX7D_PAD_GPIO1_IO05__I2C1_SDA = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05D8, 2, 0), + + MX7D_PAD_GPIO1_IO06__GPIO1_IO6 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO06__USB_OTG2_OC = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 1, 0x0728, 1, 0), + MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 2, 0x059C, 1, 0), + MX7D_PAD_GPIO1_IO06__UART5_RX_DATA = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 3, 0x0714, 4, 0), + MX7D_PAD_GPIO1_IO06__I2C2_SCL = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05DC, 2, 0), + MX7D_PAD_GPIO1_IO06__CCM_WAIT = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO06__KPP_ROW4 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 6, 0x0624, 1, 0), + + MX7D_PAD_GPIO1_IO07__GPIO1_IO7 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 2, 0x05A0, 1, 0), + MX7D_PAD_GPIO1_IO07__UART5_TX_DATA = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 3, 0x0714, 5, 0), + MX7D_PAD_GPIO1_IO07__I2C2_SDA = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05E0, 2, 0), + MX7D_PAD_GPIO1_IO07__CCM_STOP = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO07__KPP_COL4 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 6, 0x0604, 1, 0), +}; + +enum { + MX7D_PAD_GPIO1_IO08__GPIO1_IO8 = IOMUX_PAD(0x026C, 0x0014, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO08__SD1_VSELECT = IOMUX_PAD(0x026C, 0x0014, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B = IOMUX_PAD(0x026C, 0x0014, 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO08__UART3_DCE_RX = IOMUX_PAD(0x026C, 0x0014, 3, 0x0704, 0, 0), + MX7D_PAD_GPIO1_IO08__UART3_DTE_TX = IOMUX_PAD(0x026C, 0x0014, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO08__I2C3_SCL = IOMUX_PAD(0x026C, 0x0014, IOMUX_CONFIG_SION | 4, 0x05E4, 0, 0), + MX7D_PAD_GPIO1_IO08__KPP_COL5 = IOMUX_PAD(0x026C, 0x0014, 6, 0x0608, 0, 0), + MX7D_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x026C, 0x0014, 7, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 = IOMUX_PAD(0x0270, 0x0018, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO09__SD1_LCTL = IOMUX_PAD(0x0270, 0x0018, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x0270, 0x0018, 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO09__UART3_DCE_TX = IOMUX_PAD(0x0270, 0x0018, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO09__UART3_DTE_RX = IOMUX_PAD(0x0270, 0x0018, 3, 0x0704, 1, 0), + MX7D_PAD_GPIO1_IO09__I2C3_SDA = IOMUX_PAD(0x0270, 0x0018, IOMUX_CONFIG_SION | 4, 0x05E8, 0, 0), + MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY = IOMUX_PAD(0x0270, 0x0018, 5, 0x04F4, 0, 0), + MX7D_PAD_GPIO1_IO09__KPP_ROW5 = IOMUX_PAD(0x0270, 0x0018, 6, 0x0628, 0, 0), + MX7D_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x0270, 0x0018, 7, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x0274, 0x001C, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO10__SD2_LCTL = IOMUX_PAD(0x0274, 0x001C, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO10__ENET1_MDIO = IOMUX_PAD(0x0274, 0x001C, 2, 0x0568, 0, 0), + MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS = IOMUX_PAD(0x0274, 0x001C, 3, 0x0700, 0, 0), + MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS = IOMUX_PAD(0x0274, 0x001C, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO10__I2C4_SCL = IOMUX_PAD(0x0274, 0x001C, IOMUX_CONFIG_SION | 4, 0x05EC, 0, 0), + MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA = IOMUX_PAD(0x0274, 0x001C, 5, 0x05A4, 0, 0), + MX7D_PAD_GPIO1_IO10__KPP_COL6 = IOMUX_PAD(0x0274, 0x001C, 6, 0x060C, 0, 0), + MX7D_PAD_GPIO1_IO10__PWM3_OUT = IOMUX_PAD(0x0274, 0x001C, 7, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x0278, 0x0020, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO11__SD3_LCTL = IOMUX_PAD(0x0278, 0x0020, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO11__ENET1_MDC = IOMUX_PAD(0x0278, 0x0020, 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS = IOMUX_PAD(0x0278, 0x0020, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS = IOMUX_PAD(0x0278, 0x0020, 3, 0x0700, 1, 0), + MX7D_PAD_GPIO1_IO11__I2C4_SDA = IOMUX_PAD(0x0278, 0x0020, IOMUX_CONFIG_SION | 4, 0x05F0, 0, 0), + MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB = IOMUX_PAD(0x0278, 0x0020, 5, 0x05A8, 0, 0), + MX7D_PAD_GPIO1_IO11__KPP_ROW6 = IOMUX_PAD(0x0278, 0x0020, 6, 0x062C, 0, 0), + MX7D_PAD_GPIO1_IO11__PWM4_OUT = IOMUX_PAD(0x0278, 0x0020, 7, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x027C, 0x0024, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO12__SD2_VSELECT = IOMUX_PAD(0x027C, 0x0024, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x027C, 0x0024, 2, 0x0564, 0, 0), + MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX = IOMUX_PAD(0x027C, 0x0024, 3, 0x04DC, 0, 0), + MX7D_PAD_GPIO1_IO12__CM4_NMI = IOMUX_PAD(0x027C, 0x0024, 4, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 = IOMUX_PAD(0x027C, 0x0024, 5, 0x04E4, 0, 0), + MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 = IOMUX_PAD(0x027C, 0x0024, 6, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO12__USB_OTG1_ID = IOMUX_PAD(0x027C, 0x0024, 7, 0x0734, 0, 0), + + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x0280, 0x0028, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO13__SD3_VSELECT = IOMUX_PAD(0x0280, 0x0028, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x0280, 0x0028, 2, 0x0570, 0, 0), + MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX = IOMUX_PAD(0x0280, 0x0028, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY = IOMUX_PAD(0x0280, 0x0028, 4, 0x04F4, 1, 0), + MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 = IOMUX_PAD(0x0280, 0x0028, 5, 0x04E8, 0, 0), + MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL = IOMUX_PAD(0x0280, 0x0028, 6, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO13__USB_OTG2_ID = IOMUX_PAD(0x0280, 0x0028, 7, 0x0730, 0, 0), + + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x0284, 0x002C, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO14__SD3_CD_B = IOMUX_PAD(0x0284, 0x002C, 1, 0x0738, 0, 0), + MX7D_PAD_GPIO1_IO14__ENET2_MDIO = IOMUX_PAD(0x0284, 0x002C, 2, 0x0574, 0, 0), + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX = IOMUX_PAD(0x0284, 0x002C, 3, 0x04E0, 0, 0), + MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B = IOMUX_PAD(0x0284, 0x002C, 4, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 = IOMUX_PAD(0x0284, 0x002C, 5, 0x04EC, 0, 0), + MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 = IOMUX_PAD(0x0284, 0x002C, 6, 0x06D8, 0, 0), + + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x0288, 0x0030, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO15__SD3_WP = IOMUX_PAD(0x0288, 0x0030, 1, 0x073C, 0, 0), + MX7D_PAD_GPIO1_IO15__ENET2_MDC = IOMUX_PAD(0x0288, 0x0030, 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX = IOMUX_PAD(0x0288, 0x0030, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B = IOMUX_PAD(0x0288, 0x0030, 4, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 = IOMUX_PAD(0x0288, 0x0030, 5, 0x04F0, 0, 0), + MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0288, 0x0030, 6, 0x06DC, 0, 0), + + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD = IOMUX_PAD(0x02A4, 0x0034, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__KPP_ROW3 = IOMUX_PAD(0x02A4, 0x0034, 3, 0x0620, 0, 0), + MX7D_PAD_EPDC_DATA00__EIM_AD0 = IOMUX_PAD(0x02A4, 0x0034, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 = IOMUX_PAD(0x02A4, 0x0034, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__LCD_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 6, 0x0638, 0, 0), + MX7D_PAD_EPDC_DATA00__LCD_CLK = IOMUX_PAD(0x02A4, 0x0034, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK = IOMUX_PAD(0x02A8, 0x0038, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__KPP_COL3 = IOMUX_PAD(0x02A8, 0x0038, 3, 0x0600, 0, 0), + MX7D_PAD_EPDC_DATA01__EIM_AD1 = IOMUX_PAD(0x02A8, 0x0038, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 = IOMUX_PAD(0x02A8, 0x0038, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__LCD_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 6, 0x063C, 0, 0), + MX7D_PAD_EPDC_DATA01__LCD_ENABLE = IOMUX_PAD(0x02A8, 0x0038, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B = IOMUX_PAD(0x02AC, 0x003C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__KPP_ROW2 = IOMUX_PAD(0x02AC, 0x003C, 3, 0x061C, 0, 0), + MX7D_PAD_EPDC_DATA02__EIM_AD2 = IOMUX_PAD(0x02AC, 0x003C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 = IOMUX_PAD(0x02AC, 0x003C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__LCD_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 6, 0x0640, 0, 0), + MX7D_PAD_EPDC_DATA02__LCD_VSYNC = IOMUX_PAD(0x02AC, 0x003C, 7, 0x0698, 0, 0), + + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN = IOMUX_PAD(0x02B0, 0x0040, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__KPP_COL2 = IOMUX_PAD(0x02B0, 0x0040, 3, 0x05FC, 0, 0), + MX7D_PAD_EPDC_DATA03__EIM_AD3 = IOMUX_PAD(0x02B0, 0x0040, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 = IOMUX_PAD(0x02B0, 0x0040, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__LCD_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 6, 0x0644, 0, 0), + MX7D_PAD_EPDC_DATA03__LCD_HSYNC = IOMUX_PAD(0x02B0, 0x0040, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 = IOMUX_PAD(0x02B4, 0x0044, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD = IOMUX_PAD(0x02B4, 0x0044, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS = IOMUX_PAD(0x02B4, 0x0044, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__KPP_ROW1 = IOMUX_PAD(0x02B4, 0x0044, 3, 0x0618, 0, 0), + MX7D_PAD_EPDC_DATA04__EIM_AD4 = IOMUX_PAD(0x02B4, 0x0044, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 = IOMUX_PAD(0x02B4, 0x0044, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__LCD_DATA4 = IOMUX_PAD(0x02B4, 0x0044, 6, 0x0648, 0, 0), + MX7D_PAD_EPDC_DATA04__JTAG_FAIL = IOMUX_PAD(0x02B4, 0x0044, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 = IOMUX_PAD(0x02B8, 0x0048, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD = IOMUX_PAD(0x02B8, 0x0048, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK = IOMUX_PAD(0x02B8, 0x0048, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__KPP_COL1 = IOMUX_PAD(0x02B8, 0x0048, 3, 0x05F8, 0, 0), + MX7D_PAD_EPDC_DATA05__EIM_AD5 = IOMUX_PAD(0x02B8, 0x0048, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 = IOMUX_PAD(0x02B8, 0x0048, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__LCD_DATA5 = IOMUX_PAD(0x02B8, 0x0048, 6, 0x064C, 0, 0), + MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE = IOMUX_PAD(0x02B8, 0x0048, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 = IOMUX_PAD(0x02BC, 0x004C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK = IOMUX_PAD(0x02BC, 0x004C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B = IOMUX_PAD(0x02BC, 0x004C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__KPP_ROW0 = IOMUX_PAD(0x02BC, 0x004C, 3, 0x0614, 0, 0), + MX7D_PAD_EPDC_DATA06__EIM_AD6 = IOMUX_PAD(0x02BC, 0x004C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__GPIO2_IO6 = IOMUX_PAD(0x02BC, 0x004C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__LCD_DATA6 = IOMUX_PAD(0x02BC, 0x004C, 6, 0x0650, 0, 0), + MX7D_PAD_EPDC_DATA06__JTAG_DE_B = IOMUX_PAD(0x02BC, 0x004C, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 = IOMUX_PAD(0x02C0, 0x0050, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B = IOMUX_PAD(0x02C0, 0x0050, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B = IOMUX_PAD(0x02C0, 0x0050, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__KPP_COL0 = IOMUX_PAD(0x02C0, 0x0050, 3, 0x05F4, 0, 0), + MX7D_PAD_EPDC_DATA07__EIM_AD7 = IOMUX_PAD(0x02C0, 0x0050, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 = IOMUX_PAD(0x02C0, 0x0050, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__LCD_DATA7 = IOMUX_PAD(0x02C0, 0x0050, 6, 0x0654, 0, 0), + MX7D_PAD_EPDC_DATA07__JTAG_DONE = IOMUX_PAD(0x02C0, 0x0050, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA08__EPDC_DATA8 = IOMUX_PAD(0x02C4, 0x0054, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD = IOMUX_PAD(0x02C4, 0x0054, 1, 0x06E4, 0, 0), + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 = IOMUX_PAD(0x02C4, 0x0054, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__UART6_DCE_RX = IOMUX_PAD(0x02C4, 0x0054, 3, 0x071C, 0, 0), + MX7D_PAD_EPDC_DATA08__UART6_DTE_TX = IOMUX_PAD(0x02C4, 0x0054, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__EIM_OE = IOMUX_PAD(0x02C4, 0x0054, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__GPIO2_IO8 = IOMUX_PAD(0x02C4, 0x0054, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__LCD_DATA8 = IOMUX_PAD(0x02C4, 0x0054, 6, 0x0658, 0, 0), + MX7D_PAD_EPDC_DATA08__LCD_BUSY = IOMUX_PAD(0x02C4, 0x0054, 7, 0x0634, 0, 0), + MX7D_PAD_EPDC_DATA08__EPDC_SDCLK = IOMUX_PAD(0x02C4, 0x0054, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA09__EPDC_DATA9 = IOMUX_PAD(0x02C8, 0x0058, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK = IOMUX_PAD(0x02C8, 0x0058, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 = IOMUX_PAD(0x02C8, 0x0058, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__UART6_DCE_TX = IOMUX_PAD(0x02C8, 0x0058, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__UART6_DTE_RX = IOMUX_PAD(0x02C8, 0x0058, 3, 0x071C, 1, 0), + MX7D_PAD_EPDC_DATA09__EIM_RW = IOMUX_PAD(0x02C8, 0x0058, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__GPIO2_IO9 = IOMUX_PAD(0x02C8, 0x0058, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__LCD_DATA9 = IOMUX_PAD(0x02C8, 0x0058, 6, 0x065C, 0, 0), + MX7D_PAD_EPDC_DATA09__LCD_DATA0 = IOMUX_PAD(0x02C8, 0x0058, 7, 0x0638, 1, 0), + MX7D_PAD_EPDC_DATA09__EPDC_SDLE = IOMUX_PAD(0x02C8, 0x0058, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA10__EPDC_DATA10 = IOMUX_PAD(0x02CC, 0x005C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B = IOMUX_PAD(0x02CC, 0x005C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 = IOMUX_PAD(0x02CC, 0x005C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS = IOMUX_PAD(0x02CC, 0x005C, 3, 0x0718, 0, 0), + MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS = IOMUX_PAD(0x02CC, 0x005C, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__EIM_CS0_B = IOMUX_PAD(0x02CC, 0x005C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__GPIO2_IO10 = IOMUX_PAD(0x02CC, 0x005C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__LCD_DATA10 = IOMUX_PAD(0x02CC, 0x005C, 6, 0x0660, 0, 0), + MX7D_PAD_EPDC_DATA10__LCD_DATA9 = IOMUX_PAD(0x02CC, 0x005C, 7, 0x065C, 1, 0), + MX7D_PAD_EPDC_DATA10__EPDC_SDOE = IOMUX_PAD(0x02CC, 0x005C, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA11__EPDC_DATA11 = IOMUX_PAD(0x02D0, 0x0060, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN = IOMUX_PAD(0x02D0, 0x0060, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 = IOMUX_PAD(0x02D0, 0x0060, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS = IOMUX_PAD(0x02D0, 0x0060, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS = IOMUX_PAD(0x02D0, 0x0060, 3, 0x0718, 1, 0), + MX7D_PAD_EPDC_DATA11__EIM_BCLK = IOMUX_PAD(0x02D0, 0x0060, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__GPIO2_IO11 = IOMUX_PAD(0x02D0, 0x0060, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__LCD_DATA11 = IOMUX_PAD(0x02D0, 0x0060, 6, 0x0664, 0, 0), + MX7D_PAD_EPDC_DATA11__LCD_DATA1 = IOMUX_PAD(0x02D0, 0x0060, 7, 0x063C, 1, 0), + MX7D_PAD_EPDC_DATA11__EPDC_SDCE0 = IOMUX_PAD(0x02D0, 0x0060, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA12__EPDC_DATA12 = IOMUX_PAD(0x02D4, 0x0064, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD = IOMUX_PAD(0x02D4, 0x0064, 1, 0x06E0, 0, 0), + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS = IOMUX_PAD(0x02D4, 0x0064, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__UART7_DCE_RX = IOMUX_PAD(0x02D4, 0x0064, 3, 0x0724, 0, 0), + MX7D_PAD_EPDC_DATA12__UART7_DTE_TX = IOMUX_PAD(0x02D4, 0x0064, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__EIM_LBA_B = IOMUX_PAD(0x02D4, 0x0064, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__GPIO2_IO12 = IOMUX_PAD(0x02D4, 0x0064, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__LCD_DATA12 = IOMUX_PAD(0x02D4, 0x0064, 6, 0x0668, 0, 0), + MX7D_PAD_EPDC_DATA12__LCD_DATA21 = IOMUX_PAD(0x02D4, 0x0064, 7, 0x068C, 0, 0), + MX7D_PAD_EPDC_DATA12__EPDC_GDCLK = IOMUX_PAD(0x02D4, 0x0064, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA13__EPDC_DATA13 = IOMUX_PAD(0x02D8, 0x0068, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD = IOMUX_PAD(0x02D8, 0x0068, 1, 0x06EC, 0, 0), + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK = IOMUX_PAD(0x02D8, 0x0068, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__UART7_DCE_TX = IOMUX_PAD(0x02D8, 0x0068, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__UART7_DTE_RX = IOMUX_PAD(0x02D8, 0x0068, 3, 0x0724, 1, 0), + MX7D_PAD_EPDC_DATA13__EIM_WAIT = IOMUX_PAD(0x02D8, 0x0068, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 = IOMUX_PAD(0x02D8, 0x0068, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__LCD_DATA13 = IOMUX_PAD(0x02D8, 0x0068, 6, 0x066C, 0, 0), + MX7D_PAD_EPDC_DATA13__LCD_CS = IOMUX_PAD(0x02D8, 0x0068, 7, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__EPDC_GDOE = IOMUX_PAD(0x02D8, 0x0068, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA14__EPDC_DATA14 = IOMUX_PAD(0x02DC, 0x006C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK = IOMUX_PAD(0x02DC, 0x006C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B = IOMUX_PAD(0x02DC, 0x006C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS = IOMUX_PAD(0x02DC, 0x006C, 3, 0x0720, 0, 0), + MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS = IOMUX_PAD(0x02DC, 0x006C, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__EIM_EB_B0 = IOMUX_PAD(0x02DC, 0x006C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__GPIO2_IO14 = IOMUX_PAD(0x02DC, 0x006C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__LCD_DATA14 = IOMUX_PAD(0x02DC, 0x006C, 6, 0x0670, 0, 0), + MX7D_PAD_EPDC_DATA14__LCD_DATA22 = IOMUX_PAD(0x02DC, 0x006C, 7, 0x0690, 0, 0), + MX7D_PAD_EPDC_DATA14__EPDC_GDSP = IOMUX_PAD(0x02DC, 0x006C, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA15__EPDC_DATA15 = IOMUX_PAD(0x02E0, 0x0070, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B = IOMUX_PAD(0x02E0, 0x0070, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B = IOMUX_PAD(0x02E0, 0x0070, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS = IOMUX_PAD(0x02E0, 0x0070, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS = IOMUX_PAD(0x02E0, 0x0070, 3, 0x0720, 1, 0), + MX7D_PAD_EPDC_DATA15__EIM_CS1_B = IOMUX_PAD(0x02E0, 0x0070, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__GPIO2_IO15 = IOMUX_PAD(0x02E0, 0x0070, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__LCD_DATA15 = IOMUX_PAD(0x02E0, 0x0070, 6, 0x0674, 0, 0), + MX7D_PAD_EPDC_DATA15__LCD_WR_RWN = IOMUX_PAD(0x02E0, 0x0070, 7, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM = IOMUX_PAD(0x02E0, 0x0070, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK = IOMUX_PAD(0x02E4, 0x0074, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN = IOMUX_PAD(0x02E4, 0x0074, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 = IOMUX_PAD(0x02E4, 0x0074, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__KPP_ROW4 = IOMUX_PAD(0x02E4, 0x0074, 3, 0x0624, 0, 0), + MX7D_PAD_EPDC_SDCLK__EIM_AD10 = IOMUX_PAD(0x02E4, 0x0074, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 = IOMUX_PAD(0x02E4, 0x0074, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__LCD_CLK = IOMUX_PAD(0x02E4, 0x0074, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__LCD_DATA20 = IOMUX_PAD(0x02E4, 0x0074, 7, 0x0688, 0, 0), + + MX7D_PAD_EPDC_SDLE__EPDC_SDLE = IOMUX_PAD(0x02E8, 0x0078, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD = IOMUX_PAD(0x02E8, 0x0078, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 = IOMUX_PAD(0x02E8, 0x0078, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__KPP_COL4 = IOMUX_PAD(0x02E8, 0x0078, 3, 0x0604, 0, 0), + MX7D_PAD_EPDC_SDLE__EIM_AD11 = IOMUX_PAD(0x02E8, 0x0078, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__GPIO2_IO17 = IOMUX_PAD(0x02E8, 0x0078, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__LCD_DATA16 = IOMUX_PAD(0x02E8, 0x0078, 6, 0x0678, 0, 0), + MX7D_PAD_EPDC_SDLE__LCD_DATA8 = IOMUX_PAD(0x02E8, 0x0078, 7, 0x0658, 1, 0), + + MX7D_PAD_EPDC_SDOE__EPDC_SDOE = IOMUX_PAD(0x02EC, 0x007C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0 = IOMUX_PAD(0x02EC, 0x007C, 1, 0x0584, 0, 0), + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 = IOMUX_PAD(0x02EC, 0x007C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDOE__KPP_COL5 = IOMUX_PAD(0x02EC, 0x007C, 3, 0x0608, 1, 0), + MX7D_PAD_EPDC_SDOE__EIM_AD12 = IOMUX_PAD(0x02EC, 0x007C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDOE__GPIO2_IO18 = IOMUX_PAD(0x02EC, 0x007C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDOE__LCD_DATA17 = IOMUX_PAD(0x02EC, 0x007C, 6, 0x067C, 0, 0), + MX7D_PAD_EPDC_SDOE__LCD_DATA23 = IOMUX_PAD(0x02EC, 0x007C, 7, 0x0694, 0, 0), + + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR = IOMUX_PAD(0x02F0, 0x0080, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1 = IOMUX_PAD(0x02F0, 0x0080, 1, 0x0588, 0, 0), + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 = IOMUX_PAD(0x02F0, 0x0080, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDSHR__KPP_ROW5 = IOMUX_PAD(0x02F0, 0x0080, 3, 0x0628, 1, 0), + MX7D_PAD_EPDC_SDSHR__EIM_AD13 = IOMUX_PAD(0x02F0, 0x0080, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 = IOMUX_PAD(0x02F0, 0x0080, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDSHR__LCD_DATA18 = IOMUX_PAD(0x02F0, 0x0080, 6, 0x0680, 0, 0), + MX7D_PAD_EPDC_SDSHR__LCD_DATA10 = IOMUX_PAD(0x02F0, 0x0080, 7, 0x0660, 1, 0), + + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 = IOMUX_PAD(0x02F4, 0x0084, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2 = IOMUX_PAD(0x02F4, 0x0084, 1, 0x058C, 0, 0), + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL = IOMUX_PAD(0x02F4, 0x0084, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE0__EIM_AD14 = IOMUX_PAD(0x02F4, 0x0084, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 = IOMUX_PAD(0x02F4, 0x0084, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE0__LCD_DATA19 = IOMUX_PAD(0x02F4, 0x0084, 6, 0x0684, 0, 0), + MX7D_PAD_EPDC_SDCE0__LCD_DATA5 = IOMUX_PAD(0x02F4, 0x0084, 7, 0x064C, 1, 0), + + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 = IOMUX_PAD(0x02F8, 0x0088, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3 = IOMUX_PAD(0x02F8, 0x0088, 1, 0x0590, 0, 0), + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC = IOMUX_PAD(0x02F8, 0x0088, 2, 0x0578, 0, 0), + MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER = IOMUX_PAD(0x02F8, 0x0088, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE1__EIM_AD15 = IOMUX_PAD(0x02F8, 0x0088, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 = IOMUX_PAD(0x02F8, 0x0088, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE1__LCD_DATA20 = IOMUX_PAD(0x02F8, 0x0088, 6, 0x0688, 1, 0), + MX7D_PAD_EPDC_SDCE1__LCD_DATA4 = IOMUX_PAD(0x02F8, 0x0088, 7, 0x0648, 1, 0), + + MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 = IOMUX_PAD(0x02FC, 0x008C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN = IOMUX_PAD(0x02FC, 0x008C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 = IOMUX_PAD(0x02FC, 0x008C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__KPP_COL6 = IOMUX_PAD(0x02FC, 0x008C, 3, 0x060C, 1, 0), + MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 = IOMUX_PAD(0x02FC, 0x008C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 = IOMUX_PAD(0x02FC, 0x008C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__LCD_DATA21 = IOMUX_PAD(0x02FC, 0x008C, 6, 0x068C, 1, 0), + MX7D_PAD_EPDC_SDCE2__LCD_DATA3 = IOMUX_PAD(0x02FC, 0x008C, 7, 0x0644, 1, 0), + + MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 = IOMUX_PAD(0x0300, 0x0090, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD = IOMUX_PAD(0x0300, 0x0090, 1, 0x06E8, 0, 0), + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 = IOMUX_PAD(0x0300, 0x0090, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE3__KPP_ROW6 = IOMUX_PAD(0x0300, 0x0090, 3, 0x062C, 1, 0), + MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 = IOMUX_PAD(0x0300, 0x0090, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 = IOMUX_PAD(0x0300, 0x0090, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE3__LCD_DATA22 = IOMUX_PAD(0x0300, 0x0090, 6, 0x0690, 1, 0), + MX7D_PAD_EPDC_SDCE3__LCD_DATA2 = IOMUX_PAD(0x0300, 0x0090, 7, 0x0640, 1, 0), + + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK = IOMUX_PAD(0x0304, 0x0094, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0 = IOMUX_PAD(0x0304, 0x0094, 1, 0x05AC, 0, 0), + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 = IOMUX_PAD(0x0304, 0x0094, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDCLK__KPP_COL7 = IOMUX_PAD(0x0304, 0x0094, 3, 0x0610, 0, 0), + MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 = IOMUX_PAD(0x0304, 0x0094, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 = IOMUX_PAD(0x0304, 0x0094, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDCLK__LCD_DATA23 = IOMUX_PAD(0x0304, 0x0094, 6, 0x0694, 1, 0), + MX7D_PAD_EPDC_GDCLK__LCD_DATA16 = IOMUX_PAD(0x0304, 0x0094, 7, 0x0678, 1, 0), + + MX7D_PAD_EPDC_GDOE__EPDC_GDOE = IOMUX_PAD(0x0308, 0x0098, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1 = IOMUX_PAD(0x0308, 0x0098, 1, 0x05B0, 0, 0), + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 = IOMUX_PAD(0x0308, 0x0098, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__KPP_ROW7 = IOMUX_PAD(0x0308, 0x0098, 3, 0x0630, 0, 0), + MX7D_PAD_EPDC_GDOE__EIM_ADDR19 = IOMUX_PAD(0x0308, 0x0098, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__GPIO2_IO25 = IOMUX_PAD(0x0308, 0x0098, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__LCD_WR_RWN = IOMUX_PAD(0x0308, 0x0098, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__LCD_DATA18 = IOMUX_PAD(0x0308, 0x0098, 7, 0x0680, 1, 0), + + MX7D_PAD_EPDC_GDRL__EPDC_GDRL = IOMUX_PAD(0x030C, 0x009C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2 = IOMUX_PAD(0x030C, 0x009C, 1, 0x05B4, 0, 0), + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL = IOMUX_PAD(0x030C, 0x009C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__EIM_ADDR20 = IOMUX_PAD(0x030C, 0x009C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__GPIO2_IO26 = IOMUX_PAD(0x030C, 0x009C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__LCD_RD_E = IOMUX_PAD(0x030C, 0x009C, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__LCD_DATA19 = IOMUX_PAD(0x030C, 0x009C, 7, 0x0684, 1, 0), + + MX7D_PAD_EPDC_GDSP__EPDC_GDSP = IOMUX_PAD(0x0310, 0x00A0, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3 = IOMUX_PAD(0x0310, 0x00A0, 1, 0x05B8, 0, 0), + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC = IOMUX_PAD(0x0310, 0x00A0, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__ENET2_TX_ER = IOMUX_PAD(0x0310, 0x00A0, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__EIM_ADDR21 = IOMUX_PAD(0x0310, 0x00A0, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__GPIO2_IO27 = IOMUX_PAD(0x0310, 0x00A0, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__LCD_BUSY = IOMUX_PAD(0x0310, 0x00A0, 6, 0x0634, 1, 0), + MX7D_PAD_EPDC_GDSP__LCD_DATA17 = IOMUX_PAD(0x0310, 0x00A0, 7, 0x067C, 1, 0), + + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 = IOMUX_PAD(0x0314, 0x00A4, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK = IOMUX_PAD(0x0314, 0x00A4, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x0314, 0x00A4, 3, 0x0570, 1, 0), + MX7D_PAD_EPDC_BDR0__EIM_ADDR22 = IOMUX_PAD(0x0314, 0x00A4, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 = IOMUX_PAD(0x0314, 0x00A4, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__LCD_CS = IOMUX_PAD(0x0314, 0x00A4, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__LCD_DATA7 = IOMUX_PAD(0x0314, 0x00A4, 7, 0x0654, 1, 0), + + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 = IOMUX_PAD(0x0318, 0x00A8, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN = IOMUX_PAD(0x0318, 0x00A8, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK = IOMUX_PAD(0x0318, 0x00A8, 2, 0x0578, 1, 0), + MX7D_PAD_EPDC_BDR1__EIM_AD8 = IOMUX_PAD(0x0318, 0x00A8, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 = IOMUX_PAD(0x0318, 0x00A8, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__LCD_ENABLE = IOMUX_PAD(0x0318, 0x00A8, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__LCD_DATA6 = IOMUX_PAD(0x0318, 0x00A8, 7, 0x0650, 1, 0), + + MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM = IOMUX_PAD(0x031C, 0x00AC, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA = IOMUX_PAD(0x031C, 0x00AC, 1, 0x05CC, 0, 0), + MX7D_PAD_EPDC_PWR_COM__ENET2_CRS = IOMUX_PAD(0x031C, 0x00AC, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__EIM_AD9 = IOMUX_PAD(0x031C, 0x00AC, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 = IOMUX_PAD(0x031C, 0x00AC, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC = IOMUX_PAD(0x031C, 0x00AC, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__LCD_DATA11 = IOMUX_PAD(0x031C, 0x00AC, 7, 0x0664, 1, 0), + + MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT = IOMUX_PAD(0x0320, 0x00B0, 0, 0x0580, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB = IOMUX_PAD(0x0320, 0x00B0, 1, 0x05D0, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__ENET2_COL = IOMUX_PAD(0x0320, 0x00B0, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1 = IOMUX_PAD(0x0320, 0x00B0, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 = IOMUX_PAD(0x0320, 0x00B0, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC = IOMUX_PAD(0x0320, 0x00B0, 6, 0x0698, 1, 0), + MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12 = IOMUX_PAD(0x0320, 0x00B0, 7, 0x0668, 1, 0), + + MX7D_PAD_LCD_CLK__LCD_CLK = IOMUX_PAD(0x0324, 0x00B4, 0, 0x0000, 0, 0), + MX7D_PAD_LCD_CLK__ECSPI4_MISO = IOMUX_PAD(0x0324, 0x00B4, 1, 0x0558, 0, 0), + MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x0324, 0x00B4, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_CLK__CSI_DATA16 = IOMUX_PAD(0x0324, 0x00B4, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_CLK__UART2_DCE_RX = IOMUX_PAD(0x0324, 0x00B4, 4, 0x06FC, 0, 0), + MX7D_PAD_LCD_CLK__UART2_DTE_TX = IOMUX_PAD(0x0324, 0x00B4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_CLK__GPIO3_IO0 = IOMUX_PAD(0x0324, 0x00B4, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_ENABLE__LCD_ENABLE = IOMUX_PAD(0x0328, 0x00B8, 0, 0x0000, 0, 0), + MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI = IOMUX_PAD(0x0328, 0x00B8, 1, 0x055C, 0, 0), + MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x0328, 0x00B8, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_ENABLE__CSI_DATA17 = IOMUX_PAD(0x0328, 0x00B8, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_ENABLE__UART2_DCE_TX = IOMUX_PAD(0x0328, 0x00B8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_ENABLE__UART2_DTE_RX = IOMUX_PAD(0x0328, 0x00B8, 4, 0x06FC, 1, 0), + MX7D_PAD_LCD_ENABLE__GPIO3_IO1 = IOMUX_PAD(0x0328, 0x00B8, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_HSYNC__LCD_HSYNC = IOMUX_PAD(0x032C, 0x00BC, 0, 0x0000, 0, 0), + MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK = IOMUX_PAD(0x032C, 0x00BC, 1, 0x0554, 0, 0), + MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x032C, 0x00BC, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_HSYNC__CSI_DATA18 = IOMUX_PAD(0x032C, 0x00BC, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS = IOMUX_PAD(0x032C, 0x00BC, 4, 0x06F8, 0, 0), + MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS = IOMUX_PAD(0x032C, 0x00BC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_HSYNC__GPIO3_IO2 = IOMUX_PAD(0x032C, 0x00BC, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_VSYNC__LCD_VSYNC = IOMUX_PAD(0x0330, 0x00C0, 0, 0x0698, 2, 0), + MX7D_PAD_LCD_VSYNC__ECSPI4_SS0 = IOMUX_PAD(0x0330, 0x00C0, 1, 0x0560, 0, 0), + MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x0330, 0x00C0, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_VSYNC__CSI_DATA19 = IOMUX_PAD(0x0330, 0x00C0, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS = IOMUX_PAD(0x0330, 0x00C0, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS = IOMUX_PAD(0x0330, 0x00C0, 4, 0x06F8, 1, 0), + MX7D_PAD_LCD_VSYNC__GPIO3_IO3 = IOMUX_PAD(0x0330, 0x00C0, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_RESET__LCD_RESET = IOMUX_PAD(0x0334, 0x00C4, 0, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__GPT1_COMPARE1 = IOMUX_PAD(0x0334, 0x00C4, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI = IOMUX_PAD(0x0334, 0x00C4, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__CSI_FIELD = IOMUX_PAD(0x0334, 0x00C4, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__EIM_DTACK_B = IOMUX_PAD(0x0334, 0x00C4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__GPIO3_IO4 = IOMUX_PAD(0x0334, 0x00C4, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA00__LCD_DATA0 = IOMUX_PAD(0x0338, 0x00C8, 0, 0x0638, 2, 0), + MX7D_PAD_LCD_DATA00__GPT1_COMPARE2 = IOMUX_PAD(0x0338, 0x00C8, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA00__CSI_DATA20 = IOMUX_PAD(0x0338, 0x00C8, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA00__EIM_DATA0 = IOMUX_PAD(0x0338, 0x00C8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA00__GPIO3_IO5 = IOMUX_PAD(0x0338, 0x00C8, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0 = IOMUX_PAD(0x0338, 0x00C8, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA01__LCD_DATA1 = IOMUX_PAD(0x033C, 0x00CC, 0, 0x063C, 2, 0), + MX7D_PAD_LCD_DATA01__GPT1_COMPARE3 = IOMUX_PAD(0x033C, 0x00CC, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA01__CSI_DATA21 = IOMUX_PAD(0x033C, 0x00CC, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA01__EIM_DATA1 = IOMUX_PAD(0x033C, 0x00CC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA01__GPIO3_IO6 = IOMUX_PAD(0x033C, 0x00CC, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1 = IOMUX_PAD(0x033C, 0x00CC, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA02__LCD_DATA2 = IOMUX_PAD(0x0340, 0x00D0, 0, 0x0640, 2, 0), + MX7D_PAD_LCD_DATA02__GPT1_CLK = IOMUX_PAD(0x0340, 0x00D0, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA02__CSI_DATA22 = IOMUX_PAD(0x0340, 0x00D0, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA02__EIM_DATA2 = IOMUX_PAD(0x0340, 0x00D0, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA02__GPIO3_IO7 = IOMUX_PAD(0x0340, 0x00D0, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2 = IOMUX_PAD(0x0340, 0x00D0, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA03__LCD_DATA3 = IOMUX_PAD(0x0344, 0x00D4, 0, 0x0644, 2, 0), + MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1 = IOMUX_PAD(0x0344, 0x00D4, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA03__CSI_DATA23 = IOMUX_PAD(0x0344, 0x00D4, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA03__EIM_DATA3 = IOMUX_PAD(0x0344, 0x00D4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA03__GPIO3_IO8 = IOMUX_PAD(0x0344, 0x00D4, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3 = IOMUX_PAD(0x0344, 0x00D4, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA04__LCD_DATA4 = IOMUX_PAD(0x0348, 0x00D8, 0, 0x0648, 2, 0), + MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2 = IOMUX_PAD(0x0348, 0x00D8, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA04__CSI_VSYNC = IOMUX_PAD(0x0348, 0x00D8, 3, 0x0520, 0, 0), + MX7D_PAD_LCD_DATA04__EIM_DATA4 = IOMUX_PAD(0x0348, 0x00D8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA04__GPIO3_IO9 = IOMUX_PAD(0x0348, 0x00D8, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4 = IOMUX_PAD(0x0348, 0x00D8, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA05__LCD_DATA5 = IOMUX_PAD(0x034C, 0x00DC, 0, 0x064C, 2, 0), + MX7D_PAD_LCD_DATA05__CSI_HSYNC = IOMUX_PAD(0x034C, 0x00DC, 3, 0x0518, 0, 0), + MX7D_PAD_LCD_DATA05__EIM_DATA5 = IOMUX_PAD(0x034C, 0x00DC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x034C, 0x00DC, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5 = IOMUX_PAD(0x034C, 0x00DC, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA06__LCD_DATA6 = IOMUX_PAD(0x0350, 0x00E0, 0, 0x0650, 2, 0), + MX7D_PAD_LCD_DATA06__CSI_PIXCLK = IOMUX_PAD(0x0350, 0x00E0, 3, 0x051C, 0, 0), + MX7D_PAD_LCD_DATA06__EIM_DATA6 = IOMUX_PAD(0x0350, 0x00E0, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x0350, 0x00E0, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6 = IOMUX_PAD(0x0350, 0x00E0, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA07__LCD_DATA7 = IOMUX_PAD(0x0354, 0x00E4, 0, 0x0654, 2, 0), + MX7D_PAD_LCD_DATA07__CSI_MCLK = IOMUX_PAD(0x0354, 0x00E4, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA07__EIM_DATA7 = IOMUX_PAD(0x0354, 0x00E4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x0354, 0x00E4, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7 = IOMUX_PAD(0x0354, 0x00E4, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA08__LCD_DATA8 = IOMUX_PAD(0x0358, 0x00E8, 0, 0x0658, 2, 0), + MX7D_PAD_LCD_DATA08__CSI_DATA9 = IOMUX_PAD(0x0358, 0x00E8, 3, 0x0514, 0, 0), + MX7D_PAD_LCD_DATA08__EIM_DATA8 = IOMUX_PAD(0x0358, 0x00E8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA08__GPIO3_IO13 = IOMUX_PAD(0x0358, 0x00E8, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8 = IOMUX_PAD(0x0358, 0x00E8, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA09__LCD_DATA9 = IOMUX_PAD(0x035C, 0x00EC, 0, 0x065C, 2, 0), + MX7D_PAD_LCD_DATA09__CSI_DATA8 = IOMUX_PAD(0x035C, 0x00EC, 3, 0x0510, 0, 0), + MX7D_PAD_LCD_DATA09__EIM_DATA9 = IOMUX_PAD(0x035C, 0x00EC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA09__GPIO3_IO14 = IOMUX_PAD(0x035C, 0x00EC, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9 = IOMUX_PAD(0x035C, 0x00EC, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA10__LCD_DATA10 = IOMUX_PAD(0x0360, 0x00F0, 0, 0x0660, 2, 0), + MX7D_PAD_LCD_DATA10__CSI_DATA7 = IOMUX_PAD(0x0360, 0x00F0, 3, 0x050C, 0, 0), + MX7D_PAD_LCD_DATA10__EIM_DATA10 = IOMUX_PAD(0x0360, 0x00F0, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA10__GPIO3_IO15 = IOMUX_PAD(0x0360, 0x00F0, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x0360, 0x00F0, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA11__LCD_DATA11 = IOMUX_PAD(0x0364, 0x00F4, 0, 0x0664, 2, 0), + MX7D_PAD_LCD_DATA11__CSI_DATA6 = IOMUX_PAD(0x0364, 0x00F4, 3, 0x0508, 0, 0), + MX7D_PAD_LCD_DATA11__EIM_DATA11 = IOMUX_PAD(0x0364, 0x00F4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA11__GPIO3_IO16 = IOMUX_PAD(0x0364, 0x00F4, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0364, 0x00F4, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA12__LCD_DATA12 = IOMUX_PAD(0x0368, 0x00F8, 0, 0x0668, 2, 0), + MX7D_PAD_LCD_DATA12__CSI_DATA5 = IOMUX_PAD(0x0368, 0x00F8, 3, 0x0504, 0, 0), + MX7D_PAD_LCD_DATA12__EIM_DATA12 = IOMUX_PAD(0x0368, 0x00F8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA12__GPIO3_IO17 = IOMUX_PAD(0x0368, 0x00F8, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0368, 0x00F8, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA13__LCD_DATA13 = IOMUX_PAD(0x036C, 0x00FC, 0, 0x066C, 1, 0), + MX7D_PAD_LCD_DATA13__CSI_DATA4 = IOMUX_PAD(0x036C, 0x00FC, 3, 0x0500, 0, 0), + MX7D_PAD_LCD_DATA13__EIM_DATA13 = IOMUX_PAD(0x036C, 0x00FC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA13__GPIO3_IO18 = IOMUX_PAD(0x036C, 0x00FC, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x036C, 0x00FC, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA14__LCD_DATA14 = IOMUX_PAD(0x0370, 0x0100, 0, 0x0670, 1, 0), + MX7D_PAD_LCD_DATA14__CSI_DATA3 = IOMUX_PAD(0x0370, 0x0100, 3, 0x04FC, 0, 0), + MX7D_PAD_LCD_DATA14__EIM_DATA14 = IOMUX_PAD(0x0370, 0x0100, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x0370, 0x0100, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x0370, 0x0100, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA15__LCD_DATA15 = IOMUX_PAD(0x0374, 0x0104, 0, 0x0674, 1, 0), + MX7D_PAD_LCD_DATA15__CSI_DATA2 = IOMUX_PAD(0x0374, 0x0104, 3, 0x04F8, 0, 0), + MX7D_PAD_LCD_DATA15__EIM_DATA15 = IOMUX_PAD(0x0374, 0x0104, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x0374, 0x0104, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0374, 0x0104, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA16__LCD_DATA16 = IOMUX_PAD(0x0378, 0x0108, 0, 0x0678, 2, 0), + MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4 = IOMUX_PAD(0x0378, 0x0108, 1, 0x0594, 0, 0), + MX7D_PAD_LCD_DATA16__CSI_DATA1 = IOMUX_PAD(0x0378, 0x0108, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA16__EIM_CRE = IOMUX_PAD(0x0378, 0x0108, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x0378, 0x0108, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16 = IOMUX_PAD(0x0378, 0x0108, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA17__LCD_DATA17 = IOMUX_PAD(0x037C, 0x010C, 0, 0x067C, 2, 0), + MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5 = IOMUX_PAD(0x037C, 0x010C, 1, 0x0598, 0, 0), + MX7D_PAD_LCD_DATA17__CSI_DATA0 = IOMUX_PAD(0x037C, 0x010C, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN = IOMUX_PAD(0x037C, 0x010C, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x037C, 0x010C, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17 = IOMUX_PAD(0x037C, 0x010C, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA18__LCD_DATA18 = IOMUX_PAD(0x0380, 0x0110, 0, 0x0680, 2, 0), + MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6 = IOMUX_PAD(0x0380, 0x0110, 1, 0x059C, 0, 0), + MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO = IOMUX_PAD(0x0380, 0x0110, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA18__CSI_DATA15 = IOMUX_PAD(0x0380, 0x0110, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA18__EIM_CS2_B = IOMUX_PAD(0x0380, 0x0110, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA18__GPIO3_IO23 = IOMUX_PAD(0x0380, 0x0110, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18 = IOMUX_PAD(0x0380, 0x0110, 6, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA19__EIM_CS3_B = IOMUX_PAD(0x0384, 0x0114, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA19__GPIO3_IO24 = IOMUX_PAD(0x0384, 0x0114, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19 = IOMUX_PAD(0x0384, 0x0114, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA19__LCD_DATA19 = IOMUX_PAD(0x0384, 0x0114, 0, 0x0684, 2, 0), + MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7 = IOMUX_PAD(0x0384, 0x0114, 1, 0x05A0, 0, 0), + MX7D_PAD_LCD_DATA19__CSI_DATA14 = IOMUX_PAD(0x0384, 0x0114, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA20__EIM_ADDR23 = IOMUX_PAD(0x0388, 0x0118, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA20__GPIO3_IO25 = IOMUX_PAD(0x0388, 0x0118, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA20__I2C3_SCL = IOMUX_PAD(0x0388, 0x0118, IOMUX_CONFIG_SION | 6, 0x05E4, 1, 0), + + MX7D_PAD_LCD_DATA20__LCD_DATA20 = IOMUX_PAD(0x0388, 0x0118, 0, 0x0688, 2, 0), + MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4 = IOMUX_PAD(0x0388, 0x0118, 1, 0x05BC, 0, 0), + MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x0388, 0x0118, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA20__CSI_DATA13 = IOMUX_PAD(0x0388, 0x0118, 3, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA21__LCD_DATA21 = IOMUX_PAD(0x038C, 0x011C, 0, 0x068C, 2, 0), + MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5 = IOMUX_PAD(0x038C, 0x011C, 1, 0x05C0, 0, 0), + MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x038C, 0x011C, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA21__CSI_DATA12 = IOMUX_PAD(0x038C, 0x011C, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA21__EIM_ADDR24 = IOMUX_PAD(0x038C, 0x011C, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA21__GPIO3_IO26 = IOMUX_PAD(0x038C, 0x011C, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA21__I2C3_SDA = IOMUX_PAD(0x038C, 0x011C, IOMUX_CONFIG_SION | 6, 0x05E8, 1, 0), + + MX7D_PAD_LCD_DATA22__LCD_DATA22 = IOMUX_PAD(0x0390, 0x0120, 0, 0x0690, 2, 0), + MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6 = IOMUX_PAD(0x0390, 0x0120, 1, 0x05C4, 0, 0), + MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x0390, 0x0120, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA22__CSI_DATA11 = IOMUX_PAD(0x0390, 0x0120, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA22__EIM_ADDR25 = IOMUX_PAD(0x0390, 0x0120, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA22__GPIO3_IO27 = IOMUX_PAD(0x0390, 0x0120, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA22__I2C4_SCL = IOMUX_PAD(0x0390, 0x0120, IOMUX_CONFIG_SION | 6, 0x05EC, 1, 0), + + MX7D_PAD_LCD_DATA23__LCD_DATA23 = IOMUX_PAD(0x0394, 0x0124, 0, 0x0694, 2, 0), + MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7 = IOMUX_PAD(0x0394, 0x0124, 1, 0x05C8, 0, 0), + MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x0394, 0x0124, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA23__CSI_DATA10 = IOMUX_PAD(0x0394, 0x0124, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA23__EIM_ADDR26 = IOMUX_PAD(0x0394, 0x0124, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA23__GPIO3_IO28 = IOMUX_PAD(0x0394, 0x0124, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA23__I2C4_SDA = IOMUX_PAD(0x0394, 0x0124, IOMUX_CONFIG_SION | 6, 0x05F0, 1, 0), + + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0398, 0x0128, 0, 0x06F4, 0, 0), + + MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__I2C1_SCL = IOMUX_PAD(0x0398, 0x0128, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY = IOMUX_PAD(0x0398, 0x0128, 2, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 = IOMUX_PAD(0x0398, 0x0128, 3, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x0398, 0x0128, 4, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 = IOMUX_PAD(0x0398, 0x0128, 5, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__ENET1_MDIO = IOMUX_PAD(0x0398, 0x0128, 6, 0x0000, 0, 0), + + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX = IOMUX_PAD(0x039C, 0x012C, 0, 0x0000, 0, 0), + + MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX = IOMUX_PAD(0x039C, 0x012C, 0, 0x06F4, 1, 0), + MX7D_PAD_UART1_TX_DATA__I2C1_SDA = IOMUX_PAD(0x039C, 0x012C, IOMUX_CONFIG_SION | 1, 0x05D8, 0, 0), + MX7D_PAD_UART1_TX_DATA__SAI3_MCLK = IOMUX_PAD(0x039C, 0x012C, 2, 0x0000, 0, 0), + MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2 = IOMUX_PAD(0x039C, 0x012C, 3, 0x0000, 0, 0), + MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x039C, 0x012C, 4, 0x0000, 0, 0), + MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 = IOMUX_PAD(0x039C, 0x012C, 5, 0x0000, 0, 0), + MX7D_PAD_UART1_TX_DATA__ENET1_MDC = IOMUX_PAD(0x039C, 0x012C, 6, 0x0000, 0, 0), + + MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x06FC, 2, 0), + + MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__I2C2_SCL = IOMUX_PAD(0x03A0, 0x0130, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK = IOMUX_PAD(0x03A0, 0x0130, 2, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 = IOMUX_PAD(0x03A0, 0x0130, 3, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x03A0, 0x0130, 4, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 = IOMUX_PAD(0x03A0, 0x0130, 5, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__ENET2_MDIO = IOMUX_PAD(0x03A0, 0x0130, 6, 0x0000, 0, 0), + + MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0), + + MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x06FC, 3, 0), + MX7D_PAD_UART2_TX_DATA__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0134, IOMUX_CONFIG_SION | 1, 0x05E0, 0, 0), + MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 = IOMUX_PAD(0x03A4, 0x0134, 2, 0x06C8, 0, 0), + MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY = IOMUX_PAD(0x03A4, 0x0134, 3, 0x0000, 0, 0), + MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x03A4, 0x0134, 4, 0x0000, 0, 0), + MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 = IOMUX_PAD(0x03A4, 0x0134, 5, 0x0000, 0, 0), + MX7D_PAD_UART2_TX_DATA__ENET2_MDC = IOMUX_PAD(0x03A4, 0x0134, 6, 0x0000, 0, 0), + + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX = IOMUX_PAD(0x03A8, 0x0138, 0, 0x0704, 2, 0), + + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX = IOMUX_PAD(0x03A8, 0x0138, 0, 0x0000, 0, 0), + MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC = IOMUX_PAD(0x03A8, 0x0138, 1, 0x072C, 0, 0), + MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC = IOMUX_PAD(0x03A8, 0x0138, 2, 0x06CC, 0, 0), + MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0138, 3, 0x0528, 0, 0), + MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x03A8, 0x0138, 4, 0x0000, 0, 0), + MX7D_PAD_UART3_RX_DATA__GPIO4_IO4 = IOMUX_PAD(0x03A8, 0x0138, 5, 0x0000, 0, 0), + MX7D_PAD_UART3_RX_DATA__SD1_LCTL = IOMUX_PAD(0x03A8, 0x0138, 6, 0x0000, 0, 0), + + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX = IOMUX_PAD(0x03AC, 0x013C, 0, 0x0000, 0, 0), + + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX = IOMUX_PAD(0x03AC, 0x013C, 0, 0x0704, 3, 0), + MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR = IOMUX_PAD(0x03AC, 0x013C, 1, 0x0000, 0, 0), + MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK = IOMUX_PAD(0x03AC, 0x013C, 2, 0x06D0, 0, 0), + MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x013C, 3, 0x052C, 0, 0), + MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x03AC, 0x013C, 4, 0x0000, 0, 0), + MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 = IOMUX_PAD(0x03AC, 0x013C, 5, 0x0000, 0, 0), + MX7D_PAD_UART3_TX_DATA__SD2_LCTL = IOMUX_PAD(0x03AC, 0x013C, 6, 0x0000, 0, 0), + + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0700, 2, 0), + + MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__USB_OTG2_OC = IOMUX_PAD(0x03B0, 0x0140, 1, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 = IOMUX_PAD(0x03B0, 0x0140, 2, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK = IOMUX_PAD(0x03B0, 0x0140, 3, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x03B0, 0x0140, 4, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__GPIO4_IO6 = IOMUX_PAD(0x03B0, 0x0140, 5, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__SD3_LCTL = IOMUX_PAD(0x03B0, 0x0140, 6, 0x0000, 0, 0), + + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS = IOMUX_PAD(0x03B4, 0x0144, 0, 0x0000, 0, 0), + + MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS = IOMUX_PAD(0x03B4, 0x0144, 0, 0x0700, 3, 0), + MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR = IOMUX_PAD(0x03B4, 0x0144, 1, 0x0000, 0, 0), + MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC = IOMUX_PAD(0x03B4, 0x0144, 2, 0x06D4, 0, 0), + MX7D_PAD_UART3_CTS_B__ECSPI1_SS0 = IOMUX_PAD(0x03B4, 0x0144, 3, 0x0530, 0, 0), + MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x03B4, 0x0144, 4, 0x0000, 0, 0), + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 = IOMUX_PAD(0x03B4, 0x0144, 5, 0x0000, 0, 0), + MX7D_PAD_UART3_CTS_B__SD1_VSELECT = IOMUX_PAD(0x03B4, 0x0144, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x03B8, 0x0148, IOMUX_CONFIG_SION | 0, 0x05D4, 1, 0), + MX7D_PAD_I2C1_SCL__UART4_DCE_CTS = IOMUX_PAD(0x03B8, 0x0148, 1, 0x0000, 0, 0), + MX7D_PAD_I2C1_SCL__UART4_DTE_RTS = IOMUX_PAD(0x03B8, 0x0148, 1, 0x0708, 0, 0), + MX7D_PAD_I2C1_SCL__FLEXCAN1_RX = IOMUX_PAD(0x03B8, 0x0148, 2, 0x04DC, 1, 0), + MX7D_PAD_I2C1_SCL__ECSPI3_MISO = IOMUX_PAD(0x03B8, 0x0148, 3, 0x0548, 0, 0), + MX7D_PAD_I2C1_SCL__GPIO4_IO8 = IOMUX_PAD(0x03B8, 0x0148, 5, 0x0000, 0, 0), + MX7D_PAD_I2C1_SCL__SD2_VSELECT = IOMUX_PAD(0x03B8, 0x0148, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x03BC, 0x014C, IOMUX_CONFIG_SION | 0, 0x05D8, 1, 0), + MX7D_PAD_I2C1_SDA__UART4_DCE_RTS = IOMUX_PAD(0x03BC, 0x014C, 1, 0x0708, 1, 0), + MX7D_PAD_I2C1_SDA__UART4_DTE_CTS = IOMUX_PAD(0x03BC, 0x014C, 1, 0x0000, 0, 0), + MX7D_PAD_I2C1_SDA__FLEXCAN1_TX = IOMUX_PAD(0x03BC, 0x014C, 2, 0x0000, 0, 0), + MX7D_PAD_I2C1_SDA__ECSPI3_MOSI = IOMUX_PAD(0x03BC, 0x014C, 3, 0x054C, 0, 0), + MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x03BC, 0x014C, 4, 0x0564, 1, 0), + MX7D_PAD_I2C1_SDA__GPIO4_IO9 = IOMUX_PAD(0x03BC, 0x014C, 5, 0x0000, 0, 0), + MX7D_PAD_I2C1_SDA__SD3_VSELECT = IOMUX_PAD(0x03BC, 0x014C, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x03C0, 0x0150, IOMUX_CONFIG_SION | 0, 0x05DC, 1, 0), + MX7D_PAD_I2C2_SCL__UART4_DCE_RX = IOMUX_PAD(0x03C0, 0x0150, 1, 0x070C, 0, 0), + MX7D_PAD_I2C2_SCL__UART4_DTE_TX = IOMUX_PAD(0x03C0, 0x0150, 1, 0x0000, 0, 0), + MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B = IOMUX_PAD(0x03C0, 0x0150, 2, 0x0000, 0, 0), + MX7D_PAD_I2C2_SCL__ECSPI3_SCLK = IOMUX_PAD(0x03C0, 0x0150, 3, 0x0544, 0, 0), + MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x03C0, 0x0150, 4, 0x0570, 2, 0), + MX7D_PAD_I2C2_SCL__GPIO4_IO10 = IOMUX_PAD(0x03C0, 0x0150, 5, 0x0000, 0, 0), + MX7D_PAD_I2C2_SCL__SD3_CD_B = IOMUX_PAD(0x03C0, 0x0150, 6, 0x0738, 1, 0), + + MX7D_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x03C4, 0x0154, IOMUX_CONFIG_SION | 0, 0x05E0, 1, 0), + MX7D_PAD_I2C2_SDA__UART4_DCE_TX = IOMUX_PAD(0x03C4, 0x0154, 1, 0x0000, 0, 0), + MX7D_PAD_I2C2_SDA__UART4_DTE_RX = IOMUX_PAD(0x03C4, 0x0154, 1, 0x070C, 1, 0), + MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x03C4, 0x0154, 2, 0x0000, 0, 0), + MX7D_PAD_I2C2_SDA__ECSPI3_SS0 = IOMUX_PAD(0x03C4, 0x0154, 3, 0x0550, 0, 0), + MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x03C4, 0x0154, 4, 0x0000, 0, 0), + MX7D_PAD_I2C2_SDA__GPIO4_IO11 = IOMUX_PAD(0x03C4, 0x0154, 5, 0x0000, 0, 0), + MX7D_PAD_I2C2_SDA__SD3_WP = IOMUX_PAD(0x03C4, 0x0154, 6, 0x073C, 1, 0), + + MX7D_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x03C8, 0x0158, IOMUX_CONFIG_SION | 0, 0x05E4, 2, 0), + MX7D_PAD_I2C3_SCL__UART5_DCE_CTS = IOMUX_PAD(0x03C8, 0x0158, 1, 0x0000, 0, 0), + MX7D_PAD_I2C3_SCL__UART5_DTE_RTS = IOMUX_PAD(0x03C8, 0x0158, 1, 0x0710, 0, 0), + MX7D_PAD_I2C3_SCL__FLEXCAN2_RX = IOMUX_PAD(0x03C8, 0x0158, 2, 0x04E0, 1, 0), + MX7D_PAD_I2C3_SCL__CSI_VSYNC = IOMUX_PAD(0x03C8, 0x0158, 3, 0x0520, 1, 0), + MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0 = IOMUX_PAD(0x03C8, 0x0158, 4, 0x06D8, 1, 0), + MX7D_PAD_I2C3_SCL__GPIO4_IO12 = IOMUX_PAD(0x03C8, 0x0158, 5, 0x0000, 0, 0), + MX7D_PAD_I2C3_SCL__EPDC_BDR0 = IOMUX_PAD(0x03C8, 0x0158, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x03CC, 0x015C, IOMUX_CONFIG_SION | 0, 0x05E8, 2, 0), + MX7D_PAD_I2C3_SDA__UART5_DCE_RTS = IOMUX_PAD(0x03CC, 0x015C, 1, 0x0710, 1, 0), + MX7D_PAD_I2C3_SDA__UART5_DTE_CTS = IOMUX_PAD(0x03CC, 0x015C, 1, 0x0000, 0, 0), + MX7D_PAD_I2C3_SDA__FLEXCAN2_TX = IOMUX_PAD(0x03CC, 0x015C, 2, 0x0000, 0, 0), + MX7D_PAD_I2C3_SDA__CSI_HSYNC = IOMUX_PAD(0x03CC, 0x015C, 3, 0x0518, 1, 0), + MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1 = IOMUX_PAD(0x03CC, 0x015C, 4, 0x06DC, 1, 0), + MX7D_PAD_I2C3_SDA__GPIO4_IO13 = IOMUX_PAD(0x03CC, 0x015C, 5, 0x0000, 0, 0), + MX7D_PAD_I2C3_SDA__EPDC_BDR1 = IOMUX_PAD(0x03CC, 0x015C, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x03D0, 0x0160, IOMUX_CONFIG_SION | 0, 0x05EC, 2, 0), + MX7D_PAD_I2C4_SCL__UART5_DCE_RX = IOMUX_PAD(0x03D0, 0x0160, 1, 0x0714, 0, 0), + MX7D_PAD_I2C4_SCL__UART5_DTE_TX = IOMUX_PAD(0x03D0, 0x0160, 1, 0x0000, 0, 0), + MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B = IOMUX_PAD(0x03D0, 0x0160, 2, 0x0000, 0, 0), + MX7D_PAD_I2C4_SCL__CSI_PIXCLK = IOMUX_PAD(0x03D0, 0x0160, 3, 0x051C, 1, 0), + MX7D_PAD_I2C4_SCL__USB_OTG1_ID = IOMUX_PAD(0x03D0, 0x0160, 4, 0x0734, 1, 0), + MX7D_PAD_I2C4_SCL__GPIO4_IO14 = IOMUX_PAD(0x03D0, 0x0160, 5, 0x0000, 0, 0), + MX7D_PAD_I2C4_SCL__EPDC_VCOM0 = IOMUX_PAD(0x03D0, 0x0160, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x03D4, 0x0164, IOMUX_CONFIG_SION | 0, 0x05F0, 2, 0), + MX7D_PAD_I2C4_SDA__UART5_DCE_TX = IOMUX_PAD(0x03D4, 0x0164, 1, 0x0000, 0, 0), + MX7D_PAD_I2C4_SDA__UART5_DTE_RX = IOMUX_PAD(0x03D4, 0x0164, 1, 0x0714, 1, 0), + MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB = IOMUX_PAD(0x03D4, 0x0164, 2, 0x0000, 0, 0), + MX7D_PAD_I2C4_SDA__CSI_MCLK = IOMUX_PAD(0x03D4, 0x0164, 3, 0x0000, 0, 0), + MX7D_PAD_I2C4_SDA__USB_OTG2_ID = IOMUX_PAD(0x03D4, 0x0164, 4, 0x0730, 1, 0), + MX7D_PAD_I2C4_SDA__GPIO4_IO15 = IOMUX_PAD(0x03D4, 0x0164, 5, 0x0000, 0, 0), + MX7D_PAD_I2C4_SDA__EPDC_VCOM1 = IOMUX_PAD(0x03D4, 0x0164, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x03D8, 0x0168, 0, 0x0524, 1, 0), + MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX = IOMUX_PAD(0x03D8, 0x0168, 1, 0x071C, 2, 0), + MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX = IOMUX_PAD(0x03D8, 0x0168, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 = IOMUX_PAD(0x03D8, 0x0168, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SCLK__CSI_DATA2 = IOMUX_PAD(0x03D8, 0x0168, 3, 0x04F8, 1, 0), + MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 = IOMUX_PAD(0x03D8, 0x0168, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM = IOMUX_PAD(0x03D8, 0x0168, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x03DC, 0x016C, 0, 0x052C, 1, 0), + MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX = IOMUX_PAD(0x03DC, 0x016C, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX = IOMUX_PAD(0x03DC, 0x016C, 1, 0x071C, 3, 0), + MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 = IOMUX_PAD(0x03DC, 0x016C, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MOSI__CSI_DATA3 = IOMUX_PAD(0x03DC, 0x016C, 3, 0x04FC, 1, 0), + MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 = IOMUX_PAD(0x03DC, 0x016C, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT = IOMUX_PAD(0x03DC, 0x016C, 6, 0x0580, 1, 0), + + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x03E0, 0x0170, 0, 0x0528, 1, 0), + MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS = IOMUX_PAD(0x03E0, 0x0170, 1, 0x0718, 2, 0), + MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS = IOMUX_PAD(0x03E0, 0x0170, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MISO__SD2_DATA6 = IOMUX_PAD(0x03E0, 0x0170, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MISO__CSI_DATA4 = IOMUX_PAD(0x03E0, 0x0170, 3, 0x0500, 1, 0), + MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 = IOMUX_PAD(0x03E0, 0x0170, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ = IOMUX_PAD(0x03E0, 0x0170, 6, 0x057C, 0, 0), + + MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x03E4, 0x0174, 0, 0x0530, 1, 0), + MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS = IOMUX_PAD(0x03E4, 0x0174, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS = IOMUX_PAD(0x03E4, 0x0174, 1, 0x0718, 3, 0), + MX7D_PAD_ECSPI1_SS0__SD2_DATA7 = IOMUX_PAD(0x03E4, 0x0174, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SS0__CSI_DATA5 = IOMUX_PAD(0x03E4, 0x0174, 3, 0x0504, 1, 0), + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 = IOMUX_PAD(0x03E4, 0x0174, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3 = IOMUX_PAD(0x03E4, 0x0174, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x03E8, 0x0178, 0, 0x0534, 0, 0), + MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x0178, 1, 0x0724, 2, 0), + MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX = IOMUX_PAD(0x03E8, 0x0178, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 = IOMUX_PAD(0x03E8, 0x0178, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SCLK__CSI_DATA6 = IOMUX_PAD(0x03E8, 0x0178, 3, 0x0508, 1, 0), + MX7D_PAD_ECSPI2_SCLK__LCD_DATA13 = IOMUX_PAD(0x03E8, 0x0178, 4, 0x066C, 2, 0), + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 = IOMUX_PAD(0x03E8, 0x0178, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0 = IOMUX_PAD(0x03E8, 0x0178, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x03EC, 0x017C, 0, 0x053C, 0, 0), + MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX = IOMUX_PAD(0x03EC, 0x017C, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX = IOMUX_PAD(0x03EC, 0x017C, 1, 0x0724, 3, 0), + MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 = IOMUX_PAD(0x03EC, 0x017C, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MOSI__CSI_DATA7 = IOMUX_PAD(0x03EC, 0x017C, 3, 0x050C, 1, 0), + MX7D_PAD_ECSPI2_MOSI__LCD_DATA14 = IOMUX_PAD(0x03EC, 0x017C, 4, 0x0670, 2, 0), + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 = IOMUX_PAD(0x03EC, 0x017C, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1 = IOMUX_PAD(0x03EC, 0x017C, 6, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 = IOMUX_PAD(0x03F0, 0x0180, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2 = IOMUX_PAD(0x03F0, 0x0180, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x03F0, 0x0180, 0, 0x0538, 0, 0), + MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS = IOMUX_PAD(0x03F0, 0x0180, 1, 0x0720, 2, 0), + MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS = IOMUX_PAD(0x03F0, 0x0180, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MISO__SD1_DATA6 = IOMUX_PAD(0x03F0, 0x0180, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MISO__CSI_DATA8 = IOMUX_PAD(0x03F0, 0x0180, 3, 0x0510, 1, 0), + MX7D_PAD_ECSPI2_MISO__LCD_DATA15 = IOMUX_PAD(0x03F0, 0x0180, 4, 0x0674, 2, 0), + + MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x03F4, 0x0184, 0, 0x0540, 0, 0), + MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS = IOMUX_PAD(0x03F4, 0x0184, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS = IOMUX_PAD(0x03F4, 0x0184, 1, 0x0720, 3, 0), + MX7D_PAD_ECSPI2_SS0__SD1_DATA7 = IOMUX_PAD(0x03F4, 0x0184, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SS0__CSI_DATA9 = IOMUX_PAD(0x03F4, 0x0184, 3, 0x0514, 1, 0), + MX7D_PAD_ECSPI2_SS0__LCD_RESET = IOMUX_PAD(0x03F4, 0x0184, 4, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 = IOMUX_PAD(0x03F4, 0x0184, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE = IOMUX_PAD(0x03F4, 0x0184, 6, 0x0000, 0, 0), + + MX7D_PAD_SD1_CD_B__SD1_CD_B = IOMUX_PAD(0x03F8, 0x0188, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_CD_B__UART6_DCE_RX = IOMUX_PAD(0x03F8, 0x0188, 2, 0x071C, 4, 0), + MX7D_PAD_SD1_CD_B__UART6_DTE_TX = IOMUX_PAD(0x03F8, 0x0188, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_CD_B__ECSPI4_MISO = IOMUX_PAD(0x03F8, 0x0188, 3, 0x0558, 1, 0), + MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0 = IOMUX_PAD(0x03F8, 0x0188, 4, 0x0584, 1, 0), + MX7D_PAD_SD1_CD_B__GPIO5_IO0 = IOMUX_PAD(0x03F8, 0x0188, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_CD_B__CCM_CLKO1 = IOMUX_PAD(0x03F8, 0x0188, 6, 0x0000, 0, 0), + + MX7D_PAD_SD1_WP__SD1_WP = IOMUX_PAD(0x03FC, 0x018C, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_WP__UART6_DCE_TX = IOMUX_PAD(0x03FC, 0x018C, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_WP__UART6_DTE_RX = IOMUX_PAD(0x03FC, 0x018C, 2, 0x071C, 5, 0), + MX7D_PAD_SD1_WP__ECSPI4_MOSI = IOMUX_PAD(0x03FC, 0x018C, 3, 0x055C, 1, 0), + MX7D_PAD_SD1_WP__FLEXTIMER1_CH1 = IOMUX_PAD(0x03FC, 0x018C, 4, 0x0588, 1, 0), + MX7D_PAD_SD1_WP__GPIO5_IO1 = IOMUX_PAD(0x03FC, 0x018C, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_WP__CCM_CLKO2 = IOMUX_PAD(0x03FC, 0x018C, 6, 0x0000, 0, 0), + + MX7D_PAD_SD1_RESET_B__SD1_RESET_B = IOMUX_PAD(0x0400, 0x0190, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_RESET_B__SAI3_MCLK = IOMUX_PAD(0x0400, 0x0190, 1, 0x0000, 0, 0), + MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS = IOMUX_PAD(0x0400, 0x0190, 2, 0x0718, 4, 0), + MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS = IOMUX_PAD(0x0400, 0x0190, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK = IOMUX_PAD(0x0400, 0x0190, 3, 0x0554, 1, 0), + MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2 = IOMUX_PAD(0x0400, 0x0190, 4, 0x058C, 1, 0), + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 = IOMUX_PAD(0x0400, 0x0190, 5, 0x0000, 0, 0), + + MX7D_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x0404, 0x0194, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_CLK__SAI3_RX_SYNC = IOMUX_PAD(0x0404, 0x0194, 1, 0x06CC, 1, 0), + MX7D_PAD_SD1_CLK__UART6_DCE_CTS = IOMUX_PAD(0x0404, 0x0194, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_CLK__UART6_DTE_RTS = IOMUX_PAD(0x0404, 0x0194, 2, 0x0718, 5, 0), + MX7D_PAD_SD1_CLK__ECSPI4_SS0 = IOMUX_PAD(0x0404, 0x0194, 3, 0x0560, 1, 0), + MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3 = IOMUX_PAD(0x0404, 0x0194, 4, 0x0590, 1, 0), + MX7D_PAD_SD1_CLK__GPIO5_IO3 = IOMUX_PAD(0x0404, 0x0194, 5, 0x0000, 0, 0), + + MX7D_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x0408, 0x0198, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_CMD__SAI3_RX_BCLK = IOMUX_PAD(0x0408, 0x0198, 1, 0x06C4, 1, 0), + MX7D_PAD_SD1_CMD__ECSPI4_SS1 = IOMUX_PAD(0x0408, 0x0198, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0 = IOMUX_PAD(0x0408, 0x0198, 4, 0x05AC, 1, 0), + MX7D_PAD_SD1_CMD__GPIO5_IO4 = IOMUX_PAD(0x0408, 0x0198, 5, 0x0000, 0, 0), + + MX7D_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x040C, 0x019C, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0 = IOMUX_PAD(0x040C, 0x019C, 1, 0x06C8, 1, 0), + MX7D_PAD_SD1_DATA0__UART7_DCE_RX = IOMUX_PAD(0x040C, 0x019C, 2, 0x0724, 4, 0), + MX7D_PAD_SD1_DATA0__UART7_DTE_TX = IOMUX_PAD(0x040C, 0x019C, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA0__ECSPI4_SS2 = IOMUX_PAD(0x040C, 0x019C, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1 = IOMUX_PAD(0x040C, 0x019C, 4, 0x05B0, 1, 0), + MX7D_PAD_SD1_DATA0__GPIO5_IO5 = IOMUX_PAD(0x040C, 0x019C, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1 = IOMUX_PAD(0x040C, 0x019C, 6, 0x04E4, 1, 0), + + MX7D_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x0410, 0x01A0, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK = IOMUX_PAD(0x0410, 0x01A0, 1, 0x06D0, 1, 0), + MX7D_PAD_SD1_DATA1__UART7_DCE_TX = IOMUX_PAD(0x0410, 0x01A0, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA1__UART7_DTE_RX = IOMUX_PAD(0x0410, 0x01A0, 2, 0x0724, 5, 0), + MX7D_PAD_SD1_DATA1__ECSPI4_SS3 = IOMUX_PAD(0x0410, 0x01A0, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2 = IOMUX_PAD(0x0410, 0x01A0, 4, 0x05B4, 1, 0), + MX7D_PAD_SD1_DATA1__GPIO5_IO6 = IOMUX_PAD(0x0410, 0x01A0, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2 = IOMUX_PAD(0x0410, 0x01A0, 6, 0x04E8, 1, 0), + + MX7D_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x0414, 0x01A4, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC = IOMUX_PAD(0x0414, 0x01A4, 1, 0x06D4, 1, 0), + MX7D_PAD_SD1_DATA2__UART7_DCE_CTS = IOMUX_PAD(0x0414, 0x01A4, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA2__UART7_DTE_RTS = IOMUX_PAD(0x0414, 0x01A4, 2, 0x0720, 4, 0), + MX7D_PAD_SD1_DATA2__ECSPI4_RDY = IOMUX_PAD(0x0414, 0x01A4, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3 = IOMUX_PAD(0x0414, 0x01A4, 4, 0x05B8, 1, 0), + MX7D_PAD_SD1_DATA2__GPIO5_IO7 = IOMUX_PAD(0x0414, 0x01A4, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3 = IOMUX_PAD(0x0414, 0x01A4, 6, 0x04EC, 1, 0), + + MX7D_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x0418, 0x01A8, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0 = IOMUX_PAD(0x0418, 0x01A8, 1, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__UART7_DCE_RTS = IOMUX_PAD(0x0418, 0x01A8, 2, 0x0720, 5, 0), + MX7D_PAD_SD1_DATA3__UART7_DTE_CTS = IOMUX_PAD(0x0418, 0x01A8, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__ECSPI3_SS1 = IOMUX_PAD(0x0418, 0x01A8, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA = IOMUX_PAD(0x0418, 0x01A8, 4, 0x05A4, 1, 0), + MX7D_PAD_SD1_DATA3__GPIO5_IO8 = IOMUX_PAD(0x0418, 0x01A8, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4 = IOMUX_PAD(0x0418, 0x01A8, 6, 0x04F0, 1, 0), + + MX7D_PAD_SD2_CD_B__SD2_CD_B = IOMUX_PAD(0x041C, 0x01AC, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_CD_B__ENET1_MDIO = IOMUX_PAD(0x041C, 0x01AC, 1, 0x0568, 2, 0), + MX7D_PAD_SD2_CD_B__ENET2_MDIO = IOMUX_PAD(0x041C, 0x01AC, 2, 0x0574, 2, 0), + MX7D_PAD_SD2_CD_B__ECSPI3_SS2 = IOMUX_PAD(0x041C, 0x01AC, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB = IOMUX_PAD(0x041C, 0x01AC, 4, 0x05A8, 1, 0), + MX7D_PAD_SD2_CD_B__GPIO5_IO9 = IOMUX_PAD(0x041C, 0x01AC, 5, 0x0000, 0, 0), + MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0 = IOMUX_PAD(0x041C, 0x01AC, 6, 0x06D8, 2, 0), + + MX7D_PAD_SD2_WP__SD2_WP = IOMUX_PAD(0x0420, 0x01B0, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__ENET1_MDC = IOMUX_PAD(0x0420, 0x01B0, 1, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__ENET2_MDC = IOMUX_PAD(0x0420, 0x01B0, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__ECSPI3_SS3 = IOMUX_PAD(0x0420, 0x01B0, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__USB_OTG1_ID = IOMUX_PAD(0x0420, 0x01B0, 4, 0x0734, 2, 0), + MX7D_PAD_SD2_WP__GPIO5_IO10 = IOMUX_PAD(0x0420, 0x01B0, 5, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0420, 0x01B0, 6, 0x06DC, 2, 0), + + MX7D_PAD_SD2_RESET_B__SD2_RESET_B = IOMUX_PAD(0x0424, 0x01B4, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_RESET_B__SAI2_MCLK = IOMUX_PAD(0x0424, 0x01B4, 1, 0x0000, 0, 0), + MX7D_PAD_SD2_RESET_B__SD2_RESET = IOMUX_PAD(0x0424, 0x01B4, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_RESET_B__ECSPI3_RDY = IOMUX_PAD(0x0424, 0x01B4, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_RESET_B__USB_OTG2_ID = IOMUX_PAD(0x0424, 0x01B4, 4, 0x0730, 2, 0), + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 = IOMUX_PAD(0x0424, 0x01B4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x0428, 0x01B8, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_CLK__SAI2_RX_SYNC = IOMUX_PAD(0x0428, 0x01B8, 1, 0x06B8, 0, 0), + MX7D_PAD_SD2_CLK__MQS_RIGHT = IOMUX_PAD(0x0428, 0x01B8, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_CLK__GPT4_CLK = IOMUX_PAD(0x0428, 0x01B8, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_CLK__GPIO5_IO12 = IOMUX_PAD(0x0428, 0x01B8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x042C, 0x01BC, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_CMD__SAI2_RX_BCLK = IOMUX_PAD(0x042C, 0x01BC, 1, 0x06B0, 0, 0), + MX7D_PAD_SD2_CMD__MQS_LEFT = IOMUX_PAD(0x042C, 0x01BC, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_CMD__GPT4_CAPTURE1 = IOMUX_PAD(0x042C, 0x01BC, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD = IOMUX_PAD(0x042C, 0x01BC, 4, 0x06EC, 1, 0), + MX7D_PAD_SD2_CMD__GPIO5_IO13 = IOMUX_PAD(0x042C, 0x01BC, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x0430, 0x01C0, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0 = IOMUX_PAD(0x0430, 0x01C0, 1, 0x06B4, 0, 0), + MX7D_PAD_SD2_DATA0__UART4_DCE_RX = IOMUX_PAD(0x0430, 0x01C0, 2, 0x070C, 2, 0), + MX7D_PAD_SD2_DATA0__UART4_DTE_TX = IOMUX_PAD(0x0430, 0x01C0, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2 = IOMUX_PAD(0x0430, 0x01C0, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK = IOMUX_PAD(0x0430, 0x01C0, 4, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA0__GPIO5_IO14 = IOMUX_PAD(0x0430, 0x01C0, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x0434, 0x01C4, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK = IOMUX_PAD(0x0434, 0x01C4, 1, 0x06BC, 0, 0), + MX7D_PAD_SD2_DATA1__UART4_DCE_TX = IOMUX_PAD(0x0434, 0x01C4, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA1__UART4_DTE_RX = IOMUX_PAD(0x0434, 0x01C4, 2, 0x070C, 3, 0), + MX7D_PAD_SD2_DATA1__GPT4_COMPARE1 = IOMUX_PAD(0x0434, 0x01C4, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B = IOMUX_PAD(0x0434, 0x01C4, 4, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA1__GPIO5_IO15 = IOMUX_PAD(0x0434, 0x01C4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x0438, 0x01C8, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC = IOMUX_PAD(0x0438, 0x01C8, 1, 0x06C0, 0, 0), + MX7D_PAD_SD2_DATA2__UART4_DCE_CTS = IOMUX_PAD(0x0438, 0x01C8, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA2__UART4_DTE_RTS = IOMUX_PAD(0x0438, 0x01C8, 2, 0x0708, 2, 0), + MX7D_PAD_SD2_DATA2__GPT4_COMPARE2 = IOMUX_PAD(0x0438, 0x01C8, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN = IOMUX_PAD(0x0438, 0x01C8, 4, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA2__GPIO5_IO16 = IOMUX_PAD(0x0438, 0x01C8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x043C, 0x01CC, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0 = IOMUX_PAD(0x043C, 0x01CC, 1, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA3__UART4_DCE_RTS = IOMUX_PAD(0x043C, 0x01CC, 2, 0x0708, 3, 0), + MX7D_PAD_SD2_DATA3__UART4_DTE_CTS = IOMUX_PAD(0x043C, 0x01CC, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA3__GPT4_COMPARE3 = IOMUX_PAD(0x043C, 0x01CC, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD = IOMUX_PAD(0x043C, 0x01CC, 4, 0x06E8, 1, 0), + MX7D_PAD_SD2_DATA3__GPIO5_IO17 = IOMUX_PAD(0x043C, 0x01CC, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x0440, 0x01D0, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_CLK__NAND_CLE = IOMUX_PAD(0x0440, 0x01D0, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_CLK__ECSPI4_MISO = IOMUX_PAD(0x0440, 0x01D0, 2, 0x0558, 2, 0), + MX7D_PAD_SD3_CLK__SAI3_RX_SYNC = IOMUX_PAD(0x0440, 0x01D0, 3, 0x06CC, 2, 0), + MX7D_PAD_SD3_CLK__GPT3_CLK = IOMUX_PAD(0x0440, 0x01D0, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_CLK__GPIO6_IO0 = IOMUX_PAD(0x0440, 0x01D0, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x0444, 0x01D4, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_CMD__NAND_ALE = IOMUX_PAD(0x0444, 0x01D4, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_CMD__ECSPI4_MOSI = IOMUX_PAD(0x0444, 0x01D4, 2, 0x055C, 2, 0), + MX7D_PAD_SD3_CMD__SAI3_RX_BCLK = IOMUX_PAD(0x0444, 0x01D4, 3, 0x06C4, 2, 0), + MX7D_PAD_SD3_CMD__GPT3_CAPTURE1 = IOMUX_PAD(0x0444, 0x01D4, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_CMD__GPIO6_IO1 = IOMUX_PAD(0x0444, 0x01D4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA0__SD3_DATA0 = IOMUX_PAD(0x0448, 0x01D8, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA0__NAND_DATA00 = IOMUX_PAD(0x0448, 0x01D8, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA0__ECSPI4_SS0 = IOMUX_PAD(0x0448, 0x01D8, 2, 0x0560, 2, 0), + MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0 = IOMUX_PAD(0x0448, 0x01D8, 3, 0x06C8, 2, 0), + MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2 = IOMUX_PAD(0x0448, 0x01D8, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA0__GPIO6_IO2 = IOMUX_PAD(0x0448, 0x01D8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA1__SD3_DATA1 = IOMUX_PAD(0x044C, 0x01DC, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA1__NAND_DATA01 = IOMUX_PAD(0x044C, 0x01DC, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA1__ECSPI4_SCLK = IOMUX_PAD(0x044C, 0x01DC, 2, 0x0554, 2, 0), + MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK = IOMUX_PAD(0x044C, 0x01DC, 3, 0x06D0, 2, 0), + MX7D_PAD_SD3_DATA1__GPT3_COMPARE1 = IOMUX_PAD(0x044C, 0x01DC, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA1__GPIO6_IO3 = IOMUX_PAD(0x044C, 0x01DC, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA2__SD3_DATA2 = IOMUX_PAD(0x0450, 0x01E0, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA2__NAND_DATA02 = IOMUX_PAD(0x0450, 0x01E0, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA2__I2C3_SDA = IOMUX_PAD(0x0450, 0x01E0, IOMUX_CONFIG_SION | 2, 0x05E8, 3, 0), + MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC = IOMUX_PAD(0x0450, 0x01E0, 3, 0x06D4, 2, 0), + MX7D_PAD_SD3_DATA2__GPT3_COMPARE2 = IOMUX_PAD(0x0450, 0x01E0, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA2__GPIO6_IO4 = IOMUX_PAD(0x0450, 0x01E0, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA3__SD3_DATA3 = IOMUX_PAD(0x0454, 0x01E4, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA3__NAND_DATA03 = IOMUX_PAD(0x0454, 0x01E4, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA3__I2C3_SCL = IOMUX_PAD(0x0454, 0x01E4, IOMUX_CONFIG_SION | 2, 0x05E4, 3, 0), + MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0 = IOMUX_PAD(0x0454, 0x01E4, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA3__GPT3_COMPARE3 = IOMUX_PAD(0x0454, 0x01E4, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA3__GPIO6_IO5 = IOMUX_PAD(0x0454, 0x01E4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA4__SD3_DATA4 = IOMUX_PAD(0x0458, 0x01E8, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA4__NAND_DATA04 = IOMUX_PAD(0x0458, 0x01E8, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA4__UART3_DCE_RX = IOMUX_PAD(0x0458, 0x01E8, 3, 0x0704, 4, 0), + MX7D_PAD_SD3_DATA4__UART3_DTE_TX = IOMUX_PAD(0x0458, 0x01E8, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA4__FLEXCAN2_RX = IOMUX_PAD(0x0458, 0x01E8, 4, 0x04E0, 2, 0), + MX7D_PAD_SD3_DATA4__GPIO6_IO6 = IOMUX_PAD(0x0458, 0x01E8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA5__SD3_DATA5 = IOMUX_PAD(0x045C, 0x01EC, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA5__NAND_DATA05 = IOMUX_PAD(0x045C, 0x01EC, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA5__UART3_DCE_TX = IOMUX_PAD(0x045C, 0x01EC, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA5__UART3_DTE_RX = IOMUX_PAD(0x045C, 0x01EC, 3, 0x0704, 5, 0), + MX7D_PAD_SD3_DATA5__FLEXCAN1_TX = IOMUX_PAD(0x045C, 0x01EC, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA5__GPIO6_IO7 = IOMUX_PAD(0x045C, 0x01EC, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA6__SD3_DATA6 = IOMUX_PAD(0x0460, 0x01F0, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA6__NAND_DATA06 = IOMUX_PAD(0x0460, 0x01F0, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA6__SD3_WP = IOMUX_PAD(0x0460, 0x01F0, 2, 0x073C, 2, 0), + MX7D_PAD_SD3_DATA6__UART3_DCE_RTS = IOMUX_PAD(0x0460, 0x01F0, 3, 0x0700, 4, 0), + MX7D_PAD_SD3_DATA6__UART3_DTE_CTS = IOMUX_PAD(0x0460, 0x01F0, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA6__FLEXCAN2_TX = IOMUX_PAD(0x0460, 0x01F0, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA6__GPIO6_IO8 = IOMUX_PAD(0x0460, 0x01F0, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA7__SD3_DATA7 = IOMUX_PAD(0x0464, 0x01F4, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA7__NAND_DATA07 = IOMUX_PAD(0x0464, 0x01F4, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA7__SD3_CD_B = IOMUX_PAD(0x0464, 0x01F4, 2, 0x0738, 2, 0), + MX7D_PAD_SD3_DATA7__UART3_DCE_CTS = IOMUX_PAD(0x0464, 0x01F4, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA7__UART3_DTE_RTS = IOMUX_PAD(0x0464, 0x01F4, 3, 0x0700, 5, 0), + MX7D_PAD_SD3_DATA7__FLEXCAN1_RX = IOMUX_PAD(0x0464, 0x01F4, 4, 0x04DC, 2, 0), + MX7D_PAD_SD3_DATA7__GPIO6_IO9 = IOMUX_PAD(0x0464, 0x01F4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_STROBE__SD3_STROBE = IOMUX_PAD(0x0468, 0x01F8, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_STROBE__NAND_RE_B = IOMUX_PAD(0x0468, 0x01F8, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_STROBE__GPIO6_IO10 = IOMUX_PAD(0x0468, 0x01F8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_RESET_B__SD3_RESET_B = IOMUX_PAD(0x046C, 0x01FC, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_RESET_B__NAND_WE_B = IOMUX_PAD(0x046C, 0x01FC, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_RESET_B__SD3_RESET = IOMUX_PAD(0x046C, 0x01FC, 2, 0x0000, 0, 0), + MX7D_PAD_SD3_RESET_B__SAI3_MCLK = IOMUX_PAD(0x046C, 0x01FC, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 = IOMUX_PAD(0x046C, 0x01FC, 5, 0x0000, 0, 0), + + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 = IOMUX_PAD(0x0470, 0x0200, 0, 0x06A0, 0, 0), + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B = IOMUX_PAD(0x0470, 0x0200, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX = IOMUX_PAD(0x0470, 0x0200, 2, 0x0714, 2, 0), + MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX = IOMUX_PAD(0x0470, 0x0200, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX = IOMUX_PAD(0x0470, 0x0200, 3, 0x04DC, 3, 0), + MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD = IOMUX_PAD(0x0470, 0x0200, 4, 0x06E4, 1, 0), + MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 = IOMUX_PAD(0x0470, 0x0200, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET = IOMUX_PAD(0x0470, 0x0200, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK = IOMUX_PAD(0x0474, 0x0204, 0, 0x06A8, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B = IOMUX_PAD(0x0474, 0x0204, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX = IOMUX_PAD(0x0474, 0x0204, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX = IOMUX_PAD(0x0474, 0x0204, 2, 0x0714, 3, 0), + MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX = IOMUX_PAD(0x0474, 0x0204, 3, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK = IOMUX_PAD(0x0474, 0x0204, 4, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 = IOMUX_PAD(0x0474, 0x0204, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET = IOMUX_PAD(0x0474, 0x0204, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC = IOMUX_PAD(0x0478, 0x0208, 0, 0x06AC, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__NAND_DQS = IOMUX_PAD(0x0478, 0x0208, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS = IOMUX_PAD(0x0478, 0x0208, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS = IOMUX_PAD(0x0478, 0x0208, 2, 0x0710, 2, 0), + MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX = IOMUX_PAD(0x0478, 0x0208, 3, 0x04E0, 3, 0), + MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B = IOMUX_PAD(0x0478, 0x0208, 4, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 = IOMUX_PAD(0x0478, 0x0208, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT = IOMUX_PAD(0x0478, 0x0208, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 = IOMUX_PAD(0x047C, 0x020C, 0, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B = IOMUX_PAD(0x047C, 0x020C, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS = IOMUX_PAD(0x047C, 0x020C, 2, 0x0710, 3, 0), + MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS = IOMUX_PAD(0x047C, 0x020C, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX = IOMUX_PAD(0x047C, 0x020C, 3, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN = IOMUX_PAD(0x047C, 0x020C, 4, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 = IOMUX_PAD(0x047C, 0x020C, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET = IOMUX_PAD(0x047C, 0x020C, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC = IOMUX_PAD(0x0480, 0x0210, 0, 0x06A4, 0, 0), + MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B = IOMUX_PAD(0x0480, 0x0210, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC = IOMUX_PAD(0x0480, 0x0210, 2, 0x06B8, 1, 0), + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL = IOMUX_PAD(0x0480, 0x0210, IOMUX_CONFIG_SION | 3, 0x05EC, 3, 0), + MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD = IOMUX_PAD(0x0480, 0x0210, 4, 0x06E0, 1, 0), + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 = IOMUX_PAD(0x0480, 0x0210, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT = IOMUX_PAD(0x0480, 0x0210, 6, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0 = IOMUX_PAD(0x0480, 0x0210, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK = IOMUX_PAD(0x0484, 0x0214, 0, 0x069C, 0, 0), + MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B = IOMUX_PAD(0x0484, 0x0214, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK = IOMUX_PAD(0x0484, 0x0214, 2, 0x06B0, 1, 0), + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA = IOMUX_PAD(0x0484, 0x0214, IOMUX_CONFIG_SION | 3, 0x05F0, 3, 0), + MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA = IOMUX_PAD(0x0484, 0x0214, 4, 0x05CC, 1, 0), + MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 = IOMUX_PAD(0x0484, 0x0214, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT = IOMUX_PAD(0x0484, 0x0214, 6, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1 = IOMUX_PAD(0x0484, 0x0214, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_MCLK__SAI1_MCLK = IOMUX_PAD(0x0488, 0x0218, 0, 0x0000, 0, 0), + MX7D_PAD_SAI1_MCLK__NAND_WP_B = IOMUX_PAD(0x0488, 0x0218, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_MCLK__SAI2_MCLK = IOMUX_PAD(0x0488, 0x0218, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY = IOMUX_PAD(0x0488, 0x0218, 3, 0x04F4, 3, 0), + MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB = IOMUX_PAD(0x0488, 0x0218, 4, 0x05D0, 1, 0), + MX7D_PAD_SAI1_MCLK__GPIO6_IO18 = IOMUX_PAD(0x0488, 0x0218, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK = IOMUX_PAD(0x0488, 0x0218, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC = IOMUX_PAD(0x048C, 0x021C, 0, 0x06C0, 1, 0), + MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x021C, 1, 0x0548, 1, 0), + MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX = IOMUX_PAD(0x048C, 0x021C, 2, 0x070C, 4, 0), + MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX = IOMUX_PAD(0x048C, 0x021C, 2, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS = IOMUX_PAD(0x048C, 0x021C, 3, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS = IOMUX_PAD(0x048C, 0x021C, 3, 0x06F0, 0, 0), + MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4 = IOMUX_PAD(0x048C, 0x021C, 4, 0x05BC, 1, 0), + MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 = IOMUX_PAD(0x048C, 0x021C, 5, 0x0000, 0, 0), + + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK = IOMUX_PAD(0x0490, 0x0220, 0, 0x06BC, 1, 0), + MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI = IOMUX_PAD(0x0490, 0x0220, 1, 0x054C, 1, 0), + MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX = IOMUX_PAD(0x0490, 0x0220, 2, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX = IOMUX_PAD(0x0490, 0x0220, 2, 0x070C, 5, 0), + MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS = IOMUX_PAD(0x0490, 0x0220, 3, 0x06F0, 1, 0), + MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS = IOMUX_PAD(0x0490, 0x0220, 3, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5 = IOMUX_PAD(0x0490, 0x0220, 4, 0x05C0, 1, 0), + MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 = IOMUX_PAD(0x0490, 0x0220, 5, 0x0000, 0, 0), + + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 = IOMUX_PAD(0x0494, 0x0224, 0, 0x06B4, 1, 0), + MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK = IOMUX_PAD(0x0494, 0x0224, 1, 0x0544, 1, 0), + MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS = IOMUX_PAD(0x0494, 0x0224, 2, 0x0000, 0, 0), + MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS = IOMUX_PAD(0x0494, 0x0224, 2, 0x0708, 4, 0), + MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS = IOMUX_PAD(0x0494, 0x0224, 3, 0x0000, 0, 0), + MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS = IOMUX_PAD(0x0494, 0x0224, 3, 0x06F8, 2, 0), + MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6 = IOMUX_PAD(0x0494, 0x0224, 4, 0x05C4, 1, 0), + MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 = IOMUX_PAD(0x0494, 0x0224, 5, 0x0000, 0, 0), + MX7D_PAD_SAI2_RX_DATA__KPP_COL7 = IOMUX_PAD(0x0494, 0x0224, 6, 0x0610, 1, 0), + + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 = IOMUX_PAD(0x0498, 0x0228, 0, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 = IOMUX_PAD(0x0498, 0x0228, 1, 0x0550, 1, 0), + MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS = IOMUX_PAD(0x0498, 0x0228, 2, 0x0708, 5, 0), + MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS = IOMUX_PAD(0x0498, 0x0228, 2, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS = IOMUX_PAD(0x0498, 0x0228, 3, 0x06F8, 3, 0), + MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS = IOMUX_PAD(0x0498, 0x0228, 3, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7 = IOMUX_PAD(0x0498, 0x0228, 4, 0x05C8, 1, 0), + MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 = IOMUX_PAD(0x0498, 0x0228, 5, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_DATA__KPP_ROW7 = IOMUX_PAD(0x0498, 0x0228, 6, 0x0630, 1, 0), + + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 = IOMUX_PAD(0x049C, 0x022C, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT = IOMUX_PAD(0x049C, 0x022C, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL = IOMUX_PAD(0x049C, 0x022C, IOMUX_CONFIG_SION | 2, 0x05E4, 4, 0), + MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS = IOMUX_PAD(0x049C, 0x022C, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS = IOMUX_PAD(0x049C, 0x022C, 3, 0x06F0, 2, 0), + MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0 = IOMUX_PAD(0x049C, 0x022C, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 = IOMUX_PAD(0x049C, 0x022C, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3 = IOMUX_PAD(0x049C, 0x022C, 6, 0x0620, 1, 0), + + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 = IOMUX_PAD(0x04A0, 0x0230, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT = IOMUX_PAD(0x04A0, 0x0230, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA = IOMUX_PAD(0x04A0, 0x0230, IOMUX_CONFIG_SION | 2, 0x05E8, 4, 0), + MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS = IOMUX_PAD(0x04A0, 0x0230, 3, 0x06F0, 3, 0), + MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS = IOMUX_PAD(0x04A0, 0x0230, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1 = IOMUX_PAD(0x04A0, 0x0230, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 = IOMUX_PAD(0x04A0, 0x0230, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3 = IOMUX_PAD(0x04A0, 0x0230, 6, 0x0600, 1, 0), + + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 = IOMUX_PAD(0x04A4, 0x0234, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX = IOMUX_PAD(0x04A4, 0x0234, 1, 0x04DC, 4, 0), + MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK = IOMUX_PAD(0x04A4, 0x0234, 2, 0x0534, 1, 0), + MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX = IOMUX_PAD(0x04A4, 0x0234, 3, 0x06F4, 2, 0), + MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX = IOMUX_PAD(0x04A4, 0x0234, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4 = IOMUX_PAD(0x04A4, 0x0234, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 = IOMUX_PAD(0x04A4, 0x0234, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2 = IOMUX_PAD(0x04A4, 0x0234, 6, 0x061C, 1, 0), + + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 = IOMUX_PAD(0x04A8, 0x0238, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX = IOMUX_PAD(0x04A8, 0x0238, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI = IOMUX_PAD(0x04A8, 0x0238, 2, 0x053C, 1, 0), + MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX = IOMUX_PAD(0x04A8, 0x0238, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX = IOMUX_PAD(0x04A8, 0x0238, 3, 0x06F4, 3, 0), + MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5 = IOMUX_PAD(0x04A8, 0x0238, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 = IOMUX_PAD(0x04A8, 0x0238, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2 = IOMUX_PAD(0x04A8, 0x0238, 6, 0x05FC, 1, 0), + + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x04AC, 0x023C, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1 = IOMUX_PAD(0x04AC, 0x023C, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6 = IOMUX_PAD(0x04AC, 0x023C, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 = IOMUX_PAD(0x04AC, 0x023C, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1 = IOMUX_PAD(0x04AC, 0x023C, 6, 0x0618, 1, 0), + + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC = IOMUX_PAD(0x04B0, 0x0240, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER = IOMUX_PAD(0x04B0, 0x0240, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2 = IOMUX_PAD(0x04B0, 0x0240, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7 = IOMUX_PAD(0x04B0, 0x0240, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 = IOMUX_PAD(0x04B0, 0x0240, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1 = IOMUX_PAD(0x04B0, 0x0240, 6, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 = IOMUX_PAD(0x04B4, 0x0244, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT = IOMUX_PAD(0x04B4, 0x0244, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3 = IOMUX_PAD(0x04B4, 0x0244, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8 = IOMUX_PAD(0x04B4, 0x0244, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 = IOMUX_PAD(0x04B4, 0x0244, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0 = IOMUX_PAD(0x04B4, 0x0244, 6, 0x0614, 1, 0), + + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x04B8, 0x0248, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT = IOMUX_PAD(0x04B8, 0x0248, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY = IOMUX_PAD(0x04B8, 0x0248, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9 = IOMUX_PAD(0x04B8, 0x0248, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 = IOMUX_PAD(0x04B8, 0x0248, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0 = IOMUX_PAD(0x04B8, 0x0248, 6, 0x05F4, 1, 0), + + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 = IOMUX_PAD(0x04BC, 0x024C, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX = IOMUX_PAD(0x04BC, 0x024C, 1, 0x04E0, 4, 0), + MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO = IOMUX_PAD(0x04BC, 0x024C, 2, 0x0538, 1, 0), + MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL = IOMUX_PAD(0x04BC, 0x024C, IOMUX_CONFIG_SION | 3, 0x05EC, 4, 0), + MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED = IOMUX_PAD(0x04BC, 0x024C, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 = IOMUX_PAD(0x04BC, 0x024C, 5, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 = IOMUX_PAD(0x04C0, 0x0250, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX = IOMUX_PAD(0x04C0, 0x0250, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0 = IOMUX_PAD(0x04C0, 0x0250, 2, 0x0540, 1, 0), + MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA = IOMUX_PAD(0x04C0, 0x0250, IOMUX_CONFIG_SION | 3, 0x05F0, 4, 0), + MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ = IOMUX_PAD(0x04C0, 0x0250, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 = IOMUX_PAD(0x04C0, 0x0250, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x04C0, 0x0250, 7, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x04C4, 0x0254, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC = IOMUX_PAD(0x04C4, 0x0254, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 = IOMUX_PAD(0x04C4, 0x0254, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 = IOMUX_PAD(0x04C4, 0x0254, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 = IOMUX_PAD(0x04C4, 0x0254, 5, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC = IOMUX_PAD(0x04C8, 0x0258, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER = IOMUX_PAD(0x04C8, 0x0258, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK = IOMUX_PAD(0x04C8, 0x0258, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 = IOMUX_PAD(0x04C8, 0x0258, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 = IOMUX_PAD(0x04C8, 0x0258, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 = IOMUX_PAD(0x04C8, 0x0258, 5, 0x0000, 0, 0), + + MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK = IOMUX_PAD(0x04CC, 0x025C, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x04CC, 0x025C, 1, 0x0564, 2, 0), + MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 = IOMUX_PAD(0x04CC, 0x025C, 2, 0x06A0, 1, 0), + MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3 = IOMUX_PAD(0x04CC, 0x025C, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ = IOMUX_PAD(0x04CC, 0x025C, 4, 0x057C, 1, 0), + MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 = IOMUX_PAD(0x04CC, 0x025C, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1 = IOMUX_PAD(0x04CC, 0x025C, 6, 0x04E4, 2, 0), + MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0 = IOMUX_PAD(0x04CC, 0x025C, 7, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK = IOMUX_PAD(0x04D0, 0x0260, 0, 0x056C, 0, 0), + MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B = IOMUX_PAD(0x04D0, 0x0260, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK = IOMUX_PAD(0x04D0, 0x0260, 2, 0x06A8, 1, 0), + MX7D_PAD_ENET1_RX_CLK__GPT2_CLK = IOMUX_PAD(0x04D0, 0x0260, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE = IOMUX_PAD(0x04D0, 0x0260, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 = IOMUX_PAD(0x04D0, 0x0260, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2 = IOMUX_PAD(0x04D0, 0x0260, 6, 0x04E8, 2, 0), + MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1 = IOMUX_PAD(0x04D0, 0x0260, 7, 0x0000, 0, 0), + + MX7D_PAD_ENET1_CRS__ENET1_CRS = IOMUX_PAD(0x04D4, 0x0264, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x04D4, 0x0264, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC = IOMUX_PAD(0x04D4, 0x0264, 2, 0x06AC, 1, 0), + MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1 = IOMUX_PAD(0x04D4, 0x0264, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0 = IOMUX_PAD(0x04D4, 0x0264, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__GPIO7_IO14 = IOMUX_PAD(0x04D4, 0x0264, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3 = IOMUX_PAD(0x04D4, 0x0264, 6, 0x04EC, 2, 0), + MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2 = IOMUX_PAD(0x04D4, 0x0264, 7, 0x0000, 0, 0), + + MX7D_PAD_ENET1_COL__ENET1_COL = IOMUX_PAD(0x04D8, 0x0268, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY = IOMUX_PAD(0x04D8, 0x0268, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 = IOMUX_PAD(0x04D8, 0x0268, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__GPT2_CAPTURE2 = IOMUX_PAD(0x04D8, 0x0268, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1 = IOMUX_PAD(0x04D8, 0x0268, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__GPIO7_IO15 = IOMUX_PAD(0x04D8, 0x0268, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__CCM_EXT_CLK4 = IOMUX_PAD(0x04D8, 0x0268, 6, 0x04F0, 2, 0), + MX7D_PAD_ENET1_COL__CSU_INT_DEB = IOMUX_PAD(0x04D8, 0x0268, 7, 0x0000, 0, 0), +}; +#endif /* __ASM_ARCH_IMX7D_PINS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx7/mx7d_rdc.h b/roms/u-boot/arch/arm/include/asm/arch-mx7/mx7d_rdc.h new file mode 100644 index 000000000..2ea175ceb --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx7/mx7d_rdc.h @@ -0,0 +1,162 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#ifndef __MX7D_RDC_H__ +#define __MX7D_RDC_H__ + +#define RDC_SEMA_PROC_ID 2 /* The processor ID for main CPU */ + +enum { + RDC_PER_GPIO1 = 0, + RDC_PER_GPIO2, + RDC_PER_GPIO3, + RDC_PER_GPIO4, + RDC_PER_GPIO5, + RDC_PER_GPIO6, + RDC_PER_GPIO7, + RDC_PER_IOMUXC_LPSR_GPR, + RDC_PER_WDOG1, + RDC_PER_WDOG2, + RDC_PER_WDOG3, + RDC_PER_WDOG4, + RDC_PER_IOMUXC_LPSR, + RDC_PER_GPT1, + RDC_PER_GPT2, + RDC_PER_GPT3, + RDC_PER_GPT4, + RDC_PER_ROMCP, + RDC_PER_KPP, + RDC_PER_IOMUXC, + RDC_PER_IOMUXCGPR, + RDC_PER_OCOTP, + RDC_PER_ANATOP_DIG, + RDC_PER_SNVS_HP, + RDC_PER_CCM, + RDC_PER_SRC, + RDC_PER_GPC, + RDC_PER_SEMA1, + RDC_PER_SEMA2, + RDC_PER_RDC, + RDC_PER_CSU, + RDC_PER_RESERVED1, + RDC_PER_RESERVED2, + RDC_PER_ADC1, + RDC_PER_ADC2, + RDC_PER_ECSPI4, + RDC_PER_FLEX_TIMER1, + RDC_PER_FLEX_TIMER2, + RDC_PER_PWM1, + RDC_PER_PWM2, + RDC_PER_PWM3, + RDC_PER_PWM4, + RDC_PER_SYSTEM_COUNTER_READ, + RDC_PER_SYSTEM_COUNTER_COMPARE, + RDC_PER_SYSTEM_COUNTER_CONTROL, + RDC_PER_PCIE_PHY, + RDC_PER_RESERVED3, + RDC_PER_EPDC, + RDC_PER_PXP, + RDC_PER_CSI, + RDC_PER_RESERVED4, + RDC_PER_LCDIF, + RDC_PER_RESERVED5, + RDC_PER_MIPI_CSI, + RDC_PER_MIPI_DSI, + RDC_PER_RESERVED6, + RDC_PER_TZASC, + RDC_PER_DDR_PHY, + RDC_PER_DDRC, + RDC_PER_RESERVED7, + RDC_PER_PERFMON1, + RDC_PER_PERFMON2, + RDC_PER_AXI_DEBUG_MON, + RDC_PER_QOSC, + RDC_PER_FLEXCAN1, + RDC_PER_FLEXCAN2, + RDC_PER_I2C1, + RDC_PER_I2C2, + RDC_PER_I2C3, + RDC_PER_I2C4, + RDC_PER_UART4, + RDC_PER_UART5, + RDC_PER_UART6, + RDC_PER_UART7, + RDC_PER_MU_A, + RDC_PER_MU_B, + RDC_PER_SEMAPHORE_HS, + RDC_PER_USB_PL301, + RDC_PER_RESERVED8, + RDC_PER_RESERVED9, + RDC_PER_RESERVED10, + RDC_PER_USB1, + RDC_PER_USB2, + RDC_PER_USB3, + RDC_PER_USDHC1, + RDC_PER_USDHC2, + RDC_PER_USDHC3, + RDC_PER_RESERVED11, + RDC_PER_RESERVED12, + RDC_PER_SIM1, + RDC_PER_SIM2, + RDC_PER_QSPI, + RDC_PER_WEIM, + RDC_PER_SDMA, + RDC_PER_ENET1, + RDC_PER_ENET2, + RDC_PER_RESERVED13, + RDC_PER_RESERVED14, + RDC_PER_ECSPI1, + RDC_PER_ECSPI2, + RDC_PER_ECSPI3, + RDC_PER_RESERVED15, + RDC_PER_UART1, + RDC_PER_UART2, + RDC_PER_UART3, + RDC_PER_RESERVED16, + RDC_PER_SAI1, + RDC_PER_SAI2, + RDC_PER_SAI3, + RDC_PER_RESERVED17, + RDC_PER_RESERVED18, + RDC_PER_SPBA, + RDC_PER_DAP, + RDC_PER_RESERVED19, + RDC_PER_RESERVED20, + RDC_PER_RESERVED21, + RDC_PER_CAAM, + RDC_PER_RESERVED22, +}; + +enum { + RDC_MA_A7 = 0, + RDC_MA_M4, + RDC_MA_PCIE, + RDC_MA_CSI, + RDC_MA_EPDC, + RDC_MA_LCDIF, + RDC_MA_DISPLAY_PORT, + RDC_MA_PXP, + RDC_MA_CORESIGHT, + RDC_MA_DAP, + RDC_MA_CAAM, + RDC_MA_SDMA_PERI, + RDC_MA_SDMA_BURST, + RDC_MA_APBHDMA, + RDC_MA_RAWNAND, + RDC_MA_USDHC1, + RDC_MA_USDHC2, + RDC_MA_USDHC3, + RDC_MA_NC1, + RDC_MA_USB, + RDC_MA_NC2, + RDC_MA_TEST, + RDC_MA_ENET1_TX, + RDC_MA_ENET1_RX, + RDC_MA_ENET2_TX, + RDC_MA_ENET2_RX, + RDC_MA_SDMA, +}; + +#endif /* __MX7D_RDC_H__*/ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx7/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-mx7/sys_proto.h new file mode 100644 index 000000000..e46a02198 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx7/sys_proto.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ +#ifndef __SYS_PROTO_IMX7_ +#define __SYS_PROTO_IMX7_ + +#include + +void set_wdog_reset(struct wdog_regs *wdog); +enum boot_device get_boot_device(void); + +#endif /* __SYS_PROTO_IMX7_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/clock.h b/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/clock.h new file mode 100644 index 000000000..92d4463df --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/clock.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#ifndef _ASM_ARCH_CLOCK_H +#define _ASM_ARCH_CLOCK_H + +#include +#include + +/* Mainly for compatible to imx common code. */ +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_UART_CLK, + MXC_CSPI_CLK, + MXC_AXI_CLK, + MXC_DDR_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_I2C_CLK, +}; + +u32 mxc_get_clock(enum mxc_clock clk); +u32 get_lpuart_clk(void); +#ifdef CONFIG_SYS_I2C_IMX_LPI2C +int enable_i2c_clk(unsigned char enable, unsigned i2c_num); +u32 imx_get_i2cclk(unsigned i2c_num); +#endif +#ifdef CONFIG_MXC_OCOTP +void enable_ocotp_clk(unsigned char enable); +#endif +#ifdef CONFIG_USB_EHCI_HCD +void enable_usboh3_clk(unsigned char enable); +#endif +void init_clk_usdhc(u32 index); +void clock_init(void); +void hab_caam_clock_enable(unsigned char enable); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/gpio.h new file mode 100644 index 000000000..7c625609b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/gpio.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#ifndef __ASM_ARCH_MX7ULP_GPIO_H +#define __ASM_ARCH_MX7ULP_GPIO_H + +struct gpio_regs { + u32 gpio_pdor; + u32 gpio_psor; + u32 gpio_pcor; + u32 gpio_ptor; + u32 gpio_pdir; + u32 gpio_pddr; + u32 gpio_gacr; +}; + +#define IMX_GPIO_NR(port, index) ((((port)-1)*32)+((index)&31)) + +#endif /* __ASM_ARCH_MX7ULP_GPIO_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/imx-regs.h new file mode 100644 index 000000000..cb0c2c15c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -0,0 +1,1157 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#ifndef _MX7ULP_REGS_H_ +#define _MX7ULP_REGS_H_ + +#include + +#define ARCH_MXC + +#define ROM_SW_INFO_ADDR 0x000001E8 + +#define CAAM_SEC_SRAM_BASE (0x26000000) +#define CAAM_SEC_SRAM_SIZE (SZ_32K) +#define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1) + +#define CAAM_ARB_BASE_ADDR CAAM_SEC_SRAM_BASE + +#define OCRAM_0_BASE (0x2F000000) +#define OCRAM_0_SIZE (SZ_128K) +#define OCRAM_0_END (OCRAM_0_BASE + OCRAM_0_SIZE - 1) + +#define OCRAM_1_BASE (0x2F020000) +#define OCRAM_1_SIZE (SZ_128K) +#define OCRAM_1_END (OCRAM_1_BASE + OCRAM_1_SIZE - 1) + +#define TCML_BASE (0x1FFD0000) +#define TCMU_BASE (0x20000000) + +#define AIPS3_BASE (0x40800000UL) +#define AIPS3_SLOT_SIZE (SZ_64K) +#define AIPS2_BASE (0x40000000UL) +#define AIPS2_SLOT_SIZE (SZ_64K) +#define AIPS1_BASE (0x41080000UL) +#define AIPS1_SLOT_SIZE (SZ_4K) +#define AIPS0_BASE (0x41000000UL) +#define AIPS0_SLOT_SIZE (SZ_4K) +#define IOMUXC0_AIPS0_SLOT (61) +#define WDG0_AIPS0_SLOT (37) +#define WDG1_AIPS2_SLOT (61) +#define WDG2_AIPS2_SLOT (67) +#define WDG0_PCC0_SLOT (37) +#define IOMUXC1_AIPS3_SLOT (44) +#define CMC0_AIPS1_SLOT (36) +#define CMC1_AIPS2_SLOT (65) +#define SCG0_AIPS0_SLOT (39) +#define PCC0_AIPS0_SLOT (38) +#define PCC1_AIPS1_SLOT (50) +#define PCC2_AIPS2_SLOT (63) +#define PCC3_AIPS3_SLOT (51) +#define SCG1_AIPS2_SLOT (62) +#define SIM0_AIPS1_SLOT (35) +#define SIM1_AIPS1_SLOT (48) +#define USBOTG0_AIPS2_SLOT (51) +#define USBOTG1_AIPS2_SLOT (52) +#define USBPHY_AIPS2_SLOT (53) +#define USDHC0_AIPS2_SLOT (55) +#define USDHC1_AIPS2_SLOT (56) +#define RGPIO2P0_AIPS0_SLOT (15) +#define RGPIO2P1_AIPS2_SLOT (15) +#define SNVS_AIPS2_SLOT (35) +#define IOMUXC0_AIPS0_SLOT (61) +#define OCOTP_CTRL_AIPS1_SLOT (38) +#define OCOTP_CTRL_PCC1_SLOT (38) +#define SIM1_PCC1_SLOT (48) +#define MMDC0_AIPS3_SLOT (43) +#define IOMUXC_DDR_AIPS3_SLOT (45) + +#define LPI2C0_AIPS0_SLOT (51) +#define LPI2C1_AIPS0_SLOT (52) +#define LPI2C2_AIPS0_SLOT (53) +#define LPI2C3_AIPS0_SLOT (54) +#define LPI2C4_AIPS2_SLOT (43) +#define LPI2C5_AIPS2_SLOT (44) +#define LPI2C6_AIPS3_SLOT (36) +#define LPI2C7_AIPS3_SLOT (37) + +#define LPUART0_PCC0_SLOT (58) +#define LPUART1_PCC0_SLOT (59) +#define LPUART2_PCC1_SLOT (43) +#define LPUART3_PCC1_SLOT (44) +#define LPUART0_AIPS0_SLOT (58) +#define LPUART1_AIPS0_SLOT (59) +#define LPUART2_AIPS1_SLOT (43) +#define LPUART3_AIPS1_SLOT (44) +#define LPUART4_AIPS2_SLOT (45) +#define LPUART5_AIPS2_SLOT (46) +#define LPUART6_AIPS3_SLOT (38) +#define LPUART7_AIPS3_SLOT (39) + +#define CORE_B_ROM_SIZE (SZ_32K + SZ_64K) +#define CORE_B_ROM_BASE (0x00000000) + +#define ROMCP_ARB_BASE_ADDR CORE_B_ROM_BASE +#define ROMCP_ARB_END_ADDR CORE_B_ROM_SIZE +#define IRAM_BASE_ADDR OCRAM_0_BASE +#define IRAM_SIZE (SZ_128K + SZ_128K) + +#define IOMUXC_PCR_MUX_ALT0 (0<<8) +#define IOMUXC_PCR_MUX_ALT1 (1<<8) +#define IOMUXC_PCR_MUX_ALT2 (2<<8) +#define IOMUXC_PCR_MUX_ALT3 (3<<8) +#define IOMUXC_PCR_MUX_ALT4 (4<<8) +#define IOMUXC_PCR_MUX_ALT5 (5<<8) +#define IOMUXC_PCR_MUX_ALT6 (6<<8) +#define IOMUXC_PCR_MUX_ALT7 (7<<8) +#define IOMUXC_PCR_MUX_ALT8 (8<<8) +#define IOMUXC_PCR_MUX_ALT9 (9<<8) +#define IOMUXC_PCR_MUX_ALT10 (10<<8) +#define IOMUXC_PCR_MUX_ALT11 (11<<8) +#define IOMUXC_PCR_MUX_ALT12 (12<<8) +#define IOMUXC_PCR_MUX_ALT13 (13<<8) +#define IOMUXC_PCR_MUX_ALT14 (14<<8) +#define IOMUXC_PCR_MUX_ALT15 (15<<8) + +#define IOMUXC_PSMI_IMUX_ALT0 (0x0) +#define IOMUXC_PSMI_IMUX_ALT1 (0x1) +#define IOMUXC_PSMI_IMUX_ALT2 (0x2) +#define IOMUXC_PSMI_IMUX_ALT3 (0x3) +#define IOMUXC_PSMI_IMUX_ALT4 (0x4) +#define IOMUXC_PSMI_IMUX_ALT5 (0x5) +#define IOMUXC_PSMI_IMUX_ALT6 (0x6) +#define IOMUXC_PSMI_IMUX_ALT7 (0x7) + + +#define SIM_SOPT1_EN_SNVS_HARD_RST (1<<8) +#define SIM_SOPT1_PMIC_STBY_REQ (1<<2) +#define SIM_SOPT1_A7_SW_RESET (1<<0) + +#define IOMUXC_PCR_MUX_ALT_SHIFT (8) +#define IOMUXC_PCR_MUX_ALT_MASK (0xF00) +#define IOMUXC_PSMI_IMUX_ALT_SHIFT (0) + +#define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT))) +#define IOMUXC1_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC1_AIPS3_SLOT))) +#define WDG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * WDG0_AIPS0_SLOT))) +#define WDG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG1_AIPS2_SLOT))) +#define WDG2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG2_AIPS2_SLOT))) +#define SCG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * SCG0_AIPS0_SLOT))) +#define SCG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SCG1_AIPS2_SLOT))) +#define PCC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * PCC0_AIPS0_SLOT))) +#define PCC1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * PCC1_AIPS1_SLOT))) +#define PCC2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * PCC2_AIPS2_SLOT))) +#define PCC3_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * PCC3_AIPS3_SLOT))) +#define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT))) +#define PSMI0_RBASE ((IOMUXC0_RBASE + 0x100)) /* in iomuxc0 after pta and ptb */ +#define CMC0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * CMC0_AIPS1_SLOT))) +#define CMC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * CMC1_AIPS2_SLOT))) +#define OCOTP_BASE_ADDR ((AIPS1_BASE + (AIPS1_SLOT_SIZE * OCOTP_CTRL_AIPS1_SLOT))) +#define SIM0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM0_AIPS1_SLOT))) +#define SIM1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM1_AIPS1_SLOT))) +#define MMDC0_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * MMDC0_AIPS3_SLOT))) + +#define USBOTG0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG0_AIPS2_SLOT))) +#define USBOTG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG1_AIPS2_SLOT))) +#define USBPHY_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBPHY_AIPS2_SLOT))) +#define USB_PHY0_BASE_ADDR USBPHY_RBASE +#define USB_BASE_ADDR USBOTG0_RBASE + +#define LPI2C1_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C0_AIPS0_SLOT))) +#define LPI2C2_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C1_AIPS0_SLOT))) +#define LPI2C3_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C2_AIPS0_SLOT))) +#define LPI2C4_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C3_AIPS0_SLOT))) +#define LPI2C5_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C4_AIPS2_SLOT))) +#define LPI2C6_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C5_AIPS2_SLOT))) +#define LPI2C7_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C6_AIPS3_SLOT))) +#define LPI2C8_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C7_AIPS3_SLOT))) + +#define LPUART0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART0_AIPS0_SLOT))) +#define LPUART1_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART1_AIPS0_SLOT))) +#define LPUART2_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART2_AIPS1_SLOT))) +#define LPUART3_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART3_AIPS1_SLOT))) +#define LPUART4_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART4_AIPS2_SLOT))) +#define LPUART5_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART5_AIPS2_SLOT))) +#define LPUART6_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART6_AIPS3_SLOT))) +#define LPUART7_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART7_AIPS3_SLOT))) + +#define USDHC0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT))) +#define USDHC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT))) + +#define SNVS_BASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SNVS_AIPS2_SLOT))) +#define SNVS_LP_LPCR (SNVS_BASE + 0x38) + +#define RGPIO2P0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT))) +#define RGPIO2P1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * RGPIO2P1_AIPS2_SLOT))) + +#define WDG0_PCC_REG (PCC0_RBASE + (4 * WDG0_PCC0_SLOT)) +#define WDG1_PCC_REG (PCC2_RBASE + (4 * WDG1_PCC2_SLOT)) +#define CMC0_SRS (CMC0_RBASE + 0x20) +#define CMC0_SSRS (CMC0_RBASE + 0x28) +#define CMC1_SRS (CMC1_RBASE + 0x20) +#define CMC1_SSRS (CMC1_RBASE + 0x28) + +#define IOMUXC0_PCR0 (IOMUXC0_RBASE + (4 * 0)) +#define IOMUXC0_PCR1 (IOMUXC0_RBASE + (4 * 1)) +#define IOMUXC0_PCR2 (IOMUXC0_RBASE + (4 * 2)) +#define IOMUXC0_PCR3 (IOMUXC0_RBASE + (4 * 3)) +#define IOMUXC0_PSMI62 (PSMI0_RBASE + (4 * 62)) +#define IOMUXC0_PSMI63 (PSMI0_RBASE + (4 * 63)) +#define IOMUXC0_PSMI64 (PSMI0_RBASE + (4 * 64)) + +#define SCG_CSR (SCG0_RBASE + 0x010) +#define SCG_RCCR (SCG0_RBASE + 0x014) +#define SCG_VCCR (SCG0_RBASE + 0x018) +#define SCG_HCCR (SCG0_RBASE + 0x01c) + +#define LPUART0_PCC_REG (PCC0_RBASE + (4 * LPUART0_PCC0_SLOT)) +#define LPUART1_PCC_REG (PCC0_RBASE + (4 * LPUART1_PCC0_SLOT)) +#define LPUART2_PCC_REG (PCC1_RBASE + (4 * LPUART2_PCC1_SLOT)) +#define LPUART3_PCC_REG (PCC1_RBASE + (4 * LPUART3_PCC1_SLOT)) +#define LPUART4_PCC_REG (PCC2_RBASE + (4 * LPUART4_PCC2_SLOT)) +#define LPUART5_PCC_REG (PCC2_RBASE + (4 * LPUART5_PCC2_SLOT)) +#define LPUART6_PCC_REG (PCC3_RBASE + (4 * LPUART6_PCC3_SLOT)) +#define LPUART7_PCC_REG (PCC3_RBASE + (4 * LPUART7_PCC3_SLOT)) + +#define USDHC0_PCC_REG (PCC2_RBASE + (4 * USDHC0_PCC2_SLOT)) +#define USDHC1_PCC_REG (PCC2_RBASE + (4 * USDHC1_PCC2_SLOT)) + +#define SIM1_PCC_REG (PCC1_RBASE + (4 * SIM1_PCC1_SLOT)) +#define SCG1_PCC_REG (PCC2_RBASE + (4 * SCG1_PCC2_SLOT)) + +#define OCOTP_CTRL_PCC_REG (PCC1_RBASE + (4 * OCOTP_CTRL_PCC1_SLOT)) + +#define IOMUXC_DDR_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC_DDR_AIPS3_SLOT))) +#define MMDC0_PCC_REG (PCC3_RBASE + (4 * MMDC0_PCC3_SLOT)) + +#define CAAM_IPS_BASE_ADDR (AIPS2_BASE + 0x240000) /* 40240000 */ + +#define CONFIG_SYS_FSL_SEC_OFFSET 0 +#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ + CONFIG_SYS_FSL_JR0_OFFSET) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + +#define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32))) +#define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33))) +#define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34))) +#define IOMUXC_DPCR_DDR_DQS3 ((IOMUXC_DDR_RBASE + (4 * 35))) + + +#define IOMUXC_DPCR_DDR_DQ0 ((IOMUXC_DDR_RBASE + (4 * 0))) +#define IOMUXC_DPCR_DDR_DQ1 ((IOMUXC_DDR_RBASE + (4 * 1))) +#define IOMUXC_DPCR_DDR_DQ2 ((IOMUXC_DDR_RBASE + (4 * 2))) +#define IOMUXC_DPCR_DDR_DQ3 ((IOMUXC_DDR_RBASE + (4 * 3))) +#define IOMUXC_DPCR_DDR_DQ4 ((IOMUXC_DDR_RBASE + (4 * 4))) +#define IOMUXC_DPCR_DDR_DQ5 ((IOMUXC_DDR_RBASE + (4 * 5))) +#define IOMUXC_DPCR_DDR_DQ6 ((IOMUXC_DDR_RBASE + (4 * 6))) +#define IOMUXC_DPCR_DDR_DQ7 ((IOMUXC_DDR_RBASE + (4 * 7))) +#define IOMUXC_DPCR_DDR_DQ8 ((IOMUXC_DDR_RBASE + (4 * 8))) +#define IOMUXC_DPCR_DDR_DQ9 ((IOMUXC_DDR_RBASE + (4 * 9))) +#define IOMUXC_DPCR_DDR_DQ10 ((IOMUXC_DDR_RBASE + (4 * 10))) +#define IOMUXC_DPCR_DDR_DQ11 ((IOMUXC_DDR_RBASE + (4 * 11))) +#define IOMUXC_DPCR_DDR_DQ12 ((IOMUXC_DDR_RBASE + (4 * 12))) +#define IOMUXC_DPCR_DDR_DQ13 ((IOMUXC_DDR_RBASE + (4 * 13))) +#define IOMUXC_DPCR_DDR_DQ14 ((IOMUXC_DDR_RBASE + (4 * 14))) +#define IOMUXC_DPCR_DDR_DQ15 ((IOMUXC_DDR_RBASE + (4 * 15))) +#define IOMUXC_DPCR_DDR_DQ16 ((IOMUXC_DDR_RBASE + (4 * 16))) +#define IOMUXC_DPCR_DDR_DQ17 ((IOMUXC_DDR_RBASE + (4 * 17))) +#define IOMUXC_DPCR_DDR_DQ18 ((IOMUXC_DDR_RBASE + (4 * 18))) +#define IOMUXC_DPCR_DDR_DQ19 ((IOMUXC_DDR_RBASE + (4 * 19))) +#define IOMUXC_DPCR_DDR_DQ20 ((IOMUXC_DDR_RBASE + (4 * 20))) +#define IOMUXC_DPCR_DDR_DQ21 ((IOMUXC_DDR_RBASE + (4 * 21))) +#define IOMUXC_DPCR_DDR_DQ22 ((IOMUXC_DDR_RBASE + (4 * 22))) +#define IOMUXC_DPCR_DDR_DQ23 ((IOMUXC_DDR_RBASE + (4 * 23))) +#define IOMUXC_DPCR_DDR_DQ24 ((IOMUXC_DDR_RBASE + (4 * 24))) +#define IOMUXC_DPCR_DDR_DQ25 ((IOMUXC_DDR_RBASE + (4 * 25))) +#define IOMUXC_DPCR_DDR_DQ26 ((IOMUXC_DDR_RBASE + (4 * 26))) +#define IOMUXC_DPCR_DDR_DQ27 ((IOMUXC_DDR_RBASE + (4 * 27))) +#define IOMUXC_DPCR_DDR_DQ28 ((IOMUXC_DDR_RBASE + (4 * 28))) +#define IOMUXC_DPCR_DDR_DQ29 ((IOMUXC_DDR_RBASE + (4 * 29))) +#define IOMUXC_DPCR_DDR_DQ30 ((IOMUXC_DDR_RBASE + (4 * 30))) +#define IOMUXC_DPCR_DDR_DQ31 ((IOMUXC_DDR_RBASE + (4 * 31))) + +/* Remap the rgpio2p registers addr to driver's addr */ +#define RGPIO2P_GPIO1_BASE_ADDR RGPIO2P0_RBASE +#define RGPIO2P_GPIO2_BASE_ADDR (RGPIO2P0_RBASE + 0x40) +#define RGPIO2P_GPIO3_BASE_ADDR (RGPIO2P1_RBASE) +#define RGPIO2P_GPIO4_BASE_ADDR (RGPIO2P1_RBASE + 0x40) +#define RGPIO2P_GPIO5_BASE_ADDR (RGPIO2P1_RBASE + 0x80) +#define RGPIO2P_GPIO6_BASE_ADDR (RGPIO2P1_RBASE + 0xc0) + +/* MMDC registers addresses */ +#define MMDC_MDCTL_OFFSET (0x000) +#define MMDC_MDPDC_OFFSET (0x004) +#define MMDC_MDOTC_OFFSET (0x008) +#define MMDC_MDCFG0_OFFSET (0x00C) +#define MMDC_MDCFG1_OFFSET (0x010) +#define MMDC_MDCFG2_OFFSET (0x014) +#define MMDC_MDMISC_OFFSET (0x018) +#define MMDC_MDSCR_OFFSET (0x01C) +#define MMDC_MDREF_OFFSET (0x020) +#define MMDC_MDRWD_OFFSET (0x02C) +#define MMDC_MDOR_OFFSET (0x030) +#define MMDC_MDMRR_OFFSET (0x034) +#define MMDC_MDCFG3LP_OFFSET (0x038) +#define MMDC_MDMR4_OFFSET (0x03C) +#define MMDC_MDASP_OFFSET (0x040) + +#define MMDC_MAARCR_OFFSET (0x400) +#define MMDC_MAPSR_OFFSET (0x404) +#define MMDC_MAEXIDR0_OFFSET (0x408) +#define MMDC_MAEXIDR1_OFFSET (0x40C) +#define MMDC_MADPCR0_OFFSET (0x410) +#define MMDC_MADPCR1_OFFSET (0x414) +#define MMDC_MADPSR0_OFFSET (0x418) +#define MMDC_MADPSR1_OFFSET (0x41C) +#define MMDC_MADPSR2_OFFSET (0x420) +#define MMDC_MADPSR3_OFFSET (0x424) +#define MMDC_MADPSR4_OFFSET (0x428) +#define MMDC_MADPSR5_OFFSET (0x42C) +#define MMDC_MASBS0_OFFSET (0x430) +#define MMDC_MASBS1_OFFSET (0x434) +#define MMDC_MAGENP_OFFSET (0x440) + +#define MMDC_MPZQHWCTRL_OFFSET (0x800) +#define MMDC_MPZQSWCTRL_OFFSET (0x804) +#define MMDC_MPWLGCR_OFFSET (0x808) +#define MMDC_MPWLDECTRL0_OFFSET (0x80C) +#define MMDC_MPWLDECTRL1_OFFSET (0x810) +#define MMDC_MPWLDLST_OFFSET (0x814) +#define MMDC_MPODTCTRL_OFFSET (0x818) +#define MMDC_MPREDQBY0DL_OFFSET (0x81C) +#define MMDC_MPREDQBY1DL_OFFSET (0x820) +#define MMDC_MPREDQBY2DL_OFFSET (0x824) +#define MMDC_MPREDQBY3DL_OFFSET (0x828) +#define MMDC_MPWRDQBY0DL_OFFSET (0x82C) +#define MMDC_MPWRDQBY1DL_OFFSET (0x830) +#define MMDC_MPWRDQBY2DL_OFFSET (0x834) +#define MMDC_MPWRDQBY3DL_OFFSET (0x838) +#define MMDC_MPDGCTRL0_OFFSET (0x83C) +#define MMDC_MPDGCTRL1_OFFSET (0x840) +#define MMDC_MPDGDLST_OFFSET (0x844) +#define MMDC_MPRDDLCTL_OFFSET (0x848) +#define MMDC_MPRDDLST_OFFSET (0x84C) +#define MMDC_MPWRDLCTL_OFFSET (0x850) +#define MMDC_MPWRDLST_OFFSET (0x854) +#define MMDC_MPSDCTRL_OFFSET (0x858) +#define MMDC_MPZQLP2CTL_OFFSET (0x85C) +#define MMDC_MPRDDLHWCTL_OFFSET (0x860) +#define MMDC_MPWRDLHWCTL_OFFSET (0x864) +#define MMDC_MPRDDLHWST0_OFFSET (0x868) +#define MMDC_MPRDDLHWST1_OFFSET (0x86C) +#define MMDC_MPWRDLHWST0_OFFSET (0x870) +#define MMDC_MPWRDLHWST1_OFFSET (0x874) +#define MMDC_MPWLHWERR_OFFSET (0x878) +#define MMDC_MPDGHWST0_OFFSET (0x87C) +#define MMDC_MPDGHWST1_OFFSET (0x880) +#define MMDC_MPDGHWST2_OFFSET (0x884) +#define MMDC_MPDGHWST3_OFFSET (0x888) +#define MMDC_MPPDCMPR1_OFFSET (0x88C) +#define MMDC_MPPDCMPR2_OFFSET (0x890) +#define MMDC_MPSWDAR_OFFSET (0x894) +#define MMDC_MPSWDRDR0_OFFSET (0x898) +#define MMDC_MPSWDRDR1_OFFSET (0x89C) +#define MMDC_MPSWDRDR2_OFFSET (0x8A0) +#define MMDC_MPSWDRDR3_OFFSET (0x8A4) +#define MMDC_MPSWDRDR4_OFFSET (0x8A8) +#define MMDC_MPSWDRDR5_OFFSET (0x8AC) +#define MMDC_MPSWDRDR6_OFFSET (0x8B0) +#define MMDC_MPSWDRDR7_OFFSET (0x8B4) +#define MMDC_MPMUR_OFFSET (0x8B8) +#define MMDC_MPWRCADL_OFFSET (0x8BC) +#define MMDC_MPDCCR_OFFSET (0x8C0) +#define MMDC_MPBC_OFFSET (0x8C4) +#define MMDC_MPSWDRAR_OFFSET (0x8C8) + +/* First MMDC invalid IPS address */ +#define MMDC_IPS_ILL_ADDR_START_OFFSET (0x8CC) +#define MMDC_REGS_BASE MMDC0_RBASE + +#define MMDC_MDCTL ((MMDC_REGS_BASE + MMDC_MDCTL_OFFSET)) +#define MMDC_MDPDC ((MMDC_REGS_BASE + MMDC_MDPDC_OFFSET)) +#define MMDC_MDOTC ((MMDC_REGS_BASE + MMDC_MDOTC_OFFSET)) +#define MMDC_MDCFG0 ((MMDC_REGS_BASE + MMDC_MDCFG0_OFFSET)) +#define MMDC_MDCFG1 ((MMDC_REGS_BASE + MMDC_MDCFG1_OFFSET)) +#define MMDC_MDCFG2 ((MMDC_REGS_BASE + MMDC_MDCFG2_OFFSET)) +#define MMDC_MDMISC ((MMDC_REGS_BASE + MMDC_MDMISC_OFFSET)) +#define MMDC_MDSCR ((MMDC_REGS_BASE + MMDC_MDSCR_OFFSET)) +#define MMDC_MDREF ((MMDC_REGS_BASE + MMDC_MDREF_OFFSET)) +#define MMDC_MDRWD ((MMDC_REGS_BASE + MMDC_MDRWD_OFFSET)) +#define MMDC_MDOR ((MMDC_REGS_BASE + MMDC_MDOR_OFFSET)) +#define MMDC_MDMRR ((MMDC_REGS_BASE + MMDC_MDMRR_OFFSET)) +#define MMDC_MDCFG3LP ((MMDC_REGS_BASE + MMDC_MDCFG3LP_OFFSET)) +#define MMDC_MDMR4 ((MMDC_REGS_BASE + MMDC_MDMR4_OFFSET)) +#define MMDC_MDASP ((MMDC_REGS_BASE + MMDC_MDASP_OFFSET)) + +#define MMDC_MAARCR ((MMDC_REGS_BASE + MMDC_MAARCR_OFFSET)) +#define MMDC_MAPSR ((MMDC_REGS_BASE + MMDC_MAPSR_OFFSET)) +#define MMDC_MAEXIDR0 ((MMDC_REGS_BASE + MMDC_MAEXIDR0_OFFSET)) +#define MMDC_MAEXIDR1 ((MMDC_REGS_BASE + MMDC_MAEXIDR1_OFFSET)) +#define MMDC_MADPCR0 ((MMDC_REGS_BASE + MMDC_MADPCR0_OFFSET)) +#define MMDC_MADPCR1 ((MMDC_REGS_BASE + MMDC_MADPCR1_OFFSET)) +#define MMDC_MADPSR0 ((MMDC_REGS_BASE + MMDC_MADPSR0_OFFSET)) +#define MMDC_MADPSR1 ((MMDC_REGS_BASE + MMDC_MADPSR1_OFFSET)) +#define MMDC_MADPSR2 ((MMDC_REGS_BASE + MMDC_MADPSR2_OFFSET)) +#define MMDC_MADPSR3 ((MMDC_REGS_BASE + MMDC_MADPSR3_OFFSET)) +#define MMDC_MADPSR4 ((MMDC_REGS_BASE + MMDC_MADPSR4_OFFSET)) +#define MMDC_MADPSR5 ((MMDC_REGS_BASE + MMDC_MADPSR5_OFFSET)) +#define MMDC_MASBS0 ((MMDC_REGS_BASE + MMDC_MASBS0_OFFSET)) +#define MMDC_MASBS1 ((MMDC_REGS_BASE + MMDC_MASBS1_OFFSET)) +#define MMDC_MAGENP ((MMDC_REGS_BASE + MMDC_MAGENP_OFFSET)) + +#define MMDC_MPZQHWCTRL ((MMDC_REGS_BASE + MMDC_MPZQHWCTRL_OFFSET)) +#define MMDC_MPZQSWCTRL ((MMDC_REGS_BASE + MMDC_MPZQSWCTRL_OFFSET)) +#define MMDC_MPWLGCR ((MMDC_REGS_BASE + MMDC_MPWLGCR_OFFSET)) +#define MMDC_MPWLDECTRL0 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL0_OFFSET)) +#define MMDC_MPWLDECTRL1 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL1_OFFSET)) +#define MMDC_MPWLDLST ((MMDC_REGS_BASE + MMDC_MPWLDLST_OFFSET)) +#define MMDC_MPODTCTRL ((MMDC_REGS_BASE + MMDC_MPODTCTRL_OFFSET)) +#define MMDC_MPREDQBY0DL ((MMDC_REGS_BASE + MMDC_MPREDQBY0DL_OFFSET)) +#define MMDC_MPREDQBY1DL ((MMDC_REGS_BASE + MMDC_MPREDQBY1DL_OFFSET)) +#define MMDC_MPREDQBY2DL ((MMDC_REGS_BASE + MMDC_MPREDQBY2DL_OFFSET)) +#define MMDC_MPREDQBY3DL ((MMDC_REGS_BASE + MMDC_MPREDQBY3DL_OFFSET)) +#define MMDC_MPWRDQBY0DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY0DL_OFFSET)) +#define MMDC_MPWRDQBY1DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY1DL_OFFSET)) +#define MMDC_MPWRDQBY2DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY2DL_OFFSET)) +#define MMDC_MPWRDQBY3DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY3DL_OFFSET)) +#define MMDC_MPDGCTRL0 ((MMDC_REGS_BASE + MMDC_MPDGCTRL0_OFFSET)) +#define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) +#define MMDC_MPDGDLST ((MMDC_REGS_BASE + MMDC_MPDGDLST_OFFSET)) +#define MMDC_MPRDDLCTL ((MMDC_REGS_BASE + MMDC_MPRDDLCTL_OFFSET)) +#define MMDC_MPRDDLST ((MMDC_REGS_BASE + MMDC_MPRDDLST_OFFSET)) +#define MMDC_MPWRDLCTL ((MMDC_REGS_BASE + MMDC_MPWRDLCTL_OFFSET)) +#define MMDC_MPWRDLST ((MMDC_REGS_BASE + MMDC_MPWRDLST_OFFSET)) +#define MMDC_MPSDCTRL ((MMDC_REGS_BASE + MMDC_MPSDCTRL_OFFSET)) +#define MMDC_MPZQLP2CTL ((MMDC_REGS_BASE + MMDC_MPZQLP2CTL_OFFSET)) +#define MMDC_MPRDDLHWCTL ((MMDC_REGS_BASE + MMDC_MPRDDLHWCTL_OFFSET)) +#define MMDC_MPWRDLHWCTL ((MMDC_REGS_BASE + MMDC_MPWRDLHWCTL_OFFSET)) +#define MMDC_MPRDDLHWST0 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST0_OFFSET)) +#define MMDC_MPRDDLHWST1 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST1_OFFSET)) +#define MMDC_MPWRDLHWST0 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST0_OFFSET)) +#define MMDC_MPWRDLHWST1 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST1_OFFSET)) +#define MMDC_MPWLHWERR ((MMDC_REGS_BASE + MMDC_MPWLHWERR_OFFSET)) +#define MMDC_MPDGHWST0 ((MMDC_REGS_BASE + MMDC_MPDGHWST0_OFFSET)) +#define MMDC_MPDGHWST1 ((MMDC_REGS_BASE + MMDC_MPDGHWST1_OFFSET)) +#define MMDC_MPDGHWST2 ((MMDC_REGS_BASE + MMDC_MPDGHWST2_OFFSET)) +#define MMDC_MPDGHWST3 ((MMDC_REGS_BASE + MMDC_MPDGHWST3_OFFSET)) +#define MMDC_MPPDCMPR1 ((MMDC_REGS_BASE + MMDC_MPPDCMPR1_OFFSET)) +#define MMDC_MPPDCMPR2 ((MMDC_REGS_BASE + MMDC_MPPDCMPR2_OFFSET)) +#define MMDC_MPSWDAR ((MMDC_REGS_BASE + MMDC_MPSWDAR_OFFSET)) +#define MMDC_MPSWDRDR0 ((MMDC_REGS_BASE + MMDC_MPSWDRDR0_OFFSET)) +#define MMDC_MPSWDRDR1 ((MMDC_REGS_BASE + MMDC_MPSWDRDR1_OFFSET)) +#define MMDC_MPSWDRDR2 ((MMDC_REGS_BASE + MMDC_MPSWDRDR2_OFFSET)) +#define MMDC_MPSWDRDR3 ((MMDC_REGS_BASE + MMDC_MPSWDRDR3_OFFSET)) +#define MMDC_MPSWDRDR4 ((MMDC_REGS_BASE + MMDC_MPSWDRDR4_OFFSET)) +#define MMDC_MPSWDRDR5 ((MMDC_REGS_BASE + MMDC_MPSWDRDR5_OFFSET)) +#define MMDC_MPSWDRDR6 ((MMDC_REGS_BASE + MMDC_MPSWDRDR6_OFFSET)) +#define MMDC_MPSWDRDR7 ((MMDC_REGS_BASE + MMDC_MPSWDRDR7_OFFSET)) +#define MMDC_MPMUR ((MMDC_REGS_BASE + MMDC_MPMUR_OFFSET)) +#define MMDC_MPWRCADL ((MMDC_REGS_BASE + MMDC_MPWRCADL_OFFSET)) +#define MMDC_MPDCCR ((MMDC_REGS_BASE + MMDC_MPDCCR_OFFSET)) +#define MMDC_MPBC ((MMDC_REGS_BASE + MMDC_MPBC_OFFSET)) +#define MMDC_MPSWDRAR ((MMDC_REGS_BASE + MMDC_MPSWDRAR_OFFSET)) + +/* MMDC registers bit defines */ +#define MMDC_MDCTL_SDE_0 (31) +#define MMDC_MDCTL_SDE_1 (30) +#define MMDC_MDCTL_ROW (24) +#define MMDC_MDCTL_COL (20) +#define MMDC_MDCTL_BL (19) +#define MMDC_MDCTL_DSIZ (16) + +/* MDMISC */ +#define MMDC_MDMISC_CS0_RDY (31) +#define MMDC_MDMISC_CS1_RDY (30) +#define MMDC_MDMISC_CK1_DEL (22) +#define MMDC_MDMISC_CK1_GATING (21) +#define MMDC_MDMISC_CALIB_PER_CS (20) +#define MMDC_MDMISC_ADDR_MIRROR (19) +#define MMDC_MDMISC_LHD (18) +#define MMDC_MDMISC_WALAT (16) +#define MMDC_MDMISC_BI (12) +#define MMDC_MDMISC_LPDDR2_S (11) +#define MMDC_MDMISC_MIF3_MODE (9) +#define MMDC_MDMISC_RALAT (6) +#define MMDC_MDMISC_DDR_4_BANK (5) +#define MMDC_MDMISC_DDR_TYPE (3) +#define MMDC_MDMISC_RST (1) + +/* MPWLGCR */ +#define MMDC_MPWLGCR_WL_HW_ERR (8) + +/* MDSCR */ +#define MMDC_MDSCR_CMD_ADDR_MSB (24) +#define MMDC_MDSCR_MR_OP (24) +#define MMDC_MDSCR_CMD_ADDR_LSB (16) +#define MMDC_MDSCR_MR_ADDR (16) +#define MMDC_MDSCR_CON_REQ (15) +#define MMDC_MDSCR_CON_ACK (14) +#define MMDC_MDSCR_MRR_READ_DATA_VALID (10) +#define MMDC_MDSCR_WL_EN (9) +#define MMDC_MDSCR_CMD (4) +#define MMDC_MDSCR_CMD_CS (3) +#define MMDC_MDSCR_CMD_BA (0) + +/* MPZQHWCTRL */ +#define MMDC_MPZQHWCTRL_ZQ_HW_FOR (16) +#define MMDC_MPZQHWCTRL_ZQ_MODE (0) + +/* MPZQSWCTRL */ +#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP (16) +#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL (13) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD (12) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL (7) +#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL (2) +#define MMDC_MPZQSWCTRL_ZQ_SW_RES (1) +#define MMDC_MPZQSWCTRL_ZQ_SW_FOR (0) + +/* MPDGCTRL0 */ +#define MMDC_MPDGCTRL0_RST_RD_FIFO (31) +#define MMDC_MPDGCTRL0_DG_CMP_CYC (30) +#define MMDC_MPDGCTRL0_DG_DIS (29) +#define MMDC_MPDGCTRL0_HW_DG_EN (28) +#define MMDC_MPDGCTRL0_HW_DG_ERR (12) + +/* MPRDDLHWCTL */ +#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC (5) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN (4) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR (0) + +/* MPWRDLHWCTL */ +#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC (5) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN (4) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR (0) + +/* MPSWDAR */ +#define MMDC_MPSWDAR_TEST_DUMMY_EN (6) +#define MMDC_MPSWDAR_SW_DUM_CMP3 (5) +#define MMDC_MPSWDAR_SW_DUM_CMP2 (4) +#define MMDC_MPSWDAR_SW_DUM_CMP1 (3) +#define MMDC_MPSWDAR_SW_DUM_CMP0 (2) +#define MMDC_MPSWDAR_SW_DUMMY_RD (1) +#define MMDC_MPSWDAR_SW_DUMMY_WR (0) + +/* MADPCR0 */ +#define MMDC_MADPCR0_SBS (9) +#define MMDC_MADPCR0_SBS_EN (8) + +/* MASBS1 */ +#define MMDC_MASBS1_SBS_VLD (0) +#define MMDC_MASBS1_SBS_TYPE (1) + +/* MDREF */ +#define MMDC_MDREF_REF_CNT (16) +#define MMDC_MDREF_REF_SEL (14) +#define MMDC_MDREF_REFR (11) +#define MMDC_MDREF_START_REF (0) + +/* MPWLGCR */ +#define MMDC_MPWLGCR_HW_WL_EN (0) + +/* MPBC */ +#define MMDC_MPBC_BIST_DM_LP_EN (0) +#define MMDC_MPBC_BIST_CA0_LP_EN (1) +#define MMDC_MPBC_BIST_DQ0_LP_EN (3) +#define MMDC_MPBC_BIST_DQ1_LP_EN (4) +#define MMDC_MPBC_BIST_DQ2_LP_EN (5) +#define MMDC_MPBC_BIST_DQ3_LP_EN (6) + +/* MPMUR */ +#define MMDC_MPMUR_FRC_MSR (11) + +/* MPODTCTRL */ +#define MMDC_MPODTCTRL_ODT_RD_ACT_EN (3) +#define MMDC_MPODTCTRL_ODT_RD_PAS_EN (2) +#define MMDC_MPODTCTRL_ODT_WR_ACT_EN (1) +#define MMDC_MPODTCTRL_ODT_WR_PAS_EN (0) + +/* MAPSR */ +#define MMDC_MAPSR_DVACK (25) +#define MMDC_MAPSR_LPACK (24) +#define MMDC_MAPSR_DVFS (21) +#define MMDC_MAPSR_LPMD (20) + +/* MAARCR */ +#define MMDC_MAARCR_ARCR_EXC_ERR_EN (28) + +/* MPZQLP2CTL */ +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS (24) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL (16) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT (0) + +/* MDCFG3LP */ +#define MMDC_MDCFG3LP_tRC_LP (16) +#define MMDC_MDCFG3LP_tRCD_LP (8) +#define MMDC_MDCFG3LP_tRPpb_LP (4) +#define MMDC_MDCFG3LP_tRPab_LP (0) + +/* MDOR */ +#define MMDC_MDOR_tXPR (16) +#define MMDC_MDOR_SDE_to_RST (8) +#define MMDC_MDOR_RST_to_CKE (0) + +/* MDCFG0 */ +#define MMDC_MDCFG0_tRFC (24) +#define MMDC_MDCFG0_tXS (16) +#define MMDC_MDCFG0_tXP (13) +#define MMDC_MDCFG0_tXPDLL (9) +#define MMDC_MDCFG0_tFAW (4) +#define MMDC_MDCFG0_tCL (0) + +/* MDCFG1 */ +#define MMDC_MDCFG1_tRCD (29) +#define MMDC_MDCFG1_tRP (26) +#define MMDC_MDCFG1_tRC (21) +#define MMDC_MDCFG1_tRAS (16) +#define MMDC_MDCFG1_tRPA (15) +#define MMDC_MDCFG1_tWR (9) +#define MMDC_MDCFG1_tMRD (5) +#define MMDC_MDCFG1_tCWL (0) + +/* MDCFG2 */ +#define MMDC_MDCFG2_tDLLK (16) +#define MMDC_MDCFG2_tRTP (6) +#define MMDC_MDCFG2_tWTR (3) +#define MMDC_MDCFG2_tRRD (0) + +/* MDRWD */ +#define MMDC_MDRWD_tDAI (16) +#define MMDC_MDRWD_RTW_SAME (12) +#define MMDC_MDRWD_WTR_DIFF (9) +#define MMDC_MDRWD_WTW_DIFF (6) +#define MMDC_MDRWD_RTW_DIFF (3) +#define MMDC_MDRWD_RTR_DIFF (0) + +/* MDPDC */ +#define MMDC_MDPDC_PRCT_1 (28) +#define MMDC_MDPDC_PRCT_0 (24) +#define MMDC_MDPDC_tCKE (16) +#define MMDC_MDPDC_PWDT_1 (12) +#define MMDC_MDPDC_PWDT_0 (8) +#define MMDC_MDPDC_SLOW_PD (7) +#define MMDC_MDPDC_BOTH_CS_PD (6) +#define MMDC_MDPDC_tCKSRX (3) +#define MMDC_MDPDC_tCKSRE (0) + +/* MDASP */ +#define MMDC_MDASP_CS0_END (0) + +/* MAEXIDR0 */ +#define MMDC_MAEXIDR0_EXC_ID_MONITOR1 (16) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR0 (0) + +/* MAEXIDR1 */ +#define MMDC_MAEXIDR1_EXC_ID_MONITOR3 (16) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR2 (0) + +/* MPWRDLCTL */ +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3 (24) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2 (16) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1 (8) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0 (0) + +/* MPRDDLCTL */ +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3 (24) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2 (16) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1 (8) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0 (0) + +/* MPWRDQBY0DL */ +#define MMDC_MPWRDQBY0DL_WR_DM0_DEL (30) +#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL (28) +#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL (24) +#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL (20) +#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL (16) +#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL (12) +#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL (8) +#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL (4) +#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL (0) + +/* MPWRDQBY1DL */ +#define MMDC_MPWRDQBY1DL_WR_DM1_DEL (30) +#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL (28) +#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL (24) +#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL (20) +#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL (16) +#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL (12) +#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL (8) +#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL (4) +#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL (0) + +/* MPWRDQBY2DL */ +#define MMDC_MPWRDQBY2DL_WR_DM2_DEL (30) +#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL (28) +#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL (24) +#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL (20) +#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL (16) +#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL (12) +#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL (8) +#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL (4) +#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL (0) + +/* MPWRDQBY3DL */ +#define MMDC_MPWRDQBY3DL_WR_DM3_DEL (30) +#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL (28) +#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL (24) +#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL (20) +#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL (16) +#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL (12) +#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL (8) +#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL (4) +#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL (0) + +/* Fields masks */ +#define MMDC_MDCTL_SDE_0_MASK ((0x1 << MMDC_MDCTL_SDE_0)) +#define MMDC_MDCTL_SDE_1_MASK ((0x1 << MMDC_MDCTL_SDE_1)) +#define MMDC_MDCTL_BL_MASK ((0x1 << MMDC_MDCTL_BL)) +#define MMDC_MDCTL_ROW_MASK ((0x7 << MMDC_MDCTL_ROW)) +#define MMDC_MDCTL_COL_MASK ((0x7 << MMDC_MDCTL_COL)) +#define MMDC_MDCTL_DSIZ_MASK ((0x3 << MMDC_MDCTL_DSIZ)) + +/* MDMISC */ +#define MMDC_MDMISC_CS0_RDY_MASK ((0x1 << MMDC_MDMISC_CS0_RDY)) +#define MMDC_MDMISC_CS1_RDY_MASK ((0x1 << MMDC_MDMISC_CS1_RDY)) +#define MMDC_MDMISC_CK1_DEL_MASK ((0x3 << MMDC_MDMISC_CK1_DEL)) +#define MMDC_MDMISC_CK1_GATING_MASK ((0x1 << MMDC_MDMISC_CK1_GATING)) +#define MMDC_MDMISC_CALIB_PER_CS_MASK ((0x1 << MMDC_MDMISC_CALIB_PER_CS)) +#define MMDC_MDMISC_ADDR_MIRROR_MASK ((0x1 << MMDC_MDMISC_ADDR_MIRROR)) +#define MMDC_MDMISC_LHD_MASK ((0x1 << MMDC_MDMISC_LHD)) +#define MMDC_MDMISC_WALAT_MASK ((0x3 << MMDC_MDMISC_WALAT)) +#define MMDC_MDMISC_BI_MASK ((0x1 << MMDC_MDMISC_BI)) +#define MMDC_MDMISC_LPDDR2_S_MASK ((0x1 << MMDC_MDMISC_LPDDR2_S)) +#define MMDC_MDMISC_MIF3_MODE_MASK ((0x3 << MMDC_MDMISC_MIF3_MODE)) +#define MMDC_MDMISC_RALAT_MASK ((0x7 << MMDC_MDMISC_RALAT)) +#define MMDC_MDMISC_DDR_4_BANK_MASK ((0x1 << MMDC_MDMISC_DDR_4_BANK)) +#define MMDC_MDMISC_DDR_TYPE_MASK ((0x3 << MMDC_MDMISC_DDR_TYPE)) +#define MMDC_MDMISC_RST_MASK ((0x1 << MMDC_MDMISC_RST)) + +/* MPWLGCR */ +#define MMDC_MPWLGCR_WL_HW_ERR_MASK ((0xf << MMDC_MPWLGCR_WL_HW_ERR)) + +/* MDSCR */ +#define MMDC_MDSCR_CMD_ADDR_MSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_MSB)) +#define MMDC_MDSCR_MR_OP_MASK ((0xff << MMDC_MDSCR_MR_OP)) +#define MMDC_MDSCR_CMD_ADDR_LSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_LSB)) +#define MMDC_MDSCR_MR_ADDR_MASK ((0xff << MMDC_MDSCR_MR_ADDR)) +#define MMDC_MDSCR_CON_REQ_MASK ((0x1 << MMDC_MDSCR_CON_REQ)) +#define MMDC_MDSCR_CON_ACK_MASK ((0x1 << MMDC_MDSCR_CON_ACK)) +#define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK ((0x1 << MMDC_MDSCR_MRR_READ_DATA_VALID)) +#define MMDC_MDSCR_WL_EN_MASK ((0x1 << MMDC_MDSCR_WL_EN)) +#define MMDC_MDSCR_CMD_MASK ((0x7 << MMDC_MDSCR_CMD)) +#define MMDC_MDSCR_CMD_CS_MASK ((0x1 << MMDC_MDSCR_CMD_CS)) +#define MMDC_MDSCR_CMD_BA_MASK ((0x7 << MMDC_MDSCR_CMD_BA)) + +/* MPZQHWCTRL */ +#define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK ((0x1 << MMDC_MPZQHWCTRL_ZQ_HW_FOR)) +#define MMDC_MPZQHWCTRL_ZQ_MODE_MASK ((0x3 << MMDC_MPZQHWCTRL_ZQ_MODE)) + +/* MPZQSWCTRL */ +#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK ((0x3 << MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP)) +#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK ((0x1 << MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL)) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_PD)) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL)) +#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL)) +#define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_RES)) +#define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_FOR)) + +/* MPDGCTRL0 */ +#define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK ((0x1 << MMDC_MPDGCTRL0_RST_RD_FIFO)) +#define MMDC_MPDGCTRL0_DG_CMP_CYC_MASK ((0x1 << MMDC_MPDGCTRL0_DG_CMP_CYC)) +#define MMDC_MPDGCTRL0_DG_DIS_MASK ((0x1 << MMDC_MPDGCTRL0_DG_DIS)) +#define MMDC_MPDGCTRL0_HW_DG_EN_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_EN)) +#define MMDC_MPDGCTRL0_HW_DG_ERR_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_ERR)) + +/* MPRDDLHWCTL */ +#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC)) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_EN)) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR_MASK ((0xf << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR)) + +/* MPWRDLHWCTL */ +#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC)) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_EN)) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR_MASK ((0xf << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR)) + +/* MPSWDAR */ +#define MMDC_MPSWDAR_TEST_DUMMY_EN_MASK ((0x1 << MMDC_MPSWDAR_TEST_DUMMY_EN)) +#define MMDC_MPSWDAR_SW_DUM_CMP3_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP3)) +#define MMDC_MPSWDAR_SW_DUM_CMP2_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP2)) +#define MMDC_MPSWDAR_SW_DUM_CMP1_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP1)) +#define MMDC_MPSWDAR_SW_DUM_CMP0_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP0)) +#define MMDC_MPSWDAR_SW_DUMMY_RD_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_RD)) +#define MMDC_MPSWDAR_SW_DUMMY_WR_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_WR)) + +/* MADPCR0 */ +#define MMDC_MADPCR0_SBS_MASK ((0x1 << MMDC_MADPCR0_SBS)) +#define MMDC_MADPCR0_SBS_EN_MASK ((0x1 << MMDC_MADPCR0_SBS_EN)) + +/* MASBS1 */ +#define MMDC_MASBS1_SBS_VLD_MASK ((0x1 << MMDC_MASBS1_SBS_VLD)) +#define MMDC_MASBS1_SBS_TYPE_MASK ((0x1 << MMDC_MASBS1_SBS_TYPE)) + +/* MDREF */ +#define MMDC_MDREF_REF_CNT_MASK ((0xffff << MMDC_MDREF_REF_CNT)) +#define MMDC_MDREF_REF_SEL_MASK ((0x3 << MMDC_MDREF_REF_SEL)) +#define MMDC_MDREF_REFR_MASK ((0x7 << MMDC_MDREF_REFR)) +#define MMDC_MDREF_START_REF_MASK ((0x1 << MMDC_MDREF_START_REF)) + +/* MPWLGCR */ +#define MMDC_MPWLGCR_HW_WL_EN_MASK ((0x1 << MMDC_MPWLGCR_HW_WL_EN)) + +/* MPBC */ +#define MMDC_MPBC_BIST_DM_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DM_LP_EN)) +#define MMDC_MPBC_BIST_CA0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_CA0_LP_EN)) +#define MMDC_MPBC_BIST_DQ0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ0_LP_EN)) +#define MMDC_MPBC_BIST_DQ1_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ1_LP_EN)) +#define MMDC_MPBC_BIST_DQ2_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ2_LP_EN)) +#define MMDC_MPBC_BIST_DQ3_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ3_LP_EN)) +#define MMDC_MPBC_BIST_DQ_LP_EN_MASK ((0xf << MMDC_MPBC_BIST_DQ0_LP_EN)) + +/* MPMUR */ +#define MMDC_MPMUR_FRC_MSR_MASK ((0x1 << MMDC_MPMUR_FRC_MSR)) + +/* MPODTCTRL */ +#define MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_ACT_EN)) +#define MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_PAS_EN)) +#define MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_ACT_EN)) +#define MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_PAS_EN)) + +/* MAPSR */ +#define MMDC_MAPSR_DVACK_MASK ((0x1 << MMDC_MAPSR_DVACK)) +#define MMDC_MAPSR_LPACK_MASK ((0x1 << MMDC_MAPSR_LPACK)) +#define MMDC_MAPSR_DVFS_MASK ((0x1 << MMDC_MAPSR_DVFS)) +#define MMDC_MAPSR_LPMD_MASK ((0x1 << MMDC_MAPSR_LPMD)) + +/* MAARCR */ +#define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK ((0x1 << MMDC_MAARCR_ARCR_EXC_ERR_EN)) + +/* MPZQLP2CTL */ +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK ((0x7f << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS)) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK ((0xff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL)) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK ((0x1ff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT)) + +/* MDCFG3LP */ +#define MMDC_MDCFG3LP_tRC_LP_MASK ((0x3f << MMDC_MDCFG3LP_tRC_LP)) +#define MMDC_MDCFG3LP_tRCD_LP_MASK ((0xf << MMDC_MDCFG3LP_tRCD_LP)) +#define MMDC_MDCFG3LP_tRPpb_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPpb_LP)) +#define MMDC_MDCFG3LP_tRPab_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPab_LP)) + +/* MDOR */ +#define MMDC_MDOR_tXPR_MASK ((0xff << MMDC_MDOR_tXPR)) +#define MMDC_MDOR_SDE_to_RST_MASK ((0x3f << MMDC_MDOR_SDE_to_RST)) +#define MMDC_MDOR_RST_to_CKE_MASK ((0x3f << MMDC_MDOR_RST_to_CKE)) + +/* MDCFG0 */ +#define MMDC_MDCFG0_tRFC_MASK ((0xff << MMDC_MDCFG0_tRFC)) +#define MMDC_MDCFG0_tXS_MASK ((0xff << MMDC_MDCFG0_tXS)) +#define MMDC_MDCFG0_tXP_MASK ((0x7 << MMDC_MDCFG0_tXP)) +#define MMDC_MDCFG0_tXPDLL_MASK ((0xf << MMDC_MDCFG0_tXPDLL)) +#define MMDC_MDCFG0_tFAW_MASK ((0x1f << MMDC_MDCFG0_tFAW)) +#define MMDC_MDCFG0_tCL_MASK ((0xf << MMDC_MDCFG0_tCL)) + +/* MDCFG1 */ +#define MMDC_MDCFG1_tRCD_MASK ((0x7 << MMDC_MDCFG1_tRCD)) +#define MMDC_MDCFG1_tRP_MASK ((0x7 << MMDC_MDCFG1_tRP)) +#define MMDC_MDCFG1_tRC_MASK ((0x1f << MMDC_MDCFG1_tRC)) +#define MMDC_MDCFG1_tRAS_MASK ((0x1f << MMDC_MDCFG1_tRAS)) +#define MMDC_MDCFG1_tRPA_MASK ((0x1 << MMDC_MDCFG1_tRPA)) +#define MMDC_MDCFG1_tWR_MASK ((0x7 << MMDC_MDCFG1_tWR)) +#define MMDC_MDCFG1_tMRD_MASK ((0xf << MMDC_MDCFG1_tMRD)) +#define MMDC_MDCFG1_tCWL_MASK ((0x7 << MMDC_MDCFG1_tCWL)) + +/* MDCFG2 */ +#define MMDC_MDCFG2_tDLLK_MASK ((0x1ff << MMDC_MDCFG2_tDLLK)) +#define MMDC_MDCFG2_tRTP_MASK ((0x7 << MMDC_MDCFG2_tRTP)) +#define MMDC_MDCFG2_tWTR_MASK ((0x7 << MMDC_MDCFG2_tWTR)) +#define MMDC_MDCFG2_tRRD_MASK ((0x7 << MMDC_MDCFG2_tRRD)) + +/* MDRWD */ +#define MMDC_MDRWD_tDAI_MASK ((0x1fff << MMDC_MDRWD_tDAI)) +#define MMDC_MDRWD_RTW_SAME_MASK ((0x7 << MMDC_MDRWD_RTW_SAME)) +#define MMDC_MDRWD_WTR_DIFF_MASK ((0x7 << MMDC_MDRWD_WTR_DIFF)) +#define MMDC_MDRWD_WTW_DIFF_MASK ((0x7 << MMDC_MDRWD_WTW_DIFF)) +#define MMDC_MDRWD_RTW_DIFF_MASK ((0x7 << MMDC_MDRWD_RTW_DIFF)) +#define MMDC_MDRWD_RTR_DIFF_MASK ((0x7 << MMDC_MDRWD_RTR_DIFF)) + +/* MDPDC */ +#define MMDC_MDPDC_PRCT_1_MASK ((0x7 << MMDC_MDPDC_PRCT_1)) +#define MMDC_MDPDC_PRCT_0_MASK ((0x7 << MMDC_MDPDC_PRCT_0)) +#define MMDC_MDPDC_tCKE_MASK ((0x7 << MMDC_MDPDC_tCKE)) +#define MMDC_MDPDC_PWDT_1_MASK ((0xf << MMDC_MDPDC_PWDT_1)) +#define MMDC_MDPDC_PWDT_0_MASK ((0xf << MMDC_MDPDC_PWDT_0)) +#define MMDC_MDPDC_SLOW_PD_MASK ((0x1 << MMDC_MDPDC_SLOW_PD)) +#define MMDC_MDPDC_BOTH_CS_PD_MASK ((0x1 << MMDC_MDPDC_BOTH_CS_PD)) +#define MMDC_MDPDC_tCKSRX_MASK ((0x7 << MMDC_MDPDC_tCKSRX)) +#define MMDC_MDPDC_tCKSRE_MASK ((0x7 << MMDC_MDPDC_tCKSRE)) + +/* MDASP */ +#define MMDC_MDASP_CS0_END_MASK ((0x7f << MMDC_MDASP_CS0_END)) + +/* MAEXIDR0 */ +#define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR1)) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR0)) + +/* MAEXIDR1 */ +#define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR3)) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR2)) + +/* MPWRDLCTL */ +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3)) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2)) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1)) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0)) + +/* MPRDDLCTL */ +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3)) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2)) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1)) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0)) + +/* MPWRDQBY0DL */ +#define MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DM0_DEL)) +#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ7_DEL)) +#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ6_DEL)) +#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ5_DEL)) +#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ4_DEL)) +#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ3_DEL)) +#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ2_DEL)) +#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ1_DEL)) +#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ0_DEL)) + +/* MPWRDQBY1DL */ +#define MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DM1_DEL)) +#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ15_DEL)) +#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ14_DEL)) +#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ13_DEL)) +#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ12_DEL)) +#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ11_DEL)) +#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ10_DEL)) +#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ9_DEL)) +#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ8_DEL)) + +/* MPWRDQBY2DL */ +#define MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DM2_DEL)) +#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ23_DEL)) +#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ22_DEL)) +#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ21_DEL)) +#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ20_DEL)) +#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ19_DEL)) +#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ18_DEL)) +#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ17_DEL)) +#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ16_DEL)) + +/* MPWRDQBY3DL */ +#define MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DM3_DEL)) +#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ31_DEL)) +#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ30_DEL)) +#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ29_DEL)) +#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ28_DEL)) +#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ27_DEL)) +#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ26_DEL)) +#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ25_DEL)) +#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ24_DEL)) + +#define SNVS_LPCR_DPEN (0x20) +#define SNVS_LPCR_SRTC_ENV (0x1) + +#define SRC_BASE_ADDR CMC1_RBASE +#define IRAM_BASE_ADDR OCRAM_0_BASE +#define IOMUXC_BASE_ADDR IOMUXC1_RBASE + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) + +#include + +struct fuse_word { + u32 fuse; + u32 rsvd[3]; +}; + +struct ocotp_regs { + u32 ctrl; + u32 ctrl_set; + u32 ctrl_clr; + u32 ctrl_tog; + u32 pdn; + u32 rsvd0[3]; + u32 data; + u32 rsvd1[3]; + u32 read_ctrl; + u32 rsvd2[3]; + u32 read_fuse_data; + u32 rsvd3[3]; + u32 sw_sticky; + u32 rsvd4[3]; + u32 scs; + u32 scs_set; + u32 scs_clr; + u32 scs_tog; + u32 out_status; + u32 out_status_set; + u32 out_status_clr; + u32 out_status_tog; + u32 startword; + u32 rsvd5[3]; + u32 version; + u32 rsvd6[19]; + struct fuse_word mem_repair[8]; + u32 rsvd7[0xa8]; + + /* fuse banks */ + struct fuse_bank { + u32 fuse_regs[0x20]; + } bank[0]; +}; + +struct fuse_bank1_regs { + u32 lock0; + u32 rsvd0[3]; + u32 lock1; + u32 rsvd1[3]; + u32 lock2; + u32 rsvd2[3]; + u32 cfg0; + u32 rsvd3[3]; + u32 cfg1; + u32 rsvd4[3]; + u32 cfg2; + u32 rsvd5[3]; + u32 cfg3; + u32 rsvd6[3]; + u32 cfg4; + u32 rsvd7[3]; +}; + +struct fuse_bank2_regs { + struct fuse_word boot[8]; +}; + +struct fuse_bank3_regs { + u32 mem0; + u32 rsvd0[3]; + u32 mem1; + u32 rsvd1[3]; + u32 mem2; + u32 rsvd2[3]; + u32 mem3; + u32 rsvd3[3]; + u32 ana0; + u32 rsvd4[3]; + u32 ana1; + u32 rsvd5[3]; + u32 ana2; + u32 rsvd6[3]; + u32 ana3; + u32 rsvd7[3]; +}; + +struct fuse_bank7_regs { + u32 sjc_resp0; + u32 rsvd0[3]; + u32 sjc_resp1; + u32 rsvd1[3]; + u32 gp0; + u32 rsvd2[3]; + u32 gp1; + u32 rsvd3[3]; + u32 gp2; + u32 rsvd4[3]; + u32 gp3; + u32 rsvd5[3]; + u32 gp4; + u32 rsvd6[3]; + u32 gp5; + u32 rsvd7[3]; +}; + +struct usbphy_regs { + u32 usbphy_pwd; /* 0x000 */ + u32 usbphy_pwd_set; /* 0x004 */ + u32 usbphy_pwd_clr; /* 0x008 */ + u32 usbphy_pwd_tog; /* 0x00c */ + u32 usbphy_tx; /* 0x010 */ + u32 usbphy_tx_set; /* 0x014 */ + u32 usbphy_tx_clr; /* 0x018 */ + u32 usbphy_tx_tog; /* 0x01c */ + u32 usbphy_rx; /* 0x020 */ + u32 usbphy_rx_set; /* 0x024 */ + u32 usbphy_rx_clr; /* 0x028 */ + u32 usbphy_rx_tog; /* 0x02c */ + u32 usbphy_ctrl; /* 0x030 */ + u32 usbphy_ctrl_set; /* 0x034 */ + u32 usbphy_ctrl_clr; /* 0x038 */ + u32 usbphy_ctrl_tog; /* 0x03c */ + u32 usbphy_status; /* 0x040 */ + u32 reserved0[3]; + u32 usbphy_debug0; /* 0x050 */ + u32 usbphy_debug0_set; /* 0x054 */ + u32 usbphy_debug0_clr; /* 0x058 */ + u32 usbphy_debug0_tog; /* 0x05c */ + u32 reserved1[4]; + u32 usbphy_debug1; /* 0x070 */ + u32 usbphy_debug1_set; /* 0x074 */ + u32 usbphy_debug1_clr; /* 0x078 */ + u32 usbphy_debug1_tog; /* 0x07c */ + u32 usbphy_version; /* 0x080 */ + u32 reserved2[7]; + u32 usb1_pll_480_ctrl; /* 0x0a0 */ + u32 usb1_pll_480_ctrl_set; /* 0x0a4 */ + u32 usb1_pll_480_ctrl_clr; /* 0x0a8 */ + u32 usb1_pll_480_ctrl_tog; /* 0x0ac */ + u32 reserved3[4]; + u32 usb1_vbus_detect; /* 0xc0 */ + u32 usb1_vbus_detect_set; /* 0xc4 */ + u32 usb1_vbus_detect_clr; /* 0xc8 */ + u32 usb1_vbus_detect_tog; /* 0xcc */ + u32 usb1_vbus_det_stat; /* 0xd0 */ + u32 reserved4[3]; + u32 usb1_chrg_detect; /* 0xe0 */ + u32 usb1_chrg_detect_set; /* 0xe4 */ + u32 usb1_chrg_detect_clr; /* 0xe8 */ + u32 usb1_chrg_detect_tog; /* 0xec */ + u32 usb1_chrg_det_stat; /* 0xf0 */ + u32 reserved5[3]; + u32 usbphy_anactrl; /* 0x100 */ + u32 usbphy_anactrl_set; /* 0x104 */ + u32 usbphy_anactrl_clr; /* 0x108 */ + u32 usbphy_anactrl_tog; /* 0x10c */ + u32 usb1_loopback; /* 0x110 */ + u32 usb1_loopback_set; /* 0x114 */ + u32 usb1_loopback_clr; /* 0x118 */ + u32 usb1_loopback_tog; /* 0x11c */ + u32 usb1_loopback_hsfscnt; /* 0x120 */ + u32 usb1_loopback_hsfscnt_set; /* 0x124 */ + u32 usb1_loopback_hsfscnt_clr; /* 0x128 */ + u32 usb1_loopback_hsfscnt_tog; /* 0x12c */ + u32 usphy_trim_override_en; /* 0x130 */ + u32 usphy_trim_override_en_set; /* 0x134 */ + u32 usphy_trim_override_en_clr; /* 0x138 */ + u32 usphy_trim_override_en_tog; /* 0x13c */ + u32 usb1_pfda_ctrl1; /* 0x140 */ + u32 usb1_pfda_ctrl1_set; /* 0x144 */ + u32 usb1_pfda_ctrl1_clr; /* 0x148 */ + u32 usb1_pfda_ctrl1_tog; /* 0x14c */ +}; + +struct bootrom_sw_info { + u8 reserved_1; + u8 boot_dev_instance; + u8 boot_dev_type; + u8 reserved_2; + u32 core_freq; + u32 axi_freq; + u32 ddr_freq; + u32 rom_tick_freq; + u32 reserved_3[3]; +}; + +#define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20))) +#define disconnect_from_pc(void) writel(0x0, USBOTG0_RBASE + 0x140) + +#endif + +#endif /* _MX7ULP_REGS_H_*/ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/iomux.h b/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/iomux.h new file mode 100644 index 000000000..f067c0206 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/iomux.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Based on Linux i.MX iomux-v3.h file: + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * + * + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#ifndef __MACH_IOMUX_H__ +#define __MACH_IOMUX_H__ + +/* + * build IOMUX_PAD structure + * + * This iomux scheme is based around pads, which are the physical balls + * on the processor. + * + * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls + * things like driving strength and pullup/pulldown. + * - Each pad can have but not necessarily does have an output routing register + * (IOMUXC_SW_MUX_CTL_PAD_x). + * - Each pad can have but not necessarily does have an input routing register + * (IOMUXC_x_SELECT_INPUT) + * + * The three register sets do not have a fixed offset to each other, + * hence we order this table by pad control registers (which all pads + * have) and put the optional i/o routing registers into additional + * fields. + * + * The naming convention for the pad modes is SOC_PAD___ + * If or refers to a GPIO, it is named GPIO__ + * + * IOMUX/PAD Bit field definitions + * + * MUX_CTRL_OFS: 0..15 (16) + * SEL_INPUT_OFS: 16..31 (16) + * MUX_MODE: 32..37 (6) + * SEL_INP: 38..41 (4) + * PAD_CTRL + NO_PAD_CTRL: 42..60 (19) + * reserved: 61-63 (3) +*/ + +typedef u64 iomux_cfg_t; + +#define MUX_CTRL_OFS_SHIFT 0 +#define MUX_CTRL_OFS_MASK ((iomux_cfg_t)0xffff << MUX_CTRL_OFS_SHIFT) +#define MUX_SEL_INPUT_OFS_SHIFT 16 +#define MUX_SEL_INPUT_OFS_MASK ((iomux_cfg_t)0xffff << \ + MUX_SEL_INPUT_OFS_SHIFT) + +#define MUX_MODE_SHIFT 32 +#define MUX_MODE_MASK ((iomux_cfg_t)0x3f << MUX_MODE_SHIFT) +#define MUX_SEL_INPUT_SHIFT 38 +#define MUX_SEL_INPUT_MASK ((iomux_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) +#define MUX_PAD_CTRL_SHIFT 42 +#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0x7ffff << MUX_PAD_CTRL_SHIFT) + +#define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) + +#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ + sel_input, pad_ctrl) \ + (((iomux_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ + ((iomux_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \ + ((iomux_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ + ((iomux_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \ + ((iomux_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT)) + +#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \ + MUX_PAD_CTRL(pad)) + + +#define IOMUX_CONFIG_MPORTS 0x20 +#define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \ + MUX_MODE_SHIFT) + +/* Bit definition below needs to be fixed acccording to ulp rm */ + +#define NO_PAD_CTRL (1 << 18) +#define PAD_CTL_OBE_ENABLE (1 << 17) +#define PAD_CTL_IBE_ENABLE (1 << 16) +#define PAD_CTL_DSE (1 << 6) +#define PAD_CTL_ODE (1 << 5) +#define PAD_CTL_SRE_FAST (0 << 2) +#define PAD_CTL_SRE_SLOW (1 << 2) +#define PAD_CTL_PUE (1 << 1) +#define PAD_CTL_PUS_UP ((1 << 0) | PAD_CTL_PUE) +#define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE) + + +void mx7ulp_iomux_setup_pad(iomux_cfg_t pad); +void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, + unsigned count); +#endif /* __MACH_IOMUX_H__*/ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h b/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h new file mode 100644 index 000000000..139b766c2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h @@ -0,0 +1,909 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + */ + +#ifndef __ASM_ARCH_IMX7ULP_PINS_H__ +#define __ASM_ARCH_IMX7ULP_PINS_H__ + +#include + +enum { + MX7ULP_PAD_PTA0__CMP0_IN1_3V = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA0__PTA0 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA0__LPSPI0_PCS1 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x2, 0), + MX7ULP_PAD_PTA0__LPUART0_CTS_b = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x2, 0), + MX7ULP_PAD_PTA0__LPI2C0_SCL = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x2, 0), + MX7ULP_PAD_PTA0__TPM0_CLKIN = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x2, 0), + MX7ULP_PAD_PTA0__I2S0_RX_BCLK = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8, 0x2, 0), + MX7ULP_PAD_PTA0__LLWU0_P0 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA1__CMP0_IN2_3V = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA1__PTA1 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA1__LPSPI0_PCS2 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x1, 0), + MX7ULP_PAD_PTA1__LPUART0_RTS_b = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA1__LPI2C0_SDA = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x1, 0), + MX7ULP_PAD_PTA1__TPM0_CH0 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x1, 0), + MX7ULP_PAD_PTA1__I2S0_RX_FS = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x7, 0xD1BC, 0x1, 0), + MX7ULP_PAD_PTA2__CMP1_IN2_3V = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA2__PTA2 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA2__LPSPI0_PCS3 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x1, 0), + MX7ULP_PAD_PTA2__LPUART0_TX = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x4, 0xD200, 0x1, 0), + MX7ULP_PAD_PTA2__LPI2C0_HREQ = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x5, 0xD178, 0x1, 0), + MX7ULP_PAD_PTA2__TPM0_CH1 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x1, 0), + MX7ULP_PAD_PTA2__I2S0_RXD0 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x7, 0xD1DC, 0x1, 0), + MX7ULP_PAD_PTA3__CMP1_IN4_3V = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA3__PTA3 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA3__LPSPI0_PCS0 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x1, 0), + MX7ULP_PAD_PTA3__LPUART0_RX = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x4, 0xD1FC, 0x1, 0), + MX7ULP_PAD_PTA3__TPM0_CH2 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x6, 0xD140, 0x1, 0), + MX7ULP_PAD_PTA3__I2S0_RXD1 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E0, 0x1, 0), + MX7ULP_PAD_PTA3__CMP0_OUT = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA3__LLWU0_P1 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA4__ADC1_CH3A = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA4__PTA4 = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA4__LPSPI0_SIN = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x1, 0), + MX7ULP_PAD_PTA4__LPUART1_CTS_b = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x1, 0), + MX7ULP_PAD_PTA4__LPI2C1_SCL = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x1, 0), + MX7ULP_PAD_PTA4__TPM0_CH3 = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x6, 0xD144, 0x1, 0), + MX7ULP_PAD_PTA4__I2S0_MCLK = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B4, 0x1, 0), + MX7ULP_PAD_PTA5__ADC1_CH3B = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA5__PTA5 = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA5__LPSPI0_SOUT = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x1, 0), + MX7ULP_PAD_PTA5__LPUART1_RTS_b = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA5__LPI2C1_SDA = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x1, 0), + MX7ULP_PAD_PTA5__TPM0_CH4 = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x6, 0xD148, 0x1, 0), + MX7ULP_PAD_PTA5__I2S0_TX_BCLK = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C0, 0x1, 0), + MX7ULP_PAD_PTA6__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA6__PTA6 = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA6__LPSPI0_SCK = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x1, 0), + MX7ULP_PAD_PTA6__LPUART1_TX = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x1, 0), + MX7ULP_PAD_PTA6__LPI2C1_HREQ = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x1, 0), + MX7ULP_PAD_PTA6__TPM0_CH5 = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x6, 0xD14C, 0x1, 0), + MX7ULP_PAD_PTA6__I2S0_TX_FS = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C4, 0x1, 0), + MX7ULP_PAD_PTA7__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA7__PTA7 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA7__LPUART1_RX = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x1, 0), + MX7ULP_PAD_PTA7__TPM1_CH1 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x1, 0), + MX7ULP_PAD_PTA7__I2S0_TXD0 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA8__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA8__PTA8 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA8__LPSPI1_PCS1 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x1, 0), + MX7ULP_PAD_PTA8__LPUART2_CTS_b = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x1, 0), + MX7ULP_PAD_PTA8__LPI2C2_SCL = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x1, 0), + MX7ULP_PAD_PTA8__TPM1_CLKIN = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x1, 0), + MX7ULP_PAD_PTA8__I2S0_TXD1 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA9__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA9__PTA9 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA9__LPSPI1_PCS2 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x1, 0), + MX7ULP_PAD_PTA9__LPUART2_RTS_b = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA9__LPI2C2_SDA = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x1, 0), + MX7ULP_PAD_PTA9__TPM1_CH0 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x1, 0), + MX7ULP_PAD_PTA9__NMI0_b = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA10__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA10__PTA10 = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA10__LPSPI1_PCS3 = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x1, 0), + MX7ULP_PAD_PTA10__LPUART2_TX = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x1, 0), + MX7ULP_PAD_PTA10__LPI2C2_HREQ = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x1, 0), + MX7ULP_PAD_PTA10__TPM2_CLKIN = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x1, 0), + MX7ULP_PAD_PTA10__I2S0_RX_BCLK = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8, 0x1, 0), + MX7ULP_PAD_PTA11__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA11__PTA11 = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA11__LPUART2_RX = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x1, 0), + MX7ULP_PAD_PTA11__TPM2_CH0 = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x1, 0), + MX7ULP_PAD_PTA11__I2S0_RX_FS = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1BC, 0x2, 0), + MX7ULP_PAD_PTA12__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA12__PTA12 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA12__LPSPI1_SIN = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x1, 0), + MX7ULP_PAD_PTA12__LPUART3_CTS_b = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x1, 0), + MX7ULP_PAD_PTA12__LPI2C3_SCL = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x1, 0), + MX7ULP_PAD_PTA12__TPM2_CH1 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x1, 0), + MX7ULP_PAD_PTA12__I2S0_RXD0 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x7, 0xD1DC, 0x2, 0), + MX7ULP_PAD_PTA13__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA13__PTA13 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA13__LPSPI1_SOUT = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x2, 0), + MX7ULP_PAD_PTA13__LPUART3_RTS_b = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA13__LPI2C3_SDA = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x2, 0), + MX7ULP_PAD_PTA13__TPM3_CLKIN = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x1, 0), + MX7ULP_PAD_PTA13__I2S0_RXD1 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E0, 0x2, 0), + MX7ULP_PAD_PTA13__CMP0_OUT = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA13__LLWU0_P2 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA14__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA14__PTA14 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA14__LPSPI1_SCK = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x2, 0), + MX7ULP_PAD_PTA14__LPUART3_TX = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x2, 0), + MX7ULP_PAD_PTA14__LPI2C3_HREQ = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x2, 0), + MX7ULP_PAD_PTA14__TPM3_CH0 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x1, 0), + MX7ULP_PAD_PTA14__I2S0_MCLK = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B4, 0x2, 0), + MX7ULP_PAD_PTA14__LLWU0_P3 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA15__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA15__PTA15 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA15__LPSPI1_PCS0 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x1, 0), + MX7ULP_PAD_PTA15__LPUART3_RX = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x1, 0), + MX7ULP_PAD_PTA15__TPM3_CH1 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x1, 0), + MX7ULP_PAD_PTA15__I2S0_TX_BCLK = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C0, 0x2, 0), + MX7ULP_PAD_PTA16__CMP1_IN5_3V = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA16__PTA16 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA16__FXIO0_D0 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA16__LPSPI0_SOUT = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x2, 0), + MX7ULP_PAD_PTA16__LPUART0_CTS_b = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x1, 0), + MX7ULP_PAD_PTA16__LPI2C0_SCL = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x1, 0), + MX7ULP_PAD_PTA16__TPM3_CH2 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x6, 0xD168, 0x1, 0), + MX7ULP_PAD_PTA16__I2S0_TX_FS = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C4, 0x2, 0), + MX7ULP_PAD_PTA17__CMP1_IN6_3V = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA17__PTA17 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA17__FXIO0_D1 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA17__LPSPI0_SCK = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x2, 0), + MX7ULP_PAD_PTA17__LPUART0_RTS_b = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA17__LPI2C0_SDA = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x2, 0), + MX7ULP_PAD_PTA17__TPM3_CH3 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x6, 0xD16C, 0x1, 0), + MX7ULP_PAD_PTA17__I2S0_TXD0 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA18__CMP1_IN1_3V = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA18__PTA18 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA18__FXIO0_D2 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA18__LPSPI0_PCS0 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x2, 0), + MX7ULP_PAD_PTA18__LPUART0_TX = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x4, 0xD200, 0x2, 0), + MX7ULP_PAD_PTA18__LPI2C0_HREQ = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x5, 0xD178, 0x2, 0), + MX7ULP_PAD_PTA18__TPM3_CH4 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x6, 0xD170, 0x1, 0), + MX7ULP_PAD_PTA18__I2S0_TXD1 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA18__LLWU0_P4 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA19__CMP1_IN3_3V = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA19__PTA19 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA19__FXIO0_D3 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA19__LPUART0_RX = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x4, 0xD1FC, 0x2, 0), + MX7ULP_PAD_PTA19__TPM3_CH5 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x6, 0xD174, 0x1, 0), + MX7ULP_PAD_PTA19__I2S1_RX_BCLK = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1CC, 0x1, 0), + MX7ULP_PAD_PTA19__LPTMR0_ALT3 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA19__LLWU0_P5 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA20__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA20__PTA20 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA20__FXIO0_D4 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA20__LPSPI0_SIN = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x2, 0), + MX7ULP_PAD_PTA20__LPUART1_CTS_b = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x2, 0), + MX7ULP_PAD_PTA20__LPI2C1_SCL = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x2, 0), + MX7ULP_PAD_PTA20__TPM0_CLKIN = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x1, 0), + MX7ULP_PAD_PTA20__I2S1_RX_FS = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D0, 0x1, 0), + MX7ULP_PAD_PTA21__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA21__PTA21 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA21__FXIO0_D5 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA21__LPSPI0_PCS1 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x1, 0), + MX7ULP_PAD_PTA21__LPUART1_RTS_b = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA21__LPI2C1_SDA = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x2, 0), + MX7ULP_PAD_PTA21__TPM0_CH0 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x2, 0), + MX7ULP_PAD_PTA21__I2S1_RXD0 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E4, 0x1, 0), + MX7ULP_PAD_PTA22__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA22__PTA22 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA22__FXIO0_D6 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA22__LPSPI0_PCS2 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x2, 0), + MX7ULP_PAD_PTA22__LPUART1_TX = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x2, 0), + MX7ULP_PAD_PTA22__LPI2C1_HREQ = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x2, 0), + MX7ULP_PAD_PTA22__TPM0_CH1 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x2, 0), + MX7ULP_PAD_PTA22__I2S1_RXD1 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E8, 0x1, 0), + MX7ULP_PAD_PTA22__LPTMR0_ALT2 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA22__EWM_OUT_b = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA23__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA23__PTA23 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA23__FXIO0_D7 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA23__LPSPI0_PCS3 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x2, 0), + MX7ULP_PAD_PTA23__LPUART1_RX = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x2, 0), + MX7ULP_PAD_PTA23__TPM0_CH2 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x6, 0xD140, 0x2, 0), + MX7ULP_PAD_PTA23__I2S1_MCLK = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C8, 0x1, 0), + MX7ULP_PAD_PTA23__LLWU0_P6 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA24__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA24__PTA24 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA24__FXIO0_D8 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA24__LPSPI1_PCS1 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x2, 0), + MX7ULP_PAD_PTA24__LPUART2_CTS_b = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x2, 0), + MX7ULP_PAD_PTA24__LPI2C2_SCL = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x2, 0), + MX7ULP_PAD_PTA24__TPM0_CH3 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x6, 0xD144, 0x2, 0), + MX7ULP_PAD_PTA24__I2S1_TX_BCLK = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D4, 0x1, 0), + MX7ULP_PAD_PTA25__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA25__PTA25 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA25__FXIO0_D9 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA25__LPSPI1_PCS2 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x2, 0), + MX7ULP_PAD_PTA25__LPUART2_RTS_b = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA25__LPI2C2_SDA = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x2, 0), + MX7ULP_PAD_PTA25__TPM0_CH4 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x6, 0xD148, 0x2, 0), + MX7ULP_PAD_PTA25__I2S1_TX_FS = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D8, 0x1, 0), + MX7ULP_PAD_PTA26__PTA26 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA26__JTAG_TMS_SWD_DIO = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA26__FXIO0_D10 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA26__LPSPI1_PCS3 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x2, 0), + MX7ULP_PAD_PTA26__LPUART2_TX = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x2, 0), + MX7ULP_PAD_PTA26__LPI2C2_HREQ = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x2, 0), + MX7ULP_PAD_PTA26__TPM0_CH5 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x6, 0xD14C, 0x2, 0), + MX7ULP_PAD_PTA26__I2S1_RXD2 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x7, 0xD1EC, 0x1, 0), + MX7ULP_PAD_PTA27__PTA27 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA27__JTAG_TDO = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA27__FXIO0_D11 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA27__LPUART2_RX = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x2, 0), + MX7ULP_PAD_PTA27__TPM1_CH1 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x2, 0), + MX7ULP_PAD_PTA27__I2S1_RXD3 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1F0, 0x1, 0), + MX7ULP_PAD_PTA28__PTA28 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA28__JTAG_TDI = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA28__FXIO0_D12 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA28__LPSPI1_SIN = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x2, 0), + MX7ULP_PAD_PTA28__LPUART3_CTS_b = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x2, 0), + MX7ULP_PAD_PTA28__LPI2C3_SCL = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x2, 0), + MX7ULP_PAD_PTA28__TPM1_CLKIN = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x2, 0), + MX7ULP_PAD_PTA28__I2S1_TXD2 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA29__PTA29 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA29__JTAG_TCLK_SWD_CLK = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA29__FXIO0_D13 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA29__LPSPI1_SOUT = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x1, 0), + MX7ULP_PAD_PTA29__LPUART3_RTS_b = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA29__LPI2C3_SDA = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x1, 0), + MX7ULP_PAD_PTA29__TPM1_CH0 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x2, 0), + MX7ULP_PAD_PTA29__I2S1_TXD3 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA30__ADC0_CH1A = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA30__PTA30 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA30__FXIO0_D14 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA30__LPSPI1_SCK = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x1, 0), + MX7ULP_PAD_PTA30__LPUART3_TX = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x1, 0), + MX7ULP_PAD_PTA30__LPI2C3_HREQ = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x1, 0), + MX7ULP_PAD_PTA30__TPM2_CLKIN = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x2, 0), + MX7ULP_PAD_PTA30__I2S1_TXD0 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA30__JTAG_TRST_b = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA31__ADC0_CH1B = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA31__PTA31 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA31__FXIO0_D15 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA31__LPSPI1_PCS0 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x2, 0), + MX7ULP_PAD_PTA31__LPUART3_RX = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x2, 0), + MX7ULP_PAD_PTA31__TPM2_CH0 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x2, 0), + MX7ULP_PAD_PTA31__I2S1_TXD1 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA31__LPTMR0_ALT1 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA31__EWM_IN = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0xc, 0xD228, 0x1, 0), + MX7ULP_PAD_PTA31__LLWU0_P7 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB0__ADC0_CH0A = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB0__PTB0 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB0__FXIO0_D16 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB0__LPSPI0_SIN = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x3, 0), + MX7ULP_PAD_PTB0__LPUART0_TX = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x4, 0xD200, 0x3, 0), + MX7ULP_PAD_PTB0__TPM2_CH1 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x2, 0), + MX7ULP_PAD_PTB0__CLKOUT0 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB0__CMP1_OUT = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB0__EWM_OUT_b = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB1__ADC0_CH0B = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB1__PTB1 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB1__FXIO0_D17 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB1__LPSPI0_SOUT = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x3, 0), + MX7ULP_PAD_PTB1__LPUART0_RX = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x4, 0xD1FC, 0x3, 0), + MX7ULP_PAD_PTB1__TPM3_CLKIN = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x3, 0), + MX7ULP_PAD_PTB1__I2S1_TX_BCLK = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D4, 0x2, 0), + MX7ULP_PAD_PTB1__RTC_CLKOUT = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB1__EWM_IN = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xc, 0xD228, 0x2, 0), + MX7ULP_PAD_PTB1__LLWU0_P8 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB2__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB2__PTB2 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB2__FXIO0_D18 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB2__LPSPI0_SCK = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x3, 0), + MX7ULP_PAD_PTB2__LPUART1_TX = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x3, 0), + MX7ULP_PAD_PTB2__TPM3_CH0 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x2, 0), + MX7ULP_PAD_PTB2__I2S1_TX_FS = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D8, 0x2, 0), + MX7ULP_PAD_PTB2__TRACE_CLKOUT = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB3__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB3__PTB3 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB3__FXIO0_D19 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB3__LPSPI0_PCS0 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x3, 0), + MX7ULP_PAD_PTB3__LPUART1_RX = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x3, 0), + MX7ULP_PAD_PTB3__TPM3_CH1 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x2, 0), + MX7ULP_PAD_PTB3__I2S1_TXD0 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB3__TRACE_D0 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB3__LPTMR1_ALT2 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB3__LLWU0_P9 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB4__PTB4 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB4__FXIO0_D20 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB4__LPSPI0_PCS1 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x3, 0), + MX7ULP_PAD_PTB4__LPUART2_TX = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x3, 0), + MX7ULP_PAD_PTB4__LPI2C0_HREQ = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x5, 0xD178, 0x3, 0), + MX7ULP_PAD_PTB4__TPM3_CH2 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x6, 0xD168, 0x2, 0), + MX7ULP_PAD_PTB4__I2S1_TXD1 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB4__QSPIA_DATA7 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB4__TRACE_D1 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB5__PTB5 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB5__FXIO0_D21 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB5__LPSPI0_PCS2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x3, 0), + MX7ULP_PAD_PTB5__LPUART2_RX = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x3, 0), + MX7ULP_PAD_PTB5__LPI2C1_HREQ = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x3, 0), + MX7ULP_PAD_PTB5__TPM3_CH3 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x6, 0xD16C, 0x2, 0), + MX7ULP_PAD_PTB5__I2S1_TXD2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB5__QSPIA_DATA6 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB5__TRACE_D2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB6__ADC1_CH1A = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB6__PTB6 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB6__FXIO0_D22 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB6__LPSPI0_PCS3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x3, 0), + MX7ULP_PAD_PTB6__LPUART3_TX = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x3, 0), + MX7ULP_PAD_PTB6__LPI2C0_SCL = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x3, 0), + MX7ULP_PAD_PTB6__TPM3_CH4 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x6, 0xD170, 0x2, 0), + MX7ULP_PAD_PTB6__I2S1_TXD3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB6__QSPIA_DATA5 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB6__TRACE_D3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB6__LPTMR1_ALT3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB6__LLWU0_P10 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB7__ADC1_CH1B = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB7__PTB7 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB7__FXIO0_D23 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB7__LPSPI1_SIN = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x3, 0), + MX7ULP_PAD_PTB7__LPUART3_RX = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x3, 0), + MX7ULP_PAD_PTB7__LPI2C0_SDA = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x3, 0), + MX7ULP_PAD_PTB7__TPM3_CH5 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x6, 0xD174, 0x2, 0), + MX7ULP_PAD_PTB7__I2S1_MCLK = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C8, 0x2, 0), + MX7ULP_PAD_PTB7__QSPIA_SS1_B = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB7__CMP1_OUT = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB7__LLWU0_P11 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB8__ADC0_CH14A_CMP0_IN0 = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB8__PTB8 = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB8__FXIO0_D24 = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB8__LPSPI1_SOUT = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x3, 0), + MX7ULP_PAD_PTB8__LPI2C1_SCL = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x3, 0), + MX7ULP_PAD_PTB8__TPM0_CLKIN = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x3, 0), + MX7ULP_PAD_PTB8__I2S1_RX_BCLK = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x7, 0xD1CC, 0x2, 0), + MX7ULP_PAD_PTB8__QSPIA_SS0_B = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB8__RTC_CLKOUT = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB9__ADC0_CH14B_CMP0_IN2 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB9__PTB9 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB9__FXIO0_D25 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB9__LPSPI1_SCK = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x3, 0), + MX7ULP_PAD_PTB9__LPI2C1_SDA = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x3, 0), + MX7ULP_PAD_PTB9__TPM0_CH0 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x3, 0), + MX7ULP_PAD_PTB9__I2S1_RX_FS = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D0, 0x2, 0), + MX7ULP_PAD_PTB9__QSPIA_DQS = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB9__LLWU0_P12 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB10__CMP0_IN1 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB10__PTB10 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB10__FXIO0_D26 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB10__LPSPI1_PCS0 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x3, 0), + MX7ULP_PAD_PTB10__LPI2C2_SCL = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x3, 0), + MX7ULP_PAD_PTB10__TPM0_CH1 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x3, 0), + MX7ULP_PAD_PTB10__I2S1_RXD0 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E4, 0x2, 0), + MX7ULP_PAD_PTB10__TRACE_D4 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB11__CMP0_IN3 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB11__PTB11 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB11__FXIO0_D27 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB11__LPSPI1_PCS1 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x3, 0), + MX7ULP_PAD_PTB11__LPI2C2_SDA = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x3, 0), + MX7ULP_PAD_PTB11__TPM1_CLKIN = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x3, 0), + MX7ULP_PAD_PTB11__I2S1_RXD1 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E8, 0x2, 0), + MX7ULP_PAD_PTB11__TRACE_D5 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB12__ADC1_CH13A_CMP1_IN0 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB12__PTB12 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB12__FXIO0_D28 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB12__LPSPI1_PCS2 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x3, 0), + MX7ULP_PAD_PTB12__LPI2C3_SCL = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x3, 0), + MX7ULP_PAD_PTB12__TPM1_CH0 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x3, 0), + MX7ULP_PAD_PTB12__I2S1_RXD2 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x7, 0xD1EC, 0x2, 0), + MX7ULP_PAD_PTB12__TRACE_D6 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB13__ADC1_CH13B_CMP1_IN1 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB13__PTB13 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB13__FXIO0_D29 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB13__LPSPI1_PCS3 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x3, 0), + MX7ULP_PAD_PTB13__LPI2C3_SDA = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x3, 0), + MX7ULP_PAD_PTB13__TPM1_CH1 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x3, 0), + MX7ULP_PAD_PTB13__I2S1_RXD3 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x7, 0xD1F0, 0x2, 0), + MX7ULP_PAD_PTB13__QSPIA_DATA4 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB13__TRACE_D7 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB14__ADC1_CH2A = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB14__PTB14 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB14__FXIO0_D30 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB14__LPI2C2_HREQ = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x3, 0), + MX7ULP_PAD_PTB14__TPM2_CLKIN = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x3, 0), + MX7ULP_PAD_PTB14__QSPIA_SS1_B = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB14__QSPIA_SCLK_b = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB14__LLWU0_P13 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB15__ADC1_CH2B = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB15__PTB15 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB15__FXIO0_D31 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB15__LPI2C3_HREQ = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x3, 0), + MX7ULP_PAD_PTB15__TPM2_CH0 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x3, 0), + MX7ULP_PAD_PTB15__QSPIA_SCLK = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB16__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB16__PTB16 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB16__TPM2_CH1 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x3, 0), + MX7ULP_PAD_PTB16__QSPIA_DATA3 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB16__LLWU0_P14 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB17__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB17__PTB17 = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB17__TPM3_CLKIN = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x2, 0), + MX7ULP_PAD_PTB17__QSPIA_DATA2 = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB18__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB18__PTB18 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB18__TPM3_CH0 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x3, 0), + MX7ULP_PAD_PTB18__QSPIA_DATA1 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB19__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB19__PTB19 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB19__TPM3_CH1 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x3, 0), + MX7ULP_PAD_PTB19__QSPIA_DATA0 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB19__USB0_ID = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB19__LLWU0_P15 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC0__PTC0 = IOMUX_PAD(0x0000, 0x0000, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC0__LPUART4_CTS_b = IOMUX_PAD(0x0000, 0x0000, 0x4, 0x0244, 0x1, 0), + MX7ULP_PAD_PTC0__LPI2C4_SCL = IOMUX_PAD(0x0000, 0x0000, 0x5, 0x0278, 0x1, 0), + MX7ULP_PAD_PTC0__TPM4_CLKIN = IOMUX_PAD(0x0000, 0x0000, 0x6, 0x0298, 0x1, 0), + MX7ULP_PAD_PTC0__FB_AD0 = IOMUX_PAD(0x0000, 0x0000, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC0__TRACE_D15 = IOMUX_PAD(0x0000, 0x0000, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC0__DEBUG_MUX0 = IOMUX_PAD(0x0000, 0x0000, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC1__PTC1 = IOMUX_PAD(0x0004, 0x0004, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC1__LPUART4_RTS_b = IOMUX_PAD(0x0004, 0x0004, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC1__LPI2C4_SDA = IOMUX_PAD(0x0004, 0x0004, 0x5, 0x027C, 0x1, 0), + MX7ULP_PAD_PTC1__TPM4_CH0 = IOMUX_PAD(0x0004, 0x0004, 0x6, 0x0280, 0x1, 0), + MX7ULP_PAD_PTC1__FB_AD1 = IOMUX_PAD(0x0004, 0x0004, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC1__TRACE_D14 = IOMUX_PAD(0x0004, 0x0004, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC1__DEBUG_MUX1 = IOMUX_PAD(0x0004, 0x0004, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC2__PTC2 = IOMUX_PAD(0x0008, 0x0008, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC2__LPUART4_TX = IOMUX_PAD(0x0008, 0x0008, 0x4, 0x024C, 0x1, 0), + MX7ULP_PAD_PTC2__LPI2C4_HREQ = IOMUX_PAD(0x0008, 0x0008, 0x5, 0x0274, 0x1, 0), + MX7ULP_PAD_PTC2__TPM4_CH1 = IOMUX_PAD(0x0008, 0x0008, 0x6, 0x0284, 0x1, 0), + MX7ULP_PAD_PTC2__FB_AD2 = IOMUX_PAD(0x0008, 0x0008, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC2__TRACE_D13 = IOMUX_PAD(0x0008, 0x0008, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC2__DEBUG_MUX2 = IOMUX_PAD(0x0008, 0x0008, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC3__PTC3 = IOMUX_PAD(0x000C, 0x000C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC3__LPUART4_RX = IOMUX_PAD(0x000C, 0x000C, 0x4, 0x0248, 0x1, 0), + MX7ULP_PAD_PTC3__TPM4_CH2 = IOMUX_PAD(0x000C, 0x000C, 0x6, 0x0288, 0x1, 0), + MX7ULP_PAD_PTC3__FB_AD3 = IOMUX_PAD(0x000C, 0x000C, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC3__TRACE_D12 = IOMUX_PAD(0x000C, 0x000C, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC3__DEBUG_MUX3 = IOMUX_PAD(0x000C, 0x000C, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC4__PTC4 = IOMUX_PAD(0x0010, 0x0010, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC4__FXIO1_D0 = IOMUX_PAD(0x0010, 0x0010, 0x2, 0x0204, 0x1, 0), + MX7ULP_PAD_PTC4__LPSPI2_PCS1 = IOMUX_PAD(0x0010, 0x0010, 0x3, 0x02A0, 0x1, 0), + MX7ULP_PAD_PTC4__LPUART5_CTS_b = IOMUX_PAD(0x0010, 0x0010, 0x4, 0x0250, 0x1, 0), + MX7ULP_PAD_PTC4__LPI2C5_SCL = IOMUX_PAD(0x0010, 0x0010, 0x5, 0x02BC, 0x1, 0), + MX7ULP_PAD_PTC4__TPM4_CH3 = IOMUX_PAD(0x0010, 0x0010, 0x6, 0x028C, 0x1, 0), + MX7ULP_PAD_PTC4__FB_AD4 = IOMUX_PAD(0x0010, 0x0010, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC4__TRACE_D11 = IOMUX_PAD(0x0010, 0x0010, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC4__DEBUG_MUX4 = IOMUX_PAD(0x0010, 0x0010, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC5__PTC5 = IOMUX_PAD(0x0014, 0x0014, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC5__FXIO1_D1 = IOMUX_PAD(0x0014, 0x0014, 0x2, 0x0208, 0x1, 0), + MX7ULP_PAD_PTC5__LPSPI2_PCS2 = IOMUX_PAD(0x0014, 0x0014, 0x3, 0x02A4, 0x1, 0), + MX7ULP_PAD_PTC5__LPUART5_RTS_b = IOMUX_PAD(0x0014, 0x0014, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC5__LPI2C5_SDA = IOMUX_PAD(0x0014, 0x0014, 0x5, 0x02C0, 0x1, 0), + MX7ULP_PAD_PTC5__TPM4_CH4 = IOMUX_PAD(0x0014, 0x0014, 0x6, 0x0290, 0x1, 0), + MX7ULP_PAD_PTC5__FB_AD5 = IOMUX_PAD(0x0014, 0x0014, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC5__TRACE_D10 = IOMUX_PAD(0x0014, 0x0014, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC5__DEBUG_MUX5 = IOMUX_PAD(0x0014, 0x0014, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC6__PTC6 = IOMUX_PAD(0x0018, 0x0018, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC6__FXIO1_D2 = IOMUX_PAD(0x0018, 0x0018, 0x2, 0x020C, 0x1, 0), + MX7ULP_PAD_PTC6__LPSPI2_PCS3 = IOMUX_PAD(0x0018, 0x0018, 0x3, 0x02A8, 0x1, 0), + MX7ULP_PAD_PTC6__LPUART5_TX = IOMUX_PAD(0x0018, 0x0018, 0x4, 0x0258, 0x1, 0), + MX7ULP_PAD_PTC6__LPI2C5_HREQ = IOMUX_PAD(0x0018, 0x0018, 0x5, 0x02B8, 0x1, 0), + MX7ULP_PAD_PTC6__TPM4_CH5 = IOMUX_PAD(0x0018, 0x0018, 0x6, 0x0294, 0x1, 0), + MX7ULP_PAD_PTC6__FB_AD6 = IOMUX_PAD(0x0018, 0x0018, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC6__TRACE_D9 = IOMUX_PAD(0x0018, 0x0018, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC6__DEBUG_MUX6 = IOMUX_PAD(0x0018, 0x0018, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC7__PTC7 = IOMUX_PAD(0x001C, 0x001C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC7__FXIO1_D3 = IOMUX_PAD(0x001C, 0x001C, 0x2, 0x0210, 0x1, 0), + MX7ULP_PAD_PTC7__LPUART5_RX = IOMUX_PAD(0x001C, 0x001C, 0x4, 0x0254, 0x1, 0), + MX7ULP_PAD_PTC7__TPM5_CH1 = IOMUX_PAD(0x001C, 0x001C, 0x6, 0x02C8, 0x1, 0), + MX7ULP_PAD_PTC7__FB_AD7 = IOMUX_PAD(0x001C, 0x001C, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC7__TRACE_D8 = IOMUX_PAD(0x001C, 0x001C, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC7__DEBUG_MUX7 = IOMUX_PAD(0x001C, 0x001C, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC8__PTC8 = IOMUX_PAD(0x0020, 0x0020, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC8__FXIO1_D4 = IOMUX_PAD(0x0020, 0x0020, 0x2, 0x0214, 0x1, 0), + MX7ULP_PAD_PTC8__LPSPI2_SIN = IOMUX_PAD(0x0020, 0x0020, 0x3, 0x02B0, 0x1, 0), + MX7ULP_PAD_PTC8__LPUART6_CTS_b = IOMUX_PAD(0x0020, 0x0020, 0x4, 0x025C, 0x1, 0), + MX7ULP_PAD_PTC8__LPI2C6_SCL = IOMUX_PAD(0x0020, 0x0020, 0x5, 0x02FC, 0x1, 0), + MX7ULP_PAD_PTC8__TPM5_CLKIN = IOMUX_PAD(0x0020, 0x0020, 0x6, 0x02CC, 0x1, 0), + MX7ULP_PAD_PTC8__FB_AD8 = IOMUX_PAD(0x0020, 0x0020, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC8__TRACE_D7 = IOMUX_PAD(0x0020, 0x0020, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC8__DEBUG_MUX8 = IOMUX_PAD(0x0020, 0x0020, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC9__PTC9 = IOMUX_PAD(0x0024, 0x0024, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC9__FXIO1_D5 = IOMUX_PAD(0x0024, 0x0024, 0x2, 0x0218, 0x1, 0), + MX7ULP_PAD_PTC9__LPSPI2_SOUT = IOMUX_PAD(0x0024, 0x0024, 0x3, 0x02B4, 0x1, 0), + MX7ULP_PAD_PTC9__LPUART6_RTS_b = IOMUX_PAD(0x0024, 0x0024, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC9__LPI2C6_SDA = IOMUX_PAD(0x0024, 0x0024, 0x5, 0x0300, 0x1, 0), + MX7ULP_PAD_PTC9__TPM5_CH0 = IOMUX_PAD(0x0024, 0x0024, 0x6, 0x02C4, 0x1, 0), + MX7ULP_PAD_PTC9__FB_AD9 = IOMUX_PAD(0x0024, 0x0024, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC9__TRACE_D6 = IOMUX_PAD(0x0024, 0x0024, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC9__DEBUG_MUX9 = IOMUX_PAD(0x0024, 0x0024, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC10__PTC10 = IOMUX_PAD(0x0028, 0x0028, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC10__FXIO1_D6 = IOMUX_PAD(0x0028, 0x0028, 0x2, 0x021C, 0x1, 0), + MX7ULP_PAD_PTC10__LPSPI2_SCK = IOMUX_PAD(0x0028, 0x0028, 0x3, 0x02AC, 0x1, 0), + MX7ULP_PAD_PTC10__LPUART6_TX = IOMUX_PAD(0x0028, 0x0028, 0x4, 0x0264, 0x1, 0), + MX7ULP_PAD_PTC10__LPI2C6_HREQ = IOMUX_PAD(0x0028, 0x0028, 0x5, 0x02F8, 0x1, 0), + MX7ULP_PAD_PTC10__TPM7_CH3 = IOMUX_PAD(0x0028, 0x0028, 0x6, 0x02E8, 0x1, 0), + MX7ULP_PAD_PTC10__FB_AD10 = IOMUX_PAD(0x0028, 0x0028, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC10__TRACE_D5 = IOMUX_PAD(0x0028, 0x0028, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC10__DEBUG_MUX10 = IOMUX_PAD(0x0028, 0x0028, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC11__PTC11 = IOMUX_PAD(0x002C, 0x002C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC11__FXIO1_D7 = IOMUX_PAD(0x002C, 0x002C, 0x2, 0x0220, 0x1, 0), + MX7ULP_PAD_PTC11__LPSPI2_PCS0 = IOMUX_PAD(0x002C, 0x002C, 0x3, 0x029C, 0x1, 0), + MX7ULP_PAD_PTC11__LPUART6_RX = IOMUX_PAD(0x002C, 0x002C, 0x4, 0x0260, 0x1, 0), + MX7ULP_PAD_PTC11__TPM7_CH4 = IOMUX_PAD(0x002C, 0x002C, 0x6, 0x02EC, 0x1, 0), + MX7ULP_PAD_PTC11__FB_AD11 = IOMUX_PAD(0x002C, 0x002C, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC11__TRACE_D4 = IOMUX_PAD(0x002C, 0x002C, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC11__DEBUG_MUX11 = IOMUX_PAD(0x002C, 0x002C, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC12__PTC12 = IOMUX_PAD(0x0030, 0x0030, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC12__FXIO1_D8 = IOMUX_PAD(0x0030, 0x0030, 0x2, 0x0224, 0x1, 0), + MX7ULP_PAD_PTC12__LPSPI3_PCS1 = IOMUX_PAD(0x0030, 0x0030, 0x3, 0x0314, 0x1, 0), + MX7ULP_PAD_PTC12__LPUART7_CTS_b = IOMUX_PAD(0x0030, 0x0030, 0x4, 0x0268, 0x1, 0), + MX7ULP_PAD_PTC12__LPI2C7_SCL = IOMUX_PAD(0x0030, 0x0030, 0x5, 0x0308, 0x1, 0), + MX7ULP_PAD_PTC12__TPM7_CH5 = IOMUX_PAD(0x0030, 0x0030, 0x6, 0x02F0, 0x1, 0), + MX7ULP_PAD_PTC12__FB_AD12 = IOMUX_PAD(0x0030, 0x0030, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC12__TRACE_D3 = IOMUX_PAD(0x0030, 0x0030, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC12__DEBUG_MUX12 = IOMUX_PAD(0x0030, 0x0030, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC13__PTC13 = IOMUX_PAD(0x0034, 0x0034, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC13__FXIO1_D9 = IOMUX_PAD(0x0034, 0x0034, 0x2, 0x0228, 0x1, 0), + MX7ULP_PAD_PTC13__LPSPI3_PCS2 = IOMUX_PAD(0x0034, 0x0034, 0x3, 0x0318, 0x1, 0), + MX7ULP_PAD_PTC13__LPUART7_RTS_b = IOMUX_PAD(0x0034, 0x0034, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC13__LPI2C7_SDA = IOMUX_PAD(0x0034, 0x0034, 0x5, 0x030C, 0x1, 0), + MX7ULP_PAD_PTC13__TPM7_CLKIN = IOMUX_PAD(0x0034, 0x0034, 0x6, 0x02F4, 0x1, 0), + MX7ULP_PAD_PTC13__FB_AD13 = IOMUX_PAD(0x0034, 0x0034, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC13__TRACE_D2 = IOMUX_PAD(0x0034, 0x0034, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC13__DEBUG_MUX13 = IOMUX_PAD(0x0034, 0x0034, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC14__PTC14 = IOMUX_PAD(0x0038, 0x0038, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC14__FXIO1_D10 = IOMUX_PAD(0x0038, 0x0038, 0x2, 0x022C, 0x1, 0), + MX7ULP_PAD_PTC14__LPSPI3_PCS3 = IOMUX_PAD(0x0038, 0x0038, 0x3, 0x031C, 0x1, 0), + MX7ULP_PAD_PTC14__LPUART7_TX = IOMUX_PAD(0x0038, 0x0038, 0x4, 0x0270, 0x1, 0), + MX7ULP_PAD_PTC14__LPI2C7_HREQ = IOMUX_PAD(0x0038, 0x0038, 0x5, 0x0304, 0x1, 0), + MX7ULP_PAD_PTC14__TPM7_CH0 = IOMUX_PAD(0x0038, 0x0038, 0x6, 0x02DC, 0x1, 0), + MX7ULP_PAD_PTC14__FB_AD14 = IOMUX_PAD(0x0038, 0x0038, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC14__TRACE_D1 = IOMUX_PAD(0x0038, 0x0038, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC14__DEBUG_MUX14 = IOMUX_PAD(0x0038, 0x0038, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC15__PTC15 = IOMUX_PAD(0x003C, 0x003C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC15__FXIO1_D11 = IOMUX_PAD(0x003C, 0x003C, 0x2, 0x0230, 0x1, 0), + MX7ULP_PAD_PTC15__LPUART7_RX = IOMUX_PAD(0x003C, 0x003C, 0x4, 0x026C, 0x1, 0), + MX7ULP_PAD_PTC15__TPM7_CH1 = IOMUX_PAD(0x003C, 0x003C, 0x6, 0x02E0, 0x1, 0), + MX7ULP_PAD_PTC15__FB_AD15 = IOMUX_PAD(0x003C, 0x003C, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC15__TRACE_D0 = IOMUX_PAD(0x003C, 0x003C, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC15__DEBUG_MUX15 = IOMUX_PAD(0x003C, 0x003C, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC16__PTC16 = IOMUX_PAD(0x0040, 0x0040, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC16__FXIO1_D12 = IOMUX_PAD(0x0040, 0x0040, 0x2, 0x0234, 0x1, 0), + MX7ULP_PAD_PTC16__LPSPI3_SIN = IOMUX_PAD(0x0040, 0x0040, 0x3, 0x0324, 0x1, 0), + MX7ULP_PAD_PTC16__TPM7_CH2 = IOMUX_PAD(0x0040, 0x0040, 0x6, 0x02E4, 0x1, 0), + MX7ULP_PAD_PTC16__FB_ALE_FB_CS1_b_FB_TS_b = IOMUX_PAD(0x0040, 0x0040, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC16__TRACE_CLKOUT = IOMUX_PAD(0x0040, 0x0040, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC16__USB1_ULPI_OC2 = IOMUX_PAD(0x0040, 0x0040, 0xb, 0x0334, 0x1, 0), + MX7ULP_PAD_PTC17__PTC17 = IOMUX_PAD(0x0044, 0x0044, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC17__FXIO1_D13 = IOMUX_PAD(0x0044, 0x0044, 0x2, 0x0238, 0x1, 0), + MX7ULP_PAD_PTC17__LPSPI3_SOUT = IOMUX_PAD(0x0044, 0x0044, 0x3, 0x0328, 0x1, 0), + MX7ULP_PAD_PTC17__TPM6_CLKIN = IOMUX_PAD(0x0044, 0x0044, 0x6, 0x02D8, 0x1, 0), + MX7ULP_PAD_PTC17__FB_CS0_b = IOMUX_PAD(0x0044, 0x0044, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC17__DEBUG_MUX16 = IOMUX_PAD(0x0044, 0x0044, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC18__PTC18 = IOMUX_PAD(0x0048, 0x0048, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC18__FXIO1_D14 = IOMUX_PAD(0x0048, 0x0048, 0x2, 0x023C, 0x1, 0), + MX7ULP_PAD_PTC18__LPSPI3_SCK = IOMUX_PAD(0x0048, 0x0048, 0x3, 0x0320, 0x1, 0), + MX7ULP_PAD_PTC18__TPM6_CH0 = IOMUX_PAD(0x0048, 0x0048, 0x6, 0x02D0, 0x1, 0), + MX7ULP_PAD_PTC18__FB_OE_b = IOMUX_PAD(0x0048, 0x0048, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC18__DEBUG_MUX17 = IOMUX_PAD(0x0048, 0x0048, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC19__PTC19 = IOMUX_PAD(0x004C, 0x004C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC19__FXIO1_D15 = IOMUX_PAD(0x004C, 0x004C, 0x2, 0x0240, 0x1, 0), + MX7ULP_PAD_PTC19__LPSPI3_PCS0 = IOMUX_PAD(0x004C, 0x004C, 0x3, 0x0310, 0x1, 0), + MX7ULP_PAD_PTC19__TPM6_CH1 = IOMUX_PAD(0x004C, 0x004C, 0x6, 0x02D4, 0x1, 0), + MX7ULP_PAD_PTC19__FB_A16 = IOMUX_PAD(0x004C, 0x004C, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC19__USB1_ULPI_PWR2 = IOMUX_PAD(0x004C, 0x004C, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD0__PTD0 = IOMUX_PAD(0x0080, 0x0080, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD0__SDHC0_RESET_b = IOMUX_PAD(0x0080, 0x0080, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD0__DEBUG_MUX18 = IOMUX_PAD(0x0080, 0x0080, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD1__PTD1 = IOMUX_PAD(0x0084, 0x0084, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD1__SDHC0_CMD = IOMUX_PAD(0x0084, 0x0084, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD1__DEBUG_MUX19 = IOMUX_PAD(0x0084, 0x0084, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD2__PTD2 = IOMUX_PAD(0x0088, 0x0088, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD2__SDHC0_CLK = IOMUX_PAD(0x0088, 0x0088, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD2__DEBUG_MUX20 = IOMUX_PAD(0x0088, 0x0088, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD3__PTD3 = IOMUX_PAD(0x008C, 0x008C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD3__SDHC0_D7 = IOMUX_PAD(0x008C, 0x008C, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD3__DEBUG_MUX21 = IOMUX_PAD(0x008C, 0x008C, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD4__PTD4 = IOMUX_PAD(0x0090, 0x0090, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD4__SDHC0_D6 = IOMUX_PAD(0x0090, 0x0090, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD4__DEBUG_MUX22 = IOMUX_PAD(0x0090, 0x0090, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD5__PTD5 = IOMUX_PAD(0x0094, 0x0094, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD5__SDHC0_D5 = IOMUX_PAD(0x0094, 0x0094, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD5__DEBUG_MUX23 = IOMUX_PAD(0x0094, 0x0094, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD6__PTD6 = IOMUX_PAD(0x0098, 0x0098, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD6__SDHC0_D4 = IOMUX_PAD(0x0098, 0x0098, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD6__DEBUG_MUX24 = IOMUX_PAD(0x0098, 0x0098, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD7__PTD7 = IOMUX_PAD(0x009C, 0x009C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD7__SDHC0_D3 = IOMUX_PAD(0x009C, 0x009C, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD7__DEBUG_MUX25 = IOMUX_PAD(0x009C, 0x009C, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD8__PTD8 = IOMUX_PAD(0x00A0, 0x00A0, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD8__TPM4_CLKIN = IOMUX_PAD(0x00A0, 0x00A0, 0x6, 0x0298, 0x2, 0), + MX7ULP_PAD_PTD8__SDHC0_D2 = IOMUX_PAD(0x00A0, 0x00A0, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD8__DEBUG_MUX26 = IOMUX_PAD(0x00A0, 0x00A0, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD9__PTD9 = IOMUX_PAD(0x00A4, 0x00A4, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD9__TPM4_CH0 = IOMUX_PAD(0x00A4, 0x00A4, 0x6, 0x0280, 0x2, 0), + MX7ULP_PAD_PTD9__SDHC0_D1 = IOMUX_PAD(0x00A4, 0x00A4, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD9__DEBUG_MUX27 = IOMUX_PAD(0x00A4, 0x00A4, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD10__PTD10 = IOMUX_PAD(0x00A8, 0x00A8, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD10__TPM4_CH1 = IOMUX_PAD(0x00A8, 0x00A8, 0x6, 0x0284, 0x2, 0), + MX7ULP_PAD_PTD10__SDHC0_D0 = IOMUX_PAD(0x00A8, 0x00A8, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD10__DEBUG_MUX28 = IOMUX_PAD(0x00A8, 0x00A8, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD11__PTD11 = IOMUX_PAD(0x00AC, 0x00AC, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD11__TPM4_CH2 = IOMUX_PAD(0x00AC, 0x00AC, 0x6, 0x0288, 0x2, 0), + MX7ULP_PAD_PTD11__SDHC0_DQS = IOMUX_PAD(0x00AC, 0x00AC, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD11__DEBUG_MUX29 = IOMUX_PAD(0x00AC, 0x00AC, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE0__PTE0 = IOMUX_PAD(0x0100, 0x0100, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE0__FXIO1_D31 = IOMUX_PAD(0x0100, 0x0100, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE0__LPSPI2_PCS1 = IOMUX_PAD(0x0100, 0x0100, 0x3, 0x02A0, 0x2, 0), + MX7ULP_PAD_PTE0__LPUART4_CTS_b = IOMUX_PAD(0x0100, 0x0100, 0x4, 0x0244, 0x2, 0), + MX7ULP_PAD_PTE0__LPI2C4_SCL = IOMUX_PAD(0x0100, 0x0100, 0x5, 0x0278, 0x2, 0), + MX7ULP_PAD_PTE0__SDHC1_D1 = IOMUX_PAD(0x0100, 0x0100, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE0__FB_A25 = IOMUX_PAD(0x0100, 0x0100, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE0__DEBUG_MUX30 = IOMUX_PAD(0x0100, 0x0100, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE1__PTE1 = IOMUX_PAD(0x0104, 0x0104, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE1__FXIO1_D30 = IOMUX_PAD(0x0104, 0x0104, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE1__LPSPI2_PCS2 = IOMUX_PAD(0x0104, 0x0104, 0x3, 0x02A4, 0x2, 0), + MX7ULP_PAD_PTE1__LPUART4_RTS_b = IOMUX_PAD(0x0104, 0x0104, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE1__LPI2C4_SDA = IOMUX_PAD(0x0104, 0x0104, 0x5, 0x027C, 0x2, 0), + MX7ULP_PAD_PTE1__SDHC1_D0 = IOMUX_PAD(0x0104, 0x0104, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE1__FB_A26 = IOMUX_PAD(0x0104, 0x0104, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE1__DEBUG_MUX31 = IOMUX_PAD(0x0104, 0x0104, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE2__PTE2 = IOMUX_PAD(0x0108, 0x0108, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE2__FXIO1_D29 = IOMUX_PAD(0x0108, 0x0108, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE2__LPSPI2_PCS3 = IOMUX_PAD(0x0108, 0x0108, 0x3, 0x02A8, 0x2, 0), + MX7ULP_PAD_PTE2__LPUART4_TX = IOMUX_PAD(0x0108, 0x0108, 0x4, 0x024C, 0x2, 0), + MX7ULP_PAD_PTE2__LPI2C4_HREQ = IOMUX_PAD(0x0108, 0x0108, 0x5, 0x0274, 0x2, 0), + MX7ULP_PAD_PTE2__SDHC1_CLK = IOMUX_PAD(0x0108, 0x0108, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE2__DEBUG_MUX32 = IOMUX_PAD(0x0108, 0x0108, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE3__PTE3 = IOMUX_PAD(0x010C, 0x010C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE3__FXIO1_D28 = IOMUX_PAD(0x010C, 0x010C, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE3__LPUART4_RX = IOMUX_PAD(0x010C, 0x010C, 0x4, 0x0248, 0x2, 0), + MX7ULP_PAD_PTE3__TPM5_CH1 = IOMUX_PAD(0x010C, 0x010C, 0x6, 0x02C8, 0x2, 0), + MX7ULP_PAD_PTE3__SDHC1_CMD = IOMUX_PAD(0x010C, 0x010C, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE3__DEBUG_MUX33 = IOMUX_PAD(0x010C, 0x010C, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE4__PTE4 = IOMUX_PAD(0x0110, 0x0110, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE4__FXIO1_D27 = IOMUX_PAD(0x0110, 0x0110, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE4__LPSPI2_SIN = IOMUX_PAD(0x0110, 0x0110, 0x3, 0x02B0, 0x2, 0), + MX7ULP_PAD_PTE4__LPUART5_CTS_b = IOMUX_PAD(0x0110, 0x0110, 0x4, 0x0250, 0x2, 0), + MX7ULP_PAD_PTE4__LPI2C5_SCL = IOMUX_PAD(0x0110, 0x0110, 0x5, 0x02BC, 0x2, 0), + MX7ULP_PAD_PTE4__TPM5_CLKIN = IOMUX_PAD(0x0110, 0x0110, 0x6, 0x02CC, 0x2, 0), + MX7ULP_PAD_PTE4__SDHC1_D3 = IOMUX_PAD(0x0110, 0x0110, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE5__PTE5 = IOMUX_PAD(0x0114, 0x0114, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE5__FXIO1_D26 = IOMUX_PAD(0x0114, 0x0114, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE5__LPSPI2_SOUT = IOMUX_PAD(0x0114, 0x0114, 0x3, 0x02B4, 0x2, 0), + MX7ULP_PAD_PTE5__LPUART5_RTS_b = IOMUX_PAD(0x0114, 0x0114, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE5__LPI2C5_SDA = IOMUX_PAD(0x0114, 0x0114, 0x5, 0x02C0, 0x2, 0), + MX7ULP_PAD_PTE5__TPM5_CH0 = IOMUX_PAD(0x0114, 0x0114, 0x6, 0x02C4, 0x2, 0), + MX7ULP_PAD_PTE5__SDHC1_D2 = IOMUX_PAD(0x0114, 0x0114, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE6__PTE6 = IOMUX_PAD(0x0118, 0x0118, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE6__FXIO1_D25 = IOMUX_PAD(0x0118, 0x0118, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE6__LPSPI2_SCK = IOMUX_PAD(0x0118, 0x0118, 0x3, 0x02AC, 0x2, 0), + MX7ULP_PAD_PTE6__LPUART5_TX = IOMUX_PAD(0x0118, 0x0118, 0x4, 0x0258, 0x2, 0), + MX7ULP_PAD_PTE6__LPI2C5_HREQ = IOMUX_PAD(0x0118, 0x0118, 0x5, 0x02B8, 0x2, 0), + MX7ULP_PAD_PTE6__TPM7_CH3 = IOMUX_PAD(0x0118, 0x0118, 0x6, 0x02E8, 0x2, 0), + MX7ULP_PAD_PTE6__SDHC1_D4 = IOMUX_PAD(0x0118, 0x0118, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE6__FB_A17 = IOMUX_PAD(0x0118, 0x0118, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE6__USB0_OC = IOMUX_PAD(0x0118, 0x0118, 0xb, 0x0330, 0x1, 0), + MX7ULP_PAD_PTE7__PTE7 = IOMUX_PAD(0x011C, 0x011C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE7__FXIO1_D24 = IOMUX_PAD(0x011C, 0x011C, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE7__LPSPI2_PCS0 = IOMUX_PAD(0x011C, 0x011C, 0x3, 0x029C, 0x2, 0), + MX7ULP_PAD_PTE7__LPUART5_RX = IOMUX_PAD(0x011C, 0x011C, 0x4, 0x0254, 0x2, 0), + MX7ULP_PAD_PTE7__TPM7_CH4 = IOMUX_PAD(0x011C, 0x011C, 0x6, 0x02EC, 0x2, 0), + MX7ULP_PAD_PTE7__SDHC1_D5 = IOMUX_PAD(0x011C, 0x011C, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE7__FB_A18 = IOMUX_PAD(0x011C, 0x011C, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE7__TRACE_D7 = IOMUX_PAD(0x011C, 0x011C, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE7__USB0_PWR = IOMUX_PAD(0x011C, 0x011C, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE7__VIU_FID = IOMUX_PAD(0x011C, 0x011C, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE8__PTE8 = IOMUX_PAD(0x0120, 0x0120, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE8__TRACE_D6 = IOMUX_PAD(0x0120, 0x0120, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE8__VIU_D16 = IOMUX_PAD(0x0120, 0x0120, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE8__FXIO1_D23 = IOMUX_PAD(0x0120, 0x0120, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE8__LPSPI3_PCS1 = IOMUX_PAD(0x0120, 0x0120, 0x3, 0x0314, 0x2, 0), + MX7ULP_PAD_PTE8__LPUART6_CTS_b = IOMUX_PAD(0x0120, 0x0120, 0x4, 0x025C, 0x2, 0), + MX7ULP_PAD_PTE8__LPI2C6_SCL = IOMUX_PAD(0x0120, 0x0120, 0x5, 0x02FC, 0x2, 0), + MX7ULP_PAD_PTE8__TPM7_CH5 = IOMUX_PAD(0x0120, 0x0120, 0x6, 0x02F0, 0x2, 0), + MX7ULP_PAD_PTE8__SDHC1_WP = IOMUX_PAD(0x0120, 0x0120, 0x7, 0x0200, 0x1, 0), + MX7ULP_PAD_PTE8__SDHC1_D6 = IOMUX_PAD(0x0120, 0x0120, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE8__FB_CS3_b_FB_BE7_0_BLS31_24_b = IOMUX_PAD(0x0120, 0x0120, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE9__PTE9 = IOMUX_PAD(0x0124, 0x0124, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE9__TRACE_D5 = IOMUX_PAD(0x0124, 0x0124, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE9__VIU_D17 = IOMUX_PAD(0x0124, 0x0124, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE9__FXIO1_D22 = IOMUX_PAD(0x0124, 0x0124, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE9__LPSPI3_PCS2 = IOMUX_PAD(0x0124, 0x0124, 0x3, 0x0318, 0x2, 0), + MX7ULP_PAD_PTE9__LPUART6_RTS_b = IOMUX_PAD(0x0124, 0x0124, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE9__LPI2C6_SDA = IOMUX_PAD(0x0124, 0x0124, 0x5, 0x0300, 0x2, 0), + MX7ULP_PAD_PTE9__TPM7_CLKIN = IOMUX_PAD(0x0124, 0x0124, 0x6, 0x02F4, 0x2, 0), + MX7ULP_PAD_PTE9__SDHC1_CD = IOMUX_PAD(0x0124, 0x0124, 0x7, 0x032C, 0x1, 0), + MX7ULP_PAD_PTE9__SDHC1_D7 = IOMUX_PAD(0x0124, 0x0124, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE9__FB_TBST_b_FB_CS2_b_FB_BE15_8_BLS23_16_b = IOMUX_PAD(0x0124, 0x0124, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE10__PTE10 = IOMUX_PAD(0x0128, 0x0128, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE10__TRACE_D4 = IOMUX_PAD(0x0128, 0x0128, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE10__VIU_D18 = IOMUX_PAD(0x0128, 0x0128, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE10__FXIO1_D21 = IOMUX_PAD(0x0128, 0x0128, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE10__LPSPI3_PCS3 = IOMUX_PAD(0x0128, 0x0128, 0x3, 0x031C, 0x2, 0), + MX7ULP_PAD_PTE10__LPUART6_TX = IOMUX_PAD(0x0128, 0x0128, 0x4, 0x0264, 0x2, 0), + MX7ULP_PAD_PTE10__LPI2C6_HREQ = IOMUX_PAD(0x0128, 0x0128, 0x5, 0x02F8, 0x2, 0), + MX7ULP_PAD_PTE10__TPM7_CH0 = IOMUX_PAD(0x0128, 0x0128, 0x6, 0x02DC, 0x2, 0), + MX7ULP_PAD_PTE10__SDHC1_VS = IOMUX_PAD(0x0128, 0x0128, 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE10__SDHC1_DQS = IOMUX_PAD(0x0128, 0x0128, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE10__FB_A19 = IOMUX_PAD(0x0128, 0x0128, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE11__PTE11 = IOMUX_PAD(0x012C, 0x012C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE11__TRACE_D3 = IOMUX_PAD(0x012C, 0x012C, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE11__VIU_D19 = IOMUX_PAD(0x012C, 0x012C, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE11__FXIO1_D20 = IOMUX_PAD(0x012C, 0x012C, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE11__LPUART6_RX = IOMUX_PAD(0x012C, 0x012C, 0x4, 0x0260, 0x2, 0), + MX7ULP_PAD_PTE11__TPM7_CH1 = IOMUX_PAD(0x012C, 0x012C, 0x6, 0x02E0, 0x2, 0), + MX7ULP_PAD_PTE11__SDHC1_RESET_b = IOMUX_PAD(0x012C, 0x012C, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE11__FB_A20 = IOMUX_PAD(0x012C, 0x012C, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE12__PTE12 = IOMUX_PAD(0x0130, 0x0130, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE12__FXIO1_D19 = IOMUX_PAD(0x0130, 0x0130, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE12__LPSPI3_SIN = IOMUX_PAD(0x0130, 0x0130, 0x3, 0x0324, 0x2, 0), + MX7ULP_PAD_PTE12__LPUART7_CTS_b = IOMUX_PAD(0x0130, 0x0130, 0x4, 0x0268, 0x2, 0), + MX7ULP_PAD_PTE12__LPI2C7_SCL = IOMUX_PAD(0x0130, 0x0130, 0x5, 0x0308, 0x2, 0), + MX7ULP_PAD_PTE12__TPM7_CH2 = IOMUX_PAD(0x0130, 0x0130, 0x6, 0x02E4, 0x2, 0), + MX7ULP_PAD_PTE12__SDHC1_WP = IOMUX_PAD(0x0130, 0x0130, 0x8, 0x0200, 0x2, 0), + MX7ULP_PAD_PTE12__FB_A21 = IOMUX_PAD(0x0130, 0x0130, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE12__TRACE_D2 = IOMUX_PAD(0x0130, 0x0130, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE12__USB1_ULPI_OC2 = IOMUX_PAD(0x0130, 0x0130, 0xb, 0x0334, 0x2, 0), + MX7ULP_PAD_PTE12__VIU_D20 = IOMUX_PAD(0x0130, 0x0130, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE13__PTE13 = IOMUX_PAD(0x0134, 0x0134, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE13__FXIO1_D18 = IOMUX_PAD(0x0134, 0x0134, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE13__LPSPI3_SOUT = IOMUX_PAD(0x0134, 0x0134, 0x3, 0x0328, 0x2, 0), + MX7ULP_PAD_PTE13__LPUART7_RTS_b = IOMUX_PAD(0x0134, 0x0134, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE13__LPI2C7_SDA = IOMUX_PAD(0x0134, 0x0134, 0x5, 0x030C, 0x2, 0), + MX7ULP_PAD_PTE13__TPM6_CLKIN = IOMUX_PAD(0x0134, 0x0134, 0x6, 0x02D8, 0x2, 0), + MX7ULP_PAD_PTE13__SDHC1_CD = IOMUX_PAD(0x0134, 0x0134, 0x8, 0x032C, 0x2, 0), + MX7ULP_PAD_PTE13__FB_A22 = IOMUX_PAD(0x0134, 0x0134, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE13__TRACE_D1 = IOMUX_PAD(0x0134, 0x0134, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE13__USB1_ULPI_PWR2 = IOMUX_PAD(0x0134, 0x0134, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE13__VIU_D21 = IOMUX_PAD(0x0134, 0x0134, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE14__PTE14 = IOMUX_PAD(0x0138, 0x0138, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE14__FXIO1_D17 = IOMUX_PAD(0x0138, 0x0138, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE14__LPSPI3_SCK = IOMUX_PAD(0x0138, 0x0138, 0x3, 0x0320, 0x2, 0), + MX7ULP_PAD_PTE14__LPUART7_TX = IOMUX_PAD(0x0138, 0x0138, 0x4, 0x0270, 0x2, 0), + MX7ULP_PAD_PTE14__LPI2C7_HREQ = IOMUX_PAD(0x0138, 0x0138, 0x5, 0x0304, 0x2, 0), + MX7ULP_PAD_PTE14__TPM6_CH0 = IOMUX_PAD(0x0138, 0x0138, 0x6, 0x02D0, 0x2, 0), + MX7ULP_PAD_PTE14__SDHC1_VS = IOMUX_PAD(0x0138, 0x0138, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE14__FB_A23 = IOMUX_PAD(0x0138, 0x0138, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE14__TRACE_D0 = IOMUX_PAD(0x0138, 0x0138, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE14__USB0_OC = IOMUX_PAD(0x0138, 0x0138, 0xb, 0x0330, 0x2, 0), + MX7ULP_PAD_PTE14__VIU_D22 = IOMUX_PAD(0x0138, 0x0138, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE15__PTE15 = IOMUX_PAD(0x013C, 0x013C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE15__FXIO1_D16 = IOMUX_PAD(0x013C, 0x013C, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE15__LPSPI3_PCS0 = IOMUX_PAD(0x013C, 0x013C, 0x3, 0x0310, 0x2, 0), + MX7ULP_PAD_PTE15__LPUART7_RX = IOMUX_PAD(0x013C, 0x013C, 0x4, 0x026C, 0x2, 0), + MX7ULP_PAD_PTE15__TPM6_CH1 = IOMUX_PAD(0x013C, 0x013C, 0x6, 0x02D4, 0x2, 0), + MX7ULP_PAD_PTE15__FB_A24 = IOMUX_PAD(0x013C, 0x013C, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE15__TRACE_CLKOUT = IOMUX_PAD(0x013C, 0x013C, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE15__USB0_PWR = IOMUX_PAD(0x013C, 0x013C, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE15__VIU_D23 = IOMUX_PAD(0x013C, 0x013C, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF0__PTF0 = IOMUX_PAD(0x0180, 0x0180, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF0__LPUART4_CTS_b = IOMUX_PAD(0x0180, 0x0180, 0x4, 0x0244, 0x3, 0), + MX7ULP_PAD_PTF0__LPI2C4_SCL = IOMUX_PAD(0x0180, 0x0180, 0x5, 0x0278, 0x3, 0), + MX7ULP_PAD_PTF0__TPM4_CLKIN = IOMUX_PAD(0x0180, 0x0180, 0x6, 0x0298, 0x3, 0), + MX7ULP_PAD_PTF0__FB_RW_b = IOMUX_PAD(0x0180, 0x0180, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF0__VIU_DE = IOMUX_PAD(0x0180, 0x0180, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF1__PTF1 = IOMUX_PAD(0x0184, 0x0184, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF1__LPUART4_RTS_b = IOMUX_PAD(0x0184, 0x0184, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF1__LPI2C4_SDA = IOMUX_PAD(0x0184, 0x0184, 0x5, 0x027C, 0x3, 0), + MX7ULP_PAD_PTF1__TPM4_CH0 = IOMUX_PAD(0x0184, 0x0184, 0x6, 0x0280, 0x3, 0), + MX7ULP_PAD_PTF1__CLKOUT = IOMUX_PAD(0x0184, 0x0184, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF1__VIU_HSYNC = IOMUX_PAD(0x0184, 0x0184, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF2__PTF2 = IOMUX_PAD(0x0188, 0x0188, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF2__LPUART4_TX = IOMUX_PAD(0x0188, 0x0188, 0x4, 0x024C, 0x3, 0), + MX7ULP_PAD_PTF2__LPI2C4_HREQ = IOMUX_PAD(0x0188, 0x0188, 0x5, 0x0274, 0x3, 0), + MX7ULP_PAD_PTF2__TPM4_CH1 = IOMUX_PAD(0x0188, 0x0188, 0x6, 0x0284, 0x3, 0), + MX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_b_FB_BE23_16_BLS15_8_b = IOMUX_PAD(0x0188, 0x0188, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF2__VIU_VSYNC = IOMUX_PAD(0x0188, 0x0188, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF3__PTF3 = IOMUX_PAD(0x018C, 0x018C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF3__LPUART4_RX = IOMUX_PAD(0x018C, 0x018C, 0x4, 0x0248, 0x3, 0), + MX7ULP_PAD_PTF3__TPM4_CH2 = IOMUX_PAD(0x018C, 0x018C, 0x6, 0x0288, 0x3, 0), + MX7ULP_PAD_PTF3__FB_AD16 = IOMUX_PAD(0x018C, 0x018C, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF3__VIU_PCLK = IOMUX_PAD(0x018C, 0x018C, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF4__PTF4 = IOMUX_PAD(0x0190, 0x0190, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF4__FXIO1_D0 = IOMUX_PAD(0x0190, 0x0190, 0x2, 0x0204, 0x2, 0), + MX7ULP_PAD_PTF4__LPSPI2_PCS1 = IOMUX_PAD(0x0190, 0x0190, 0x3, 0x02A0, 0x3, 0), + MX7ULP_PAD_PTF4__LPUART5_CTS_b = IOMUX_PAD(0x0190, 0x0190, 0x4, 0x0250, 0x3, 0), + MX7ULP_PAD_PTF4__LPI2C5_SCL = IOMUX_PAD(0x0190, 0x0190, 0x5, 0x02BC, 0x3, 0), + MX7ULP_PAD_PTF4__TPM4_CH3 = IOMUX_PAD(0x0190, 0x0190, 0x6, 0x028C, 0x2, 0), + MX7ULP_PAD_PTF4__FB_AD17 = IOMUX_PAD(0x0190, 0x0190, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF4__VIU_D0 = IOMUX_PAD(0x0190, 0x0190, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF5__PTF5 = IOMUX_PAD(0x0194, 0x0194, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF5__FXIO1_D1 = IOMUX_PAD(0x0194, 0x0194, 0x2, 0x0208, 0x2, 0), + MX7ULP_PAD_PTF5__LPSPI2_PCS2 = IOMUX_PAD(0x0194, 0x0194, 0x3, 0x02A4, 0x3, 0), + MX7ULP_PAD_PTF5__LPUART5_RTS_b = IOMUX_PAD(0x0194, 0x0194, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF5__LPI2C5_SDA = IOMUX_PAD(0x0194, 0x0194, 0x5, 0x02C0, 0x3, 0), + MX7ULP_PAD_PTF5__TPM4_CH4 = IOMUX_PAD(0x0194, 0x0194, 0x6, 0x0290, 0x2, 0), + MX7ULP_PAD_PTF5__FB_AD18 = IOMUX_PAD(0x0194, 0x0194, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF5__VIU_D1 = IOMUX_PAD(0x0194, 0x0194, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF6__PTF6 = IOMUX_PAD(0x0198, 0x0198, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF6__FXIO1_D2 = IOMUX_PAD(0x0198, 0x0198, 0x2, 0x020C, 0x2, 0), + MX7ULP_PAD_PTF6__LPSPI2_PCS3 = IOMUX_PAD(0x0198, 0x0198, 0x3, 0x02A8, 0x3, 0), + MX7ULP_PAD_PTF6__LPUART5_TX = IOMUX_PAD(0x0198, 0x0198, 0x4, 0x0258, 0x3, 0), + MX7ULP_PAD_PTF6__LPI2C5_HREQ = IOMUX_PAD(0x0198, 0x0198, 0x5, 0x02B8, 0x3, 0), + MX7ULP_PAD_PTF6__TPM4_CH5 = IOMUX_PAD(0x0198, 0x0198, 0x6, 0x0294, 0x2, 0), + MX7ULP_PAD_PTF6__FB_AD19 = IOMUX_PAD(0x0198, 0x0198, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF6__VIU_D2 = IOMUX_PAD(0x0198, 0x0198, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF7__PTF7 = IOMUX_PAD(0x019C, 0x019C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF7__FXIO1_D3 = IOMUX_PAD(0x019C, 0x019C, 0x2, 0x0210, 0x2, 0), + MX7ULP_PAD_PTF7__LPUART5_RX = IOMUX_PAD(0x019C, 0x019C, 0x4, 0x0254, 0x3, 0), + MX7ULP_PAD_PTF7__TPM5_CH1 = IOMUX_PAD(0x019C, 0x019C, 0x6, 0x02C8, 0x3, 0), + MX7ULP_PAD_PTF7__FB_AD20 = IOMUX_PAD(0x019C, 0x019C, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF7__VIU_D3 = IOMUX_PAD(0x019C, 0x019C, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF8__PTF8 = IOMUX_PAD(0x01A0, 0x01A0, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF8__FXIO1_D4 = IOMUX_PAD(0x01A0, 0x01A0, 0x2, 0x0214, 0x2, 0), + MX7ULP_PAD_PTF8__LPSPI2_SIN = IOMUX_PAD(0x01A0, 0x01A0, 0x3, 0x02B0, 0x3, 0), + MX7ULP_PAD_PTF8__LPUART6_CTS_b = IOMUX_PAD(0x01A0, 0x01A0, 0x4, 0x025C, 0x3, 0), + MX7ULP_PAD_PTF8__LPI2C6_SCL = IOMUX_PAD(0x01A0, 0x01A0, 0x5, 0x02FC, 0x3, 0), + MX7ULP_PAD_PTF8__TPM5_CLKIN = IOMUX_PAD(0x01A0, 0x01A0, 0x6, 0x02CC, 0x3, 0), + MX7ULP_PAD_PTF8__FB_AD21 = IOMUX_PAD(0x01A0, 0x01A0, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF8__USB1_ULPI_CLK = IOMUX_PAD(0x01A0, 0x01A0, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF8__VIU_D4 = IOMUX_PAD(0x01A0, 0x01A0, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF9__PTF9 = IOMUX_PAD(0x01A4, 0x01A4, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF9__FXIO1_D5 = IOMUX_PAD(0x01A4, 0x01A4, 0x2, 0x0218, 0x2, 0), + MX7ULP_PAD_PTF9__LPSPI2_SOUT = IOMUX_PAD(0x01A4, 0x01A4, 0x3, 0x02B4, 0x3, 0), + MX7ULP_PAD_PTF9__LPUART6_RTS_b = IOMUX_PAD(0x01A4, 0x01A4, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF9__LPI2C6_SDA = IOMUX_PAD(0x01A4, 0x01A4, 0x5, 0x0300, 0x3, 0), + MX7ULP_PAD_PTF9__TPM5_CH0 = IOMUX_PAD(0x01A4, 0x01A4, 0x6, 0x02C4, 0x3, 0), + MX7ULP_PAD_PTF9__FB_AD22 = IOMUX_PAD(0x01A4, 0x01A4, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF9__USB1_ULPI_NXT = IOMUX_PAD(0x01A4, 0x01A4, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF9__VIU_D5 = IOMUX_PAD(0x01A4, 0x01A4, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF10__PTF10 = IOMUX_PAD(0x01A8, 0x01A8, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF10__FXIO1_D6 = IOMUX_PAD(0x01A8, 0x01A8, 0x2, 0x021C, 0x2, 0), + MX7ULP_PAD_PTF10__LPSPI2_SCK = IOMUX_PAD(0x01A8, 0x01A8, 0x3, 0x02AC, 0x3, 0), + MX7ULP_PAD_PTF10__LPUART6_TX = IOMUX_PAD(0x01A8, 0x01A8, 0x4, 0x0264, 0x3, 0), + MX7ULP_PAD_PTF10__LPI2C6_HREQ = IOMUX_PAD(0x01A8, 0x01A8, 0x5, 0x02F8, 0x3, 0), + MX7ULP_PAD_PTF10__TPM7_CH3 = IOMUX_PAD(0x01A8, 0x01A8, 0x6, 0x02E8, 0x3, 0), + MX7ULP_PAD_PTF10__FB_AD23 = IOMUX_PAD(0x01A8, 0x01A8, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF10__USB1_ULPI_STP = IOMUX_PAD(0x01A8, 0x01A8, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF10__VIU_D6 = IOMUX_PAD(0x01A8, 0x01A8, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF11__PTF11 = IOMUX_PAD(0x01AC, 0x01AC, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF11__FXIO1_D7 = IOMUX_PAD(0x01AC, 0x01AC, 0x2, 0x0220, 0x2, 0), + MX7ULP_PAD_PTF11__LPSPI2_PCS0 = IOMUX_PAD(0x01AC, 0x01AC, 0x3, 0x029C, 0x3, 0), + MX7ULP_PAD_PTF11__LPUART6_RX = IOMUX_PAD(0x01AC, 0x01AC, 0x4, 0x0260, 0x3, 0), + MX7ULP_PAD_PTF11__TPM7_CH4 = IOMUX_PAD(0x01AC, 0x01AC, 0x6, 0x02EC, 0x3, 0), + MX7ULP_PAD_PTF11__FB_CS4_b_FB_TSIZ0_FB_BE31_24_BLS7_0_b = IOMUX_PAD(0x01AC, 0x01AC, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF11__USB1_ULPI_DIR = IOMUX_PAD(0x01AC, 0x01AC, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF11__VIU_D7 = IOMUX_PAD(0x01AC, 0x01AC, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF12__PTF12 = IOMUX_PAD(0x01B0, 0x01B0, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF12__FXIO1_D8 = IOMUX_PAD(0x01B0, 0x01B0, 0x2, 0x0224, 0x2, 0), + MX7ULP_PAD_PTF12__LPSPI3_PCS1 = IOMUX_PAD(0x01B0, 0x01B0, 0x3, 0x0314, 0x3, 0), + MX7ULP_PAD_PTF12__LPUART7_CTS_b = IOMUX_PAD(0x01B0, 0x01B0, 0x4, 0x0268, 0x3, 0), + MX7ULP_PAD_PTF12__LPI2C7_SCL = IOMUX_PAD(0x01B0, 0x01B0, 0x5, 0x0308, 0x3, 0), + MX7ULP_PAD_PTF12__TPM7_CH5 = IOMUX_PAD(0x01B0, 0x01B0, 0x6, 0x02F0, 0x3, 0), + MX7ULP_PAD_PTF12__FB_AD24 = IOMUX_PAD(0x01B0, 0x01B0, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF12__USB1_ULPI_DATA0 = IOMUX_PAD(0x01B0, 0x01B0, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF12__VIU_D8 = IOMUX_PAD(0x01B0, 0x01B0, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF13__PTF13 = IOMUX_PAD(0x01B4, 0x01B4, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF13__FXIO1_D9 = IOMUX_PAD(0x01B4, 0x01B4, 0x2, 0x0228, 0x2, 0), + MX7ULP_PAD_PTF13__LPSPI3_PCS2 = IOMUX_PAD(0x01B4, 0x01B4, 0x3, 0x0318, 0x3, 0), + MX7ULP_PAD_PTF13__LPUART7_RTS_b = IOMUX_PAD(0x01B4, 0x01B4, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF13__LPI2C7_SDA = IOMUX_PAD(0x01B4, 0x01B4, 0x5, 0x030C, 0x3, 0), + MX7ULP_PAD_PTF13__TPM7_CLKIN = IOMUX_PAD(0x01B4, 0x01B4, 0x6, 0x02F4, 0x3, 0), + MX7ULP_PAD_PTF13__FB_AD25 = IOMUX_PAD(0x01B4, 0x01B4, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF13__USB1_ULPI_DATA1 = IOMUX_PAD(0x01B4, 0x01B4, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF13__VIU_D9 = IOMUX_PAD(0x01B4, 0x01B4, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF14__PTF14 = IOMUX_PAD(0x01B8, 0x01B8, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF14__FXIO1_D10 = IOMUX_PAD(0x01B8, 0x01B8, 0x2, 0x022C, 0x2, 0), + MX7ULP_PAD_PTF14__LPSPI3_PCS3 = IOMUX_PAD(0x01B8, 0x01B8, 0x3, 0x031C, 0x3, 0), + MX7ULP_PAD_PTF14__LPUART7_TX = IOMUX_PAD(0x01B8, 0x01B8, 0x4, 0x0270, 0x3, 0), + MX7ULP_PAD_PTF14__LPI2C7_HREQ = IOMUX_PAD(0x01B8, 0x01B8, 0x5, 0x0304, 0x3, 0), + MX7ULP_PAD_PTF14__TPM7_CH0 = IOMUX_PAD(0x01B8, 0x01B8, 0x6, 0x02DC, 0x3, 0), + MX7ULP_PAD_PTF14__FB_AD26 = IOMUX_PAD(0x01B8, 0x01B8, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF14__USB1_ULPI_DATA2 = IOMUX_PAD(0x01B8, 0x01B8, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF14__VIU_D10 = IOMUX_PAD(0x01B8, 0x01B8, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF15__PTF15 = IOMUX_PAD(0x01BC, 0x01BC, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF15__FXIO1_D11 = IOMUX_PAD(0x01BC, 0x01BC, 0x2, 0x0230, 0x2, 0), + MX7ULP_PAD_PTF15__LPUART7_RX = IOMUX_PAD(0x01BC, 0x01BC, 0x4, 0x026C, 0x3, 0), + MX7ULP_PAD_PTF15__TPM7_CH1 = IOMUX_PAD(0x01BC, 0x01BC, 0x6, 0x02E0, 0x3, 0), + MX7ULP_PAD_PTF15__FB_AD27 = IOMUX_PAD(0x01BC, 0x01BC, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF15__USB1_ULPI_DATA3 = IOMUX_PAD(0x01BC, 0x01BC, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF15__VIU_D11 = IOMUX_PAD(0x01BC, 0x01BC, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF16__PTF16 = IOMUX_PAD(0x01C0, 0x01C0, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF16__USB1_ULPI_DATA4 = IOMUX_PAD(0x01C0, 0x01C0, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF16__VIU_D12 = IOMUX_PAD(0x01C0, 0x01C0, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF16__FXIO1_D12 = IOMUX_PAD(0x01C0, 0x01C0, 0x2, 0x0234, 0x2, 0), + MX7ULP_PAD_PTF16__LPSPI3_SIN = IOMUX_PAD(0x01C0, 0x01C0, 0x3, 0x0324, 0x3, 0), + MX7ULP_PAD_PTF16__TPM7_CH2 = IOMUX_PAD(0x01C0, 0x01C0, 0x6, 0x02E4, 0x3, 0), + MX7ULP_PAD_PTF16__FB_AD28 = IOMUX_PAD(0x01C0, 0x01C0, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF17__PTF17 = IOMUX_PAD(0x01C4, 0x01C4, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF17__USB1_ULPI_DATA5 = IOMUX_PAD(0x01C4, 0x01C4, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF17__VIU_D13 = IOMUX_PAD(0x01C4, 0x01C4, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF17__FXIO1_D13 = IOMUX_PAD(0x01C4, 0x01C4, 0x2, 0x0238, 0x2, 0), + MX7ULP_PAD_PTF17__LPSPI3_SOUT = IOMUX_PAD(0x01C4, 0x01C4, 0x3, 0x0328, 0x3, 0), + MX7ULP_PAD_PTF17__TPM6_CLKIN = IOMUX_PAD(0x01C4, 0x01C4, 0x6, 0x02D8, 0x3, 0), + MX7ULP_PAD_PTF17__FB_AD29 = IOMUX_PAD(0x01C4, 0x01C4, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF18__PTF18 = IOMUX_PAD(0x01C8, 0x01C8, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF18__USB1_ULPI_DATA6 = IOMUX_PAD(0x01C8, 0x01C8, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF18__VIU_D14 = IOMUX_PAD(0x01C8, 0x01C8, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF18__FXIO1_D14 = IOMUX_PAD(0x01C8, 0x01C8, 0x2, 0x023C, 0x2, 0), + MX7ULP_PAD_PTF18__LPSPI3_SCK = IOMUX_PAD(0x01C8, 0x01C8, 0x3, 0x0320, 0x3, 0), + MX7ULP_PAD_PTF18__TPM6_CH0 = IOMUX_PAD(0x01C8, 0x01C8, 0x6, 0x02D0, 0x3, 0), + MX7ULP_PAD_PTF18__FB_AD30 = IOMUX_PAD(0x01C8, 0x01C8, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF19__PTF19 = IOMUX_PAD(0x01CC, 0x01CC, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF19__USB1_ULPI_DATA7 = IOMUX_PAD(0x01CC, 0x01CC, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF19__VIU_D15 = IOMUX_PAD(0x01CC, 0x01CC, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF19__FXIO1_D15 = IOMUX_PAD(0x01CC, 0x01CC, 0x2, 0x0240, 0x2, 0), + MX7ULP_PAD_PTF19__LPSPI3_PCS0 = IOMUX_PAD(0x01CC, 0x01CC, 0x3, 0x0310, 0x3, 0), + MX7ULP_PAD_PTF19__TPM6_CH1 = IOMUX_PAD(0x01CC, 0x01CC, 0x6, 0x02D4, 0x3, 0), + MX7ULP_PAD_PTF19__FB_AD31 = IOMUX_PAD(0x01CC, 0x01CC, 0x9, 0x0000, 0x0, 0), +}; +#endif /* __ASM_ARCH_IMX7ULP_PINS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S b/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S new file mode 100644 index 000000000..bcc804b58 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#include + +#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180 +#define ROM_VERSION_OFFSET 0x80 +#define ROM_API_HWCNFG_SETUP_OFFSET 0x08 + +plugin_start: + + push {r0-r4, lr} + + imx7ulp_ddr_setting + imx7ulp_clock_gating + imx7ulp_qos_setting + +normal_boot: + +/* + * The following is to fill in those arguments for this ROM function + * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data) + * This function is used to copy data from the storage media into DDR. + * start - Initial (possibly partial) image load address on entry. + * Final image load address on exit. + * bytes - Initial (possibly partial) image size on entry. + * Final image size on exit. + * boot_data - Initial @ref ivt Boot Data load address. + */ + adr r0, boot_data2 + adr r1, image_len2 + adr r2, boot_data2 + +/* + * check the _pu_irom_api_table for the address + */ +before_calling_rom___pu_irom_hwcnfg_setup: + ldr r3, =ROM_VERSION_OFFSET + ldr r4, [r3] + ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY + ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET] + blx r4 +after_calling_rom___pu_irom_hwcnfg_setup: + +/* + * To return to ROM from plugin, we need to fill in these argument. + * Here is what need to do: + * Need to construct the parameters for this function before return to ROM: + * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset) + */ + pop {r0-r4, lr} + push {r5} + ldr r5, boot_data2 + str r5, [r0] + ldr r5, image_len2 + str r5, [r1] + ldr r5, second_ivt_offset + str r5, [r2] + mov r0, #1 + pop {r5} + + /* return back to ROM code */ + bx lr + +/* make the following data right in the end of the output*/ +.ltorg + +#define FLASH_OFFSET 0x400 + +/* + * second_ivt_offset is the offset from the "second_ivt_header" to + * "image_copy_start", which involves FLASH_OFFSET, plus the first + * ivt_header, the plugin code size itself recorded by "ivt2_header" + */ + +second_ivt_offset: .long (ivt2_header + 0x2C + FLASH_OFFSET) + +/* + * The following is the second IVT header plus the second boot data + */ +ivt2_header: .long 0x0 +app2_code_jump_v: .long 0x0 +reserv3: .long 0x0 +dcd2_ptr: .long 0x0 +boot_data2_ptr: .long 0x0 +self_ptr2: .long 0x0 +app_code_csf2: .long 0x0 +reserv4: .long 0x0 +boot_data2: .long 0x0 +image_len2: .long 0x0 +plugin2: .long 0x0 diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/pcc.h b/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/pcc.h new file mode 100644 index 000000000..8f0d70062 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/pcc.h @@ -0,0 +1,371 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#ifndef _ASM_ARCH_PCC_H +#define _ASM_ARCH_PCC_H + +#include + +/* PCC2 */ + +enum pcc2_entry { + /* On-Platform (32 entries) */ + RSVD0_PCC2_SLOT = 0, + RSVD1_PCC2_SLOT = 1, + CA7_GIC_PCC2_SLOT = 2, + RSVD3_PCC2_SLOT = 3, + RSVD4_PCC2_SLOT = 4, + RSVD5_PCC2_SLOT = 5, + RSVD6_PCC2_SLOT = 6, + RSVD7_PCC2_SLOT = 7, + DMA1_PCC2_SLOT = 8, + RSVD9_PCC2_SLOT = 9, + RSVD10_PCC2_SLOT = 10, + RSVD11_PCC2_SLOT = 11, + RSVD12_PCC2_SLOT = 12, + RSVD13_PCC2_SLOT = 13, + RSVD14_PCC2_SLOT = 14, + RGPIO1_PCC2_SLOT = 15, + FLEXBUS0_PCC2_SLOT = 16, + RSVD17_PCC2_SLOT = 17, + RSVD18_PCC2_SLOT = 18, + RSVD19_PCC2_SLOT = 19, + RSVD20_PCC2_SLOT = 20, + RSVD21_PCC2_SLOT = 21, + RSVD22_PCC2_SLOT = 22, + RSVD23_PCC2_SLOT = 23, + RSVD24_PCC2_SLOT = 24, + RSVD25_PCC2_SLOT = 25, + RSVD26_PCC2_SLOT = 26, + SEMA42_1_PCC2_SLOT = 27, + RSVD28_PCC2_SLOT = 28, + RSVD29_PCC2_SLOT = 29, + RSVD30_PCC2_SLOT = 30, + RSVD31_PCC2_SLOT = 31, + + /* Off-Platform (96 entries) */ + RSVD32_PCC2_SLOT = 32, + DMA1_CH_MUX0_PCC2_SLOT = 33, + MU_B_PCC2_SLOT = 34, + SNVS_PCC2_SLOT = 35, + CAAM_PCC2_SLOT = 36, + LPTPM4_PCC2_SLOT = 37, + LPTPM5_PCC2_SLOT = 38, + LPIT1_PCC2_SLOT = 39, + RSVD40_PCC2_SLOT = 40, + LPSPI2_PCC2_SLOT = 41, + LPSPI3_PCC2_SLOT = 42, + LPI2C4_PCC2_SLOT = 43, + LPI2C5_PCC2_SLOT = 44, + LPUART4_PCC2_SLOT = 45, + LPUART5_PCC2_SLOT = 46, + RSVD47_PCC2_SLOT = 47, + RSVD48_PCC2_SLOT = 48, + FLEXIO1_PCC2_SLOT = 49, + RSVD50_PCC2_SLOT = 50, + USBOTG0_PCC2_SLOT = 51, + USBOTG1_PCC2_SLOT = 52, + USBPHY_PCC2_SLOT = 53, + USB_PL301_PCC2_SLOT = 54, + USDHC0_PCC2_SLOT = 55, + USDHC1_PCC2_SLOT = 56, + RSVD57_PCC2_SLOT = 57, + TRGMUX1_PCC2_SLOT = 58, + RSVD59_PCC2_SLOT = 59, + RSVD60_PCC2_SLOT = 60, + WDG1_PCC2_SLOT = 61, + SCG1_PCC2_SLOT = 62, + PCC2_PCC2_SLOT = 63, + PMC1_PCC2_SLOT = 64, + SMC1_PCC2_SLOT = 65, + RCM1_PCC2_SLOT = 66, + WDG2_PCC2_SLOT = 67, + RSVD68_PCC2_SLOT = 68, + TEST_SPACE1_PCC2_SLOT = 69, + TEST_SPACE2_PCC2_SLOT = 70, + TEST_SPACE3_PCC2_SLOT = 71, + RSVD72_PCC2_SLOT = 72, + RSVD73_PCC2_SLOT = 73, + RSVD74_PCC2_SLOT = 74, + RSVD75_PCC2_SLOT = 75, + RSVD76_PCC2_SLOT = 76, + RSVD77_PCC2_SLOT = 77, + RSVD78_PCC2_SLOT = 78, + RSVD79_PCC2_SLOT = 79, + RSVD80_PCC2_SLOT = 80, + RSVD81_PCC2_SLOT = 81, + RSVD82_PCC2_SLOT = 82, + RSVD83_PCC2_SLOT = 83, + RSVD84_PCC2_SLOT = 84, + RSVD85_PCC2_SLOT = 85, + RSVD86_PCC2_SLOT = 86, + RSVD87_PCC2_SLOT = 87, + RSVD88_PCC2_SLOT = 88, + RSVD89_PCC2_SLOT = 89, + RSVD90_PCC2_SLOT = 90, + RSVD91_PCC2_SLOT = 91, + RSVD92_PCC2_SLOT = 92, + RSVD93_PCC2_SLOT = 93, + RSVD94_PCC2_SLOT = 94, + RSVD95_PCC2_SLOT = 95, + RSVD96_PCC2_SLOT = 96, + RSVD97_PCC2_SLOT = 97, + RSVD98_PCC2_SLOT = 98, + RSVD99_PCC2_SLOT = 99, + RSVD100_PCC2_SLOT = 100, + RSVD101_PCC2_SLOT = 101, + RSVD102_PCC2_SLOT = 102, + RSVD103_PCC2_SLOT = 103, + RSVD104_PCC2_SLOT = 104, + RSVD105_PCC2_SLOT = 105, + RSVD106_PCC2_SLOT = 106, + RSVD107_PCC2_SLOT = 107, + RSVD108_PCC2_SLOT = 108, + RSVD109_PCC2_SLOT = 109, + RSVD110_PCC2_SLOT = 110, + RSVD111_PCC2_SLOT = 111, + RSVD112_PCC2_SLOT = 112, + RSVD113_PCC2_SLOT = 113, + RSVD114_PCC2_SLOT = 114, + RSVD115_PCC2_SLOT = 115, + RSVD116_PCC2_SLOT = 116, + RSVD117_PCC2_SLOT = 117, + RSVD118_PCC2_SLOT = 118, + RSVD119_PCC2_SLOT = 119, + RSVD120_PCC2_SLOT = 120, + RSVD121_PCC2_SLOT = 121, + RSVD122_PCC2_SLOT = 122, + RSVD123_PCC2_SLOT = 123, + RSVD124_PCC2_SLOT = 124, + RSVD125_PCC2_SLOT = 125, + RSVD126_PCC2_SLOT = 126, + RSVD127_PCC2_SLOT = 127, +}; + +enum pcc3_entry { + /* On-Platform (32 entries) */ + RSVD0_PCC3_SLOT = 0, + RSVD1_PCC3_SLOT = 1, + RSVD2_PCC3_SLOT = 2, + RSVD3_PCC3_SLOT = 3, + RSVD4_PCC3_SLOT = 4, + RSVD5_PCC3_SLOT = 5, + RSVD6_PCC3_SLOT = 6, + RSVD7_PCC3_SLOT = 7, + RSVD8_PCC3_SLOT = 8, + RSVD9_PCC3_SLOT = 9, + RSVD10_PCC3_SLOT = 10, + RSVD11_PCC3_SLOT = 11, + RSVD12_PCC3_SLOT = 12, + RSVD13_PCC3_SLOT = 13, + RSVD14_PCC3_SLOT = 14, + RSVD15_PCC3_SLOT = 15, + ROMCP1_PCC3_SLOT = 16, + RSVD17_PCC3_SLOT = 17, + RSVD18_PCC3_SLOT = 18, + RSVD19_PCC3_SLOT = 19, + RSVD20_PCC3_SLOT = 20, + RSVD21_PCC3_SLOT = 21, + RSVD22_PCC3_SLOT = 22, + RSVD23_PCC3_SLOT = 23, + RSVD24_PCC3_SLOT = 24, + RSVD25_PCC3_SLOT = 25, + RSVD26_PCC3_SLOT = 26, + RSVD27_PCC3_SLOT = 27, + RSVD28_PCC3_SLOT = 28, + RSVD29_PCC3_SLOT = 29, + RSVD30_PCC3_SLOT = 30, + RSVD31_PCC3_SLOT = 31, + + /* Off-Platform (96 entries) */ + RSVD32_PCC3_SLOT = 32, + LPTPM6_PCC3_SLOT = 33, + LPTPM7_PCC3_SLOT = 34, + RSVD35_PCC3_SLOT = 35, + LPI2C6_PCC3_SLOT = 36, + LPI2C7_PCC3_SLOT = 37, + LPUART6_PCC3_SLOT = 38, + LPUART7_PCC3_SLOT = 39, + VIU0_PCC3_SLOT = 40, + DSI0_PCC3_SLOT = 41, + LCDIF0_PCC3_SLOT = 42, + MMDC0_PCC3_SLOT = 43, + IOMUXC1_PCC3_SLOT = 44, + IOMUXC_DDR_PCC3_SLOT = 45, + PORTC_PCC3_SLOT = 46, + PORTD_PCC3_SLOT = 47, + PORTE_PCC3_SLOT = 48, + PORTF_PCC3_SLOT = 49, + RSVD50_PCC3_SLOT = 50, + PCC3_PCC3_SLOT = 51, + RSVD52_PCC3_SLOT = 52, + WKPU_PCC3_SLOT = 53, + RSVD54_PCC3_SLOT = 54, + RSVD55_PCC3_SLOT = 55, + RSVD56_PCC3_SLOT = 56, + RSVD57_PCC3_SLOT = 57, + RSVD58_PCC3_SLOT = 58, + RSVD59_PCC3_SLOT = 59, + RSVD60_PCC3_SLOT = 60, + RSVD61_PCC3_SLOT = 61, + RSVD62_PCC3_SLOT = 62, + RSVD63_PCC3_SLOT = 63, + RSVD64_PCC3_SLOT = 64, + RSVD65_PCC3_SLOT = 65, + RSVD66_PCC3_SLOT = 66, + RSVD67_PCC3_SLOT = 67, + RSVD68_PCC3_SLOT = 68, + RSVD69_PCC3_SLOT = 69, + RSVD70_PCC3_SLOT = 70, + RSVD71_PCC3_SLOT = 71, + RSVD72_PCC3_SLOT = 72, + RSVD73_PCC3_SLOT = 73, + RSVD74_PCC3_SLOT = 74, + RSVD75_PCC3_SLOT = 75, + RSVD76_PCC3_SLOT = 76, + RSVD77_PCC3_SLOT = 77, + RSVD78_PCC3_SLOT = 78, + RSVD79_PCC3_SLOT = 79, + RSVD80_PCC3_SLOT = 80, + GPU3D_PCC3_SLOT = 81, + GPU2D_PCC3_SLOT = 82, + RSVD83_PCC3_SLOT = 83, + RSVD84_PCC3_SLOT = 84, + RSVD85_PCC3_SLOT = 85, + RSVD86_PCC3_SLOT = 86, + RSVD87_PCC3_SLOT = 87, + RSVD88_PCC3_SLOT = 88, + RSVD89_PCC3_SLOT = 89, + RSVD90_PCC3_SLOT = 90, + RSVD91_PCC3_SLOT = 91, + RSVD92_PCC3_SLOT = 92, + RSVD93_PCC3_SLOT = 93, + RSVD94_PCC3_SLOT = 94, + RSVD95_PCC3_SLOT = 95, + RSVD96_PCC3_SLOT = 96, + RSVD97_PCC3_SLOT = 97, + RSVD98_PCC3_SLOT = 98, + RSVD99_PCC3_SLOT = 99, + RSVD100_PCC3_SLOT = 100, + RSVD101_PCC3_SLOT = 101, + RSVD102_PCC3_SLOT = 102, + RSVD103_PCC3_SLOT = 103, + RSVD104_PCC3_SLOT = 104, + RSVD105_PCC3_SLOT = 105, + RSVD106_PCC3_SLOT = 106, + RSVD107_PCC3_SLOT = 107, + RSVD108_PCC3_SLOT = 108, + RSVD109_PCC3_SLOT = 109, + RSVD110_PCC3_SLOT = 110, + RSVD111_PCC3_SLOT = 111, + RSVD112_PCC3_SLOT = 112, + RSVD113_PCC3_SLOT = 113, + RSVD114_PCC3_SLOT = 114, + RSVD115_PCC3_SLOT = 115, + RSVD116_PCC3_SLOT = 116, + RSVD117_PCC3_SLOT = 117, + RSVD118_PCC3_SLOT = 118, + RSVD119_PCC3_SLOT = 119, + RSVD120_PCC3_SLOT = 120, + RSVD121_PCC3_SLOT = 121, + RSVD122_PCC3_SLOT = 122, + RSVD123_PCC3_SLOT = 123, + RSVD124_PCC3_SLOT = 124, + RSVD125_PCC3_SLOT = 125, + RSVD126_PCC3_SLOT = 126, + RSVD127_PCC3_SLOT = 127, +}; + + +/* PCC registers */ +#define PCC_PR_OFFSET 31 +#define PCC_PR_MASK (0x1 << PCC_PR_OFFSET) +#define PCC_CGC_OFFSET 30 +#define PCC_CGC_MASK (0x1 << PCC_CGC_OFFSET) +#define PCC_INUSE_OFFSET 29 +#define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET) +#define PCC_PCS_OFFSET 24 +#define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET) +#define PCC_FRAC_OFFSET 3 +#define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET) +#define PCC_PCD_OFFSET 0 +#define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET) + + +enum pcc_clksrc_type { + CLKSRC_PER_PLAT = 0, + CLKSRC_PER_BUS = 1, + CLKSRC_NO_PCS = 2, +}; + +enum pcc_div_type { + PCC_HAS_DIV, + PCC_NO_DIV, +}; + +/* All peripheral clocks on A7 PCCs */ +enum pcc_clk { + /*PCC2 clocks*/ + PER_CLK_DMA1 = 0, + PER_CLK_RGPIO2P1, + PER_CLK_FLEXBUS, + PER_CLK_SEMA42_1, + PER_CLK_DMA_MUX1, + PER_CLK_SNVS, + PER_CLK_CAAM, + PER_CLK_LPTPM4, + PER_CLK_LPTPM5, + PER_CLK_LPIT1, + PER_CLK_LPSPI2, + PER_CLK_LPSPI3, + PER_CLK_LPI2C4, + PER_CLK_LPI2C5, + PER_CLK_LPUART4, + PER_CLK_LPUART5, + PER_CLK_FLEXIO1, + PER_CLK_USB0, + PER_CLK_USB1, + PER_CLK_USB_PHY, + PER_CLK_USB_PL301, + PER_CLK_USDHC0, + PER_CLK_USDHC1, + PER_CLK_WDG1, + PER_CLK_WDG2, + + /*PCC3 clocks*/ + PER_CLK_LPTPM6, + PER_CLK_LPTPM7, + PER_CLK_LPI2C6, + PER_CLK_LPI2C7, + PER_CLK_LPUART6, + PER_CLK_LPUART7, + PER_CLK_VIU, + PER_CLK_DSI, + PER_CLK_LCDIF, + PER_CLK_MMDC, + PER_CLK_PCTLC, + PER_CLK_PCTLD, + PER_CLK_PCTLE, + PER_CLK_PCTLF, + PER_CLK_GPU3D, + PER_CLK_GPU2D, +}; + + +/* This structure keeps info for each pcc slot */ +struct pcc_entry { + u32 pcc_base; + u32 pcc_slot; + enum pcc_clksrc_type clksrc; + enum pcc_div_type div; +}; + +int pcc_clock_enable(enum pcc_clk clk, bool enable); +int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src); +int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div); +bool pcc_clock_is_enable(enum pcc_clk clk); +int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src); +u32 pcc_clock_get_rate(enum pcc_clk clk); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/scg.h b/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/scg.h new file mode 100644 index 000000000..3b5b7f680 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/scg.h @@ -0,0 +1,339 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#ifndef _ASM_ARCH_SCG_H +#define _ASM_ARCH_SCG_H + +#ifdef CONFIG_CLK_DEBUG +#define clk_debug(fmt, args...) printf(fmt, ##args) +#else +#define clk_debug(fmt, args...) +#endif + +#define SCG_CCR_SCS_SHIFT (24) +#define SCG_CCR_SCS_MASK ((0xFUL) << SCG_CCR_SCS_SHIFT) +#define SCG_CCR_DIVCORE_SHIFT (16) +#define SCG_CCR_DIVCORE_MASK ((0xFUL) << SCG_CCR_DIVCORE_SHIFT) +#define SCG_CCR_DIVPLAT_SHIFT (12) +#define SCG_CCR_DIVPLAT_MASK ((0xFUL) << SCG_CCR_DIVPLAT_SHIFT) +#define SCG_CCR_DIVEXT_SHIFT (8) +#define SCG_CCR_DIVEXT_MASK ((0xFUL) << SCG_CCR_DIVEXT_SHIFT) +#define SCG_CCR_DIVBUS_SHIFT (4) +#define SCG_CCR_DIVBUS_MASK ((0xFUL) << SCG_CCR_DIVBUS_SHIFT) +#define SCG_CCR_DIVSLOW_SHIFT (0) +#define SCG_CCR_DIVSLOW_MASK ((0xFUL) << SCG_CCR_DIVSLOW_SHIFT) + +/* SCG DDR Clock Control Register */ +#define SCG_DDRCCR_DDRCS_SHIFT (24) +#define SCG_DDRCCR_DDRCS_MASK ((0x1UL) << SCG_DDRCCR_DDRCS_SHIFT) + +#define SCG_DDRCCR_DDRDIV_SHIFT (0) +#define SCG_DDRCCR_DDRDIV_MASK ((0x7UL) << SCG_DDRCCR_DDRDIV_SHIFT) + +/* SCG NIC Clock Control Register */ +#define SCG_NICCCR_NICCS_SHIFT (28) +#define SCG_NICCCR_NICCS_MASK ((0x1UL) << SCG_NICCCR_NICCS_SHIFT) + +#define SCG_NICCCR_NIC0_DIV_SHIFT (24) +#define SCG_NICCCR_NIC0_DIV_MASK ((0xFUL) << SCG_NICCCR_NIC0_DIV_SHIFT) + +#define SCG_NICCCR_GPU_DIV_SHIFT (20) +#define SCG_NICCCR_GPU_DIV_MASK ((0xFUL) << SCG_NICCCR_GPU_DIV_SHIFT) + +#define SCG_NICCCR_NIC1_DIV_SHIFT (16) +#define SCG_NICCCR_NIC1_DIV_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIV_SHIFT) + +#define SCG_NICCCR_NIC1_DIVEXT_SHIFT (8) +#define SCG_NICCCR_NIC1_DIVEXT_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIVEXT_SHIFT) + +#define SCG_NICCCR_NIC1_DIVBUS_SHIFT (4) +#define SCG_NICCCR_NIC1_DIVBUS_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIVBUS_SHIFT) + +/* SCG NIC clock status register */ +#define SCG_NICCSR_NICCS_SHIFT (28) +#define SCG_NICCSR_NICCS_MASK ((0x1UL) << SCG_NICCSR_NICCS_SHIFT) + +#define SCG_NICCSR_NIC0DIV_SHIFT (24) +#define SCG_NICCSR_NIC0DIV_MASK ((0xFUL) << SCG_NICCSR_NIC0DIV_SHIFT) +#define SCG_NICCSR_GPUDIV_SHIFT (20) +#define SCG_NICCSR_GPUDIV_MASK ((0xFUL) << SCG_NICCSR_GPUDIV_SHIFT) +#define SCG_NICCSR_NIC1DIV_SHIFT (16) +#define SCG_NICCSR_NIC1DIV_MASK ((0xFUL) << SCG_NICCSR_NIC1DIV_SHIFT) +#define SCG_NICCSR_NIC1EXTDIV_SHIFT (8) +#define SCG_NICCSR_NIC1EXTDIV_MASK ((0xFUL) << SCG_NICCSR_NIC1EXTDIV_SHIFT) +#define SCG_NICCSR_NIC1BUSDIV_SHIFT (4) +#define SCG_NICCSR_NIC1BUSDIV_MASK ((0xFUL) << SCG_NICCSR_NIC1BUSDIV_SHIFT) + +/* SCG Slow IRC Control Status Register */ +#define SCG_SIRC_CSR_SIRCVLD_SHIFT (24) +#define SCG_SIRC_CSR_SIRCVLD_MASK ((0x1UL) << SCG_SIRC_CSR_SIRCVLD_SHIFT) + +#define SCG_SIRC_CSR_SIRCEN_SHIFT (0) +#define SCG_SIRC_CSR_SIRCEN_MASK ((0x1UL) << SCG_SIRC_CSR_SIRCEN_SHIFT) + +/* SCG Slow IRC Configuration Register */ +#define SCG_SIRCCFG_RANGE_SHIFT (0) +#define SCG_SIRCCFG_RANGE_MASK ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT) +#define SCG_SIRCCFG_RANGE_4M ((0x0UL) << SCG_SIRCCFG_RANGE_SHIFT) +#define SCG_SIRCCFG_RANGE_16M ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT) + +/* SCG Slow IRC Divide Register */ +#define SCG_SIRCDIV_DIV3_SHIFT (16) +#define SCG_SIRCDIV_DIV3_MASK ((0x7UL) << SCG_SIRCDIV_DIV3_SHIFT) + +#define SCG_SIRCDIV_DIV2_SHIFT (8) +#define SCG_SIRCDIV_DIV2_MASK ((0x7UL) << SCG_SIRCDIV_DIV2_SHIFT) + +#define SCG_SIRCDIV_DIV1_SHIFT (0) +#define SCG_SIRCDIV_DIV1_MASK ((0x7UL) << SCG_SIRCDIV_DIV1_SHIFT) +/* + * FIRC/SIRC DIV1 ==> xIRC_PLAT_CLK + * FIRC/SIRC DIV2 ==> xIRC_BUS_CLK + * FIRC/SIRC DIV3 ==> xIRC_SLOW_CLK + */ + +/* SCG Fast IRC Control Status Register */ +#define SCG_FIRC_CSR_FIRCVLD_SHIFT (24) +#define SCG_FIRC_CSR_FIRCVLD_MASK ((0x1UL) << SCG_FIRC_CSR_FIRCVLD_SHIFT) + +#define SCG_FIRC_CSR_FIRCEN_SHIFT (0) +#define SCG_FIRC_CSR_FIRCEN_MASK ((0x1UL) << SCG_FIRC_CSR_FIRCEN_SHIFT) + +/* SCG Fast IRC Divide Register */ +#define SCG_FIRCDIV_DIV3_SHIFT (16) +#define SCG_FIRCDIV_DIV3_MASK ((0x7UL) << SCG_FIRCDIV_DIV3_SHIFT) + +#define SCG_FIRCDIV_DIV2_SHIFT (8) +#define SCG_FIRCDIV_DIV2_MASK ((0x7UL) << SCG_FIRCDIV_DIV2_SHIFT) + +#define SCG_FIRCDIV_DIV1_SHIFT (0) +#define SCG_FIRCDIV_DIV1_MASK ((0x7UL) << SCG_FIRCDIV_DIV1_SHIFT) + +#define SCG_FIRCCFG_RANGE_SHIFT (0) +#define SCG_FIRCCFG_RANGE_MASK ((0x3UL) << SCG_FIRCCFG_RANGE_SHIFT) + +#define SCG_FIRCCFG_RANGE_SHIFT (0) +#define SCG_FIRCCFG_RANGE_48M ((0x0UL) << SCG_FIRCCFG_RANGE_SHIFT) + +/* SCG System OSC Control Status Register */ +#define SCG_SOSC_CSR_SOSCVLD_SHIFT (24) +#define SCG_SOSC_CSR_SOSCVLD_MASK ((0x1UL) << SCG_SOSC_CSR_SOSCVLD_SHIFT) + +/* SCG Fast IRC Divide Register */ +#define SCG_SOSCDIV_DIV3_SHIFT (16) +#define SCG_SOSCDIV_DIV3_MASK ((0x7UL) << SCG_SOSCDIV_DIV3_SHIFT) + +#define SCG_SOSCDIV_DIV2_SHIFT (8) +#define SCG_SOSCDIV_DIV2_MASK ((0x7UL) << SCG_SOSCDIV_DIV2_SHIFT) + +#define SCG_SOSCDIV_DIV1_SHIFT (0) +#define SCG_SOSCDIV_DIV1_MASK ((0x7UL) << SCG_SOSCDIV_DIV1_SHIFT) + +/* SCG RTC OSC Control Status Register */ +#define SCG_ROSC_CSR_ROSCVLD_SHIFT (24) +#define SCG_ROSC_CSR_ROSCVLD_MASK ((0x1UL) << SCG_ROSC_CSR_ROSCVLD_SHIFT) + +#define SCG_SPLL_CSR_SPLLVLD_SHIFT (24) +#define SCG_SPLL_CSR_SPLLVLD_MASK ((0x1UL) << SCG_SPLL_CSR_SPLLVLD_SHIFT) +#define SCG_SPLL_CSR_SPLLEN_SHIFT (0) +#define SCG_SPLL_CSR_SPLLEN_MASK ((0x1UL) << SCG_SPLL_CSR_SPLLEN_SHIFT) +#define SCG_APLL_CSR_APLLEN_SHIFT (0) +#define SCG_APLL_CSR_APLLEN_MASK (0x1UL) +#define SCG_APLL_CSR_APLLVLD_MASK (0x01000000) + +#define SCG_UPLL_CSR_UPLLVLD_MASK (0x01000000) + + +#define SCG_PLL_PFD3_GATE_MASK (0x80000000) +#define SCG_PLL_PFD2_GATE_MASK (0x00800000) +#define SCG_PLL_PFD1_GATE_MASK (0x00008000) +#define SCG_PLL_PFD0_GATE_MASK (0x00000080) +#define SCG_PLL_PFD3_VALID_MASK (0x40000000) +#define SCG_PLL_PFD2_VALID_MASK (0x00400000) +#define SCG_PLL_PFD1_VALID_MASK (0x00004000) +#define SCG_PLL_PFD0_VALID_MASK (0x00000040) + +#define SCG_PLL_PFD0_FRAC_SHIFT (0) +#define SCG_PLL_PFD0_FRAC_MASK ((0x3F) << SCG_PLL_PFD0_FRAC_SHIFT) +#define SCG_PLL_PFD1_FRAC_SHIFT (8) +#define SCG_PLL_PFD1_FRAC_MASK ((0x3F) << SCG_PLL_PFD1_FRAC_SHIFT) +#define SCG_PLL_PFD2_FRAC_SHIFT (16) +#define SCG_PLL_PFD2_FRAC_MASK ((0x3F) << SCG_PLL_PFD2_FRAC_SHIFT) +#define SCG_PLL_PFD3_FRAC_SHIFT (24) +#define SCG_PLL_PFD3_FRAC_MASK ((0x3F) << SCG_PLL_PFD3_FRAC_SHIFT) + +#define SCG_PLL_CFG_POSTDIV2_SHIFT (28) +#define SCG_PLL_CFG_POSTDIV2_MASK ((0xFUL) << SCG_PLL_CFG_POSTDIV2_SHIFT) +#define SCG_PLL_CFG_POSTDIV1_SHIFT (24) +#define SCG_PLL_CFG_POSTDIV1_MASK ((0xFUL) << SCG_PLL_CFG_POSTDIV1_SHIFT) +#define SCG_PLL_CFG_MULT_SHIFT (16) +#define SCG1_SPLL_CFG_MULT_MASK ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT) +#define SCG_APLL_CFG_MULT_MASK ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT) +#define SCG_PLL_CFG_PFDSEL_SHIFT (14) +#define SCG_PLL_CFG_PFDSEL_MASK ((0x3UL) << SCG_PLL_CFG_PFDSEL_SHIFT) +#define SCG_PLL_CFG_PREDIV_SHIFT (8) +#define SCG_PLL_CFG_PREDIV_MASK ((0x7UL) << SCG_PLL_CFG_PREDIV_SHIFT) +#define SCG_PLL_CFG_BYPASS_SHIFT (2) +/* 0: SPLL, 1: bypass */ +#define SCG_PLL_CFG_BYPASS_MASK ((0x1UL) << SCG_PLL_CFG_BYPASS_SHIFT) +#define SCG_PLL_CFG_PLLSEL_SHIFT (1) +/* 0: pll, 1: pfd */ +#define SCG_PLL_CFG_PLLSEL_MASK ((0x1UL) << SCG_PLL_CFG_PLLSEL_SHIFT) +#define SCG_PLL_CFG_CLKSRC_SHIFT (0) +/* 0: Sys-OSC, 1: FIRC */ +#define SCG_PLL_CFG_CLKSRC_MASK ((0x1UL) << SCG_PLL_CFG_CLKSRC_SHIFT) +#define SCG0_SPLL_CFG_MULT_SHIFT (17) +/* 0: Multiplier = 20, 1: Multiplier = 22 */ +#define SCG0_SPLL_CFG_MULT_MASK ((0x1UL) << SCG0_SPLL_CFG_MULT_SHIFT) + +#define PLL_USB_EN_USB_CLKS_MASK (0x01 << 6) +#define PLL_USB_PWR_MASK (0x01 << 12) +#define PLL_USB_ENABLE_MASK (0x01 << 13) +#define PLL_USB_BYPASS_MASK (0x01 << 16) +#define PLL_USB_REG_ENABLE_MASK (0x01 << 21) +#define PLL_USB_DIV_SEL_MASK (0x07 << 22) +#define PLL_USB_LOCK_MASK (0x01 << 31) + +enum scg_clk { + SCG_SOSC_CLK, + SCG_FIRC_CLK, + SCG_SIRC_CLK, + SCG_ROSC_CLK, + SCG_SIRC_DIV1_CLK, + SCG_SIRC_DIV2_CLK, + SCG_SIRC_DIV3_CLK, + SCG_FIRC_DIV1_CLK, + SCG_FIRC_DIV2_CLK, + SCG_FIRC_DIV3_CLK, + SCG_SOSC_DIV1_CLK, + SCG_SOSC_DIV2_CLK, + SCG_SOSC_DIV3_CLK, + SCG_CORE_CLK, + SCG_BUS_CLK, + SCG_SPLL_PFD0_CLK, + SCG_SPLL_PFD1_CLK, + SCG_SPLL_PFD2_CLK, + SCG_SPLL_PFD3_CLK, + SCG_DDR_CLK, + SCG_NIC0_CLK, + SCG_GPU_CLK, + SCG_NIC1_CLK, + SCG_NIC1_BUS_CLK, + SCG_NIC1_EXT_CLK, + SCG_APLL_PFD0_CLK, + SCG_APLL_PFD1_CLK, + SCG_APLL_PFD2_CLK, + SCG_APLL_PFD3_CLK, + USB_PLL_OUT, + MIPI_PLL_OUT +}; + +enum scg_sys_src { + SCG_SCS_SYS_OSC = 1, + SCG_SCS_SLOW_IRC, + SCG_SCS_FAST_IRC, + SCG_SCS_RTC_OSC, + SCG_SCS_AUX_PLL, + SCG_SCS_SYS_PLL, + SCG_SCS_USBPHY_PLL, +}; + +/* PLL supported by i.mx7ulp */ +enum pll_clocks { + PLL_M4_SPLL, /* M4 SPLL */ + PLL_M4_APLL, /* M4 APLL*/ + PLL_A7_SPLL, /* A7 SPLL */ + PLL_A7_APLL, /* A7 APLL */ + PLL_USB, /* USB PLL*/ + PLL_MIPI, /* MIPI PLL */ +}; + +typedef struct scg_regs { + u32 verid; /* VERSION_ID */ + u32 param; /* PARAMETER */ + u32 rsvd11[2]; + + u32 csr; /* Clock Status Register */ + u32 rccr; /* Run Clock Control Register */ + u32 vccr; /* VLPR Clock Control Register */ + u32 hccr; /* HSRUN Clock Control Register */ + u32 clkoutcnfg; /* SCG CLKOUT Configuration Register */ + u32 rsvd12[3]; + u32 ddrccr; /* SCG DDR Clock Control Register */ + u32 rsvd13[3]; + u32 nicccr; /* NIC Clock Control Register */ + u32 niccsr; /* NIC Clock Status Register */ + u32 rsvd10[46]; + + u32 sosccsr; /* System OSC Control Status Register, offset 0x100 */ + u32 soscdiv; /* System OSC Divide Register */ + u32 sosccfg; /* System Oscillator Configuration Register */ + u32 sosctest; /* System Oscillator Test Register */ + u32 rsvd20[60]; + + u32 sirccsr; /* Slow IRC Control Status Register, offset 0x200 */ + u32 sircdiv; /* Slow IRC Divide Register */ + u32 sirccfg; /* Slow IRC Configuration Register */ + u32 sirctrim; /* Slow IRC Trim Register */ + u32 loptrim; /* Low Power Oscillator Trim Register */ + u32 sirctest; /* Slow IRC Test Register */ + u32 rsvd30[58]; + + u32 firccsr; /* Fast IRC Control Status Register, offset 0x300 */ + u32 fircdiv; + u32 firccfg; + u32 firctcfg; /* Fast IRC Trim Configuration Register */ + u32 firctriml; /* Fast IRC Trim Low Register */ + u32 firctrimh; + u32 fircstat; /* Fast IRC Status Register */ + u32 firctest; /* Fast IRC Test Register */ + u32 rsvd40[56]; + + u32 rtccsr; /* RTC OSC Control Status Register, offset 0x400 */ + u32 rsvd50[63]; + + u32 apllcsr; /* Auxiliary PLL Control Status Register, offset 0x500 */ + u32 aplldiv; /* Auxiliary PLL Divider Register */ + u32 apllcfg; /* Auxiliary PLL Configuration Register */ + u32 apllpfd; /* Auxiliary PLL PFD Register */ + u32 apllnum; /* Auxiliary PLL Numerator Register */ + u32 aplldenom; /* Auxiliary PLL Denominator Register */ + u32 apllss; /* Auxiliary PLL Spread Spectrum Register */ + u32 rsvd60[55]; + u32 apllock_cnfg; /* Auxiliary PLL LOCK Configuration Register */ + u32 rsvd61[1]; + + u32 spllcsr; /* System PLL Control Status Register, offset 0x600 */ + u32 splldiv; /* System PLL Divide Register */ + u32 spllcfg; /* System PLL Configuration Register */ + u32 spllpfd; /* System PLL Test Register */ + u32 spllnum; /* System PLL Numerator Register */ + u32 splldenom; /* System PLL Denominator Register */ + u32 spllss; /* System PLL Spread Spectrum Register */ + u32 rsvd70[55]; + u32 spllock_cnfg; /* System PLL LOCK Configuration Register */ + u32 rsvd71[1]; + + u32 upllcsr; /* USB PLL Control Status Register, offset 0x700 */ + u32 uplldiv; /* USB PLL Divide Register */ + u32 upllcfg; /* USB PLL Configuration Register */ +} scg_t, *scg_p; + +u32 scg_clk_get_rate(enum scg_clk clk); +int scg_enable_pll_pfd(enum scg_clk clk, u32 frac); +int scg_enable_usb_pll(bool usb_control); +u32 decode_pll(enum pll_clocks pll); + +void scg_a7_rccr_init(void); +void scg_a7_spll_init(void); +void scg_a7_ddrclk_init(void); +void scg_a7_firc_init(void); +void scg_a7_nicclk_init(void); +void scg_a7_sys_clk_sel(enum scg_sys_src clk); +void scg_a7_info(void); +void scg_a7_soscdiv_init(void); +void scg_a7_init_core_clk(void); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/sys_proto.h new file mode 100644 index 000000000..0e4c8ad15 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/sys_proto.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#ifndef _SYS_PROTO_MX7ULP_H_ +#define _SYS_PROTO_MX7ULP_H_ + +#include + +#define BT0CFG_LPBOOT_MASK 0x1 +#define BT0CFG_DUALBOOT_MASK 0x2 + +enum bt_mode { + LOW_POWER_BOOT, /* LP_BT = 1 */ + DUAL_BOOT, /* LP_BT = 0, DUAL_BT = 1 */ + SINGLE_BOOT /* LP_BT = 0, DUAL_BT = 0 */ +}; + +enum boot_device get_boot_device(void); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/clock.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/clock.h new file mode 100644 index 000000000..ee56d10fe --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/clock.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX23/i.MX28 Clock + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ + +#ifndef __CLOCK_H__ +#define __CLOCK_H__ + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_EMI_CLK, + MXC_GPMI_CLK, + MXC_IO0_CLK, + MXC_IO1_CLK, + MXC_XTAL_CLK, + MXC_SSP0_CLK, +#ifdef CONFIG_MX28 + MXC_SSP1_CLK, + MXC_SSP2_CLK, + MXC_SSP3_CLK, +#endif +}; + +enum mxs_ioclock { + MXC_IOCLK0 = 0, + MXC_IOCLK1, +}; + +enum mxs_sspclock { + MXC_SSPCLK0 = 0, +#ifdef CONFIG_MX28 + MXC_SSPCLK1, + MXC_SSPCLK2, + MXC_SSPCLK3, +#endif +}; + +uint32_t mxc_get_clock(enum mxc_clock clk); + +void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq); +void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal); +void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq); +void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq); + +/* Compatibility with the FEC Ethernet driver */ +#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK) + +#endif /* __CLOCK_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/gpio.h new file mode 100644 index 000000000..34fa42194 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/gpio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX28 GPIO + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ + +#ifndef __MX28_GPIO_H__ +#define __MX28_GPIO_H__ + +#ifdef CONFIG_MXS_GPIO +void mxs_gpio_init(void); +#else +inline void mxs_gpio_init(void) {} +#endif + +#endif /* __MX28_GPIO_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/imx-regs.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/imx-regs.h new file mode 100644 index 000000000..f853c484b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/imx-regs.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX23/i.MX28 Registers + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ + +#ifndef __IMX_REGS_H__ +#define __IMX_REGS_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_MX23 +#include +#include +#endif + +#ifdef CONFIG_MX28 +#include +#include +#endif + +#endif /* __IMX_REGS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx23.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx23.h new file mode 100644 index 000000000..2706efa75 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx23.h @@ -0,0 +1,349 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2009-2010 Amit Kucheria + * Copyright (C) 2010 Freescale Semiconductor, Inc. + */ + +#ifndef __MACH_IOMUX_MX23_H__ +#define __MACH_IOMUX_MX23_H__ + +#include + +/* + * The naming convention for the pad modes is MX23_PAD___ + * If or refers to a GPIO, it is named GPIO__ + * See also iomux.h + * + * BANK PIN MUX + */ +/* MUXSEL_0 */ +#define MX23_PAD_GPMI_D00__GPMI_D00 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D01__GPMI_D01 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D02__GPMI_D02 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D03__GPMI_D03 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D04__GPMI_D04 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D05__GPMI_D05 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D06__GPMI_D06 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D07__GPMI_D07 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D08__GPMI_D08 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D09__GPMI_D09 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D10__GPMI_D10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D11__GPMI_D11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D12__GPMI_D12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D13__GPMI_D13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D14__GPMI_D14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D15__GPMI_D15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_WPN__GPMI_WPN MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) +#define MX23_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) +#define MX23_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) +#define MX23_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) +#define MX23_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0) +#define MX23_PAD_I2C_SCL__I2C_SCL MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0) +#define MX23_PAD_I2C_SDA__I2C_SDA MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0) + +#define MX23_PAD_LCD_D00__LCD_D00 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D01__LCD_D01 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D02__LCD_D02 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D03__LCD_D03 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D04__LCD_D04 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D05__LCD_D05 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D06__LCD_D06 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D07__LCD_D07 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D08__LCD_D08 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D09__LCD_D09 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) +#define MX23_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) +#define MX23_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) +#define MX23_PAD_LCD_WR__LCD_WR MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) +#define MX23_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) +#define MX23_PAD_LCD_DOTCK__LCD_DOTCK MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) +#define MX23_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) +#define MX23_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) +#define MX23_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) +#define MX23_PAD_PWM0__PWM0 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) +#define MX23_PAD_PWM1__PWM1 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) +#define MX23_PAD_PWM2__PWM2 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) +#define MX23_PAD_PWM3__PWM3 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) +#define MX23_PAD_PWM4__PWM4 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) + +#define MX23_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) +#define MX23_PAD_SSP1_DETECT__SSP1_DETECT MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) +#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) +#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) +#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) +#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) +#define MX23_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) +#define MX23_PAD_ROTARYA__ROTARYA MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) +#define MX23_PAD_ROTARYB__ROTARYB MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A00__EMI_A00 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A01__EMI_A01 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A02__EMI_A02 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A03__EMI_A03 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A04__EMI_A04 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A05__EMI_A05 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A06__EMI_A06 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A07__EMI_A07 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A08__EMI_A08 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A09__EMI_A09 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A10__EMI_A10 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A11__EMI_A11 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A12__EMI_A12 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) +#define MX23_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0) +#define MX23_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0) +#define MX23_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) +#define MX23_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) +#define MX23_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0) +#define MX23_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0) +#define MX23_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0) +#define MX23_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0) + +#define MX23_PAD_EMI_D00__EMI_D00 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D01__EMI_D01 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D02__EMI_D02 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D03__EMI_D03 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D04__EMI_D04 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D05__EMI_D05 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D06__EMI_D06 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D07__EMI_D07 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D08__EMI_D08 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D09__EMI_D09 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D10__EMI_D10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D11__EMI_D11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D12__EMI_D12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D13__EMI_D13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D14__EMI_D14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D15__EMI_D15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) +#define MX23_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) +#define MX23_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) +#define MX23_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) +#define MX23_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0) +#define MX23_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) +#define MX23_PAD_EMI_CLKN__EMI_CLKN MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) + +/* MUXSEL_1 */ +#define MX23_PAD_GPMI_D00__LCD_D8 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D01__LCD_D9 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D02__LCD_D10 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D03__LCD_D11 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D04__LCD_D12 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D05__LCD_D13 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D06__LCD_D14 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D07__LCD_D15 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D08__LCD_D18 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D09__LCD_D19 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D10__LCD_D20 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D11__LCD_D21 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D12__LCD_D22 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D13__LCD_D23 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D14__AUART2_RX MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D15__AUART2_TX MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_CLE__LCD_D16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_ALE__LCD_D17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_CE2N__ATA_A2 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) +#define MX23_PAD_AUART1_RTS__IR_CLK MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) +#define MX23_PAD_AUART1_RX__IR_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) +#define MX23_PAD_AUART1_TX__IR_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1) +#define MX23_PAD_I2C_SCL__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1) +#define MX23_PAD_I2C_SDA__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1) + +#define MX23_PAD_LCD_D00__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D01__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D02__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D03__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D04__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D05__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D06__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D07__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D08__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D09__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D10__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D11__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D12__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D13__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D14__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D15__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1) +#define MX23_PAD_LCD_RESET__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1) +#define MX23_PAD_LCD_RS__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1) +#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) +#define MX23_PAD_LCD_ENABLE__I2C_SCL MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) +#define MX23_PAD_LCD_HSYNC__I2C_SDA MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) +#define MX23_PAD_LCD_VSYNC__LCD_BUSY MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) +#define MX23_PAD_PWM0__ROTARYA MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) +#define MX23_PAD_PWM1__ROTARYB MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) +#define MX23_PAD_PWM2__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) +#define MX23_PAD_PWM3__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) +#define MX23_PAD_PWM4__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) + +#define MX23_PAD_SSP1_DETECT__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_1) +#define MX23_PAD_SSP1_DATA1__I2C_SCL MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_1) +#define MX23_PAD_SSP1_DATA2__I2C_SDA MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) +#define MX23_PAD_ROTARYA__AUART2_RTS MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) +#define MX23_PAD_ROTARYB__AUART2_CTS MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_1) + +/* MUXSEL_2 */ +#define MX23_PAD_GPMI_D00__SSP2_DATA0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D01__SSP2_DATA1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D02__SSP2_DATA2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D03__SSP2_DATA3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D04__SSP2_DATA4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D05__SSP2_DATA5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D06__SSP2_DATA6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D07__SSP2_DATA7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D08__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D09__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D10__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D11__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D15__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_RDY0__SSP2_DETECT MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_RDY1__SSP2_CMD MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_WRN__SSP2_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2) +#define MX23_PAD_AUART1_CTS__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) +#define MX23_PAD_AUART1_RTS__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) +#define MX23_PAD_AUART1_RX__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2) +#define MX23_PAD_AUART1_TX__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2) +#define MX23_PAD_I2C_SCL__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2) +#define MX23_PAD_I2C_SDA__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2) + +#define MX23_PAD_LCD_D08__SAIF2_SDATA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) +#define MX23_PAD_LCD_D09__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) +#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) +#define MX23_PAD_LCD_D11__SAIF_LRCLK MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) +#define MX23_PAD_LCD_D12__SAIF2_SDATA1 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) +#define MX23_PAD_LCD_D13__SAIF2_SDATA2 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) +#define MX23_PAD_LCD_D14__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) +#define MX23_PAD_LCD_D15__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) +#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) +#define MX23_PAD_LCD_RESET__GPMI_CE3N MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) +#define MX23_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2) +#define MX23_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2) +#define MX23_PAD_PWM3__AUART1_CTS MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) +#define MX23_PAD_PWM4__AUART1_RTS MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) + +#define MX23_PAD_SSP1_CMD__JTAG_TDO MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_2) +#define MX23_PAD_SSP1_DETECT__USB_OTG_ID MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_2) +#define MX23_PAD_SSP1_DATA0__JTAG_TDI MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_2) +#define MX23_PAD_SSP1_DATA1__JTAG_TCLK MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_2) +#define MX23_PAD_SSP1_DATA2__JTAG_RTCK MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_2) +#define MX23_PAD_SSP1_DATA3__JTAG_TMS MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_2) +#define MX23_PAD_SSP1_SCK__JTAG_TRST MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_2) +#define MX23_PAD_ROTARYA__SPDIF MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_2) +#define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2) + +/* MUXSEL_GPIO */ +#define MX23_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D08__GPIO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D09__GPIO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D10__GPIO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D11__GPIO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D12__GPIO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D13__GPIO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D14__GPIO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D15__GPIO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_CLE__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_ALE__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_RDY0__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_RDY1__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_RDY2__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_RDY3__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_WPN__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_WRN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_RDN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) +#define MX23_PAD_AUART1_CTS__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) +#define MX23_PAD_AUART1_RTS__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) +#define MX23_PAD_AUART1_RX__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) +#define MX23_PAD_AUART1_TX__GPIO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO) +#define MX23_PAD_I2C_SCL__GPIO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO) +#define MX23_PAD_I2C_SDA__GPIO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO) + +#define MX23_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_RESET__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_RS__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_WR__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_CS__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_DOTCK__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_ENABLE__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_HSYNC__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_VSYNC__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) +#define MX23_PAD_PWM0__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) +#define MX23_PAD_PWM1__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) +#define MX23_PAD_PWM2__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) +#define MX23_PAD_PWM3__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) +#define MX23_PAD_PWM4__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) + +#define MX23_PAD_SSP1_CMD__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) +#define MX23_PAD_SSP1_DETECT__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) +#define MX23_PAD_SSP1_DATA0__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) +#define MX23_PAD_SSP1_DATA1__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) +#define MX23_PAD_SSP1_DATA2__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) +#define MX23_PAD_SSP1_DATA3__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) +#define MX23_PAD_SSP1_SCK__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) +#define MX23_PAD_ROTARYA__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) +#define MX23_PAD_ROTARYB__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A00__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A01__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A02__GPIO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A03__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A04__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A05__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A06__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A07__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A08__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A09__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A10__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A11__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A12__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_BA0__GPIO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_BA1__GPIO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_CASN__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_CE0N__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_CE1N__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_CE1N__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_CE0N__GPIO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_CKE__GPIO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_RASN__GPIO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_WEN__GPIO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO) + +#endif /* __MACH_IOMUX_MX23_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx28.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx28.h new file mode 100644 index 000000000..00356f013 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx28.h @@ -0,0 +1,531 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2009-2010 Amit Kucheria + * Copyright (C) 2010 Freescale Semiconductor, Inc. + */ + +#ifndef __MACH_IOMUX_MX28_H__ +#define __MACH_IOMUX_MX28_H__ + +#include + +/* + * The naming convention for the pad modes is MX28_PAD___ + * If or refers to a GPIO, it is named GPIO__ + * See also iomux.h + * + * BANK PIN MUX + */ +/* MUXSEL_0 */ +#define MX28_PAD_GPMI_D00__GPMI_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D01__GPMI_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D02__GPMI_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D03__GPMI_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D04__GPMI_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D05__GPMI_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D06__GPMI_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D07__GPMI_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE3N__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY0__GPMI_READY0 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY1__GPMI_READY1 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY2__GPMI_READY2 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY3__GPMI_READY3 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RESETN__GPMI_RESETN MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) + +#define MX28_PAD_LCD_D00__LCD_D0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D01__LCD_D1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D02__LCD_D2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D03__LCD_D3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D04__LCD_D4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D05__LCD_D5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D06__LCD_D6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D07__LCD_D7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D08__LCD_D8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D09__LCD_D9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D18__LCD_D18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D19__LCD_D19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D20__LCD_D20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D21__LCD_D21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D22__LCD_D22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D23__LCD_D23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) +#define MX28_PAD_LCD_RD_E__LCD_RD_E MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) +#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) +#define MX28_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) +#define MX28_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) +#define MX28_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) +#define MX28_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) +#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) +#define MX28_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0) + +#define MX28_PAD_SSP0_DATA0__SSP0_D0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA1__SSP0_D1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA2__SSP0_D2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA3__SSP0_D3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA4__SSP0_D4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA5__SSP0_D5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA6__SSP0_D6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA7__SSP0_D7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_CMD__SSP0_CMD MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_SCK__SSP0_SCK MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_DATA0__SSP1_D0 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_DATA3__SSP1_D3 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SCK__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_MOSI__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_MISO__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SS0__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SS1__SSP2_D4 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SS2__SSP2_D5 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_SCK__SSP3_SCK MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_MOSI__SSP3_CMD MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_MISO__SSP3_D0 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_SS0__SSP3_D3 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) + +#define MX28_PAD_AUART0_RX__AUART0_RX MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) +#define MX28_PAD_AUART0_TX__AUART0_TX MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) +#define MX28_PAD_AUART0_CTS__AUART0_CTS MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) +#define MX28_PAD_AUART0_RTS__AUART0_RTS MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_RX__AUART2_RX MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_TX__AUART2_TX MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_CTS__AUART2_CTS MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_RTS__AUART2_RTS MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_RX__AUART3_RX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_TX__AUART3_TX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_CTS__AUART3_CTS MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_RTS__AUART3_RTS MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) +#define MX28_PAD_PWM0__PWM_0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) +#define MX28_PAD_PWM1__PWM_1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) +#define MX28_PAD_PWM2__PWM_2 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0) +#define MX28_PAD_I2C0_SCL__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0) +#define MX28_PAD_I2C0_SDA__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0) +#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0) +#define MX28_PAD_SPDIF__SPDIF_TX MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0) +#define MX28_PAD_PWM3__PWM_3 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0) +#define MX28_PAD_PWM4__PWM_4 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0) +#define MX28_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0) + +#define MX28_PAD_ENET0_MDC__ENET0_MDC MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_MDIO__ENET0_MDIO MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_COL__ENET0_COL MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_CRS__ENET0_CRS MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0) +#define MX28_PAD_ENET_CLK__CLKCTRL_ENET MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0) +#define MX28_PAD_JTAG_RTCK__JTAG_RTCK MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0) + +#define MX28_PAD_EMI_D00__EMI_DATA0 MXS_IOMUX_PAD_NAKED(5, 0, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D01__EMI_DATA1 MXS_IOMUX_PAD_NAKED(5, 1, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D02__EMI_DATA2 MXS_IOMUX_PAD_NAKED(5, 2, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D03__EMI_DATA3 MXS_IOMUX_PAD_NAKED(5, 3, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D04__EMI_DATA4 MXS_IOMUX_PAD_NAKED(5, 4, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D05__EMI_DATA5 MXS_IOMUX_PAD_NAKED(5, 5, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D06__EMI_DATA6 MXS_IOMUX_PAD_NAKED(5, 6, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D07__EMI_DATA7 MXS_IOMUX_PAD_NAKED(5, 7, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D08__EMI_DATA8 MXS_IOMUX_PAD_NAKED(5, 8, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D09__EMI_DATA9 MXS_IOMUX_PAD_NAKED(5, 9, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D10__EMI_DATA10 MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D11__EMI_DATA11 MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D12__EMI_DATA12 MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D13__EMI_DATA13 MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D14__EMI_DATA14 MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D15__EMI_DATA15 MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0) +#define MX28_PAD_EMI_ODT0__EMI_ODT0 MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0) +#define MX28_PAD_EMI_ODT1__EMI_ODT1 MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0) + +#define MX28_PAD_EMI_A00__EMI_ADDR0 MXS_IOMUX_PAD_NAKED(6, 0, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A01__EMI_ADDR1 MXS_IOMUX_PAD_NAKED(6, 1, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A02__EMI_ADDR2 MXS_IOMUX_PAD_NAKED(6, 2, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A03__EMI_ADDR3 MXS_IOMUX_PAD_NAKED(6, 3, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A04__EMI_ADDR4 MXS_IOMUX_PAD_NAKED(6, 4, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A05__EMI_ADDR5 MXS_IOMUX_PAD_NAKED(6, 5, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A06__EMI_ADDR6 MXS_IOMUX_PAD_NAKED(6, 6, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A07__EMI_ADDR7 MXS_IOMUX_PAD_NAKED(6, 7, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A08__EMI_ADDR8 MXS_IOMUX_PAD_NAKED(6, 8, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A09__EMI_ADDR9 MXS_IOMUX_PAD_NAKED(6, 9, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A10__EMI_ADDR10 MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A11__EMI_ADDR11 MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A12__EMI_ADDR12 MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A13__EMI_ADDR13 MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A14__EMI_ADDR14 MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0) +#define MX28_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0) +#define MX28_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0) +#define MX28_PAD_EMI_BA2__EMI_BA2 MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0) +#define MX28_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0) +#define MX28_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0) + +/* MUXSEL_1 */ +#define MX28_PAD_GPMI_D00__SSP1_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D01__SSP1_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D02__SSP1_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D03__SSP1_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D04__SSP1_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D05__SSP1_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D06__SSP1_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D07__SSP1_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE0N__SSP3_D0 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE1N__SSP3_D3 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE2N__CAN1_TX MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE3N__CAN1_RX MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY1__SSP1_CMD MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY2__CAN0_TX MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY3__CAN0_RX MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDN__SSP3_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_WRN__SSP1_SCK MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_ALE__SSP3_D1 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CLE__SSP3_D2 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RESETN__SSP3_CMD MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) + +#define MX28_PAD_LCD_D03__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D04__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D08__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D09__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) +#define MX28_PAD_LCD_RD_E__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) +#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) +#define MX28_PAD_LCD_RS__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) +#define MX28_PAD_LCD_CS__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) +#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) +#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) +#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) + +#define MX28_PAD_SSP0_DATA4__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) +#define MX28_PAD_SSP0_DATA5__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_1) +#define MX28_PAD_SSP0_DATA6__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_1) +#define MX28_PAD_SSP0_DATA7__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_SCK__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_CMD__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_DATA0__SSP2_D6 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_DATA3__SSP2_D7 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SCK__AUART2_RX MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_MOSI__AUART2_TX MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_MISO__AUART3_RX MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SS0__AUART3_TX MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SS1__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SS2__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_SCK__AUART4_TX MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_MOSI__AUART4_RX MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_MISO__AUART4_RTS MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_SS0__AUART4_CTS MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1) + +#define MX28_PAD_AUART0_RX__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_1) +#define MX28_PAD_AUART0_TX__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_1) +#define MX28_PAD_AUART0_CTS__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_1) +#define MX28_PAD_AUART0_RTS__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_RTS__USB0_ID MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_RX__SSP3_D1 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_TX__SSP3_D2 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_CTS__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_RTS__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_RX__CAN0_TX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_TX__CAN0_RX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_CTS__CAN1_TX MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_RTS__CAN1_RX MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1) +#define MX28_PAD_PWM0__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1) +#define MX28_PAD_PWM1__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1) +#define MX28_PAD_PWM2__USB0_ID MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_MCLK__PWM_3 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_LRCLK__PWM_4 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_BITCLK__PWM_5 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_SDATA0__PWM_6 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1) +#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1) +#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1) +#define MX28_PAD_SAIF1_SDATA0__PWM_7 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1) +#define MX28_PAD_LCD_RESET__LCD_VSYNC MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1) + +#define MX28_PAD_ENET0_MDC__GPMI_CE4N MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_MDIO__GPMI_CE5N MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD0__GPMI_CE7N MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD1__GPMI_READY4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD0__GPMI_READY6 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD1__GPMI_READY7 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_COL__ENET1_TX_EN MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_CRS__ENET1_RX_EN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1) + +/* MUXSEL_2 */ +#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_RDY0__USB0_ID MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_ALE__SSP3_D4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_CLE__SSP3_D5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) + +#define MX28_PAD_LCD_D00__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D01__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D02__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D03__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D04__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D05__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D06__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D07__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D08__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D09__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D10__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D11__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D12__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D13__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D14__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D15__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D16__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D17__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D18__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D19__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D20__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D21__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D22__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D23__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2) +#define MX28_PAD_LCD_RD_E__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2) +#define MX28_PAD_LCD_WR_RWN__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2) +#define MX28_PAD_LCD_HSYNC__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) +#define MX28_PAD_LCD_DOTCLK__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) + +#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2) +#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2) +#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2) +#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2) + +#define MX28_PAD_AUART0_RX__DUART_CTS MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_2) +#define MX28_PAD_AUART0_TX__DUART_RTS MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_2) +#define MX28_PAD_AUART0_CTS__DUART_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_2) +#define MX28_PAD_AUART0_RTS__DUART_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_RX__PWM_0 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_TX__PWM_1 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_RX__SSP3_D4 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_TX__SSP3_D5 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2) +#define MX28_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2) +#define MX28_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2) +#define MX28_PAD_PWM2__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_MCLK__AUART4_CTS MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_BITCLK__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_SDATA0__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2) +#define MX28_PAD_I2C0_SCL__DUART_RX MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2) +#define MX28_PAD_I2C0_SDA__DUART_TX MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2) +#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2) +#define MX28_PAD_SPDIF__ENET1_RX_ER MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2) + +#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2) + +/* MUXSEL_GPIO */ +#define MX28_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE0N__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE1N__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE3N__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY0__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY1__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY2__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY3__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_WRN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_ALE__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CLE__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RESETN__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) + +#define MX28_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D18__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D19__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D20__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D21__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D22__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D23__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_RD_E__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_RS__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_CS__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_VSYNC__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_HSYNC__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_ENABLE__GPIO_1_31 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO) + +#define MX28_PAD_SSP0_DATA0__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA1__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA2__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA3__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA4__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA5__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA6__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA7__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_CMD__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DETECT__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_SCK__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_SCK__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_CMD__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_DATA0__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_DATA3__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SCK__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_MOSI__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_MISO__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SS0__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SS1__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SS2__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_SCK__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_MOSI__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_MISO__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_SS0__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) + +#define MX28_PAD_AUART0_RX__GPIO_3_0 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART0_TX__GPIO_3_1 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART0_CTS__GPIO_3_2 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART0_RTS__GPIO_3_3 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_RX__GPIO_3_4 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_TX__GPIO_3_5 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_CTS__GPIO_3_6 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_RTS__GPIO_3_7 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_RX__GPIO_3_8 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_TX__GPIO_3_9 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_CTS__GPIO_3_10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_RTS__GPIO_3_11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_RX__GPIO_3_12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_TX__GPIO_3_13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_CTS__GPIO_3_14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_RTS__GPIO_3_15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM0__GPIO_3_16 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM1__GPIO_3_17 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM2__GPIO_3_18 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO) +#define MX28_PAD_I2C0_SCL__GPIO_3_24 MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_I2C0_SDA__GPIO_3_25 MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_SPDIF__GPIO_3_27 MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM3__GPIO_3_28 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM4__GPIO_3_29 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_RESET__GPIO_3_30 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO) + +#define MX28_PAD_ENET0_MDC__GPIO_4_0 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_MDIO__GPIO_4_1 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD0__GPIO_4_3 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD1__GPIO_4_4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD0__GPIO_4_7 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD1__GPIO_4_8 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD2__GPIO_4_9 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD3__GPIO_4_10 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD2__GPIO_4_11 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD3__GPIO_4_12 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_COL__GPIO_4_14 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_CRS__GPIO_4_15 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET_CLK__GPIO_4_16 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_JTAG_RTCK__GPIO_4_20 MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO) + +#endif /* __MACH_IOMUX_MX28_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux.h new file mode 100644 index 000000000..a9896e10b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __MACH_MXS_IOMUX_H__ +#define __MACH_MXS_IOMUX_H__ + +#ifndef __ASSEMBLY__ + +#include + +/* + * IOMUX/PAD Bit field definitions + * + * PAD_BANK: 0..2 (3) + * PAD_PIN: 3..7 (5) + * PAD_MUXSEL: 8..9 (2) + * PAD_MA: 10..11 (2) + * PAD_MA_VALID: 12 (1) + * PAD_VOL: 13 (1) + * PAD_VOL_VALID: 14 (1) + * PAD_PULL: 15 (1) + * PAD_PULL_VALID: 16 (1) + * RESERVED: 17..31 (15) + */ +typedef u32 iomux_cfg_t; + +#define MXS_PAD_BANK_SHIFT 0 +#define MXS_PAD_BANK_MASK ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT) +#define MXS_PAD_PIN_SHIFT 3 +#define MXS_PAD_PIN_MASK ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT) +#define MXS_PAD_MUXSEL_SHIFT 8 +#define MXS_PAD_MUXSEL_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT) +#define MXS_PAD_MA_SHIFT 10 +#define MXS_PAD_MA_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT) +#define MXS_PAD_MA_VALID_SHIFT 12 +#define MXS_PAD_MA_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT) +#define MXS_PAD_VOL_SHIFT 13 +#define MXS_PAD_VOL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT) +#define MXS_PAD_VOL_VALID_SHIFT 14 +#define MXS_PAD_VOL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT) +#define MXS_PAD_PULL_SHIFT 15 +#define MXS_PAD_PULL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT) +#define MXS_PAD_PULL_VALID_SHIFT 16 +#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT) + +#define PAD_MUXSEL_0 0 +#define PAD_MUXSEL_1 1 +#define PAD_MUXSEL_2 2 +#define PAD_MUXSEL_GPIO 3 + +#define PAD_4MA 0 +#define PAD_8MA 1 +#define PAD_12MA 2 +#define PAD_16MA 3 + +#define PAD_1V8 0 +#if defined(CONFIG_MX28) +#define PAD_3V3 1 +#else +#define PAD_3V3 0 +#endif + +#define PAD_NOPULL 0 +#define PAD_PULLUP 1 + +#define MXS_PAD_4MA ((PAD_4MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) +#define MXS_PAD_8MA ((PAD_8MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) +#define MXS_PAD_12MA ((PAD_12MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) +#define MXS_PAD_16MA ((PAD_16MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) + +#define MXS_PAD_1V8 ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \ + MXS_PAD_VOL_VALID_MASK) +#define MXS_PAD_3V3 ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \ + MXS_PAD_VOL_VALID_MASK) + +#define MXS_PAD_NOPULL ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \ + MXS_PAD_PULL_VALID_MASK) +#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \ + MXS_PAD_PULL_VALID_MASK) + +/* generic pad control used in most cases */ +#define MXS_PAD_CTRL (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL) + +#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \ + (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \ + ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \ + ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) | \ + ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) | \ + ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) | \ + ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT)) + +/* + * A pad becomes naked, when none of mA, vol or pull + * validity bits is set. + */ +#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \ + MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0) + +static inline unsigned int PAD_BANK(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT; +} + +static inline unsigned int PAD_PIN(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT; +} + +static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT; +} + +static inline unsigned int PAD_MA(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT; +} + +static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT; +} + +static inline unsigned int PAD_VOL(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT; +} + +static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT; +} + +static inline unsigned int PAD_PULL(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT; +} + +static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT; +} + +/* + * configures a single pad in the iomuxer + */ +int mxs_iomux_setup_pad(iomux_cfg_t pad); + +/* + * configures multiple pads + * convenient way to call the above function with tables + */ +int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count); + +#endif /* __ASSEMBLY__ */ +#endif /* __MACH_MXS_IOMUX_H__*/ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-base.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-base.h new file mode 100644 index 000000000..44d40cade --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-base.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX23/i.MX28 Peripheral Base Addresses + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright (C) 2008 Embedded Alley Solutions Inc. + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + */ + +#ifndef __MXS_REGS_BASE_H__ +#define __MXS_REGS_BASE_H__ + +/* + * Register base addresses for i.MX23 + */ +#if defined(CONFIG_MX23) +#define MXS_ICOLL_BASE 0x80000000 +#define MXS_APBH_BASE 0x80004000 +#define MXS_ECC8_BASE 0x80008000 +#define MXS_BCH_BASE 0x8000A000 +#define MXS_GPMI_BASE 0x8000C000 +#define MXS_SSP0_BASE 0x80010000 +#define MXS_SSP1_BASE 0x80034000 +#define MXS_ETM_BASE 0x80014000 +#define MXS_PINCTRL_BASE 0x80018000 +#define MXS_DIGCTL_BASE 0x8001C000 +#define MXS_EMI_BASE 0x80020000 +#define MXS_APBX_BASE 0x80024000 +#define MXS_DCP_BASE 0x80028000 +#define MXS_PXP_BASE 0x8002A000 +#define MXS_OCOTP_BASE 0x8002C000 +#define MXS_AXI_BASE 0x8002E000 +#define MXS_LCDIF_BASE 0x80030000 +#define MXS_SSP1_BASE 0x80034000 +#define MXS_TVENC_BASE 0x80038000 +#define MXS_CLKCTRL_BASE 0x80040000 +#define MXS_SAIF0_BASE 0x80042000 +#define MXS_POWER_BASE 0x80044000 +#define MXS_SAIF1_BASE 0x80046000 +#define MXS_AUDIOOUT_BASE 0x80048000 +#define MXS_AUDIOIN_BASE 0x8004C000 +#define MXS_LRADC_BASE 0x80050000 +#define MXS_SPDIF_BASE 0x80054000 +#define MXS_I2C0_BASE 0x80058000 +#define MXS_RTC_BASE 0x8005C000 +#define MXS_PWM_BASE 0x80064000 +#define MXS_TIMROT_BASE 0x80068000 +#define MXS_UARTAPP0_BASE 0x8006C000 +#define MXS_UARTAPP1_BASE 0x8006E000 +#define MXS_UARTDBG_BASE 0x80070000 +#define MXS_USBPHY0_BASE 0x8007C000 +#define MXS_USBCTRL0_BASE 0x80080000 +#define MXS_DRAM_BASE 0x800E0000 + +/* + * Register base addresses for i.MX28 + */ +#elif defined(CONFIG_MX28) +#define MXS_ICOL_BASE 0x80000000 +#define MXS_HSADC_BASE 0x80002000 +#define MXS_APBH_BASE 0x80004000 +#define MXS_PERFMON_BASE 0x80006000 +#define MXS_BCH_BASE 0x8000A000 +#define MXS_GPMI_BASE 0x8000C000 +#define MXS_SSP0_BASE 0x80010000 +#define MXS_SSP1_BASE 0x80012000 +#define MXS_SSP2_BASE 0x80014000 +#define MXS_SSP3_BASE 0x80016000 +#define MXS_PINCTRL_BASE 0x80018000 +#define MXS_DIGCTL_BASE 0x8001C000 +#define MXS_ETM_BASE 0x80022000 +#define MXS_APBX_BASE 0x80024000 +#define MXS_DCP_BASE 0x80028000 +#define MXS_PXP_BASE 0x8002A000 +#define MXS_OCOTP_BASE 0x8002C000 +#define MXS_AXI_AHB0_BASE 0x8002E000 +#define MXS_LCDIF_BASE 0x80030000 +#define MXS_CAN0_BASE 0x80032000 +#define MXS_CAN1_BASE 0x80034000 +#define MXS_SIMDBG_BASE 0x8003C000 +#define MXS_SIMGPMISEL_BASE 0x8003C200 +#define MXS_SIMSSPSEL_BASE 0x8003C300 +#define MXS_SIMMEMSEL_BASE 0x8003C400 +#define MXS_GPIOMON_BASE 0x8003C500 +#define MXS_SIMENET_BASE 0x8003C700 +#define MXS_ARMJTAG_BASE 0x8003C800 +#define MXS_CLKCTRL_BASE 0x80040000 +#define MXS_SAIF0_BASE 0x80042000 +#define MXS_POWER_BASE 0x80044000 +#define MXS_SAIF1_BASE 0x80046000 +#define MXS_LRADC_BASE 0x80050000 +#define MXS_SPDIF_BASE 0x80054000 +#define MXS_RTC_BASE 0x80056000 +#define MXS_I2C0_BASE 0x80058000 +#define MXS_I2C1_BASE 0x8005A000 +#define MXS_PWM_BASE 0x80064000 +#define MXS_TIMROT_BASE 0x80068000 +#define MXS_UARTAPP0_BASE 0x8006A000 +#define MXS_UARTAPP1_BASE 0x8006C000 +#define MXS_UARTAPP2_BASE 0x8006E000 +#define MXS_UARTAPP3_BASE 0x80070000 +#define MXS_UARTAPP4_BASE 0x80072000 +#define MXS_UARTDBG_BASE 0x80074000 +#define MXS_USBPHY0_BASE 0x8007C000 +#define MXS_USBPHY1_BASE 0x8007E000 +#define MXS_USBCTRL0_BASE 0x80080000 +#define MXS_USBCTRL1_BASE 0x80090000 +#define MXS_DFLPT_BASE 0x800C0000 +#define MXS_DRAM_BASE 0x800E0000 +#define MXS_ENET0_BASE 0x800F0000 +#define MXS_ENET1_BASE 0x800F4000 +#else +#error Unkown SoC. Please set CONFIG_MX23 or CONFIG_MX28 +#endif + +#endif /* __MXS_REGS_BASE_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h new file mode 100644 index 000000000..50fdc9cd0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX23 CLKCTRL Register Definitions + * + * Copyright (C) 2012 Marek Vasut + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __MX23_REGS_CLKCTRL_H__ +#define __MX23_REGS_CLKCTRL_H__ + +#include + +#ifndef __ASSEMBLY__ +struct mxs_clkctrl_regs { + mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ + uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */ + uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */ + mxs_reg_32(hw_clkctrl_cpu) /* 0x20 */ + mxs_reg_32(hw_clkctrl_hbus) /* 0x30 */ + mxs_reg_32(hw_clkctrl_xbus) /* 0x40 */ + mxs_reg_32(hw_clkctrl_xtal) /* 0x50 */ + mxs_reg_32(hw_clkctrl_pix) /* 0x60 */ + uint32_t hw_clkctrl_ssp0; /* 0x70 */ + uint32_t reserved_ssp0[3]; /* 0x74-0x7c */ + uint32_t hw_clkctrl_gpmi; /* 0x80 */ + uint32_t reserved_gpmi[3]; /* 0x84-0x8c */ + mxs_reg_32(hw_clkctrl_spdif) /* 0x90 */ + mxs_reg_32(hw_clkctrl_emi) /* 0xa0 */ + + uint32_t reserved1[4]; + + mxs_reg_32(hw_clkctrl_saif0) /* 0xc0 */ + mxs_reg_32(hw_clkctrl_tv) /* 0xd0 */ + mxs_reg_32(hw_clkctrl_etm) /* 0xe0 */ + mxs_reg_8(hw_clkctrl_frac0) /* 0xf0 */ + mxs_reg_8(hw_clkctrl_frac1) /* 0x100 */ + mxs_reg_32(hw_clkctrl_clkseq) /* 0x110 */ + mxs_reg_32(hw_clkctrl_reset) /* 0x120 */ + mxs_reg_32(hw_clkctrl_status) /* 0x130 */ + mxs_reg_32(hw_clkctrl_version) /* 0x140 */ +}; +#endif + +#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) +#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20 +#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) +#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) +#define CLKCTRL_PLL0CTRL0_POWER (1 << 16) + +#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) +#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) +#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff +#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 + +#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) +#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) +#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) +#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) +#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 +#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) +#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) +#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f +#define CLKCTRL_CPU_DIV_CPU_OFFSET 0 + +#define CLKCTRL_HBUS_BUSY (1 << 29) +#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 28) +#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 27) +#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) +#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) +#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) +#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) +#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) +#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) +#define CLKCTRL_HBUS_AUTO_SLOW_MODE (1 << 20) +#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 +#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) +#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) +#define CLKCTRL_HBUS_DIV_MASK 0x1f +#define CLKCTRL_HBUS_DIV_OFFSET 0 + +#define CLKCTRL_XBUS_BUSY (1 << 31) +#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_XBUS_DIV_MASK 0x3ff +#define CLKCTRL_XBUS_DIV_OFFSET 0 + +#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) +#define CLKCTRL_XTAL_FILT_CLK24M_GATE (1 << 30) +#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) +#define CLKCTRL_XTAL_DRI_CLK24M_GATE (1 << 28) +#define CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE (1 << 27) +#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) +#define CLKCTRL_XTAL_DIV_UART_MASK 0x3 +#define CLKCTRL_XTAL_DIV_UART_OFFSET 0 + +#define CLKCTRL_PIX_CLKGATE (1 << 31) +#define CLKCTRL_PIX_BUSY (1 << 29) +#define CLKCTRL_PIX_DIV_FRAC_EN (1 << 12) +#define CLKCTRL_PIX_DIV_MASK 0xfff +#define CLKCTRL_PIX_DIV_OFFSET 0 + +#define CLKCTRL_SSP_CLKGATE (1 << 31) +#define CLKCTRL_SSP_BUSY (1 << 29) +#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) +#define CLKCTRL_SSP_DIV_MASK 0x1ff +#define CLKCTRL_SSP_DIV_OFFSET 0 + +#define CLKCTRL_GPMI_CLKGATE (1 << 31) +#define CLKCTRL_GPMI_BUSY (1 << 29) +#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_GPMI_DIV_MASK 0x3ff +#define CLKCTRL_GPMI_DIV_OFFSET 0 + +#define CLKCTRL_SPDIF_CLKGATE (1 << 31) + +#define CLKCTRL_EMI_CLKGATE (1 << 31) +#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) +#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) +#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) +#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) +#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) +#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) +#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) +#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) +#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 +#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f +#define CLKCTRL_EMI_DIV_EMI_OFFSET 0 + +#define CLKCTRL_IR_CLKGATE (1 << 31) +#define CLKCTRL_IR_AUTO_DIV (1 << 29) +#define CLKCTRL_IR_IR_BUSY (1 << 28) +#define CLKCTRL_IR_IROV_BUSY (1 << 27) +#define CLKCTRL_IR_IROV_DIV_MASK (0x1ff << 16) +#define CLKCTRL_IR_IROV_DIV_OFFSET 16 +#define CLKCTRL_IR_IR_DIV_MASK 0x3ff +#define CLKCTRL_IR_IR_DIV_OFFSET 0 + +#define CLKCTRL_SAIF0_CLKGATE (1 << 31) +#define CLKCTRL_SAIF0_BUSY (1 << 29) +#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) +#define CLKCTRL_SAIF0_DIV_MASK 0xffff +#define CLKCTRL_SAIF0_DIV_OFFSET 0 + +#define CLKCTRL_TV_CLK_TV108M_GATE (1 << 31) +#define CLKCTRL_TV_CLK_TV_GATE (1 << 30) + +#define CLKCTRL_ETM_CLKGATE (1 << 31) +#define CLKCTRL_ETM_BUSY (1 << 29) +#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 6) +#define CLKCTRL_ETM_DIV_MASK 0x3f +#define CLKCTRL_ETM_DIV_OFFSET 0 + +#define CLKCTRL_FRAC_CLKGATE (1 << 7) +#define CLKCTRL_FRAC_STABLE (1 << 6) +#define CLKCTRL_FRAC_FRAC_MASK 0x3f +#define CLKCTRL_FRAC_FRAC_OFFSET 0 +#define CLKCTRL_FRAC0_CPU 0 +#define CLKCTRL_FRAC0_EMI 1 +#define CLKCTRL_FRAC0_PIX 2 +#define CLKCTRL_FRAC0_IO0 3 +#define CLKCTRL_FRAC1_VID 3 + +#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) +#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 7) +#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 6) +#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 5) +#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 4) +#define CLKCTRL_CLKSEQ_BYPASS_IR (1 << 3) +#define CLKCTRL_CLKSEQ_BYPASS_PIX (1 << 1) +#define CLKCTRL_CLKSEQ_BYPASS_SAIF (1 << 0) + +#define CLKCTRL_RESET_CHIP (1 << 1) +#define CLKCTRL_RESET_DIG (1 << 0) + +#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) +#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 + +#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24) +#define CLKCTRL_VERSION_MAJOR_OFFSET 24 +#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16) +#define CLKCTRL_VERSION_MINOR_OFFSET 16 +#define CLKCTRL_VERSION_STEP_MASK 0xffff +#define CLKCTRL_VERSION_STEP_OFFSET 0 + +#endif /* __MX23_REGS_CLKCTRL_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h new file mode 100644 index 000000000..caef9e4b1 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h @@ -0,0 +1,287 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX28 CLKCTRL Register Definitions + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __MX28_REGS_CLKCTRL_H__ +#define __MX28_REGS_CLKCTRL_H__ + +#include + +#ifndef __ASSEMBLY__ +struct mxs_clkctrl_regs { + mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ + uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */ + uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */ + mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */ + uint32_t hw_clkctrl_pll1ctrl1; /* 0x30 */ + uint32_t reserved_pll1ctrl1[3]; /* 0x34-0x3c */ + mxs_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */ + mxs_reg_32(hw_clkctrl_cpu) /* 0x50 */ + mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */ + mxs_reg_32(hw_clkctrl_xbus) /* 0x70 */ + mxs_reg_32(hw_clkctrl_xtal) /* 0x80 */ + uint32_t hw_clkctrl_ssp0; /* 0x90 */ + uint32_t reserved_ssp0[3]; /* 0x94-0x9c */ + uint32_t hw_clkctrl_ssp1; /* 0xa0 */ + uint32_t reserved_ssp1[3]; /* 0xa4-0xac */ + uint32_t hw_clkctrl_ssp2; /* 0xb0 */ + uint32_t reserved_ssp2[3]; /* 0xb4-0xbc */ + uint32_t hw_clkctrl_ssp3; /* 0xc0 */ + uint32_t reserved_ssp3[3]; /* 0xc4-0xcc */ + uint32_t hw_clkctrl_gpmi; /* 0xd0 */ + uint32_t reserved_gpmi[3]; /* 0xd4-0xdc */ + mxs_reg_32(hw_clkctrl_spdif) /* 0xe0 */ + mxs_reg_32(hw_clkctrl_emi) /* 0xf0 */ + mxs_reg_32(hw_clkctrl_saif0) /* 0x100 */ + mxs_reg_32(hw_clkctrl_saif1) /* 0x110 */ + mxs_reg_32(hw_clkctrl_lcdif) /* 0x120 */ + mxs_reg_32(hw_clkctrl_etm) /* 0x130 */ + mxs_reg_32(hw_clkctrl_enet) /* 0x140 */ + mxs_reg_32(hw_clkctrl_hsadc) /* 0x150 */ + mxs_reg_32(hw_clkctrl_flexcan) /* 0x160 */ + + uint32_t reserved[16]; + + mxs_reg_8(hw_clkctrl_frac0) /* 0x1b0 */ + mxs_reg_8(hw_clkctrl_frac1) /* 0x1c0 */ + mxs_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */ + mxs_reg_32(hw_clkctrl_reset) /* 0x1e0 */ + mxs_reg_32(hw_clkctrl_status) /* 0x1f0 */ + mxs_reg_32(hw_clkctrl_version) /* 0x200 */ +}; +#endif + +#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) +#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20 +#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) +#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) +#define CLKCTRL_PLL0CTRL0_POWER (1 << 17) + +#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) +#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) +#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff +#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 + +#define CLKCTRL_PLL1CTRL0_CLKGATEEMI (1 << 31) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT (0x0 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) +#define CLKCTRL_PLL1CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT (0x0 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2 (0x1 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05 (0x2 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED (0x3 << 24) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_MASK (0x3 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET 20 +#define CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT (0x0 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER (0x1 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST (0x2 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) +#define CLKCTRL_PLL1CTRL0_EN_USB_CLKS (1 << 18) +#define CLKCTRL_PLL1CTRL0_POWER (1 << 17) + +#define CLKCTRL_PLL1CTRL1_LOCK (1 << 31) +#define CLKCTRL_PLL1CTRL1_FORCE_LOCK (1 << 30) +#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK 0xffff +#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET 0 + +#define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31) +#define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B (1 << 26) +#define CLKCTRL_PLL2CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL2CTRL0_POWER (1 << 23) + +#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) +#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) +#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) +#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) +#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 +#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) +#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) +#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f +#define CLKCTRL_CPU_DIV_CPU_OFFSET 0 + +#define CLKCTRL_HBUS_ASM_BUSY (1 << 31) +#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 30) +#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 29) +#define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE (1 << 27) +#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) +#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) +#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) +#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) +#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) +#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) +#define CLKCTRL_HBUS_ASM_ENABLE (1 << 20) +#define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE (1 << 19) +#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 +#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) +#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) +#define CLKCTRL_HBUS_DIV_MASK 0x1f +#define CLKCTRL_HBUS_DIV_OFFSET 0 + +#define CLKCTRL_XBUS_BUSY (1 << 31) +#define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE (1 << 11) +#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_XBUS_DIV_MASK 0x3ff +#define CLKCTRL_XBUS_DIV_OFFSET 0 + +#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) +#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) +#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) +#define CLKCTRL_XTAL_DIV_UART_MASK 0x3 +#define CLKCTRL_XTAL_DIV_UART_OFFSET 0 + +#define CLKCTRL_SSP_CLKGATE (1 << 31) +#define CLKCTRL_SSP_BUSY (1 << 29) +#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) +#define CLKCTRL_SSP_DIV_MASK 0x1ff +#define CLKCTRL_SSP_DIV_OFFSET 0 + +#define CLKCTRL_GPMI_CLKGATE (1 << 31) +#define CLKCTRL_GPMI_BUSY (1 << 29) +#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_GPMI_DIV_MASK 0x3ff +#define CLKCTRL_GPMI_DIV_OFFSET 0 + +#define CLKCTRL_SPDIF_CLKGATE (1 << 31) + +#define CLKCTRL_EMI_CLKGATE (1 << 31) +#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) +#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) +#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) +#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) +#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) +#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) +#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) +#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) +#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 +#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f +#define CLKCTRL_EMI_DIV_EMI_OFFSET 0 + +#define CLKCTRL_SAIF0_CLKGATE (1 << 31) +#define CLKCTRL_SAIF0_BUSY (1 << 29) +#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) +#define CLKCTRL_SAIF0_DIV_MASK 0xffff +#define CLKCTRL_SAIF0_DIV_OFFSET 0 + +#define CLKCTRL_SAIF1_CLKGATE (1 << 31) +#define CLKCTRL_SAIF1_BUSY (1 << 29) +#define CLKCTRL_SAIF1_DIV_FRAC_EN (1 << 16) +#define CLKCTRL_SAIF1_DIV_MASK 0xffff +#define CLKCTRL_SAIF1_DIV_OFFSET 0 + +#define CLKCTRL_DIS_LCDIF_CLKGATE (1 << 31) +#define CLKCTRL_DIS_LCDIF_BUSY (1 << 29) +#define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN (1 << 13) +#define CLKCTRL_DIS_LCDIF_DIV_MASK 0x1fff +#define CLKCTRL_DIS_LCDIF_DIV_OFFSET 0 + +#define CLKCTRL_ETM_CLKGATE (1 << 31) +#define CLKCTRL_ETM_BUSY (1 << 29) +#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 7) +#define CLKCTRL_ETM_DIV_MASK 0x7f +#define CLKCTRL_ETM_DIV_OFFSET 0 + +#define CLKCTRL_ENET_SLEEP (1 << 31) +#define CLKCTRL_ENET_DISABLE (1 << 30) +#define CLKCTRL_ENET_STATUS (1 << 29) +#define CLKCTRL_ENET_BUSY_TIME (1 << 27) +#define CLKCTRL_ENET_DIV_TIME_MASK (0x3f << 21) +#define CLKCTRL_ENET_DIV_TIME_OFFSET 21 +#define CLKCTRL_ENET_TIME_SEL_MASK (0x3 << 19) +#define CLKCTRL_ENET_TIME_SEL_OFFSET 19 +#define CLKCTRL_ENET_TIME_SEL_XTAL (0x0 << 19) +#define CLKCTRL_ENET_TIME_SEL_PLL (0x1 << 19) +#define CLKCTRL_ENET_TIME_SEL_RMII_CLK (0x2 << 19) +#define CLKCTRL_ENET_TIME_SEL_UNDEFINED (0x3 << 19) +#define CLKCTRL_ENET_CLK_OUT_EN (1 << 18) +#define CLKCTRL_ENET_RESET_BY_SW_CHIP (1 << 17) +#define CLKCTRL_ENET_RESET_BY_SW (1 << 16) + +#define CLKCTRL_HSADC_RESETB (1 << 30) +#define CLKCTRL_HSADC_FREQDIV_MASK (0x3 << 28) +#define CLKCTRL_HSADC_FREQDIV_OFFSET 28 + +#define CLKCTRL_FLEXCAN_STOP_CAN0 (1 << 30) +#define CLKCTRL_FLEXCAN_CAN0_STATUS (1 << 29) +#define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28) +#define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27) + +#define CLKCTRL_FRAC_CLKGATE (1 << 7) +#define CLKCTRL_FRAC_STABLE (1 << 6) +#define CLKCTRL_FRAC_FRAC_MASK 0x3f +#define CLKCTRL_FRAC_FRAC_OFFSET 0 +#define CLKCTRL_FRAC0_CPU 0 +#define CLKCTRL_FRAC0_EMI 1 +#define CLKCTRL_FRAC0_IO1 2 +#define CLKCTRL_FRAC0_IO0 3 +#define CLKCTRL_FRAC1_PIX 0 +#define CLKCTRL_FRAC1_HSADC 1 +#define CLKCTRL_FRAC1_GPMI 2 + +#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18) +#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14) +#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS (0x1 << 14) +#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD (0x0 << 14) +#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) +#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7) +#define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6) +#define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5) +#define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4) +#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3) +#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2) +#define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1) +#define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0) + +#define CLKCTRL_RESET_WDOG_POR_DISABLE (1 << 5) +#define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE (1 << 4) +#define CLKCTRL_RESET_THERMAL_RESET_ENABLE (1 << 3) +#define CLKCTRL_RESET_THERMAL_RESET_DEFAULT (1 << 2) +#define CLKCTRL_RESET_CHIP (1 << 1) +#define CLKCTRL_RESET_DIG (1 << 0) + +#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) +#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 + +#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24) +#define CLKCTRL_VERSION_MAJOR_OFFSET 24 +#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16) +#define CLKCTRL_VERSION_MINOR_OFFSET 16 +#define CLKCTRL_VERSION_STEP_MASK 0xffff +#define CLKCTRL_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_CLKCTRL_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-digctl.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-digctl.h new file mode 100644 index 000000000..219f58ba7 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-digctl.h @@ -0,0 +1,146 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX28 DIGCTL Register Definitions + * + * Copyright (C) 2012 Robert Delien + */ + +#ifndef __MX28_REGS_DIGCTL_H__ +#define __MX28_REGS_DIGCTL_H__ + +#include + +#ifndef __ASSEMBLY__ +struct mxs_digctl_regs { + mxs_reg_32(hw_digctl_ctrl) /* 0x000 */ + mxs_reg_32(hw_digctl_status) /* 0x010 */ + mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */ + mxs_reg_32(hw_digctl_ramctrl) /* 0x030 */ + mxs_reg_32(hw_digctl_emi_status) /* 0x040 */ + mxs_reg_32(hw_digctl_read_margin) /* 0x050 */ + uint32_t hw_digctl_writeonce; /* 0x060 */ + uint32_t reserved_writeonce[3]; + mxs_reg_32(hw_digctl_bist_ctl) /* 0x070 */ + mxs_reg_32(hw_digctl_bist_status) /* 0x080 */ + uint32_t hw_digctl_entropy; /* 0x090 */ + uint32_t reserved_entropy[3]; + uint32_t hw_digctl_entropy_latched; /* 0x0a0 */ + uint32_t reserved_entropy_latched[3]; + + uint32_t reserved1[4]; + + mxs_reg_32(hw_digctl_microseconds) /* 0x0c0 */ + uint32_t hw_digctl_dbgrd; /* 0x0d0 */ + uint32_t reserved_hw_digctl_dbgrd[3]; + uint32_t hw_digctl_dbg; /* 0x0e0 */ + uint32_t reserved_hw_digctl_dbg[3]; + + uint32_t reserved2[4]; + + mxs_reg_32(hw_digctl_usb_loopback) /* 0x100 */ + mxs_reg_32(hw_digctl_ocram_status0) /* 0x110 */ + mxs_reg_32(hw_digctl_ocram_status1) /* 0x120 */ + mxs_reg_32(hw_digctl_ocram_status2) /* 0x130 */ + mxs_reg_32(hw_digctl_ocram_status3) /* 0x140 */ + mxs_reg_32(hw_digctl_ocram_status4) /* 0x150 */ + mxs_reg_32(hw_digctl_ocram_status5) /* 0x160 */ + mxs_reg_32(hw_digctl_ocram_status6) /* 0x170 */ + mxs_reg_32(hw_digctl_ocram_status7) /* 0x180 */ + mxs_reg_32(hw_digctl_ocram_status8) /* 0x190 */ + mxs_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */ + mxs_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */ + mxs_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */ + mxs_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */ + mxs_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */ + + uint32_t reserved3[36]; + + uint32_t hw_digctl_scratch0; /* 0x280 */ + uint32_t reserved_hw_digctl_scratch0[3]; + uint32_t hw_digctl_scratch1; /* 0x290 */ + uint32_t reserved_hw_digctl_scratch1[3]; + uint32_t hw_digctl_armcache; /* 0x2a0 */ + uint32_t reserved_hw_digctl_armcache[3]; + mxs_reg_32(hw_digctl_debug_trap) /* 0x2b0 */ + uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */ + uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3]; + uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */ + uint32_t reserved_hw_digctl_debug_trap_l0_addr_high[3]; + uint32_t hw_digctl_debug_trap_l3_addr_low; /* 0x2e0 */ + uint32_t reserved_hw_digctl_debug_trap_l3_addr_low[3]; + uint32_t hw_digctl_debug_trap_l3_addr_high; /* 0x2f0 */ + uint32_t reserved_hw_digctl_debug_trap_l3_addr_high[3]; + uint32_t hw_digctl_fsl; /* 0x300 */ + uint32_t reserved_hw_digctl_fsl[3]; + uint32_t hw_digctl_chipid; /* 0x310 */ + uint32_t reserved_hw_digctl_chipid[3]; + + uint32_t reserved4[4]; + + uint32_t hw_digctl_ahb_stats_select; /* 0x330 */ + uint32_t reserved_hw_digctl_ahb_stats_select[3]; + + uint32_t reserved5[12]; + + uint32_t hw_digctl_l1_ahb_active_cycles; /* 0x370 */ + uint32_t reserved_hw_digctl_l1_ahb_active_cycles[3]; + uint32_t hw_digctl_l1_ahb_data_stalled; /* 0x380 */ + uint32_t reserved_hw_digctl_l1_ahb_data_stalled[3]; + uint32_t hw_digctl_l1_ahb_data_cycles; /* 0x390 */ + uint32_t reserved_hw_digctl_l1_ahb_data_cycles[3]; + uint32_t hw_digctl_l2_ahb_active_cycles; /* 0x3a0 */ + uint32_t reserved_hw_digctl_l2_ahb_active_cycles[3]; + uint32_t hw_digctl_l2_ahb_data_stalled; /* 0x3b0 */ + uint32_t reserved_hw_digctl_l2_ahb_data_stalled[3]; + uint32_t hw_digctl_l2_ahb_data_cycles; /* 0x3c0 */ + uint32_t reserved_hw_digctl_l2_ahb_data_cycles[3]; + uint32_t hw_digctl_l3_ahb_active_cycles; /* 0x3d0 */ + uint32_t reserved_hw_digctl_l3_ahb_active_cycles[3]; + uint32_t hw_digctl_l3_ahb_data_stalled; /* 0x3e0 */ + uint32_t reserved_hw_digctl_l3_ahb_data_stalled[3]; + uint32_t hw_digctl_l3_ahb_data_cycles; /* 0x3f0 */ + uint32_t reserved_hw_digctl_l3_ahb_data_cycles[3]; + + uint32_t reserved6[64]; + + uint32_t hw_digctl_mpte0_loc; /* 0x500 */ + uint32_t reserved_hw_digctl_mpte0_loc[3]; + uint32_t hw_digctl_mpte1_loc; /* 0x510 */ + uint32_t reserved_hw_digctl_mpte1_loc[3]; + uint32_t hw_digctl_mpte2_loc; /* 0x520 */ + uint32_t reserved_hw_digctl_mpte2_loc[3]; + uint32_t hw_digctl_mpte3_loc; /* 0x530 */ + uint32_t reserved_hw_digctl_mpte3_loc[3]; + uint32_t hw_digctl_mpte4_loc; /* 0x540 */ + uint32_t reserved_hw_digctl_mpte4_loc[3]; + uint32_t hw_digctl_mpte5_loc; /* 0x550 */ + uint32_t reserved_hw_digctl_mpte5_loc[3]; + uint32_t hw_digctl_mpte6_loc; /* 0x560 */ + uint32_t reserved_hw_digctl_mpte6_loc[3]; + uint32_t hw_digctl_mpte7_loc; /* 0x570 */ + uint32_t reserved_hw_digctl_mpte7_loc[3]; + uint32_t hw_digctl_mpte8_loc; /* 0x580 */ + uint32_t reserved_hw_digctl_mpte8_loc[3]; + uint32_t hw_digctl_mpte9_loc; /* 0x590 */ + uint32_t reserved_hw_digctl_mpte9_loc[3]; + uint32_t hw_digctl_mpte10_loc; /* 0x5a0 */ + uint32_t reserved_hw_digctl_mpte10_loc[3]; + uint32_t hw_digctl_mpte11_loc; /* 0x5b0 */ + uint32_t reserved_hw_digctl_mpte11_loc[3]; + uint32_t hw_digctl_mpte12_loc; /* 0x5c0 */ + uint32_t reserved_hw_digctl_mpte12_loc[3]; + uint32_t hw_digctl_mpte13_loc; /* 0x5d0 */ + uint32_t reserved_hw_digctl_mpte13_loc[3]; + uint32_t hw_digctl_mpte14_loc; /* 0x5e0 */ + uint32_t reserved_hw_digctl_mpte14_loc[3]; + uint32_t hw_digctl_mpte15_loc; /* 0x5f0 */ + uint32_t reserved_hw_digctl_mpte15_loc[3]; +}; +#endif + +/* Product code identification */ +#define HW_DIGCTL_CHIPID_MASK (0xffff << 16) +#define HW_DIGCTL_CHIPID_MX23 (0x3780 << 16) +#define HW_DIGCTL_CHIPID_MX28 (0x2800 << 16) + +#endif /* __MX28_REGS_DIGCTL_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-i2c.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-i2c.h new file mode 100644 index 000000000..4cc2e0ba5 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-i2c.h @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX28 I2C Register Definitions + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ + +#ifndef __MX28_REGS_I2C_H__ +#define __MX28_REGS_I2C_H__ + +#include + +#ifndef __ASSEMBLY__ +struct mxs_i2c_regs { + mxs_reg_32(hw_i2c_ctrl0) + mxs_reg_32(hw_i2c_timing0) + mxs_reg_32(hw_i2c_timing1) + mxs_reg_32(hw_i2c_timing2) + mxs_reg_32(hw_i2c_ctrl1) + mxs_reg_32(hw_i2c_stat) + mxs_reg_32(hw_i2c_queuectrl) + mxs_reg_32(hw_i2c_queuestat) + mxs_reg_32(hw_i2c_queuecmd) + mxs_reg_32(hw_i2c_queuedata) + mxs_reg_32(hw_i2c_data) + mxs_reg_32(hw_i2c_debug0) + mxs_reg_32(hw_i2c_debug1) + mxs_reg_32(hw_i2c_version) +}; +#endif + +#define I2C_CTRL_SFTRST (1 << 31) +#define I2C_CTRL_CLKGATE (1 << 30) +#define I2C_CTRL_RUN (1 << 29) +#define I2C_CTRL_PREACK (1 << 27) +#define I2C_CTRL_ACKNOWLEDGE (1 << 26) +#define I2C_CTRL_SEND_NAK_ON_LAST (1 << 25) +#define I2C_CTRL_MULTI_MASTER (1 << 23) +#define I2C_CTRL_CLOCK_HELD (1 << 22) +#define I2C_CTRL_RETAIN_CLOCK (1 << 21) +#define I2C_CTRL_POST_SEND_STOP (1 << 20) +#define I2C_CTRL_PRE_SEND_START (1 << 19) +#define I2C_CTRL_SLAVE_ADDRESS_ENABLE (1 << 18) +#define I2C_CTRL_MASTER_MODE (1 << 17) +#define I2C_CTRL_DIRECTION (1 << 16) +#define I2C_CTRL_XFER_COUNT_MASK 0xffff +#define I2C_CTRL_XFER_COUNT_OFFSET 0 + +#define I2C_TIMING0_HIGH_COUNT_MASK (0x3ff << 16) +#define I2C_TIMING0_HIGH_COUNT_OFFSET 16 +#define I2C_TIMING0_RCV_COUNT_MASK 0x3ff +#define I2C_TIMING0_RCV_COUNT_OFFSET 0 + +#define I2C_TIMING1_LOW_COUNT_MASK (0x3ff << 16) +#define I2C_TIMING1_LOW_COUNT_OFFSET 16 +#define I2C_TIMING1_XMIT_COUNT_MASK 0x3ff +#define I2C_TIMING1_XMIT_COUNT_OFFSET 0 + +#define I2C_TIMING2_BUS_FREE_MASK (0x3ff << 16) +#define I2C_TIMING2_BUS_FREE_OFFSET 16 +#define I2C_TIMING2_LEADIN_COUNT_MASK 0x3ff +#define I2C_TIMING2_LEADIN_COUNT_OFFSET 0 + +#define I2C_CTRL1_RD_QUEUE_IRQ (1 << 30) +#define I2C_CTRL1_WR_QUEUE_IRQ (1 << 29) +#define I2C_CTRL1_CLR_GOT_A_NAK (1 << 28) +#define I2C_CTRL1_ACK_MODE (1 << 27) +#define I2C_CTRL1_FORCE_DATA_IDLE (1 << 26) +#define I2C_CTRL1_FORCE_CLK_IDLE (1 << 25) +#define I2C_CTRL1_BCAST_SLAVE_EN (1 << 24) +#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_MASK (0xff << 16) +#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_OFFSET 16 +#define I2C_CTRL1_BUS_FREE_IRQ_EN (1 << 15) +#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN (1 << 14) +#define I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN (1 << 13) +#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN (1 << 12) +#define I2C_CTRL1_EARLY_TERM_IRQ_EN (1 << 11) +#define I2C_CTRL1_MASTER_LOSS_IRQ_EN (1 << 10) +#define I2C_CTRL1_SLAVE_STOP_IRQ_EN (1 << 9) +#define I2C_CTRL1_SLAVE_IRQ_EN (1 << 8) +#define I2C_CTRL1_BUS_FREE_IRQ (1 << 7) +#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ (1 << 6) +#define I2C_CTRL1_NO_SLAVE_ACK_IRQ (1 << 5) +#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ (1 << 4) +#define I2C_CTRL1_EARLY_TERM_IRQ (1 << 3) +#define I2C_CTRL1_MASTER_LOSS_IRQ (1 << 2) +#define I2C_CTRL1_SLAVE_STOP_IRQ (1 << 1) +#define I2C_CTRL1_SLAVE_IRQ (1 << 0) + +#define I2C_STAT_MASTER_PRESENT (1 << 31) +#define I2C_STAT_SLAVE_PRESENT (1 << 30) +#define I2C_STAT_ANY_ENABLED_IRQ (1 << 29) +#define I2C_STAT_GOT_A_NAK (1 << 28) +#define I2C_STAT_RCVD_SLAVE_ADDR_MASK (0xff << 16) +#define I2C_STAT_RCVD_SLAVE_ADDR_OFFSET 16 +#define I2C_STAT_SLAVE_ADDR_EQ_ZERO (1 << 15) +#define I2C_STAT_SLAVE_FOUND (1 << 14) +#define I2C_STAT_SLAVE_SEARCHING (1 << 13) +#define I2C_STAT_DATA_ENGING_DMA_WAIT (1 << 12) +#define I2C_STAT_BUS_BUSY (1 << 11) +#define I2C_STAT_CLK_GEN_BUSY (1 << 10) +#define I2C_STAT_DATA_ENGINE_BUSY (1 << 9) +#define I2C_STAT_SLAVE_BUSY (1 << 8) +#define I2C_STAT_BUS_FREE_IRQ_SUMMARY (1 << 7) +#define I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY (1 << 6) +#define I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY (1 << 5) +#define I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY (1 << 4) +#define I2C_STAT_EARLY_TERM_IRQ_SUMMARY (1 << 3) +#define I2C_STAT_MASTER_LOSS_IRQ_SUMMARY (1 << 2) +#define I2C_STAT_SLAVE_STOP_IRQ_SUMMARY (1 << 1) +#define I2C_STAT_SLAVE_IRQ_SUMMARY (1 << 0) + +#define I2C_QUEUECTRL_RD_THRESH_MASK (0x1f << 16) +#define I2C_QUEUECTRL_RD_THRESH_OFFSET 16 +#define I2C_QUEUECTRL_WR_THRESH_MASK (0x1f << 8) +#define I2C_QUEUECTRL_WR_THRESH_OFFSET 8 +#define I2C_QUEUECTRL_QUEUE_RUN (1 << 5) +#define I2C_QUEUECTRL_RD_CLEAR (1 << 4) +#define I2C_QUEUECTRL_WR_CLEAR (1 << 3) +#define I2C_QUEUECTRL_PIO_QUEUE_MODE (1 << 2) +#define I2C_QUEUECTRL_RD_QUEUE_IRQ_EN (1 << 1) +#define I2C_QUEUECTRL_WR_QUEUE_IRQ_EN (1 << 0) + +#define I2C_QUEUESTAT_RD_QUEUE_FULL (1 << 14) +#define I2C_QUEUESTAT_RD_QUEUE_EMPTY (1 << 13) +#define I2C_QUEUESTAT_RD_QUEUE_CNT_MASK (0x1f << 8) +#define I2C_QUEUESTAT_RD_QUEUE_CNT_OFFSET 8 +#define I2C_QUEUESTAT_WR_QUEUE_FULL (1 << 6) +#define I2C_QUEUESTAT_WR_QUEUE_EMPTY (1 << 5) +#define I2C_QUEUESTAT_WR_QUEUE_CNT_MASK 0x1f +#define I2C_QUEUESTAT_WR_QUEUE_CNT_OFFSET 0 + +#define I2C_QUEUECMD_PREACK (1 << 27) +#define I2C_QUEUECMD_ACKNOWLEDGE (1 << 26) +#define I2C_QUEUECMD_SEND_NAK_ON_LAST (1 << 25) +#define I2C_QUEUECMD_MULTI_MASTER (1 << 23) +#define I2C_QUEUECMD_CLOCK_HELD (1 << 22) +#define I2C_QUEUECMD_RETAIN_CLOCK (1 << 21) +#define I2C_QUEUECMD_POST_SEND_STOP (1 << 20) +#define I2C_QUEUECMD_PRE_SEND_START (1 << 19) +#define I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE (1 << 18) +#define I2C_QUEUECMD_MASTER_MODE (1 << 17) +#define I2C_QUEUECMD_DIRECTION (1 << 16) +#define I2C_QUEUECMD_XFER_COUNT_MASK 0xffff +#define I2C_QUEUECMD_XFER_COUNT_OFFSET 0 + +#define I2C_QUEUEDATA_DATA_MASK 0xffffffff +#define I2C_QUEUEDATA_DATA_OFFSET 0 + +#define I2C_DATA_DATA_MASK 0xffffffff +#define I2C_DATA_DATA_OFFSET 0 + +#define I2C_DEBUG0_DMAREQ (1 << 31) +#define I2C_DEBUG0_DMAENDCMD (1 << 30) +#define I2C_DEBUG0_DMAKICK (1 << 29) +#define I2C_DEBUG0_DMATERMINATE (1 << 28) +#define I2C_DEBUG0_STATE_VALUE_MASK (0x3 << 26) +#define I2C_DEBUG0_STATE_VALUE_OFFSET 26 +#define I2C_DEBUG0_DMA_STATE_MASK (0x3ff << 16) +#define I2C_DEBUG0_DMA_STATE_OFFSET 16 +#define I2C_DEBUG0_START_TOGGLE (1 << 15) +#define I2C_DEBUG0_STOP_TOGGLE (1 << 14) +#define I2C_DEBUG0_GRAB_TOGGLE (1 << 13) +#define I2C_DEBUG0_CHANGE_TOGGLE (1 << 12) +#define I2C_DEBUG0_STATE_LATCH (1 << 11) +#define I2C_DEBUG0_SLAVE_HOLD_CLK (1 << 10) +#define I2C_DEBUG0_STATE_STATE_MASK 0x3ff +#define I2C_DEBUG0_STATE_STATE_OFFSET 0 + +#define I2C_DEBUG1_I2C_CLK_IN (1 << 31) +#define I2C_DEBUG1_I2C_DATA_IN (1 << 30) +#define I2C_DEBUG1_DMA_BYTE_ENABLES_MASK (0xf << 24) +#define I2C_DEBUG1_DMA_BYTE_ENABLES_OFFSET 24 +#define I2C_DEBUG1_CLK_GEN_STATE_MASK (0xff << 16) +#define I2C_DEBUG1_CLK_GEN_STATE_OFFSET 16 +#define I2C_DEBUG1_LST_MODE_MASK (0x3 << 9) +#define I2C_DEBUG1_LST_MODE_OFFSET 9 +#define I2C_DEBUG1_LOCAL_SLAVE_TEST (1 << 8) +#define I2C_DEBUG1_FORCE_CLK_ON (1 << 4) +#define I2C_DEBUG1_FORCE_ABR_LOSS (1 << 3) +#define I2C_DEBUG1_FORCE_RCV_ACK (1 << 2) +#define I2C_DEBUG1_FORCE_I2C_DATA_OE (1 << 1) +#define I2C_DEBUG1_FORCE_I2C_CLK_OE (1 << 0) + +#define I2C_VERSION_MAJOR_MASK (0xff << 24) +#define I2C_VERSION_MAJOR_OFFSET 24 +#define I2C_VERSION_MINOR_MASK (0xff << 16) +#define I2C_VERSION_MINOR_OFFSET 16 +#define I2C_VERSION_STEP_MASK 0xffff +#define I2C_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_I2C_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-lradc.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-lradc.h new file mode 100644 index 000000000..a48f7a435 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-lradc.h @@ -0,0 +1,386 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX28 LRADC Register Definitions + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __MX28_REGS_LRADC_H__ +#define __MX28_REGS_LRADC_H__ + +#include + +#ifndef __ASSEMBLY__ +struct mxs_lradc_regs { + mxs_reg_32(hw_lradc_ctrl0); + mxs_reg_32(hw_lradc_ctrl1); + mxs_reg_32(hw_lradc_ctrl2); + mxs_reg_32(hw_lradc_ctrl3); + mxs_reg_32(hw_lradc_status); + mxs_reg_32(hw_lradc_ch0); + mxs_reg_32(hw_lradc_ch1); + mxs_reg_32(hw_lradc_ch2); + mxs_reg_32(hw_lradc_ch3); + mxs_reg_32(hw_lradc_ch4); + mxs_reg_32(hw_lradc_ch5); + mxs_reg_32(hw_lradc_ch6); + mxs_reg_32(hw_lradc_ch7); + mxs_reg_32(hw_lradc_delay0); + mxs_reg_32(hw_lradc_delay1); + mxs_reg_32(hw_lradc_delay2); + mxs_reg_32(hw_lradc_delay3); + mxs_reg_32(hw_lradc_debug0); + mxs_reg_32(hw_lradc_debug1); + mxs_reg_32(hw_lradc_conversion); + mxs_reg_32(hw_lradc_ctrl4); + mxs_reg_32(hw_lradc_treshold0); + mxs_reg_32(hw_lradc_treshold1); + mxs_reg_32(hw_lradc_version); +}; +#endif + +#define LRADC_CTRL0_SFTRST (1 << 31) +#define LRADC_CTRL0_CLKGATE (1 << 30) +#define LRADC_CTRL0_ONCHIP_GROUNDREF (1 << 26) +#define LRADC_CTRL0_BUTTON1_DETECT_ENABLE (1 << 25) +#define LRADC_CTRL0_BUTTON0_DETECT_ENABLE (1 << 24) +#define LRADC_CTRL0_TOUCH_DETECT_ENABLE (1 << 23) +#define LRADC_CTRL0_TOUCH_SCREEN_TYPE (1 << 22) +#define LRADC_CTRL0_YNLRSW (1 << 21) +#define LRADC_CTRL0_YPLLSW_MASK (0x3 << 19) +#define LRADC_CTRL0_YPLLSW_OFFSET 19 +#define LRADC_CTRL0_XNURSW_MASK (0x3 << 17) +#define LRADC_CTRL0_XNURSW_OFFSET 17 +#define LRADC_CTRL0_XPULSW (1 << 16) +#define LRADC_CTRL0_SCHEDULE_MASK 0xff +#define LRADC_CTRL0_SCHEDULE_OFFSET 0 + +#define LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN (1 << 28) +#define LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN (1 << 27) +#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN (1 << 26) +#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN (1 << 25) +#define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN (1 << 24) +#define LRADC_CTRL1_LRADC7_IRQ_EN (1 << 23) +#define LRADC_CTRL1_LRADC6_IRQ_EN (1 << 22) +#define LRADC_CTRL1_LRADC5_IRQ_EN (1 << 21) +#define LRADC_CTRL1_LRADC4_IRQ_EN (1 << 20) +#define LRADC_CTRL1_LRADC3_IRQ_EN (1 << 19) +#define LRADC_CTRL1_LRADC2_IRQ_EN (1 << 18) +#define LRADC_CTRL1_LRADC1_IRQ_EN (1 << 17) +#define LRADC_CTRL1_LRADC0_IRQ_EN (1 << 16) +#define LRADC_CTRL1_BUTTON1_DETECT_IRQ (1 << 12) +#define LRADC_CTRL1_BUTTON0_DETECT_IRQ (1 << 11) +#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ (1 << 10) +#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ (1 << 9) +#define LRADC_CTRL1_TOUCH_DETECT_IRQ (1 << 8) +#define LRADC_CTRL1_LRADC7_IRQ (1 << 7) +#define LRADC_CTRL1_LRADC6_IRQ (1 << 6) +#define LRADC_CTRL1_LRADC5_IRQ (1 << 5) +#define LRADC_CTRL1_LRADC4_IRQ (1 << 4) +#define LRADC_CTRL1_LRADC3_IRQ (1 << 3) +#define LRADC_CTRL1_LRADC2_IRQ (1 << 2) +#define LRADC_CTRL1_LRADC1_IRQ (1 << 1) +#define LRADC_CTRL1_LRADC0_IRQ (1 << 0) + +#define LRADC_CTRL2_DIVIDE_BY_TWO_MASK (0xff << 24) +#define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24 +#define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15) +#define LRADC_CTRL2_VTHSENSE_MASK (0x3 << 13) +#define LRADC_CTRL2_VTHSENSE_OFFSET 13 +#define LRADC_CTRL2_DISABLE_MUXAMP_BYPASS (1 << 12) +#define LRADC_CTRL2_TEMP_SENSOR_IENABLE1 (1 << 9) +#define LRADC_CTRL2_TEMP_SENSOR_IENABLE0 (1 << 8) +#define LRADC_CTRL2_TEMP_ISRC1_MASK (0xf << 4) +#define LRADC_CTRL2_TEMP_ISRC1_OFFSET 4 +#define LRADC_CTRL2_TEMP_ISRC1_300 (0xf << 4) +#define LRADC_CTRL2_TEMP_ISRC1_280 (0xe << 4) +#define LRADC_CTRL2_TEMP_ISRC1_260 (0xd << 4) +#define LRADC_CTRL2_TEMP_ISRC1_240 (0xc << 4) +#define LRADC_CTRL2_TEMP_ISRC1_220 (0xb << 4) +#define LRADC_CTRL2_TEMP_ISRC1_200 (0xa << 4) +#define LRADC_CTRL2_TEMP_ISRC1_180 (0x9 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_160 (0x8 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_140 (0x7 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_120 (0x6 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_100 (0x5 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_80 (0x4 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_60 (0x3 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_40 (0x2 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_20 (0x1 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_ZERO (0x0 << 4) +#define LRADC_CTRL2_TEMP_ISRC0_MASK (0xf << 0) +#define LRADC_CTRL2_TEMP_ISRC0_OFFSET 0 +#define LRADC_CTRL2_TEMP_ISRC0_300 (0xf << 0) +#define LRADC_CTRL2_TEMP_ISRC0_280 (0xe << 0) +#define LRADC_CTRL2_TEMP_ISRC0_260 (0xd << 0) +#define LRADC_CTRL2_TEMP_ISRC0_240 (0xc << 0) +#define LRADC_CTRL2_TEMP_ISRC0_220 (0xb << 0) +#define LRADC_CTRL2_TEMP_ISRC0_200 (0xa << 0) +#define LRADC_CTRL2_TEMP_ISRC0_180 (0x9 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_160 (0x8 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_140 (0x7 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_120 (0x6 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_100 (0x5 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_80 (0x4 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_60 (0x3 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_40 (0x2 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_20 (0x1 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_ZERO (0x0 << 0) + +#define LRADC_CTRL3_DISCARD_MASK (0x3 << 24) +#define LRADC_CTRL3_DISCARD_OFFSET 24 +#define LRADC_CTRL3_DISCARD_1_SAMPLE (0x1 << 24) +#define LRADC_CTRL3_DISCARD_2_SAMPLES (0x2 << 24) +#define LRADC_CTRL3_DISCARD_3_SAMPLES (0x3 << 24) +#define LRADC_CTRL3_FORCE_ANALOG_PWUP (1 << 23) +#define LRADC_CTRL3_FORCE_ANALOG_PWDN (1 << 22) +#define LRADC_CTRL3_CYCLE_TIME_MASK (0x3 << 8) +#define LRADC_CTRL3_CYCLE_TIME_OFFSET 8 +#define LRADC_CTRL3_CYCLE_TIME_6MHZ (0x0 << 8) +#define LRADC_CTRL3_CYCLE_TIME_4MHZ (0x1 << 8) +#define LRADC_CTRL3_CYCLE_TIME_3MHZ (0x2 << 8) +#define LRADC_CTRL3_CYCLE_TIME_2MHZ (0x3 << 8) +#define LRADC_CTRL3_HIGH_TIME_MASK (0x3 << 4) +#define LRADC_CTRL3_HIGH_TIME_OFFSET 4 +#define LRADC_CTRL3_HIGH_TIME_42NS (0x0 << 4) +#define LRADC_CTRL3_HIGH_TIME_83NS (0x1 << 4) +#define LRADC_CTRL3_HIGH_TIME_125NS (0x2 << 4) +#define LRADC_CTRL3_HIGH_TIME_250NS (0x3 << 4) +#define LRADC_CTRL3_DELAY_CLOCK (1 << 1) +#define LRADC_CTRL3_INVERT_CLOCK (1 << 0) + +#define LRADC_STATUS_BUTTON1_PRESENT (1 << 28) +#define LRADC_STATUS_BUTTON0_PRESENT (1 << 27) +#define LRADC_STATUS_TEMP1_PRESENT (1 << 26) +#define LRADC_STATUS_TEMP0_PRESENT (1 << 25) +#define LRADC_STATUS_TOUCH_PANEL_PRESENT (1 << 24) +#define LRADC_STATUS_CHANNEL7_PRESENT (1 << 23) +#define LRADC_STATUS_CHANNEL6_PRESENT (1 << 22) +#define LRADC_STATUS_CHANNEL5_PRESENT (1 << 21) +#define LRADC_STATUS_CHANNEL4_PRESENT (1 << 20) +#define LRADC_STATUS_CHANNEL3_PRESENT (1 << 19) +#define LRADC_STATUS_CHANNEL2_PRESENT (1 << 18) +#define LRADC_STATUS_CHANNEL1_PRESENT (1 << 17) +#define LRADC_STATUS_CHANNEL0_PRESENT (1 << 16) +#define LRADC_STATUS_BUTTON1_DETECT_RAW (1 << 2) +#define LRADC_STATUS_BUTTON0_DETECT_RAW (1 << 1) +#define LRADC_STATUS_TOUCH_DETECT_RAW (1 << 0) + +#define LRADC_CH_TOGGLE (1 << 31) +#define LRADC_CH7_TESTMODE_TOGGLE (1 << 30) +#define LRADC_CH_ACCUMULATE (1 << 29) +#define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24) +#define LRADC_CH_NUM_SAMPLES_OFFSET 24 +#define LRADC_CH_VALUE_MASK 0x3ffff +#define LRADC_CH_VALUE_OFFSET 0 + +#define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24) +#define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24 +#define LRADC_DELAY_KICK (1 << 20) +#define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16) +#define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16 +#define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11) +#define LRADC_DELAY_LOOP_COUNT_OFFSET 11 +#define LRADC_DELAY_DELAY_MASK 0x7ff +#define LRADC_DELAY_DELAY_OFFSET 0 + +#define LRADC_DEBUG0_READONLY_MASK (0xffff << 16) +#define LRADC_DEBUG0_READONLY_OFFSET 16 +#define LRADC_DEBUG0_STATE_MASK (0xfff << 0) +#define LRADC_DEBUG0_STATE_OFFSET 0 + +#define LRADC_DEBUG1_REQUEST_MASK (0xff << 16) +#define LRADC_DEBUG1_REQUEST_OFFSET 16 +#define LRADC_DEBUG1_TESTMODE_COUNT_MASK (0x1f << 8) +#define LRADC_DEBUG1_TESTMODE_COUNT_OFFSET 8 +#define LRADC_DEBUG1_TESTMODE6 (1 << 2) +#define LRADC_DEBUG1_TESTMODE5 (1 << 1) +#define LRADC_DEBUG1_TESTMODE (1 << 0) + +#define LRADC_CONVERSION_AUTOMATIC (1 << 20) +#define LRADC_CONVERSION_SCALE_FACTOR_MASK (0x3 << 16) +#define LRADC_CONVERSION_SCALE_FACTOR_OFFSET 16 +#define LRADC_CONVERSION_SCALE_FACTOR_NIMH (0x0 << 16) +#define LRADC_CONVERSION_SCALE_FACTOR_DUAL_NIMH (0x1 << 16) +#define LRADC_CONVERSION_SCALE_FACTOR_LI_ION (0x2 << 16) +#define LRADC_CONVERSION_SCALE_FACTOR_ALT_LI_ION (0x3 << 16) +#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_MASK 0x3ff +#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_OFFSET 0 + +#define LRADC_CTRL4_LRADC7SELECT_MASK (0xf << 28) +#define LRADC_CTRL4_LRADC7SELECT_OFFSET 28 +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL0 (0x0 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL1 (0x1 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL2 (0x2 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL3 (0x3 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL4 (0x4 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL5 (0x5 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL6 (0x6 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL7 (0x7 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL8 (0x8 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL9 (0x9 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL10 (0xa << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL11 (0xb << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL12 (0xc << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL13 (0xd << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL14 (0xe << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL15 (0xf << 28) +#define LRADC_CTRL4_LRADC6SELECT_MASK (0xf << 24) +#define LRADC_CTRL4_LRADC6SELECT_OFFSET 24 +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL0 (0x0 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL1 (0x1 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL2 (0x2 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL3 (0x3 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL4 (0x4 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL5 (0x5 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL6 (0x6 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL7 (0x7 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL8 (0x8 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL9 (0x9 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL10 (0xa << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL11 (0xb << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL12 (0xc << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL13 (0xd << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL14 (0xe << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL15 (0xf << 24) +#define LRADC_CTRL4_LRADC5SELECT_MASK (0xf << 20) +#define LRADC_CTRL4_LRADC5SELECT_OFFSET 20 +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL0 (0x0 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL1 (0x1 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL2 (0x2 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL3 (0x3 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL4 (0x4 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL5 (0x5 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL6 (0x6 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL7 (0x7 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL8 (0x8 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL9 (0x9 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL10 (0xa << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL11 (0xb << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL12 (0xc << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL13 (0xd << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL14 (0xe << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL15 (0xf << 20) +#define LRADC_CTRL4_LRADC4SELECT_MASK (0xf << 16) +#define LRADC_CTRL4_LRADC4SELECT_OFFSET 16 +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL0 (0x0 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL1 (0x1 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL2 (0x2 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL3 (0x3 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL4 (0x4 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL5 (0x5 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL6 (0x6 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL7 (0x7 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL8 (0x8 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL9 (0x9 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL10 (0xa << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL11 (0xb << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL12 (0xc << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL13 (0xd << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL14 (0xe << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL15 (0xf << 16) +#define LRADC_CTRL4_LRADC3SELECT_MASK (0xf << 12) +#define LRADC_CTRL4_LRADC3SELECT_OFFSET 12 +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL0 (0x0 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL1 (0x1 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL2 (0x2 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL3 (0x3 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL4 (0x4 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL5 (0x5 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL6 (0x6 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL7 (0x7 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL8 (0x8 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL9 (0x9 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL10 (0xa << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL11 (0xb << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL12 (0xc << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL13 (0xd << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL14 (0xe << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL15 (0xf << 12) +#define LRADC_CTRL4_LRADC2SELECT_MASK (0xf << 8) +#define LRADC_CTRL4_LRADC2SELECT_OFFSET 8 +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL0 (0x0 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL1 (0x1 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL2 (0x2 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL3 (0x3 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL4 (0x4 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL5 (0x5 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL6 (0x6 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL7 (0x7 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL8 (0x8 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL9 (0x9 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL10 (0xa << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL11 (0xb << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL12 (0xc << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL13 (0xd << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL14 (0xe << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL15 (0xf << 8) +#define LRADC_CTRL4_LRADC1SELECT_MASK (0xf << 4) +#define LRADC_CTRL4_LRADC1SELECT_OFFSET 4 +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL0 (0x0 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL1 (0x1 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL2 (0x2 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL3 (0x3 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL4 (0x4 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL5 (0x5 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL6 (0x6 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL7 (0x7 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL8 (0x8 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL9 (0x9 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL10 (0xa << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL11 (0xb << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL12 (0xc << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL13 (0xd << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL14 (0xe << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL15 (0xf << 4) +#define LRADC_CTRL4_LRADC0SELECT_MASK 0xf +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL0 (0x0 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL1 (0x1 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL2 (0x2 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL3 (0x3 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL4 (0x4 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL5 (0x5 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL6 (0x6 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL7 (0x7 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL8 (0x8 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL9 (0x9 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL10 (0xa << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL11 (0xb << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL12 (0xc << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL13 (0xd << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL14 (0xe << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL15 (0xf << 0) + +#define LRADC_THRESHOLD_ENABLE (1 << 24) +#define LRADC_THRESHOLD_BATTCHRG_DISABLE (1 << 23) +#define LRADC_THRESHOLD_CHANNEL_SEL_MASK (0x7 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_OFFSET 20 +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL0 (0x0 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL1 (0x1 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL2 (0x2 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL3 (0x3 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL4 (0x4 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL5 (0x5 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL6 (0x6 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL7 (0x7 << 20) +#define LRADC_THRESHOLD_SETTING_MASK (0x3 << 18) +#define LRADC_THRESHOLD_SETTING_OFFSET 18 +#define LRADC_THRESHOLD_SETTING_NO_COMPARE (0x0 << 18) +#define LRADC_THRESHOLD_SETTING_DETECT_LOW (0x1 << 18) +#define LRADC_THRESHOLD_SETTING_DETECT_HIGH (0x2 << 18) +#define LRADC_THRESHOLD_SETTING_RESERVED (0x3 << 18) +#define LRADC_THRESHOLD_VALUE_MASK 0x3ffff +#define LRADC_THRESHOLD_VALUE_OFFSET 0 + +#define LRADC_VERSION_MAJOR_MASK (0xff << 24) +#define LRADC_VERSION_MAJOR_OFFSET 24 +#define LRADC_VERSION_MINOR_MASK (0xff << 16) +#define LRADC_VERSION_MINOR_OFFSET 16 +#define LRADC_VERSION_STEP_MASK 0xffff +#define LRADC_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_LRADC_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ocotp.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ocotp.h new file mode 100644 index 000000000..8bfbd19d5 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ocotp.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX28 OCOTP Register Definitions + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __MX28_REGS_OCOTP_H__ +#define __MX28_REGS_OCOTP_H__ + +#include + +#ifndef __ASSEMBLY__ +struct mxs_ocotp_regs { + mxs_reg_32(hw_ocotp_ctrl) /* 0x0 */ + mxs_reg_32(hw_ocotp_data) /* 0x10 */ + mxs_reg_32(hw_ocotp_cust0) /* 0x20 */ + mxs_reg_32(hw_ocotp_cust1) /* 0x30 */ + mxs_reg_32(hw_ocotp_cust2) /* 0x40 */ + mxs_reg_32(hw_ocotp_cust3) /* 0x50 */ + mxs_reg_32(hw_ocotp_crypto0) /* 0x60 */ + mxs_reg_32(hw_ocotp_crypto1) /* 0x70 */ + mxs_reg_32(hw_ocotp_crypto2) /* 0x80 */ + mxs_reg_32(hw_ocotp_crypto3) /* 0x90 */ + mxs_reg_32(hw_ocotp_hwcap0) /* 0xa0 */ + mxs_reg_32(hw_ocotp_hwcap1) /* 0xb0 */ + mxs_reg_32(hw_ocotp_hwcap2) /* 0xc0 */ + mxs_reg_32(hw_ocotp_hwcap3) /* 0xd0 */ + mxs_reg_32(hw_ocotp_hwcap4) /* 0xe0 */ + mxs_reg_32(hw_ocotp_hwcap5) /* 0xf0 */ + mxs_reg_32(hw_ocotp_swcap) /* 0x100 */ + mxs_reg_32(hw_ocotp_custcap) /* 0x110 */ + mxs_reg_32(hw_ocotp_lock) /* 0x120 */ + mxs_reg_32(hw_ocotp_ops0) /* 0x130 */ + mxs_reg_32(hw_ocotp_ops1) /* 0x140 */ + mxs_reg_32(hw_ocotp_ops2) /* 0x150 */ + mxs_reg_32(hw_ocotp_ops3) /* 0x160 */ + mxs_reg_32(hw_ocotp_un0) /* 0x170 */ + mxs_reg_32(hw_ocotp_un1) /* 0x180 */ + mxs_reg_32(hw_ocotp_un2) /* 0x190 */ + mxs_reg_32(hw_ocotp_rom0) /* 0x1a0 */ + mxs_reg_32(hw_ocotp_rom1) /* 0x1b0 */ + mxs_reg_32(hw_ocotp_rom2) /* 0x1c0 */ + mxs_reg_32(hw_ocotp_rom3) /* 0x1d0 */ + mxs_reg_32(hw_ocotp_rom4) /* 0x1e0 */ + mxs_reg_32(hw_ocotp_rom5) /* 0x1f0 */ + mxs_reg_32(hw_ocotp_rom6) /* 0x200 */ + mxs_reg_32(hw_ocotp_rom7) /* 0x210 */ + mxs_reg_32(hw_ocotp_srk0) /* 0x220 */ + mxs_reg_32(hw_ocotp_srk1) /* 0x230 */ + mxs_reg_32(hw_ocotp_srk2) /* 0x240 */ + mxs_reg_32(hw_ocotp_srk3) /* 0x250 */ + mxs_reg_32(hw_ocotp_srk4) /* 0x260 */ + mxs_reg_32(hw_ocotp_srk5) /* 0x270 */ + mxs_reg_32(hw_ocotp_srk6) /* 0x280 */ + mxs_reg_32(hw_ocotp_srk7) /* 0x290 */ + mxs_reg_32(hw_ocotp_version) /* 0x2a0 */ +}; +#endif + +#define OCOTP_CTRL_WR_UNLOCK_MASK (0xffff << 16) +#define OCOTP_CTRL_WR_UNLOCK_OFFSET 16 +#define OCOTP_CTRL_WR_UNLOCK_KEY (0x3e77 << 16) +#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 13) +#define OCOTP_CTRL_RD_BANK_OPEN (1 << 12) +#define OCOTP_CTRL_ERROR (1 << 9) +#define OCOTP_CTRL_BUSY (1 << 8) +#define OCOTP_CTRL_ADDR_MASK 0x3f +#define OCOTP_CTRL_ADDR_OFFSET 0 + +#define OCOTP_DATA_DATA_MASK 0xffffffff +#define OCOTP_DATA_DATA_OFFSET 0 + +#define OCOTP_CUST_BITS_MASK 0xffffffff +#define OCOTP_CUST_BITS_OFFSET 0 + +#define OCOTP_CRYPTO_BITS_MASK 0xffffffff +#define OCOTP_CRYPTO_BITS_OFFSET 0 + +#define OCOTP_HWCAP_BITS_MASK 0xffffffff +#define OCOTP_HWCAP_BITS_OFFSET 0 + +#define OCOTP_SWCAP_BITS_MASK 0xffffffff +#define OCOTP_SWCAP_BITS_OFFSET 0 + +#define OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT (1 << 2) +#define OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT (1 << 1) + +#define OCOTP_LOCK_ROM7 (1 << 31) +#define OCOTP_LOCK_ROM6 (1 << 30) +#define OCOTP_LOCK_ROM5 (1 << 29) +#define OCOTP_LOCK_ROM4 (1 << 28) +#define OCOTP_LOCK_ROM3 (1 << 27) +#define OCOTP_LOCK_ROM2 (1 << 26) +#define OCOTP_LOCK_ROM1 (1 << 25) +#define OCOTP_LOCK_ROM0 (1 << 24) +#define OCOTP_LOCK_HWSW_SHADOW_ALT (1 << 23) +#define OCOTP_LOCK_CRYPTODCP_ALT (1 << 22) +#define OCOTP_LOCK_CRYPTOKEY_ALT (1 << 21) +#define OCOTP_LOCK_PIN (1 << 20) +#define OCOTP_LOCK_OPS (1 << 19) +#define OCOTP_LOCK_UN2 (1 << 18) +#define OCOTP_LOCK_UN1 (1 << 17) +#define OCOTP_LOCK_UN0 (1 << 16) +#define OCOTP_LOCK_SRK (1 << 15) +#define OCOTP_LOCK_UNALLOCATED_MASK (0x7 << 12) +#define OCOTP_LOCK_UNALLOCATED_OFFSET 12 +#define OCOTP_LOCK_SRK_SHADOW (1 << 11) +#define OCOTP_LOCK_ROM_SHADOW (1 << 10) +#define OCOTP_LOCK_CUSTCAP (1 << 9) +#define OCOTP_LOCK_HWSW (1 << 8) +#define OCOTP_LOCK_CUSTCAP_SHADOW (1 << 7) +#define OCOTP_LOCK_HWSW_SHADOW (1 << 6) +#define OCOTP_LOCK_CRYPTODCP (1 << 5) +#define OCOTP_LOCK_CRYPTOKEY (1 << 4) +#define OCOTP_LOCK_CUST3 (1 << 3) +#define OCOTP_LOCK_CUST2 (1 << 2) +#define OCOTP_LOCK_CUST1 (1 << 1) +#define OCOTP_LOCK_CUST0 (1 << 0) + +#define OCOTP_OPS_BITS_MASK 0xffffffff +#define OCOTP_OPS_BITS_OFFSET 0 + +#define OCOTP_UN_BITS_MASK 0xffffffff +#define OCOTP_UN_BITS_OFFSET 0 + +#define OCOTP_ROM_BOOT_MODE_MASK (0xff << 24) +#define OCOTP_ROM_BOOT_MODE_OFFSET 24 +#define OCOTP_ROM_SD_MMC_MODE_MASK (0x3 << 22) +#define OCOTP_ROM_SD_MMC_MODE_OFFSET 22 +#define OCOTP_ROM_SD_POWER_GATE_GPIO_MASK (0x3 << 20) +#define OCOTP_ROM_SD_POWER_GATE_GPIO_OFFSET 20 +#define OCOTP_ROM_SD_POWER_UP_DELAY_MASK (0x3f << 14) +#define OCOTP_ROM_SD_POWER_UP_DELAY_OFFSET 14 +#define OCOTP_ROM_SD_BUS_WIDTH_MASK (0x3 << 12) +#define OCOTP_ROM_SD_BUS_WIDTH_OFFSET 12 +#define OCOTP_ROM_SSP_SCK_INDEX_MASK (0xf << 8) +#define OCOTP_ROM_SSP_SCK_INDEX_OFFSET 8 +#define OCOTP_ROM_EMMC_USE_DDR (1 << 7) +#define OCOTP_ROM_DISABLE_SPI_NOR_FAST_READ (1 << 6) +#define OCOTP_ROM_ENABLE_USB_BOOT_SERIAL_NUM (1 << 5) +#define OCOTP_ROM_ENABLE_UNENCRYPTED_BOOT (1 << 4) +#define OCOTP_ROM_SD_MBR_BOOT (1 << 3) + +#define OCOTP_SRK_BITS_MASK 0xffffffff +#define OCOTP_SRK_BITS_OFFSET 0 + +#define OCOTP_VERSION_MAJOR_MASK (0xff << 24) +#define OCOTP_VERSION_MAJOR_OFFSET 24 +#define OCOTP_VERSION_MINOR_MASK (0xff << 16) +#define OCOTP_VERSION_MINOR_OFFSET 16 +#define OCOTP_VERSION_STEP_MASK 0xffff +#define OCOTP_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_OCOTP_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-pinctrl.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-pinctrl.h new file mode 100644 index 000000000..134d436ee --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-pinctrl.h @@ -0,0 +1,1270 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX28 PINCTRL Register Definitions + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __MX28_REGS_PINCTRL_H__ +#define __MX28_REGS_PINCTRL_H__ + +#include + +#ifndef __ASSEMBLY__ +struct mxs_pinctrl_regs { + mxs_reg_32(hw_pinctrl_ctrl) /* 0x0 */ + + uint32_t reserved1[60]; + + mxs_reg_32(hw_pinctrl_muxsel0) /* 0x100 */ + mxs_reg_32(hw_pinctrl_muxsel1) /* 0x110 */ + mxs_reg_32(hw_pinctrl_muxsel2) /* 0x120 */ + mxs_reg_32(hw_pinctrl_muxsel3) /* 0x130 */ + mxs_reg_32(hw_pinctrl_muxsel4) /* 0x140 */ + mxs_reg_32(hw_pinctrl_muxsel5) /* 0x150 */ + mxs_reg_32(hw_pinctrl_muxsel6) /* 0x160 */ + mxs_reg_32(hw_pinctrl_muxsel7) /* 0x170 */ + mxs_reg_32(hw_pinctrl_muxsel8) /* 0x180 */ + mxs_reg_32(hw_pinctrl_muxsel9) /* 0x190 */ + mxs_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */ + mxs_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */ + mxs_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */ + mxs_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */ + + uint32_t reserved2[72]; + + mxs_reg_32(hw_pinctrl_drive0) /* 0x300 */ + mxs_reg_32(hw_pinctrl_drive1) /* 0x310 */ + mxs_reg_32(hw_pinctrl_drive2) /* 0x320 */ + mxs_reg_32(hw_pinctrl_drive3) /* 0x330 */ + mxs_reg_32(hw_pinctrl_drive4) /* 0x340 */ + mxs_reg_32(hw_pinctrl_drive5) /* 0x350 */ + mxs_reg_32(hw_pinctrl_drive6) /* 0x360 */ + mxs_reg_32(hw_pinctrl_drive7) /* 0x370 */ + mxs_reg_32(hw_pinctrl_drive8) /* 0x380 */ + mxs_reg_32(hw_pinctrl_drive9) /* 0x390 */ + mxs_reg_32(hw_pinctrl_drive10) /* 0x3a0 */ + mxs_reg_32(hw_pinctrl_drive11) /* 0x3b0 */ + mxs_reg_32(hw_pinctrl_drive12) /* 0x3c0 */ + mxs_reg_32(hw_pinctrl_drive13) /* 0x3d0 */ + mxs_reg_32(hw_pinctrl_drive14) /* 0x3e0 */ + mxs_reg_32(hw_pinctrl_drive15) /* 0x3f0 */ + mxs_reg_32(hw_pinctrl_drive16) /* 0x400 */ + mxs_reg_32(hw_pinctrl_drive17) /* 0x410 */ + mxs_reg_32(hw_pinctrl_drive18) /* 0x420 */ + mxs_reg_32(hw_pinctrl_drive19) /* 0x430 */ + + uint32_t reserved3[112]; + + mxs_reg_32(hw_pinctrl_pull0) /* 0x600 */ + mxs_reg_32(hw_pinctrl_pull1) /* 0x610 */ + mxs_reg_32(hw_pinctrl_pull2) /* 0x620 */ + mxs_reg_32(hw_pinctrl_pull3) /* 0x630 */ + mxs_reg_32(hw_pinctrl_pull4) /* 0x640 */ + mxs_reg_32(hw_pinctrl_pull5) /* 0x650 */ + mxs_reg_32(hw_pinctrl_pull6) /* 0x660 */ + + uint32_t reserved4[36]; + + mxs_reg_32(hw_pinctrl_dout0) /* 0x700 */ + mxs_reg_32(hw_pinctrl_dout1) /* 0x710 */ + mxs_reg_32(hw_pinctrl_dout2) /* 0x720 */ + mxs_reg_32(hw_pinctrl_dout3) /* 0x730 */ + mxs_reg_32(hw_pinctrl_dout4) /* 0x740 */ + + uint32_t reserved5[108]; + + mxs_reg_32(hw_pinctrl_din0) /* 0x900 */ + mxs_reg_32(hw_pinctrl_din1) /* 0x910 */ + mxs_reg_32(hw_pinctrl_din2) /* 0x920 */ + mxs_reg_32(hw_pinctrl_din3) /* 0x930 */ + mxs_reg_32(hw_pinctrl_din4) /* 0x940 */ + + uint32_t reserved6[108]; + + mxs_reg_32(hw_pinctrl_doe0) /* 0xb00 */ + mxs_reg_32(hw_pinctrl_doe1) /* 0xb10 */ + mxs_reg_32(hw_pinctrl_doe2) /* 0xb20 */ + mxs_reg_32(hw_pinctrl_doe3) /* 0xb30 */ + mxs_reg_32(hw_pinctrl_doe4) /* 0xb40 */ + + uint32_t reserved7[300]; + + mxs_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */ + mxs_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */ + mxs_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */ + mxs_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */ + mxs_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */ + + uint32_t reserved8[44]; + + mxs_reg_32(hw_pinctrl_irqen0) /* 0x1100 */ + mxs_reg_32(hw_pinctrl_irqen1) /* 0x1110 */ + mxs_reg_32(hw_pinctrl_irqen2) /* 0x1120 */ + mxs_reg_32(hw_pinctrl_irqen3) /* 0x1130 */ + mxs_reg_32(hw_pinctrl_irqen4) /* 0x1140 */ + + uint32_t reserved9[44]; + + mxs_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */ + mxs_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */ + mxs_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */ + mxs_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */ + mxs_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */ + + uint32_t reserved10[44]; + + mxs_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */ + mxs_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */ + mxs_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */ + mxs_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */ + mxs_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */ + + uint32_t reserved11[44]; + + mxs_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */ + mxs_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */ + mxs_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */ + mxs_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */ + mxs_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */ + + uint32_t reserved12[380]; + + mxs_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */ + + uint32_t reserved13[76]; + + mxs_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */ +}; +#endif + +#define PINCTRL_CTRL_SFTRST (1 << 31) +#define PINCTRL_CTRL_CLKGATE (1 << 30) +#define PINCTRL_CTRL_PRESENT4 (1 << 24) +#define PINCTRL_CTRL_PRESENT3 (1 << 23) +#define PINCTRL_CTRL_PRESENT2 (1 << 22) +#define PINCTRL_CTRL_PRESENT1 (1 << 21) +#define PINCTRL_CTRL_PRESENT0 (1 << 20) +#define PINCTRL_CTRL_IRQOUT4 (1 << 4) +#define PINCTRL_CTRL_IRQOUT3 (1 << 3) +#define PINCTRL_CTRL_IRQOUT2 (1 << 2) +#define PINCTRL_CTRL_IRQOUT1 (1 << 1) +#define PINCTRL_CTRL_IRQOUT0 (1 << 0) + +#define PINCTRL_MUXSEL0_BANK0_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL0_BANK0_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL0_BANK0_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL0_BANK0_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL0_BANK0_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL0_BANK0_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL0_BANK0_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL0_BANK0_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL0_BANK0_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL0_BANK0_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL0_BANK0_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL0_BANK0_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL0_BANK0_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL0_BANK0_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL0_BANK0_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL0_BANK0_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL1_BANK0_PIN28_MASK (0x3 << 24) +#define PINCTRL_MUXSEL1_BANK0_PIN28_OFFSET 24 +#define PINCTRL_MUXSEL1_BANK0_PIN27_MASK (0x3 << 22) +#define PINCTRL_MUXSEL1_BANK0_PIN27_OFFSET 22 +#define PINCTRL_MUXSEL1_BANK0_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL1_BANK0_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL1_BANK0_PIN25_MASK (0x3 << 18) +#define PINCTRL_MUXSEL1_BANK0_PIN25_OFFSET 18 +#define PINCTRL_MUXSEL1_BANK0_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL1_BANK0_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL1_BANK0_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL1_BANK0_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL1_BANK0_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL1_BANK0_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL1_BANK0_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL1_BANK0_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL1_BANK0_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL1_BANK0_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL1_BANK0_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL1_BANK0_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL1_BANK0_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL1_BANK0_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL1_BANK0_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL1_BANK0_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL1_BANK0_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL1_BANK0_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL2_BANK1_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL2_BANK1_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL2_BANK1_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL2_BANK1_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL2_BANK1_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL2_BANK1_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL2_BANK1_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL2_BANK1_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL2_BANK1_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL2_BANK1_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL2_BANK1_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL2_BANK1_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL2_BANK1_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL2_BANK1_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL2_BANK1_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL2_BANK1_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL2_BANK1_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL2_BANK1_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL2_BANK1_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL2_BANK1_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL2_BANK1_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL2_BANK1_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL2_BANK1_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL2_BANK1_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL2_BANK1_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL2_BANK1_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL2_BANK1_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL2_BANK1_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL2_BANK1_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL2_BANK1_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL2_BANK1_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL2_BANK1_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL3_BANK1_PIN31_MASK (0x3 << 30) +#define PINCTRL_MUXSEL3_BANK1_PIN31_OFFSET 30 +#define PINCTRL_MUXSEL3_BANK1_PIN30_MASK (0x3 << 28) +#define PINCTRL_MUXSEL3_BANK1_PIN30_OFFSET 28 +#define PINCTRL_MUXSEL3_BANK1_PIN29_MASK (0x3 << 26) +#define PINCTRL_MUXSEL3_BANK1_PIN29_OFFSET 26 +#define PINCTRL_MUXSEL3_BANK1_PIN28_MASK (0x3 << 24) +#define PINCTRL_MUXSEL3_BANK1_PIN28_OFFSET 24 +#define PINCTRL_MUXSEL3_BANK1_PIN27_MASK (0x3 << 22) +#define PINCTRL_MUXSEL3_BANK1_PIN27_OFFSET 22 +#define PINCTRL_MUXSEL3_BANK1_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL3_BANK1_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL3_BANK1_PIN25_MASK (0x3 << 18) +#define PINCTRL_MUXSEL3_BANK1_PIN25_OFFSET 18 +#define PINCTRL_MUXSEL3_BANK1_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL3_BANK1_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL3_BANK1_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL3_BANK1_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL3_BANK1_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL3_BANK1_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL3_BANK1_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL3_BANK1_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL3_BANK1_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL3_BANK1_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL3_BANK1_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL3_BANK1_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL3_BANK1_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL3_BANK1_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL3_BANK1_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL3_BANK1_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL3_BANK1_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL3_BANK1_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL4_BANK2_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL4_BANK2_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL4_BANK2_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL4_BANK2_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL4_BANK2_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL4_BANK2_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL4_BANK2_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL4_BANK2_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL4_BANK2_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL4_BANK2_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL4_BANK2_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL4_BANK2_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL4_BANK2_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL4_BANK2_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL4_BANK2_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL4_BANK2_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL4_BANK2_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL4_BANK2_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL4_BANK2_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL4_BANK2_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL4_BANK2_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL4_BANK2_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL4_BANK2_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL4_BANK2_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL4_BANK2_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL4_BANK2_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL4_BANK2_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL4_BANK2_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL4_BANK2_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL4_BANK2_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL5_BANK2_PIN27_MASK (0x3 << 22) +#define PINCTRL_MUXSEL5_BANK2_PIN27_OFFSET 22 +#define PINCTRL_MUXSEL5_BANK2_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL5_BANK2_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL5_BANK2_PIN25_MASK (0x3 << 18) +#define PINCTRL_MUXSEL5_BANK2_PIN25_OFFSET 18 +#define PINCTRL_MUXSEL5_BANK2_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL5_BANK2_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL5_BANK2_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL5_BANK2_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL5_BANK2_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL5_BANK2_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL5_BANK2_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL5_BANK2_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL5_BANK2_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL5_BANK2_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL5_BANK2_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL5_BANK2_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL5_BANK2_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL5_BANK2_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL6_BANK3_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL6_BANK3_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL6_BANK3_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL6_BANK3_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL6_BANK3_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL6_BANK3_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL6_BANK3_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL6_BANK3_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL6_BANK3_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL6_BANK3_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL6_BANK3_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL6_BANK3_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL6_BANK3_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL6_BANK3_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL6_BANK3_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL6_BANK3_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL6_BANK3_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL6_BANK3_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL6_BANK3_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL6_BANK3_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL6_BANK3_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL6_BANK3_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL6_BANK3_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL6_BANK3_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL6_BANK3_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL6_BANK3_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL6_BANK3_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL6_BANK3_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL6_BANK3_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL6_BANK3_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL6_BANK3_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL6_BANK3_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL7_BANK3_PIN30_MASK (0x3 << 28) +#define PINCTRL_MUXSEL7_BANK3_PIN30_OFFSET 28 +#define PINCTRL_MUXSEL7_BANK3_PIN29_MASK (0x3 << 26) +#define PINCTRL_MUXSEL7_BANK3_PIN29_OFFSET 26 +#define PINCTRL_MUXSEL7_BANK3_PIN28_MASK (0x3 << 24) +#define PINCTRL_MUXSEL7_BANK3_PIN28_OFFSET 24 +#define PINCTRL_MUXSEL7_BANK3_PIN27_MASK (0x3 << 22) +#define PINCTRL_MUXSEL7_BANK3_PIN27_OFFSET 22 +#define PINCTRL_MUXSEL7_BANK3_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL7_BANK3_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL7_BANK3_PIN25_MASK (0x3 << 18) +#define PINCTRL_MUXSEL7_BANK3_PIN25_OFFSET 18 +#define PINCTRL_MUXSEL7_BANK3_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL7_BANK3_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL7_BANK3_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL7_BANK3_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL7_BANK3_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL7_BANK3_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL7_BANK3_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL7_BANK3_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL7_BANK3_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL7_BANK3_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL7_BANK3_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL7_BANK3_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL7_BANK3_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL7_BANK3_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL7_BANK3_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL7_BANK3_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL8_BANK4_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL8_BANK4_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL8_BANK4_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL8_BANK4_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL8_BANK4_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL8_BANK4_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL8_BANK4_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL8_BANK4_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL8_BANK4_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL8_BANK4_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL8_BANK4_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL8_BANK4_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL8_BANK4_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL8_BANK4_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL8_BANK4_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL8_BANK4_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL8_BANK4_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL8_BANK4_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL8_BANK4_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL8_BANK4_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL8_BANK4_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL8_BANK4_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL8_BANK4_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL8_BANK4_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL8_BANK4_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL8_BANK4_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL8_BANK4_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL8_BANK4_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL8_BANK4_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL8_BANK4_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL8_BANK4_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL8_BANK4_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL9_BANK4_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL9_BANK4_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL9_BANK4_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL9_BANK4_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL10_BANK5_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL10_BANK5_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL10_BANK5_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL10_BANK5_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL10_BANK5_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL10_BANK5_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL10_BANK5_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL10_BANK5_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL10_BANK5_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL10_BANK5_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL10_BANK5_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL10_BANK5_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL10_BANK5_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL10_BANK5_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL10_BANK5_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL10_BANK5_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL10_BANK5_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL10_BANK5_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL10_BANK5_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL10_BANK5_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL10_BANK5_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL10_BANK5_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL10_BANK5_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL10_BANK5_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL10_BANK5_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL10_BANK5_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL10_BANK5_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL10_BANK5_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL10_BANK5_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL10_BANK5_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL10_BANK5_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL10_BANK5_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL11_BANK5_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL11_BANK5_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL11_BANK5_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL11_BANK5_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL11_BANK5_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL11_BANK5_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL11_BANK5_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL11_BANK5_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL11_BANK5_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL11_BANK5_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL11_BANK5_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL11_BANK5_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL11_BANK5_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL11_BANK5_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL11_BANK5_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL11_BANK5_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL11_BANK5_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL11_BANK5_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL12_BANK6_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL12_BANK6_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL12_BANK6_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL12_BANK6_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL12_BANK6_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL12_BANK6_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL12_BANK6_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL12_BANK6_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL12_BANK6_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL12_BANK6_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL12_BANK6_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL12_BANK6_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL12_BANK6_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL12_BANK6_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL12_BANK6_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL12_BANK6_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL12_BANK6_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL12_BANK6_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL12_BANK6_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL12_BANK6_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL12_BANK6_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL12_BANK6_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL12_BANK6_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL12_BANK6_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL12_BANK6_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL12_BANK6_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL12_BANK6_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL12_BANK6_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL12_BANK6_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL12_BANK6_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL13_BANK6_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL13_BANK6_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL13_BANK6_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL13_BANK6_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL13_BANK6_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL13_BANK6_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL13_BANK6_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL13_BANK6_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL13_BANK6_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL13_BANK6_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL13_BANK6_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL13_BANK6_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL13_BANK6_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL13_BANK6_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL13_BANK6_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL13_BANK6_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL13_BANK6_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL13_BANK6_PIN16_OFFSET 0 + +#define PINCTRL_DRIVE0_BANK0_PIN07_V (1 << 30) +#define PINCTRL_DRIVE0_BANK0_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE0_BANK0_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE0_BANK0_PIN06_V (1 << 26) +#define PINCTRL_DRIVE0_BANK0_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE0_BANK0_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE0_BANK0_PIN05_V (1 << 22) +#define PINCTRL_DRIVE0_BANK0_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE0_BANK0_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE0_BANK0_PIN04_V (1 << 18) +#define PINCTRL_DRIVE0_BANK0_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE0_BANK0_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE0_BANK0_PIN03_V (1 << 14) +#define PINCTRL_DRIVE0_BANK0_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE0_BANK0_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE0_BANK0_PIN02_V (1 << 10) +#define PINCTRL_DRIVE0_BANK0_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE0_BANK0_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE0_BANK0_PIN01_V (1 << 6) +#define PINCTRL_DRIVE0_BANK0_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE0_BANK0_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE0_BANK0_PIN00_V (1 << 2) +#define PINCTRL_DRIVE0_BANK0_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE0_BANK0_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE2_BANK0_PIN23_V (1 << 30) +#define PINCTRL_DRIVE2_BANK0_PIN23_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE2_BANK0_PIN23_MA_OFFSET 28 +#define PINCTRL_DRIVE2_BANK0_PIN22_V (1 << 26) +#define PINCTRL_DRIVE2_BANK0_PIN22_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE2_BANK0_PIN22_MA_OFFSET 24 +#define PINCTRL_DRIVE2_BANK0_PIN21_V (1 << 22) +#define PINCTRL_DRIVE2_BANK0_PIN21_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE2_BANK0_PIN21_MA_OFFSET 20 +#define PINCTRL_DRIVE2_BANK0_PIN20_V (1 << 18) +#define PINCTRL_DRIVE2_BANK0_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE2_BANK0_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE2_BANK0_PIN19_V (1 << 14) +#define PINCTRL_DRIVE2_BANK0_PIN19_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE2_BANK0_PIN19_MA_OFFSET 12 +#define PINCTRL_DRIVE2_BANK0_PIN18_V (1 << 10) +#define PINCTRL_DRIVE2_BANK0_PIN18_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE2_BANK0_PIN18_MA_OFFSET 8 +#define PINCTRL_DRIVE2_BANK0_PIN17_V (1 << 6) +#define PINCTRL_DRIVE2_BANK0_PIN17_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE2_BANK0_PIN17_MA_OFFSET 4 +#define PINCTRL_DRIVE2_BANK0_PIN16_V (1 << 2) +#define PINCTRL_DRIVE2_BANK0_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE2_BANK0_PIN16_MA_OFFSET 0 + +#define PINCTRL_DRIVE3_BANK0_PIN28_V (1 << 18) +#define PINCTRL_DRIVE3_BANK0_PIN28_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE3_BANK0_PIN28_MA_OFFSET 16 +#define PINCTRL_DRIVE3_BANK0_PIN27_V (1 << 14) +#define PINCTRL_DRIVE3_BANK0_PIN27_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE3_BANK0_PIN27_MA_OFFSET 12 +#define PINCTRL_DRIVE3_BANK0_PIN26_V (1 << 10) +#define PINCTRL_DRIVE3_BANK0_PIN26_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE3_BANK0_PIN26_MA_OFFSET 8 +#define PINCTRL_DRIVE3_BANK0_PIN25_V (1 << 6) +#define PINCTRL_DRIVE3_BANK0_PIN25_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE3_BANK0_PIN25_MA_OFFSET 4 +#define PINCTRL_DRIVE3_BANK0_PIN24_V (1 << 2) +#define PINCTRL_DRIVE3_BANK0_PIN24_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE3_BANK0_PIN24_MA_OFFSET 0 + +#define PINCTRL_DRIVE4_BANK1_PIN07_V (1 << 30) +#define PINCTRL_DRIVE4_BANK1_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE4_BANK1_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE4_BANK1_PIN06_V (1 << 26) +#define PINCTRL_DRIVE4_BANK1_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE4_BANK1_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE4_BANK1_PIN05_V (1 << 22) +#define PINCTRL_DRIVE4_BANK1_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE4_BANK1_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE4_BANK1_PIN04_V (1 << 18) +#define PINCTRL_DRIVE4_BANK1_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE4_BANK1_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE4_BANK1_PIN03_V (1 << 14) +#define PINCTRL_DRIVE4_BANK1_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE4_BANK1_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE4_BANK1_PIN02_V (1 << 10) +#define PINCTRL_DRIVE4_BANK1_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE4_BANK1_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE4_BANK1_PIN01_V (1 << 6) +#define PINCTRL_DRIVE4_BANK1_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE4_BANK1_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE4_BANK1_PIN00_V (1 << 2) +#define PINCTRL_DRIVE4_BANK1_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE4_BANK1_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE5_BANK1_PIN15_V (1 << 30) +#define PINCTRL_DRIVE5_BANK1_PIN15_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE5_BANK1_PIN15_MA_OFFSET 28 +#define PINCTRL_DRIVE5_BANK1_PIN14_V (1 << 26) +#define PINCTRL_DRIVE5_BANK1_PIN14_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE5_BANK1_PIN14_MA_OFFSET 24 +#define PINCTRL_DRIVE5_BANK1_PIN13_V (1 << 22) +#define PINCTRL_DRIVE5_BANK1_PIN13_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE5_BANK1_PIN13_MA_OFFSET 20 +#define PINCTRL_DRIVE5_BANK1_PIN12_V (1 << 18) +#define PINCTRL_DRIVE5_BANK1_PIN12_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE5_BANK1_PIN12_MA_OFFSET 16 +#define PINCTRL_DRIVE5_BANK1_PIN11_V (1 << 14) +#define PINCTRL_DRIVE5_BANK1_PIN11_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE5_BANK1_PIN11_MA_OFFSET 12 +#define PINCTRL_DRIVE5_BANK1_PIN10_V (1 << 10) +#define PINCTRL_DRIVE5_BANK1_PIN10_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE5_BANK1_PIN10_MA_OFFSET 8 +#define PINCTRL_DRIVE5_BANK1_PIN09_V (1 << 6) +#define PINCTRL_DRIVE5_BANK1_PIN09_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE5_BANK1_PIN09_MA_OFFSET 4 +#define PINCTRL_DRIVE5_BANK1_PIN08_V (1 << 2) +#define PINCTRL_DRIVE5_BANK1_PIN08_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE5_BANK1_PIN08_MA_OFFSET 0 + +#define PINCTRL_DRIVE6_BANK1_PIN23_V (1 << 30) +#define PINCTRL_DRIVE6_BANK1_PIN23_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE6_BANK1_PIN23_MA_OFFSET 28 +#define PINCTRL_DRIVE6_BANK1_PIN22_V (1 << 26) +#define PINCTRL_DRIVE6_BANK1_PIN22_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE6_BANK1_PIN22_MA_OFFSET 24 +#define PINCTRL_DRIVE6_BANK1_PIN21_V (1 << 22) +#define PINCTRL_DRIVE6_BANK1_PIN21_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE6_BANK1_PIN21_MA_OFFSET 20 +#define PINCTRL_DRIVE6_BANK1_PIN20_V (1 << 18) +#define PINCTRL_DRIVE6_BANK1_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE6_BANK1_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE6_BANK1_PIN19_V (1 << 14) +#define PINCTRL_DRIVE6_BANK1_PIN19_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE6_BANK1_PIN19_MA_OFFSET 12 +#define PINCTRL_DRIVE6_BANK1_PIN18_V (1 << 10) +#define PINCTRL_DRIVE6_BANK1_PIN18_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE6_BANK1_PIN18_MA_OFFSET 8 +#define PINCTRL_DRIVE6_BANK1_PIN17_V (1 << 6) +#define PINCTRL_DRIVE6_BANK1_PIN17_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE6_BANK1_PIN17_MA_OFFSET 4 +#define PINCTRL_DRIVE6_BANK1_PIN16_V (1 << 2) +#define PINCTRL_DRIVE6_BANK1_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE6_BANK1_PIN16_MA_OFFSET 0 + +#define PINCTRL_DRIVE7_BANK1_PIN31_V (1 << 30) +#define PINCTRL_DRIVE7_BANK1_PIN31_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE7_BANK1_PIN31_MA_OFFSET 28 +#define PINCTRL_DRIVE7_BANK1_PIN30_V (1 << 26) +#define PINCTRL_DRIVE7_BANK1_PIN30_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE7_BANK1_PIN30_MA_OFFSET 24 +#define PINCTRL_DRIVE7_BANK1_PIN29_V (1 << 22) +#define PINCTRL_DRIVE7_BANK1_PIN29_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE7_BANK1_PIN29_MA_OFFSET 20 +#define PINCTRL_DRIVE7_BANK1_PIN28_V (1 << 18) +#define PINCTRL_DRIVE7_BANK1_PIN28_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE7_BANK1_PIN28_MA_OFFSET 16 +#define PINCTRL_DRIVE7_BANK1_PIN27_V (1 << 14) +#define PINCTRL_DRIVE7_BANK1_PIN27_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE7_BANK1_PIN27_MA_OFFSET 12 +#define PINCTRL_DRIVE7_BANK1_PIN26_V (1 << 10) +#define PINCTRL_DRIVE7_BANK1_PIN26_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE7_BANK1_PIN26_MA_OFFSET 8 +#define PINCTRL_DRIVE7_BANK1_PIN25_V (1 << 6) +#define PINCTRL_DRIVE7_BANK1_PIN25_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE7_BANK1_PIN25_MA_OFFSET 4 +#define PINCTRL_DRIVE7_BANK1_PIN24_V (1 << 2) +#define PINCTRL_DRIVE7_BANK1_PIN24_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE7_BANK1_PIN24_MA_OFFSET 0 + +#define PINCTRL_DRIVE8_BANK2_PIN07_V (1 << 30) +#define PINCTRL_DRIVE8_BANK2_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE8_BANK2_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE8_BANK2_PIN06_V (1 << 26) +#define PINCTRL_DRIVE8_BANK2_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE8_BANK2_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE8_BANK2_PIN05_V (1 << 22) +#define PINCTRL_DRIVE8_BANK2_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE8_BANK2_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE8_BANK2_PIN04_V (1 << 18) +#define PINCTRL_DRIVE8_BANK2_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE8_BANK2_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE8_BANK2_PIN03_V (1 << 14) +#define PINCTRL_DRIVE8_BANK2_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE8_BANK2_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE8_BANK2_PIN02_V (1 << 10) +#define PINCTRL_DRIVE8_BANK2_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE8_BANK2_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE8_BANK2_PIN01_V (1 << 6) +#define PINCTRL_DRIVE8_BANK2_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE8_BANK2_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE8_BANK2_PIN00_V (1 << 2) +#define PINCTRL_DRIVE8_BANK2_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE8_BANK2_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE9_BANK2_PIN15_V (1 << 30) +#define PINCTRL_DRIVE9_BANK2_PIN15_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE9_BANK2_PIN15_MA_OFFSET 28 +#define PINCTRL_DRIVE9_BANK2_PIN14_V (1 << 26) +#define PINCTRL_DRIVE9_BANK2_PIN14_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE9_BANK2_PIN14_MA_OFFSET 24 +#define PINCTRL_DRIVE9_BANK2_PIN13_V (1 << 22) +#define PINCTRL_DRIVE9_BANK2_PIN13_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE9_BANK2_PIN13_MA_OFFSET 20 +#define PINCTRL_DRIVE9_BANK2_PIN12_V (1 << 18) +#define PINCTRL_DRIVE9_BANK2_PIN12_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE9_BANK2_PIN12_MA_OFFSET 16 +#define PINCTRL_DRIVE9_BANK2_PIN10_V (1 << 10) +#define PINCTRL_DRIVE9_BANK2_PIN10_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE9_BANK2_PIN10_MA_OFFSET 8 +#define PINCTRL_DRIVE9_BANK2_PIN09_V (1 << 6) +#define PINCTRL_DRIVE9_BANK2_PIN09_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE9_BANK2_PIN09_MA_OFFSET 4 +#define PINCTRL_DRIVE9_BANK2_PIN08_V (1 << 2) +#define PINCTRL_DRIVE9_BANK2_PIN08_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE9_BANK2_PIN08_MA_OFFSET 0 + +#define PINCTRL_DRIVE10_BANK2_PIN21_V (1 << 22) +#define PINCTRL_DRIVE10_BANK2_PIN21_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE10_BANK2_PIN21_MA_OFFSET 20 +#define PINCTRL_DRIVE10_BANK2_PIN20_V (1 << 18) +#define PINCTRL_DRIVE10_BANK2_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE10_BANK2_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE10_BANK2_PIN19_V (1 << 14) +#define PINCTRL_DRIVE10_BANK2_PIN19_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE10_BANK2_PIN19_MA_OFFSET 12 +#define PINCTRL_DRIVE10_BANK2_PIN18_V (1 << 10) +#define PINCTRL_DRIVE10_BANK2_PIN18_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE10_BANK2_PIN18_MA_OFFSET 8 +#define PINCTRL_DRIVE10_BANK2_PIN17_V (1 << 6) +#define PINCTRL_DRIVE10_BANK2_PIN17_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE10_BANK2_PIN17_MA_OFFSET 4 +#define PINCTRL_DRIVE10_BANK2_PIN16_V (1 << 2) +#define PINCTRL_DRIVE10_BANK2_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE10_BANK2_PIN16_MA_OFFSET 0 + +#define PINCTRL_DRIVE11_BANK2_PIN27_V (1 << 14) +#define PINCTRL_DRIVE11_BANK2_PIN27_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE11_BANK2_PIN27_MA_OFFSET 12 +#define PINCTRL_DRIVE11_BANK2_PIN26_V (1 << 10) +#define PINCTRL_DRIVE11_BANK2_PIN26_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE11_BANK2_PIN26_MA_OFFSET 8 +#define PINCTRL_DRIVE11_BANK2_PIN25_V (1 << 6) +#define PINCTRL_DRIVE11_BANK2_PIN25_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE11_BANK2_PIN25_MA_OFFSET 4 +#define PINCTRL_DRIVE11_BANK2_PIN24_V (1 << 2) +#define PINCTRL_DRIVE11_BANK2_PIN24_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE11_BANK2_PIN24_MA_OFFSET 0 + +#define PINCTRL_DRIVE12_BANK3_PIN07_V (1 << 30) +#define PINCTRL_DRIVE12_BANK3_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE12_BANK3_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE12_BANK3_PIN06_V (1 << 26) +#define PINCTRL_DRIVE12_BANK3_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE12_BANK3_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE12_BANK3_PIN05_V (1 << 22) +#define PINCTRL_DRIVE12_BANK3_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE12_BANK3_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE12_BANK3_PIN04_V (1 << 18) +#define PINCTRL_DRIVE12_BANK3_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE12_BANK3_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE12_BANK3_PIN03_V (1 << 14) +#define PINCTRL_DRIVE12_BANK3_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE12_BANK3_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE12_BANK3_PIN02_V (1 << 10) +#define PINCTRL_DRIVE12_BANK3_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE12_BANK3_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE12_BANK3_PIN01_V (1 << 6) +#define PINCTRL_DRIVE12_BANK3_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE12_BANK3_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE12_BANK3_PIN00_V (1 << 2) +#define PINCTRL_DRIVE12_BANK3_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE12_BANK3_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE13_BANK3_PIN15_V (1 << 30) +#define PINCTRL_DRIVE13_BANK3_PIN15_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE13_BANK3_PIN15_MA_OFFSET 28 +#define PINCTRL_DRIVE13_BANK3_PIN14_V (1 << 26) +#define PINCTRL_DRIVE13_BANK3_PIN14_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE13_BANK3_PIN14_MA_OFFSET 24 +#define PINCTRL_DRIVE13_BANK3_PIN13_V (1 << 22) +#define PINCTRL_DRIVE13_BANK3_PIN13_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE13_BANK3_PIN13_MA_OFFSET 20 +#define PINCTRL_DRIVE13_BANK3_PIN12_V (1 << 18) +#define PINCTRL_DRIVE13_BANK3_PIN12_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE13_BANK3_PIN12_MA_OFFSET 16 +#define PINCTRL_DRIVE13_BANK3_PIN11_V (1 << 14) +#define PINCTRL_DRIVE13_BANK3_PIN11_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE13_BANK3_PIN11_MA_OFFSET 12 +#define PINCTRL_DRIVE13_BANK3_PIN10_V (1 << 10) +#define PINCTRL_DRIVE13_BANK3_PIN10_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE13_BANK3_PIN10_MA_OFFSET 8 +#define PINCTRL_DRIVE13_BANK3_PIN09_V (1 << 6) +#define PINCTRL_DRIVE13_BANK3_PIN09_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE13_BANK3_PIN09_MA_OFFSET 4 +#define PINCTRL_DRIVE13_BANK3_PIN08_V (1 << 2) +#define PINCTRL_DRIVE13_BANK3_PIN08_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE13_BANK3_PIN08_MA_OFFSET 0 + +#define PINCTRL_DRIVE14_BANK3_PIN23_V (1 << 30) +#define PINCTRL_DRIVE14_BANK3_PIN23_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE14_BANK3_PIN23_MA_OFFSET 28 +#define PINCTRL_DRIVE14_BANK3_PIN22_V (1 << 26) +#define PINCTRL_DRIVE14_BANK3_PIN22_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE14_BANK3_PIN22_MA_OFFSET 24 +#define PINCTRL_DRIVE14_BANK3_PIN21_V (1 << 22) +#define PINCTRL_DRIVE14_BANK3_PIN21_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE14_BANK3_PIN21_MA_OFFSET 20 +#define PINCTRL_DRIVE14_BANK3_PIN20_V (1 << 18) +#define PINCTRL_DRIVE14_BANK3_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE14_BANK3_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE14_BANK3_PIN18_V (1 << 10) +#define PINCTRL_DRIVE14_BANK3_PIN18_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE14_BANK3_PIN18_MA_OFFSET 8 +#define PINCTRL_DRIVE14_BANK3_PIN17_V (1 << 6) +#define PINCTRL_DRIVE14_BANK3_PIN17_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE14_BANK3_PIN17_MA_OFFSET 4 +#define PINCTRL_DRIVE14_BANK3_PIN16_V (1 << 2) +#define PINCTRL_DRIVE14_BANK3_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE14_BANK3_PIN16_MA_OFFSET 0 + +#define PINCTRL_DRIVE15_BANK3_PIN30_V (1 << 26) +#define PINCTRL_DRIVE15_BANK3_PIN30_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE15_BANK3_PIN30_MA_OFFSET 24 +#define PINCTRL_DRIVE15_BANK3_PIN29_V (1 << 22) +#define PINCTRL_DRIVE15_BANK3_PIN29_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE15_BANK3_PIN29_MA_OFFSET 20 +#define PINCTRL_DRIVE15_BANK3_PIN28_V (1 << 18) +#define PINCTRL_DRIVE15_BANK3_PIN28_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE15_BANK3_PIN28_MA_OFFSET 16 +#define PINCTRL_DRIVE15_BANK3_PIN27_V (1 << 14) +#define PINCTRL_DRIVE15_BANK3_PIN27_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE15_BANK3_PIN27_MA_OFFSET 12 +#define PINCTRL_DRIVE15_BANK3_PIN26_V (1 << 10) +#define PINCTRL_DRIVE15_BANK3_PIN26_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE15_BANK3_PIN26_MA_OFFSET 8 +#define PINCTRL_DRIVE15_BANK3_PIN25_V (1 << 6) +#define PINCTRL_DRIVE15_BANK3_PIN25_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE15_BANK3_PIN25_MA_OFFSET 4 +#define PINCTRL_DRIVE15_BANK3_PIN24_V (1 << 2) +#define PINCTRL_DRIVE15_BANK3_PIN24_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE15_BANK3_PIN24_MA_OFFSET 0 + +#define PINCTRL_DRIVE16_BANK4_PIN07_V (1 << 30) +#define PINCTRL_DRIVE16_BANK4_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE16_BANK4_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE16_BANK4_PIN06_V (1 << 26) +#define PINCTRL_DRIVE16_BANK4_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE16_BANK4_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE16_BANK4_PIN05_V (1 << 22) +#define PINCTRL_DRIVE16_BANK4_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE16_BANK4_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE16_BANK4_PIN04_V (1 << 18) +#define PINCTRL_DRIVE16_BANK4_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE16_BANK4_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE16_BANK4_PIN03_V (1 << 14) +#define PINCTRL_DRIVE16_BANK4_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE16_BANK4_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE16_BANK4_PIN02_V (1 << 10) +#define PINCTRL_DRIVE16_BANK4_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE16_BANK4_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE16_BANK4_PIN01_V (1 << 6) +#define PINCTRL_DRIVE16_BANK4_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE16_BANK4_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE16_BANK4_PIN00_V (1 << 2) +#define PINCTRL_DRIVE16_BANK4_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE16_BANK4_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE17_BANK4_PIN15_V (1 << 30) +#define PINCTRL_DRIVE17_BANK4_PIN15_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE17_BANK4_PIN15_MA_OFFSET 28 +#define PINCTRL_DRIVE17_BANK4_PIN14_V (1 << 26) +#define PINCTRL_DRIVE17_BANK4_PIN14_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE17_BANK4_PIN14_MA_OFFSET 24 +#define PINCTRL_DRIVE17_BANK4_PIN13_V (1 << 22) +#define PINCTRL_DRIVE17_BANK4_PIN13_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE17_BANK4_PIN13_MA_OFFSET 20 +#define PINCTRL_DRIVE17_BANK4_PIN12_V (1 << 18) +#define PINCTRL_DRIVE17_BANK4_PIN12_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE17_BANK4_PIN12_MA_OFFSET 16 +#define PINCTRL_DRIVE17_BANK4_PIN11_V (1 << 14) +#define PINCTRL_DRIVE17_BANK4_PIN11_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE17_BANK4_PIN11_MA_OFFSET 12 +#define PINCTRL_DRIVE17_BANK4_PIN10_V (1 << 10) +#define PINCTRL_DRIVE17_BANK4_PIN10_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE17_BANK4_PIN10_MA_OFFSET 8 +#define PINCTRL_DRIVE17_BANK4_PIN09_V (1 << 6) +#define PINCTRL_DRIVE17_BANK4_PIN09_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE17_BANK4_PIN09_MA_OFFSET 4 +#define PINCTRL_DRIVE17_BANK4_PIN08_V (1 << 2) +#define PINCTRL_DRIVE17_BANK4_PIN08_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE17_BANK4_PIN08_MA_OFFSET 0 + +#define PINCTRL_DRIVE18_BANK4_PIN20_V (1 << 18) +#define PINCTRL_DRIVE18_BANK4_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE18_BANK4_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE18_BANK4_PIN16_V (1 << 2) +#define PINCTRL_DRIVE18_BANK4_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE18_BANK4_PIN16_MA_OFFSET 0 + +#define PINCTRL_PULL0_BANK0_PIN28 (1 << 28) +#define PINCTRL_PULL0_BANK0_PIN27 (1 << 27) +#define PINCTRL_PULL0_BANK0_PIN26 (1 << 26) +#define PINCTRL_PULL0_BANK0_PIN25 (1 << 25) +#define PINCTRL_PULL0_BANK0_PIN24 (1 << 24) +#define PINCTRL_PULL0_BANK0_PIN23 (1 << 23) +#define PINCTRL_PULL0_BANK0_PIN22 (1 << 22) +#define PINCTRL_PULL0_BANK0_PIN21 (1 << 21) +#define PINCTRL_PULL0_BANK0_PIN20 (1 << 20) +#define PINCTRL_PULL0_BANK0_PIN19 (1 << 19) +#define PINCTRL_PULL0_BANK0_PIN18 (1 << 18) +#define PINCTRL_PULL0_BANK0_PIN17 (1 << 17) +#define PINCTRL_PULL0_BANK0_PIN16 (1 << 16) +#define PINCTRL_PULL0_BANK0_PIN07 (1 << 7) +#define PINCTRL_PULL0_BANK0_PIN06 (1 << 6) +#define PINCTRL_PULL0_BANK0_PIN05 (1 << 5) +#define PINCTRL_PULL0_BANK0_PIN04 (1 << 4) +#define PINCTRL_PULL0_BANK0_PIN03 (1 << 3) +#define PINCTRL_PULL0_BANK0_PIN02 (1 << 2) +#define PINCTRL_PULL0_BANK0_PIN01 (1 << 1) +#define PINCTRL_PULL0_BANK0_PIN00 (1 << 0) + +#define PINCTRL_PULL1_BANK1_PIN31 (1 << 31) +#define PINCTRL_PULL1_BANK1_PIN30 (1 << 30) +#define PINCTRL_PULL1_BANK1_PIN29 (1 << 29) +#define PINCTRL_PULL1_BANK1_PIN28 (1 << 28) +#define PINCTRL_PULL1_BANK1_PIN27 (1 << 27) +#define PINCTRL_PULL1_BANK1_PIN26 (1 << 26) +#define PINCTRL_PULL1_BANK1_PIN25 (1 << 25) +#define PINCTRL_PULL1_BANK1_PIN24 (1 << 24) +#define PINCTRL_PULL1_BANK1_PIN23 (1 << 23) +#define PINCTRL_PULL1_BANK1_PIN22 (1 << 22) +#define PINCTRL_PULL1_BANK1_PIN21 (1 << 21) +#define PINCTRL_PULL1_BANK1_PIN20 (1 << 20) +#define PINCTRL_PULL1_BANK1_PIN19 (1 << 19) +#define PINCTRL_PULL1_BANK1_PIN18 (1 << 18) +#define PINCTRL_PULL1_BANK1_PIN17 (1 << 17) +#define PINCTRL_PULL1_BANK1_PIN16 (1 << 16) +#define PINCTRL_PULL1_BANK1_PIN15 (1 << 15) +#define PINCTRL_PULL1_BANK1_PIN14 (1 << 14) +#define PINCTRL_PULL1_BANK1_PIN13 (1 << 13) +#define PINCTRL_PULL1_BANK1_PIN12 (1 << 12) +#define PINCTRL_PULL1_BANK1_PIN11 (1 << 11) +#define PINCTRL_PULL1_BANK1_PIN10 (1 << 10) +#define PINCTRL_PULL1_BANK1_PIN09 (1 << 9) +#define PINCTRL_PULL1_BANK1_PIN08 (1 << 8) +#define PINCTRL_PULL1_BANK1_PIN07 (1 << 7) +#define PINCTRL_PULL1_BANK1_PIN06 (1 << 6) +#define PINCTRL_PULL1_BANK1_PIN05 (1 << 5) +#define PINCTRL_PULL1_BANK1_PIN04 (1 << 4) +#define PINCTRL_PULL1_BANK1_PIN03 (1 << 3) +#define PINCTRL_PULL1_BANK1_PIN02 (1 << 2) +#define PINCTRL_PULL1_BANK1_PIN01 (1 << 1) +#define PINCTRL_PULL1_BANK1_PIN00 (1 << 0) + +#define PINCTRL_PULL2_BANK2_PIN27 (1 << 27) +#define PINCTRL_PULL2_BANK2_PIN26 (1 << 26) +#define PINCTRL_PULL2_BANK2_PIN25 (1 << 25) +#define PINCTRL_PULL2_BANK2_PIN24 (1 << 24) +#define PINCTRL_PULL2_BANK2_PIN21 (1 << 21) +#define PINCTRL_PULL2_BANK2_PIN20 (1 << 20) +#define PINCTRL_PULL2_BANK2_PIN19 (1 << 19) +#define PINCTRL_PULL2_BANK2_PIN18 (1 << 18) +#define PINCTRL_PULL2_BANK2_PIN17 (1 << 17) +#define PINCTRL_PULL2_BANK2_PIN16 (1 << 16) +#define PINCTRL_PULL2_BANK2_PIN15 (1 << 15) +#define PINCTRL_PULL2_BANK2_PIN14 (1 << 14) +#define PINCTRL_PULL2_BANK2_PIN13 (1 << 13) +#define PINCTRL_PULL2_BANK2_PIN12 (1 << 12) +#define PINCTRL_PULL2_BANK2_PIN10 (1 << 10) +#define PINCTRL_PULL2_BANK2_PIN09 (1 << 9) +#define PINCTRL_PULL2_BANK2_PIN08 (1 << 8) +#define PINCTRL_PULL2_BANK2_PIN07 (1 << 7) +#define PINCTRL_PULL2_BANK2_PIN06 (1 << 6) +#define PINCTRL_PULL2_BANK2_PIN05 (1 << 5) +#define PINCTRL_PULL2_BANK2_PIN04 (1 << 4) +#define PINCTRL_PULL2_BANK2_PIN03 (1 << 3) +#define PINCTRL_PULL2_BANK2_PIN02 (1 << 2) +#define PINCTRL_PULL2_BANK2_PIN01 (1 << 1) +#define PINCTRL_PULL2_BANK2_PIN00 (1 << 0) + +#define PINCTRL_PULL3_BANK3_PIN30 (1 << 30) +#define PINCTRL_PULL3_BANK3_PIN29 (1 << 29) +#define PINCTRL_PULL3_BANK3_PIN28 (1 << 28) +#define PINCTRL_PULL3_BANK3_PIN27 (1 << 27) +#define PINCTRL_PULL3_BANK3_PIN26 (1 << 26) +#define PINCTRL_PULL3_BANK3_PIN25 (1 << 25) +#define PINCTRL_PULL3_BANK3_PIN24 (1 << 24) +#define PINCTRL_PULL3_BANK3_PIN23 (1 << 23) +#define PINCTRL_PULL3_BANK3_PIN22 (1 << 22) +#define PINCTRL_PULL3_BANK3_PIN21 (1 << 21) +#define PINCTRL_PULL3_BANK3_PIN20 (1 << 20) +#define PINCTRL_PULL3_BANK3_PIN18 (1 << 18) +#define PINCTRL_PULL3_BANK3_PIN17 (1 << 17) +#define PINCTRL_PULL3_BANK3_PIN16 (1 << 16) +#define PINCTRL_PULL3_BANK3_PIN15 (1 << 15) +#define PINCTRL_PULL3_BANK3_PIN14 (1 << 14) +#define PINCTRL_PULL3_BANK3_PIN13 (1 << 13) +#define PINCTRL_PULL3_BANK3_PIN12 (1 << 12) +#define PINCTRL_PULL3_BANK3_PIN11 (1 << 11) +#define PINCTRL_PULL3_BANK3_PIN10 (1 << 10) +#define PINCTRL_PULL3_BANK3_PIN09 (1 << 9) +#define PINCTRL_PULL3_BANK3_PIN08 (1 << 8) +#define PINCTRL_PULL3_BANK3_PIN07 (1 << 7) +#define PINCTRL_PULL3_BANK3_PIN06 (1 << 6) +#define PINCTRL_PULL3_BANK3_PIN05 (1 << 5) +#define PINCTRL_PULL3_BANK3_PIN04 (1 << 4) +#define PINCTRL_PULL3_BANK3_PIN03 (1 << 3) +#define PINCTRL_PULL3_BANK3_PIN02 (1 << 2) +#define PINCTRL_PULL3_BANK3_PIN01 (1 << 1) +#define PINCTRL_PULL3_BANK3_PIN00 (1 << 0) + +#define PINCTRL_PULL4_BANK4_PIN20 (1 << 20) +#define PINCTRL_PULL4_BANK4_PIN16 (1 << 16) +#define PINCTRL_PULL4_BANK4_PIN15 (1 << 15) +#define PINCTRL_PULL4_BANK4_PIN14 (1 << 14) +#define PINCTRL_PULL4_BANK4_PIN13 (1 << 13) +#define PINCTRL_PULL4_BANK4_PIN12 (1 << 12) +#define PINCTRL_PULL4_BANK4_PIN11 (1 << 11) +#define PINCTRL_PULL4_BANK4_PIN10 (1 << 10) +#define PINCTRL_PULL4_BANK4_PIN09 (1 << 9) +#define PINCTRL_PULL4_BANK4_PIN08 (1 << 8) +#define PINCTRL_PULL4_BANK4_PIN07 (1 << 7) +#define PINCTRL_PULL4_BANK4_PIN06 (1 << 6) +#define PINCTRL_PULL4_BANK4_PIN05 (1 << 5) +#define PINCTRL_PULL4_BANK4_PIN04 (1 << 4) +#define PINCTRL_PULL4_BANK4_PIN03 (1 << 3) +#define PINCTRL_PULL4_BANK4_PIN02 (1 << 2) +#define PINCTRL_PULL4_BANK4_PIN01 (1 << 1) +#define PINCTRL_PULL4_BANK4_PIN00 (1 << 0) + +#define PINCTRL_PULL5_BANK5_PIN26 (1 << 26) +#define PINCTRL_PULL5_BANK5_PIN23 (1 << 23) +#define PINCTRL_PULL5_BANK5_PIN22 (1 << 22) +#define PINCTRL_PULL5_BANK5_PIN21 (1 << 21) +#define PINCTRL_PULL5_BANK5_PIN20 (1 << 20) +#define PINCTRL_PULL5_BANK5_PIN19 (1 << 19) +#define PINCTRL_PULL5_BANK5_PIN18 (1 << 18) +#define PINCTRL_PULL5_BANK5_PIN17 (1 << 17) +#define PINCTRL_PULL5_BANK5_PIN16 (1 << 16) +#define PINCTRL_PULL5_BANK5_PIN15 (1 << 15) +#define PINCTRL_PULL5_BANK5_PIN14 (1 << 14) +#define PINCTRL_PULL5_BANK5_PIN13 (1 << 13) +#define PINCTRL_PULL5_BANK5_PIN12 (1 << 12) +#define PINCTRL_PULL5_BANK5_PIN11 (1 << 11) +#define PINCTRL_PULL5_BANK5_PIN10 (1 << 10) +#define PINCTRL_PULL5_BANK5_PIN09 (1 << 9) +#define PINCTRL_PULL5_BANK5_PIN08 (1 << 8) +#define PINCTRL_PULL5_BANK5_PIN07 (1 << 7) +#define PINCTRL_PULL5_BANK5_PIN06 (1 << 6) +#define PINCTRL_PULL5_BANK5_PIN05 (1 << 5) +#define PINCTRL_PULL5_BANK5_PIN04 (1 << 4) +#define PINCTRL_PULL5_BANK5_PIN03 (1 << 3) +#define PINCTRL_PULL5_BANK5_PIN02 (1 << 2) +#define PINCTRL_PULL5_BANK5_PIN01 (1 << 1) +#define PINCTRL_PULL5_BANK5_PIN00 (1 << 0) + +#define PINCTRL_PULL6_BANK6_PIN24 (1 << 24) +#define PINCTRL_PULL6_BANK6_PIN23 (1 << 23) +#define PINCTRL_PULL6_BANK6_PIN22 (1 << 22) +#define PINCTRL_PULL6_BANK6_PIN21 (1 << 21) +#define PINCTRL_PULL6_BANK6_PIN20 (1 << 20) +#define PINCTRL_PULL6_BANK6_PIN19 (1 << 19) +#define PINCTRL_PULL6_BANK6_PIN18 (1 << 18) +#define PINCTRL_PULL6_BANK6_PIN17 (1 << 17) +#define PINCTRL_PULL6_BANK6_PIN16 (1 << 16) +#define PINCTRL_PULL6_BANK6_PIN14 (1 << 14) +#define PINCTRL_PULL6_BANK6_PIN13 (1 << 13) +#define PINCTRL_PULL6_BANK6_PIN12 (1 << 12) +#define PINCTRL_PULL6_BANK6_PIN11 (1 << 11) +#define PINCTRL_PULL6_BANK6_PIN10 (1 << 10) +#define PINCTRL_PULL6_BANK6_PIN09 (1 << 9) +#define PINCTRL_PULL6_BANK6_PIN08 (1 << 8) +#define PINCTRL_PULL6_BANK6_PIN07 (1 << 7) +#define PINCTRL_PULL6_BANK6_PIN06 (1 << 6) +#define PINCTRL_PULL6_BANK6_PIN05 (1 << 5) +#define PINCTRL_PULL6_BANK6_PIN04 (1 << 4) +#define PINCTRL_PULL6_BANK6_PIN03 (1 << 3) +#define PINCTRL_PULL6_BANK6_PIN02 (1 << 2) +#define PINCTRL_PULL6_BANK6_PIN01 (1 << 1) +#define PINCTRL_PULL6_BANK6_PIN00 (1 << 0) + +#define PINCTRL_DOUT0_DOUT_MASK 0x1fffffff +#define PINCTRL_DOUT0_DOUT_OFFSET 0 + +#define PINCTRL_DOUT1_DOUT_MASK 0xffffffff +#define PINCTRL_DOUT1_DOUT_OFFSET 0 + +#define PINCTRL_DOUT2_DOUT_MASK 0xfffffff +#define PINCTRL_DOUT2_DOUT_OFFSET 0 + +#define PINCTRL_DOUT3_DOUT_MASK 0x7fffffff +#define PINCTRL_DOUT3_DOUT_OFFSET 0 + +#define PINCTRL_DOUT4_DOUT_MASK 0x1fffff +#define PINCTRL_DOUT4_DOUT_OFFSET 0 + +#define PINCTRL_DIN0_DIN_MASK 0x1fffffff +#define PINCTRL_DIN0_DIN_OFFSET 0 + +#define PINCTRL_DIN1_DIN_MASK 0xffffffff +#define PINCTRL_DIN1_DIN_OFFSET 0 + +#define PINCTRL_DIN2_DIN_MASK 0xfffffff +#define PINCTRL_DIN2_DIN_OFFSET 0 + +#define PINCTRL_DIN3_DIN_MASK 0x7fffffff +#define PINCTRL_DIN3_DIN_OFFSET 0 + +#define PINCTRL_DIN4_DIN_MASK 0x1fffff +#define PINCTRL_DIN4_DIN_OFFSET 0 + +#define PINCTRL_DOE0_DOE_MASK 0x1fffffff +#define PINCTRL_DOE0_DOE_OFFSET 0 + +#define PINCTRL_DOE1_DOE_MASK 0xffffffff +#define PINCTRL_DOE1_DOE_OFFSET 0 + +#define PINCTRL_DOE2_DOE_MASK 0xfffffff +#define PINCTRL_DOE2_DOE_OFFSET 0 + +#define PINCTRL_DOE3_DOE_MASK 0x7fffffff +#define PINCTRL_DOE3_DOE_OFFSET 0 + +#define PINCTRL_DOE4_DOE_MASK 0x1fffff +#define PINCTRL_DOE4_DOE_OFFSET 0 + +#define PINCTRL_PIN2IRQ0_PIN2IRQ_MASK 0x1fffffff +#define PINCTRL_PIN2IRQ0_PIN2IRQ_OFFSET 0 + +#define PINCTRL_PIN2IRQ1_PIN2IRQ_MASK 0xffffffff +#define PINCTRL_PIN2IRQ1_PIN2IRQ_OFFSET 0 + +#define PINCTRL_PIN2IRQ2_PIN2IRQ_MASK 0xfffffff +#define PINCTRL_PIN2IRQ2_PIN2IRQ_OFFSET 0 + +#define PINCTRL_PIN2IRQ3_PIN2IRQ_MASK 0x7fffffff +#define PINCTRL_PIN2IRQ3_PIN2IRQ_OFFSET 0 + +#define PINCTRL_PIN2IRQ4_PIN2IRQ_MASK 0x1fffff +#define PINCTRL_PIN2IRQ4_PIN2IRQ_OFFSET 0 + +#define PINCTRL_IRQEN0_IRQEN_MASK 0x1fffffff +#define PINCTRL_IRQEN0_IRQEN_OFFSET 0 + +#define PINCTRL_IRQEN1_IRQEN_MASK 0xffffffff +#define PINCTRL_IRQEN1_IRQEN_OFFSET 0 + +#define PINCTRL_IRQEN2_IRQEN_MASK 0xfffffff +#define PINCTRL_IRQEN2_IRQEN_OFFSET 0 + +#define PINCTRL_IRQEN3_IRQEN_MASK 0x7fffffff +#define PINCTRL_IRQEN3_IRQEN_OFFSET 0 + +#define PINCTRL_IRQEN4_IRQEN_MASK 0x1fffff +#define PINCTRL_IRQEN4_IRQEN_OFFSET 0 + +#define PINCTRL_IRQLEVEL0_IRQLEVEL_MASK 0x1fffffff +#define PINCTRL_IRQLEVEL0_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQLEVEL1_IRQLEVEL_MASK 0xffffffff +#define PINCTRL_IRQLEVEL1_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQLEVEL2_IRQLEVEL_MASK 0xfffffff +#define PINCTRL_IRQLEVEL2_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQLEVEL3_IRQLEVEL_MASK 0x7fffffff +#define PINCTRL_IRQLEVEL3_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQLEVEL4_IRQLEVEL_MASK 0x1fffff +#define PINCTRL_IRQLEVEL4_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQPOL0_IRQPOL_MASK 0x1fffffff +#define PINCTRL_IRQPOL0_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQPOL1_IRQPOL_MASK 0xffffffff +#define PINCTRL_IRQPOL1_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQPOL2_IRQPOL_MASK 0xfffffff +#define PINCTRL_IRQPOL2_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQPOL3_IRQPOL_MASK 0x7fffffff +#define PINCTRL_IRQPOL3_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQPOL4_IRQPOL_MASK 0x1fffff +#define PINCTRL_IRQPOL4_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQSTAT0_IRQSTAT_MASK 0x1fffffff +#define PINCTRL_IRQSTAT0_IRQSTAT_OFFSET 0 + +#define PINCTRL_IRQSTAT1_IRQSTAT_MASK 0xffffffff +#define PINCTRL_IRQSTAT1_IRQSTAT_OFFSET 0 + +#define PINCTRL_IRQSTAT2_IRQSTAT_MASK 0xfffffff +#define PINCTRL_IRQSTAT2_IRQSTAT_OFFSET 0 + +#define PINCTRL_IRQSTAT3_IRQSTAT_MASK 0x7fffffff +#define PINCTRL_IRQSTAT3_IRQSTAT_OFFSET 0 + +#define PINCTRL_IRQSTAT4_IRQSTAT_MASK 0x1fffff +#define PINCTRL_IRQSTAT4_IRQSTAT_OFFSET 0 + +#define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_MASK (0x3 << 26) +#define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_OFFSET 26 +#define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_MASK (0x3 << 24) +#define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_OFFSET 24 +#define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_MASK (0x3 << 22) +#define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_OFFSET 22 +#define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_MASK (0x3 << 20) +#define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_OFFSET 20 +#define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_MASK (0x3 << 18) +#define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_OFFSET 18 +#define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_MASK (0x3 << 16) +#define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_OFFSET 16 +#define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_MASK (0x3 << 14) +#define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_OFFSET 14 +#define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_MASK (0x3 << 12) +#define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_OFFSET 12 +#define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_MASK (0x3 << 10) +#define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_OFFSET 10 +#define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_MASK (0x3 << 8) +#define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_OFFSET 8 +#define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_MASK (0x3 << 6) +#define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_OFFSET 6 +#define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_MASK (0x3 << 4) +#define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_OFFSET 4 +#define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_MASK (0x3 << 2) +#define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_OFFSET 2 +#define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_MASK (0x3 << 0) +#define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_OFFSET 0 + +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_MASK (0x3 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_OFFSET 16 +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_mDDR (0x0 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_GPIO (0x1 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_LVDDR2 (0x2 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2 (0x3 << 16) +#define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK (0x3 << 12) +#define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_OFFSET 12 +#define PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK (0x3 << 10) +#define PINCTRL_EMI_DS_CTRL_CONTROL_MA_OFFSET 10 +#define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK (0x3 << 8) +#define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_OFFSET 8 +#define PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK (0x3 << 6) +#define PINCTRL_EMI_DS_CTRL_SLICE3_MA_OFFSET 6 +#define PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK (0x3 << 4) +#define PINCTRL_EMI_DS_CTRL_SLICE2_MA_OFFSET 4 +#define PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK (0x3 << 2) +#define PINCTRL_EMI_DS_CTRL_SLICE1_MA_OFFSET 2 +#define PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK (0x3 << 0) +#define PINCTRL_EMI_DS_CTRL_SLICE0_MA_OFFSET 0 + +#endif /* __MX28_REGS_PINCTRL_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx23.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx23.h new file mode 100644 index 000000000..a0dc78102 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx23.h @@ -0,0 +1,344 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX23 Power Controller Register Definitions + * + * Copyright (C) 2012 Marek Vasut + */ + +#ifndef __MX23_REGS_POWER_H__ +#define __MX23_REGS_POWER_H__ + +#include + +#ifndef __ASSEMBLY__ +struct mxs_power_regs { + mxs_reg_32(hw_power_ctrl) + mxs_reg_32(hw_power_5vctrl) + mxs_reg_32(hw_power_minpwr) + mxs_reg_32(hw_power_charge) + uint32_t hw_power_vdddctrl; + uint32_t reserved_vddd[3]; + uint32_t hw_power_vddactrl; + uint32_t reserved_vdda[3]; + uint32_t hw_power_vddioctrl; + uint32_t reserved_vddio[3]; + uint32_t hw_power_vddmemctrl; + uint32_t reserved_vddmem[3]; + uint32_t hw_power_dcdc4p2; + uint32_t reserved_dcdc4p2[3]; + uint32_t hw_power_misc; + uint32_t reserved_misc[3]; + uint32_t hw_power_dclimits; + uint32_t reserved_dclimits[3]; + mxs_reg_32(hw_power_loopctrl) + uint32_t hw_power_sts; + uint32_t reserved_sts[3]; + mxs_reg_32(hw_power_speed) + uint32_t hw_power_battmonitor; + uint32_t reserved_battmonitor[3]; + + uint32_t reserved1[4]; + + mxs_reg_32(hw_power_reset) + + uint32_t reserved2[4]; + + mxs_reg_32(hw_power_special) + mxs_reg_32(hw_power_version) +}; +#endif + +#define POWER_CTRL_CLKGATE (1 << 30) +#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27) +#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24) +#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23) +#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22) +#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21) +#define POWER_CTRL_PSWITCH_IRQ (1 << 20) +#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19) +#define POWER_CTRL_POLARITY_PSWITCH (1 << 18) +#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17) +#define POWER_CTRL_POLARITY_DC_OK (1 << 16) +#define POWER_CTRL_DC_OK_IRQ (1 << 15) +#define POWER_CTRL_ENIRQ_DC_OK (1 << 14) +#define POWER_CTRL_BATT_BO_IRQ (1 << 13) +#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12) +#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11) +#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10) +#define POWER_CTRL_VDDA_BO_IRQ (1 << 9) +#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8) +#define POWER_CTRL_VDDD_BO_IRQ (1 << 7) +#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6) +#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5) +#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4) +#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3) +#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2) +#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1) +#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0) + +#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 28) +#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 28 +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 28) +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 28) +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 28) +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 28) +#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24) +#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24 +#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x1 << 20) +#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20 +#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12) +#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12 +#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8 +#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8) +#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7) +#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6) +#define POWER_5VCTRL_DCDC_XFER (1 << 5) +#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4) +#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3) +#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2) +#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1) +#define POWER_5VCTRL_ENABLE_DCDC (1 << 0) + +#define POWER_MINPWR_LOWPWR_4P2 (1 << 14) +#define POWER_MINPWR_VDAC_DUMP_CTRL (1 << 13) +#define POWER_MINPWR_PWD_BO (1 << 12) +#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11) +#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) +#define POWER_MINPWR_ENABLE_OSC (1 << 9) +#define POWER_MINPWR_SELECT_OSC (1 << 8) +#define POWER_MINPWR_VBG_OFF (1 << 7) +#define POWER_MINPWR_DOUBLE_FETS (1 << 6) +#define POWER_MINPWR_HALFFETS (1 << 5) +#define POWER_MINPWR_LESSANA_I (1 << 4) +#define POWER_MINPWR_PWD_XTAL24 (1 << 3) +#define POWER_MINPWR_DC_STOPCLK (1 << 2) +#define POWER_MINPWR_EN_DC_PFM (1 << 1) +#define POWER_MINPWR_DC_HALFCLK (1 << 0) + +#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24) +#define POWER_CHARGE_ADJ_VOLT_OFFSET 24 +#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24) +#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24) +#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24) +#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24) +#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24) +#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24) +#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24) +#define POWER_CHARGE_ENABLE_LOAD (1 << 22) +#define POWER_CHARGE_ENABLE_CHARGER_RESISTORS (1 << 21) +#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20) +#define POWER_CHARGE_CHRG_STS_OFF (1 << 19) +#define POWER_CHARGE_USE_EXTERN_R (1 << 17) +#define POWER_CHARGE_PWD_BATTCHRG (1 << 16) +#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8) +#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8 +#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8) +#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8) +#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8) +#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8) +#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f +#define POWER_CHARGE_BATTCHRG_I_OFFSET 0 +#define POWER_CHARGE_BATTCHRG_I_10MA 0x01 +#define POWER_CHARGE_BATTCHRG_I_20MA 0x02 +#define POWER_CHARGE_BATTCHRG_I_50MA 0x04 +#define POWER_CHARGE_BATTCHRG_I_100MA 0x08 +#define POWER_CHARGE_BATTCHRG_I_200MA 0x10 +#define POWER_CHARGE_BATTCHRG_I_400MA 0x20 + +#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28) +#define POWER_VDDDCTRL_ADJTN_OFFSET 28 +#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23) +#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22) +#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21) +#define POWER_VDDDCTRL_DISABLE_FET (1 << 20) +#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16 +#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16) +#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8) +#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8 +#define POWER_VDDDCTRL_TRG_MASK 0x1f +#define POWER_VDDDCTRL_TRG_OFFSET 0 + +#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19) +#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18) +#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17) +#define POWER_VDDACTRL_DISABLE_FET (1 << 16) +#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12 +#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) +#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8) +#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8 +#define POWER_VDDACTRL_TRG_MASK 0x1f +#define POWER_VDDACTRL_TRG_OFFSET 0 + +#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20) +#define POWER_VDDIOCTRL_ADJTN_OFFSET 20 +#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18) +#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17) +#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16) +#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12 +#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) +#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8) +#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8 +#define POWER_VDDIOCTRL_TRG_MASK 0x1f +#define POWER_VDDIOCTRL_TRG_OFFSET 0 + +#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10) +#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9) +#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8) +#define POWER_VDDMEMCTRL_TRG_MASK 0x1f +#define POWER_VDDMEMCTRL_TRG_OFFSET 0 + +#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28) +#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28 +#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28) +#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28) +#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28) +#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24) +#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24 +#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23) +#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22) +#define POWER_DCDC4P2_HYST_DIR (1 << 21) +#define POWER_DCDC4P2_HYST_THRESH (1 << 20) +#define POWER_DCDC4P2_TRG_MASK (0x7 << 16) +#define POWER_DCDC4P2_TRG_OFFSET 16 +#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16) +#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16) +#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16) +#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16) +#define POWER_DCDC4P2_TRG_BATT (0x4 << 16) +#define POWER_DCDC4P2_BO_MASK (0x1f << 8) +#define POWER_DCDC4P2_BO_OFFSET 8 +#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f +#define POWER_DCDC4P2_CMPTRIP_OFFSET 0 + +#define POWER_MISC_FREQSEL_MASK (0x7 << 4) +#define POWER_MISC_FREQSEL_OFFSET 4 +#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4) +#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4) +#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4) +#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4) +#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4) +#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4) +#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4) +#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3) +#define POWER_MISC_DELAY_TIMING (1 << 2) +#define POWER_MISC_TEST (1 << 1) +#define POWER_MISC_SEL_PLLCLK (1 << 0) + +#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) +#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 +#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f +#define POWER_DCLIMITS_NEGLIMIT_OFFSET 0 + +#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) +#define POWER_LOOPCTRL_HYST_SIGN (1 << 19) +#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18) +#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17) +#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16) +#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15) +#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14) +#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12 +#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12) +#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8) +#define POWER_LOOPCTRL_DC_FF_OFFSET 8 +#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4) +#define POWER_LOOPCTRL_DC_R_OFFSET 4 +#define POWER_LOOPCTRL_DC_C_MASK 0x3 +#define POWER_LOOPCTRL_DC_C_OFFSET 0 +#define POWER_LOOPCTRL_DC_C_MAX 0x0 +#define POWER_LOOPCTRL_DC_C_2X 0x1 +#define POWER_LOOPCTRL_DC_C_4X 0x2 +#define POWER_LOOPCTRL_DC_C_MIN 0x3 + +#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24) +#define POWER_STS_PWRUP_SOURCE_OFFSET 24 +#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24) +#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24) +#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24) +#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24) +#define POWER_STS_PSWITCH_MASK (0x3 << 20) +#define POWER_STS_PSWITCH_OFFSET 20 +#define POWER_STS_AVALID0_STATUS (1 << 17) +#define POWER_STS_BVALID0_STATUS (1 << 16) +#define POWER_STS_VBUSVALID0_STATUS (1 << 15) +#define POWER_STS_SESSEND0_STATUS (1 << 14) +#define POWER_STS_BATT_BO (1 << 13) +#define POWER_STS_VDD5V_FAULT (1 << 12) +#define POWER_STS_CHRGSTS (1 << 11) +#define POWER_STS_DCDC_4P2_BO (1 << 10) +#define POWER_STS_DC_OK (1 << 9) +#define POWER_STS_VDDIO_BO (1 << 8) +#define POWER_STS_VDDA_BO (1 << 7) +#define POWER_STS_VDDD_BO (1 << 6) +#define POWER_STS_VDD5V_GT_VDDIO (1 << 5) +#define POWER_STS_VDD5V_DROOP (1 << 4) +#define POWER_STS_AVALID0 (1 << 3) +#define POWER_STS_BVALID0 (1 << 2) +#define POWER_STS_VBUSVALID0 (1 << 1) +#define POWER_STS_SESSEND0 (1 << 0) + +#define POWER_SPEED_STATUS_MASK (0xff << 16) +#define POWER_SPEED_STATUS_OFFSET 16 +#define POWER_SPEED_CTRL_MASK 0x3 +#define POWER_SPEED_CTRL_OFFSET 0 +#define POWER_SPEED_CTRL_SS_OFF 0x0 +#define POWER_SPEED_CTRL_SS_ON 0x1 +#define POWER_SPEED_CTRL_SS_ENABLE 0x3 + +#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16) +#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16 +#define POWER_BATTMONITOR_EN_BATADJ (1 << 10) +#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9) +#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8) +#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f +#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0 + +#define POWER_RESET_UNLOCK_MASK (0xffff << 16) +#define POWER_RESET_UNLOCK_OFFSET 16 +#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16) +#define POWER_RESET_PWD_OFF (1 << 1) +#define POWER_RESET_PWD (1 << 0) + +#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3) +#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2) +#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1) +#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0) + +#define POWER_SPECIAL_TEST_MASK 0xffffffff +#define POWER_SPECIAL_TEST_OFFSET 0 + +#define POWER_VERSION_MAJOR_MASK (0xff << 24) +#define POWER_VERSION_MAJOR_OFFSET 24 +#define POWER_VERSION_MINOR_MASK (0xff << 16) +#define POWER_VERSION_MINOR_OFFSET 16 +#define POWER_VERSION_STEP_MASK 0xffff +#define POWER_VERSION_STEP_OFFSET 0 + +#endif /* __MX23_REGS_POWER_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx28.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx28.h new file mode 100644 index 000000000..39250c506 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx28.h @@ -0,0 +1,399 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX28 Power Controller Register Definitions + * + * Copyright (C) 2011 Marek Vasut + */ + +#ifndef __MX28_REGS_POWER_H__ +#define __MX28_REGS_POWER_H__ + +#include + +#ifndef __ASSEMBLY__ +struct mxs_power_regs { + mxs_reg_32(hw_power_ctrl) + mxs_reg_32(hw_power_5vctrl) + mxs_reg_32(hw_power_minpwr) + mxs_reg_32(hw_power_charge) + uint32_t hw_power_vdddctrl; + uint32_t reserved_vddd[3]; + uint32_t hw_power_vddactrl; + uint32_t reserved_vdda[3]; + uint32_t hw_power_vddioctrl; + uint32_t reserved_vddio[3]; + uint32_t hw_power_vddmemctrl; + uint32_t reserved_vddmem[3]; + uint32_t hw_power_dcdc4p2; + uint32_t reserved_dcdc4p2[3]; + uint32_t hw_power_misc; + uint32_t reserved_misc[3]; + uint32_t hw_power_dclimits; + uint32_t reserved_dclimits[3]; + mxs_reg_32(hw_power_loopctrl) + uint32_t hw_power_sts; + uint32_t reserved_sts[3]; + mxs_reg_32(hw_power_speed) + uint32_t hw_power_battmonitor; + uint32_t reserved_battmonitor[3]; + + uint32_t reserved[4]; + + mxs_reg_32(hw_power_reset) + mxs_reg_32(hw_power_debug) + mxs_reg_32(hw_power_thermal) + mxs_reg_32(hw_power_usb1ctrl) + mxs_reg_32(hw_power_special) + mxs_reg_32(hw_power_version) + mxs_reg_32(hw_power_anaclkctrl) + mxs_reg_32(hw_power_refctrl) +}; +#endif + +#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27) +#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24) +#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23) +#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22) +#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21) +#define POWER_CTRL_PSWITCH_IRQ (1 << 20) +#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19) +#define POWER_CTRL_POLARITY_PSWITCH (1 << 18) +#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17) +#define POWER_CTRL_POLARITY_DC_OK (1 << 16) +#define POWER_CTRL_DC_OK_IRQ (1 << 15) +#define POWER_CTRL_ENIRQ_DC_OK (1 << 14) +#define POWER_CTRL_BATT_BO_IRQ (1 << 13) +#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12) +#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11) +#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10) +#define POWER_CTRL_VDDA_BO_IRQ (1 << 9) +#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8) +#define POWER_CTRL_VDDD_BO_IRQ (1 << 7) +#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6) +#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5) +#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4) +#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3) +#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2) +#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1) +#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0) + +#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 30) +#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 30 +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 30) +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 30) +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 30) +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 30) +#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24) +#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24 +#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x3 << 20) +#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20 +#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12) +#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12 +#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8 +#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8) +#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7) +#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6) +#define POWER_5VCTRL_DCDC_XFER (1 << 5) +#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4) +#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3) +#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2) +#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1) +#define POWER_5VCTRL_ENABLE_DCDC (1 << 0) + +#define POWER_MINPWR_LOWPWR_4P2 (1 << 14) +#define POWER_MINPWR_PWD_BO (1 << 12) +#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11) +#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) +#define POWER_MINPWR_ENABLE_OSC (1 << 9) +#define POWER_MINPWR_SELECT_OSC (1 << 8) +#define POWER_MINPWR_VBG_OFF (1 << 7) +#define POWER_MINPWR_DOUBLE_FETS (1 << 6) +#define POWER_MINPWR_HALFFETS (1 << 5) +#define POWER_MINPWR_LESSANA_I (1 << 4) +#define POWER_MINPWR_PWD_XTAL24 (1 << 3) +#define POWER_MINPWR_DC_STOPCLK (1 << 2) +#define POWER_MINPWR_EN_DC_PFM (1 << 1) +#define POWER_MINPWR_DC_HALFCLK (1 << 0) + +#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24) +#define POWER_CHARGE_ADJ_VOLT_OFFSET 24 +#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24) +#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24) +#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24) +#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24) +#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24) +#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24) +#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24) +#define POWER_CHARGE_ENABLE_LOAD (1 << 22) +#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20) +#define POWER_CHARGE_CHRG_STS_OFF (1 << 19) +#define POWER_CHARGE_LIION_4P1 (1 << 18) +#define POWER_CHARGE_PWD_BATTCHRG (1 << 16) +#define POWER_CHARGE_ENABLE_CHARGER_USB1 (1 << 13) +#define POWER_CHARGE_ENABLE_CHARGER_USB0 (1 << 12) +#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8) +#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8 +#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8) +#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8) +#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8) +#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8) +#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f +#define POWER_CHARGE_BATTCHRG_I_OFFSET 0 +#define POWER_CHARGE_BATTCHRG_I_10MA 0x01 +#define POWER_CHARGE_BATTCHRG_I_20MA 0x02 +#define POWER_CHARGE_BATTCHRG_I_50MA 0x04 +#define POWER_CHARGE_BATTCHRG_I_100MA 0x08 +#define POWER_CHARGE_BATTCHRG_I_200MA 0x10 +#define POWER_CHARGE_BATTCHRG_I_400MA 0x20 + +#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28) +#define POWER_VDDDCTRL_ADJTN_OFFSET 28 +#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23) +#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22) +#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21) +#define POWER_VDDDCTRL_DISABLE_FET (1 << 20) +#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16 +#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16) +#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8) +#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8 +#define POWER_VDDDCTRL_TRG_MASK 0x1f +#define POWER_VDDDCTRL_TRG_OFFSET 0 + +#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19) +#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18) +#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17) +#define POWER_VDDACTRL_DISABLE_FET (1 << 16) +#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12 +#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) +#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8) +#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8 +#define POWER_VDDACTRL_TRG_MASK 0x1f +#define POWER_VDDACTRL_TRG_OFFSET 0 + +#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20) +#define POWER_VDDIOCTRL_ADJTN_OFFSET 20 +#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18) +#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17) +#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16) +#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12 +#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) +#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8) +#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8 +#define POWER_VDDIOCTRL_TRG_MASK 0x1f +#define POWER_VDDIOCTRL_TRG_OFFSET 0 + +#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10) +#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9) +#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8) +#define POWER_VDDMEMCTRL_BO_OFFSET_MASK (0x7 << 5) +#define POWER_VDDMEMCTRL_BO_OFFSET_OFFSET 5 +#define POWER_VDDMEMCTRL_TRG_MASK 0x1f +#define POWER_VDDMEMCTRL_TRG_OFFSET 0 + +#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28) +#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28 +#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28) +#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28) +#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28) +#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24) +#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24 +#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23) +#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22) +#define POWER_DCDC4P2_HYST_DIR (1 << 21) +#define POWER_DCDC4P2_HYST_THRESH (1 << 20) +#define POWER_DCDC4P2_TRG_MASK (0x7 << 16) +#define POWER_DCDC4P2_TRG_OFFSET 16 +#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16) +#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16) +#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16) +#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16) +#define POWER_DCDC4P2_TRG_BATT (0x4 << 16) +#define POWER_DCDC4P2_BO_MASK (0x1f << 8) +#define POWER_DCDC4P2_BO_OFFSET 8 +#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f +#define POWER_DCDC4P2_CMPTRIP_OFFSET 0 + +#define POWER_MISC_FREQSEL_MASK (0x7 << 4) +#define POWER_MISC_FREQSEL_OFFSET 4 +#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4) +#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4) +#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4) +#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4) +#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4) +#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4) +#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4) +#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3) +#define POWER_MISC_DELAY_TIMING (1 << 2) +#define POWER_MISC_TEST (1 << 1) +#define POWER_MISC_SEL_PLLCLK (1 << 0) + +#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) +#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 +#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f +#define POWER_DCLIMITS_NEGLIMIT_OFFSET 0 + +#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) +#define POWER_LOOPCTRL_HYST_SIGN (1 << 19) +#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18) +#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17) +#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16) +#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15) +#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14) +#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12 +#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12) +#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8) +#define POWER_LOOPCTRL_DC_FF_OFFSET 8 +#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4) +#define POWER_LOOPCTRL_DC_R_OFFSET 4 +#define POWER_LOOPCTRL_DC_C_MASK 0x3 +#define POWER_LOOPCTRL_DC_C_OFFSET 0 +#define POWER_LOOPCTRL_DC_C_MAX 0x0 +#define POWER_LOOPCTRL_DC_C_2X 0x1 +#define POWER_LOOPCTRL_DC_C_4X 0x2 +#define POWER_LOOPCTRL_DC_C_MIN 0x3 + +#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24) +#define POWER_STS_PWRUP_SOURCE_OFFSET 24 +#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24) +#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24) +#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24) +#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24) +#define POWER_STS_PSWITCH_MASK (0x3 << 20) +#define POWER_STS_PSWITCH_OFFSET 20 +#define POWER_STS_THERMAL_WARNING (1 << 19) +#define POWER_STS_VDDMEM_BO (1 << 18) +#define POWER_STS_AVALID0_STATUS (1 << 17) +#define POWER_STS_BVALID0_STATUS (1 << 16) +#define POWER_STS_VBUSVALID0_STATUS (1 << 15) +#define POWER_STS_SESSEND0_STATUS (1 << 14) +#define POWER_STS_BATT_BO (1 << 13) +#define POWER_STS_VDD5V_FAULT (1 << 12) +#define POWER_STS_CHRGSTS (1 << 11) +#define POWER_STS_DCDC_4P2_BO (1 << 10) +#define POWER_STS_DC_OK (1 << 9) +#define POWER_STS_VDDIO_BO (1 << 8) +#define POWER_STS_VDDA_BO (1 << 7) +#define POWER_STS_VDDD_BO (1 << 6) +#define POWER_STS_VDD5V_GT_VDDIO (1 << 5) +#define POWER_STS_VDD5V_DROOP (1 << 4) +#define POWER_STS_AVALID0 (1 << 3) +#define POWER_STS_BVALID0 (1 << 2) +#define POWER_STS_VBUSVALID0 (1 << 1) +#define POWER_STS_SESSEND0 (1 << 0) + +#define POWER_SPEED_STATUS_MASK (0xffff << 8) +#define POWER_SPEED_STATUS_OFFSET 8 +#define POWER_SPEED_STATUS_SEL_MASK (0x3 << 6) +#define POWER_SPEED_STATUS_SEL_OFFSET 6 +#define POWER_SPEED_STATUS_SEL_DCDC_STAT (0x0 << 6) +#define POWER_SPEED_STATUS_SEL_CORE_STAT (0x1 << 6) +#define POWER_SPEED_STATUS_SEL_ARM_STAT (0x2 << 6) +#define POWER_SPEED_CTRL_MASK 0x3 +#define POWER_SPEED_CTRL_OFFSET 0 +#define POWER_SPEED_CTRL_SS_OFF 0x0 +#define POWER_SPEED_CTRL_SS_ON 0x1 +#define POWER_SPEED_CTRL_SS_ENABLE 0x3 + +#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16) +#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16 +#define POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN (1 << 11) +#define POWER_BATTMONITOR_EN_BATADJ (1 << 10) +#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9) +#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8) +#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f +#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0 + +#define POWER_RESET_UNLOCK_MASK (0xffff << 16) +#define POWER_RESET_UNLOCK_OFFSET 16 +#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16) +#define POWER_RESET_FASTFALL_PSWITCH_OFF (1 << 2) +#define POWER_RESET_PWD_OFF (1 << 1) +#define POWER_RESET_PWD (1 << 0) + +#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3) +#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2) +#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1) +#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0) + +#define POWER_THERMAL_TEST (1 << 8) +#define POWER_THERMAL_PWD (1 << 7) +#define POWER_THERMAL_LOW_POWER (1 << 6) +#define POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4) +#define POWER_THERMAL_OFFSET_ADJ_OFFSET 4 +#define POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3) +#define POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7 +#define POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0 + +#define POWER_USB1CTRL_AVALID1 (1 << 3) +#define POWER_USB1CTRL_BVALID1 (1 << 2) +#define POWER_USB1CTRL_VBUSVALID1 (1 << 1) +#define POWER_USB1CTRL_SESSEND1 (1 << 0) + +#define POWER_SPECIAL_TEST_MASK 0xffffffff +#define POWER_SPECIAL_TEST_OFFSET 0 + +#define POWER_VERSION_MAJOR_MASK (0xff << 24) +#define POWER_VERSION_MAJOR_OFFSET 24 +#define POWER_VERSION_MINOR_MASK (0xff << 16) +#define POWER_VERSION_MINOR_OFFSET 16 +#define POWER_VERSION_STEP_MASK 0xffff +#define POWER_VERSION_STEP_OFFSET 0 + +#define POWER_ANACLKCTRL_CLKGATE_0 (1 << 31) +#define POWER_ANACLKCTRL_OUTDIV_MASK (0x7 << 28) +#define POWER_ANACLKCTRL_OUTDIV_OFFSET 28 +#define POWER_ANACLKCTRL_INVERT_OUTCLK (1 << 27) +#define POWER_ANACLKCTRL_CLKGATE_I (1 << 26) +#define POWER_ANACLKCTRL_DITHER_OFF (1 << 10) +#define POWER_ANACLKCTRL_SLOW_DITHER (1 << 9) +#define POWER_ANACLKCTRL_INVERT_INCLK (1 << 8) +#define POWER_ANACLKCTRL_INCLK_SHIFT_MASK (0x3 << 4) +#define POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET 4 +#define POWER_ANACLKCTRL_INDIV_MASK 0x7 +#define POWER_ANACLKCTRL_INDIV_OFFSET 0 + +#define POWER_REFCTRL_FASTSETTLING (1 << 26) +#define POWER_REFCTRL_RAISE_REF (1 << 25) +#define POWER_REFCTRL_XTAL_BGR_BIAS (1 << 24) +#define POWER_REFCTRL_VBG_ADJ_MASK (0x7 << 20) +#define POWER_REFCTRL_VBG_ADJ_OFFSET 20 +#define POWER_REFCTRL_LOW_PWR (1 << 19) +#define POWER_REFCTRL_BIAS_CTRL_MASK (0x3 << 16) +#define POWER_REFCTRL_BIAS_CTRL_OFFSET 16 +#define POWER_REFCTRL_VDDXTAL_TO_VDDD (1 << 14) +#define POWER_REFCTRL_ADJ_ANA (1 << 13) +#define POWER_REFCTRL_ADJ_VAG (1 << 12) +#define POWER_REFCTRL_ANA_REFVAL_MASK (0xf << 8) +#define POWER_REFCTRL_ANA_REFVAL_OFFSET 8 +#define POWER_REFCTRL_VAG_VAL_MASK (0xf << 4) +#define POWER_REFCTRL_VAG_VAL_OFFSET 4 + +#endif /* __MX28_REGS_POWER_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-rtc.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-rtc.h new file mode 100644 index 000000000..8d6ba573d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-rtc.h @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX28 RTC Register Definitions + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ + +#ifndef __MX28_REGS_RTC_H__ +#define __MX28_REGS_RTC_H__ + +#include + +#ifndef __ASSEMBLY__ +struct mxs_rtc_regs { + mxs_reg_32(hw_rtc_ctrl) + mxs_reg_32(hw_rtc_stat) + mxs_reg_32(hw_rtc_milliseconds) + mxs_reg_32(hw_rtc_seconds) + mxs_reg_32(hw_rtc_rtc_alarm) + mxs_reg_32(hw_rtc_watchdog) + mxs_reg_32(hw_rtc_persistent0) + mxs_reg_32(hw_rtc_persistent1) + mxs_reg_32(hw_rtc_persistent2) + mxs_reg_32(hw_rtc_persistent3) + mxs_reg_32(hw_rtc_persistent4) + mxs_reg_32(hw_rtc_persistent5) + mxs_reg_32(hw_rtc_debug) + mxs_reg_32(hw_rtc_version) +}; +#endif + +#define RTC_CTRL_SFTRST (1 << 31) +#define RTC_CTRL_CLKGATE (1 << 30) +#define RTC_CTRL_SUPPRESS_COPY2ANALOG (1 << 6) +#define RTC_CTRL_FORCE_UPDATE (1 << 5) +#define RTC_CTRL_WATCHDOGEN (1 << 4) +#define RTC_CTRL_ONEMSEC_IRQ (1 << 3) +#define RTC_CTRL_ALARM_IRQ (1 << 2) +#define RTC_CTRL_ONEMSEC_IRQ_EN (1 << 1) +#define RTC_CTRL_ALARM_IRQ_EN (1 << 0) + +#define RTC_STAT_RTC_PRESENT (1 << 31) +#define RTC_STAT_ALARM_PRESENT (1 << 30) +#define RTC_STAT_WATCHDOG_PRESENT (1 << 29) +#define RTC_STAT_XTAL32000_PRESENT (1 << 28) +#define RTC_STAT_XTAL32768_PRESENT (1 << 27) +#define RTC_STAT_STALE_REGS_MASK (0xff << 16) +#define RTC_STAT_STALE_REGS_OFFSET 16 +#define RTC_STAT_NEW_REGS_MASK (0xff << 8) +#define RTC_STAT_NEW_REGS_OFFSET 8 + +#define RTC_MILLISECONDS_COUNT_MASK 0xffffffff +#define RTC_MILLISECONDS_COUNT_OFFSET 0 + +#define RTC_SECONDS_COUNT_MASK 0xffffffff +#define RTC_SECONDS_COUNT_OFFSET 0 + +#define RTC_ALARM_VALUE_MASK 0xffffffff +#define RTC_ALARM_VALUE_OFFSET 0 + +#define RTC_WATCHDOG_COUNT_MASK 0xffffffff +#define RTC_WATCHDOG_COUNT_OFFSET 0 + +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_MASK (0xf << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_OFFSET 28 +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V83 (0x0 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V78 (0x1 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V73 (0x2 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V68 (0x3 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V62 (0x4 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57 (0x5 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52 (0x6 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48 (0x7 << 28) +#define RTC_PERSISTENT0_EXTERNAL_RESET (1 << 21) +#define RTC_PERSISTENT0_THERMAL_RESET (1 << 20) +#define RTC_PERSISTENT0_ENABLE_LRADC_PWRUP (1 << 18) +#define RTC_PERSISTENT0_AUTO_RESTART (1 << 17) +#define RTC_PERSISTENT0_DISABLE_PSWITCH (1 << 16) +#define RTC_PERSISTENT0_LOWERBIAS_MASK (0xf << 14) +#define RTC_PERSISTENT0_LOWERBIAS_OFFSET 14 +#define RTC_PERSISTENT0_LOWERBIAS_NOMINAL (0x0 << 14) +#define RTC_PERSISTENT0_LOWERBIAS_M25P (0x1 << 14) +#define RTC_PERSISTENT0_LOWERBIAS_M50P (0x3 << 14) +#define RTC_PERSISTENT0_DISABLE_XTALOK (1 << 13) +#define RTC_PERSISTENT0_MSEC_RES_MASK (0x1f << 8) +#define RTC_PERSISTENT0_MSEC_RES_OFFSET 8 +#define RTC_PERSISTENT0_MSEC_RES_1MS (0x01 << 8) +#define RTC_PERSISTENT0_MSEC_RES_2MS (0x02 << 8) +#define RTC_PERSISTENT0_MSEC_RES_4MS (0x04 << 8) +#define RTC_PERSISTENT0_MSEC_RES_8MS (0x08 << 8) +#define RTC_PERSISTENT0_MSEC_RES_16MS (0x10 << 8) +#define RTC_PERSISTENT0_ALARM_WAKE (1 << 7) +#define RTC_PERSISTENT0_XTAL32_FREQ (1 << 6) +#define RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5) +#define RTC_PERSISTENT0_XTAL24KHZ_PWRUP (1 << 4) +#define RTC_PERSISTENT0_LCK_SECS (1 << 3) +#define RTC_PERSISTENT0_ALARM_EN (1 << 2) +#define RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1) +#define RTC_PERSISTENT0_CLOCKSOURCE (1 << 0) + +#define RTC_PERSISTENT1_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT1_GENERAL_OFFSET 0 +#define RTC_PERSISTENT1_GENERAL_OTG_ALT_ROLE 0x0080 +#define RTC_PERSISTENT1_GENERAL_OTG_HNP 0x0100 +#define RTC_PERSISTENT1_GENERAL_USB_LPM 0x0200 +#define RTC_PERSISTENT1_GENERAL_SKIP_CHECKDISK 0x0400 +#define RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER 0x0800 +#define RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X 0x1000 + +#define RTC_PERSISTENT2_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT2_GENERAL_OFFSET 0 + +#define RTC_PERSISTENT3_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT3_GENERAL_OFFSET 0 + +#define RTC_PERSISTENT4_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT4_GENERAL_OFFSET 0 + +#define RTC_PERSISTENT5_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT5_GENERAL_OFFSET 0 + +#define RTC_DEBUG_WATCHDOG_RESET_MASK (1 << 1) +#define RTC_DEBUG_WATCHDOG_RESET (1 << 0) + +#define RTC_VERSION_MAJOR_MASK (0xff << 24) +#define RTC_VERSION_MAJOR_OFFSET 24 +#define RTC_VERSION_MINOR_MASK (0xff << 16) +#define RTC_VERSION_MINOR_OFFSET 16 +#define RTC_VERSION_STEP_MASK 0xffff +#define RTC_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_RTC_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ssp.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ssp.h new file mode 100644 index 000000000..eeb7e7f44 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ssp.h @@ -0,0 +1,415 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX28 SSP Register Definitions + * + * Copyright (C) 2011 Marek Vasut + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __MX28_REGS_SSP_H__ +#define __MX28_REGS_SSP_H__ + +#include + +#ifndef __ASSEMBLY__ +#if defined(CONFIG_MX23) +struct mxs_ssp_regs { + mxs_reg_32(hw_ssp_ctrl0) + mxs_reg_32(hw_ssp_cmd0) + mxs_reg_32(hw_ssp_cmd1) + mxs_reg_32(hw_ssp_compref) + mxs_reg_32(hw_ssp_compmask) + mxs_reg_32(hw_ssp_timing) + mxs_reg_32(hw_ssp_ctrl1) + mxs_reg_32(hw_ssp_data) + mxs_reg_32(hw_ssp_sdresp0) + mxs_reg_32(hw_ssp_sdresp1) + mxs_reg_32(hw_ssp_sdresp2) + mxs_reg_32(hw_ssp_sdresp3) + mxs_reg_32(hw_ssp_status) + + uint32_t reserved1[12]; + + mxs_reg_32(hw_ssp_debug) + mxs_reg_32(hw_ssp_version) +}; +#elif defined(CONFIG_MX28) +struct mxs_ssp_regs { + mxs_reg_32(hw_ssp_ctrl0) + mxs_reg_32(hw_ssp_cmd0) + mxs_reg_32(hw_ssp_cmd1) + mxs_reg_32(hw_ssp_xfer_size) + mxs_reg_32(hw_ssp_block_size) + mxs_reg_32(hw_ssp_compref) + mxs_reg_32(hw_ssp_compmask) + mxs_reg_32(hw_ssp_timing) + mxs_reg_32(hw_ssp_ctrl1) + mxs_reg_32(hw_ssp_data) + mxs_reg_32(hw_ssp_sdresp0) + mxs_reg_32(hw_ssp_sdresp1) + mxs_reg_32(hw_ssp_sdresp2) + mxs_reg_32(hw_ssp_sdresp3) + mxs_reg_32(hw_ssp_ddr_ctrl) + mxs_reg_32(hw_ssp_dll_ctrl) + mxs_reg_32(hw_ssp_status) + mxs_reg_32(hw_ssp_dll_sts) + mxs_reg_32(hw_ssp_debug) + mxs_reg_32(hw_ssp_version) +}; +#endif + +static inline int mxs_ssp_bus_id_valid(int bus) +{ +#if defined(CONFIG_MX23) + const unsigned int mxs_ssp_chan_count = 2; +#elif defined(CONFIG_MX28) + const unsigned int mxs_ssp_chan_count = 4; +#endif + + if (bus >= mxs_ssp_chan_count) + return 0; + + if (bus < 0) + return 0; + + return 1; +} + +static inline int mxs_ssp_clock_by_bus(unsigned int clock) +{ +#if defined(CONFIG_MX23) + return 0; +#elif defined(CONFIG_MX28) + return clock; +#endif +} + +static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) +{ + switch (port) { + case 0: + return (struct mxs_ssp_regs *)MXS_SSP0_BASE; + case 1: + return (struct mxs_ssp_regs *)MXS_SSP1_BASE; +#ifdef CONFIG_MX28 + case 2: + return (struct mxs_ssp_regs *)MXS_SSP2_BASE; + case 3: + return (struct mxs_ssp_regs *)MXS_SSP3_BASE; +#endif + default: + return NULL; + } +} +#endif + +#define SSP_CTRL0_SFTRST (1 << 31) +#define SSP_CTRL0_CLKGATE (1 << 30) +#define SSP_CTRL0_RUN (1 << 29) +#define SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) +#define SSP_CTRL0_LOCK_CS (1 << 27) +#define SSP_CTRL0_IGNORE_CRC (1 << 26) +#define SSP_CTRL0_READ (1 << 25) +#define SSP_CTRL0_DATA_XFER (1 << 24) +#define SSP_CTRL0_BUS_WIDTH_MASK (0x3 << 22) +#define SSP_CTRL0_BUS_WIDTH_OFFSET 22 +#define SSP_CTRL0_BUS_WIDTH_ONE_BIT (0x0 << 22) +#define SSP_CTRL0_BUS_WIDTH_FOUR_BIT (0x1 << 22) +#define SSP_CTRL0_BUS_WIDTH_EIGHT_BIT (0x2 << 22) +#define SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) +#define SSP_CTRL0_WAIT_FOR_CMD (1 << 20) +#define SSP_CTRL0_LONG_RESP (1 << 19) +#define SSP_CTRL0_CHECK_RESP (1 << 18) +#define SSP_CTRL0_GET_RESP (1 << 17) +#define SSP_CTRL0_ENABLE (1 << 16) + +#ifdef CONFIG_MX23 +#define SSP_CTRL0_XFER_COUNT_OFFSET 0 +#define SSP_CTRL0_XFER_COUNT_MASK 0xffff +#endif + +#define SSP_CMD0_SOFT_TERMINATE (1 << 26) +#define SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) +#define SSP_CMD0_PRIM_BOOT_OP_EN (1 << 24) +#define SSP_CMD0_BOOT_ACK_EN (1 << 23) +#define SSP_CMD0_SLOW_CLKING_EN (1 << 22) +#define SSP_CMD0_CONT_CLKING_EN (1 << 21) +#define SSP_CMD0_APPEND_8CYC (1 << 20) +#if defined(CONFIG_MX23) +#define SSP_CMD0_BLOCK_SIZE_MASK (0xf << 16) +#define SSP_CMD0_BLOCK_SIZE_OFFSET 16 +#define SSP_CMD0_BLOCK_COUNT_MASK (0xff << 8) +#define SSP_CMD0_BLOCK_COUNT_OFFSET 8 +#endif +#define SSP_CMD0_CMD_MASK 0xff +#define SSP_CMD0_CMD_OFFSET 0 +#define SSP_CMD0_CMD_MMC_GO_IDLE_STATE 0x00 +#define SSP_CMD0_CMD_MMC_SEND_OP_COND 0x01 +#define SSP_CMD0_CMD_MMC_ALL_SEND_CID 0x02 +#define SSP_CMD0_CMD_MMC_SET_RELATIVE_ADDR 0x03 +#define SSP_CMD0_CMD_MMC_SET_DSR 0x04 +#define SSP_CMD0_CMD_MMC_RESERVED_5 0x05 +#define SSP_CMD0_CMD_MMC_SWITCH 0x06 +#define SSP_CMD0_CMD_MMC_SELECT_DESELECT_CARD 0x07 +#define SSP_CMD0_CMD_MMC_SEND_EXT_CSD 0x08 +#define SSP_CMD0_CMD_MMC_SEND_CSD 0x09 +#define SSP_CMD0_CMD_MMC_SEND_CID 0x0a +#define SSP_CMD0_CMD_MMC_READ_DAT_UNTIL_STOP 0x0b +#define SSP_CMD0_CMD_MMC_STOP_TRANSMISSION 0x0c +#define SSP_CMD0_CMD_MMC_SEND_STATUS 0x0d +#define SSP_CMD0_CMD_MMC_BUSTEST_R 0x0e +#define SSP_CMD0_CMD_MMC_GO_INACTIVE_STATE 0x0f +#define SSP_CMD0_CMD_MMC_SET_BLOCKLEN 0x10 +#define SSP_CMD0_CMD_MMC_READ_SINGLE_BLOCK 0x11 +#define SSP_CMD0_CMD_MMC_READ_MULTIPLE_BLOCK 0x12 +#define SSP_CMD0_CMD_MMC_BUSTEST_W 0x13 +#define SSP_CMD0_CMD_MMC_WRITE_DAT_UNTIL_STOP 0x14 +#define SSP_CMD0_CMD_MMC_SET_BLOCK_COUNT 0x17 +#define SSP_CMD0_CMD_MMC_WRITE_BLOCK 0x18 +#define SSP_CMD0_CMD_MMC_WRITE_MULTIPLE_BLOCK 0x19 +#define SSP_CMD0_CMD_MMC_PROGRAM_CID 0x1a +#define SSP_CMD0_CMD_MMC_PROGRAM_CSD 0x1b +#define SSP_CMD0_CMD_MMC_SET_WRITE_PROT 0x1c +#define SSP_CMD0_CMD_MMC_CLR_WRITE_PROT 0x1d +#define SSP_CMD0_CMD_MMC_SEND_WRITE_PROT 0x1e +#define SSP_CMD0_CMD_MMC_ERASE_GROUP_START 0x23 +#define SSP_CMD0_CMD_MMC_ERASE_GROUP_END 0x24 +#define SSP_CMD0_CMD_MMC_ERASE 0x26 +#define SSP_CMD0_CMD_MMC_FAST_IO 0x27 +#define SSP_CMD0_CMD_MMC_GO_IRQ_STATE 0x28 +#define SSP_CMD0_CMD_MMC_LOCK_UNLOCK 0x2a +#define SSP_CMD0_CMD_MMC_APP_CMD 0x37 +#define SSP_CMD0_CMD_MMC_GEN_CMD 0x38 +#define SSP_CMD0_CMD_SD_GO_IDLE_STATE 0x00 +#define SSP_CMD0_CMD_SD_ALL_SEND_CID 0x02 +#define SSP_CMD0_CMD_SD_SEND_RELATIVE_ADDR 0x03 +#define SSP_CMD0_CMD_SD_SET_DSR 0x04 +#define SSP_CMD0_CMD_SD_IO_SEND_OP_COND 0x05 +#define SSP_CMD0_CMD_SD_SELECT_DESELECT_CARD 0x07 +#define SSP_CMD0_CMD_SD_SEND_CSD 0x09 +#define SSP_CMD0_CMD_SD_SEND_CID 0x0a +#define SSP_CMD0_CMD_SD_STOP_TRANSMISSION 0x0c +#define SSP_CMD0_CMD_SD_SEND_STATUS 0x0d +#define SSP_CMD0_CMD_SD_GO_INACTIVE_STATE 0x0f +#define SSP_CMD0_CMD_SD_SET_BLOCKLEN 0x10 +#define SSP_CMD0_CMD_SD_READ_SINGLE_BLOCK 0x11 +#define SSP_CMD0_CMD_SD_READ_MULTIPLE_BLOCK 0x12 +#define SSP_CMD0_CMD_SD_WRITE_BLOCK 0x18 +#define SSP_CMD0_CMD_SD_WRITE_MULTIPLE_BLOCK 0x19 +#define SSP_CMD0_CMD_SD_PROGRAM_CSD 0x1b +#define SSP_CMD0_CMD_SD_SET_WRITE_PROT 0x1c +#define SSP_CMD0_CMD_SD_CLR_WRITE_PROT 0x1d +#define SSP_CMD0_CMD_SD_SEND_WRITE_PROT 0x1e +#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_START 0x20 +#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_END 0x21 +#define SSP_CMD0_CMD_SD_ERASE_GROUP_START 0x23 +#define SSP_CMD0_CMD_SD_ERASE_GROUP_END 0x24 +#define SSP_CMD0_CMD_SD_ERASE 0x26 +#define SSP_CMD0_CMD_SD_LOCK_UNLOCK 0x2a +#define SSP_CMD0_CMD_SD_IO_RW_DIRECT 0x34 +#define SSP_CMD0_CMD_SD_IO_RW_EXTENDED 0x35 +#define SSP_CMD0_CMD_SD_APP_CMD 0x37 +#define SSP_CMD0_CMD_SD_GEN_CMD 0x38 + +#define SSP_CMD1_CMD_ARG_MASK 0xffffffff +#define SSP_CMD1_CMD_ARG_OFFSET 0 + +#if defined(CONFIG_MX28) +#define SSP_XFER_SIZE_XFER_COUNT_MASK 0xffffffff +#define SSP_XFER_SIZE_XFER_COUNT_OFFSET 0 + +#define SSP_BLOCK_SIZE_BLOCK_COUNT_MASK (0xffffff << 4) +#define SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET 4 +#define SSP_BLOCK_SIZE_BLOCK_SIZE_MASK 0xf +#define SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET 0 +#endif + +#define SSP_COMPREF_REFERENCE_MASK 0xffffffff +#define SSP_COMPREF_REFERENCE_OFFSET 0 + +#define SSP_COMPMASK_MASK_MASK 0xffffffff +#define SSP_COMPMASK_MASK_OFFSET 0 + +#define SSP_TIMING_TIMEOUT_MASK (0xffff << 16) +#define SSP_TIMING_TIMEOUT_OFFSET 16 +#define SSP_TIMING_CLOCK_DIVIDE_MASK (0xff << 8) +#define SSP_TIMING_CLOCK_DIVIDE_OFFSET 8 +#define SSP_TIMING_CLOCK_RATE_MASK 0xff +#define SSP_TIMING_CLOCK_RATE_OFFSET 0 + +#define SSP_CTRL1_SDIO_IRQ (1 << 31) +#define SSP_CTRL1_SDIO_IRQ_EN (1 << 30) +#define SSP_CTRL1_RESP_ERR_IRQ (1 << 29) +#define SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) +#define SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) +#define SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) +#define SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) +#define SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) +#define SSP_CTRL1_DATA_CRC_IRQ (1 << 23) +#define SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) +#define SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) +#define SSP_CTRL1_FIFO_UNDERRUN_EN (1 << 20) +#define SSP_CTRL1_CEATA_CCS_ERR_IRQ (1 << 19) +#define SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN (1 << 18) +#define SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) +#define SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) +#define SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) +#define SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) +#define SSP_CTRL1_DMA_ENABLE (1 << 13) +#define SSP_CTRL1_CEATA_CCS_ERR_EN (1 << 12) +#define SSP_CTRL1_SLAVE_OUT_DISABLE (1 << 11) +#define SSP_CTRL1_PHASE (1 << 10) +#define SSP_CTRL1_POLARITY (1 << 9) +#define SSP_CTRL1_SLAVE_MODE (1 << 8) +#define SSP_CTRL1_WORD_LENGTH_MASK (0xf << 4) +#define SSP_CTRL1_WORD_LENGTH_OFFSET 4 +#define SSP_CTRL1_WORD_LENGTH_RESERVED0 (0x0 << 4) +#define SSP_CTRL1_WORD_LENGTH_RESERVED1 (0x1 << 4) +#define SSP_CTRL1_WORD_LENGTH_RESERVED2 (0x2 << 4) +#define SSP_CTRL1_WORD_LENGTH_FOUR_BITS (0x3 << 4) +#define SSP_CTRL1_WORD_LENGTH_EIGHT_BITS (0x7 << 4) +#define SSP_CTRL1_WORD_LENGTH_SIXTEEN_BITS (0xf << 4) +#define SSP_CTRL1_SSP_MODE_MASK 0xf +#define SSP_CTRL1_SSP_MODE_OFFSET 0 +#define SSP_CTRL1_SSP_MODE_SPI 0x0 +#define SSP_CTRL1_SSP_MODE_SSI 0x1 +#define SSP_CTRL1_SSP_MODE_SD_MMC 0x3 +#define SSP_CTRL1_SSP_MODE_MS 0x4 + +#define SSP_DATA_DATA_MASK 0xffffffff +#define SSP_DATA_DATA_OFFSET 0 + +#define SSP_SDRESP0_RESP0_MASK 0xffffffff +#define SSP_SDRESP0_RESP0_OFFSET 0 + +#define SSP_SDRESP1_RESP1_MASK 0xffffffff +#define SSP_SDRESP1_RESP1_OFFSET 0 + +#define SSP_SDRESP2_RESP2_MASK 0xffffffff +#define SSP_SDRESP2_RESP2_OFFSET 0 + +#define SSP_SDRESP3_RESP3_MASK 0xffffffff +#define SSP_SDRESP3_RESP3_OFFSET 0 + +#define SSP_DDR_CTRL_DMA_BURST_TYPE_MASK (0x3 << 30) +#define SSP_DDR_CTRL_DMA_BURST_TYPE_OFFSET 30 +#define SSP_DDR_CTRL_NIBBLE_POS (1 << 1) +#define SSP_DDR_CTRL_TXCLK_DELAY_TYPE (1 << 0) + +#define SSP_DLL_CTRL_REF_UPDATE_INT_MASK (0xf << 28) +#define SSP_DLL_CTRL_REF_UPDATE_INT_OFFSET 28 +#define SSP_DLL_CTRL_SLV_UPDATE_INT_MASK (0xff << 20) +#define SSP_DLL_CTRL_SLV_UPDATE_INT_OFFSET 20 +#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3f << 10) +#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_OFFSET 10 +#define SSP_DLL_CTRL_SLV_OVERRIDE (1 << 9) +#define SSP_DLL_CTRL_GATE_UPDATE (1 << 7) +#define SSP_DLL_CTRL_SLV_DLY_TARGET_MASK (0xf << 3) +#define SSP_DLL_CTRL_SLV_DLY_TARGET_OFFSET 3 +#define SSP_DLL_CTRL_SLV_FORCE_UPD (1 << 2) +#define SSP_DLL_CTRL_RESET (1 << 1) +#define SSP_DLL_CTRL_ENABLE (1 << 0) + +#define SSP_STATUS_PRESENT (1 << 31) +#define SSP_STATUS_MS_PRESENT (1 << 30) +#define SSP_STATUS_SD_PRESENT (1 << 29) +#define SSP_STATUS_CARD_DETECT (1 << 28) +#define SSP_STATUS_DMABURST (1 << 22) +#define SSP_STATUS_DMASENSE (1 << 21) +#define SSP_STATUS_DMATERM (1 << 20) +#define SSP_STATUS_DMAREQ (1 << 19) +#define SSP_STATUS_DMAEND (1 << 18) +#define SSP_STATUS_SDIO_IRQ (1 << 17) +#define SSP_STATUS_RESP_CRC_ERR (1 << 16) +#define SSP_STATUS_RESP_ERR (1 << 15) +#define SSP_STATUS_RESP_TIMEOUT (1 << 14) +#define SSP_STATUS_DATA_CRC_ERR (1 << 13) +#define SSP_STATUS_TIMEOUT (1 << 12) +#define SSP_STATUS_RECV_TIMEOUT_STAT (1 << 11) +#define SSP_STATUS_CEATA_CCS_ERR (1 << 10) +#define SSP_STATUS_FIFO_OVRFLW (1 << 9) +#define SSP_STATUS_FIFO_FULL (1 << 8) +#define SSP_STATUS_FIFO_EMPTY (1 << 5) +#define SSP_STATUS_FIFO_UNDRFLW (1 << 4) +#define SSP_STATUS_CMD_BUSY (1 << 3) +#define SSP_STATUS_DATA_BUSY (1 << 2) +#define SSP_STATUS_BUSY (1 << 0) + +#define SSP_DLL_STS_REF_SEL_MASK (0x3f << 8) +#define SSP_DLL_STS_REF_SEL_OFFSET 8 +#define SSP_DLL_STS_SLV_SEL_MASK (0x3f << 2) +#define SSP_DLL_STS_SLV_SEL_OFFSET 2 +#define SSP_DLL_STS_REF_LOCK (1 << 1) +#define SSP_DLL_STS_SLV_LOCK (1 << 0) + +#define SSP_DEBUG_DATACRC_ERR_MASK (0xf << 28) +#define SSP_DEBUG_DATACRC_ERR_OFFSET 28 +#define SSP_DEBUG_DATA_STALL (1 << 27) +#define SSP_DEBUG_DAT_SM_MASK (0x7 << 24) +#define SSP_DEBUG_DAT_SM_OFFSET 24 +#define SSP_DEBUG_DAT_SM_DSM_IDLE (0x0 << 24) +#define SSP_DEBUG_DAT_SM_DSM_WORD (0x2 << 24) +#define SSP_DEBUG_DAT_SM_DSM_CRC1 (0x3 << 24) +#define SSP_DEBUG_DAT_SM_DSM_CRC2 (0x4 << 24) +#define SSP_DEBUG_DAT_SM_DSM_END (0x5 << 24) +#define SSP_DEBUG_MSTK_SM_MASK (0xf << 20) +#define SSP_DEBUG_MSTK_SM_OFFSET 20 +#define SSP_DEBUG_MSTK_SM_MSTK_IDLE (0x0 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_CKON (0x1 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_BS1 (0x2 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_TPC (0x3 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_BS2 (0x4 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_HDSHK (0x5 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_BS3 (0x6 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_RW (0x7 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_CRC1 (0x8 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_CRC2 (0x9 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_BS0 (0xa << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_END1 (0xb << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_END2W (0xc << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_END2R (0xd << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_DONE (0xe << 20) +#define SSP_DEBUG_CMD_OE (1 << 19) +#define SSP_DEBUG_DMA_SM_MASK (0x7 << 16) +#define SSP_DEBUG_DMA_SM_OFFSET 16 +#define SSP_DEBUG_DMA_SM_DMA_IDLE (0x0 << 16) +#define SSP_DEBUG_DMA_SM_DMA_DMAREQ (0x1 << 16) +#define SSP_DEBUG_DMA_SM_DMA_DMAACK (0x2 << 16) +#define SSP_DEBUG_DMA_SM_DMA_STALL (0x3 << 16) +#define SSP_DEBUG_DMA_SM_DMA_BUSY (0x4 << 16) +#define SSP_DEBUG_DMA_SM_DMA_DONE (0x5 << 16) +#define SSP_DEBUG_DMA_SM_DMA_COUNT (0x6 << 16) +#define SSP_DEBUG_MMC_SM_MASK (0xf << 12) +#define SSP_DEBUG_MMC_SM_OFFSET 12 +#define SSP_DEBUG_MMC_SM_MMC_IDLE (0x0 << 12) +#define SSP_DEBUG_MMC_SM_MMC_CMD (0x1 << 12) +#define SSP_DEBUG_MMC_SM_MMC_TRC (0x2 << 12) +#define SSP_DEBUG_MMC_SM_MMC_RESP (0x3 << 12) +#define SSP_DEBUG_MMC_SM_MMC_RPRX (0x4 << 12) +#define SSP_DEBUG_MMC_SM_MMC_TX (0x5 << 12) +#define SSP_DEBUG_MMC_SM_MMC_CTOK (0x6 << 12) +#define SSP_DEBUG_MMC_SM_MMC_RX (0x7 << 12) +#define SSP_DEBUG_MMC_SM_MMC_CCS (0x8 << 12) +#define SSP_DEBUG_MMC_SM_MMC_PUP (0x9 << 12) +#define SSP_DEBUG_MMC_SM_MMC_WAIT (0xa << 12) +#define SSP_DEBUG_CMD_SM_MASK (0x3 << 10) +#define SSP_DEBUG_CMD_SM_OFFSET 10 +#define SSP_DEBUG_CMD_SM_CSM_IDLE (0x0 << 10) +#define SSP_DEBUG_CMD_SM_CSM_INDEX (0x1 << 10) +#define SSP_DEBUG_CMD_SM_CSM_ARG (0x2 << 10) +#define SSP_DEBUG_CMD_SM_CSM_CRC (0x3 << 10) +#define SSP_DEBUG_SSP_CMD (1 << 9) +#define SSP_DEBUG_SSP_RESP (1 << 8) +#define SSP_DEBUG_SSP_RXD_MASK 0xff +#define SSP_DEBUG_SSP_RXD_OFFSET 0 + +#define SSP_VERSION_MAJOR_MASK (0xff << 24) +#define SSP_VERSION_MAJOR_OFFSET 24 +#define SSP_VERSION_MINOR_MASK (0xff << 16) +#define SSP_VERSION_MINOR_OFFSET 16 +#define SSP_VERSION_STEP_MASK 0xffff +#define SSP_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_SSP_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-timrot.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-timrot.h new file mode 100644 index 000000000..9e19aabf1 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-timrot.h @@ -0,0 +1,258 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX28 TIMROT Register Definitions + * + * Copyright (C) 2011 Marek Vasut + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __MX28_REGS_TIMROT_H__ +#define __MX28_REGS_TIMROT_H__ + +#include + +#ifndef __ASSEMBLY__ +struct mxs_timrot_regs { + mxs_reg_32(hw_timrot_rotctrl) + mxs_reg_32(hw_timrot_rotcount) +#if defined(CONFIG_MX23) + mxs_reg_32(hw_timrot_timctrl0) + mxs_reg_32(hw_timrot_timcount0) + mxs_reg_32(hw_timrot_timctrl1) + mxs_reg_32(hw_timrot_timcount1) + mxs_reg_32(hw_timrot_timctrl2) + mxs_reg_32(hw_timrot_timcount2) + mxs_reg_32(hw_timrot_timctrl3) + mxs_reg_32(hw_timrot_timcount3) +#elif defined(CONFIG_MX28) + mxs_reg_32(hw_timrot_timctrl0) + mxs_reg_32(hw_timrot_running_count0) + mxs_reg_32(hw_timrot_fixed_count0) + mxs_reg_32(hw_timrot_match_count0) + mxs_reg_32(hw_timrot_timctrl1) + mxs_reg_32(hw_timrot_running_count1) + mxs_reg_32(hw_timrot_fixed_count1) + mxs_reg_32(hw_timrot_match_count1) + mxs_reg_32(hw_timrot_timctrl2) + mxs_reg_32(hw_timrot_running_count2) + mxs_reg_32(hw_timrot_fixed_count2) + mxs_reg_32(hw_timrot_match_count2) + mxs_reg_32(hw_timrot_timctrl3) + mxs_reg_32(hw_timrot_running_count3) + mxs_reg_32(hw_timrot_fixed_count3) + mxs_reg_32(hw_timrot_match_count3) +#endif + mxs_reg_32(hw_timrot_version) +}; +#endif + +#define TIMROT_ROTCTRL_SFTRST (1 << 31) +#define TIMROT_ROTCTRL_CLKGATE (1 << 30) +#define TIMROT_ROTCTRL_ROTARY_PRESENT (1 << 29) +#define TIMROT_ROTCTRL_TIM3_PRESENT (1 << 28) +#define TIMROT_ROTCTRL_TIM2_PRESENT (1 << 27) +#define TIMROT_ROTCTRL_TIM1_PRESENT (1 << 26) +#define TIMROT_ROTCTRL_TIM0_PRESENT (1 << 25) +#define TIMROT_ROTCTRL_STATE_MASK (0x7 << 22) +#define TIMROT_ROTCTRL_STATE_OFFSET 22 +#define TIMROT_ROTCTRL_DIVIDER_MASK (0x3f << 16) +#define TIMROT_ROTCTRL_DIVIDER_OFFSET 16 +#define TIMROT_ROTCTRL_RELATIVE (1 << 12) +#define TIMROT_ROTCTRL_OVERSAMPLE_MASK (0x3 << 10) +#define TIMROT_ROTCTRL_OVERSAMPLE_OFFSET 10 +#define TIMROT_ROTCTRL_OVERSAMPLE_8X (0x0 << 10) +#define TIMROT_ROTCTRL_OVERSAMPLE_4X (0x1 << 10) +#define TIMROT_ROTCTRL_OVERSAMPLE_2X (0x2 << 10) +#define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10) +#define TIMROT_ROTCTRL_POLARITY_B (1 << 9) +#define TIMROT_ROTCTRL_POLARITY_A (1 << 8) +#if defined(CONFIG_MX23) +#define TIMROT_ROTCTRL_SELECT_B_MASK (0x7 << 4) +#elif defined(CONFIG_MX28) +#define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4) +#endif +#define TIMROT_ROTCTRL_SELECT_B_OFFSET 4 +#define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM1 (0x2 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4) +#if defined(CONFIG_MX23) +#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x6 << 4) +#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0x7 << 4) +#elif defined(CONFIG_MX28) +#define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4) +#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4) +#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4) +#endif +#if defined(CONFIG_MX23) +#define TIMROT_ROTCTRL_SELECT_A_MASK 0x7 +#elif defined(CONFIG_MX28) +#define TIMROT_ROTCTRL_SELECT_A_MASK 0xf +#endif +#define TIMROT_ROTCTRL_SELECT_A_OFFSET 0 +#define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0 +#define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1 +#define TIMROT_ROTCTRL_SELECT_A_PWM1 0x2 +#define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3 +#define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4 +#define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5 +#if defined(CONFIG_MX23) +#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x6 +#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0x7 +#elif defined(CONFIG_MX28) +#define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6 +#define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7 +#define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8 +#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9 +#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa +#endif + +#define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff +#define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0 + +#define TIMROT_TIMCTRLn_IRQ (1 << 15) +#define TIMROT_TIMCTRLn_IRQ_EN (1 << 14) +#if defined(CONFIG_MX28) +#define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11) +#endif +#define TIMROT_TIMCTRLn_POLARITY (1 << 8) +#define TIMROT_TIMCTRLn_UPDATE (1 << 7) +#define TIMROT_TIMCTRLn_RELOAD (1 << 6) +#define TIMROT_TIMCTRLn_PRESCALE_MASK (0x3 << 4) +#define TIMROT_TIMCTRLn_PRESCALE_OFFSET 4 +#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1 (0x0 << 4) +#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_2 (0x1 << 4) +#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_4 (0x2 << 4) +#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_8 (0x3 << 4) +#define TIMROT_TIMCTRLn_SELECT_MASK 0xf +#define TIMROT_TIMCTRLn_SELECT_OFFSET 0 +#define TIMROT_TIMCTRLn_SELECT_NEVER_TICK 0x0 +#define TIMROT_TIMCTRLn_SELECT_PWM0 0x1 +#define TIMROT_TIMCTRLn_SELECT_PWM1 0x2 +#define TIMROT_TIMCTRLn_SELECT_PWM2 0x3 +#define TIMROT_TIMCTRLn_SELECT_PWM3 0x4 +#define TIMROT_TIMCTRLn_SELECT_PWM4 0x5 +#if defined(CONFIG_MX23) +#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x6 +#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0x7 +#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0x8 +#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0x9 +#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xa +#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xb +#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xc +#elif defined(CONFIG_MX28) +#define TIMROT_TIMCTRLn_SELECT_PWM5 0x6 +#define TIMROT_TIMCTRLn_SELECT_PWM6 0x7 +#define TIMROT_TIMCTRLn_SELECT_PWM7 0x8 +#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x9 +#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0xa +#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0xb +#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0xc +#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd +#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe +#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf +#endif + +#if defined(CONFIG_MX23) +#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK (0xffff << 16) +#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 16 +#elif defined(CONFIG_MX28) +#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff +#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0 +#endif + +#if defined(CONFIG_MX23) +#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffff +#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 +#elif defined(CONFIG_MX28) +#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff +#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 +#endif + +#if defined(CONFIG_MX28) +#define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff +#define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0 +#endif + +#define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16 +#define TIMROT_TIMCTRL3_TEST_SIGNAL_NEVER_TICK (0x0 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM0 (0x1 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM1 (0x2 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16) +#if defined(CONFIG_MX23) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x6 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0x7 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0x8 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0x9 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xa << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xb << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xc << 16) +#elif defined(CONFIG_MX28) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x9 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0xa << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0xb << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0xc << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16) +#endif +#if defined(CONFIG_MX23) +#define TIMROT_TIMCTRL3_IRQ (1 << 15) +#define TIMROT_TIMCTRL3_IRQ_EN (1 << 14) +#define TIMROT_TIMCTRL3_DUTU_VALID (1 << 10) +#endif +#define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9) +#if defined(CONFIG_MX23) +#define TIMROT_TIMCTRL3_POLARITY_MASK (0x1 << 8) +#define TIMROT_TIMCTRL3_POLARITY_OFFSET 8 +#define TIMROT_TIMCTRL3_POLARITY_POSITIVE (0x0 << 8) +#define TIMROT_TIMCTRL3_POLARITY_NEGATIVE (0x1 << 8) +#define TIMROT_TIMCTRL3_UPDATE (1 << 7) +#define TIMROT_TIMCTRL3_RELOAD (1 << 6) +#define TIMROT_TIMCTRL3_PRESCALE_MASK (0x3 << 4) +#define TIMROT_TIMCTRL3_PRESCALE_OFFSET 4 +#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1 (0x0 << 4) +#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2 (0x1 << 4) +#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4 (0x2 << 4) +#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8 (0x3 << 4) +#define TIMROT_TIMCTRL3_SELECT_MASK 0xf +#define TIMROT_TIMCTRL3_SELECT_OFFSET 0 +#define TIMROT_TIMCTRL3_SELECT_NEVER_TICK 0x0 +#define TIMROT_TIMCTRL3_SELECT_PWM0 0x1 +#define TIMROT_TIMCTRL3_SELECT_PWM1 0x2 +#define TIMROT_TIMCTRL3_SELECT_PWM2 0x3 +#define TIMROT_TIMCTRL3_SELECT_PWM3 0x4 +#define TIMROT_TIMCTRL3_SELECT_PWM4 0x5 +#define TIMROT_TIMCTRL3_SELECT_ROTARYA 0x6 +#define TIMROT_TIMCTRL3_SELECT_ROTARYB 0x7 +#define TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL 0x8 +#define TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL 0x9 +#define TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL 0xa +#define TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL 0xb +#define TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS 0xc +#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK (0xffff << 16) +#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET 16 +#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK 0xffff +#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET 0 +#endif + +#define TIMROT_VERSION_MAJOR_MASK (0xff << 24) +#define TIMROT_VERSION_MAJOR_OFFSET 24 +#define TIMROT_VERSION_MINOR_MASK (0xff << 16) +#define TIMROT_VERSION_MINOR_OFFSET 16 +#define TIMROT_VERSION_STEP_MASK 0xffff +#define TIMROT_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_TIMROT_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-uartapp.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-uartapp.h new file mode 100644 index 000000000..d89cf27b6 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-uartapp.h @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale MXS UARTAPP Register Definitions + * + * Copyright (C) 2013 Andreas Wass + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __ARCH_ARM___MXS_UARTAPP_H +#define __ARCH_ARM___MXS_UARTAPP_H + +#include + +#ifndef __ASSEMBLY__ +struct mxs_uartapp_regs { + mxs_reg_32(hw_uartapp_ctrl0) + mxs_reg_32(hw_uartapp_ctrl1) + mxs_reg_32(hw_uartapp_ctrl2) + mxs_reg_32(hw_uartapp_linectrl) + mxs_reg_32(hw_uartapp_linectrl2) + mxs_reg_32(hw_uartapp_intr) + mxs_reg_32(hw_uartapp_data) + mxs_reg_32(hw_uartapp_stat) + mxs_reg_32(hw_uartapp_debug) + mxs_reg_32(hw_uartapp_version) + mxs_reg_32(hw_uartapp_autobaud) +}; +#endif + +#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31) +#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30) +#define UARTAPP_CTRL0_RUN_MASK (1 << 29) +#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28) +#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27) +#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16 +#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16) +#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0 +#define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF + +#define UARTAPP_CTRL1_RUN_MASK (1 << 28) + +#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0 +#define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF + +#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31) +#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30) +#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29) +#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28) +#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27) +#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26) +#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25) +#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24) +#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20 +#define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20) + +#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20) +#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16 +#define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16) +#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15) +#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14) +#define UARTAPP_CTRL2_OUT2_MASK (1 << 13) +#define UARTAPP_CTRL2_OUT1_MASK (1 << 12) +#define UARTAPP_CTRL2_RTS_MASK (1 << 11) +#define UARTAPP_CTRL2_DTR_MASK (1 << 10) +#define UARTAPP_CTRL2_RXE_MASK (1 << 9) +#define UARTAPP_CTRL2_TXE_MASK (1 << 8) +#define UARTAPP_CTRL2_LBE_MASK (1 << 7) +#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6) + +#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2) +#define UARTAPP_CTRL2_SIREN_MASK (1 << 1) +#define UARTAPP_CTRL2_UARTEN_MASK 0x01 + +#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16 +#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16) +#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6 + +#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8 +#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8) +#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F + +#define UARTAPP_LINECTRL_SPS_MASK (1 << 7) +#define UARTAPP_LINECTRL_WLEN_OFFSET 5 +#define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5) +#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5) +#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5) +#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5) +#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5) + +#define UARTAPP_LINECTRL_FEN_MASK (1 << 4) +#define UARTAPP_LINECTRL_STP2_MASK (1 << 3) +#define UARTAPP_LINECTRL_EPS_MASK (1 << 2) +#define UARTAPP_LINECTRL_PEN_MASK (1 << 1) +#define UARTAPP_LINECTRL_BRK_MASK 1 + +#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16 +#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16) +#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6 + +#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8 +#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8) +#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F + +#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7) +#define UARTAPP_LINECTRL2_WLEN_OFFSET 5 +#define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5) +#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5) +#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5) +#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5) +#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5) + +#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4) +#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3) +#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2) +#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1) + +#define UARTAPP_INTR_ABDIEN_MASK (1 << 27) +#define UARTAPP_INTR_OEIEN_MASK (1 << 26) +#define UARTAPP_INTR_BEIEN_MASK (1 << 25) +#define UARTAPP_INTR_PEIEN_MASK (1 << 24) +#define UARTAPP_INTR_FEIEN_MASK (1 << 23) +#define UARTAPP_INTR_RTIEN_MASK (1 << 22) +#define UARTAPP_INTR_TXIEN_MASK (1 << 21) +#define UARTAPP_INTR_RXIEN_MASK (1 << 20) +#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19) +#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18) +#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17) +#define UARTAPP_INTR_RIMIEN_MASK (1 << 16) + +#define UARTAPP_INTR_ABDIS_MASK (1 << 11) +#define UARTAPP_INTR_OEIS_MASK (1 << 10) +#define UARTAPP_INTR_BEIS_MASK (1 << 9) +#define UARTAPP_INTR_PEIS_MASK (1 << 8) +#define UARTAPP_INTR_FEIS_MASK (1 << 7) +#define UARTAPP_INTR_RTIS_MASK (1 << 6) +#define UARTAPP_INTR_TXIS_MASK (1 << 5) +#define UARTAPP_INTR_RXIS_MASK (1 << 4) +#define UARTAPP_INTR_DSRMIS_MASK (1 << 3) +#define UARTAPP_INTR_DCDMIS_MASK (1 << 2) +#define UARTAPP_INTR_CTSMIS_MASK (1 << 1) +#define UARTAPP_INTR_RIMIS_MASK 0x1 + +#define UARTAPP_DATA_DATA_OFFSET 0 +#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF +#define UARTAPP_STAT_PRESENT_MASK (1 << 31) +#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31) +#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31) + +#define UARTAPP_STAT_HISPEED_MASK (1 << 30) +#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30) +#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30) + +#define UARTAPP_STAT_BUSY_MASK (1 << 29) +#define UARTAPP_STAT_CTS_MASK (1 << 28) +#define UARTAPP_STAT_TXFE_MASK (1 << 27) +#define UARTAPP_STAT_RXFF_MASK (1 << 26) +#define UARTAPP_STAT_TXFF_MASK (1 << 25) +#define UARTAPP_STAT_RXFE_MASK (1 << 24) +#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20 +#define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20) + +#define UARTAPP_STAT_OERR_MASK (1 << 19) +#define UARTAPP_STAT_BERR_MASK (1 << 18) +#define UARTAPP_STAT_PERR_MASK (1 << 17) +#define UARTAPP_STAT_FERR_MASK (1 << 16) +#define UARTAPP_STAT_RXCOUNT_OFFSET 0 +#define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF + +#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16 +#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16) + +#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10 +#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10) + +#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5) +#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4) +#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3) +#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2) +#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1) +#define UARTAPP_DEBUG_RXDMARQ_MASK 0x01 + +#define UARTAPP_VERSION_MAJOR_OFFSET 24 +#define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24) + +#define UARTAPP_VERSION_MINOR_OFFSET 16 +#define UARTAPP_VERSION_MINOR_MASK (0xFF << 16) + +#define UARTAPP_VERSION_STEP_OFFSET 0 +#define UARTAPP_VERSION_STEP_MASK 0xFFFF + +#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24 +#define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24) + +#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16 +#define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16) + +#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4) +#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3) +#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2) +#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1) +#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01 +#endif /* __ARCH_ARM___UARTAPP_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usb.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usb.h new file mode 100644 index 000000000..8d5168dd8 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usb.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX28 USB OTG Register Definitions + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ + +#ifndef __REGS_USB_H__ +#define __REGS_USB_H__ + +struct mxs_usb_regs { + uint32_t hw_usbctrl_id; /* 0x000 */ + uint32_t hw_usbctrl_hwgeneral; /* 0x004 */ + uint32_t hw_usbctrl_hwhost; /* 0x008 */ + uint32_t hw_usbctrl_hwdevice; /* 0x00c */ + uint32_t hw_usbctrl_hwtxbuf; /* 0x010 */ + uint32_t hw_usbctrl_hwrxbuf; /* 0x014 */ + + uint32_t reserved1[26]; + + uint32_t hw_usbctrl_gptimer0ld; /* 0x080 */ + uint32_t hw_usbctrl_gptimer0ctrl; /* 0x084 */ + uint32_t hw_usbctrl_gptimer1ld; /* 0x088 */ + uint32_t hw_usbctrl_gptimer1ctrl; /* 0x08c */ + uint32_t hw_usbctrl_sbuscfg; /* 0x090 */ + + uint32_t reserved2[27]; + + uint32_t hw_usbctrl_caplength; /* 0x100 */ + uint32_t hw_usbctrl_hcsparams; /* 0x104 */ + uint32_t hw_usbctrl_hccparams; /* 0x108 */ + + uint32_t reserved3[5]; + + uint32_t hw_usbctrl_dciversion; /* 0x120 */ + uint32_t hw_usbctrl_dccparams; /* 0x124 */ + + uint32_t reserved4[6]; + + uint32_t hw_usbctrl_usbcmd; /* 0x140 */ + uint32_t hw_usbctrl_usbsts; /* 0x144 */ + uint32_t hw_usbctrl_usbintr; /* 0x148 */ + uint32_t hw_usbctrl_frindex; /* 0x14c */ + + uint32_t reserved5; + + union { + uint32_t hw_usbctrl_periodiclistbase; /* 0x154 */ + uint32_t hw_usbctrl_deviceaddr; /* 0x154 */ + }; + union { + uint32_t hw_usbctrl_asynclistaddr; /* 0x158 */ + uint32_t hw_usbctrl_endpointlistaddr; /* 0x158 */ + }; + + uint32_t hw_usbctrl_ttctrl; /* 0x15c */ + uint32_t hw_usbctrl_burstsize; /* 0x160 */ + uint32_t hw_usbctrl_txfilltuning; /* 0x164 */ + + uint32_t reserved6; + + uint32_t hw_usbctrl_ic_usb; /* 0x16c */ + uint32_t hw_usbctrl_ulpi; /* 0x170 */ + + uint32_t reserved7; + + uint32_t hw_usbctrl_endptnak; /* 0x178 */ + uint32_t hw_usbctrl_endptnaken; /* 0x17c */ + + uint32_t reserved8; + + uint32_t hw_usbctrl_portsc1; /* 0x184 */ + + uint32_t reserved9[7]; + + uint32_t hw_usbctrl_otgsc; /* 0x1a4 */ + uint32_t hw_usbctrl_usbmode; /* 0x1a8 */ + uint32_t hw_usbctrl_endptsetupstat; /* 0x1ac */ + uint32_t hw_usbctrl_endptprime; /* 0x1b0 */ + uint32_t hw_usbctrl_endptflush; /* 0x1b4 */ + uint32_t hw_usbctrl_endptstat; /* 0x1b8 */ + uint32_t hw_usbctrl_endptcomplete; /* 0x1bc */ + uint32_t hw_usbctrl_endptctrl0; /* 0x1c0 */ + uint32_t hw_usbctrl_endptctrl1; /* 0x1c4 */ + uint32_t hw_usbctrl_endptctrl2; /* 0x1c8 */ + uint32_t hw_usbctrl_endptctrl3; /* 0x1cc */ + uint32_t hw_usbctrl_endptctrl4; /* 0x1d0 */ + uint32_t hw_usbctrl_endptctrl5; /* 0x1d4 */ + uint32_t hw_usbctrl_endptctrl6; /* 0x1d8 */ + uint32_t hw_usbctrl_endptctrl7; /* 0x1dc */ +}; + +#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) + +#define HW_USBCTRL_ID_CIVERSION_OFFSET 29 +#define HW_USBCTRL_ID_CIVERSION_MASK (0x7 << 29) +#define HW_USBCTRL_ID_VERSION_OFFSET 25 +#define HW_USBCTRL_ID_VERSION_MASK (0xf << 25) +#define HW_USBCTRL_ID_REVISION_OFFSET 21 +#define HW_USBCTRL_ID_REVISION_MASK (0xf << 21) +#define HW_USBCTRL_ID_TAG_OFFSET 16 +#define HW_USBCTRL_ID_TAG_MASK (0x1f << 16) +#define HW_USBCTRL_ID_NID_OFFSET 8 +#define HW_USBCTRL_ID_NID_MASK (0x3f << 8) +#define HW_USBCTRL_ID_ID_OFFSET 0 +#define HW_USBCTRL_ID_ID_MASK (0x3f << 0) + +#define HW_USBCTRL_HWGENERAL_SM_OFFSET 9 +#define HW_USBCTRL_HWGENERAL_SM_MASK (0x3 << 9) +#define HW_USBCTRL_HWGENERAL_PHYM_OFFSET 6 +#define HW_USBCTRL_HWGENERAL_PHYM_MASK (0x7 << 6) +#define HW_USBCTRL_HWGENERAL_PHYW_OFFSET 4 +#define HW_USBCTRL_HWGENERAL_PHYW_MASK (0x3 << 4) +#define HW_USBCTRL_HWGENERAL_BWT (1 << 3) +#define HW_USBCTRL_HWGENERAL_CLKC_OFFSET 1 +#define HW_USBCTRL_HWGENERAL_CLKC_MASK (0x3 << 1) +#define HW_USBCTRL_HWGENERAL_RT (1 << 0) + +#define HW_USBCTRL_HWHOST_TTPER_OFFSET 24 +#define HW_USBCTRL_HWHOST_TTPER_MASK (0xff << 24) +#define HW_USBCTRL_HWHOST_TTASY_OFFSET 16 +#define HW_USBCTRL_HWHOST_TTASY_MASK (0xff << 19) +#define HW_USBCTRL_HWHOST_NPORT_OFFSET 1 +#define HW_USBCTRL_HWHOST_NPORT_MASK (0x7 << 1) +#define HW_USBCTRL_HWHOST_HC (1 << 0) + +#define HW_USBCTRL_HWDEVICE_DEVEP_OFFSET 1 +#define HW_USBCTRL_HWDEVICE_DEVEP_MASK (0x1f << 1) +#define HW_USBCTRL_HWDEVICE_DC (1 << 0) + +#define HW_USBCTRL_HWTXBUF_TXLCR (1 << 31) +#define HW_USBCTRL_HWTXBUF_TXCHANADD_OFFSET 16 +#define HW_USBCTRL_HWTXBUF_TXCHANADD_MASK (0xff << 16) +#define HW_USBCTRL_HWTXBUF_TXADD_OFFSET 8 +#define HW_USBCTRL_HWTXBUF_TXADD_MASK (0xff << 8) +#define HW_USBCTRL_HWTXBUF_TXBURST_OFFSET 0 +#define HW_USBCTRL_HWTXBUF_TXBURST_MASK 0xff + +#define HW_USBCTRL_HWRXBUF_RXADD_OFFSET 8 +#define HW_USBCTRL_HWRXBUF_RXADD_MASK (0xff << 8) +#define HW_USBCTRL_HWRXBUF_RXBURST_OFFSET 0 +#define HW_USBCTRL_HWRXBUF_RXBURST_MASK 0xff + +#define HW_USBCTRL_GPTIMERLD_GPTLD_OFFSET 0 +#define HW_USBCTRL_GPTIMERLD_GPTLD_MASK 0xffffff + +#define HW_USBCTRL_GPTIMERCTRL_GPTRUN (1 << 31) +#define HW_USBCTRL_GPTIMERCTRL_GPTRST (1 << 30) +#define HW_USBCTRL_GPTIMERCTRL_GPTMODE (1 << 24) +#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_OFFSET 0 +#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_MASK 0xffffff + +#define HW_USBCTRL_SBUSCFG_AHBBURST_OFFSET 0 +#define HW_USBCTRL_SBUSCFG_AHBBURST_MASK 0x7 +#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR 0x0 +#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR4 0x1 +#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR8 0x2 +#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR16 0x3 +#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR4 0x5 +#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR8 0x6 +#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR16 0x7 + +#endif /* __REGS_USB_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usbphy.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usbphy.h new file mode 100644 index 000000000..643feab74 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usbphy.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX28 USB PHY Register Definitions + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ + +#ifndef __REGS_USBPHY_H__ +#define __REGS_USBPHY_H__ + +struct mxs_usbphy_regs { + mxs_reg_32(hw_usbphy_pwd) + mxs_reg_32(hw_usbphy_tx) + mxs_reg_32(hw_usbphy_rx) + mxs_reg_32(hw_usbphy_ctrl) + mxs_reg_32(hw_usbphy_status) + mxs_reg_32(hw_usbphy_debug) + mxs_reg_32(hw_usbphy_debug0_status) + mxs_reg_32(hw_usbphy_debug1) + mxs_reg_32(hw_usbphy_version) + mxs_reg_32(hw_usbphy_ip) +}; + +#define USBPHY_PWD_RXPWDRX (1 << 20) +#define USBPHY_PWD_RXPWDDIFF (1 << 19) +#define USBPHY_PWD_RXPWD1PT1 (1 << 18) +#define USBPHY_PWD_RXPWDENV (1 << 17) +#define USBPHY_PWD_TXPWDV2I (1 << 12) +#define USBPHY_PWD_TXPWDIBIAS (1 << 11) +#define USBPHY_PWD_TXPWDFS (1 << 10) + +#define USBPHY_TX_USBPHY_TX_EDGECTRL_OFFSET 26 +#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x7 << 26) +#define USBPHY_TX_USBPHY_TX_SYNC_INVERT (1 << 25) +#define USBPHY_TX_USBPHY_TX_SYNC_MUX (1 << 24) +#define USBPHY_TX_TXENCAL45DP (1 << 21) +#define USBPHY_TX_TXCAL45DP_OFFSET 16 +#define USBPHY_TX_TXCAL45DP_MASK (0xf << 16) +#define USBPHY_TX_TXENCAL45DM (1 << 13) +#define USBPHY_TX_TXCAL45DM_OFFSET 8 +#define USBPHY_TX_TXCAL45DM_MASK (0xf << 8) +#define USBPHY_TX_D_CAL_OFFSET 0 +#define USBPHY_TX_D_CAL_MASK 0xf + +#define USBPHY_RX_RXDBYPASS (1 << 22) +#define USBPHY_RX_DISCONADJ_OFFSET 4 +#define USBPHY_RX_DISCONADJ_MASK (0x7 << 4) +#define USBPHY_RX_ENVADJ_OFFSET 0 +#define USBPHY_RX_ENVADJ_MASK 0x7 + +#define USBPHY_CTRL_SFTRST (1 << 31) +#define USBPHY_CTRL_CLKGATE (1 << 30) +#define USBPHY_CTRL_UTMI_SUSPENDM (1 << 29) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0 (1 << 28) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS (1 << 26) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE (1 << 25) +#define USBPHY_CTRL_FSDLL_RST_EN (1 << 24) +#define USBPHY_CTRL_ENVBUSCHG_WKUP (1 << 23) +#define USBPHY_CTRL_ENIDCHG_WKUP (1 << 22) +#define USBPHY_CTRL_ENDPDMCHG_WKUP (1 << 21) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD (1 << 20) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE (1 << 19) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL (1 << 18) +#define USBPHY_CTRL_WAKEUP_IRQ (1 << 17) +#define USBPHY_CTRL_ENIRQWAKEUP (1 << 16) +#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15) +#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14) +#define USBPHY_CTRL_DATA_ON_LRADC (1 << 13) +#define USBPHY_CTRL_DEVPLUGIN_IRQ (1 << 12) +#define USBPHY_CTRL_ENIRQDEVPLUGIN (1 << 11) +#define USBPHY_CTRL_RESUME_IRQ (1 << 10) +#define USBPHY_CTRL_ENIRQRESUMEDETECT (1 << 9) +#define USBPHY_CTRL_RESUMEIRQSTICKY (1 << 8) +#define USBPHY_CTRL_ENOTGIDDETECT (1 << 7) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY (1 << 5) +#define USBPHY_CTRL_ENDEVPLUGINDETECT (1 << 4) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ (1 << 3) +#define USBPHY_CTRL_ENIRQHOSTDISCON (1 << 2) +#define USBPHY_CTRL_ENHOSTDISCONDETECT (1 << 1) + +#define USBPHY_STATUS_RESUME_STATUS (1 << 10) +#define USBPHY_STATUS_OTGID_STATUS (1 << 8) +#define USBPHY_STATUS_DEVPLUGIN_STATUS (1 << 6) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS (1 << 3) + +#define USBPHY_DEBUG_CLKGATE (1 << 30) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG (1 << 29) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_OFFSET 25 +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0xf << 25) +#define USBPHY_DEBUG_ENSQUELCHRESET (1 << 24) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_OFFSET 16 +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1f << 16) +#define USBPHY_DEBUG_ENTX2RXCOUNT (1 << 12) +#define USBPHY_DEBUG_TX2RXCOUNT_OFFSET 8 +#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xf << 8) +#define USBPHY_DEBUG_ENHSTPULLDOWN_OFFSET 4 +#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x3 << 4) +#define USBPHY_DEBUG_HSTPULLDOWN_OFFSET 2 +#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0x3 << 2) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD (1 << 1) +#define USBPHY_DEBUG_OTGIDPIDLOCK (1 << 0) + +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_OFFSET 26 +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0x3f << 26) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_OFFSET 16 +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_MASK (0x3ff << 16) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_OFFSET 0 +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_MASK 0xffff + +#define USBPHY_DEBUG1_ENTAILADJVD_OFFSET 13 +#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x3 << 13) +#define USBPHY_DEBUG1_ENTX2TX (1 << 12) +#define USBPHY_DEBUG1_DBG_ADDRESS_OFFSET 0 +#define USBPHY_DEBUG1_DBG_ADDRESS_MASK 0xf + +#define USBPHY_VERSION_MAJOR_MASK (0xff << 24) +#define USBPHY_VERSION_MAJOR_OFFSET 24 +#define USBPHY_VERSION_MINOR_MASK (0xff << 16) +#define USBPHY_VERSION_MINOR_OFFSET 16 +#define USBPHY_VERSION_STEP_MASK 0xffff +#define USBPHY_VERSION_STEP_OFFSET 0 + +#define USBPHY_IP_DIV_SEL_OFFSET 23 +#define USBPHY_IP_DIV_SEL_MASK (0x3 << 23) +#define USBPHY_IP_LFR_SEL_OFFSET 21 +#define USBPHY_IP_LFR_SEL_MASK (0x3 << 21) +#define USBPHY_IP_CP_SEL_OFFSET 19 +#define USBPHY_IP_CP_SEL_MASK (0x3 << 19) +#define USBPHY_IP_TSTI_TX_DP (1 << 18) +#define USBPHY_IP_TSTI_TX_DM (1 << 17) +#define USBPHY_IP_ANALOG_TESTMODE (1 << 16) +#define USBPHY_IP_EN_USB_CLKS (1 << 2) +#define USBPHY_IP_PLL_LOCKED (1 << 1) +#define USBPHY_IP_PLL_POWER (1 << 0) + +#endif /* __REGS_USBPHY_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-mxs/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-mxs/sys_proto.h new file mode 100644 index 000000000..20ee863ac --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX23/i.MX28 specific functions + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ + +#ifndef __MXS_SYS_PROTO_H__ +#define __MXS_SYS_PROTO_H__ + +#include + +int mxsmmc_initialize(struct bd_info *bis, int id, int (*wp)(int), + int (*cd)(int)); + +#ifdef CONFIG_SPL_BUILD + +#if defined(CONFIG_MX23) +#include +#elif defined(CONFIG_MX28) +#include +#endif + +void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, + const iomux_cfg_t *iomux_setup, + const unsigned int iomux_size); + +void mxs_power_switch_dcdc_clocksource(uint32_t freqsel); +#endif + +struct mxs_pair { + uint8_t boot_pads; + uint8_t boot_mask; + const char *mode; +}; + +static const struct mxs_pair mxs_boot_modes[] = { +#if defined(CONFIG_MX23) + { 0x00, 0x0f, "USB" }, + { 0x01, 0x1f, "I2C, master" }, + { 0x02, 0x1f, "SSP SPI #1, master, NOR" }, + { 0x03, 0x1f, "SSP SPI #2, master, NOR" }, + { 0x04, 0x1f, "NAND" }, + { 0x06, 0x1f, "JTAG" }, + { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" }, + { 0x09, 0x1f, "SSP SD/MMC #0" }, + { 0x0a, 0x1f, "SSP SD/MMC #1" }, + { 0x00, 0x00, "Reserved/Unknown/Wrong" }, +#elif defined(CONFIG_MX28) + { 0x00, 0x0f, "USB #0" }, + { 0x01, 0x1f, "I2C #0, master, 3V3" }, + { 0x11, 0x1f, "I2C #0, master, 1V8" }, + { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" }, + { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" }, + { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" }, + { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" }, + { 0x04, 0x1f, "NAND, 3V3" }, + { 0x14, 0x1f, "NAND, 1V8" }, + { 0x06, 0x1f, "JTAG" }, + { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" }, + { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" }, + { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" }, + { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" }, + { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" }, + { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" }, + { 0x00, 0x00, "Reserved/Unknown/Wrong" }, +#endif +}; + +#define MXS_BM_USB 0x00 +#define MXS_BM_I2C_MASTER_3V3 0x01 +#define MXS_BM_I2C_MASTER_1V8 0x11 +#define MXS_BM_SPI2_MASTER_3V3_NOR 0x02 +#define MXS_BM_SPI2_MASTER_1V8_NOR 0x12 +#define MXS_BM_SPI3_MASTER_3V3_NOR 0x03 +#define MXS_BM_SPI3_MASTER_1V8_NOR 0x13 +#define MXS_BM_NAND_3V3 0x04 +#define MXS_BM_NAND_1V8 0x14 +#define MXS_BM_JTAG 0x06 +#define MXS_BM_SPI3_MASTER_3V3_EEPROM 0x08 +#define MXS_BM_SPI3_MASTER_1V8_EEPROM 0x18 +#define MXS_BM_SDMMC0_3V3 0x09 +#define MXS_BM_SDMMC0_1V8 0x19 +#define MXS_BM_SDMMC1_3V3 0x0a +#define MXS_BM_SDMMC1_1V8 0x1a + +#define MXS_SPL_DATA ((struct mxs_spl_data *)(CONFIG_SYS_TEXT_BASE - 0x200)) + +struct mxs_spl_data { + uint8_t boot_mode_idx; + uint32_t mem_dram_size; +}; + +int mxs_dram_init(void); + +#endif /* __SYS_PROTO_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx/board.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx/board.h new file mode 100644 index 000000000..c9fc3993f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx/board.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +#define MAX_LMAC_PER_BGX 4 +#define LMAC_CNT MAX_LMAC_PER_BGX + +#if defined(CONFIG_TARGET_OCTEONTX_81XX) + +/** Maximum number of BGX interfaces per CPU node */ +#define MAX_BGX_PER_NODE 3 +#define OCTEONTX_XCV /* RGMII Interface */ + +#elif defined(CONFIG_TARGET_OCTEONTX_83XX) + +/** Maximum number of BGX interfaces per CPU node */ +#define MAX_BGX_PER_NODE 4 + +#endif + +/** Reg offsets */ +#define RST_BOOT 0x87E006001600ULL + +/** Structure definitions */ + +/** + * Register (RSL) rst_boot + * + * RST Boot Register This register is not accessible through ROM scripts; + * see SCR_WRITE32_S[ADDR]. + */ +union rst_boot { + u64 u; + struct rst_boot_s { + u64 rboot_pin : 1; + u64 rboot : 1; + u64 reserved_2_32 : 31; + u64 pnr_mul : 6; + u64 reserved_39 : 1; + u64 c_mul : 7; + u64 reserved_47_52 : 6; + u64 gpio_ejtag : 1; + u64 mcp_jtagdis : 1; + u64 dis_scan : 1; + u64 dis_huk : 1; + u64 vrm_err : 1; + u64 jt_tstmode : 1; + u64 ckill_ppdis : 1; + u64 trusted_mode : 1; + u64 reserved_61_62 : 2; + u64 chipkill : 1; + } s; + struct rst_boot_cn81xx { + u64 rboot_pin : 1; + u64 rboot : 1; + u64 lboot : 10; + u64 lboot_ext23 : 6; + u64 lboot_ext45 : 6; + u64 lboot_jtg : 1; + u64 lboot_ckill : 1; + u64 reserved_26_29 : 4; + u64 lboot_oci : 3; + u64 pnr_mul : 6; + u64 reserved_39 : 1; + u64 c_mul : 7; + u64 reserved_47_54 : 8; + u64 dis_scan : 1; + u64 dis_huk : 1; + u64 vrm_err : 1; + u64 jt_tstmode : 1; + u64 ckill_ppdis : 1; + u64 trusted_mode : 1; + u64 ejtagdis : 1; + u64 jtcsrdis : 1; + u64 chipkill : 1; + } cn81xx; + struct rst_boot_cn83xx { + u64 rboot_pin : 1; + u64 rboot : 1; + u64 lboot : 10; + u64 lboot_ext23 : 6; + u64 lboot_ext45 : 6; + u64 lboot_jtg : 1; + u64 lboot_ckill : 1; + u64 lboot_pf_flr : 4; + u64 lboot_oci : 3; + u64 pnr_mul : 6; + u64 reserved_39 : 1; + u64 c_mul : 7; + u64 reserved_47_54 : 8; + u64 dis_scan : 1; + u64 dis_huk : 1; + u64 vrm_err : 1; + u64 jt_tstmode : 1; + u64 ckill_ppdis : 1; + u64 trusted_mode : 1; + u64 ejtagdis : 1; + u64 jtcsrdis : 1; + u64 chipkill : 1; + } cn83xx; +}; + +extern unsigned long fdt_base_addr; + +/** Function definitions */ +void mem_map_fill(void); +int octeontx_board_has_pmp(void); +const char *fdt_get_board_model(void); +const char *fdt_get_board_serial(void); +const char *fdt_get_board_revision(void); +void fdt_parse_phy_info(void); +void fdt_board_get_ethaddr(int bgx, int lmac, unsigned char *eth); +void bgx_set_board_info(int bgx_id, int *mdio_bus, int *phy_addr, + bool *autoneg_dis, bool *lmac_reg, bool *lmac_enable); +#endif /* __BOARD_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx/clock.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx/clock.h new file mode 100644 index 000000000..7bf600a1f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx/clock.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#ifndef __CLOCK_H__ +#define __CLOCK_H__ + +/** System PLL reference clock */ +#define PLL_REF_CLK 50000000 /* 50 MHz */ +#define NS_PER_REF_CLK_TICK (1000000000 / PLL_REF_CLK) + +/** + * Returns the I/O clock speed in Hz + */ +u64 octeontx_get_io_clock(void); + +/** + * Returns the core clock speed in Hz + */ +u64 octeontx_get_core_clock(void); + +#endif /* __CLOCK_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx/csrs/csrs-mio_emm.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx/csrs/csrs-mio_emm.h new file mode 100644 index 000000000..a5a474083 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx/csrs/csrs-mio_emm.h @@ -0,0 +1,1193 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Marvell International Ltd. + * + * https://spdx.org/licenses + */ +#ifndef __CSRS_MIO_EMM_H__ +#define __CSRS_MIO_EMM_H__ + +/** + * @file + * + * Configuration and status register (CSR) address and type definitions for + * MIO_EMM. + * + * This file is auto generated. Do not edit. + * + */ + +/** + * Enumeration mio_emm_bar_e + * + * eMMC Base Address Register Enumeration Enumerates the base address + * registers. + */ +#define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN8 (0x87e009000000ll) +#define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN8_SIZE 0x800000ull +#define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN9 (0x87e009000000ll) +#define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN9_SIZE 0x10000ull +#define MIO_EMM_BAR_E_MIO_EMM_PF_BAR4 (0x87e009f00000ll) +#define MIO_EMM_BAR_E_MIO_EMM_PF_BAR4_SIZE 0x100000ull + +/** + * Enumeration mio_emm_int_vec_e + * + * eMMC MSI-X Vector Enumeration Enumerates the MSI-X interrupt vectors. + */ +#define MIO_EMM_INT_VEC_E_DMA_INT_DONE (8) +#define MIO_EMM_INT_VEC_E_DMA_INT_FIFO (7) +#define MIO_EMM_INT_VEC_E_EMM_BUF_DONE (0) +#define MIO_EMM_INT_VEC_E_EMM_CMD_DONE (1) +#define MIO_EMM_INT_VEC_E_EMM_CMD_ERR (3) +#define MIO_EMM_INT_VEC_E_EMM_DMA_DONE (2) +#define MIO_EMM_INT_VEC_E_EMM_DMA_ERR (4) +#define MIO_EMM_INT_VEC_E_EMM_SWITCH_DONE (5) +#define MIO_EMM_INT_VEC_E_EMM_SWITCH_ERR (6) +#define MIO_EMM_INT_VEC_E_NCB_FLT (9) +#define MIO_EMM_INT_VEC_E_NCB_RAS (0xa) + +/** + * Register (RSL) mio_emm_access_wdog + * + * eMMC Access Watchdog Register + */ +union mio_emm_access_wdog { + u64 u; + struct mio_emm_access_wdog_s { + u64 clk_cnt : 32; + u64 reserved_32_63 : 32; + } s; + /* struct mio_emm_access_wdog_s cn; */ +}; + +static inline u64 MIO_EMM_ACCESS_WDOG(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_ACCESS_WDOG(void) +{ + return 0x20f0; +} + +/** + * Register (RSL) mio_emm_buf_dat + * + * eMMC Data Buffer Access Register + */ +union mio_emm_buf_dat { + u64 u; + struct mio_emm_buf_dat_s { + u64 dat : 64; + } s; + /* struct mio_emm_buf_dat_s cn; */ +}; + +static inline u64 MIO_EMM_BUF_DAT(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_BUF_DAT(void) +{ + return 0x20e8; +} + +/** + * Register (RSL) mio_emm_buf_idx + * + * eMMC Data Buffer Address Register + */ +union mio_emm_buf_idx { + u64 u; + struct mio_emm_buf_idx_s { + u64 offset : 6; + u64 buf_num : 1; + u64 reserved_7_15 : 9; + u64 inc : 1; + u64 reserved_17_63 : 47; + } s; + /* struct mio_emm_buf_idx_s cn; */ +}; + +static inline u64 MIO_EMM_BUF_IDX(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_BUF_IDX(void) +{ + return 0x20e0; +} + +/** + * Register (RSL) mio_emm_calb + * + * eMMC Calbration Register This register initiates delay line + * characterization. + */ +union mio_emm_calb { + u64 u; + struct mio_emm_calb_s { + u64 start : 1; + u64 reserved_1_63 : 63; + } s; + /* struct mio_emm_calb_s cn; */ +}; + +static inline u64 MIO_EMM_CALB(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_CALB(void) +{ + return 0x20c0; +} + +/** + * Register (RSL) mio_emm_cfg + * + * eMMC Configuration Register + */ +union mio_emm_cfg { + u64 u; + struct mio_emm_cfg_s { + u64 bus_ena : 4; + u64 reserved_4_63 : 60; + } s; + /* struct mio_emm_cfg_s cn; */ +}; + +static inline u64 MIO_EMM_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_CFG(void) +{ + return 0x2000; +} + +/** + * Register (RSL) mio_emm_cmd + * + * eMMC Command Register + */ +union mio_emm_cmd { + u64 u; + struct mio_emm_cmd_s { + u64 arg : 32; + u64 cmd_idx : 6; + u64 rtype_xor : 3; + u64 ctype_xor : 2; + u64 reserved_43_48 : 6; + u64 offset : 6; + u64 dbuf : 1; + u64 reserved_56_58 : 3; + u64 cmd_val : 1; + u64 bus_id : 2; + u64 skip_busy : 1; + u64 reserved_63 : 1; + } s; + /* struct mio_emm_cmd_s cn; */ +}; + +static inline u64 MIO_EMM_CMD(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_CMD(void) +{ + return 0x2058; +} + +/** + * Register (RSL) mio_emm_comp + * + * eMMC Compensation Register + */ +union mio_emm_comp { + u64 u; + struct mio_emm_comp_s { + u64 nctl : 3; + u64 reserved_3_7 : 5; + u64 pctl : 3; + u64 reserved_11_63 : 53; + } s; + /* struct mio_emm_comp_s cn; */ +}; + +static inline u64 MIO_EMM_COMP(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_COMP(void) +{ + return 0x2040; +} + +/** + * Register (RSL) mio_emm_debug + * + * eMMC Debug Register + */ +union mio_emm_debug { + u64 u; + struct mio_emm_debug_s { + u64 clk_on : 1; + u64 reserved_1_7 : 7; + u64 cmd_sm : 4; + u64 data_sm : 4; + u64 dma_sm : 4; + u64 emmc_clk_disable : 1; + u64 rdsync_rst : 1; + u64 reserved_22_63 : 42; + } s; + struct mio_emm_debug_cn96xxp1 { + u64 clk_on : 1; + u64 reserved_1_7 : 7; + u64 cmd_sm : 4; + u64 data_sm : 4; + u64 dma_sm : 4; + u64 reserved_20_63 : 44; + } cn96xxp1; + /* struct mio_emm_debug_s cn96xxp3; */ + /* struct mio_emm_debug_cn96xxp1 cnf95xx; */ +}; + +static inline u64 MIO_EMM_DEBUG(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DEBUG(void) +{ + return 0x20f8; +} + +/** + * Register (RSL) mio_emm_dma + * + * eMMC External DMA Configuration Register + */ +union mio_emm_dma { + u64 u; + struct mio_emm_dma_s { + u64 card_addr : 32; + u64 block_cnt : 16; + u64 multi : 1; + u64 rw : 1; + u64 rel_wr : 1; + u64 thres : 6; + u64 dat_null : 1; + u64 sector : 1; + u64 dma_val : 1; + u64 bus_id : 2; + u64 skip_busy : 1; + u64 extra_args : 1; + } s; + struct mio_emm_dma_cn8 { + u64 card_addr : 32; + u64 block_cnt : 16; + u64 multi : 1; + u64 rw : 1; + u64 rel_wr : 1; + u64 thres : 6; + u64 dat_null : 1; + u64 sector : 1; + u64 dma_val : 1; + u64 bus_id : 2; + u64 skip_busy : 1; + u64 reserved_63 : 1; + } cn8; + struct mio_emm_dma_cn9 { + u64 card_addr : 32; + u64 block_cnt : 16; + u64 multi : 1; + u64 rw : 1; + u64 reserved_50 : 1; + u64 thres : 6; + u64 dat_null : 1; + u64 sector : 1; + u64 dma_val : 1; + u64 bus_id : 2; + u64 skip_busy : 1; + u64 extra_args : 1; + } cn9; +}; + +static inline u64 MIO_EMM_DMA(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA(void) +{ + return 0x2050; +} + +/** + * Register (RSL) mio_emm_dma_adr + * + * eMMC DMA Address Register This register sets the address for eMMC/SD + * flash transfers to/from memory. Sixty-four-bit operations must be used + * to access this register. This register is updated by the DMA hardware + * and can be reloaded by the values placed in the MIO_EMM_DMA_FIFO_ADR. + */ +union mio_emm_dma_adr { + u64 u; + struct mio_emm_dma_adr_s { + u64 adr : 53; + u64 reserved_53_63 : 11; + } s; + struct mio_emm_dma_adr_cn8 { + u64 adr : 49; + u64 reserved_49_63 : 15; + } cn8; + /* struct mio_emm_dma_adr_s cn9; */ +}; + +static inline u64 MIO_EMM_DMA_ADR(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_ADR(void) +{ + return 0x188; +} + +/** + * Register (RSL) mio_emm_dma_arg + * + * eMMC External DMA Extra Arguments Register + */ +union mio_emm_dma_arg { + u64 u; + struct mio_emm_dma_arg_s { + u64 cmd23_args : 8; + u64 force_pgm : 1; + u64 context_id : 4; + u64 tag_req : 1; + u64 pack_cmd : 1; + u64 rel_wr : 1; + u64 alt_cmd : 6; + u64 skip_blk_cmd : 1; + u64 reserved_23_31 : 9; + u64 alt_cmd_arg : 32; + } s; + /* struct mio_emm_dma_arg_s cn; */ +}; + +static inline u64 MIO_EMM_DMA_ARG(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_ARG(void) +{ + return 0x2090; +} + +/** + * Register (RSL) mio_emm_dma_cfg + * + * eMMC DMA Configuration Register This register controls the internal + * DMA engine used with the eMMC/SD flash controller. Sixty- four-bit + * operations must be used to access this register. This register is + * updated by the hardware DMA engine and can also be reloaded by writes + * to the MIO_EMM_DMA_FIFO_CMD register. + */ +union mio_emm_dma_cfg { + u64 u; + struct mio_emm_dma_cfg_s { + u64 reserved_0_35 : 36; + u64 size : 20; + u64 endian : 1; + u64 swap8 : 1; + u64 swap16 : 1; + u64 swap32 : 1; + u64 reserved_60 : 1; + u64 clr : 1; + u64 rw : 1; + u64 en : 1; + } s; + /* struct mio_emm_dma_cfg_s cn; */ +}; + +static inline u64 MIO_EMM_DMA_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_CFG(void) +{ + return 0x180; +} + +/** + * Register (RSL) mio_emm_dma_fifo_adr + * + * eMMC Internal DMA FIFO Address Register This register specifies the + * internal address that is loaded into the eMMC internal DMA FIFO. The + * FIFO is used to queue up operations for the + * MIO_EMM_DMA_CFG/MIO_EMM_DMA_ADR when the DMA completes successfully. + */ +union mio_emm_dma_fifo_adr { + u64 u; + struct mio_emm_dma_fifo_adr_s { + u64 reserved_0_2 : 3; + u64 adr : 50; + u64 reserved_53_63 : 11; + } s; + struct mio_emm_dma_fifo_adr_cn8 { + u64 reserved_0_2 : 3; + u64 adr : 46; + u64 reserved_49_63 : 15; + } cn8; + /* struct mio_emm_dma_fifo_adr_s cn9; */ +}; + +static inline u64 MIO_EMM_DMA_FIFO_ADR(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_FIFO_ADR(void) +{ + return 0x170; +} + +/** + * Register (RSL) mio_emm_dma_fifo_cfg + * + * eMMC Internal DMA FIFO Configuration Register This register controls + * DMA FIFO operations. + */ +union mio_emm_dma_fifo_cfg { + u64 u; + struct mio_emm_dma_fifo_cfg_s { + u64 count : 5; + u64 reserved_5_7 : 3; + u64 int_lvl : 5; + u64 reserved_13_15 : 3; + u64 clr : 1; + u64 reserved_17_63 : 47; + } s; + /* struct mio_emm_dma_fifo_cfg_s cn; */ +}; + +static inline u64 MIO_EMM_DMA_FIFO_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_FIFO_CFG(void) +{ + return 0x160; +} + +/** + * Register (RSL) mio_emm_dma_fifo_cmd + * + * eMMC Internal DMA FIFO Command Register This register specifies a + * command that is loaded into the eMMC internal DMA FIFO. The FIFO is + * used to queue up operations for the MIO_EMM_DMA_CFG/MIO_EMM_DMA_ADR + * when the DMA completes successfully. Writes to this register store + * both the MIO_EMM_DMA_FIFO_CMD and the MIO_EMM_DMA_FIFO_ADR contents + * into the FIFO and increment the MIO_EMM_DMA_FIFO_CFG[COUNT] field. + * Note: This register has a similar format to MIO_EMM_DMA_CFG with the + * exception that the EN and CLR fields are absent. These are supported + * in MIO_EMM_DMA_FIFO_CFG. + */ +union mio_emm_dma_fifo_cmd { + u64 u; + struct mio_emm_dma_fifo_cmd_s { + u64 reserved_0_35 : 36; + u64 size : 20; + u64 endian : 1; + u64 swap8 : 1; + u64 swap16 : 1; + u64 swap32 : 1; + u64 intdis : 1; + u64 reserved_61 : 1; + u64 rw : 1; + u64 reserved_63 : 1; + } s; + /* struct mio_emm_dma_fifo_cmd_s cn; */ +}; + +static inline u64 MIO_EMM_DMA_FIFO_CMD(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_FIFO_CMD(void) +{ + return 0x178; +} + +/** + * Register (RSL) mio_emm_dma_int + * + * eMMC DMA Interrupt Register Sixty-four-bit operations must be used to + * access this register. + */ +union mio_emm_dma_int { + u64 u; + struct mio_emm_dma_int_s { + u64 done : 1; + u64 fifo : 1; + u64 reserved_2_63 : 62; + } s; + /* struct mio_emm_dma_int_s cn; */ +}; + +static inline u64 MIO_EMM_DMA_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_INT(void) +{ + return 0x190; +} + +/** + * Register (RSL) mio_emm_dma_int_ena_w1c + * + * eMMC DMA Interrupt Enable Clear Register This register clears + * interrupt enable bits. + */ +union mio_emm_dma_int_ena_w1c { + u64 u; + struct mio_emm_dma_int_ena_w1c_s { + u64 done : 1; + u64 fifo : 1; + u64 reserved_2_63 : 62; + } s; + /* struct mio_emm_dma_int_ena_w1c_s cn; */ +}; + +static inline u64 MIO_EMM_DMA_INT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_INT_ENA_W1C(void) +{ + return 0x1a8; +} + +/** + * Register (RSL) mio_emm_dma_int_ena_w1s + * + * eMMC DMA Interrupt Enable Set Register This register sets interrupt + * enable bits. + */ +union mio_emm_dma_int_ena_w1s { + u64 u; + struct mio_emm_dma_int_ena_w1s_s { + u64 done : 1; + u64 fifo : 1; + u64 reserved_2_63 : 62; + } s; + /* struct mio_emm_dma_int_ena_w1s_s cn; */ +}; + +static inline u64 MIO_EMM_DMA_INT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_INT_ENA_W1S(void) +{ + return 0x1a0; +} + +/** + * Register (RSL) mio_emm_dma_int_w1s + * + * eMMC DMA Interrupt Set Register This register sets interrupt bits. + */ +union mio_emm_dma_int_w1s { + u64 u; + struct mio_emm_dma_int_w1s_s { + u64 done : 1; + u64 fifo : 1; + u64 reserved_2_63 : 62; + } s; + /* struct mio_emm_dma_int_w1s_s cn; */ +}; + +static inline u64 MIO_EMM_DMA_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_INT_W1S(void) +{ + return 0x198; +} + +/** + * Register (RSL) mio_emm_int + * + * eMMC Interrupt Register + */ +union mio_emm_int { + u64 u; + struct mio_emm_int_s { + u64 buf_done : 1; + u64 cmd_done : 1; + u64 dma_done : 1; + u64 cmd_err : 1; + u64 dma_err : 1; + u64 switch_done : 1; + u64 switch_err : 1; + u64 ncb_flt : 1; + u64 ncb_ras : 1; + u64 reserved_9_63 : 55; + } s; + struct mio_emm_int_cn8 { + u64 buf_done : 1; + u64 cmd_done : 1; + u64 dma_done : 1; + u64 cmd_err : 1; + u64 dma_err : 1; + u64 switch_done : 1; + u64 switch_err : 1; + u64 reserved_7_63 : 57; + } cn8; + /* struct mio_emm_int_s cn9; */ +}; + +static inline u64 MIO_EMM_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_INT(void) +{ + return 0x2078; +} + +/** + * Register (RSL) mio_emm_int_ena_w1c + * + * eMMC Interrupt Enable Clear Register This register clears interrupt + * enable bits. + */ +union mio_emm_int_ena_w1c { + u64 u; + struct mio_emm_int_ena_w1c_s { + u64 buf_done : 1; + u64 cmd_done : 1; + u64 dma_done : 1; + u64 cmd_err : 1; + u64 dma_err : 1; + u64 switch_done : 1; + u64 switch_err : 1; + u64 ncb_flt : 1; + u64 ncb_ras : 1; + u64 reserved_9_63 : 55; + } s; + struct mio_emm_int_ena_w1c_cn8 { + u64 buf_done : 1; + u64 cmd_done : 1; + u64 dma_done : 1; + u64 cmd_err : 1; + u64 dma_err : 1; + u64 switch_done : 1; + u64 switch_err : 1; + u64 reserved_7_63 : 57; + } cn8; + /* struct mio_emm_int_ena_w1c_s cn9; */ +}; + +static inline u64 MIO_EMM_INT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_INT_ENA_W1C(void) +{ + return 0x20b8; +} + +/** + * Register (RSL) mio_emm_int_ena_w1s + * + * eMMC Interrupt Enable Set Register This register sets interrupt enable + * bits. + */ +union mio_emm_int_ena_w1s { + u64 u; + struct mio_emm_int_ena_w1s_s { + u64 buf_done : 1; + u64 cmd_done : 1; + u64 dma_done : 1; + u64 cmd_err : 1; + u64 dma_err : 1; + u64 switch_done : 1; + u64 switch_err : 1; + u64 ncb_flt : 1; + u64 ncb_ras : 1; + u64 reserved_9_63 : 55; + } s; + struct mio_emm_int_ena_w1s_cn8 { + u64 buf_done : 1; + u64 cmd_done : 1; + u64 dma_done : 1; + u64 cmd_err : 1; + u64 dma_err : 1; + u64 switch_done : 1; + u64 switch_err : 1; + u64 reserved_7_63 : 57; + } cn8; + /* struct mio_emm_int_ena_w1s_s cn9; */ +}; + +static inline u64 MIO_EMM_INT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_INT_ENA_W1S(void) +{ + return 0x20b0; +} + +/** + * Register (RSL) mio_emm_int_w1s + * + * eMMC Interrupt Set Register This register sets interrupt bits. + */ +union mio_emm_int_w1s { + u64 u; + struct mio_emm_int_w1s_s { + u64 buf_done : 1; + u64 cmd_done : 1; + u64 dma_done : 1; + u64 cmd_err : 1; + u64 dma_err : 1; + u64 switch_done : 1; + u64 switch_err : 1; + u64 ncb_flt : 1; + u64 ncb_ras : 1; + u64 reserved_9_63 : 55; + } s; + struct mio_emm_int_w1s_cn8 { + u64 buf_done : 1; + u64 cmd_done : 1; + u64 dma_done : 1; + u64 cmd_err : 1; + u64 dma_err : 1; + u64 switch_done : 1; + u64 switch_err : 1; + u64 reserved_7_63 : 57; + } cn8; + /* struct mio_emm_int_w1s_s cn9; */ +}; + +static inline u64 MIO_EMM_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_INT_W1S(void) +{ + return 0x2080; +} + +/** + * Register (RSL) mio_emm_io_ctl + * + * eMMC I/O Control Register + */ +union mio_emm_io_ctl { + u64 u; + struct mio_emm_io_ctl_s { + u64 slew : 1; + u64 reserved_1 : 1; + u64 drive : 2; + u64 reserved_4_63 : 60; + } s; + /* struct mio_emm_io_ctl_s cn; */ +}; + +static inline u64 MIO_EMM_IO_CTL(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_IO_CTL(void) +{ + return 0x2040; +} + +/** + * Register (RSL) mio_emm_mode# + * + * eMMC Operating Mode Register + */ +union mio_emm_modex { + u64 u; + struct mio_emm_modex_s { + u64 clk_lo : 16; + u64 clk_hi : 16; + u64 power_class : 4; + u64 clk_swap : 1; + u64 reserved_37_39 : 3; + u64 bus_width : 3; + u64 reserved_43_47 : 5; + u64 hs_timing : 1; + u64 hs200_timing : 1; + u64 hs400_timing : 1; + u64 reserved_51_63 : 13; + } s; + struct mio_emm_modex_cn8 { + u64 clk_lo : 16; + u64 clk_hi : 16; + u64 power_class : 4; + u64 reserved_36_39 : 4; + u64 bus_width : 3; + u64 reserved_43_47 : 5; + u64 hs_timing : 1; + u64 reserved_49_63 : 15; + } cn8; + struct mio_emm_modex_cn96xxp1 { + u64 clk_lo : 16; + u64 clk_hi : 16; + u64 power_class : 4; + u64 reserved_36_39 : 4; + u64 bus_width : 3; + u64 reserved_43_47 : 5; + u64 hs_timing : 1; + u64 hs200_timing : 1; + u64 hs400_timing : 1; + u64 reserved_51_63 : 13; + } cn96xxp1; + /* struct mio_emm_modex_s cn96xxp3; */ + /* struct mio_emm_modex_s cnf95xx; */ +}; + +static inline u64 MIO_EMM_MODEX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_MODEX(u64 a) +{ + return 0x2008 + 8 * a; +} + +/** + * Register (RSL) mio_emm_msix_pba# + * + * eMMC MSI-X Pending Bit Array Registers This register is the MSI-X PBA + * table; the bit number is indexed by the MIO_EMM_INT_VEC_E enumeration. + */ +union mio_emm_msix_pbax { + u64 u; + struct mio_emm_msix_pbax_s { + u64 pend : 64; + } s; + /* struct mio_emm_msix_pbax_s cn; */ +}; + +static inline u64 MIO_EMM_MSIX_PBAX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_MSIX_PBAX(u64 a) +{ + return 0xf0000 + 8 * a; +} + +/** + * Register (RSL) mio_emm_msix_vec#_addr + * + * eMMC MSI-X Vector-Table Address Register This register is the MSI-X + * vector table, indexed by the MIO_EMM_INT_VEC_E enumeration. + */ +union mio_emm_msix_vecx_addr { + u64 u; + struct mio_emm_msix_vecx_addr_s { + u64 secvec : 1; + u64 reserved_1 : 1; + u64 addr : 51; + u64 reserved_53_63 : 11; + } s; + struct mio_emm_msix_vecx_addr_cn8 { + u64 secvec : 1; + u64 reserved_1 : 1; + u64 addr : 47; + u64 reserved_49_63 : 15; + } cn8; + /* struct mio_emm_msix_vecx_addr_s cn9; */ +}; + +static inline u64 MIO_EMM_MSIX_VECX_ADDR(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_MSIX_VECX_ADDR(u64 a) +{ + return 0 + 0x10 * a; +} + +/** + * Register (RSL) mio_emm_msix_vec#_ctl + * + * eMMC MSI-X Vector-Table Control and Data Register This register is the + * MSI-X vector table, indexed by the MIO_EMM_INT_VEC_E enumeration. + */ +union mio_emm_msix_vecx_ctl { + u64 u; + struct mio_emm_msix_vecx_ctl_s { + u64 data : 32; + u64 mask : 1; + u64 reserved_33_63 : 31; + } s; + struct mio_emm_msix_vecx_ctl_cn8 { + u64 data : 20; + u64 reserved_20_31 : 12; + u64 mask : 1; + u64 reserved_33_63 : 31; + } cn8; + /* struct mio_emm_msix_vecx_ctl_s cn9; */ +}; + +static inline u64 MIO_EMM_MSIX_VECX_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_MSIX_VECX_CTL(u64 a) +{ + return 8 + 0x10 * a; +} + +/** + * Register (RSL) mio_emm_rca + * + * eMMC Relative Card Address Register + */ +union mio_emm_rca { + u64 u; + struct mio_emm_rca_s { + u64 card_rca : 16; + u64 reserved_16_63 : 48; + } s; + /* struct mio_emm_rca_s cn; */ +}; + +static inline u64 MIO_EMM_RCA(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_RCA(void) +{ + return 0x20a0; +} + +/** + * Register (RSL) mio_emm_rsp_hi + * + * eMMC Response Data High Register + */ +union mio_emm_rsp_hi { + u64 u; + struct mio_emm_rsp_hi_s { + u64 dat : 64; + } s; + /* struct mio_emm_rsp_hi_s cn; */ +}; + +static inline u64 MIO_EMM_RSP_HI(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_RSP_HI(void) +{ + return 0x2070; +} + +/** + * Register (RSL) mio_emm_rsp_lo + * + * eMMC Response Data Low Register + */ +union mio_emm_rsp_lo { + u64 u; + struct mio_emm_rsp_lo_s { + u64 dat : 64; + } s; + /* struct mio_emm_rsp_lo_s cn; */ +}; + +static inline u64 MIO_EMM_RSP_LO(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_RSP_LO(void) +{ + return 0x2068; +} + +/** + * Register (RSL) mio_emm_rsp_sts + * + * eMMC Response Status Register + */ +union mio_emm_rsp_sts { + u64 u; + struct mio_emm_rsp_sts_s { + u64 cmd_done : 1; + u64 cmd_idx : 6; + u64 cmd_type : 2; + u64 rsp_type : 3; + u64 rsp_val : 1; + u64 rsp_bad_sts : 1; + u64 rsp_crc_err : 1; + u64 rsp_timeout : 1; + u64 stp_val : 1; + u64 stp_bad_sts : 1; + u64 stp_crc_err : 1; + u64 stp_timeout : 1; + u64 rsp_busybit : 1; + u64 blk_crc_err : 1; + u64 blk_timeout : 1; + u64 dbuf : 1; + u64 reserved_24_27 : 4; + u64 dbuf_err : 1; + u64 reserved_29_54 : 26; + u64 acc_timeout : 1; + u64 dma_pend : 1; + u64 dma_val : 1; + u64 switch_val : 1; + u64 cmd_val : 1; + u64 bus_id : 2; + u64 reserved_62_63 : 2; + } s; + /* struct mio_emm_rsp_sts_s cn; */ +}; + +static inline u64 MIO_EMM_RSP_STS(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_RSP_STS(void) +{ + return 0x2060; +} + +/** + * Register (RSL) mio_emm_sample + * + * eMMC Sampling Register + */ +union mio_emm_sample { + u64 u; + struct mio_emm_sample_s { + u64 dat_cnt : 10; + u64 reserved_10_15 : 6; + u64 cmd_cnt : 10; + u64 reserved_26_63 : 38; + } s; + /* struct mio_emm_sample_s cn; */ +}; + +static inline u64 MIO_EMM_SAMPLE(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_SAMPLE(void) +{ + return 0x2090; +} + +/** + * Register (RSL) mio_emm_sts_mask + * + * eMMC Status Mask Register + */ +union mio_emm_sts_mask { + u64 u; + struct mio_emm_sts_mask_s { + u64 sts_msk : 32; + u64 reserved_32_63 : 32; + } s; + /* struct mio_emm_sts_mask_s cn; */ +}; + +static inline u64 MIO_EMM_STS_MASK(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_STS_MASK(void) +{ + return 0x2098; +} + +/** + * Register (RSL) mio_emm_switch + * + * eMMC Operating Mode Switch Register This register allows software to + * change eMMC related parameters associated with a specific BUS_ID. The + * MIO_EMM_MODE() registers contain the current setting for each BUS. + * This register is also used to switch the [CLK_HI] and [CLK_LO] + * settings associated with the common EMMC_CLK. These settings can only + * be changed when [BUS_ID] = 0. + */ +union mio_emm_switch { + u64 u; + struct mio_emm_switch_s { + u64 clk_lo : 16; + u64 clk_hi : 16; + u64 power_class : 4; + u64 clk_swap : 1; + u64 reserved_37_39 : 3; + u64 bus_width : 3; + u64 reserved_43_47 : 5; + u64 hs_timing : 1; + u64 hs200_timing : 1; + u64 hs400_timing : 1; + u64 reserved_51_55 : 5; + u64 switch_err2 : 1; + u64 switch_err1 : 1; + u64 switch_err0 : 1; + u64 switch_exe : 1; + u64 bus_id : 2; + u64 reserved_62_63 : 2; + } s; + struct mio_emm_switch_cn8 { + u64 clk_lo : 16; + u64 clk_hi : 16; + u64 power_class : 4; + u64 reserved_36_39 : 4; + u64 bus_width : 3; + u64 reserved_43_47 : 5; + u64 hs_timing : 1; + u64 reserved_49_55 : 7; + u64 switch_err2 : 1; + u64 switch_err1 : 1; + u64 switch_err0 : 1; + u64 switch_exe : 1; + u64 bus_id : 2; + u64 reserved_62_63 : 2; + } cn8; + struct mio_emm_switch_cn96xxp1 { + u64 clk_lo : 16; + u64 clk_hi : 16; + u64 power_class : 4; + u64 reserved_36_39 : 4; + u64 bus_width : 3; + u64 reserved_43_47 : 5; + u64 hs_timing : 1; + u64 hs200_timing : 1; + u64 hs400_timing : 1; + u64 reserved_51_55 : 5; + u64 switch_err2 : 1; + u64 switch_err1 : 1; + u64 switch_err0 : 1; + u64 switch_exe : 1; + u64 bus_id : 2; + u64 reserved_62_63 : 2; + } cn96xxp1; + /* struct mio_emm_switch_s cn96xxp3; */ + /* struct mio_emm_switch_s cnf95xx; */ +}; + +static inline u64 MIO_EMM_SWITCH(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_SWITCH(void) +{ + return 0x2048; +} + +/** + * Register (RSL) mio_emm_tap + * + * eMMC TAP Delay Register This register indicates the delay line + * characteristics. + */ +union mio_emm_tap { + u64 u; + struct mio_emm_tap_s { + u64 delay : 8; + u64 reserved_8_63 : 56; + } s; + /* struct mio_emm_tap_s cn; */ +}; + +static inline u64 MIO_EMM_TAP(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_TAP(void) +{ + return 0x20c8; +} + +/** + * Register (RSL) mio_emm_timing + * + * eMMC Timing Register This register determines the number of tap delays + * the EMM_DAT, EMM_DS, and EMM_CMD lines are transmitted or received in + * relation to EMM_CLK. These values should only be changed when the eMMC + * bus is idle. + */ +union mio_emm_timing { + u64 u; + struct mio_emm_timing_s { + u64 data_out_tap : 6; + u64 reserved_6_15 : 10; + u64 data_in_tap : 6; + u64 reserved_22_31 : 10; + u64 cmd_out_tap : 6; + u64 reserved_38_47 : 10; + u64 cmd_in_tap : 6; + u64 reserved_54_63 : 10; + } s; + /* struct mio_emm_timing_s cn; */ +}; + +static inline u64 MIO_EMM_TIMING(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_TIMING(void) +{ + return 0x20d0; +} + +/** + * Register (RSL) mio_emm_wdog + * + * eMMC Watchdog Register + */ +union mio_emm_wdog { + u64 u; + struct mio_emm_wdog_s { + u64 clk_cnt : 26; + u64 reserved_26_63 : 38; + } s; + /* struct mio_emm_wdog_s cn; */ +}; + +static inline u64 MIO_EMM_WDOG(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_WDOG(void) +{ + return 0x2088; +} + +#endif /* __CSRS_MIO_EMM_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx/csrs/csrs-xcv.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx/csrs/csrs-xcv.h new file mode 100644 index 000000000..159f58ace --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx/csrs/csrs-xcv.h @@ -0,0 +1,428 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Marvell International Ltd. + * + * https://spdx.org/licenses + */ +#ifndef __CSRS_XCV_H__ +#define __CSRS_XCV_H__ + +/** + * @file + * + * Configuration and status register (CSR) address and type definitions for + * XCV. + * + * This file is auto generated. Do not edit. + * + */ + +/** + * Enumeration xcv_bar_e + * + * XCV Base Address Register Enumeration Enumerates the base address + * registers. + */ +#define XCV_BAR_E_XCVX_PF_BAR0(a) (0x87e0db000000ll + 0ll * (a)) +#define XCV_BAR_E_XCVX_PF_BAR0_SIZE 0x100000ull +#define XCV_BAR_E_XCVX_PF_BAR4(a) (0x87e0dbf00000ll + 0ll * (a)) +#define XCV_BAR_E_XCVX_PF_BAR4_SIZE 0x100000ull + +/** + * Enumeration xcv_int_vec_e + * + * XCV MSI-X Vector Enumeration Enumerates the MSI-X interrupt vectors. + */ +#define XCV_INT_VEC_E_INT (0) + +/** + * Register (RSL) xcv#_batch_crd_ret + * + * XCV Batch Credit Return Register + */ +union xcvx_batch_crd_ret { + u64 u; + struct xcvx_batch_crd_ret_s { + u64 crd_ret : 1; + u64 reserved_1_63 : 63; + } s; + /* struct xcvx_batch_crd_ret_s cn; */ +}; + +static inline u64 XCVX_BATCH_CRD_RET(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 XCVX_BATCH_CRD_RET(u64 a) +{ + return 0x100 + 0 * a; +} + +/** + * Register (RSL) xcv#_comp_ctl + * + * XCV Compensation Controller Register This register controls + * programmable compensation. + */ +union xcvx_comp_ctl { + u64 u; + struct xcvx_comp_ctl_s { + u64 nctl_sat : 1; + u64 reserved_1_26 : 26; + u64 nctl_lock : 1; + u64 reserved_28 : 1; + u64 pctl_sat : 1; + u64 pctl_lock : 1; + u64 reserved_31 : 1; + u64 drv_nctl : 5; + u64 reserved_37_39 : 3; + u64 drv_pctl : 5; + u64 reserved_45_47 : 3; + u64 cmp_nctl : 5; + u64 reserved_53_55 : 3; + u64 cmp_pctl : 5; + u64 reserved_61_62 : 2; + u64 drv_byp : 1; + } s; + /* struct xcvx_comp_ctl_s cn; */ +}; + +static inline u64 XCVX_COMP_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 XCVX_COMP_CTL(u64 a) +{ + return 0x20 + 0 * a; +} + +/** + * Register (RSL) xcv#_ctl + * + * XCV Control Register This register contains the status control bits. + */ +union xcvx_ctl { + u64 u; + struct xcvx_ctl_s { + u64 speed : 2; + u64 lpbk_int : 1; + u64 lpbk_ext : 1; + u64 reserved_4_63 : 60; + } s; + /* struct xcvx_ctl_s cn; */ +}; + +static inline u64 XCVX_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 XCVX_CTL(u64 a) +{ + return 0x30 + 0 * a; +} + +/** + * Register (RSL) xcv#_dll_ctl + * + * XCV DLL Controller Register The RGMII timing specification requires + * that devices transmit clock and data synchronously. The specification + * requires external sources (namely the PC board trace routes) to + * introduce the appropriate 1.5 to 2.0 ns of delay. To eliminate the + * need for the PC board delays, the RGMII interface has optional on- + * board DLLs for both transmit and receive. For correct operation, at + * most one of the transmitter, board, or receiver involved in an RGMII + * link should introduce delay. By default/reset, the RGMII receivers + * delay the received clock, and the RGMII transmitters do not delay the + * transmitted clock. Whether this default works as-is with a given link + * partner depends on the behavior of the link partner and the PC board. + * These are the possible modes of RGMII receive operation: * + * XCV()_DLL_CTL[CLKRX_BYP] = 0 (reset value) - The RGMII receive + * interface introduces clock delay using its internal DLL. This mode is + * appropriate if neither the remote transmitter nor the PC board delays + * the clock. * XCV()_DLL_CTL[CLKRX_BYP] = 1, [CLKRX_SET] = 0x0 - The + * RGMII receive interface introduces no clock delay. This mode is + * appropriate if either the remote transmitter or the PC board delays + * the clock. These are the possible modes of RGMII transmit operation: + * * XCV()_DLL_CTL[CLKTX_BYP] = 1, [CLKTX_SET] = 0x0 (reset value) - The + * RGMII transmit interface introduces no clock delay. This mode is + * appropriate is either the remote receiver or the PC board delays the + * clock. * XCV()_DLL_CTL[CLKTX_BYP] = 0 - The RGMII transmit interface + * introduces clock delay using its internal DLL. This mode is + * appropriate if neither the remote receiver nor the PC board delays the + * clock. + */ +union xcvx_dll_ctl { + u64 u; + struct xcvx_dll_ctl_s { + u64 refclk_sel : 2; + u64 reserved_2_7 : 6; + u64 clktx_set : 7; + u64 clktx_byp : 1; + u64 clkrx_set : 7; + u64 clkrx_byp : 1; + u64 clk_set : 7; + u64 lock : 1; + u64 reserved_32_63 : 32; + } s; + /* struct xcvx_dll_ctl_s cn; */ +}; + +static inline u64 XCVX_DLL_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 XCVX_DLL_CTL(u64 a) +{ + return 0x10 + 0 * a; +} + +/** + * Register (RSL) xcv#_eco + * + * INTERNAL: XCV ECO Register + */ +union xcvx_eco { + u64 u; + struct xcvx_eco_s { + u64 eco_rw : 16; + u64 reserved_16_63 : 48; + } s; + /* struct xcvx_eco_s cn; */ +}; + +static inline u64 XCVX_ECO(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 XCVX_ECO(u64 a) +{ + return 0x200 + 0 * a; +} + +/** + * Register (RSL) xcv#_inbnd_status + * + * XCV Inband Status Register This register contains RGMII inband status. + */ +union xcvx_inbnd_status { + u64 u; + struct xcvx_inbnd_status_s { + u64 link : 1; + u64 speed : 2; + u64 duplex : 1; + u64 reserved_4_63 : 60; + } s; + /* struct xcvx_inbnd_status_s cn; */ +}; + +static inline u64 XCVX_INBND_STATUS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 XCVX_INBND_STATUS(u64 a) +{ + return 0x80 + 0 * a; +} + +/** + * Register (RSL) xcv#_int + * + * XCV Interrupt Register This register flags error for TX FIFO overflow, + * TX FIFO underflow and incomplete byte for 10/100 Mode. It also flags + * status change for link duplex, link speed and link up/down. + */ +union xcvx_int { + u64 u; + struct xcvx_int_s { + u64 link : 1; + u64 speed : 1; + u64 reserved_2 : 1; + u64 duplex : 1; + u64 incomp_byte : 1; + u64 tx_undflw : 1; + u64 tx_ovrflw : 1; + u64 reserved_7_63 : 57; + } s; + /* struct xcvx_int_s cn; */ +}; + +static inline u64 XCVX_INT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 XCVX_INT(u64 a) +{ + return 0x40 + 0 * a; +} + +/** + * Register (RSL) xcv#_int_ena_w1c + * + * Loopback Error Interrupt Enable Clear Register This register clears + * interrupt enable bits. + */ +union xcvx_int_ena_w1c { + u64 u; + struct xcvx_int_ena_w1c_s { + u64 link : 1; + u64 speed : 1; + u64 reserved_2 : 1; + u64 duplex : 1; + u64 incomp_byte : 1; + u64 tx_undflw : 1; + u64 tx_ovrflw : 1; + u64 reserved_7_63 : 57; + } s; + /* struct xcvx_int_ena_w1c_s cn; */ +}; + +static inline u64 XCVX_INT_ENA_W1C(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 XCVX_INT_ENA_W1C(u64 a) +{ + return 0x50 + 0 * a; +} + +/** + * Register (RSL) xcv#_int_ena_w1s + * + * Loopback Error Interrupt Enable Set Register This register sets + * interrupt enable bits. + */ +union xcvx_int_ena_w1s { + u64 u; + struct xcvx_int_ena_w1s_s { + u64 link : 1; + u64 speed : 1; + u64 reserved_2 : 1; + u64 duplex : 1; + u64 incomp_byte : 1; + u64 tx_undflw : 1; + u64 tx_ovrflw : 1; + u64 reserved_7_63 : 57; + } s; + /* struct xcvx_int_ena_w1s_s cn; */ +}; + +static inline u64 XCVX_INT_ENA_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 XCVX_INT_ENA_W1S(u64 a) +{ + return 0x58 + 0 * a; +} + +/** + * Register (RSL) xcv#_int_w1s + * + * Loopback Error Interrupt Set Register This register sets interrupt + * bits. + */ +union xcvx_int_w1s { + u64 u; + struct xcvx_int_w1s_s { + u64 link : 1; + u64 speed : 1; + u64 reserved_2 : 1; + u64 duplex : 1; + u64 incomp_byte : 1; + u64 tx_undflw : 1; + u64 tx_ovrflw : 1; + u64 reserved_7_63 : 57; + } s; + /* struct xcvx_int_w1s_s cn; */ +}; + +static inline u64 XCVX_INT_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 XCVX_INT_W1S(u64 a) +{ + return 0x48 + 0 * a; +} + +/** + * Register (RSL) xcv#_msix_pba# + * + * XCV MSI-X Pending Bit Array Registers This register is the MSI-X PBA + * table; the bit number is indexed by the XCV_INT_VEC_E enumeration. + */ +union xcvx_msix_pbax { + u64 u; + struct xcvx_msix_pbax_s { + u64 pend : 64; + } s; + /* struct xcvx_msix_pbax_s cn; */ +}; + +static inline u64 XCVX_MSIX_PBAX(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 XCVX_MSIX_PBAX(u64 a, u64 b) +{ + return 0xf0000 + 0 * a + 8 * b; +} + +/** + * Register (RSL) xcv#_msix_vec#_addr + * + * XCV MSI-X Vector-Table Address Register This register is the MSI-X + * vector table, indexed by the XCV_INT_VEC_E enumeration. + */ +union xcvx_msix_vecx_addr { + u64 u; + struct xcvx_msix_vecx_addr_s { + u64 secvec : 1; + u64 reserved_1 : 1; + u64 addr : 47; + u64 reserved_49_63 : 15; + } s; + /* struct xcvx_msix_vecx_addr_s cn; */ +}; + +static inline u64 XCVX_MSIX_VECX_ADDR(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 XCVX_MSIX_VECX_ADDR(u64 a, u64 b) +{ + return 0 + 0 * a + 0x10 * b; +} + +/** + * Register (RSL) xcv#_msix_vec#_ctl + * + * XCV MSI-X Vector-Table Control and Data Register This register is the + * MSI-X vector table, indexed by the XCV_INT_VEC_E enumeration. + */ +union xcvx_msix_vecx_ctl { + u64 u; + struct xcvx_msix_vecx_ctl_s { + u64 data : 20; + u64 reserved_20_31 : 12; + u64 mask : 1; + u64 reserved_33_63 : 31; + } s; + /* struct xcvx_msix_vecx_ctl_s cn; */ +}; + +static inline u64 XCVX_MSIX_VECX_CTL(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 XCVX_MSIX_VECX_CTL(u64 a, u64 b) +{ + return 8 + 0 * a + 0x10 * b; +} + +/** + * Register (RSL) xcv#_reset + * + * XCV Reset Registers This register controls reset. + */ +union xcvx_reset { + u64 u; + struct xcvx_reset_s { + u64 rx_dat_rst_n : 1; + u64 rx_pkt_rst_n : 1; + u64 tx_dat_rst_n : 1; + u64 tx_pkt_rst_n : 1; + u64 reserved_4_6 : 3; + u64 comp : 1; + u64 reserved_8_10 : 3; + u64 dllrst : 1; + u64 reserved_12_14 : 3; + u64 clkrst : 1; + u64 reserved_16_62 : 47; + u64 enable : 1; + } s; + /* struct xcvx_reset_s cn; */ +}; + +static inline u64 XCVX_RESET(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 XCVX_RESET(u64 a) +{ + return 0 + 0 * a; +} + +#endif /* __CSRS_XCV_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx/gpio.h new file mode 100644 index 000000000..3943ffd95 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx/gpio.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx/smc.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx/smc.h new file mode 100644 index 000000000..beff4d158 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx/smc.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#ifndef __SMC_H__ +#define __SMC_H__ + +/* OcteonTX Service Calls version numbers */ +#define OCTEONTX_VERSION_MAJOR 0x1 +#define OCTEONTX_VERSION_MINOR 0x0 + +/* x1 - node number */ +#define OCTEONTX_DRAM_SIZE 0xc2000301 + +ssize_t smc_dram_size(unsigned int node); + +#endif /* __SMC_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx/soc.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx/soc.h new file mode 100644 index 000000000..dc081c70b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx/soc.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#ifndef __SOC_H__ +#define __SOC_H__ + +/* Product PARTNUM */ +#define CN81XX 0xA2 +#define CN83XX 0xA3 +#define CN96XX 0xB2 +#define CN95XX 0xB3 + +#define otx_is_altpkg() read_alt_pkg() +#define otx_is_soc(soc) (read_partnum() == (soc)) +#define otx_is_board(model) (!strcmp(read_board_name(), model)) +#define otx_is_platform(platform) (read_platform() == (platform)) + +enum platform { + PLATFORM_HW = 0, + PLATFORM_EMULATOR = 1, + PLATFORM_ASIM = 3, +}; + +int read_platform(void); +u8 read_partnum(void); +const char *read_board_name(void); +bool read_alt_pkg(void); + +#endif /* __SOC_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx2/board.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/board.h new file mode 100644 index 000000000..1c9ec113c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/board.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +/** Reg offsets */ +#define RST_BOOT 0x87E006001600ULL + +#define CPC_BOOT_OWNERX(a) 0x86D000000160ULL + (8 * (a)) + +/** Structure definitions */ +/** + * Register (NCB32b) cpc_boot_owner# + * + * CPC Boot Owner Registers These registers control an external arbiter + * for the boot device (SPI/eMMC) across multiple external devices. There + * is a register for each requester: _ \<0\> - SCP - reset on + * SCP reset _ \<1\> - MCP - reset on MCP reset _ \<2\> - AP + * Secure - reset on core reset _ \<3\> - AP Nonsecure - reset on core + * reset These register is only writable to the corresponding + * requestor(s) permitted with CPC_PERMIT. + */ +union cpc_boot_ownerx { + u32 u; + struct cpc_boot_ownerx_s { + u32 boot_req : 1; + u32 reserved_1_7 : 7; + u32 boot_wait : 1; + u32 reserved_9_31 : 23; + } s; +}; + +/** + * Register (RSL) rst_boot + * + * RST Boot Register This register is not accessible through ROM scripts; + * see SCR_WRITE32_S[ADDR]. + */ +union rst_boot { + u64 u; + struct rst_boot_s { + u64 rboot_pin : 1; + u64 rboot : 1; + u64 reserved_2_32 : 31; + u64 pnr_mul : 6; + u64 reserved_39 : 1; + u64 c_mul : 7; + u64 reserved_47_52 : 6; + u64 gpio_ejtag : 1; + u64 mcp_jtagdis : 1; + u64 dis_scan : 1; + u64 dis_huk : 1; + u64 vrm_err : 1; + u64 jt_tstmode : 1; + u64 ckill_ppdis : 1; + u64 trusted_mode : 1; + u64 reserved_61_62 : 2; + u64 chipkill : 1; + } s; + struct rst_boot_cn96xx { + u64 rboot_pin : 1; + u64 rboot : 1; + u64 reserved_2_23 : 22; + u64 cpt_mul : 7; + u64 reserved_31_32 : 2; + u64 pnr_mul : 6; + u64 reserved_39 : 1; + u64 c_mul : 7; + u64 reserved_47_52 : 6; + u64 gpio_ejtag : 1; + u64 mcp_jtagdis : 1; + u64 dis_scan : 1; + u64 dis_huk : 1; + u64 vrm_err : 1; + u64 reserved_58_59 : 2; + u64 trusted_mode : 1; + u64 scp_jtagdis : 1; + u64 jtagdis : 1; + u64 chipkill : 1; + } cn96xx; + struct rst_boot_cnf95xx { + u64 rboot_pin : 1; + u64 rboot : 1; + u64 reserved_2_7 : 6; + u64 bphy_mul : 7; + u64 reserved_15 : 1; + u64 dsp_mul : 7; + u64 reserved_23 : 1; + u64 cpt_mul : 7; + u64 reserved_31_32 : 2; + u64 pnr_mul : 6; + u64 reserved_39 : 1; + u64 c_mul : 7; + u64 reserved_47_52 : 6; + u64 gpio_ejtag : 1; + u64 mcp_jtagdis : 1; + u64 dis_scan : 1; + u64 dis_huk : 1; + u64 vrm_err : 1; + u64 reserved_58_59 : 2; + u64 trusted_mode : 1; + u64 scp_jtagdis : 1; + u64 jtagdis : 1; + u64 chipkill : 1; + } cnf95xx; +}; + +extern unsigned long fdt_base_addr; + +/** Function definitions */ +void mem_map_fill(void); +int fdt_get_board_mac_cnt(void); +u64 fdt_get_board_mac_addr(void); +const char *fdt_get_board_model(void); +const char *fdt_get_board_serial(void); +const char *fdt_get_board_revision(void); +void octeontx2_board_get_mac_addr(u8 index, u8 *mac_addr); +void board_acquire_flash_arb(bool acquire); +void cgx_intf_shutdown(void); + +#endif /* __BOARD_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx2/clock.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/clock.h new file mode 100644 index 000000000..7be8852a5 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/clock.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#ifndef __CLOCK_H__ + +/** System PLL reference clock */ +#define PLL_REF_CLK 50000000 /* 50 MHz */ +#define NS_PER_REF_CLK_TICK (1000000000 / PLL_REF_CLK) + +/** + * Returns the I/O clock speed in Hz + */ +u64 octeontx_get_io_clock(void); + +/** + * Returns the core clock speed in Hz + */ +u64 octeontx_get_core_clock(void); + +#endif /* __CLOCK_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-cgx.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-cgx.h new file mode 100644 index 000000000..34e7db3da --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-cgx.h @@ -0,0 +1,7851 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Marvell International Ltd. + * + * https://spdx.org/licenses + */ +#ifndef __CSRS_CGX_H__ +#define __CSRS_CGX_H__ + +/** + * @file + * + * Configuration and status register (CSR) address and type definitions for + * CGX. + * + * This file is auto generated. Do not edit. + * + */ + +/** + * Enumeration cgx_bar_e + * + * CGX Base Address Register Enumeration Enumerates the base address + * registers. + */ +#define CGX_BAR_E_CGXX_PF_BAR0(a) (0x87e0e0000000ll + 0x1000000ll * (a)) +#define CGX_BAR_E_CGXX_PF_BAR0_SIZE 0x100000ull +#define CGX_BAR_E_CGXX_PF_BAR4(a) (0x87e0e0400000ll + 0x1000000ll * (a)) +#define CGX_BAR_E_CGXX_PF_BAR4_SIZE 0x100000ull + +/** + * Enumeration cgx_int_vec_e + * + * CGX MSI-X Vector Enumeration Enumeration the MSI-X interrupt vectors. + */ +#define CGX_INT_VEC_E_CMRX_INT(a) (0 + 9 * (a)) +#define CGX_INT_VEC_E_CMRX_SW(a) (0x26 + (a)) +#define CGX_INT_VEC_E_CMR_MEM_INT (0x24) +#define CGX_INT_VEC_E_GMPX_GMI_RX_INT(a) (5 + 9 * (a)) +#define CGX_INT_VEC_E_GMPX_GMI_TX_INT(a) (6 + 9 * (a)) +#define CGX_INT_VEC_E_GMPX_GMI_WOL_INT(a) (7 + 9 * (a)) +#define CGX_INT_VEC_E_GMPX_PCS_INT(a) (4 + 9 * (a)) +#define CGX_INT_VEC_E_SMUX_RX_INT(a) (2 + 9 * (a)) +#define CGX_INT_VEC_E_SMUX_RX_WOL_INT(a) (8 + 9 * (a)) +#define CGX_INT_VEC_E_SMUX_TX_INT(a) (3 + 9 * (a)) +#define CGX_INT_VEC_E_SPUX_INT(a) (1 + 9 * (a)) +#define CGX_INT_VEC_E_SW (0x25) + +/** + * Enumeration cgx_lmac_types_e + * + * CGX LMAC Type Enumeration Enumerates the LMAC Types that CGX supports. + */ +#define CGX_LMAC_TYPES_E_FIFTYG_R (8) +#define CGX_LMAC_TYPES_E_FORTYG_R (4) +#define CGX_LMAC_TYPES_E_HUNDREDG_R (9) +#define CGX_LMAC_TYPES_E_QSGMII (6) +#define CGX_LMAC_TYPES_E_RGMII (5) +#define CGX_LMAC_TYPES_E_RXAUI (2) +#define CGX_LMAC_TYPES_E_SGMII (0) +#define CGX_LMAC_TYPES_E_TENG_R (3) +#define CGX_LMAC_TYPES_E_TWENTYFIVEG_R (7) +#define CGX_LMAC_TYPES_E_USXGMII (0xa) +#define CGX_LMAC_TYPES_E_XAUI (1) + +/** + * Enumeration cgx_opcode_e + * + * INTERNAL: CGX Error Opcode Enumeration Enumerates the error opcodes + * created by CGX and presented to NCSI/NIX. + */ +#define CGX_OPCODE_E_RE_FCS (7) +#define CGX_OPCODE_E_RE_FCS_RCV (8) +#define CGX_OPCODE_E_RE_JABBER (2) +#define CGX_OPCODE_E_RE_NONE (0) +#define CGX_OPCODE_E_RE_PARTIAL (1) +#define CGX_OPCODE_E_RE_RX_CTL (0xb) +#define CGX_OPCODE_E_RE_SKIP (0xc) +#define CGX_OPCODE_E_RE_TERMINATE (9) + +/** + * Enumeration cgx_spu_br_train_cst_e + * + * INTERNAL: CGX Training Coefficient Status Enumeration 2-bit status + * for each coefficient as defined in IEEE 802.3, Table 72-5. + */ +#define CGX_SPU_BR_TRAIN_CST_E_MAXIMUM (3) +#define CGX_SPU_BR_TRAIN_CST_E_MINIMUM (2) +#define CGX_SPU_BR_TRAIN_CST_E_NOT_UPDATED (0) +#define CGX_SPU_BR_TRAIN_CST_E_UPDATED (1) + +/** + * Enumeration cgx_spu_br_train_cup_e + * + * INTERNAL:CGX Training Coefficient Enumeration 2-bit command for each + * coefficient as defined in IEEE 802.3, Table 72-4. + */ +#define CGX_SPU_BR_TRAIN_CUP_E_DECREMENT (1) +#define CGX_SPU_BR_TRAIN_CUP_E_HOLD (0) +#define CGX_SPU_BR_TRAIN_CUP_E_INCREMENT (2) +#define CGX_SPU_BR_TRAIN_CUP_E_RSV_CMD (3) + +/** + * Enumeration cgx_usxgmii_rate_e + * + * CGX USXGMII Rate Enumeration Enumerates the USXGMII sub-port type + * rate, CGX()_SPU()_CONTROL1[USXGMII_RATE]. Selecting a rate higher + * than the maximum allowed for a given port sub-type (specified by + * CGX()_SPU()_CONTROL1[USXGMII_TYPE]), e.g., selecting ::RATE_2HG (2.5 + * Gbps) for CGX_USXGMII_TYPE_E::SXGMII_2G, will cause unpredictable + * behavior. USXGMII hardware-based autonegotiation may change this + * setting. + */ +#define CGX_USXGMII_RATE_E_RATE_100M (1) +#define CGX_USXGMII_RATE_E_RATE_10G (5) +#define CGX_USXGMII_RATE_E_RATE_10M (0) +#define CGX_USXGMII_RATE_E_RATE_1G (2) +#define CGX_USXGMII_RATE_E_RATE_20G (6) +#define CGX_USXGMII_RATE_E_RATE_2HG (3) +#define CGX_USXGMII_RATE_E_RATE_5G (4) +#define CGX_USXGMII_RATE_E_RSV_RATE (7) + +/** + * Enumeration cgx_usxgmii_type_e + * + * CGX USXGMII Port Sub-Type Enumeration Enumerates the USXGMII sub-port + * type, CGX()_SPU()_CONTROL1[USXGMII_TYPE]. The description indicates + * the maximum rate and the maximum number of ports (LMACs) for each sub- + * type. The minimum rate for any port is 10M. The rate selection for + * each LMAC is made using CGX()_SPU()_CONTROL1[USXGMII_RATE] and the + * number of active ports/LMACs is implicitly determined by the value + * given to CGX()_CMR()_CONFIG[ENABLE] for each LMAC. Selecting a rate + * higher than the maximum allowed for a given port sub-type or enabling + * more LMACs than the maximum allowed for a given port sub-type will + * cause unpredictable behavior. + */ +#define CGX_USXGMII_TYPE_E_DXGMII_10G (3) +#define CGX_USXGMII_TYPE_E_DXGMII_20G (5) +#define CGX_USXGMII_TYPE_E_DXGMII_5G (4) +#define CGX_USXGMII_TYPE_E_QXGMII_10G (7) +#define CGX_USXGMII_TYPE_E_QXGMII_20G (6) +#define CGX_USXGMII_TYPE_E_SXGMII_10G (0) +#define CGX_USXGMII_TYPE_E_SXGMII_2G (2) +#define CGX_USXGMII_TYPE_E_SXGMII_5G (1) + +/** + * Structure cgx_spu_br_lane_train_status_s + * + * INTERNAL:CGX Lane Training Status Structure This is the group of lane + * status bits for a single lane in the BASE-R PMD status register (MDIO + * address 1.151) as defined in IEEE 802.3ba-2010, Table 45-55. + */ +union cgx_spu_br_lane_train_status_s { + u32 u; + struct cgx_spu_br_lane_train_status_s_s { + u32 rx_trained : 1; + u32 frame_lock : 1; + u32 training : 1; + u32 training_failure : 1; + u32 reserved_4_31 : 28; + } s; + /* struct cgx_spu_br_lane_train_status_s_s cn; */ +}; + +/** + * Structure cgx_spu_br_train_cup_s + * + * INTERNAL:CGX Lane Training Coefficient Structure This is the + * coefficient update field of the BASE-R link training packet as defined + * in IEEE 802.3, Table 72-4. + */ +union cgx_spu_br_train_cup_s { + u32 u; + struct cgx_spu_br_train_cup_s_s { + u32 pre_cup : 2; + u32 main_cup : 2; + u32 post_cup : 2; + u32 reserved_6_11 : 6; + u32 init : 1; + u32 preset : 1; + u32 reserved_14_31 : 18; + } s; + struct cgx_spu_br_train_cup_s_cn { + u32 pre_cup : 2; + u32 main_cup : 2; + u32 post_cup : 2; + u32 reserved_6_11 : 6; + u32 init : 1; + u32 preset : 1; + u32 reserved_14_15 : 2; + u32 reserved_16_31 : 16; + } cn; +}; + +/** + * Structure cgx_spu_br_train_rep_s + * + * INTERNAL:CGX Training Report Structure This is the status report + * field of the BASE-R link training packet as defined in IEEE 802.3, + * Table 72-5. + */ +union cgx_spu_br_train_rep_s { + u32 u; + struct cgx_spu_br_train_rep_s_s { + u32 pre_cst : 2; + u32 main_cst : 2; + u32 post_cst : 2; + u32 reserved_6_14 : 9; + u32 rx_ready : 1; + u32 reserved_16_31 : 16; + } s; + /* struct cgx_spu_br_train_rep_s_s cn; */ +}; + +/** + * Structure cgx_spu_sds_cu_s + * + * INTERNAL: CGX Training Coeffiecient Structure This structure is + * similar to CGX_SPU_BR_TRAIN_CUP_S format, but with reserved fields + * removed and [RCVR_READY] field added. + */ +union cgx_spu_sds_cu_s { + u32 u; + struct cgx_spu_sds_cu_s_s { + u32 pre_cu : 2; + u32 main_cu : 2; + u32 post_cu : 2; + u32 initialize : 1; + u32 preset : 1; + u32 rcvr_ready : 1; + u32 reserved_9_31 : 23; + } s; + /* struct cgx_spu_sds_cu_s_s cn; */ +}; + +/** + * Structure cgx_spu_sds_skew_status_s + * + * CGX Skew Status Structure Provides receive skew information detected + * for a physical SerDes lane when it is assigned to a multilane + * LMAC/LPCS. Contents are valid when RX deskew is done for the + * associated LMAC/LPCS. + */ +union cgx_spu_sds_skew_status_s { + u32 u; + struct cgx_spu_sds_skew_status_s_s { + u32 am_timestamp : 12; + u32 reserved_12_15 : 4; + u32 am_lane_id : 5; + u32 reserved_21_22 : 2; + u32 lane_skew : 7; + u32 reserved_30_31 : 2; + } s; + /* struct cgx_spu_sds_skew_status_s_s cn; */ +}; + +/** + * Structure cgx_spu_sds_sr_s + * + * INTERNAL: CGX Lane Training Coefficient Structure Similar to + * CGX_SPU_BR_TRAIN_REP_S format, but with reserved and RX ready fields + * removed. + */ +union cgx_spu_sds_sr_s { + u32 u; + struct cgx_spu_sds_sr_s_s { + u32 pre_status : 2; + u32 main_status : 2; + u32 post_status : 2; + u32 reserved_6_31 : 26; + } s; + /* struct cgx_spu_sds_sr_s_s cn; */ +}; + +/** + * Register (RSL) cgx#_active_pc + * + * CGX ACTIVE PC Register This register counts the conditional clocks for + * power management. + */ +union cgxx_active_pc { + u64 u; + struct cgxx_active_pc_s { + u64 cnt : 64; + } s; + /* struct cgxx_active_pc_s cn; */ +}; + +static inline u64 CGXX_ACTIVE_PC(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_ACTIVE_PC(void) +{ + return 0x2010; +} + +/** + * Register (RSL) cgx#_cmr#_activity + * + * CGX CMR Activity Registers + */ +union cgxx_cmrx_activity { + u64 u; + struct cgxx_cmrx_activity_s { + u64 act_tx_lo : 1; + u64 act_tx_hi : 1; + u64 pause_tx : 1; + u64 act_rx_lo : 1; + u64 act_rx_hi : 1; + u64 pause_rx : 1; + u64 reserved_6_63 : 58; + } s; + /* struct cgxx_cmrx_activity_s cn; */ +}; + +static inline u64 CGXX_CMRX_ACTIVITY(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_ACTIVITY(u64 a) +{ + return 0x5f8 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_config + * + * CGX CMR Configuration Registers Logical MAC/PCS configuration + * registers; one per LMAC. The maximum number of LMACs (and maximum LMAC + * ID) that can be enabled by these registers is limited by + * CGX()_CMR_RX_LMACS[LMACS] and CGX()_CMR_TX_LMACS[LMACS]. Internal: + * \ Example configurations: ------------------------------------ + * --------------------------------------- Configuration + * LMACS Register [ENABLE] [LMAC_TYPE] ---------------- + * ----------------------------------------------------------- + * 1x50G+1x25G+1xSGMII 4 CGXn_CMR0_CONFIG 1 8 + * CGXn_CMR1_CONFIG 0 -- + * CGXn_CMR2_CONFIG 1 7 + * CGXn_CMR3_CONFIG 1 0 --------------------------------- + * ------------------------------------------ USXGMII + * 1-4 CGXn_CMR0_CONFIG 1 a + * CGXn_CMR1_CONFIG 1 a + * CGXn_CMR2_CONFIG 1 a + * CGXn_CMR3_CONFIG 1 a --------------------------------- + * ------------------------------------------ 1x100GBASE-R4 1 + * CGXn_CMR0_CONFIG 1 9 + * CGXn_CMR1_CONFIG 0 -- + * CGXn_CMR2_CONFIG 0 -- + * CGXn_CMR3_CONFIG 0 -- -------------------------------- + * ------------------------------------------- 2x50GBASE-R2 + * 2 CGXn_CMR0_CONFIG 1 8 + * CGXn_CMR1_CONFIG 1 8 + * CGXn_CMR2_CONFIG 0 -- + * CGXn_CMR3_CONFIG 0 -- -------------------------------- + * ------------------------------------------- 4x25GBASE-R + * 4 CGXn_CMR0_CONFIG 1 7 + * CGXn_CMR1_CONFIG 1 7 + * CGXn_CMR2_CONFIG 1 7 + * CGXn_CMR3_CONFIG 1 7 --------------------------------- + * ------------------------------------------ QSGMII 4 + * CGXn_CMR0_CONFIG 1 6 + * CGXn_CMR1_CONFIG 1 6 + * CGXn_CMR2_CONFIG 1 6 + * CGXn_CMR3_CONFIG 1 6 --------------------------------- + * ------------------------------------------ 1x40GBASE-R4 1 + * CGXn_CMR0_CONFIG 1 4 + * CGXn_CMR1_CONFIG 0 -- + * CGXn_CMR2_CONFIG 0 -- + * CGXn_CMR3_CONFIG 0 -- -------------------------------- + * ------------------------------------------- 4x10GBASE-R + * 4 CGXn_CMR0_CONFIG 1 3 + * CGXn_CMR1_CONFIG 1 3 + * CGXn_CMR2_CONFIG 1 3 + * CGXn_CMR3_CONFIG 1 3 --------------------------------- + * ------------------------------------------ 2xRXAUI 2 + * CGXn_CMR0_CONFIG 1 2 + * CGXn_CMR1_CONFIG 1 2 + * CGXn_CMR2_CONFIG 0 -- + * CGXn_CMR3_CONFIG 0 -- -------------------------------- + * ------------------------------------------- 1x10GBASE-X/XAUI/DXAUI + * 1 CGXn_CMR0_CONFIG 1 1 + * CGXn_CMR1_CONFIG 0 -- + * CGXn_CMR2_CONFIG 0 -- + * CGXn_CMR3_CONFIG 0 -- -------------------------------- + * ------------------------------------------- 4xSGMII/1000BASE-X + * 4 CGXn_CMR0_CONFIG 1 0 + * CGXn_CMR1_CONFIG 1 0 + * CGXn_CMR2_CONFIG 1 0 + * CGXn_CMR3_CONFIG 1 0 --------------------------------- + * ------------------------------------------ \ + */ +union cgxx_cmrx_config { + u64 u; + struct cgxx_cmrx_config_s { + u64 lane_to_sds : 8; + u64 reserved_8_39 : 32; + u64 lmac_type : 4; + u64 unused : 8; + u64 int_beat_gen : 1; + u64 data_pkt_tx_en : 1; + u64 data_pkt_rx_en : 1; + u64 enable : 1; + u64 x2p_select : 3; + u64 p2x_select : 3; + u64 reserved_62_63 : 2; + } s; + /* struct cgxx_cmrx_config_s cn; */ +}; + +static inline u64 CGXX_CMRX_CONFIG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_CONFIG(u64 a) +{ + return 0 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_int + * + * CGX CMR Interrupt Register + */ +union cgxx_cmrx_int { + u64 u; + struct cgxx_cmrx_int_s { + u64 pause_drp : 1; + u64 overflw : 1; + u64 nic_nxc : 1; + u64 nix0_nxc : 1; + u64 nix1_nxc : 1; + u64 nix0_e_nxc : 1; + u64 nix1_e_nxc : 1; + u64 reserved_7_63 : 57; + } s; + /* struct cgxx_cmrx_int_s cn; */ +}; + +static inline u64 CGXX_CMRX_INT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_INT(u64 a) +{ + return 0x40 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_int_ena_w1c + * + * CGX CMR Interrupt Enable Clear Register This register clears interrupt + * enable bits. + */ +union cgxx_cmrx_int_ena_w1c { + u64 u; + struct cgxx_cmrx_int_ena_w1c_s { + u64 pause_drp : 1; + u64 overflw : 1; + u64 nic_nxc : 1; + u64 nix0_nxc : 1; + u64 nix1_nxc : 1; + u64 nix0_e_nxc : 1; + u64 nix1_e_nxc : 1; + u64 reserved_7_63 : 57; + } s; + /* struct cgxx_cmrx_int_ena_w1c_s cn; */ +}; + +static inline u64 CGXX_CMRX_INT_ENA_W1C(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_INT_ENA_W1C(u64 a) +{ + return 0x50 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_int_ena_w1s + * + * CGX CMR Interrupt Enable Set Register This register sets interrupt + * enable bits. + */ +union cgxx_cmrx_int_ena_w1s { + u64 u; + struct cgxx_cmrx_int_ena_w1s_s { + u64 pause_drp : 1; + u64 overflw : 1; + u64 nic_nxc : 1; + u64 nix0_nxc : 1; + u64 nix1_nxc : 1; + u64 nix0_e_nxc : 1; + u64 nix1_e_nxc : 1; + u64 reserved_7_63 : 57; + } s; + /* struct cgxx_cmrx_int_ena_w1s_s cn; */ +}; + +static inline u64 CGXX_CMRX_INT_ENA_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_INT_ENA_W1S(u64 a) +{ + return 0x58 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_int_w1s + * + * CGX CMR Interrupt Set Register This register sets interrupt bits. + */ +union cgxx_cmrx_int_w1s { + u64 u; + struct cgxx_cmrx_int_w1s_s { + u64 pause_drp : 1; + u64 overflw : 1; + u64 nic_nxc : 1; + u64 nix0_nxc : 1; + u64 nix1_nxc : 1; + u64 nix0_e_nxc : 1; + u64 nix1_e_nxc : 1; + u64 reserved_7_63 : 57; + } s; + /* struct cgxx_cmrx_int_w1s_s cn; */ +}; + +static inline u64 CGXX_CMRX_INT_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_INT_W1S(u64 a) +{ + return 0x48 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_led_timing + * + * CGX MAC LED Activity Timing Registers + */ +union cgxx_cmrx_led_timing { + u64 u; + struct cgxx_cmrx_led_timing_s { + u64 extension : 8; + u64 reserved_8_63 : 56; + } s; + /* struct cgxx_cmrx_led_timing_s cn; */ +}; + +static inline u64 CGXX_CMRX_LED_TIMING(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_LED_TIMING(u64 a) +{ + return 0x5f0 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_prt_cbfc_ctl + * + * CGX CMR LMAC PFC Control Registers See CGX()_CMR()_RX_LOGL_XOFF[XOFF]. + */ +union cgxx_cmrx_prt_cbfc_ctl { + u64 u; + struct cgxx_cmrx_prt_cbfc_ctl_s { + u64 reserved_0_15 : 16; + u64 phys_bp : 16; + u64 reserved_32_63 : 32; + } s; + /* struct cgxx_cmrx_prt_cbfc_ctl_s cn; */ +}; + +static inline u64 CGXX_CMRX_PRT_CBFC_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_PRT_CBFC_CTL(u64 a) +{ + return 0x608 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_bp_drop + * + * CGX Receive Backpressure Drop Register + */ +union cgxx_cmrx_rx_bp_drop { + u64 u; + struct cgxx_cmrx_rx_bp_drop_s { + u64 mark : 7; + u64 reserved_7_63 : 57; + } s; + /* struct cgxx_cmrx_rx_bp_drop_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_BP_DROP(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_BP_DROP(u64 a) +{ + return 0xd8 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_bp_off + * + * CGX Receive Backpressure Off Register + */ +union cgxx_cmrx_rx_bp_off { + u64 u; + struct cgxx_cmrx_rx_bp_off_s { + u64 mark : 7; + u64 reserved_7_63 : 57; + } s; + /* struct cgxx_cmrx_rx_bp_off_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_BP_OFF(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_BP_OFF(u64 a) +{ + return 0xe8 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_bp_on + * + * CGX Receive Backpressure On Register + */ +union cgxx_cmrx_rx_bp_on { + u64 u; + struct cgxx_cmrx_rx_bp_on_s { + u64 mark : 13; + u64 reserved_13_63 : 51; + } s; + /* struct cgxx_cmrx_rx_bp_on_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_BP_ON(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_BP_ON(u64 a) +{ + return 0xe0 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_bp_status + * + * CGX CMR Receive Backpressure Status Registers + */ +union cgxx_cmrx_rx_bp_status { + u64 u; + struct cgxx_cmrx_rx_bp_status_s { + u64 bp : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_cmrx_rx_bp_status_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_BP_STATUS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_BP_STATUS(u64 a) +{ + return 0xf0 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_dmac_ctl0 + * + * CGX CMR Receive DMAC Address-Control0 Register DMAC CAM control + * register for use by X2P/NIX bound traffic. Received packets are only + * passed to X2P/NIX when the DMAC0 filter result is ACCEPT and STEERING0 + * filter result is PASS. See also CGX()_CMR_RX_DMAC()_CAM0 and + * CGX()_CMR_RX_STEERING0(). Internal: "* ALGORITHM Here is some pseudo + * code that represents the address filter behavior. \ + * dmac_addr_filter(uint8 prt, uint48 dmac) { for (lmac=0, lmac\<4, + * lmac++) { if (is_bcst(dmac)) // + * broadcast accept return (CGX()_CMR(lmac)_RX_DMAC_CTL0[BCST_ACCEPT] + * ? ACCEPT : REJECT); if (is_mcst(dmac) && + * CGX()_CMR(lmac)_RX_DMAC_CTL0[MCST_MODE] == 0) // multicast reject + * return REJECT; if (is_mcst(dmac) && + * CGX()_CMR(lmac)_RX_DMAC_CTL0[MCST_MODE] == 1) // multicast accept + * return ACCEPT; else // DMAC CAM filter cam_hit = 0; for + * (i=0; i\<32; i++) { cam = CGX()_CMR_RX_DMAC(i)_CAM0; if + * (cam[EN] && cam[ID] == lmac && cam[ADR] == dmac) { cam_hit = 1; + * break; } } if (cam_hit) { return + * (CGX()_CMR(lmac)_RX_DMAC_CTL0[CAM_ACCEPT] ? ACCEPT : REJECT); else + * return (CGX()_CMR(lmac)_RX_DMAC_CTL0[CAM_ACCEPT] ? REJECT : ACCEPT); + * } } \" + */ +union cgxx_cmrx_rx_dmac_ctl0 { + u64 u; + struct cgxx_cmrx_rx_dmac_ctl0_s { + u64 bcst_accept : 1; + u64 mcst_mode : 2; + u64 cam_accept : 1; + u64 reserved_4_63 : 60; + } s; + /* struct cgxx_cmrx_rx_dmac_ctl0_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_DMAC_CTL0(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_DMAC_CTL0(u64 a) +{ + return 0x1f8 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_dmac_ctl1 + * + * CGX CMR Receive DMAC Address-Control1 Register DMAC CAM control + * register for use by NCSI bound traffic. Received packets are only + * passed to NCSI when the DMAC1 filter result is ACCEPT and STEERING1 + * filter result is PASS. See also CGX()_CMR_RX_DMAC()_CAM1 and + * CGX()_CMR_RX_STEERING1(). For use with the LMAC associated with NCSI; + * see CGX()_CMR_GLOBAL_CONFIG[NCSI_LMAC_ID]. Internal: ALGORITHM: See + * CGX()_CMR()_RX_DMAC_CTL0. + */ +union cgxx_cmrx_rx_dmac_ctl1 { + u64 u; + struct cgxx_cmrx_rx_dmac_ctl1_s { + u64 bcst_accept : 1; + u64 mcst_mode : 2; + u64 cam_accept : 1; + u64 reserved_4_63 : 60; + } s; + /* struct cgxx_cmrx_rx_dmac_ctl1_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_DMAC_CTL1(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_DMAC_CTL1(u64 a) +{ + return 0x3f8 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_fifo_len + * + * CGX CMR Receive Fifo Length Registers + */ +union cgxx_cmrx_rx_fifo_len { + u64 u; + struct cgxx_cmrx_rx_fifo_len_s { + u64 fifo_len : 14; + u64 busy : 1; + u64 fifo_len_e : 14; + u64 busy_e : 1; + u64 reserved_30_63 : 34; + } s; + /* struct cgxx_cmrx_rx_fifo_len_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_FIFO_LEN(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_FIFO_LEN(u64 a) +{ + return 0x108 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_id_map + * + * CGX CMR Receive ID Map Register These registers set the RX LMAC ID + * mapping for X2P/NIX. + */ +union cgxx_cmrx_rx_id_map { + u64 u; + struct cgxx_cmrx_rx_id_map_s { + u64 pknd : 6; + u64 unused : 2; + u64 rid : 7; + u64 reserved_15_63 : 49; + } s; + /* struct cgxx_cmrx_rx_id_map_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_ID_MAP(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_ID_MAP(u64 a) +{ + return 0x60 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_logl_xoff + * + * CGX CMR Receive Logical XOFF Registers + */ +union cgxx_cmrx_rx_logl_xoff { + u64 u; + struct cgxx_cmrx_rx_logl_xoff_s { + u64 xoff : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_cmrx_rx_logl_xoff_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_LOGL_XOFF(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_LOGL_XOFF(u64 a) +{ + return 0xf8 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_logl_xon + * + * CGX CMR Receive Logical XON Registers + */ +union cgxx_cmrx_rx_logl_xon { + u64 u; + struct cgxx_cmrx_rx_logl_xon_s { + u64 xon : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_cmrx_rx_logl_xon_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_LOGL_XON(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_LOGL_XON(u64 a) +{ + return 0x100 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_merge_stat0 + * + * CGX RX Preemption Status Register 0 + */ +union cgxx_cmrx_rx_merge_stat0 { + u64 u; + struct cgxx_cmrx_rx_merge_stat0_s { + u64 fa_err_cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_rx_merge_stat0_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_MERGE_STAT0(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_MERGE_STAT0(u64 a) +{ + return 0x138 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_merge_stat1 + * + * CGX RX Preemption Status Register 1 + */ +union cgxx_cmrx_rx_merge_stat1 { + u64 u; + struct cgxx_cmrx_rx_merge_stat1_s { + u64 fs_err_cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_rx_merge_stat1_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_MERGE_STAT1(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_MERGE_STAT1(u64 a) +{ + return 0x140 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_merge_stat2 + * + * CGX RX Preemption Status Register 2 + */ +union cgxx_cmrx_rx_merge_stat2 { + u64 u; + struct cgxx_cmrx_rx_merge_stat2_s { + u64 fa_ok_cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_rx_merge_stat2_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_MERGE_STAT2(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_MERGE_STAT2(u64 a) +{ + return 0x148 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_merge_stat3 + * + * CGX RX Preemption Status Register 3 + */ +union cgxx_cmrx_rx_merge_stat3 { + u64 u; + struct cgxx_cmrx_rx_merge_stat3_s { + u64 ff_cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_rx_merge_stat3_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_MERGE_STAT3(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_MERGE_STAT3(u64 a) +{ + return 0x150 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_merge_stat4 + * + * CGX RX Preemption Status Register 4 + */ +union cgxx_cmrx_rx_merge_stat4 { + u64 u; + struct cgxx_cmrx_rx_merge_stat4_s { + u64 cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_rx_merge_stat4_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_MERGE_STAT4(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_MERGE_STAT4(u64 a) +{ + return 0x158 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_pause_drop_time + * + * CGX CMR Receive Pause Drop-Time Register + */ +union cgxx_cmrx_rx_pause_drop_time { + u64 u; + struct cgxx_cmrx_rx_pause_drop_time_s { + u64 pause_time : 16; + u64 pause_time_e : 16; + u64 reserved_32_63 : 32; + } s; + /* struct cgxx_cmrx_rx_pause_drop_time_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_PAUSE_DROP_TIME(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_PAUSE_DROP_TIME(u64 a) +{ + return 0x68 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_stat0 + * + * CGX Receive Status Register 0 These registers provide a count of + * received packets that meet the following conditions: * are not + * recognized as ERROR packets(any OPCODE). * are not recognized as PAUSE + * packets. * are not dropped due FIFO full status. * are not dropped due + * DMAC0 or STEERING0 filtering. Internal: "This pseudo code represents + * the RX STAT0 through STAT8 accounting: \ If (errored) incr + * RX_STAT8 else if (ctrl packet, i.e. Pause/PFC) incr RX_STAT2,3 else + * if (fifo full drop) incr RX_STAT6,7 else if (DMAC0/VLAN0 filter + * drop) incr RX_STAT4,5 if not a filter+decision else incr + * RX_STAT0,1 end \" + */ +union cgxx_cmrx_rx_stat0 { + u64 u; + struct cgxx_cmrx_rx_stat0_s { + u64 cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_rx_stat0_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_STAT0(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_STAT0(u64 a) +{ + return 0x70 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_stat1 + * + * CGX Receive Status Register 1 These registers provide a count of + * octets of received packets. + */ +union cgxx_cmrx_rx_stat1 { + u64 u; + struct cgxx_cmrx_rx_stat1_s { + u64 cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_rx_stat1_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_STAT1(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_STAT1(u64 a) +{ + return 0x78 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_stat2 + * + * CGX Receive Status Register 2 These registers provide a count of + * received packets that meet the following conditions: * are not + * recognized as ERROR packets(any OPCODE). * are recognized as PAUSE + * packets. Pause packets can be optionally dropped or forwarded based + * on + * CGX()_SMU()_RX_FRM_CTL[CTL_DRP]/CGX()_GMP_GMI_RX()_FRM_CTL[CTL_DRP]. + * This count increments regardless of whether the packet is dropped. + */ +union cgxx_cmrx_rx_stat2 { + u64 u; + struct cgxx_cmrx_rx_stat2_s { + u64 cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_rx_stat2_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_STAT2(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_STAT2(u64 a) +{ + return 0x80 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_stat3 + * + * CGX Receive Status Register 3 These registers provide a count of + * octets of received PAUSE and control packets. + */ +union cgxx_cmrx_rx_stat3 { + u64 u; + struct cgxx_cmrx_rx_stat3_s { + u64 cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_rx_stat3_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_STAT3(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_STAT3(u64 a) +{ + return 0x88 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_stat4 + * + * CGX Receive Status Register 4 These registers provide a count of + * received packets that meet the following conditions: * are not + * recognized as ERROR packets(any OPCODE). * are not recognized as PAUSE + * packets. * are not dropped due FIFO full status. * are dropped due + * DMAC0 or STEERING0 filtering. 16B packets or smaller (20B in case of + * FCS strip) as the result of truncation or other means are not dropped + * by CGX (unless filter and decision is also asserted) and will never + * appear in this count. Should the MAC signal to the CMR that the packet + * be filtered upon decision before the end of packet, then STAT4 and + * STAT5 will not be updated. + */ +union cgxx_cmrx_rx_stat4 { + u64 u; + struct cgxx_cmrx_rx_stat4_s { + u64 cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_rx_stat4_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_STAT4(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_STAT4(u64 a) +{ + return 0x90 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_stat5 + * + * CGX Receive Status Register 5 These registers provide a count of + * octets of filtered DMAC0 or VLAN STEERING0 packets. + */ +union cgxx_cmrx_rx_stat5 { + u64 u; + struct cgxx_cmrx_rx_stat5_s { + u64 cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_rx_stat5_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_STAT5(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_STAT5(u64 a) +{ + return 0x98 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_stat6 + * + * CGX Receive Status Register 6 These registers provide a count of + * received packets that meet the following conditions: * are not + * recognized as ERROR packets(any OPCODE). * are not recognized as PAUSE + * packets. * are dropped due FIFO full status. They do not count any + * packet that is truncated at the point of overflow and sent on to the + * NIX. The truncated packet will be marked with error and increment + * STAT8. These registers count all entire packets dropped by the FIFO + * for a given LMAC. + */ +union cgxx_cmrx_rx_stat6 { + u64 u; + struct cgxx_cmrx_rx_stat6_s { + u64 cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_rx_stat6_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_STAT6(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_STAT6(u64 a) +{ + return 0xa0 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_stat7 + * + * CGX Receive Status Register 7 These registers provide a count of + * octets of received packets that were dropped due to a full receive + * FIFO. + */ +union cgxx_cmrx_rx_stat7 { + u64 u; + struct cgxx_cmrx_rx_stat7_s { + u64 cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_rx_stat7_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_STAT7(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_STAT7(u64 a) +{ + return 0xa8 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_stat8 + * + * CGX Receive Status Register 8 These registers provide a count of + * received packets that meet the following conditions: * are recognized + * as ERROR packets(any OPCODE). + */ +union cgxx_cmrx_rx_stat8 { + u64 u; + struct cgxx_cmrx_rx_stat8_s { + u64 cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_rx_stat8_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_STAT8(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_STAT8(u64 a) +{ + return 0xb0 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_rx_stat_pri#_xoff + * + * CGX CMR RX XON to XOFF transition Registers + */ +union cgxx_cmrx_rx_stat_prix_xoff { + u64 u; + struct cgxx_cmrx_rx_stat_prix_xoff_s { + u64 cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_rx_stat_prix_xoff_s cn; */ +}; + +static inline u64 CGXX_CMRX_RX_STAT_PRIX_XOFF(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_RX_STAT_PRIX_XOFF(u64 a, u64 b) +{ + return 0x7c0 + 0x40000 * a + 8 * b; +} + +/** + * Register (RSL) cgx#_cmr#_scratch# + * + * CGX CMR Scratch Registers + */ +union cgxx_cmrx_scratchx { + u64 u; + struct cgxx_cmrx_scratchx_s { + u64 scratch : 64; + } s; + /* struct cgxx_cmrx_scratchx_s cn; */ +}; + +static inline u64 CGXX_CMRX_SCRATCHX(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_SCRATCHX(u64 a, u64 b) +{ + return 0x1050 + 0x40000 * a + 8 * b; +} + +/** + * Register (RSL) cgx#_cmr#_sw_int + * + * CGX CMR Interrupt Register + */ +union cgxx_cmrx_sw_int { + u64 u; + struct cgxx_cmrx_sw_int_s { + u64 sw_set : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_cmrx_sw_int_s cn; */ +}; + +static inline u64 CGXX_CMRX_SW_INT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_SW_INT(u64 a) +{ + return 0x180 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_sw_int_ena_w1c + * + * CGX CMR Interrupt Enable Clear Register This register clears interrupt + * enable bits. + */ +union cgxx_cmrx_sw_int_ena_w1c { + u64 u; + struct cgxx_cmrx_sw_int_ena_w1c_s { + u64 sw_set : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_cmrx_sw_int_ena_w1c_s cn; */ +}; + +static inline u64 CGXX_CMRX_SW_INT_ENA_W1C(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_SW_INT_ENA_W1C(u64 a) +{ + return 0x190 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_sw_int_ena_w1s + * + * CGX CMR Interrupt Enable Set Register This register sets interrupt + * enable bits. + */ +union cgxx_cmrx_sw_int_ena_w1s { + u64 u; + struct cgxx_cmrx_sw_int_ena_w1s_s { + u64 sw_set : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_cmrx_sw_int_ena_w1s_s cn; */ +}; + +static inline u64 CGXX_CMRX_SW_INT_ENA_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_SW_INT_ENA_W1S(u64 a) +{ + return 0x198 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_sw_int_w1s + * + * CGX CMR Interrupt Set Register This register sets interrupt bits. + */ +union cgxx_cmrx_sw_int_w1s { + u64 u; + struct cgxx_cmrx_sw_int_w1s_s { + u64 sw_set : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_cmrx_sw_int_w1s_s cn; */ +}; + +static inline u64 CGXX_CMRX_SW_INT_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_SW_INT_W1S(u64 a) +{ + return 0x188 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_channel + * + * CGX CMR Transmit-Channels Registers + */ +union cgxx_cmrx_tx_channel { + u64 u; + struct cgxx_cmrx_tx_channel_s { + u64 msk : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_cmrx_tx_channel_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_CHANNEL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_CHANNEL(u64 a) +{ + return 0x600 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_fifo_len + * + * CGX CMR Transmit Fifo Length Registers + */ +union cgxx_cmrx_tx_fifo_len { + u64 u; + struct cgxx_cmrx_tx_fifo_len_s { + u64 fifo_len : 14; + u64 lmac_idle : 1; + u64 fifo_e_len : 14; + u64 lmac_e_idle : 1; + u64 reserved_30_63 : 34; + } s; + /* struct cgxx_cmrx_tx_fifo_len_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_FIFO_LEN(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_FIFO_LEN(u64 a) +{ + return 0x618 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_hg2_status + * + * CGX CMR Transmit HiGig2 Status Registers + */ +union cgxx_cmrx_tx_hg2_status { + u64 u; + struct cgxx_cmrx_tx_hg2_status_s { + u64 lgtim2go : 16; + u64 xof : 16; + u64 reserved_32_63 : 32; + } s; + /* struct cgxx_cmrx_tx_hg2_status_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_HG2_STATUS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_HG2_STATUS(u64 a) +{ + return 0x610 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_merge_stat0 + * + * CGX TX Preemption Status Register 0 + */ +union cgxx_cmrx_tx_merge_stat0 { + u64 u; + struct cgxx_cmrx_tx_merge_stat0_s { + u64 ff_cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_merge_stat0_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_MERGE_STAT0(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_MERGE_STAT0(u64 a) +{ + return 0x160 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_ovr_bp + * + * CGX CMR Transmit-Channels Backpressure Override Registers + */ +union cgxx_cmrx_tx_ovr_bp { + u64 u; + struct cgxx_cmrx_tx_ovr_bp_s { + u64 tx_chan_bp : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_cmrx_tx_ovr_bp_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_OVR_BP(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_OVR_BP(u64 a) +{ + return 0x620 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_stat0 + * + * CGX CMR Transmit Statistics Registers 0 + */ +union cgxx_cmrx_tx_stat0 { + u64 u; + struct cgxx_cmrx_tx_stat0_s { + u64 xscol : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_stat0_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_STAT0(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_STAT0(u64 a) +{ + return 0x700 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_stat1 + * + * CGX CMR Transmit Statistics Registers 1 + */ +union cgxx_cmrx_tx_stat1 { + u64 u; + struct cgxx_cmrx_tx_stat1_s { + u64 xsdef : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_stat1_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_STAT1(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_STAT1(u64 a) +{ + return 0x708 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_stat10 + * + * CGX CMR Transmit Statistics Registers 10 + */ +union cgxx_cmrx_tx_stat10 { + u64 u; + struct cgxx_cmrx_tx_stat10_s { + u64 hist4 : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_stat10_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_STAT10(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_STAT10(u64 a) +{ + return 0x750 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_stat11 + * + * CGX CMR Transmit Statistics Registers 11 + */ +union cgxx_cmrx_tx_stat11 { + u64 u; + struct cgxx_cmrx_tx_stat11_s { + u64 hist5 : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_stat11_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_STAT11(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_STAT11(u64 a) +{ + return 0x758 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_stat12 + * + * CGX CMR Transmit Statistics Registers 12 + */ +union cgxx_cmrx_tx_stat12 { + u64 u; + struct cgxx_cmrx_tx_stat12_s { + u64 hist6 : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_stat12_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_STAT12(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_STAT12(u64 a) +{ + return 0x760 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_stat13 + * + * CGX CMR Transmit Statistics Registers 13 + */ +union cgxx_cmrx_tx_stat13 { + u64 u; + struct cgxx_cmrx_tx_stat13_s { + u64 hist7 : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_stat13_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_STAT13(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_STAT13(u64 a) +{ + return 0x768 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_stat14 + * + * CGX CMR Transmit Statistics Registers 14 + */ +union cgxx_cmrx_tx_stat14 { + u64 u; + struct cgxx_cmrx_tx_stat14_s { + u64 bcst : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_stat14_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_STAT14(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_STAT14(u64 a) +{ + return 0x770 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_stat15 + * + * CGX CMR Transmit Statistics Registers 15 + */ +union cgxx_cmrx_tx_stat15 { + u64 u; + struct cgxx_cmrx_tx_stat15_s { + u64 mcst : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_stat15_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_STAT15(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_STAT15(u64 a) +{ + return 0x778 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_stat16 + * + * CGX CMR Transmit Statistics Registers 16 + */ +union cgxx_cmrx_tx_stat16 { + u64 u; + struct cgxx_cmrx_tx_stat16_s { + u64 undflw : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_stat16_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_STAT16(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_STAT16(u64 a) +{ + return 0x780 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_stat17 + * + * CGX CMR Transmit Statistics Registers 17 + */ +union cgxx_cmrx_tx_stat17 { + u64 u; + struct cgxx_cmrx_tx_stat17_s { + u64 ctl : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_stat17_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_STAT17(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_STAT17(u64 a) +{ + return 0x788 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_stat2 + * + * CGX CMR Transmit Statistics Registers 2 + */ +union cgxx_cmrx_tx_stat2 { + u64 u; + struct cgxx_cmrx_tx_stat2_s { + u64 mcol : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_stat2_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_STAT2(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_STAT2(u64 a) +{ + return 0x710 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_stat3 + * + * CGX CMR Transmit Statistics Registers 3 + */ +union cgxx_cmrx_tx_stat3 { + u64 u; + struct cgxx_cmrx_tx_stat3_s { + u64 scol : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_stat3_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_STAT3(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_STAT3(u64 a) +{ + return 0x718 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_stat4 + * + * CGX CMR Transmit Statistics Registers 4 + */ +union cgxx_cmrx_tx_stat4 { + u64 u; + struct cgxx_cmrx_tx_stat4_s { + u64 octs : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_stat4_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_STAT4(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_STAT4(u64 a) +{ + return 0x720 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_stat5 + * + * CGX CMR Transmit Statistics Registers 5 + */ +union cgxx_cmrx_tx_stat5 { + u64 u; + struct cgxx_cmrx_tx_stat5_s { + u64 pkts : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_stat5_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_STAT5(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_STAT5(u64 a) +{ + return 0x728 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_stat6 + * + * CGX CMR Transmit Statistics Registers 6 + */ +union cgxx_cmrx_tx_stat6 { + u64 u; + struct cgxx_cmrx_tx_stat6_s { + u64 hist0 : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_stat6_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_STAT6(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_STAT6(u64 a) +{ + return 0x730 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_stat7 + * + * CGX CMR Transmit Statistics Registers 7 + */ +union cgxx_cmrx_tx_stat7 { + u64 u; + struct cgxx_cmrx_tx_stat7_s { + u64 hist1 : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_stat7_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_STAT7(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_STAT7(u64 a) +{ + return 0x738 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_stat8 + * + * CGX CMR Transmit Statistics Registers 8 + */ +union cgxx_cmrx_tx_stat8 { + u64 u; + struct cgxx_cmrx_tx_stat8_s { + u64 hist2 : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_stat8_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_STAT8(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_STAT8(u64 a) +{ + return 0x740 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_stat9 + * + * CGX CMR Transmit Statistics Registers 9 + */ +union cgxx_cmrx_tx_stat9 { + u64 u; + struct cgxx_cmrx_tx_stat9_s { + u64 hist3 : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_stat9_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_STAT9(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_STAT9(u64 a) +{ + return 0x748 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_cmr#_tx_stat_pri#_xoff + * + * CGX CMR TX XON to XOFF transition Registers + */ +union cgxx_cmrx_tx_stat_prix_xoff { + u64 u; + struct cgxx_cmrx_tx_stat_prix_xoff_s { + u64 cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmrx_tx_stat_prix_xoff_s cn; */ +}; + +static inline u64 CGXX_CMRX_TX_STAT_PRIX_XOFF(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMRX_TX_STAT_PRIX_XOFF(u64 a, u64 b) +{ + return 0x800 + 0x40000 * a + 8 * b; +} + +/** + * Register (RSL) cgx#_cmr_bad + * + * CGX CMR Bad Registers + */ +union cgxx_cmr_bad { + u64 u; + struct cgxx_cmr_bad_s { + u64 rxb_nxl : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_cmr_bad_s cn; */ +}; + +static inline u64 CGXX_CMR_BAD(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_BAD(void) +{ + return 0x1020; +} + +/** + * Register (RSL) cgx#_cmr_chan_msk_and + * + * CGX CMR Backpressure Channel Mask AND Registers + */ +union cgxx_cmr_chan_msk_and { + u64 u; + struct cgxx_cmr_chan_msk_and_s { + u64 msk_and : 64; + } s; + /* struct cgxx_cmr_chan_msk_and_s cn; */ +}; + +static inline u64 CGXX_CMR_CHAN_MSK_AND(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_CHAN_MSK_AND(void) +{ + return 0x110; +} + +/** + * Register (RSL) cgx#_cmr_chan_msk_or + * + * CGX Backpressure Channel Mask OR Registers + */ +union cgxx_cmr_chan_msk_or { + u64 u; + struct cgxx_cmr_chan_msk_or_s { + u64 msk_or : 64; + } s; + /* struct cgxx_cmr_chan_msk_or_s cn; */ +}; + +static inline u64 CGXX_CMR_CHAN_MSK_OR(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_CHAN_MSK_OR(void) +{ + return 0x118; +} + +/** + * Register (RSL) cgx#_cmr_eco + * + * INTERNAL: CGX ECO Registers + */ +union cgxx_cmr_eco { + u64 u; + struct cgxx_cmr_eco_s { + u64 eco_rw : 32; + u64 eco_ro : 32; + } s; + /* struct cgxx_cmr_eco_s cn; */ +}; + +static inline u64 CGXX_CMR_ECO(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_ECO(void) +{ + return 0x1028; +} + +/** + * Register (RSL) cgx#_cmr_global_config + * + * CGX CMR Global Configuration Register These registers configure the + * global CMR, PCS, and MAC. + */ +union cgxx_cmr_global_config { + u64 u; + struct cgxx_cmr_global_config_s { + u64 pmux_sds_sel : 1; + u64 cgx_clk_enable : 1; + u64 cmr_x2p_reset : 3; + u64 interleave_mode : 1; + u64 fcs_strip : 1; + u64 ncsi_lmac_id : 2; + u64 cmr_ncsi_drop : 1; + u64 cmr_ncsi_reset : 1; + u64 cmr_ncsi_tag_cnt : 13; + u64 cmr_clken_ovrd : 1; + u64 reserved_25_63 : 39; + } s; + /* struct cgxx_cmr_global_config_s cn; */ +}; + +static inline u64 CGXX_CMR_GLOBAL_CONFIG(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_GLOBAL_CONFIG(void) +{ + return 8; +} + +/** + * Register (RSL) cgx#_cmr_mem_int + * + * CGX CMR Memory Interrupt Register + */ +union cgxx_cmr_mem_int { + u64 u; + struct cgxx_cmr_mem_int_s { + u64 gmp_in_overfl : 1; + u64 smu_in_overfl : 1; + u64 reserved_2_63 : 62; + } s; + /* struct cgxx_cmr_mem_int_s cn; */ +}; + +static inline u64 CGXX_CMR_MEM_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_MEM_INT(void) +{ + return 0x10; +} + +/** + * Register (RSL) cgx#_cmr_mem_int_ena_w1c + * + * CGX CMR Memory Interrupt Enable Clear Register This register clears + * interrupt enable bits. + */ +union cgxx_cmr_mem_int_ena_w1c { + u64 u; + struct cgxx_cmr_mem_int_ena_w1c_s { + u64 gmp_in_overfl : 1; + u64 smu_in_overfl : 1; + u64 reserved_2_63 : 62; + } s; + /* struct cgxx_cmr_mem_int_ena_w1c_s cn; */ +}; + +static inline u64 CGXX_CMR_MEM_INT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_MEM_INT_ENA_W1C(void) +{ + return 0x20; +} + +/** + * Register (RSL) cgx#_cmr_mem_int_ena_w1s + * + * CGX CMR Memory Interrupt Enable Set Register This register sets + * interrupt enable bits. + */ +union cgxx_cmr_mem_int_ena_w1s { + u64 u; + struct cgxx_cmr_mem_int_ena_w1s_s { + u64 gmp_in_overfl : 1; + u64 smu_in_overfl : 1; + u64 reserved_2_63 : 62; + } s; + /* struct cgxx_cmr_mem_int_ena_w1s_s cn; */ +}; + +static inline u64 CGXX_CMR_MEM_INT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_MEM_INT_ENA_W1S(void) +{ + return 0x28; +} + +/** + * Register (RSL) cgx#_cmr_mem_int_w1s + * + * CGX CMR Memory Interrupt Set Register This register sets interrupt + * bits. + */ +union cgxx_cmr_mem_int_w1s { + u64 u; + struct cgxx_cmr_mem_int_w1s_s { + u64 gmp_in_overfl : 1; + u64 smu_in_overfl : 1; + u64 reserved_2_63 : 62; + } s; + /* struct cgxx_cmr_mem_int_w1s_s cn; */ +}; + +static inline u64 CGXX_CMR_MEM_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_MEM_INT_W1S(void) +{ + return 0x18; +} + +/** + * Register (RSL) cgx#_cmr_nic_nxc_adr + * + * CGX CMR NIC NXC Exception Registers + */ +union cgxx_cmr_nic_nxc_adr { + u64 u; + struct cgxx_cmr_nic_nxc_adr_s { + u64 channel : 12; + u64 lmac_id : 4; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_cmr_nic_nxc_adr_s cn; */ +}; + +static inline u64 CGXX_CMR_NIC_NXC_ADR(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_NIC_NXC_ADR(void) +{ + return 0x1030; +} + +/** + * Register (RSL) cgx#_cmr_nix0_nxc_adr + * + * CGX CMR NIX0 NXC Exception Registers + */ +union cgxx_cmr_nix0_nxc_adr { + u64 u; + struct cgxx_cmr_nix0_nxc_adr_s { + u64 channel : 12; + u64 lmac_id : 4; + u64 channel_e : 12; + u64 lmac_e_id : 4; + u64 reserved_32_63 : 32; + } s; + /* struct cgxx_cmr_nix0_nxc_adr_s cn; */ +}; + +static inline u64 CGXX_CMR_NIX0_NXC_ADR(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_NIX0_NXC_ADR(void) +{ + return 0x1038; +} + +/** + * Register (RSL) cgx#_cmr_nix1_nxc_adr + * + * CGX CMR NIX1 NXC Exception Registers + */ +union cgxx_cmr_nix1_nxc_adr { + u64 u; + struct cgxx_cmr_nix1_nxc_adr_s { + u64 channel : 12; + u64 lmac_id : 4; + u64 channel_e : 12; + u64 lmac_e_id : 4; + u64 reserved_32_63 : 32; + } s; + /* struct cgxx_cmr_nix1_nxc_adr_s cn; */ +}; + +static inline u64 CGXX_CMR_NIX1_NXC_ADR(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_NIX1_NXC_ADR(void) +{ + return 0x1040; +} + +/** + * Register (RSL) cgx#_cmr_p2x#_count + * + * CGX P2X Activity Register + */ +union cgxx_cmr_p2xx_count { + u64 u; + struct cgxx_cmr_p2xx_count_s { + u64 p2x_cnt : 64; + } s; + /* struct cgxx_cmr_p2xx_count_s cn; */ +}; + +static inline u64 CGXX_CMR_P2XX_COUNT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_P2XX_COUNT(u64 a) +{ + return 0x168 + 0x1000 * a; +} + +/** + * Register (RSL) cgx#_cmr_rx_dmac#_cam0 + * + * CGX CMR Receive CAM Registers These registers provide access to the 32 + * DMAC CAM0 entries in CGX, for use by X2P/NIX bound traffic. + */ +union cgxx_cmr_rx_dmacx_cam0 { + u64 u; + struct cgxx_cmr_rx_dmacx_cam0_s { + u64 adr : 48; + u64 en : 1; + u64 id : 2; + u64 reserved_51_63 : 13; + } s; + /* struct cgxx_cmr_rx_dmacx_cam0_s cn; */ +}; + +static inline u64 CGXX_CMR_RX_DMACX_CAM0(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_RX_DMACX_CAM0(u64 a) +{ + return 0x200 + 8 * a; +} + +/** + * Register (RSL) cgx#_cmr_rx_dmac#_cam1 + * + * CGX CMR Receive CAM Registers These registers provide access to the 32 + * DMAC CAM entries in CGX for use by NCSI bound traffic. See + * CGX()_CMR_GLOBAL_CONFIG[NCSI_LMAC_ID] and CGX()_CMR_RX_STEERING1() + * registers. + */ +union cgxx_cmr_rx_dmacx_cam1 { + u64 u; + struct cgxx_cmr_rx_dmacx_cam1_s { + u64 adr : 48; + u64 en : 1; + u64 id : 2; + u64 reserved_51_63 : 13; + } s; + /* struct cgxx_cmr_rx_dmacx_cam1_s cn; */ +}; + +static inline u64 CGXX_CMR_RX_DMACX_CAM1(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_RX_DMACX_CAM1(u64 a) +{ + return 0x400 + 8 * a; +} + +/** + * Register (RSL) cgx#_cmr_rx_lmacs + * + * CGX CMR Receive Logical MACs Registers + */ +union cgxx_cmr_rx_lmacs { + u64 u; + struct cgxx_cmr_rx_lmacs_s { + u64 lmacs : 3; + u64 reserved_3_63 : 61; + } s; + /* struct cgxx_cmr_rx_lmacs_s cn; */ +}; + +static inline u64 CGXX_CMR_RX_LMACS(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_RX_LMACS(void) +{ + return 0x128; +} + +/** + * Register (RSL) cgx#_cmr_rx_ovr_bp + * + * CGX CMR Receive-Ports Backpressure Override Registers Per-LMAC + * backpressure override register. For SMU, CGX()_CMR_RX_OVR_BP[EN]\<0\> + * must be set to one and CGX()_CMR_RX_OVR_BP[BP]\<0\> must be cleared to + * zero (to forcibly disable hardware-automatic 802.3 PAUSE packet + * generation) with the HiGig2 Protocol when + * CGX()_SMU()_HG2_CONTROL[HG2TX_EN]=0. (The HiGig2 protocol is indicated + * by CGX()_SMU()_TX_CTL[HG_EN]=1 and CGX()_SMU()_RX_UDD_SKP[LEN]=16). + * Hardware can only auto-generate backpressure through HiGig2 messages + * (optionally, when CGX()_SMU()_HG2_CONTROL[HG2TX_EN]=1) with the HiGig2 + * protocol. + */ +union cgxx_cmr_rx_ovr_bp { + u64 u; + struct cgxx_cmr_rx_ovr_bp_s { + u64 ign_fifo_bp : 4; + u64 bp : 4; + u64 en : 4; + u64 reserved_12_63 : 52; + } s; + /* struct cgxx_cmr_rx_ovr_bp_s cn; */ +}; + +static inline u64 CGXX_CMR_RX_OVR_BP(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_RX_OVR_BP(void) +{ + return 0x130; +} + +/** + * Register (RSL) cgx#_cmr_rx_stat10 + * + * CGX Receive Status Register 10 These registers provide a count of + * octets of filtered DMAC1 or VLAN STEERING1 packets. + */ +union cgxx_cmr_rx_stat10 { + u64 u; + struct cgxx_cmr_rx_stat10_s { + u64 cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmr_rx_stat10_s cn; */ +}; + +static inline u64 CGXX_CMR_RX_STAT10(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_RX_STAT10(void) +{ + return 0xc0; +} + +/** + * Register (RSL) cgx#_cmr_rx_stat11 + * + * CGX Receive Status Register 11 This registers provides a count of + * packets dropped at the NCSI interface. This includes drops due to + * CGX()_CMR_GLOBAL_CONFIG[CMR_NCSI_DROP] or NCSI FIFO full. The count of + * dropped NCSI packets is not accounted for in any other stats + * registers. + */ +union cgxx_cmr_rx_stat11 { + u64 u; + struct cgxx_cmr_rx_stat11_s { + u64 cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmr_rx_stat11_s cn; */ +}; + +static inline u64 CGXX_CMR_RX_STAT11(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_RX_STAT11(void) +{ + return 0xc8; +} + +/** + * Register (RSL) cgx#_cmr_rx_stat12 + * + * CGX Receive Status Register 12 This register provide a count of octets + * of dropped at the NCSI interface. + */ +union cgxx_cmr_rx_stat12 { + u64 u; + struct cgxx_cmr_rx_stat12_s { + u64 cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmr_rx_stat12_s cn; */ +}; + +static inline u64 CGXX_CMR_RX_STAT12(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_RX_STAT12(void) +{ + return 0xd0; +} + +/** + * Register (RSL) cgx#_cmr_rx_stat9 + * + * CGX Receive Status Register 9 These registers provide a count of all + * received packets that were dropped by the DMAC1 or VLAN STEERING1 + * filter. Packets that are dropped by the DMAC1 or VLAN STEERING1 + * filters are counted here regardless of whether they were ERR packets, + * but does not include those reported in CGX()_CMR()_RX_STAT6. 16B + * packets or smaller (20B in case of FCS strip) as the result of + * truncation or other means are not dropped by CGX (unless filter and + * decision is also asserted) and will never appear in this count. Should + * the MAC signal to the CMR that the packet be filtered upon decision + * before the end of packet, then STAT9 and STAT10 will not be updated. + */ +union cgxx_cmr_rx_stat9 { + u64 u; + struct cgxx_cmr_rx_stat9_s { + u64 cnt : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_cmr_rx_stat9_s cn; */ +}; + +static inline u64 CGXX_CMR_RX_STAT9(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_RX_STAT9(void) +{ + return 0xb8; +} + +/** + * Register (RSL) cgx#_cmr_rx_steering0# + * + * CGX CMR Receive Steering0 Registers These registers, along with + * CGX()_CMR_RX_STEERING_VETYPE0(), provide eight filters for identifying + * and steering receive traffic to X2P/NIX. Received packets are only + * passed to X2P/NIX when the DMAC0 filter result is ACCEPT and STEERING0 + * filter result is PASS. See also CGX()_CMR()_RX_DMAC_CTL0. Internal: + * "* ALGORITHM \ rx_steering(uint48 pkt_dmac, uint16 pkt_etype, + * uint16 pkt_vlan_id) { for (int i = 0; i \< 8; i++) { steer = + * CGX()_CMR_RX_STEERING0(i); vetype = + * CGX()_CMR_RX_STEERING_VETYPE0(i); if (steer[MCST_EN] || + * steer[DMAC_EN] || vetype[VLAN_EN] || vetype[VLAN_TAG_EN]) { + * // Filter is enabled. if ( (!steer[MCST_EN] || + * is_mcst(pkt_dmac)) && (!steer[DMAC_EN] || pkt_dmac == + * steer[DMAC]) && (!vetype[VLAN_EN] || pkt_vlan_id == + * vetype[VLAN_ID]) && (!vetype[VLAN_TAG_EN] || pkt_etype == + * vetype[VLAN_ETYPE]) ) { // Filter match (all + * enabled matching criteria are met). return steer[PASS]; + * } } } return CGX()_CMR_RX_STEERING_DEFAULT0[PASS]; // No + * match } \" + */ +union cgxx_cmr_rx_steering0x { + u64 u; + struct cgxx_cmr_rx_steering0x_s { + u64 dmac : 48; + u64 dmac_en : 1; + u64 mcst_en : 1; + u64 pass : 1; + u64 reserved_51_63 : 13; + } s; + /* struct cgxx_cmr_rx_steering0x_s cn; */ +}; + +static inline u64 CGXX_CMR_RX_STEERING0X(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_RX_STEERING0X(u64 a) +{ + return 0x300 + 8 * a; +} + +/** + * Register (RSL) cgx#_cmr_rx_steering1# + * + * CGX CMR Receive Steering1 Registers These registers, along with + * CGX()_CMR_RX_STEERING_VETYPE1(), provide eight filters for identifying + * and steering NCSI receive traffic. Received packets are only passed to + * NCSI when the DMAC1 filter result is ACCEPT and STEERING1 filter + * result is PASS. See also CGX()_CMR_RX_DMAC()_CAM1 and + * CGX()_CMR_RX_STEERING1(). For use with the LMAC associated with NCSI. + * See CGX()_CMR_GLOBAL_CONFIG[NCSI_LMAC_ID]. Internal: ALGORITHM: See + * CGX()_CMR_RX_STEERING0(). + */ +union cgxx_cmr_rx_steering1x { + u64 u; + struct cgxx_cmr_rx_steering1x_s { + u64 dmac : 48; + u64 dmac_en : 1; + u64 mcst_en : 1; + u64 pass : 1; + u64 reserved_51_63 : 13; + } s; + /* struct cgxx_cmr_rx_steering1x_s cn; */ +}; + +static inline u64 CGXX_CMR_RX_STEERING1X(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_RX_STEERING1X(u64 a) +{ + return 0x500 + 8 * a; +} + +/** + * Register (RSL) cgx#_cmr_rx_steering_default0 + * + * CGX CMR Receive Steering Default0 Destination Register For determining + * destination of traffic that does not meet matching algorithm described + * in registers CGX()_CMR_RX_STEERING0() and + * CGX()_CMR_RX_STEERING_VETYPE0(). All 16B packets or smaller (20B in + * case of FCS strip) as the result of truncation will steer to default + * destination + */ +union cgxx_cmr_rx_steering_default0 { + u64 u; + struct cgxx_cmr_rx_steering_default0_s { + u64 pass : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_cmr_rx_steering_default0_s cn; */ +}; + +static inline u64 CGXX_CMR_RX_STEERING_DEFAULT0(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_RX_STEERING_DEFAULT0(void) +{ + return 0x3f0; +} + +/** + * Register (RSL) cgx#_cmr_rx_steering_default1 + * + * CGX CMR Receive Steering Default1 Destination Register For use with + * the lmac_id associated with NCSI. See + * CGX()_CMR_GLOBAL_CONFIG[NCSI_LMAC_ID]. For determining destination of + * traffic that does not meet matching algorithm described in registers + * CGX()_CMR_RX_STEERING1() and CGX()_CMR_RX_STEERING_VETYPE1(). All 16B + * packets or smaller (20B in case of FCS strip) as the result of + * truncation will steer to default destination + */ +union cgxx_cmr_rx_steering_default1 { + u64 u; + struct cgxx_cmr_rx_steering_default1_s { + u64 pass : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_cmr_rx_steering_default1_s cn; */ +}; + +static inline u64 CGXX_CMR_RX_STEERING_DEFAULT1(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_RX_STEERING_DEFAULT1(void) +{ + return 0x5e0; +} + +/** + * Register (RSL) cgx#_cmr_rx_steering_vetype0# + * + * CGX CMR Receive VLAN Ethertype1 Register These registers, along with + * CGX()_CMR_RX_STEERING0(), provide eight filters for identifying and + * steering X2P/NIX receive traffic. + */ +union cgxx_cmr_rx_steering_vetype0x { + u64 u; + struct cgxx_cmr_rx_steering_vetype0x_s { + u64 vlan_etype : 16; + u64 vlan_tag_en : 1; + u64 vlan_id : 12; + u64 vlan_en : 1; + u64 reserved_30_63 : 34; + } s; + /* struct cgxx_cmr_rx_steering_vetype0x_s cn; */ +}; + +static inline u64 CGXX_CMR_RX_STEERING_VETYPE0X(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_RX_STEERING_VETYPE0X(u64 a) +{ + return 0x380 + 8 * a; +} + +/** + * Register (RSL) cgx#_cmr_rx_steering_vetype1# + * + * CGX CMR Receive VLAN Ethertype1 Register For use with the lmac_id + * associated with NCSI. See CGX()_CMR_GLOBAL_CONFIG[NCSI_LMAC_ID]. These + * registers, along with CGX()_CMR_RX_STEERING1(), provide eight filters + * for identifying and steering NCSI receive traffic. + */ +union cgxx_cmr_rx_steering_vetype1x { + u64 u; + struct cgxx_cmr_rx_steering_vetype1x_s { + u64 vlan_etype : 16; + u64 vlan_tag_en : 1; + u64 vlan_id : 12; + u64 vlan_en : 1; + u64 reserved_30_63 : 34; + } s; + /* struct cgxx_cmr_rx_steering_vetype1x_s cn; */ +}; + +static inline u64 CGXX_CMR_RX_STEERING_VETYPE1X(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_RX_STEERING_VETYPE1X(u64 a) +{ + return 0x580 + 8 * a; +} + +/** + * Register (RSL) cgx#_cmr_tx_lmacs + * + * CGX CMR Transmit Logical MACs Registers This register sets the number + * of LMACs allowed on the TX interface. The value is important for + * defining the partitioning of the transmit FIFO. + */ +union cgxx_cmr_tx_lmacs { + u64 u; + struct cgxx_cmr_tx_lmacs_s { + u64 lmacs : 3; + u64 reserved_3_63 : 61; + } s; + /* struct cgxx_cmr_tx_lmacs_s cn; */ +}; + +static inline u64 CGXX_CMR_TX_LMACS(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_TX_LMACS(void) +{ + return 0x1000; +} + +/** + * Register (RSL) cgx#_cmr_x2p#_count + * + * CGX X2P Activity Register + */ +union cgxx_cmr_x2px_count { + u64 u; + struct cgxx_cmr_x2px_count_s { + u64 x2p_cnt : 64; + } s; + /* struct cgxx_cmr_x2px_count_s cn; */ +}; + +static inline u64 CGXX_CMR_X2PX_COUNT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CMR_X2PX_COUNT(u64 a) +{ + return 0x170 + 0x1000 * a; +} + +/** + * Register (RSL) cgx#_const + * + * CGX CONST Registers This register contains constants for software + * discovery. + */ +union cgxx_const { + u64 u; + struct cgxx_const_s { + u64 tx_fifosz : 24; + u64 lmacs : 8; + u64 rx_fifosz : 24; + u64 reserved_56_63 : 8; + } s; + /* struct cgxx_const_s cn; */ +}; + +static inline u64 CGXX_CONST(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CONST(void) +{ + return 0x2000; +} + +/** + * Register (RSL) cgx#_const1 + * + * CGX CONST1 Registers This register contains constants for software + * discovery. + */ +union cgxx_const1 { + u64 u; + struct cgxx_const1_s { + u64 types : 11; + u64 res_types : 21; + u64 reserved_32_63 : 32; + } s; + /* struct cgxx_const1_s cn; */ +}; + +static inline u64 CGXX_CONST1(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_CONST1(void) +{ + return 0x2008; +} + +/** + * Register (RSL) cgx#_gmp_gmi#_rx_wol_ctrl0 + * + * CGX GMP GMI RX Wake-on-LAN Control 0 Registers + */ +union cgxx_gmp_gmix_rx_wol_ctrl0 { + u64 u; + struct cgxx_gmp_gmix_rx_wol_ctrl0_s { + u64 dmac : 48; + u64 pswd_len : 4; + u64 reserved_52_63 : 12; + } s; + /* struct cgxx_gmp_gmix_rx_wol_ctrl0_s cn; */ +}; + +static inline u64 CGXX_GMP_GMIX_RX_WOL_CTRL0(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMIX_RX_WOL_CTRL0(u64 a) +{ + return 0x38a00 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi#_rx_wol_ctrl1 + * + * CGX GMP GMI RX Wake-on-LAN Control 1 Registers + */ +union cgxx_gmp_gmix_rx_wol_ctrl1 { + u64 u; + struct cgxx_gmp_gmix_rx_wol_ctrl1_s { + u64 pswd : 64; + } s; + /* struct cgxx_gmp_gmix_rx_wol_ctrl1_s cn; */ +}; + +static inline u64 CGXX_GMP_GMIX_RX_WOL_CTRL1(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMIX_RX_WOL_CTRL1(u64 a) +{ + return 0x38a08 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi#_tx_eee + * + * INTERNAL: CGX GMP GMI TX EEE Configure Registers Reserved. Internal: + * These registers control when GMP GMI TX requests to enter or exist + * LPI. Those registers take effect only when EEE is supported and + * enabled for a given LMAC. + */ +union cgxx_gmp_gmix_tx_eee { + u64 u; + struct cgxx_gmp_gmix_tx_eee_s { + u64 idle_thresh : 28; + u64 reserved_28 : 1; + u64 force_lpi : 1; + u64 wakeup : 1; + u64 auto_lpi : 1; + u64 idle_cnt : 28; + u64 tx_lpi : 1; + u64 tx_lpi_wait : 1; + u64 sync_status_lpi_enable : 1; + u64 reserved_63 : 1; + } s; + /* struct cgxx_gmp_gmix_tx_eee_s cn; */ +}; + +static inline u64 CGXX_GMP_GMIX_TX_EEE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMIX_TX_EEE(u64 a) +{ + return 0x38800 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi#_tx_eee_cfg1 + * + * INTERNAL: CGX GMP GMI TX EEE Configure More Configuration Registers + * Reserved. Internal: Controls the GMP exiting of LPI and starting to + * send data. + */ +union cgxx_gmp_gmix_tx_eee_cfg1 { + u64 u; + struct cgxx_gmp_gmix_tx_eee_cfg1_s { + u64 wake2data_time : 24; + u64 reserved_24_35 : 12; + u64 tx_eee_enable : 1; + u64 reserved_37_39 : 3; + u64 sync2lpi_time : 21; + u64 reserved_61_63 : 3; + } s; + struct cgxx_gmp_gmix_tx_eee_cfg1_cn { + u64 wake2data_time : 24; + u64 reserved_24_31 : 8; + u64 reserved_32_35 : 4; + u64 tx_eee_enable : 1; + u64 reserved_37_39 : 3; + u64 sync2lpi_time : 21; + u64 reserved_61_63 : 3; + } cn; +}; + +static inline u64 CGXX_GMP_GMIX_TX_EEE_CFG1(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMIX_TX_EEE_CFG1(u64 a) +{ + return 0x38808 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi#_wol_int + * + * CGX GMP GMI RX WOL Interrupt Registers These registers allow WOL + * interrupts to be sent to the control processor. + */ +union cgxx_gmp_gmix_wol_int { + u64 u; + struct cgxx_gmp_gmix_wol_int_s { + u64 wol_rcvd : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_gmp_gmix_wol_int_s cn; */ +}; + +static inline u64 CGXX_GMP_GMIX_WOL_INT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMIX_WOL_INT(u64 a) +{ + return 0x38a80 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi#_wol_int_ena_w1c + * + * CGX GMP GMI RX WOL Interrupt Enable Clear Registers This register + * clears interrupt enable bits. + */ +union cgxx_gmp_gmix_wol_int_ena_w1c { + u64 u; + struct cgxx_gmp_gmix_wol_int_ena_w1c_s { + u64 wol_rcvd : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_gmp_gmix_wol_int_ena_w1c_s cn; */ +}; + +static inline u64 CGXX_GMP_GMIX_WOL_INT_ENA_W1C(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMIX_WOL_INT_ENA_W1C(u64 a) +{ + return 0x38a90 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi#_wol_int_ena_w1s + * + * CGX GMP GMI RX WOL Interrupt Enable Set Registers This register sets + * interrupt enable bits. + */ +union cgxx_gmp_gmix_wol_int_ena_w1s { + u64 u; + struct cgxx_gmp_gmix_wol_int_ena_w1s_s { + u64 wol_rcvd : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_gmp_gmix_wol_int_ena_w1s_s cn; */ +}; + +static inline u64 CGXX_GMP_GMIX_WOL_INT_ENA_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMIX_WOL_INT_ENA_W1S(u64 a) +{ + return 0x38a98 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi#_wol_int_w1s + * + * CGX GMP GMI RX WOL Interrupt Set Registers This register sets + * interrupt bits. + */ +union cgxx_gmp_gmix_wol_int_w1s { + u64 u; + struct cgxx_gmp_gmix_wol_int_w1s_s { + u64 wol_rcvd : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_gmp_gmix_wol_int_w1s_s cn; */ +}; + +static inline u64 CGXX_GMP_GMIX_WOL_INT_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMIX_WOL_INT_W1S(u64 a) +{ + return 0x38a88 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_prt#_cfg + * + * CGX GMP GMI LMAC Configuration Registers This register controls the + * configuration of the LMAC. + */ +union cgxx_gmp_gmi_prtx_cfg { + u64 u; + struct cgxx_gmp_gmi_prtx_cfg_s { + u64 reserved_0 : 1; + u64 speed : 1; + u64 duplex : 1; + u64 slottime : 1; + u64 reserved_4_7 : 4; + u64 speed_msb : 1; + u64 reserved_9_11 : 3; + u64 rx_idle : 1; + u64 tx_idle : 1; + u64 reserved_14_63 : 50; + } s; + /* struct cgxx_gmp_gmi_prtx_cfg_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_PRTX_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_PRTX_CFG(u64 a) +{ + return 0x38020 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_rx#_decision + * + * CGX GMP Packet-Decision Registers This register specifies the byte + * count used to determine when to accept or to filter a packet. As each + * byte in a packet is received by GMI, the L2 byte count is compared + * against [CNT]. In normal operation, the L2 header begins after the + * PREAMBLE + SFD (CGX()_GMP_GMI_RX()_FRM_CTL[PRE_CHK] = 1) and any + * optional UDD skip data (CGX()_GMP_GMI_RX()_UDD_SKP[LEN]). Internal: + * Notes: As each byte in a packet is received by GMI, the L2 byte count + * is compared against the [CNT]. The L2 byte count is the number of + * bytes from the beginning of the L2 header (DMAC). In normal + * operation, the L2 header begins after the PREAMBLE+SFD + * (CGX()_GMP_GMI_RX()_FRM_CTL[PRE_CHK]=1) and any optional UDD skip data + * (CGX()_GMP_GMI_RX()_UDD_SKP[LEN]). When + * CGX()_GMP_GMI_RX()_FRM_CTL[PRE_CHK] is clear, PREAMBLE+SFD are + * prepended to the packet and would require UDD skip length to account + * for them. Full Duplex: _ L2 Size \< [CNT] - Accept packet. No + * filtering is applied. _ L2 Size \>= [CNT] - Apply filter. Accept + * packet based on PAUSE packet filter. Half Duplex: _ L2 Size \< + * [CNT] - Drop packet. Packet is unconditionally dropped. _ L2 Size + * \>= [CNT] - Accept packet. where L2_size = MAX(0, total_packet_size - + * CGX()_GMP_GMI_RX()_UDD_SKP[LEN] - + * ((CGX()_GMP_GMI_RX()_FRM_CTL[PRE_CHK]==1)*8)). + */ +union cgxx_gmp_gmi_rxx_decision { + u64 u; + struct cgxx_gmp_gmi_rxx_decision_s { + u64 cnt : 5; + u64 reserved_5_63 : 59; + } s; + /* struct cgxx_gmp_gmi_rxx_decision_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_RXX_DECISION(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_RXX_DECISION(u64 a) +{ + return 0x38040 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_rx#_frm_chk + * + * CGX GMP Frame Check Registers + */ +union cgxx_gmp_gmi_rxx_frm_chk { + u64 u; + struct cgxx_gmp_gmi_rxx_frm_chk_s { + u64 minerr : 1; + u64 carext : 1; + u64 reserved_2 : 1; + u64 jabber : 1; + u64 fcserr : 1; + u64 reserved_5_6 : 2; + u64 rcverr : 1; + u64 skperr : 1; + u64 reserved_9_63 : 55; + } s; + /* struct cgxx_gmp_gmi_rxx_frm_chk_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_RXX_FRM_CHK(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_RXX_FRM_CHK(u64 a) +{ + return 0x38030 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_rx#_frm_ctl + * + * CGX GMP Frame Control Registers This register controls the handling of + * the frames. The [CTL_BCK] and [CTL_DRP] bits control how the hardware + * handles incoming PAUSE packets. The most common modes of operation: _ + * [CTL_BCK] = 1, [CTL_DRP] = 1: hardware handles everything. _ [CTL_BCK] + * = 0, [CTL_DRP] = 0: software sees all PAUSE frames. _ [CTL_BCK] = 0, + * [CTL_DRP] = 1: all PAUSE frames are completely ignored. These control + * bits should be set to [CTL_BCK] = 0, [CTL_DRP] = 0 in half-duplex + * mode. Since PAUSE packets only apply to full duplex operation, any + * PAUSE packet would constitute an exception which should be handled by + * the processing cores. PAUSE packets should not be forwarded. + * Internal: Notes: [PRE_STRP]: When [PRE_CHK] is set (indicating that + * the PREAMBLE will be sent), [PRE_STRP] determines if the PREAMBLE+SFD + * bytes are thrown away or sent to the Octane core as part of the + * packet. In either mode, the PREAMBLE+SFD bytes are not counted toward + * the packet size when checking against the MIN and MAX bounds. + * Furthermore, the bytes are skipped when locating the start of the L2 + * header for DMAC and Control frame recognition. + */ +union cgxx_gmp_gmi_rxx_frm_ctl { + u64 u; + struct cgxx_gmp_gmi_rxx_frm_ctl_s { + u64 pre_chk : 1; + u64 pre_strp : 1; + u64 ctl_drp : 1; + u64 ctl_bck : 1; + u64 ctl_mcst : 1; + u64 ctl_smac : 1; + u64 pre_free : 1; + u64 reserved_7_8 : 2; + u64 pre_align : 1; + u64 null_dis : 1; + u64 reserved_11 : 1; + u64 ptp_mode : 1; + u64 rx_fc_type : 1; + u64 reserved_14_63 : 50; + } s; + struct cgxx_gmp_gmi_rxx_frm_ctl_cn { + u64 pre_chk : 1; + u64 pre_strp : 1; + u64 ctl_drp : 1; + u64 ctl_bck : 1; + u64 ctl_mcst : 1; + u64 ctl_smac : 1; + u64 pre_free : 1; + u64 reserved_7 : 1; + u64 reserved_8 : 1; + u64 pre_align : 1; + u64 null_dis : 1; + u64 reserved_11 : 1; + u64 ptp_mode : 1; + u64 rx_fc_type : 1; + u64 reserved_14_63 : 50; + } cn; +}; + +static inline u64 CGXX_GMP_GMI_RXX_FRM_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_RXX_FRM_CTL(u64 a) +{ + return 0x38028 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_rx#_ifg + * + * CGX GMI Minimum Interframe-Gap Cycles Registers This register + * specifies the minimum number of interframe-gap (IFG) cycles between + * packets. + */ +union cgxx_gmp_gmi_rxx_ifg { + u64 u; + struct cgxx_gmp_gmi_rxx_ifg_s { + u64 ifg : 4; + u64 reserved_4_63 : 60; + } s; + /* struct cgxx_gmp_gmi_rxx_ifg_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_RXX_IFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_RXX_IFG(u64 a) +{ + return 0x38058 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_rx#_int + * + * CGX GMP GMI RX Interrupt Registers These registers allow interrupts to + * be sent to the control processor. * Exception conditions \<10:0\> can + * also set the rcv/opcode in the received packet's work-queue entry. + * CGX()_GMP_GMI_RX()_FRM_CHK provides a bit mask for configuring which + * conditions set the error. In half duplex operation, the expectation is + * that collisions will appear as either MINERR or CAREXT errors. + * Internal: Notes: (1) exception conditions 10:0 can also set the + * rcv/opcode in the received packet's workQ entry. The + * CGX()_GMP_GMI_RX()_FRM_CHK register provides a bit mask for + * configuring which conditions set the error. (2) in half duplex + * operation, the expectation is that collisions will appear as either + * MINERR o r CAREXT errors. (3) JABBER An RX jabber error indicates + * that a packet was received which is longer than the maximum allowed + * packet as defined by the system. GMI will truncate the packet at the + * JABBER count. Failure to do so could lead to system instabilty. (4) + * NIBERR This error is illegal at 1000Mbs speeds + * (CGX()_GMP_GMI_PRT()_CFG[SPEED]==0) and will never assert. (5) MINERR + * total frame DA+SA+TL+DATA+PAD+FCS \< 64 (6) ALNERR Indicates that the + * packet received was not an integer number of bytes. If FCS checking + * is enabled, ALNERR will only assert if the FCS is bad. If FCS + * checking is disabled, ALNERR will assert in all non-integer frame + * cases. (7) Collisions Collisions can only occur in half-duplex mode. + * A collision is assumed by the receiver when the slottime + * (CGX()_GMP_GMI_PRT()_CFG[SLOTTIME]) is not satisfied. In 10/100 mode, + * this will result in a frame \< SLOTTIME. In 1000 mode, it could + * result either in frame \< SLOTTIME or a carrier extend error with the + * SLOTTIME. These conditions are visible by... . transfer ended before + * slottime COLDET . carrier extend error CAREXT (A) LENERR + * Length errors occur when the received packet does not match the length + * field. LENERR is only checked for packets between 64 and 1500 bytes. + * For untagged frames, the length must exact match. For tagged frames + * the length or length+4 must match. (B) PCTERR checks that the frame + * begins with a valid PREAMBLE sequence. Does not check the number of + * PREAMBLE cycles. (C) OVRERR *DON'T PUT IN HRM* OVRERR is an + * architectural assertion check internal to GMI to make sure no + * assumption was violated. In a correctly operating system, this + * interrupt can never fire. GMI has an internal arbiter which selects + * which of four ports to buffer in the main RX FIFO. If we normally + * buffer eight bytes, then each port will typically push a tick every + * eight cycles if the packet interface is going as fast as possible. If + * there are four ports, they push every two cycles. So that's the + * assumption. That the inbound module will always be able to consume + * the tick before another is produced. If that doesn't happen that's + * when OVRERR will assert." + */ +union cgxx_gmp_gmi_rxx_int { + u64 u; + struct cgxx_gmp_gmi_rxx_int_s { + u64 minerr : 1; + u64 carext : 1; + u64 jabber : 1; + u64 fcserr : 1; + u64 rcverr : 1; + u64 skperr : 1; + u64 ovrerr : 1; + u64 pcterr : 1; + u64 rsverr : 1; + u64 falerr : 1; + u64 coldet : 1; + u64 ifgerr : 1; + u64 reserved_12_63 : 52; + } s; + struct cgxx_gmp_gmi_rxx_int_cn { + u64 minerr : 1; + u64 carext : 1; + u64 jabber : 1; + u64 fcserr : 1; + u64 rcverr : 1; + u64 skperr : 1; + u64 ovrerr : 1; + u64 pcterr : 1; + u64 rsverr : 1; + u64 falerr : 1; + u64 coldet : 1; + u64 ifgerr : 1; + u64 reserved_12_15 : 4; + u64 reserved_16_63 : 48; + } cn; +}; + +static inline u64 CGXX_GMP_GMI_RXX_INT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_RXX_INT(u64 a) +{ + return 0x38000 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_rx#_int_ena_w1c + * + * CGX GMP GMI RX Interrupt Enable Clear Registers This register clears + * interrupt enable bits. + */ +union cgxx_gmp_gmi_rxx_int_ena_w1c { + u64 u; + struct cgxx_gmp_gmi_rxx_int_ena_w1c_s { + u64 minerr : 1; + u64 carext : 1; + u64 jabber : 1; + u64 fcserr : 1; + u64 rcverr : 1; + u64 skperr : 1; + u64 ovrerr : 1; + u64 pcterr : 1; + u64 rsverr : 1; + u64 falerr : 1; + u64 coldet : 1; + u64 ifgerr : 1; + u64 reserved_12_63 : 52; + } s; + struct cgxx_gmp_gmi_rxx_int_ena_w1c_cn { + u64 minerr : 1; + u64 carext : 1; + u64 jabber : 1; + u64 fcserr : 1; + u64 rcverr : 1; + u64 skperr : 1; + u64 ovrerr : 1; + u64 pcterr : 1; + u64 rsverr : 1; + u64 falerr : 1; + u64 coldet : 1; + u64 ifgerr : 1; + u64 reserved_12_15 : 4; + u64 reserved_16_63 : 48; + } cn; +}; + +static inline u64 CGXX_GMP_GMI_RXX_INT_ENA_W1C(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_RXX_INT_ENA_W1C(u64 a) +{ + return 0x38010 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_rx#_int_ena_w1s + * + * CGX GMP GMI RX Interrupt Enable Set Registers This register sets + * interrupt enable bits. + */ +union cgxx_gmp_gmi_rxx_int_ena_w1s { + u64 u; + struct cgxx_gmp_gmi_rxx_int_ena_w1s_s { + u64 minerr : 1; + u64 carext : 1; + u64 jabber : 1; + u64 fcserr : 1; + u64 rcverr : 1; + u64 skperr : 1; + u64 ovrerr : 1; + u64 pcterr : 1; + u64 rsverr : 1; + u64 falerr : 1; + u64 coldet : 1; + u64 ifgerr : 1; + u64 reserved_12_63 : 52; + } s; + struct cgxx_gmp_gmi_rxx_int_ena_w1s_cn { + u64 minerr : 1; + u64 carext : 1; + u64 jabber : 1; + u64 fcserr : 1; + u64 rcverr : 1; + u64 skperr : 1; + u64 ovrerr : 1; + u64 pcterr : 1; + u64 rsverr : 1; + u64 falerr : 1; + u64 coldet : 1; + u64 ifgerr : 1; + u64 reserved_12_15 : 4; + u64 reserved_16_63 : 48; + } cn; +}; + +static inline u64 CGXX_GMP_GMI_RXX_INT_ENA_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_RXX_INT_ENA_W1S(u64 a) +{ + return 0x38018 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_rx#_int_w1s + * + * CGX GMP GMI RX Interrupt Set Registers This register sets interrupt + * bits. + */ +union cgxx_gmp_gmi_rxx_int_w1s { + u64 u; + struct cgxx_gmp_gmi_rxx_int_w1s_s { + u64 minerr : 1; + u64 carext : 1; + u64 jabber : 1; + u64 fcserr : 1; + u64 rcverr : 1; + u64 skperr : 1; + u64 ovrerr : 1; + u64 pcterr : 1; + u64 rsverr : 1; + u64 falerr : 1; + u64 coldet : 1; + u64 ifgerr : 1; + u64 reserved_12_63 : 52; + } s; + struct cgxx_gmp_gmi_rxx_int_w1s_cn { + u64 minerr : 1; + u64 carext : 1; + u64 jabber : 1; + u64 fcserr : 1; + u64 rcverr : 1; + u64 skperr : 1; + u64 ovrerr : 1; + u64 pcterr : 1; + u64 rsverr : 1; + u64 falerr : 1; + u64 coldet : 1; + u64 ifgerr : 1; + u64 reserved_12_15 : 4; + u64 reserved_16_63 : 48; + } cn; +}; + +static inline u64 CGXX_GMP_GMI_RXX_INT_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_RXX_INT_W1S(u64 a) +{ + return 0x38008 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_rx#_jabber + * + * CGX GMP Maximum Packet-Size Registers This register specifies the + * maximum size for packets, beyond which the GMI truncates. + */ +union cgxx_gmp_gmi_rxx_jabber { + u64 u; + struct cgxx_gmp_gmi_rxx_jabber_s { + u64 cnt : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_gmp_gmi_rxx_jabber_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_RXX_JABBER(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_RXX_JABBER(u64 a) +{ + return 0x38038 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_rx#_udd_skp + * + * CGX GMP GMI User-Defined Data Skip Registers This register specifies + * the amount of user-defined data (UDD) added before the start of the + * L2C data. Internal: Notes: (1) The skip bytes are part of the packet + * and will be handled by NIX. (2) The system can determine if the UDD + * bytes are included in the FCS check by using the FCSSEL field - if the + * FCS check is enabled. (3) Assume that the preamble/sfd is always at + * the start of the frame - even before UDD bytes. In most cases, there + * will be no preamble in these cases since it will be packet interface + * in direct communication to another packet interface (MAC to MAC) + * without a PHY involved. (4) We can still do address filtering and + * control packet filtering is the user desires. (5) + * CGX()_GMP_GMI_RX()_UDD_SKP[LEN] must be 0 in half-duplex operation + * unless CGX()_GMP_GMI_RX()_FRM_CTL[PRE_CHK] is clear. If + * CGX()_GMP_GMI_RX()_FRM_CTL[PRE_CHK] is clear, then + * CGX()_GMP_GMI_RX()_UDD_SKP[LEN] will normally be 8. (6) In all cases, + * the UDD bytes will be sent down the packet interface as part of the + * packet. The UDD bytes are never stripped from the actual packet. + */ +union cgxx_gmp_gmi_rxx_udd_skp { + u64 u; + struct cgxx_gmp_gmi_rxx_udd_skp_s { + u64 len : 7; + u64 reserved_7 : 1; + u64 fcssel : 1; + u64 reserved_9_63 : 55; + } s; + /* struct cgxx_gmp_gmi_rxx_udd_skp_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_RXX_UDD_SKP(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_RXX_UDD_SKP(u64 a) +{ + return 0x38048 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_smac# + * + * CGX GMI SMAC Registers + */ +union cgxx_gmp_gmi_smacx { + u64 u; + struct cgxx_gmp_gmi_smacx_s { + u64 smac : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_gmp_gmi_smacx_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_SMACX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_SMACX(u64 a) +{ + return 0x38230 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx#_append + * + * CGX GMI TX Append Control Registers + */ +union cgxx_gmp_gmi_txx_append { + u64 u; + struct cgxx_gmp_gmi_txx_append_s { + u64 preamble : 1; + u64 pad : 1; + u64 fcs : 1; + u64 force_fcs : 1; + u64 reserved_4_63 : 60; + } s; + /* struct cgxx_gmp_gmi_txx_append_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_TXX_APPEND(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TXX_APPEND(u64 a) +{ + return 0x38218 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx#_burst + * + * CGX GMI TX Burst-Counter Registers + */ +union cgxx_gmp_gmi_txx_burst { + u64 u; + struct cgxx_gmp_gmi_txx_burst_s { + u64 burst : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_gmp_gmi_txx_burst_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_TXX_BURST(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TXX_BURST(u64 a) +{ + return 0x38228 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx#_ctl + * + * CGX GMI Transmit Control Registers + */ +union cgxx_gmp_gmi_txx_ctl { + u64 u; + struct cgxx_gmp_gmi_txx_ctl_s { + u64 xscol_en : 1; + u64 xsdef_en : 1; + u64 tx_fc_type : 1; + u64 link_drain : 1; + u64 reserved_4_63 : 60; + } s; + /* struct cgxx_gmp_gmi_txx_ctl_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_TXX_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TXX_CTL(u64 a) +{ + return 0x38270 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx#_int + * + * CGX GMI TX Interrupt Registers + */ +union cgxx_gmp_gmi_txx_int { + u64 u; + struct cgxx_gmp_gmi_txx_int_s { + u64 undflw : 1; + u64 xscol : 1; + u64 xsdef : 1; + u64 late_col : 1; + u64 ptp_lost : 1; + u64 reserved_5_63 : 59; + } s; + struct cgxx_gmp_gmi_txx_int_cn { + u64 undflw : 1; + u64 xscol : 1; + u64 xsdef : 1; + u64 late_col : 1; + u64 ptp_lost : 1; + u64 reserved_5_7 : 3; + u64 reserved_8 : 1; + u64 reserved_9_63 : 55; + } cn; +}; + +static inline u64 CGXX_GMP_GMI_TXX_INT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TXX_INT(u64 a) +{ + return 0x38500 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx#_int_ena_w1c + * + * CGX GMI TX Interrupt Enable Clear Registers This register clears + * interrupt enable bits. + */ +union cgxx_gmp_gmi_txx_int_ena_w1c { + u64 u; + struct cgxx_gmp_gmi_txx_int_ena_w1c_s { + u64 undflw : 1; + u64 xscol : 1; + u64 xsdef : 1; + u64 late_col : 1; + u64 ptp_lost : 1; + u64 reserved_5_63 : 59; + } s; + struct cgxx_gmp_gmi_txx_int_ena_w1c_cn { + u64 undflw : 1; + u64 xscol : 1; + u64 xsdef : 1; + u64 late_col : 1; + u64 ptp_lost : 1; + u64 reserved_5_7 : 3; + u64 reserved_8 : 1; + u64 reserved_9_63 : 55; + } cn; +}; + +static inline u64 CGXX_GMP_GMI_TXX_INT_ENA_W1C(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TXX_INT_ENA_W1C(u64 a) +{ + return 0x38510 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx#_int_ena_w1s + * + * CGX GMI TX Interrupt Enable Set Registers This register sets interrupt + * enable bits. + */ +union cgxx_gmp_gmi_txx_int_ena_w1s { + u64 u; + struct cgxx_gmp_gmi_txx_int_ena_w1s_s { + u64 undflw : 1; + u64 xscol : 1; + u64 xsdef : 1; + u64 late_col : 1; + u64 ptp_lost : 1; + u64 reserved_5_63 : 59; + } s; + struct cgxx_gmp_gmi_txx_int_ena_w1s_cn { + u64 undflw : 1; + u64 xscol : 1; + u64 xsdef : 1; + u64 late_col : 1; + u64 ptp_lost : 1; + u64 reserved_5_7 : 3; + u64 reserved_8 : 1; + u64 reserved_9_63 : 55; + } cn; +}; + +static inline u64 CGXX_GMP_GMI_TXX_INT_ENA_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TXX_INT_ENA_W1S(u64 a) +{ + return 0x38518 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx#_int_w1s + * + * CGX GMI TX Interrupt Set Registers This register sets interrupt bits. + */ +union cgxx_gmp_gmi_txx_int_w1s { + u64 u; + struct cgxx_gmp_gmi_txx_int_w1s_s { + u64 undflw : 1; + u64 xscol : 1; + u64 xsdef : 1; + u64 late_col : 1; + u64 ptp_lost : 1; + u64 reserved_5_63 : 59; + } s; + struct cgxx_gmp_gmi_txx_int_w1s_cn { + u64 undflw : 1; + u64 xscol : 1; + u64 xsdef : 1; + u64 late_col : 1; + u64 ptp_lost : 1; + u64 reserved_5_7 : 3; + u64 reserved_8 : 1; + u64 reserved_9_63 : 55; + } cn; +}; + +static inline u64 CGXX_GMP_GMI_TXX_INT_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TXX_INT_W1S(u64 a) +{ + return 0x38508 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx#_min_pkt + * + * CGX GMI TX Minimum-Size-Packet Registers + */ +union cgxx_gmp_gmi_txx_min_pkt { + u64 u; + struct cgxx_gmp_gmi_txx_min_pkt_s { + u64 min_size : 8; + u64 reserved_8_63 : 56; + } s; + /* struct cgxx_gmp_gmi_txx_min_pkt_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_TXX_MIN_PKT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TXX_MIN_PKT(u64 a) +{ + return 0x38240 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx#_pause_pkt_interval + * + * CGX GMI TX PAUSE-Packet Transmission-Interval Registers This register + * specifies how often PAUSE packets are sent. Internal: Notes: Choosing + * proper values of CGX()_GMP_GMI_TX()_PAUSE_PKT_TIME[PTIME] and + * CGX()_GMP_GMI_TX()_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to + * the system designer. It is suggested that TIME be much greater than + * INTERVAL and CGX()_GMP_GMI_TX()_PAUSE_ZERO[SEND] be set. This allows + * a periodic refresh of the PAUSE count and then when the backpressure + * condition is lifted, a PAUSE packet with TIME==0 will be sent + * indicating that Octane is ready for additional data. If the system + * chooses to not set CGX()_GMP_GMI_TX()_PAUSE_ZERO[SEND], then it is + * suggested that TIME and INTERVAL are programmed such that they + * satisify the following rule: _ INTERVAL \<= TIME - (largest_pkt_size + * + IFG + pause_pkt_size) where largest_pkt_size is that largest packet + * that the system can send (normally 1518B), IFG is the interframe gap + * and pause_pkt_size is the size of the PAUSE packet (normally 64B). + */ +union cgxx_gmp_gmi_txx_pause_pkt_interval { + u64 u; + struct cgxx_gmp_gmi_txx_pause_pkt_interval_s { + u64 interval : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_gmp_gmi_txx_pause_pkt_interval_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_TXX_PAUSE_PKT_INTERVAL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TXX_PAUSE_PKT_INTERVAL(u64 a) +{ + return 0x38248 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx#_pause_pkt_time + * + * CGX GMI TX PAUSE Packet PAUSE-Time Registers + */ +union cgxx_gmp_gmi_txx_pause_pkt_time { + u64 u; + struct cgxx_gmp_gmi_txx_pause_pkt_time_s { + u64 ptime : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_gmp_gmi_txx_pause_pkt_time_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_TXX_PAUSE_PKT_TIME(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TXX_PAUSE_PKT_TIME(u64 a) +{ + return 0x38238 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx#_pause_togo + * + * CGX GMI TX Time-to-Backpressure Registers + */ +union cgxx_gmp_gmi_txx_pause_togo { + u64 u; + struct cgxx_gmp_gmi_txx_pause_togo_s { + u64 ptime : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_gmp_gmi_txx_pause_togo_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_TXX_PAUSE_TOGO(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TXX_PAUSE_TOGO(u64 a) +{ + return 0x38258 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx#_pause_zero + * + * CGX GMI TX PAUSE-Zero-Enable Registers + */ +union cgxx_gmp_gmi_txx_pause_zero { + u64 u; + struct cgxx_gmp_gmi_txx_pause_zero_s { + u64 send : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_gmp_gmi_txx_pause_zero_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_TXX_PAUSE_ZERO(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TXX_PAUSE_ZERO(u64 a) +{ + return 0x38260 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx#_sgmii_ctl + * + * CGX SGMII Control Registers + */ +union cgxx_gmp_gmi_txx_sgmii_ctl { + u64 u; + struct cgxx_gmp_gmi_txx_sgmii_ctl_s { + u64 align : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_gmp_gmi_txx_sgmii_ctl_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_TXX_SGMII_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TXX_SGMII_CTL(u64 a) +{ + return 0x38300 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx#_slot + * + * CGX GMI TX Slottime Counter Registers + */ +union cgxx_gmp_gmi_txx_slot { + u64 u; + struct cgxx_gmp_gmi_txx_slot_s { + u64 slot : 10; + u64 reserved_10_63 : 54; + } s; + /* struct cgxx_gmp_gmi_txx_slot_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_TXX_SLOT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TXX_SLOT(u64 a) +{ + return 0x38220 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx#_soft_pause + * + * CGX GMI TX Software PAUSE Registers + */ +union cgxx_gmp_gmi_txx_soft_pause { + u64 u; + struct cgxx_gmp_gmi_txx_soft_pause_s { + u64 ptime : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_gmp_gmi_txx_soft_pause_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_TXX_SOFT_PAUSE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TXX_SOFT_PAUSE(u64 a) +{ + return 0x38250 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx#_thresh + * + * CGX GMI TX Threshold Registers + */ +union cgxx_gmp_gmi_txx_thresh { + u64 u; + struct cgxx_gmp_gmi_txx_thresh_s { + u64 cnt : 11; + u64 reserved_11_63 : 53; + } s; + /* struct cgxx_gmp_gmi_txx_thresh_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_TXX_THRESH(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TXX_THRESH(u64 a) +{ + return 0x38210 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx_col_attempt + * + * CGX TX Collision Attempts Before Dropping Frame Registers + */ +union cgxx_gmp_gmi_tx_col_attempt { + u64 u; + struct cgxx_gmp_gmi_tx_col_attempt_s { + u64 limit : 5; + u64 reserved_5_63 : 59; + } s; + /* struct cgxx_gmp_gmi_tx_col_attempt_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_TX_COL_ATTEMPT(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TX_COL_ATTEMPT(void) +{ + return 0x39010; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx_ifg + * + * CGX GMI TX Interframe-Gap Cycles Registers Consider the following when + * programming IFG1 and IFG2: * For 10/100/1000 Mb/s half-duplex systems + * that require IEEE 802.3 compatibility, IFG1 must be in the range of + * 1-8, [IFG2] must be in the range of 4-12, and the [IFG1] + [IFG2] sum + * must be 12. * For 10/100/1000 Mb/s full-duplex systems that require + * IEEE 802.3 compatibility, IFG1 must be in the range of 1-11, [IFG2] + * must be in the range of 1-11, and the [IFG1] + [IFG2] sum must be 12. + * For all other systems, IFG1 and IFG2 can be any value in the range of + * 1-15, allowing for a total possible IFG sum of 2-30. + */ +union cgxx_gmp_gmi_tx_ifg { + u64 u; + struct cgxx_gmp_gmi_tx_ifg_s { + u64 ifg1 : 4; + u64 ifg2 : 4; + u64 reserved_8_63 : 56; + } s; + /* struct cgxx_gmp_gmi_tx_ifg_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_TX_IFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TX_IFG(void) +{ + return 0x39000; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx_jam + * + * CGX GMI TX JAM Pattern Registers This register provides the pattern + * used in JAM bytes. + */ +union cgxx_gmp_gmi_tx_jam { + u64 u; + struct cgxx_gmp_gmi_tx_jam_s { + u64 jam : 8; + u64 reserved_8_63 : 56; + } s; + /* struct cgxx_gmp_gmi_tx_jam_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_TX_JAM(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TX_JAM(void) +{ + return 0x39008; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx_lfsr + * + * CGX GMI TX LFSR Registers This register shows the contents of the + * linear feedback shift register (LFSR), which is used to implement + * truncated binary exponential backoff. + */ +union cgxx_gmp_gmi_tx_lfsr { + u64 u; + struct cgxx_gmp_gmi_tx_lfsr_s { + u64 lfsr : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_gmp_gmi_tx_lfsr_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_TX_LFSR(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TX_LFSR(void) +{ + return 0x39028; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx_pause_pkt_dmac + * + * CGX TX PAUSE-Packet DMAC-Field Registers + */ +union cgxx_gmp_gmi_tx_pause_pkt_dmac { + u64 u; + struct cgxx_gmp_gmi_tx_pause_pkt_dmac_s { + u64 dmac : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_gmp_gmi_tx_pause_pkt_dmac_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_TX_PAUSE_PKT_DMAC(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TX_PAUSE_PKT_DMAC(void) +{ + return 0x39018; +} + +/** + * Register (RSL) cgx#_gmp_gmi_tx_pause_pkt_type + * + * CGX GMI TX PAUSE-Packet-PTYPE Field Registers This register provides + * the PTYPE field that is placed in outbound PAUSE packets. + */ +union cgxx_gmp_gmi_tx_pause_pkt_type { + u64 u; + struct cgxx_gmp_gmi_tx_pause_pkt_type_s { + u64 ptype : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_gmp_gmi_tx_pause_pkt_type_s cn; */ +}; + +static inline u64 CGXX_GMP_GMI_TX_PAUSE_PKT_TYPE(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_GMI_TX_PAUSE_PKT_TYPE(void) +{ + return 0x39020; +} + +/** + * Register (RSL) cgx#_gmp_misc#_cfg + * + * CGX GMP PCS Miscellaneous Control Registers This register contains + * general configuration that should not need to be changed from reset + * settings. Internal: Per lmac diagnostic and chicken bits. + */ +union cgxx_gmp_miscx_cfg { + u64 u; + struct cgxx_gmp_miscx_cfg_s { + u64 tx_eee_quiet_credit_mode : 1; + u64 tx_eee_wait_gmi_fast_idle : 1; + u64 tx_qsgmii_port0_init : 1; + u64 tx_eee_rx_sync_status_enable : 1; + u64 pcs_alt_an : 1; + u64 reserved_5_7 : 3; + u64 rx_pcs_sync_signal_detect : 1; + u64 rx_pcs_sync_timeout : 1; + u64 rx_pcs_eee_mode_enable : 1; + u64 rx_pcs_lpi_enable : 1; + u64 rx_pcs_802_rx_k : 1; + u64 rx_pcs_alt_qlb2i : 1; + u64 reserved_14_15 : 2; + u64 rx_cgp_gser_throttle : 1; + u64 rx_cgp_edet_filter : 1; + u64 rx_cgp_edet_qlm_val : 1; + u64 reserved_19_63 : 45; + } s; + /* struct cgxx_gmp_miscx_cfg_s cn; */ +}; + +static inline u64 CGXX_GMP_MISCX_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_MISCX_CFG(u64 a) +{ + return 0x34000 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs#_an_expansion + * + * CGX GMP PCS AN Expansion register Register 6 AN status + */ +union cgxx_gmp_pcsx_an_expansion { + u64 u; + struct cgxx_gmp_pcsx_an_expansion_s { + u64 reserved_0 : 1; + u64 page_received : 1; + u64 next_page_able : 1; + u64 reserved_3_63 : 61; + } s; + /* struct cgxx_gmp_pcsx_an_expansion_s cn; */ +}; + +static inline u64 CGXX_GMP_PCSX_AN_EXPANSION(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCSX_AN_EXPANSION(u64 a) +{ + return 0x30a60 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs#_an_lp_abil_np + * + * CGX GMP PCS AN Link Partner Ability Next Page Register 8 This register + * contains the advertised ability of the link partners Next Page. The + * definition for this register is provided in 32.5.4.2 for changes to + * 28.2.4.1.4. + */ +union cgxx_gmp_pcsx_an_lp_abil_np { + u64 u; + struct cgxx_gmp_pcsx_an_lp_abil_np_s { + u64 m_u : 11; + u64 toggle : 1; + u64 ack2 : 1; + u64 mp : 1; + u64 ack : 1; + u64 np : 1; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_gmp_pcsx_an_lp_abil_np_s cn; */ +}; + +static inline u64 CGXX_GMP_PCSX_AN_LP_ABIL_NP(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCSX_AN_LP_ABIL_NP(u64 a) +{ + return 0x30a80 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs#_an_np_tx + * + * CGX GMP PCS AN Next Page Transmit Register 7 Software programs this + * register with the contents of the AN message next page or unformatted + * next page link code word to be transmitted during autonegotiation. + * Next page exchange occurs after the base link code words have been + * exchanged if either end of the link segment sets the NP bit to 1, + * indicating that it has at least one next page to send. Once initiated, + * next page exchange continues until both ends of the link segment set + * their NP bits to 0. Both sides must be NP capable to use NP exchanges. + */ +union cgxx_gmp_pcsx_an_np_tx { + u64 u; + struct cgxx_gmp_pcsx_an_np_tx_s { + u64 m_u : 11; + u64 toggle : 1; + u64 ack2 : 1; + u64 mp : 1; + u64 ack : 1; + u64 np : 1; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_gmp_pcsx_an_np_tx_s cn; */ +}; + +static inline u64 CGXX_GMP_PCSX_AN_NP_TX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCSX_AN_NP_TX(u64 a) +{ + return 0x30a70 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs#_dbg_control + * + * CGX PCS Debug Control Registers + */ +union cgxx_gmp_pcsx_dbg_control { + u64 u; + struct cgxx_gmp_pcsx_dbg_control_s { + u64 us_clk_period : 7; + u64 reserved_7_63 : 57; + } s; + /* struct cgxx_gmp_pcsx_dbg_control_s cn; */ +}; + +static inline u64 CGXX_GMP_PCSX_DBG_CONTROL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCSX_DBG_CONTROL(u64 a) +{ + return 0x31000 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs#_rx_eee_wake + * + * INTERNAL: CGX GMP PCS RX EEE Wake Error Counter Registers Reserved. + * Internal: This register is used by PHY types that support EEE to count + * wake time faults where the PHY fails to complete its normal wake + * sequence within the time required for the specific PHY type. The + * definition of the fault event to be counted is defined for each PHY + * and may occur during a refresh or a wake-up as defined by the PHY. + * This 16-bit counter shall be reset to all zeros upon execution of the + * PCS reset. This counter shall be held at all ones in the case of + * overflow. + */ +union cgxx_gmp_pcsx_rx_eee_wake { + u64 u; + struct cgxx_gmp_pcsx_rx_eee_wake_s { + u64 error_counter : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_gmp_pcsx_rx_eee_wake_s cn; */ +}; + +static inline u64 CGXX_GMP_PCSX_RX_EEE_WAKE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCSX_RX_EEE_WAKE(u64 a) +{ + return 0x30910 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs#_rx_lpi_timing + * + * INTERNAL: CGX GMP PCS RX EEE LPI Timing Parameters Registers + * Reserved. Internal: Receiver LPI timing parameters Tqr, Twr and Twtf. + */ +union cgxx_gmp_pcsx_rx_lpi_timing { + u64 u; + struct cgxx_gmp_pcsx_rx_lpi_timing_s { + u64 twtf : 18; + u64 reserved_18_19 : 2; + u64 twr : 12; + u64 tqr : 20; + u64 reserved_52_63 : 12; + } s; + /* struct cgxx_gmp_pcsx_rx_lpi_timing_s cn; */ +}; + +static inline u64 CGXX_GMP_PCSX_RX_LPI_TIMING(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCSX_RX_LPI_TIMING(u64 a) +{ + return 0x30900 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs#_status1 + * + * CGX GMP PCS Status 1 Register PCS LPI Status, Link OK. Register 3.1 + */ +union cgxx_gmp_pcsx_status1 { + u64 u; + struct cgxx_gmp_pcsx_status1_s { + u64 reserved_0_1 : 2; + u64 receive_link_status : 1; + u64 reserved_3_7 : 5; + u64 rx_lpi_indication : 1; + u64 tx_lpi_indication : 1; + u64 rx_lpi_received : 1; + u64 tx_lpi_received : 1; + u64 reserved_12_63 : 52; + } s; + /* struct cgxx_gmp_pcsx_status1_s cn; */ +}; + +static inline u64 CGXX_GMP_PCSX_STATUS1(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCSX_STATUS1(u64 a) +{ + return 0x30880 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs#_tx_lpi_timing + * + * INTERNAL: CGX GMP GMI TX EEE LPI Timing Parameters Registers + * Reserved. Internal: Transmitter LPI timing parameters Tsl, Tql and + * Tul. + */ +union cgxx_gmp_pcsx_tx_lpi_timing { + u64 u; + struct cgxx_gmp_pcsx_tx_lpi_timing_s { + u64 tql : 19; + u64 reserved_19_31 : 13; + u64 tul : 12; + u64 reserved_44_47 : 4; + u64 tsl : 12; + u64 reserved_60_63 : 4; + } s; + /* struct cgxx_gmp_pcsx_tx_lpi_timing_s cn; */ +}; + +static inline u64 CGXX_GMP_PCSX_TX_LPI_TIMING(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCSX_TX_LPI_TIMING(u64 a) +{ + return 0x30800 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs_an#_adv + * + * CGX GMP PCS Autonegotiation Advertisement Registers + */ +union cgxx_gmp_pcs_anx_adv { + u64 u; + struct cgxx_gmp_pcs_anx_adv_s { + u64 reserved_0_4 : 5; + u64 fd : 1; + u64 hfd : 1; + u64 pause : 2; + u64 reserved_9_11 : 3; + u64 rem_flt : 2; + u64 reserved_14 : 1; + u64 np : 1; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_gmp_pcs_anx_adv_s cn; */ +}; + +static inline u64 CGXX_GMP_PCS_ANX_ADV(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCS_ANX_ADV(u64 a) +{ + return 0x30010 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs_an#_ext_st + * + * CGX GMO PCS Autonegotiation Extended Status Registers + */ +union cgxx_gmp_pcs_anx_ext_st { + u64 u; + struct cgxx_gmp_pcs_anx_ext_st_s { + u64 reserved_0_11 : 12; + u64 thou_thd : 1; + u64 thou_tfd : 1; + u64 thou_xhd : 1; + u64 thou_xfd : 1; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_gmp_pcs_anx_ext_st_s cn; */ +}; + +static inline u64 CGXX_GMP_PCS_ANX_EXT_ST(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCS_ANX_EXT_ST(u64 a) +{ + return 0x30028 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs_an#_lp_abil + * + * CGX GMP PCS Autonegotiation Link Partner Ability Registers This is the + * autonegotiation link partner ability register 5 as per IEEE 802.3, + * Clause 37. + */ +union cgxx_gmp_pcs_anx_lp_abil { + u64 u; + struct cgxx_gmp_pcs_anx_lp_abil_s { + u64 reserved_0_4 : 5; + u64 fd : 1; + u64 hfd : 1; + u64 pause : 2; + u64 reserved_9_11 : 3; + u64 rem_flt : 2; + u64 ack : 1; + u64 np : 1; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_gmp_pcs_anx_lp_abil_s cn; */ +}; + +static inline u64 CGXX_GMP_PCS_ANX_LP_ABIL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCS_ANX_LP_ABIL(u64 a) +{ + return 0x30018 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs_an#_results + * + * CGX GMP PCS Autonegotiation Results Registers This register is not + * valid when CGX()_GMP_PCS_MISC()_CTL[AN_OVRD] is set to 1. If + * CGX()_GMP_PCS_MISC()_CTL[AN_OVRD] is set to 0 and + * CGX()_GMP_PCS_AN()_RESULTS[AN_CPT] is set to 1, this register is + * valid. + */ +union cgxx_gmp_pcs_anx_results { + u64 u; + struct cgxx_gmp_pcs_anx_results_s { + u64 link_ok : 1; + u64 dup : 1; + u64 an_cpt : 1; + u64 spd : 2; + u64 pause : 2; + u64 reserved_7_63 : 57; + } s; + /* struct cgxx_gmp_pcs_anx_results_s cn; */ +}; + +static inline u64 CGXX_GMP_PCS_ANX_RESULTS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCS_ANX_RESULTS(u64 a) +{ + return 0x30020 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs_int# + * + * CGX GMP PCS Interrupt Registers + */ +union cgxx_gmp_pcs_intx { + u64 u; + struct cgxx_gmp_pcs_intx_s { + u64 lnkspd : 1; + u64 xmit : 1; + u64 an_err : 1; + u64 txfifu : 1; + u64 txfifo : 1; + u64 txbad : 1; + u64 rxerr : 1; + u64 rxbad : 1; + u64 rxlock : 1; + u64 an_bad : 1; + u64 sync_bad : 1; + u64 dup : 1; + u64 dbg_sync : 1; + u64 reserved_13_15 : 3; + u64 an_page_received : 1; + u64 an_complete : 1; + u64 reserved_18_19 : 2; + u64 eee_tx_change : 1; + u64 eee_rx_change : 1; + u64 eee_rx_link_fail : 1; + u64 reserved_23_63 : 41; + } s; + /* struct cgxx_gmp_pcs_intx_s cn; */ +}; + +static inline u64 CGXX_GMP_PCS_INTX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCS_INTX(u64 a) +{ + return 0x30080 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs_int#_ena_w1c + * + * CGX GMP PCS Interrupt Enable Clear Registers This register clears + * interrupt enable bits. + */ +union cgxx_gmp_pcs_intx_ena_w1c { + u64 u; + struct cgxx_gmp_pcs_intx_ena_w1c_s { + u64 lnkspd : 1; + u64 xmit : 1; + u64 an_err : 1; + u64 txfifu : 1; + u64 txfifo : 1; + u64 txbad : 1; + u64 rxerr : 1; + u64 rxbad : 1; + u64 rxlock : 1; + u64 an_bad : 1; + u64 sync_bad : 1; + u64 dup : 1; + u64 dbg_sync : 1; + u64 reserved_13_15 : 3; + u64 an_page_received : 1; + u64 an_complete : 1; + u64 reserved_18_19 : 2; + u64 eee_tx_change : 1; + u64 eee_rx_change : 1; + u64 eee_rx_link_fail : 1; + u64 reserved_23_63 : 41; + } s; + /* struct cgxx_gmp_pcs_intx_ena_w1c_s cn; */ +}; + +static inline u64 CGXX_GMP_PCS_INTX_ENA_W1C(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCS_INTX_ENA_W1C(u64 a) +{ + return 0x30090 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs_int#_ena_w1s + * + * CGX GMP PCS Interrupt Enable Set Registers This register sets + * interrupt enable bits. + */ +union cgxx_gmp_pcs_intx_ena_w1s { + u64 u; + struct cgxx_gmp_pcs_intx_ena_w1s_s { + u64 lnkspd : 1; + u64 xmit : 1; + u64 an_err : 1; + u64 txfifu : 1; + u64 txfifo : 1; + u64 txbad : 1; + u64 rxerr : 1; + u64 rxbad : 1; + u64 rxlock : 1; + u64 an_bad : 1; + u64 sync_bad : 1; + u64 dup : 1; + u64 dbg_sync : 1; + u64 reserved_13_15 : 3; + u64 an_page_received : 1; + u64 an_complete : 1; + u64 reserved_18_19 : 2; + u64 eee_tx_change : 1; + u64 eee_rx_change : 1; + u64 eee_rx_link_fail : 1; + u64 reserved_23_63 : 41; + } s; + /* struct cgxx_gmp_pcs_intx_ena_w1s_s cn; */ +}; + +static inline u64 CGXX_GMP_PCS_INTX_ENA_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCS_INTX_ENA_W1S(u64 a) +{ + return 0x30098 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs_int#_w1s + * + * CGX GMP PCS Interrupt Set Registers This register sets interrupt bits. + */ +union cgxx_gmp_pcs_intx_w1s { + u64 u; + struct cgxx_gmp_pcs_intx_w1s_s { + u64 lnkspd : 1; + u64 xmit : 1; + u64 an_err : 1; + u64 txfifu : 1; + u64 txfifo : 1; + u64 txbad : 1; + u64 rxerr : 1; + u64 rxbad : 1; + u64 rxlock : 1; + u64 an_bad : 1; + u64 sync_bad : 1; + u64 dup : 1; + u64 dbg_sync : 1; + u64 reserved_13_15 : 3; + u64 an_page_received : 1; + u64 an_complete : 1; + u64 reserved_18_19 : 2; + u64 eee_tx_change : 1; + u64 eee_rx_change : 1; + u64 eee_rx_link_fail : 1; + u64 reserved_23_63 : 41; + } s; + /* struct cgxx_gmp_pcs_intx_w1s_s cn; */ +}; + +static inline u64 CGXX_GMP_PCS_INTX_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCS_INTX_W1S(u64 a) +{ + return 0x30088 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs_link#_timer + * + * CGX GMP PCS Link Timer Registers This is the 1.6 ms nominal link timer + * register. + */ +union cgxx_gmp_pcs_linkx_timer { + u64 u; + struct cgxx_gmp_pcs_linkx_timer_s { + u64 count : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_gmp_pcs_linkx_timer_s cn; */ +}; + +static inline u64 CGXX_GMP_PCS_LINKX_TIMER(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCS_LINKX_TIMER(u64 a) +{ + return 0x30040 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs_misc#_ctl + * + * CGX GMP SGMII Miscellaneous Control Registers Internal: SGMII bit [12] + * is really a misnomer, it is a decode of pi_qlm_cfg pins to indicate + * SGMII or 1000Base-X modes. Note: The SGMII AN Advertisement Register + * above will be sent during Auto Negotiation if [MAC_PHY] is set (1=PHY + * mode). If the bit is not set (0=MAC mode), the tx_Config_Reg\<14\> + * becomes ACK bit and tx_Config_Reg\<0\> is always 1. All other bits in + * tx_Config_Reg sent will be 0. The PHY dictates the Auto Negotiation + * results. + */ +union cgxx_gmp_pcs_miscx_ctl { + u64 u; + struct cgxx_gmp_pcs_miscx_ctl_s { + u64 samp_pt : 7; + u64 an_ovrd : 1; + u64 mode : 1; + u64 mac_phy : 1; + u64 loopbck2 : 1; + u64 gmxeno : 1; + u64 reserved_12 : 1; + u64 disp_en : 1; + u64 reserved_14_15 : 2; + u64 qsgmii_comma_wd : 16; + u64 qsgmii_comma_wd_en : 1; + u64 reserved_33_63 : 31; + } s; + struct cgxx_gmp_pcs_miscx_ctl_cn { + u64 samp_pt : 7; + u64 an_ovrd : 1; + u64 mode : 1; + u64 mac_phy : 1; + u64 loopbck2 : 1; + u64 gmxeno : 1; + u64 reserved_12 : 1; + u64 disp_en : 1; + u64 reserved_14_15 : 2; + u64 qsgmii_comma_wd : 16; + u64 qsgmii_comma_wd_en : 1; + u64 reserved_33_35 : 3; + u64 reserved_36_63 : 28; + } cn; +}; + +static inline u64 CGXX_GMP_PCS_MISCX_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCS_MISCX_CTL(u64 a) +{ + return 0x30078 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs_mr#_control + * + * CGX GMP PCS Control Registers + */ +union cgxx_gmp_pcs_mrx_control { + u64 u; + struct cgxx_gmp_pcs_mrx_control_s { + u64 reserved_0_4 : 5; + u64 uni : 1; + u64 spdmsb : 1; + u64 coltst : 1; + u64 dup : 1; + u64 rst_an : 1; + u64 reserved_10 : 1; + u64 pwr_dn : 1; + u64 an_en : 1; + u64 spdlsb : 1; + u64 loopbck1 : 1; + u64 reset : 1; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_gmp_pcs_mrx_control_s cn; */ +}; + +static inline u64 CGXX_GMP_PCS_MRX_CONTROL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCS_MRX_CONTROL(u64 a) +{ + return 0x30000 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs_mr#_status + * + * CGX GMP PCS Status Registers Bits \<15:9\> in this register indicate + * the ability to operate when CGX()_GMP_PCS_MISC()_CTL[MAC_PHY] is set + * to MAC mode. Bits \<15:9\> are always read as 0, indicating that the + * chip cannot operate in the corresponding modes. The field [RM_FLT] is + * a 'don't care' when the selected mode is SGMII/QSGMII. + */ +union cgxx_gmp_pcs_mrx_status { + u64 u; + struct cgxx_gmp_pcs_mrx_status_s { + u64 extnd : 1; + u64 reserved_1 : 1; + u64 lnk_st : 1; + u64 an_abil : 1; + u64 rm_flt : 1; + u64 an_cpt : 1; + u64 prb_sup : 1; + u64 reserved_7 : 1; + u64 ext_st : 1; + u64 hun_t2hd : 1; + u64 hun_t2fd : 1; + u64 ten_hd : 1; + u64 ten_fd : 1; + u64 hun_xhd : 1; + u64 hun_xfd : 1; + u64 hun_t4 : 1; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_gmp_pcs_mrx_status_s cn; */ +}; + +static inline u64 CGXX_GMP_PCS_MRX_STATUS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCS_MRX_STATUS(u64 a) +{ + return 0x30008 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs_rx#_states + * + * CGX GMP PCS RX State-Machines States Registers + */ +union cgxx_gmp_pcs_rxx_states { + u64 u; + struct cgxx_gmp_pcs_rxx_states_s { + u64 an_st : 4; + u64 an_bad : 1; + u64 sync : 4; + u64 sync_bad : 1; + u64 rx_st : 5; + u64 rx_bad : 1; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_gmp_pcs_rxx_states_s cn; */ +}; + +static inline u64 CGXX_GMP_PCS_RXX_STATES(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCS_RXX_STATES(u64 a) +{ + return 0x30058 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs_rx#_sync + * + * CGX GMP PCS Code Group Synchronization Registers + */ +union cgxx_gmp_pcs_rxx_sync { + u64 u; + struct cgxx_gmp_pcs_rxx_sync_s { + u64 bit_lock : 1; + u64 sync : 1; + u64 reserved_2_63 : 62; + } s; + /* struct cgxx_gmp_pcs_rxx_sync_s cn; */ +}; + +static inline u64 CGXX_GMP_PCS_RXX_SYNC(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCS_RXX_SYNC(u64 a) +{ + return 0x30050 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs_sgm#_an_adv + * + * CGX GMP PCS SGMII Autonegotiation Advertisement Registers This is the + * SGMII autonegotiation advertisement register (sent out as + * tx_Config_Reg\<15:0\> as defined in IEEE 802.3 clause 37). This + * register is sent during autonegotiation if + * CGX()_GMP_PCS_MISC()_CTL[MAC_PHY] is set (1 = PHY mode). If the bit is + * not set (0 = MAC mode), then tx_Config_Reg\<14\> becomes ACK bit and + * tx_Config_Reg\<0\> is always 1. All other bits in tx_Config_Reg sent + * will be 0. The PHY dictates the autonegotiation results. + */ +union cgxx_gmp_pcs_sgmx_an_adv { + u64 u; + struct cgxx_gmp_pcs_sgmx_an_adv_s { + u64 one : 1; + u64 reserved_1_9 : 9; + u64 speed : 2; + u64 dup : 1; + u64 reserved_13 : 1; + u64 ack : 1; + u64 link : 1; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_gmp_pcs_sgmx_an_adv_s cn; */ +}; + +static inline u64 CGXX_GMP_PCS_SGMX_AN_ADV(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCS_SGMX_AN_ADV(u64 a) +{ + return 0x30068 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs_sgm#_lp_adv + * + * CGX GMP PCS SGMII Link-Partner-Advertisement Registers This is the + * SGMII link partner advertisement register (received as + * rx_Config_Reg\<15:0\> as defined in IEEE 802.3 clause 37). + */ +union cgxx_gmp_pcs_sgmx_lp_adv { + u64 u; + struct cgxx_gmp_pcs_sgmx_lp_adv_s { + u64 one : 1; + u64 reserved_1_9 : 9; + u64 speed : 2; + u64 dup : 1; + u64 reserved_13_14 : 2; + u64 link : 1; + u64 reserved_16_63 : 48; + } s; + struct cgxx_gmp_pcs_sgmx_lp_adv_cn { + u64 one : 1; + u64 reserved_1_9 : 9; + u64 speed : 2; + u64 dup : 1; + u64 reserved_13 : 1; + u64 reserved_14 : 1; + u64 link : 1; + u64 reserved_16_63 : 48; + } cn; +}; + +static inline u64 CGXX_GMP_PCS_SGMX_LP_ADV(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCS_SGMX_LP_ADV(u64 a) +{ + return 0x30070 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs_tx#_states + * + * CGX GMP PCS TX State-Machines States Registers + */ +union cgxx_gmp_pcs_txx_states { + u64 u; + struct cgxx_gmp_pcs_txx_states_s { + u64 ord_st : 4; + u64 tx_bad : 1; + u64 xmit : 2; + u64 reserved_7_63 : 57; + } s; + /* struct cgxx_gmp_pcs_txx_states_s cn; */ +}; + +static inline u64 CGXX_GMP_PCS_TXX_STATES(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCS_TXX_STATES(u64 a) +{ + return 0x30060 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_gmp_pcs_tx_rx#_polarity + * + * CGX GMP PCS TX/RX Polarity Registers + * CGX()_GMP_PCS_TX_RX()_POLARITY[AUTORXPL] shows correct polarity needed + * on the link receive path after code group synchronization is achieved. + * When LMAC_TYPE=QSGMII, only lane 0 polarity data and settings are + * relevant and settings for lanes 1, 2 and 3 are unused. + */ +union cgxx_gmp_pcs_tx_rxx_polarity { + u64 u; + struct cgxx_gmp_pcs_tx_rxx_polarity_s { + u64 txplrt : 1; + u64 rxplrt : 1; + u64 autorxpl : 1; + u64 rxovrd : 1; + u64 reserved_4_63 : 60; + } s; + /* struct cgxx_gmp_pcs_tx_rxx_polarity_s cn; */ +}; + +static inline u64 CGXX_GMP_PCS_TX_RXX_POLARITY(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_GMP_PCS_TX_RXX_POLARITY(u64 a) +{ + return 0x30048 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_msix_pba# + * + * CGX MSI-X Pending Bit Array Registers This register is the MSI-X PBA + * table, the bit number is indexed by the CGX_INT_VEC_E enumeration. + */ +union cgxx_msix_pbax { + u64 u; + struct cgxx_msix_pbax_s { + u64 pend : 64; + } s; + /* struct cgxx_msix_pbax_s cn; */ +}; + +static inline u64 CGXX_MSIX_PBAX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_MSIX_PBAX(u64 a) +{ + return 0xf0000 + 8 * a; +} + +/** + * Register (RSL) cgx#_msix_vec#_addr + * + * CGX MSI-X Vector Table Address Registers This register is the MSI-X + * vector table, indexed by the CGX_INT_VEC_E enumeration. + */ +union cgxx_msix_vecx_addr { + u64 u; + struct cgxx_msix_vecx_addr_s { + u64 secvec : 1; + u64 reserved_1 : 1; + u64 addr : 51; + u64 reserved_53_63 : 11; + } s; + /* struct cgxx_msix_vecx_addr_s cn; */ +}; + +static inline u64 CGXX_MSIX_VECX_ADDR(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_MSIX_VECX_ADDR(u64 a) +{ + return 0 + 0x10 * a; +} + +/** + * Register (RSL) cgx#_msix_vec#_ctl + * + * CGX MSI-X Vector Table Control and Data Registers This register is the + * MSI-X vector table, indexed by the CGX_INT_VEC_E enumeration. + */ +union cgxx_msix_vecx_ctl { + u64 u; + struct cgxx_msix_vecx_ctl_s { + u64 data : 32; + u64 mask : 1; + u64 reserved_33_63 : 31; + } s; + /* struct cgxx_msix_vecx_ctl_s cn; */ +}; + +static inline u64 CGXX_MSIX_VECX_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_MSIX_VECX_CTL(u64 a) +{ + return 8 + 0x10 * a; +} + +/** + * Register (RSL) cgx#_smu#_bp_test + * + * INTERNAL: CGX SMU TX Backpressure Test Registers + */ +union cgxx_smux_bp_test { + u64 u; + struct cgxx_smux_bp_test_s { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 8; + u64 reserved_24_47 : 24; + u64 enable : 4; + u64 reserved_52_63 : 12; + } s; + /* struct cgxx_smux_bp_test_s cn; */ +}; + +static inline u64 CGXX_SMUX_BP_TEST(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_BP_TEST(u64 a) +{ + return 0x20230 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_cbfc_ctl + * + * CGX SMU PFC Control Registers Internal: INTERNAL: XOFF for a specific + * class/channel \ is XOFF\ = ([PHYS_EN]\ & cmr_rx_phys_bp) | + * ([LOGL_EN]\ & cmr_rx_logl_xoff\). + */ +union cgxx_smux_cbfc_ctl { + u64 u; + struct cgxx_smux_cbfc_ctl_s { + u64 rx_en : 1; + u64 tx_en : 1; + u64 drp_en : 1; + u64 bck_en : 1; + u64 reserved_4_31 : 28; + u64 logl_en : 16; + u64 phys_en : 16; + } s; + /* struct cgxx_smux_cbfc_ctl_s cn; */ +}; + +static inline u64 CGXX_SMUX_CBFC_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_CBFC_CTL(u64 a) +{ + return 0x20218 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_ctrl + * + * CGX SMU Control Registers + */ +union cgxx_smux_ctrl { + u64 u; + struct cgxx_smux_ctrl_s { + u64 rx_idle : 1; + u64 tx_idle : 1; + u64 reserved_2_63 : 62; + } s; + /* struct cgxx_smux_ctrl_s cn; */ +}; + +static inline u64 CGXX_SMUX_CTRL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_CTRL(u64 a) +{ + return 0x20200 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_ext_loopback + * + * CGX SMU External Loopback Registers In loopback mode, the IFG1+IFG2 of + * local and remote parties must match exactly; otherwise loopback FIFO + * will overrun: CGX()_SMU()_TX_INT[LB_OVRFLW]. + */ +union cgxx_smux_ext_loopback { + u64 u; + struct cgxx_smux_ext_loopback_s { + u64 thresh : 6; + u64 reserved_6_7 : 2; + u64 depth : 6; + u64 reserved_14_15 : 2; + u64 en : 1; + u64 reserved_17_63 : 47; + } s; + /* struct cgxx_smux_ext_loopback_s cn; */ +}; + +static inline u64 CGXX_SMUX_EXT_LOOPBACK(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_EXT_LOOPBACK(u64 a) +{ + return 0x20208 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_hg2_control + * + * CGX SMU HiGig2 Control Registers HiGig2 TX- and RX-enable are normally + * set together for HiGig2 messaging. Setting just the TX or RX bit + * results in only the HG2 message transmit or receive capability. + * Setting [PHYS_EN] and [LOGL_EN] to 1 allows link PAUSE or backpressure + * to NIX as per the received HiGig2 message. Setting these fields to 0 + * disables link PAUSE and backpressure to NIX in response to received + * messages. CGX()_SMU()_TX_CTL[HG_EN] must be set (to enable HiGig) + * whenever either [HG2TX_EN] or [HG2RX_EN] are set. + * CGX()_SMU()_RX_UDD_SKP[LEN] must be set to 16 (to select HiGig2) + * whenever either [HG2TX_EN] or [HG2RX_EN] are set. + * CGX()_CMR_RX_OVR_BP[EN]\<0\> must be set and + * CGX()_CMR_RX_OVR_BP[BP]\<0\> must be cleared to 0 (to forcibly disable + * hardware-automatic 802.3 PAUSE packet generation) with the HiGig2 + * Protocol when [HG2TX_EN] = 0. (The HiGig2 protocol is indicated by + * CGX()_SMU()_TX_CTL[HG_EN] = 1 and CGX()_SMU()_RX_UDD_SKP[LEN]=16.) + * Hardware can only autogenerate backpressure via HiGig2 messages + * (optionally, when [HG2TX_EN] = 1) with the HiGig2 protocol. + */ +union cgxx_smux_hg2_control { + u64 u; + struct cgxx_smux_hg2_control_s { + u64 logl_en : 16; + u64 phys_en : 1; + u64 hg2rx_en : 1; + u64 hg2tx_en : 1; + u64 reserved_19_63 : 45; + } s; + /* struct cgxx_smux_hg2_control_s cn; */ +}; + +static inline u64 CGXX_SMUX_HG2_CONTROL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_HG2_CONTROL(u64 a) +{ + return 0x20210 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_mmsi_ctl_sta + * + * CGX SMU MAC Merge Service Interface (MMSI) Control/Status Registers + * MMSI control and status registers for frame preemption mode. Refer to + * IEEE 802.3br, Clause 99. + */ +union cgxx_smux_mmsi_ctl_sta { + u64 u; + struct cgxx_smux_mmsi_ctl_sta_s { + u64 p_en : 1; + u64 dis_v : 1; + u64 afs : 2; + u64 v_sta : 3; + u64 tx_pactive : 1; + u64 reserved_8_31 : 24; + u64 v_time : 24; + u64 reserved_56_63 : 8; + } s; + /* struct cgxx_smux_mmsi_ctl_sta_s cn; */ +}; + +static inline u64 CGXX_SMUX_MMSI_CTL_STA(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_MMSI_CTL_STA(u64 a) +{ + return 0x20220 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_rx_bad_col_ctrl + * + * CGX SMU RX Bad Column High Registers + */ +union cgxx_smux_rx_bad_col_ctrl { + u64 u; + struct cgxx_smux_rx_bad_col_ctrl_s { + u64 lane_rxc : 16; + u64 state : 3; + u64 val : 1; + u64 reserved_20_63 : 44; + } s; + /* struct cgxx_smux_rx_bad_col_ctrl_s cn; */ +}; + +static inline u64 CGXX_SMUX_RX_BAD_COL_CTRL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_RX_BAD_COL_CTRL(u64 a) +{ + return 0x20060 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_rx_bad_col_data_hi + * + * CGX SMU RX Bad Column Low Registers + */ +union cgxx_smux_rx_bad_col_data_hi { + u64 u; + struct cgxx_smux_rx_bad_col_data_hi_s { + u64 lane_rxd : 64; + } s; + /* struct cgxx_smux_rx_bad_col_data_hi_s cn; */ +}; + +static inline u64 CGXX_SMUX_RX_BAD_COL_DATA_HI(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_RX_BAD_COL_DATA_HI(u64 a) +{ + return 0x20058 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_rx_bad_col_data_lo + * + * CGX SMU RX Bad Column Low Registers + */ +union cgxx_smux_rx_bad_col_data_lo { + u64 u; + struct cgxx_smux_rx_bad_col_data_lo_s { + u64 lane_rxd : 64; + } s; + /* struct cgxx_smux_rx_bad_col_data_lo_s cn; */ +}; + +static inline u64 CGXX_SMUX_RX_BAD_COL_DATA_LO(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_RX_BAD_COL_DATA_LO(u64 a) +{ + return 0x20050 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_rx_ctl + * + * CGX SMU RX Control Registers + */ +union cgxx_smux_rx_ctl { + u64 u; + struct cgxx_smux_rx_ctl_s { + u64 status : 2; + u64 reserved_2_63 : 62; + } s; + /* struct cgxx_smux_rx_ctl_s cn; */ +}; + +static inline u64 CGXX_SMUX_RX_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_RX_CTL(u64 a) +{ + return 0x20048 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_rx_decision + * + * CGX SMU Packet Decision Registers This register specifies the byte + * count used to determine when to accept or to filter a packet. As each + * byte in a packet is received by CGX, the L2 byte count (i.e. the + * number of bytes from the beginning of the L2 header (DMAC)) is + * compared against CNT. In normal operation, the L2 header begins after + * the PREAMBLE + SFD (CGX()_SMU()_RX_FRM_CTL[PRE_CHK] = 1) and any + * optional UDD skip data (CGX()_SMU()_RX_UDD_SKP[LEN]). + */ +union cgxx_smux_rx_decision { + u64 u; + struct cgxx_smux_rx_decision_s { + u64 cnt : 5; + u64 reserved_5_63 : 59; + } s; + /* struct cgxx_smux_rx_decision_s cn; */ +}; + +static inline u64 CGXX_SMUX_RX_DECISION(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_RX_DECISION(u64 a) +{ + return 0x20038 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_rx_frm_chk + * + * CGX SMU RX Frame Check Registers The CSRs provide the enable bits for + * a subset of errors passed to CMR encoded. + */ +union cgxx_smux_rx_frm_chk { + u64 u; + struct cgxx_smux_rx_frm_chk_s { + u64 reserved_0_2 : 3; + u64 jabber : 1; + u64 fcserr_d : 1; + u64 fcserr_c : 1; + u64 reserved_6 : 1; + u64 rcverr : 1; + u64 skperr : 1; + u64 reserved_9_63 : 55; + } s; + /* struct cgxx_smux_rx_frm_chk_s cn; */ +}; + +static inline u64 CGXX_SMUX_RX_FRM_CHK(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_RX_FRM_CHK(u64 a) +{ + return 0x20028 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_rx_frm_ctl + * + * CGX SMU RX Frame Control Registers This register controls the handling + * of the frames. The [CTL_BCK] and [CTL_DRP] bits control how the + * hardware handles incoming PAUSE packets. The most common modes of + * operation: _ [CTL_BCK] = 1, [CTL_DRP] = 1: hardware handles everything + * _ [CTL_BCK] = 0, [CTL_DRP] = 0: software sees all PAUSE frames _ + * [CTL_BCK] = 0, [CTL_DRP] = 1: all PAUSE frames are completely ignored + * These control bits should be set to [CTL_BCK] = 0, [CTL_DRP] = 0 in + * half-duplex mode. Since PAUSE packets only apply to full duplex + * operation, any PAUSE packet would constitute an exception which should + * be handled by the processing cores. PAUSE packets should not be + * forwarded. + */ +union cgxx_smux_rx_frm_ctl { + u64 u; + struct cgxx_smux_rx_frm_ctl_s { + u64 pre_chk : 1; + u64 pre_strp : 1; + u64 ctl_drp : 1; + u64 ctl_bck : 1; + u64 ctl_mcst : 1; + u64 ctl_smac : 1; + u64 reserved_6_11 : 6; + u64 ptp_mode : 1; + u64 reserved_13_63 : 51; + } s; + /* struct cgxx_smux_rx_frm_ctl_s cn; */ +}; + +static inline u64 CGXX_SMUX_RX_FRM_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_RX_FRM_CTL(u64 a) +{ + return 0x20020 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_rx_int + * + * CGX SMU Receive Interrupt Registers SMU Interrupt Register. Internal: + * Exception conditions \<9\> and \<4:0\> can also set the rcv/opcode in + * the received packet's work queue entry. CGX()_SMU()_RX_FRM_CHK + * provides a bit mask for configuring which conditions set the error. + */ +union cgxx_smux_rx_int { + u64 u; + struct cgxx_smux_rx_int_s { + u64 jabber : 1; + u64 fcserr : 1; + u64 rcverr : 1; + u64 skperr : 1; + u64 pcterr : 1; + u64 rsverr : 1; + u64 loc_fault : 1; + u64 rem_fault : 1; + u64 bad_seq : 1; + u64 bad_term : 1; + u64 hg2fld : 1; + u64 hg2cc : 1; + u64 badver : 1; + u64 badrsp : 1; + u64 reserved_14_63 : 50; + } s; + /* struct cgxx_smux_rx_int_s cn; */ +}; + +static inline u64 CGXX_SMUX_RX_INT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_RX_INT(u64 a) +{ + return 0x20000 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_rx_int_ena_w1c + * + * CGX SMU Receive Interrupt Enable Clear Registers This register clears + * interrupt enable bits. + */ +union cgxx_smux_rx_int_ena_w1c { + u64 u; + struct cgxx_smux_rx_int_ena_w1c_s { + u64 jabber : 1; + u64 fcserr : 1; + u64 rcverr : 1; + u64 skperr : 1; + u64 pcterr : 1; + u64 rsverr : 1; + u64 loc_fault : 1; + u64 rem_fault : 1; + u64 bad_seq : 1; + u64 bad_term : 1; + u64 hg2fld : 1; + u64 hg2cc : 1; + u64 badver : 1; + u64 badrsp : 1; + u64 reserved_14_63 : 50; + } s; + /* struct cgxx_smux_rx_int_ena_w1c_s cn; */ +}; + +static inline u64 CGXX_SMUX_RX_INT_ENA_W1C(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_RX_INT_ENA_W1C(u64 a) +{ + return 0x20010 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_rx_int_ena_w1s + * + * CGX SMU Receive Interrupt Enable Set Registers This register sets + * interrupt enable bits. + */ +union cgxx_smux_rx_int_ena_w1s { + u64 u; + struct cgxx_smux_rx_int_ena_w1s_s { + u64 jabber : 1; + u64 fcserr : 1; + u64 rcverr : 1; + u64 skperr : 1; + u64 pcterr : 1; + u64 rsverr : 1; + u64 loc_fault : 1; + u64 rem_fault : 1; + u64 bad_seq : 1; + u64 bad_term : 1; + u64 hg2fld : 1; + u64 hg2cc : 1; + u64 badver : 1; + u64 badrsp : 1; + u64 reserved_14_63 : 50; + } s; + /* struct cgxx_smux_rx_int_ena_w1s_s cn; */ +}; + +static inline u64 CGXX_SMUX_RX_INT_ENA_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_RX_INT_ENA_W1S(u64 a) +{ + return 0x20018 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_rx_int_w1s + * + * CGX SMU Receive Interrupt Set Registers This register sets interrupt + * bits. + */ +union cgxx_smux_rx_int_w1s { + u64 u; + struct cgxx_smux_rx_int_w1s_s { + u64 jabber : 1; + u64 fcserr : 1; + u64 rcverr : 1; + u64 skperr : 1; + u64 pcterr : 1; + u64 rsverr : 1; + u64 loc_fault : 1; + u64 rem_fault : 1; + u64 bad_seq : 1; + u64 bad_term : 1; + u64 hg2fld : 1; + u64 hg2cc : 1; + u64 badver : 1; + u64 badrsp : 1; + u64 reserved_14_63 : 50; + } s; + /* struct cgxx_smux_rx_int_w1s_s cn; */ +}; + +static inline u64 CGXX_SMUX_RX_INT_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_RX_INT_W1S(u64 a) +{ + return 0x20008 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_rx_jabber + * + * CGX SMU Maximum Packet-Size Registers This register specifies the + * maximum size for packets, beyond which the SMU truncates. Internal: + * JABBER[CNT] is checked against the packet that arrives from SPU. The + * checking is performed before preamble is stripped or PTP is inserted. + * If present, preamble is counted as eight bytes of the incoming packet. + */ +union cgxx_smux_rx_jabber { + u64 u; + struct cgxx_smux_rx_jabber_s { + u64 cnt : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_smux_rx_jabber_s cn; */ +}; + +static inline u64 CGXX_SMUX_RX_JABBER(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_RX_JABBER(u64 a) +{ + return 0x20030 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_rx_udd_skp + * + * CGX SMU User-Defined Data Skip Registers Internal: (1) The skip bytes + * are part of the packet and will be sent down the NCB packet interface + * and will be handled by NIX. (2) The system can determine if the UDD + * bytes are included in the FCS check by using the FCSSEL field if the + * FCS check is enabled. (3) Assume that the preamble/sfd is always at + * the start of the frame even before UDD bytes. In most cases, there + * will be no preamble in these cases since it will be packet interface + * in direct communication to another packet interface (MAC to MAC) + * without a PHY involved. (4) We can still do address filtering and + * control packet filtering if the user desires. (5) In all cases, the + * UDD bytes will be sent down the packet interface as part of the + * packet. The UDD bytes are never stripped from the actual packet. + */ +union cgxx_smux_rx_udd_skp { + u64 u; + struct cgxx_smux_rx_udd_skp_s { + u64 len : 7; + u64 reserved_7 : 1; + u64 fcssel : 1; + u64 reserved_9_63 : 55; + } s; + /* struct cgxx_smux_rx_udd_skp_s cn; */ +}; + +static inline u64 CGXX_SMUX_RX_UDD_SKP(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_RX_UDD_SKP(u64 a) +{ + return 0x20040 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_rx_wol_ctrl0 + * + * CGX SMU RX Wake-on-LAN Control 0 Registers + */ +union cgxx_smux_rx_wol_ctrl0 { + u64 u; + struct cgxx_smux_rx_wol_ctrl0_s { + u64 dmac : 48; + u64 pswd_len : 4; + u64 reserved_52_63 : 12; + } s; + /* struct cgxx_smux_rx_wol_ctrl0_s cn; */ +}; + +static inline u64 CGXX_SMUX_RX_WOL_CTRL0(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_RX_WOL_CTRL0(u64 a) +{ + return 0x20068 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_rx_wol_ctrl1 + * + * CGX SMU RX Wake-on-LAN Control 1 Registers + */ +union cgxx_smux_rx_wol_ctrl1 { + u64 u; + struct cgxx_smux_rx_wol_ctrl1_s { + u64 pswd : 64; + } s; + /* struct cgxx_smux_rx_wol_ctrl1_s cn; */ +}; + +static inline u64 CGXX_SMUX_RX_WOL_CTRL1(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_RX_WOL_CTRL1(u64 a) +{ + return 0x20070 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_rx_wol_int + * + * CGX SMU RX WOL Interrupt Registers These registers allow WOL + * interrupts to be sent to the control processor. + */ +union cgxx_smux_rx_wol_int { + u64 u; + struct cgxx_smux_rx_wol_int_s { + u64 wol_rcvd : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_smux_rx_wol_int_s cn; */ +}; + +static inline u64 CGXX_SMUX_RX_WOL_INT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_RX_WOL_INT(u64 a) +{ + return 0x20078 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_rx_wol_int_ena_w1c + * + * CGX SMU RX WOL Interrupt Enable Clear Registers This register clears + * interrupt enable bits. + */ +union cgxx_smux_rx_wol_int_ena_w1c { + u64 u; + struct cgxx_smux_rx_wol_int_ena_w1c_s { + u64 wol_rcvd : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_smux_rx_wol_int_ena_w1c_s cn; */ +}; + +static inline u64 CGXX_SMUX_RX_WOL_INT_ENA_W1C(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_RX_WOL_INT_ENA_W1C(u64 a) +{ + return 0x20088 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_rx_wol_int_ena_w1s + * + * CGX SMU RX WOL Interrupt Enable Set Registers This register sets + * interrupt enable bits. + */ +union cgxx_smux_rx_wol_int_ena_w1s { + u64 u; + struct cgxx_smux_rx_wol_int_ena_w1s_s { + u64 wol_rcvd : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_smux_rx_wol_int_ena_w1s_s cn; */ +}; + +static inline u64 CGXX_SMUX_RX_WOL_INT_ENA_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_RX_WOL_INT_ENA_W1S(u64 a) +{ + return 0x20090 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_rx_wol_int_w1s + * + * CGX SMU RX WOL Interrupt Set Registers This register sets interrupt + * bits. + */ +union cgxx_smux_rx_wol_int_w1s { + u64 u; + struct cgxx_smux_rx_wol_int_w1s_s { + u64 wol_rcvd : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_smux_rx_wol_int_w1s_s cn; */ +}; + +static inline u64 CGXX_SMUX_RX_WOL_INT_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_RX_WOL_INT_W1S(u64 a) +{ + return 0x20080 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_smac + * + * CGX SMU SMAC Registers + */ +union cgxx_smux_smac { + u64 u; + struct cgxx_smux_smac_s { + u64 smac : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_smux_smac_s cn; */ +}; + +static inline u64 CGXX_SMUX_SMAC(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_SMAC(u64 a) +{ + return 0x20108 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_append + * + * CGX SMU TX Append Control Registers For more details on the + * interactions between FCS and PAD, see also the description of + * CGX()_SMU()_TX_MIN_PKT[MIN_SIZE]. + */ +union cgxx_smux_tx_append { + u64 u; + struct cgxx_smux_tx_append_s { + u64 preamble : 1; + u64 pad : 1; + u64 fcs_d : 1; + u64 fcs_c : 1; + u64 reserved_4_63 : 60; + } s; + /* struct cgxx_smux_tx_append_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_APPEND(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_APPEND(u64 a) +{ + return 0x20100 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_ctl + * + * CGX SMU Transmit Control Registers + */ +union cgxx_smux_tx_ctl { + u64 u; + struct cgxx_smux_tx_ctl_s { + u64 dic_en : 1; + u64 uni_en : 1; + u64 x4a_dis : 1; + u64 mia_en : 1; + u64 ls : 2; + u64 ls_byp : 1; + u64 l2p_bp_conv : 1; + u64 hg_en : 1; + u64 hg_pause_hgi : 2; + u64 reserved_11_63 : 53; + } s; + /* struct cgxx_smux_tx_ctl_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_CTL(u64 a) +{ + return 0x20178 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_dack + * + * CGX SMU TX Drop Counters Registers + */ +union cgxx_smux_tx_dack { + u64 u; + struct cgxx_smux_tx_dack_s { + u64 dpi_sdrop_ack : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_smux_tx_dack_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_DACK(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_DACK(u64 a) +{ + return 0x201b0 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_dcnt + * + * CGX SMU TX Drop Counters Registers + */ +union cgxx_smux_tx_dcnt { + u64 u; + struct cgxx_smux_tx_dcnt_s { + u64 dpi_sdrop_cnt : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_smux_tx_dcnt_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_DCNT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_DCNT(u64 a) +{ + return 0x201a8 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_eee + * + * INTERNAL: CGX SMU TX EEE Configure Registers Resvered. Internal: + * These registers control when SMU TX requests to enter or exist LPI. + * Those registers take effect only when EEE is supported and enabled for + * a given LMAC. + */ +union cgxx_smux_tx_eee { + u64 u; + struct cgxx_smux_tx_eee_s { + u64 idle_thresh : 28; + u64 reserved_28 : 1; + u64 force_lpi : 1; + u64 wakeup : 1; + u64 auto_lpi : 1; + u64 idle_cnt : 28; + u64 reserved_60_61 : 2; + u64 tx_lpi_wake : 1; + u64 tx_lpi : 1; + } s; + /* struct cgxx_smux_tx_eee_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_EEE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_EEE(u64 a) +{ + return 0x20190 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_eee_timer_status + * + * INTERNAL: CGX SMU TX EEE TIMER STATUS Registers Reserved. Internal: + * These registers configure SMU TX EEE timing parameters. + */ +union cgxx_smux_tx_eee_timer_status { + u64 u; + struct cgxx_smux_tx_eee_timer_status_s { + u64 lpi_wake_cnt : 16; + u64 reserved_16_30 : 15; + u64 wake_timer_done : 1; + u64 link_ok_cnt : 30; + u64 reserved_62 : 1; + u64 link_timer_done : 1; + } s; + /* struct cgxx_smux_tx_eee_timer_status_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_EEE_TIMER_STATUS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_EEE_TIMER_STATUS(u64 a) +{ + return 0x201a0 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_eee_timing + * + * INTERNAL: CGX SMU TX EEE TIMING Parameter Registers Reserved. + * Internal: These registers configure SMU TX EEE timing parameters. + */ +union cgxx_smux_tx_eee_timing { + u64 u; + struct cgxx_smux_tx_eee_timing_s { + u64 w_sys_tx_min : 16; + u64 reserved_16_31 : 16; + u64 link_ok_min : 30; + u64 reserved_62_63 : 2; + } s; + /* struct cgxx_smux_tx_eee_timing_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_EEE_TIMING(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_EEE_TIMING(u64 a) +{ + return 0x20198 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_ifg + * + * CGX SMU TX Interframe-Gap Cycles Registers Programming IFG1 and IFG2: + * * For XAUI/RXAUI/10G/25G/40G/50G/100G systems that require IEEE 802.3 + * compatibility, the [IFG1]+[IFG2] sum must be 12. * In loopback mode, + * the [IFG1]+[IFG2] of local and remote parties must match exactly; + * otherwise loopback FIFO will overrun: CGX()_SMU()_TX_INT[LB_OVRFLW]. * + * When CGX()_SMU()_TX_CTL[DIC_EN] is set, [IFG1]+[IFG2] sum must be at + * least 8. The behavior of smaller values is un-determined. * When + * CGX()_SMU()_TX_CTL[DIC_EN] is cleared, the minimum value of + * [IFG1]+[IFG2] is 1 for 40G/50G/100G LMAC_TYPE configurations and 5 for + * all other values. The behavior of smaller values is un-determined. + * Internal: When CGX()_SMU()_TX_CTL[DIC_EN] is set, SMU TX treats + * ([IFG1]+[IFG2]) \< 8 as 8 for 40G/50G/100G MACs and ([IFG1]+[IFG2]) \< + * 8 as 8 for other MACs. When CGX()_SMU()_TX_CTL[DIC_EN] is cleared, SMU + * TX can work correctly with any IFG1 and IFG2. + */ +union cgxx_smux_tx_ifg { + u64 u; + struct cgxx_smux_tx_ifg_s { + u64 ifg1 : 4; + u64 ifg2 : 4; + u64 mia_amt : 2; + u64 reserved_10_15 : 6; + u64 mia_cnt : 8; + u64 reserved_24_63 : 40; + } s; + /* struct cgxx_smux_tx_ifg_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_IFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_IFG(u64 a) +{ + return 0x20160 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_int + * + * CGX SMU TX Interrupt Registers + */ +union cgxx_smux_tx_int { + u64 u; + struct cgxx_smux_tx_int_s { + u64 undflw : 1; + u64 xchange : 1; + u64 fake_commit : 1; + u64 lb_undflw : 1; + u64 lb_ovrflw : 1; + u64 dpi_sdrop : 1; + u64 reserved_6_63 : 58; + } s; + /* struct cgxx_smux_tx_int_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_INT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_INT(u64 a) +{ + return 0x20140 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_int_ena_w1c + * + * CGX SMU TX Interrupt Enable Clear Registers This register clears + * interrupt enable bits. + */ +union cgxx_smux_tx_int_ena_w1c { + u64 u; + struct cgxx_smux_tx_int_ena_w1c_s { + u64 undflw : 1; + u64 xchange : 1; + u64 fake_commit : 1; + u64 lb_undflw : 1; + u64 lb_ovrflw : 1; + u64 dpi_sdrop : 1; + u64 reserved_6_63 : 58; + } s; + /* struct cgxx_smux_tx_int_ena_w1c_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_INT_ENA_W1C(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_INT_ENA_W1C(u64 a) +{ + return 0x20150 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_int_ena_w1s + * + * CGX SMU TX Interrupt Enable Set Registers This register sets interrupt + * enable bits. + */ +union cgxx_smux_tx_int_ena_w1s { + u64 u; + struct cgxx_smux_tx_int_ena_w1s_s { + u64 undflw : 1; + u64 xchange : 1; + u64 fake_commit : 1; + u64 lb_undflw : 1; + u64 lb_ovrflw : 1; + u64 dpi_sdrop : 1; + u64 reserved_6_63 : 58; + } s; + /* struct cgxx_smux_tx_int_ena_w1s_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_INT_ENA_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_INT_ENA_W1S(u64 a) +{ + return 0x20158 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_int_w1s + * + * CGX SMU TX Interrupt Set Registers This register sets interrupt bits. + */ +union cgxx_smux_tx_int_w1s { + u64 u; + struct cgxx_smux_tx_int_w1s_s { + u64 undflw : 1; + u64 xchange : 1; + u64 fake_commit : 1; + u64 lb_undflw : 1; + u64 lb_ovrflw : 1; + u64 dpi_sdrop : 1; + u64 reserved_6_63 : 58; + } s; + /* struct cgxx_smux_tx_int_w1s_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_INT_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_INT_W1S(u64 a) +{ + return 0x20148 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_min_pkt + * + * CGX SMU TX Minimum-Size-Packet Registers Internal: [MIN_SIZE] less + * than 16 will be ignored by hardware which will use 16 instead. + */ +union cgxx_smux_tx_min_pkt { + u64 u; + struct cgxx_smux_tx_min_pkt_s { + u64 min_size : 8; + u64 reserved_8_63 : 56; + } s; + /* struct cgxx_smux_tx_min_pkt_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_MIN_PKT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_MIN_PKT(u64 a) +{ + return 0x20118 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_pause_pkt_dmac + * + * CGX SMU TX PAUSE-Packet DMAC-Field Registers This register provides + * the DMAC value that is placed in outbound PAUSE packets. + */ +union cgxx_smux_tx_pause_pkt_dmac { + u64 u; + struct cgxx_smux_tx_pause_pkt_dmac_s { + u64 dmac : 48; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_smux_tx_pause_pkt_dmac_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_PAUSE_PKT_DMAC(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_PAUSE_PKT_DMAC(u64 a) +{ + return 0x20168 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_pause_pkt_interval + * + * CGX SMU TX PAUSE-Packet Transmission-Interval Registers This register + * specifies how often PAUSE packets are sent. + */ +union cgxx_smux_tx_pause_pkt_interval { + u64 u; + struct cgxx_smux_tx_pause_pkt_interval_s { + u64 interval : 16; + u64 hg2_intra_interval : 16; + u64 hg2_intra_en : 1; + u64 reserved_33_63 : 31; + } s; + /* struct cgxx_smux_tx_pause_pkt_interval_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_PAUSE_PKT_INTERVAL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_PAUSE_PKT_INTERVAL(u64 a) +{ + return 0x20120 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_pause_pkt_time + * + * CGX SMU TX PAUSE Packet Time Registers + */ +union cgxx_smux_tx_pause_pkt_time { + u64 u; + struct cgxx_smux_tx_pause_pkt_time_s { + u64 p_time : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_smux_tx_pause_pkt_time_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_PAUSE_PKT_TIME(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_PAUSE_PKT_TIME(u64 a) +{ + return 0x20110 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_pause_pkt_type + * + * CGX SMU TX PAUSE-Packet P_TYPE-Field Registers This register provides + * the P_TYPE field that is placed in outbound PAUSE packets. + */ +union cgxx_smux_tx_pause_pkt_type { + u64 u; + struct cgxx_smux_tx_pause_pkt_type_s { + u64 p_type : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_smux_tx_pause_pkt_type_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_PAUSE_PKT_TYPE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_PAUSE_PKT_TYPE(u64 a) +{ + return 0x20170 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_pause_togo + * + * CGX SMU TX Time-to-Backpressure Registers + */ +union cgxx_smux_tx_pause_togo { + u64 u; + struct cgxx_smux_tx_pause_togo_s { + u64 p_time : 16; + u64 msg_time : 16; + u64 reserved_32_63 : 32; + } s; + /* struct cgxx_smux_tx_pause_togo_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_PAUSE_TOGO(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_PAUSE_TOGO(u64 a) +{ + return 0x20130 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_pause_zero + * + * CGX SMU TX PAUSE Zero Registers + */ +union cgxx_smux_tx_pause_zero { + u64 u; + struct cgxx_smux_tx_pause_zero_s { + u64 send : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_smux_tx_pause_zero_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_PAUSE_ZERO(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_PAUSE_ZERO(u64 a) +{ + return 0x20138 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_soft_pause + * + * CGX SMU TX Soft PAUSE Registers + */ +union cgxx_smux_tx_soft_pause { + u64 u; + struct cgxx_smux_tx_soft_pause_s { + u64 p_time : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_smux_tx_soft_pause_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_SOFT_PAUSE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_SOFT_PAUSE(u64 a) +{ + return 0x20128 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_smu#_tx_thresh + * + * CGX SMU TX Threshold Registers + */ +union cgxx_smux_tx_thresh { + u64 u; + struct cgxx_smux_tx_thresh_s { + u64 cnt : 12; + u64 reserved_12_15 : 4; + u64 dpi_thresh : 5; + u64 reserved_21_23 : 3; + u64 dpi_depth : 5; + u64 reserved_29_31 : 3; + u64 ecnt : 12; + u64 reserved_44_63 : 20; + } s; + /* struct cgxx_smux_tx_thresh_s cn; */ +}; + +static inline u64 CGXX_SMUX_TX_THRESH(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SMUX_TX_THRESH(u64 a) +{ + return 0x20180 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_an_adv + * + * CGX SPU Autonegotiation Advertisement Registers Software programs this + * register with the contents of the AN-link code word base page to be + * transmitted during autonegotiation. (See IEEE 802.3 section 73.6 for + * details.) Any write operations to this register prior to completion of + * autonegotiation, as indicated by CGX()_SPU()_AN_STATUS[AN_COMPLETE], + * should be followed by a renegotiation in order for the new values to + * take effect. Renegotiation is initiated by setting + * CGX()_SPU()_AN_CONTROL[AN_RESTART]. Once autonegotiation has + * completed, software can examine this register along with + * CGX()_SPU()_AN_LP_BASE to determine the highest common denominator + * technology. + */ +union cgxx_spux_an_adv { + u64 u; + struct cgxx_spux_an_adv_s { + u64 s : 5; + u64 e : 5; + u64 pause : 1; + u64 asm_dir : 1; + u64 xnp_able : 1; + u64 rf : 1; + u64 ack : 1; + u64 np : 1; + u64 t : 5; + u64 a1g_kx : 1; + u64 a10g_kx4 : 1; + u64 a10g_kr : 1; + u64 a40g_kr4 : 1; + u64 a40g_cr4 : 1; + u64 a100g_cr10 : 1; + u64 a100g_kp4 : 1; + u64 a100g_kr4 : 1; + u64 a100g_cr4 : 1; + u64 a25g_krs_crs : 1; + u64 a25g_kr_cr : 1; + u64 arsv : 12; + u64 a25g_rs_fec_req : 1; + u64 a25g_br_fec_req : 1; + u64 fec_able : 1; + u64 fec_req : 1; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_spux_an_adv_s cn; */ +}; + +static inline u64 CGXX_SPUX_AN_ADV(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_AN_ADV(u64 a) +{ + return 0x10198 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_an_bp_status + * + * CGX SPU Autonegotiation Backplane Ethernet & BASE-R Copper Status + * Registers The contents of this register are updated during + * autonegotiation and are valid when CGX()_SPU()_AN_STATUS[AN_COMPLETE] + * is set. At that time, one of the port type bits will be set depending + * on the AN priority resolution. The port types are listed in order of + * decreasing priority. If a BASE-R type is negotiated then [FEC] or + * [RS_FEC] will be set to indicate whether/which FEC operation has been + * negotiated and will be clear otherwise. + */ +union cgxx_spux_an_bp_status { + u64 u; + struct cgxx_spux_an_bp_status_s { + u64 bp_an_able : 1; + u64 n1g_kx : 1; + u64 n10g_kx4 : 1; + u64 n10g_kr : 1; + u64 n25g_kr1 : 1; + u64 n25g_cr1 : 1; + u64 n25g_krs_crs : 1; + u64 n25g_kr_cr : 1; + u64 n40g_kr4 : 1; + u64 n40g_cr4 : 1; + u64 n50g_kr2 : 1; + u64 n50g_cr2 : 1; + u64 n100g_cr10 : 1; + u64 n100g_kp4 : 1; + u64 n100g_kr4 : 1; + u64 n100g_cr4 : 1; + u64 fec : 1; + u64 rs_fec : 1; + u64 reserved_18_63 : 46; + } s; + /* struct cgxx_spux_an_bp_status_s cn; */ +}; + +static inline u64 CGXX_SPUX_AN_BP_STATUS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_AN_BP_STATUS(u64 a) +{ + return 0x101b8 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_an_control + * + * CGX SPU Autonegotiation Control Registers + */ +union cgxx_spux_an_control { + u64 u; + struct cgxx_spux_an_control_s { + u64 reserved_0_8 : 9; + u64 an_restart : 1; + u64 reserved_10_11 : 2; + u64 an_en : 1; + u64 xnp_en : 1; + u64 reserved_14 : 1; + u64 an_reset : 1; + u64 an_arb_link_chk_en : 1; + u64 usx_an_arb_link_chk_en : 1; + u64 reserved_18_63 : 46; + } s; + /* struct cgxx_spux_an_control_s cn; */ +}; + +static inline u64 CGXX_SPUX_AN_CONTROL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_AN_CONTROL(u64 a) +{ + return 0x10188 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_an_lp_base + * + * CGX SPU Autonegotiation Link-Partner Base-Page Ability Registers This + * register captures the contents of the latest AN link code word base + * page received from the link partner during autonegotiation. (See IEEE + * 802.3 section 73.6 for details.) CGX()_SPU()_AN_STATUS[PAGE_RX] is set + * when this register is updated by hardware. + */ +union cgxx_spux_an_lp_base { + u64 u; + struct cgxx_spux_an_lp_base_s { + u64 s : 5; + u64 e : 5; + u64 pause : 1; + u64 asm_dir : 1; + u64 xnp_able : 1; + u64 rf : 1; + u64 ack : 1; + u64 np : 1; + u64 t : 5; + u64 a1g_kx : 1; + u64 a10g_kx4 : 1; + u64 a10g_kr : 1; + u64 a40g_kr4 : 1; + u64 a40g_cr4 : 1; + u64 a100g_cr10 : 1; + u64 a100g_kp4 : 1; + u64 a100g_kr4 : 1; + u64 a100g_cr4 : 1; + u64 a25g_krs_crs : 1; + u64 a25g_kr_cr : 1; + u64 arsv : 12; + u64 a25g_rs_fec_req : 1; + u64 a25g_br_fec_req : 1; + u64 fec_able : 1; + u64 fec_req : 1; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_spux_an_lp_base_s cn; */ +}; + +static inline u64 CGXX_SPUX_AN_LP_BASE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_AN_LP_BASE(u64 a) +{ + return 0x101a0 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_an_lp_xnp + * + * CGX SPU Autonegotiation Link Partner Extended Next Page Ability + * Registers This register captures the contents of the latest next page + * code word received from the link partner during autonegotiation, if + * any. See IEEE 802.3 section 73.7.7 for details. + */ +union cgxx_spux_an_lp_xnp { + u64 u; + struct cgxx_spux_an_lp_xnp_s { + u64 m_u : 11; + u64 toggle : 1; + u64 ack2 : 1; + u64 mp : 1; + u64 ack : 1; + u64 np : 1; + u64 u : 32; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_spux_an_lp_xnp_s cn; */ +}; + +static inline u64 CGXX_SPUX_AN_LP_XNP(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_AN_LP_XNP(u64 a) +{ + return 0x101b0 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_an_status + * + * CGX SPU Autonegotiation Status Registers + */ +union cgxx_spux_an_status { + u64 u; + struct cgxx_spux_an_status_s { + u64 lp_an_able : 1; + u64 reserved_1 : 1; + u64 link_status : 1; + u64 an_able : 1; + u64 rmt_flt : 1; + u64 an_complete : 1; + u64 page_rx : 1; + u64 xnp_stat : 1; + u64 reserved_8 : 1; + u64 prl_flt : 1; + u64 reserved_10_63 : 54; + } s; + /* struct cgxx_spux_an_status_s cn; */ +}; + +static inline u64 CGXX_SPUX_AN_STATUS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_AN_STATUS(u64 a) +{ + return 0x10190 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_an_xnp_tx + * + * CGX SPU Autonegotiation Extended Next Page Transmit Registers Software + * programs this register with the contents of the AN message next page + * or unformatted next page link code word to be transmitted during + * autonegotiation. Next page exchange occurs after the base link code + * words have been exchanged if either end of the link segment sets the + * NP bit to 1, indicating that it has at least one next page to send. + * Once initiated, next page exchange continues until both ends of the + * link segment set their NP bits to 0. See IEEE 802.3 section 73.7.7 for + * details. + */ +union cgxx_spux_an_xnp_tx { + u64 u; + struct cgxx_spux_an_xnp_tx_s { + u64 m_u : 11; + u64 toggle : 1; + u64 ack2 : 1; + u64 mp : 1; + u64 ack : 1; + u64 np : 1; + u64 u : 32; + u64 reserved_48_63 : 16; + } s; + /* struct cgxx_spux_an_xnp_tx_s cn; */ +}; + +static inline u64 CGXX_SPUX_AN_XNP_TX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_AN_XNP_TX(u64 a) +{ + return 0x101a8 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_br_algn_status + * + * CGX SPU Multilane BASE-R PCS Alignment-Status Registers This register + * implements the IEEE 802.3 multilane BASE-R PCS alignment status 1-4 + * registers (3.50-3.53). It is valid only when the LPCS type is + * 40GBASE-R, 50GBASE-R, 100GBASE-R, (CGX()_CMR()_CONFIG[LMAC_TYPE] = + * CGX_LMAC_TYPES_E::FORTYG_R,FIFTYG_R,HUNDREDG_R), and always returns + * 0x0 for all other LPCS types. Service interfaces (lanes) 19-0 (100G) + * and 3-0 (all others) are mapped to PCS lanes 19-0 or 3-0 via + * CGX()_SPU()_BR_LANE_MAP()[LN_MAPPING]. For 100G, logical lane 0 fans + * out to service interfaces 0-4, logical lane 1 fans out to service + * interfaces 5-9, ... etc. For all other modes, logical lanes and + * service interfaces are identical. Logical interfaces (lanes) map to + * SerDes lanes via CGX()_CMR()_CONFIG[LANE_TO_SDS] (programmable). + */ +union cgxx_spux_br_algn_status { + u64 u; + struct cgxx_spux_br_algn_status_s { + u64 block_lock : 20; + u64 reserved_20_29 : 10; + u64 alignd : 1; + u64 reserved_31_40 : 10; + u64 marker_lock : 20; + u64 reserved_61_63 : 3; + } s; + /* struct cgxx_spux_br_algn_status_s cn; */ +}; + +static inline u64 CGXX_SPUX_BR_ALGN_STATUS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_BR_ALGN_STATUS(u64 a) +{ + return 0x10050 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_br_lane_map# + * + * CGX SPU 40,50,100GBASE-R Lane-Mapping Registers This register + * implements the IEEE 802.3 lane 0-19 mapping registers (3.400-3.403). + * It is valid only when the LPCS type is 40GBASE-R, 50GBASE-R, + * 100GBASE-R, USXGMII (CGX()_CMR()_CONFIG[LMAC_TYPE]), and always + * returns 0x0 for all other LPCS types. The LNx_MAPPING field for each + * programmed PCS lane (called service interface in 802.3) is valid when + * that lane has achieved alignment marker lock on the receive side (i.e. + * the associated CGX()_SPU()_BR_ALGN_STATUS[MARKER_LOCK] = 1), and is + * invalid otherwise. When valid, it returns the actual detected receive + * PCS lane number based on the received alignment marker contents + * received on that service interface. In RS-FEC mode the LNx_MAPPING + * field is valid when that lane has achieved alignment marker lock on + * the receive side (i.e. the associated + * CGX()_SPU()_RSFEC_STATUS[AMPS_LOCK] = 1), and is invalid otherwise. + * When valid, it returns the actual detected receive FEC lane number + * based on the received alignment marker contents received on that + * logical lane therefore expect for RS-FEC that LNx_MAPPING = x. The + * mapping is flexible because IEEE 802.3 allows multilane BASE-R receive + * lanes to be re-ordered. Note that for the transmit side, each logical + * lane is mapped to a physical SerDes lane based on the programming of + * CGX()_CMR()_CONFIG[LANE_TO_SDS]. For the receive side, + * CGX()_CMR()_CONFIG[LANE_TO_SDS] specifies the logical lane to physical + * SerDes lane mapping, and this register specifies the service interface + * (or lane) to PCS lane mapping. + */ +union cgxx_spux_br_lane_mapx { + u64 u; + struct cgxx_spux_br_lane_mapx_s { + u64 ln_mapping : 6; + u64 reserved_6_63 : 58; + } s; + /* struct cgxx_spux_br_lane_mapx_s cn; */ +}; + +static inline u64 CGXX_SPUX_BR_LANE_MAPX(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_BR_LANE_MAPX(u64 a, u64 b) +{ + return 0x10600 + 0x40000 * a + 8 * b; +} + +/** + * Register (RSL) cgx#_spu#_br_pmd_control + * + * CGX SPU BASE-R PMD Control Registers + */ +union cgxx_spux_br_pmd_control { + u64 u; + struct cgxx_spux_br_pmd_control_s { + u64 train_restart : 1; + u64 train_en : 1; + u64 use_lane_poly : 1; + u64 max_wait_disable : 1; + u64 reserved_4_63 : 60; + } s; + struct cgxx_spux_br_pmd_control_cn96xx { + u64 train_restart : 1; + u64 train_en : 1; + u64 use_lane_poly : 1; + u64 reserved_3_63 : 61; + } cn96xx; + /* struct cgxx_spux_br_pmd_control_s cnf95xxp1; */ + /* struct cgxx_spux_br_pmd_control_cn96xx cnf95xxp2; */ +}; + +static inline u64 CGXX_SPUX_BR_PMD_CONTROL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_BR_PMD_CONTROL(u64 a) +{ + return 0x100a8 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_br_pmd_ld_cup + * + * INTERNAL:CGX SPU BASE-R PMD Local Device Coefficient Update Registers + * This register implements MDIO register 1.154 of 802.3-2012 Section 5 + * CL45 for 10GBASE-R and and of 802.3by-2016 CL45 for 25GBASE-R. Note + * that for 10G, 25G LN0_ only is used. It implements MDIO registers + * 1.1300-1.1303 for all other BASE-R modes (40G, 50G, 100G) per + * 802.3bj-2014 CL45. Note that for 50G LN0_ and LN1_ only are used. The + * fields in this register are read/write even though they are specified + * as read-only in 802.3. The register is automatically cleared at the + * start of training. When link training is in progress, each field + * reflects the contents of the coefficient update field in the + * associated lane's outgoing training frame. If + * CGX()_SPU_DBG_CONTROL[BR_PMD_TRAIN_SOFT_EN] is set, then this register + * must be updated by software during link training and hardware updates + * are disabled. If CGX()_SPU_DBG_CONTROL[BR_PMD_TRAIN_SOFT_EN] is clear, + * this register is automatically updated by hardware, and it should not + * be written by software. The lane fields in this register are indexed + * by logical PCS lane ID. + */ +union cgxx_spux_br_pmd_ld_cup { + u64 u; + struct cgxx_spux_br_pmd_ld_cup_s { + u64 ln0_cup : 16; + u64 ln1_cup : 16; + u64 ln2_cup : 16; + u64 ln3_cup : 16; + } s; + /* struct cgxx_spux_br_pmd_ld_cup_s cn; */ +}; + +static inline u64 CGXX_SPUX_BR_PMD_LD_CUP(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_BR_PMD_LD_CUP(u64 a) +{ + return 0x100c8 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_br_pmd_ld_rep + * + * INTERNAL:CGX SPU BASE-R PMD Local Device Status Report Registers This + * register implements MDIO register 1.155 of 802.3-2012 Section 5 CL45 + * for 10GBASE-R and and of 802.3by-2016 CL45 for 25GBASE-R. Note that + * for 10G, 25G LN0_ only is used. It implements MDIO registers + * 1.1400-1.1403 for all other BASE-R modes (40G, 50G, 100G) per + * 802.3bj-2014 CL45. Note that for 50G LN0_ and LN1_ only are used. The + * fields in this register are read/write even though they are specified + * as read-only in 802.3. The register is automatically cleared at the + * start of training. Each field reflects the contents of the status + * report field in the associated lane's outgoing training frame. If + * CGX()_SPU_DBG_CONTROL[BR_PMD_TRAIN_SOFT_EN] is set, then this register + * must be updated by software during link training and hardware updates + * are disabled. If CGX()_SPU_DBG_CONTROL[BR_PMD_TRAIN_SOFT_EN] is clear, + * this register is automatically updated by hardware, and it should not + * be written by software. The lane fields in this register are indexed + * by logical PCS lane ID. + */ +union cgxx_spux_br_pmd_ld_rep { + u64 u; + struct cgxx_spux_br_pmd_ld_rep_s { + u64 ln0_rep : 16; + u64 ln1_rep : 16; + u64 ln2_rep : 16; + u64 ln3_rep : 16; + } s; + /* struct cgxx_spux_br_pmd_ld_rep_s cn; */ +}; + +static inline u64 CGXX_SPUX_BR_PMD_LD_REP(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_BR_PMD_LD_REP(u64 a) +{ + return 0x100d0 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_br_pmd_lp_cup + * + * INTERNAL:CGX SPU BASE-R PMD Link Partner Coefficient Update Registers + * This register implements MDIO register 1.152 of 802.3-2012 Section 5 + * CL45 for 10GBASE-R and and of 802.3by-2016 CL45 for 25GBASE-R. Note + * that for 10G, 25G LN0_ only is used. It implements MDIO registers + * 1.1100-1.1103 for all other BASE-R modes (40G, 50G, 100G) per + * 802.3bj-2014 CL45. Note that for 50G LN0_ and LN1_ only are used. The + * register is automatically cleared at the start of training. Each field + * reflects the contents of the coefficient update field in the lane's + * most recently received training frame. This register should not be + * written when link training is enabled, i.e. when + * CGX()_SPU()_BR_PMD_CONTROL[TRAIN_EN] is set. The lane fields in this + * register are indexed by logical PCS lane ID. + */ +union cgxx_spux_br_pmd_lp_cup { + u64 u; + struct cgxx_spux_br_pmd_lp_cup_s { + u64 ln0_cup : 16; + u64 ln1_cup : 16; + u64 ln2_cup : 16; + u64 ln3_cup : 16; + } s; + /* struct cgxx_spux_br_pmd_lp_cup_s cn; */ +}; + +static inline u64 CGXX_SPUX_BR_PMD_LP_CUP(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_BR_PMD_LP_CUP(u64 a) +{ + return 0x100b8 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_br_pmd_lp_rep + * + * INTERNAL:CGX SPU BASE-R PMD Link Partner Status Report Registers This + * register implements MDIO register 1.153 of 802.3-2012 Section 5 CL45 + * for 10GBASE-R and and of 802.3by-2016 CL45 for 25GBASE-R. Note that + * for 10G, 25G LN0_ only is used. It implements MDIO registers + * 1.1200-1.1203 for all other BASE-R modes (40G, 50G, 100G) per + * 802.3bj-2014 CL45. Note that for 50G LN0_ and LN1_ only are used. The + * register is automatically cleared at the start of training. Each field + * reflects the contents of the coefficient update field in the lane's + * most recently received training frame. This register should not be + * written when link training is enabled, i.e. when + * CGX()_SPU()_BR_PMD_CONTROL[TRAIN_EN] is set. The lane fields in this + * register are indexed by logical PCS lane ID. + */ +union cgxx_spux_br_pmd_lp_rep { + u64 u; + struct cgxx_spux_br_pmd_lp_rep_s { + u64 ln0_rep : 16; + u64 ln1_rep : 16; + u64 ln2_rep : 16; + u64 ln3_rep : 16; + } s; + /* struct cgxx_spux_br_pmd_lp_rep_s cn; */ +}; + +static inline u64 CGXX_SPUX_BR_PMD_LP_REP(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_BR_PMD_LP_REP(u64 a) +{ + return 0x100c0 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_br_pmd_status + * + * INTERNAL:CGX SPU BASE-R PMD Status Registers The lane fields in this + * register are indexed by logical PCS lane ID. The lane 0 field (LN0_*) + * is valid for 10GBASE-R, 25GBASE-R, 40GBASE-R, 50GBASE-R and + * 100GBASE-R. The lane 1 field (LN1_*) is valid for 40GBASE-R, 50GBASE-R + * and 100GBASE-R. The remaining fields (LN2_*, LN3_*) are only valid for + * 40GBASE-R and 100GBASE-R. + */ +union cgxx_spux_br_pmd_status { + u64 u; + struct cgxx_spux_br_pmd_status_s { + u64 ln0_train_status : 4; + u64 ln1_train_status : 4; + u64 ln2_train_status : 4; + u64 ln3_train_status : 4; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_spux_br_pmd_status_s cn; */ +}; + +static inline u64 CGXX_SPUX_BR_PMD_STATUS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_BR_PMD_STATUS(u64 a) +{ + return 0x100b0 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_br_status1 + * + * CGX SPU BASE-R Status 1 Registers + */ +union cgxx_spux_br_status1 { + u64 u; + struct cgxx_spux_br_status1_s { + u64 blk_lock : 1; + u64 hi_ber : 1; + u64 prbs31 : 1; + u64 prbs9 : 1; + u64 reserved_4_11 : 8; + u64 rcv_lnk : 1; + u64 reserved_13_63 : 51; + } s; + /* struct cgxx_spux_br_status1_s cn; */ +}; + +static inline u64 CGXX_SPUX_BR_STATUS1(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_BR_STATUS1(u64 a) +{ + return 0x10030 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_br_status2 + * + * CGX SPU BASE-R Status 2 Registers This register implements a + * combination of the following IEEE 802.3 registers: * BASE-R PCS status + * 2 (MDIO address 3.33). * BASE-R BER high-order counter (MDIO address + * 3.44). * Errored-blocks high-order counter (MDIO address 3.45). Note + * that the relative locations of some fields have been moved from IEEE + * 802.3 in order to make the register layout more software friendly: the + * BER counter high-order and low-order bits from sections 3.44 and 3.33 + * have been combined into the contiguous, 22-bit [BER_CNT] field; + * likewise, the errored-blocks counter high-order and low-order bits + * from section 3.45 have been combined into the contiguous, 22-bit + * [ERR_BLKS] field. + */ +union cgxx_spux_br_status2 { + u64 u; + struct cgxx_spux_br_status2_s { + u64 reserved_0_13 : 14; + u64 latched_ber : 1; + u64 latched_lock : 1; + u64 ber_cnt : 22; + u64 reserved_38_39 : 2; + u64 err_blks : 22; + u64 reserved_62_63 : 2; + } s; + /* struct cgxx_spux_br_status2_s cn; */ +}; + +static inline u64 CGXX_SPUX_BR_STATUS2(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_BR_STATUS2(u64 a) +{ + return 0x10038 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_br_tp_control + * + * CGX SPU BASE-R Test-Pattern Control Registers Refer to the test + * pattern methodology described in 802.3 sections 49.2.8 and 82.2.10. + */ +union cgxx_spux_br_tp_control { + u64 u; + struct cgxx_spux_br_tp_control_s { + u64 dp_sel : 1; + u64 tp_sel : 1; + u64 rx_tp_en : 1; + u64 tx_tp_en : 1; + u64 prbs31_tx : 1; + u64 prbs31_rx : 1; + u64 prbs9_tx : 1; + u64 scramble_tp : 2; + u64 pr_tp_data_type : 1; + u64 reserved_10_63 : 54; + } s; + /* struct cgxx_spux_br_tp_control_s cn; */ +}; + +static inline u64 CGXX_SPUX_BR_TP_CONTROL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_BR_TP_CONTROL(u64 a) +{ + return 0x10040 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_br_tp_err_cnt + * + * CGX SPU BASE-R Test-Pattern Error-Count Registers This register + * provides the BASE-R PCS test-pattern error counter. + */ +union cgxx_spux_br_tp_err_cnt { + u64 u; + struct cgxx_spux_br_tp_err_cnt_s { + u64 err_cnt : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_spux_br_tp_err_cnt_s cn; */ +}; + +static inline u64 CGXX_SPUX_BR_TP_ERR_CNT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_BR_TP_ERR_CNT(u64 a) +{ + return 0x10048 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_br_tp_seed_a + * + * CGX SPU BASE-R Test-Pattern Seed A Registers Refer to the test pattern + * methodology described in 802.3 sections 49.2.8 and 82.2.10. + */ +union cgxx_spux_br_tp_seed_a { + u64 u; + struct cgxx_spux_br_tp_seed_a_s { + u64 tp_seed_a : 58; + u64 reserved_58_63 : 6; + } s; + /* struct cgxx_spux_br_tp_seed_a_s cn; */ +}; + +static inline u64 CGXX_SPUX_BR_TP_SEED_A(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_BR_TP_SEED_A(u64 a) +{ + return 0x10060 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_br_tp_seed_b + * + * CGX SPU BASE-R Test-Pattern Seed B Registers Refer to the test pattern + * methodology described in 802.3 sections 49.2.8 and 82.2.10. + */ +union cgxx_spux_br_tp_seed_b { + u64 u; + struct cgxx_spux_br_tp_seed_b_s { + u64 tp_seed_b : 58; + u64 reserved_58_63 : 6; + } s; + /* struct cgxx_spux_br_tp_seed_b_s cn; */ +}; + +static inline u64 CGXX_SPUX_BR_TP_SEED_B(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_BR_TP_SEED_B(u64 a) +{ + return 0x10068 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_bx_status + * + * CGX SPU BASE-X Status Registers + */ +union cgxx_spux_bx_status { + u64 u; + struct cgxx_spux_bx_status_s { + u64 lsync : 4; + u64 reserved_4_10 : 7; + u64 pattst : 1; + u64 alignd : 1; + u64 reserved_13_63 : 51; + } s; + /* struct cgxx_spux_bx_status_s cn; */ +}; + +static inline u64 CGXX_SPUX_BX_STATUS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_BX_STATUS(u64 a) +{ + return 0x10028 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_control1 + * + * CGX SPU Control 1 Registers + */ +union cgxx_spux_control1 { + u64 u; + struct cgxx_spux_control1_s { + u64 reserved_0_1 : 2; + u64 spd : 4; + u64 spdsel0 : 1; + u64 reserved_7_10 : 4; + u64 lo_pwr : 1; + u64 reserved_12 : 1; + u64 spdsel1 : 1; + u64 loopbck : 1; + u64 reset : 1; + u64 usxgmii_type : 3; + u64 usxgmii_rate : 3; + u64 disable_am : 1; + u64 reserved_23_63 : 41; + } s; + struct cgxx_spux_control1_cn96xxp1 { + u64 reserved_0_1 : 2; + u64 spd : 4; + u64 spdsel0 : 1; + u64 reserved_7_10 : 4; + u64 lo_pwr : 1; + u64 reserved_12 : 1; + u64 spdsel1 : 1; + u64 loopbck : 1; + u64 reset : 1; + u64 usxgmii_type : 3; + u64 usxgmii_rate : 3; + u64 reserved_22_63 : 42; + } cn96xxp1; + /* struct cgxx_spux_control1_s cn96xxp3; */ + /* struct cgxx_spux_control1_cn96xxp1 cnf95xxp1; */ + struct cgxx_spux_control1_cnf95xxp2 { + u64 reserved_0_1 : 2; + u64 spd : 4; + u64 spdsel0 : 1; + u64 reserved_7_10 : 4; + u64 lo_pwr : 1; + u64 reserved_12 : 1; + u64 spdsel1 : 1; + u64 loopbck : 1; + u64 reset : 1; + u64 usxgmii_type : 3; + u64 usxgmii_rate : 3; + u64 reserved_22 : 1; + u64 reserved_23_63 : 41; + } cnf95xxp2; +}; + +static inline u64 CGXX_SPUX_CONTROL1(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_CONTROL1(u64 a) +{ + return 0x10000 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_control2 + * + * CGX SPU Control 2 Registers + */ +union cgxx_spux_control2 { + u64 u; + struct cgxx_spux_control2_s { + u64 pcs_type : 4; + u64 reserved_4_63 : 60; + } s; + /* struct cgxx_spux_control2_s cn; */ +}; + +static inline u64 CGXX_SPUX_CONTROL2(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_CONTROL2(u64 a) +{ + return 0x10018 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_fec_abil + * + * CGX SPU Forward Error Correction Ability Registers + */ +union cgxx_spux_fec_abil { + u64 u; + struct cgxx_spux_fec_abil_s { + u64 fec_abil : 1; + u64 err_abil : 1; + u64 reserved_2_63 : 62; + } s; + /* struct cgxx_spux_fec_abil_s cn; */ +}; + +static inline u64 CGXX_SPUX_FEC_ABIL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_FEC_ABIL(u64 a) +{ + return 0x100d8 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_fec_control + * + * CGX SPU Forward Error Correction Control Registers + */ +union cgxx_spux_fec_control { + u64 u; + struct cgxx_spux_fec_control_s { + u64 fec_en : 2; + u64 err_en : 1; + u64 fec_byp_ind_en : 1; + u64 fec_byp_cor_en : 1; + u64 reserved_5_63 : 59; + } s; + /* struct cgxx_spux_fec_control_s cn; */ +}; + +static inline u64 CGXX_SPUX_FEC_CONTROL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_FEC_CONTROL(u64 a) +{ + return 0x100e0 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_fec_ln#_rsfec_err + * + * CGX SPU Reed-Solomon FEC Symbol Error Counter for FEC Lanes 0-3 + * Registers This register is valid only when Reed-Solomon FEC is + * enabled. The symbol error counters are defined in 802.3 section + * 91.6.11 (for 100G and extended to 50G) and 802.3by-2016 section + * 108.6.9 (for 25G and extended to USXGMII). The counter is reset to all + * zeros when the register is read, and held at all ones in case of + * overflow. The reset operation takes precedence over the increment + * operation; if the register is read on the same clock cycle as an + * increment operation, the counter is reset to all zeros and the + * increment operation is lost. The counters are writable for test + * purposes, rather than read-only as specified in IEEE 802.3. + */ +union cgxx_spux_fec_lnx_rsfec_err { + u64 u; + struct cgxx_spux_fec_lnx_rsfec_err_s { + u64 symb_err_cnt : 32; + u64 reserved_32_63 : 32; + } s; + /* struct cgxx_spux_fec_lnx_rsfec_err_s cn; */ +}; + +static inline u64 CGXX_SPUX_FEC_LNX_RSFEC_ERR(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_FEC_LNX_RSFEC_ERR(u64 a, u64 b) +{ + return 0x10900 + 0x40000 * a + 8 * b; +} + +/** + * Register (RSL) cgx#_spu#_int + * + * CGX SPU Interrupt Registers + */ +union cgxx_spux_int { + u64 u; + struct cgxx_spux_int_s { + u64 rx_link_up : 1; + u64 rx_link_down : 1; + u64 err_blk : 1; + u64 bitlckls : 1; + u64 synlos : 1; + u64 algnlos : 1; + u64 dbg_sync : 1; + u64 bip_err : 1; + u64 fec_corr : 1; + u64 fec_uncorr : 1; + u64 an_page_rx : 1; + u64 an_link_good : 1; + u64 an_complete : 1; + u64 training_done : 1; + u64 training_failure : 1; + u64 fec_align_status : 1; + u64 rsfec_corr : 1; + u64 rsfec_uncorr : 1; + u64 hi_ser : 1; + u64 usx_an_lnk_st : 1; + u64 usx_an_cpt : 1; + u64 reserved_21_63 : 43; + } s; + /* struct cgxx_spux_int_s cn; */ +}; + +static inline u64 CGXX_SPUX_INT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_INT(u64 a) +{ + return 0x10220 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_int_ena_w1c + * + * CGX SPU Interrupt Enable Clear Registers This register clears + * interrupt enable bits. + */ +union cgxx_spux_int_ena_w1c { + u64 u; + struct cgxx_spux_int_ena_w1c_s { + u64 rx_link_up : 1; + u64 rx_link_down : 1; + u64 err_blk : 1; + u64 bitlckls : 1; + u64 synlos : 1; + u64 algnlos : 1; + u64 dbg_sync : 1; + u64 bip_err : 1; + u64 fec_corr : 1; + u64 fec_uncorr : 1; + u64 an_page_rx : 1; + u64 an_link_good : 1; + u64 an_complete : 1; + u64 training_done : 1; + u64 training_failure : 1; + u64 fec_align_status : 1; + u64 rsfec_corr : 1; + u64 rsfec_uncorr : 1; + u64 hi_ser : 1; + u64 usx_an_lnk_st : 1; + u64 usx_an_cpt : 1; + u64 reserved_21_63 : 43; + } s; + /* struct cgxx_spux_int_ena_w1c_s cn; */ +}; + +static inline u64 CGXX_SPUX_INT_ENA_W1C(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_INT_ENA_W1C(u64 a) +{ + return 0x10230 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_int_ena_w1s + * + * CGX SPU Interrupt Enable Set Registers This register sets interrupt + * enable bits. + */ +union cgxx_spux_int_ena_w1s { + u64 u; + struct cgxx_spux_int_ena_w1s_s { + u64 rx_link_up : 1; + u64 rx_link_down : 1; + u64 err_blk : 1; + u64 bitlckls : 1; + u64 synlos : 1; + u64 algnlos : 1; + u64 dbg_sync : 1; + u64 bip_err : 1; + u64 fec_corr : 1; + u64 fec_uncorr : 1; + u64 an_page_rx : 1; + u64 an_link_good : 1; + u64 an_complete : 1; + u64 training_done : 1; + u64 training_failure : 1; + u64 fec_align_status : 1; + u64 rsfec_corr : 1; + u64 rsfec_uncorr : 1; + u64 hi_ser : 1; + u64 usx_an_lnk_st : 1; + u64 usx_an_cpt : 1; + u64 reserved_21_63 : 43; + } s; + /* struct cgxx_spux_int_ena_w1s_s cn; */ +}; + +static inline u64 CGXX_SPUX_INT_ENA_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_INT_ENA_W1S(u64 a) +{ + return 0x10238 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_int_w1s + * + * CGX SPU Interrupt Set Registers This register sets interrupt bits. + */ +union cgxx_spux_int_w1s { + u64 u; + struct cgxx_spux_int_w1s_s { + u64 rx_link_up : 1; + u64 rx_link_down : 1; + u64 err_blk : 1; + u64 bitlckls : 1; + u64 synlos : 1; + u64 algnlos : 1; + u64 dbg_sync : 1; + u64 bip_err : 1; + u64 fec_corr : 1; + u64 fec_uncorr : 1; + u64 an_page_rx : 1; + u64 an_link_good : 1; + u64 an_complete : 1; + u64 training_done : 1; + u64 training_failure : 1; + u64 fec_align_status : 1; + u64 rsfec_corr : 1; + u64 rsfec_uncorr : 1; + u64 hi_ser : 1; + u64 usx_an_lnk_st : 1; + u64 usx_an_cpt : 1; + u64 reserved_21_63 : 43; + } s; + /* struct cgxx_spux_int_w1s_s cn; */ +}; + +static inline u64 CGXX_SPUX_INT_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_INT_W1S(u64 a) +{ + return 0x10228 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_ln#_br_bip_err_cnt + * + * CGX SPU 40,50,100GBASE-R BIP Error-Counter Registers This register + * implements the IEEE 802.3 BIP error-counter registers for PCS lanes + * 0-19 (3.200-3.203). It is valid only when the LPCS type is 40GBASE-R, + * 50GBASE-R, 100GBASE-R, (CGX()_CMR()_CONFIG[LMAC_TYPE]), and always + * returns 0x0 for all other LPCS types. The counters are indexed by the + * RX PCS lane number based on the alignment marker detected on each lane + * and captured in CGX()_SPU()_BR_LANE_MAP(). Each counter counts the BIP + * errors for its PCS lane, and is held at all ones in case of overflow. + * The counters are reset to all zeros when this register is read by + * software. The reset operation takes precedence over the increment + * operation; if the register is read on the same clock cycle as an + * increment operation, the counter is reset to all zeros and the + * increment operation is lost. The counters are writable for test + * purposes, rather than read-only as specified in IEEE 802.3. + */ +union cgxx_spux_lnx_br_bip_err_cnt { + u64 u; + struct cgxx_spux_lnx_br_bip_err_cnt_s { + u64 bip_err_cnt : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_spux_lnx_br_bip_err_cnt_s cn; */ +}; + +static inline u64 CGXX_SPUX_LNX_BR_BIP_ERR_CNT(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_LNX_BR_BIP_ERR_CNT(u64 a, u64 b) +{ + return 0x10500 + 0x40000 * a + 8 * b; +} + +/** + * Register (RSL) cgx#_spu#_ln#_fec_corr_blks + * + * CGX SPU FEC Corrected-Blocks Counters 0-19 Registers This register is + * valid only when the LPCS type is BASE-R + * (CGX()_CMR()_CONFIG[LMAC_TYPE]) and applies to BASE-R FEC and Reed- + * Solomon FEC (RS-FEC). When BASE-R FEC is enabled, the FEC corrected- + * block counters are defined in IEEE 802.3 section 74.8.4.1. Each + * corrected-blocks counter increments by one for a corrected FEC block, + * i.e. an FEC block that has been received with invalid parity on the + * associated PCS lane and has been corrected by the FEC decoder. The + * counter is reset to all zeros when the register is read, and held at + * all ones in case of overflow. The reset operation takes precedence + * over the increment operation; if the register is read on the same + * clock cycle as an increment operation, the counter is reset to all + * zeros and the increment operation is lost. The counters are writable + * for test purposes, rather than read-only as specified in IEEE 802.3. + */ +union cgxx_spux_lnx_fec_corr_blks { + u64 u; + struct cgxx_spux_lnx_fec_corr_blks_s { + u64 ln_corr_blks : 32; + u64 reserved_32_63 : 32; + } s; + /* struct cgxx_spux_lnx_fec_corr_blks_s cn; */ +}; + +static inline u64 CGXX_SPUX_LNX_FEC_CORR_BLKS(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_LNX_FEC_CORR_BLKS(u64 a, u64 b) +{ + return 0x10700 + 0x40000 * a + 8 * b; +} + +/** + * Register (RSL) cgx#_spu#_ln#_fec_uncorr_blks + * + * CGX SPU FEC Uncorrected-Blocks Counters 0-19 Registers This register + * is valid only when the LPCS type is BASE-R + * (CGX()_CMR()_CONFIG[LMAC_TYPE]) and applies to BASE-R FEC and Reed- + * Solomon FEC (RS-FEC). When BASE-R FEC is enabled, the FEC corrected- + * block counters are defined in IEEE 802.3 section 74.8.4.2. Each + * uncorrected-blocks counter increments by one for an uncorrected FEC + * block, i.e. an FEC block that has been received with invalid parity on + * the associated PCS lane and has not been corrected by the FEC decoder. + * The counter is reset to all zeros when the register is read, and held + * at all ones in case of overflow. The reset operation takes precedence + * over the increment operation; if the register is read on the same + * clock cycle as an increment operation, the counter is reset to all + * zeros and the increment operation is lost. The counters are writable + * for test purposes, rather than read-only as specified in IEEE 802.3. + */ +union cgxx_spux_lnx_fec_uncorr_blks { + u64 u; + struct cgxx_spux_lnx_fec_uncorr_blks_s { + u64 ln_uncorr_blks : 32; + u64 reserved_32_63 : 32; + } s; + /* struct cgxx_spux_lnx_fec_uncorr_blks_s cn; */ +}; + +static inline u64 CGXX_SPUX_LNX_FEC_UNCORR_BLKS(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_LNX_FEC_UNCORR_BLKS(u64 a, u64 b) +{ + return 0x10800 + 0x40000 * a + 8 * b; +} + +/** + * Register (RSL) cgx#_spu#_lpcs_states + * + * CGX SPU BASE-X Transmit/Receive States Registers + */ +union cgxx_spux_lpcs_states { + u64 u; + struct cgxx_spux_lpcs_states_s { + u64 deskew_sm : 3; + u64 reserved_3 : 1; + u64 deskew_am_found : 20; + u64 bx_rx_sm : 2; + u64 reserved_26_27 : 2; + u64 br_rx_sm : 3; + u64 reserved_31_63 : 33; + } s; + /* struct cgxx_spux_lpcs_states_s cn; */ +}; + +static inline u64 CGXX_SPUX_LPCS_STATES(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_LPCS_STATES(u64 a) +{ + return 0x10208 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_misc_control + * + * CGX SPU Miscellaneous Control Registers "* RX logical PCS lane + * polarity vector \<3:0\> = [XOR_RXPLRT]\<3:0\> ^ {4{[RXPLRT]}}. * TX + * logical PCS lane polarity vector \<3:0\> = [XOR_TXPLRT]\<3:0\> ^ + * {4{[TXPLRT]}}. In short, keep [RXPLRT] and [TXPLRT] cleared, and use + * [XOR_RXPLRT] and [XOR_TXPLRT] fields to define the polarity per + * logical PCS lane. Only bit 0 of vector is used for 10GBASE-R, and only + * bits 1:0 of vector are used for RXAUI." + */ +union cgxx_spux_misc_control { + u64 u; + struct cgxx_spux_misc_control_s { + u64 txplrt : 1; + u64 rxplrt : 1; + u64 xor_txplrt : 4; + u64 xor_rxplrt : 4; + u64 intlv_rdisp : 1; + u64 skip_after_term : 1; + u64 rx_packet_dis : 1; + u64 rx_edet_signal_ok : 1; + u64 reserved_14_63 : 50; + } s; + /* struct cgxx_spux_misc_control_s cn; */ +}; + +static inline u64 CGXX_SPUX_MISC_CONTROL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_MISC_CONTROL(u64 a) +{ + return 0x10218 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_rsfec_corr + * + * CGX SPU Reed-Solomon FEC Corrected Codeword Counter Register This + * register implements the IEEE 802.3 RS-FEC corrected codewords counter + * described in 802.3 section 91.6.8 (for 100G and extended to 50G) and + * 802.3by-2016 section 108.6.7 (for 25G and extended to USXGMII). + */ +union cgxx_spux_rsfec_corr { + u64 u; + struct cgxx_spux_rsfec_corr_s { + u64 cw_cnt : 32; + u64 reserved_32_63 : 32; + } s; + /* struct cgxx_spux_rsfec_corr_s cn; */ +}; + +static inline u64 CGXX_SPUX_RSFEC_CORR(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_RSFEC_CORR(u64 a) +{ + return 0x10088 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_rsfec_status + * + * CGX SPU Reed-Solomon FEC Status Registers This register implements the + * IEEE 802.3 RS-FEC status and lane mapping registers as described in + * 802.3 section 91.6 (for 100G and extended to 50G) and 802.3by-2016 + * section 108-6 (for 25G and extended to USXGMII). + */ +union cgxx_spux_rsfec_status { + u64 u; + struct cgxx_spux_rsfec_status_s { + u64 fec_lane_mapping : 8; + u64 fec_align_status : 1; + u64 amps_lock : 4; + u64 hi_ser : 1; + u64 fec_byp_ind_abil : 1; + u64 fec_byp_cor_abil : 1; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_spux_rsfec_status_s cn; */ +}; + +static inline u64 CGXX_SPUX_RSFEC_STATUS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_RSFEC_STATUS(u64 a) +{ + return 0x10080 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_rsfec_uncorr + * + * CGX SPU Reed-Solomon FEC Uncorrected Codeword Counter Register This + * register implements the IEEE 802.3 RS-FEC uncorrected codewords + * counter described in 802.3 section 91.6.9 (for 100G and extended to + * 50G) and 802.3by-2016 section 108.6.8 (for 25G and extended to + * USXGMII). + */ +union cgxx_spux_rsfec_uncorr { + u64 u; + struct cgxx_spux_rsfec_uncorr_s { + u64 cw_cnt : 32; + u64 reserved_32_63 : 32; + } s; + /* struct cgxx_spux_rsfec_uncorr_s cn; */ +}; + +static inline u64 CGXX_SPUX_RSFEC_UNCORR(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_RSFEC_UNCORR(u64 a) +{ + return 0x10090 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_rx_eee_wake + * + * INTERNAL: CGX SPU RX EEE Wake Error Counter Registers Reserved. + * Internal: A counter that is incremented each time that the LPI receive + * state diagram enters the RX_WTF state indicating that a wake time + * fault has been detected. + */ +union cgxx_spux_rx_eee_wake { + u64 u; + struct cgxx_spux_rx_eee_wake_s { + u64 wtf_error_counter : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_spux_rx_eee_wake_s cn; */ +}; + +static inline u64 CGXX_SPUX_RX_EEE_WAKE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_RX_EEE_WAKE(u64 a) +{ + return 0x103e0 + 8 * a; +} + +/** + * Register (RSL) cgx#_spu#_rx_lpi_timing + * + * INTERNAL: CGX SPU RX EEE LPI Timing Parameters Registers Reserved. + * Internal: This register specifies receiver LPI timing parameters Tqr, + * Twr and Twtf. + */ +union cgxx_spux_rx_lpi_timing { + u64 u; + struct cgxx_spux_rx_lpi_timing_s { + u64 twtf : 20; + u64 twr : 20; + u64 tqr : 20; + u64 reserved_60_61 : 2; + u64 rx_lpi_fw : 1; + u64 rx_lpi_en : 1; + } s; + /* struct cgxx_spux_rx_lpi_timing_s cn; */ +}; + +static inline u64 CGXX_SPUX_RX_LPI_TIMING(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_RX_LPI_TIMING(u64 a) +{ + return 0x103c0 + 8 * a; +} + +/** + * Register (RSL) cgx#_spu#_rx_lpi_timing2 + * + * INTERNAL: CGX SPU RX EEE LPI Timing2 Parameters Registers Reserved. + * Internal: This register specifies receiver LPI timing parameters + * hold_off_timer. + */ +union cgxx_spux_rx_lpi_timing2 { + u64 u; + struct cgxx_spux_rx_lpi_timing2_s { + u64 hold_off_timer : 20; + u64 reserved_20_63 : 44; + } s; + /* struct cgxx_spux_rx_lpi_timing2_s cn; */ +}; + +static inline u64 CGXX_SPUX_RX_LPI_TIMING2(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_RX_LPI_TIMING2(u64 a) +{ + return 0x10420 + 8 * a; +} + +/** + * Register (RSL) cgx#_spu#_rx_mrk_cnt + * + * CGX SPU Receiver Marker Interval Count Control Registers + */ +union cgxx_spux_rx_mrk_cnt { + u64 u; + struct cgxx_spux_rx_mrk_cnt_s { + u64 mrk_cnt : 20; + u64 reserved_20_43 : 24; + u64 by_mrk_100g : 1; + u64 reserved_45_47 : 3; + u64 ram_mrk_cnt : 8; + u64 reserved_56_63 : 8; + } s; + /* struct cgxx_spux_rx_mrk_cnt_s cn; */ +}; + +static inline u64 CGXX_SPUX_RX_MRK_CNT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_RX_MRK_CNT(u64 a) +{ + return 0x103a0 + 8 * a; +} + +/** + * Register (RSL) cgx#_spu#_spd_abil + * + * CGX SPU PCS Speed Ability Registers + */ +union cgxx_spux_spd_abil { + u64 u; + struct cgxx_spux_spd_abil_s { + u64 tengb : 1; + u64 tenpasst : 1; + u64 usxgmii : 1; + u64 twentyfivegb : 1; + u64 fortygb : 1; + u64 fiftygb : 1; + u64 hundredgb : 1; + u64 reserved_7_63 : 57; + } s; + /* struct cgxx_spux_spd_abil_s cn; */ +}; + +static inline u64 CGXX_SPUX_SPD_ABIL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_SPD_ABIL(u64 a) +{ + return 0x10010 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_status1 + * + * CGX SPU Status 1 Registers + */ +union cgxx_spux_status1 { + u64 u; + struct cgxx_spux_status1_s { + u64 reserved_0 : 1; + u64 lpable : 1; + u64 rcv_lnk : 1; + u64 reserved_3_6 : 4; + u64 flt : 1; + u64 rx_lpi_indication : 1; + u64 tx_lpi_indication : 1; + u64 rx_lpi_received : 1; + u64 tx_lpi_received : 1; + u64 reserved_12_63 : 52; + } s; + /* struct cgxx_spux_status1_s cn; */ +}; + +static inline u64 CGXX_SPUX_STATUS1(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_STATUS1(u64 a) +{ + return 0x10008 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_status2 + * + * CGX SPU Status 2 Registers + */ +union cgxx_spux_status2 { + u64 u; + struct cgxx_spux_status2_s { + u64 tengb_r : 1; + u64 tengb_x : 1; + u64 tengb_w : 1; + u64 tengb_t : 1; + u64 usxgmii_r : 1; + u64 twentyfivegb_r : 1; + u64 fortygb_r : 1; + u64 fiftygb_r : 1; + u64 hundredgb_r : 1; + u64 reserved_9 : 1; + u64 rcvflt : 1; + u64 xmtflt : 1; + u64 reserved_12_13 : 2; + u64 dev : 2; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_spux_status2_s cn; */ +}; + +static inline u64 CGXX_SPUX_STATUS2(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_STATUS2(u64 a) +{ + return 0x10020 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_tx_lpi_timing + * + * INTERNAL: CGX SPU TX EEE LPI Timing Parameters Registers Reserved. + * Internal: Transmit LPI timing parameters Tsl, Tql and Tul + */ +union cgxx_spux_tx_lpi_timing { + u64 u; + struct cgxx_spux_tx_lpi_timing_s { + u64 tql : 19; + u64 reserved_19_31 : 13; + u64 tul : 12; + u64 reserved_44_47 : 4; + u64 tsl : 12; + u64 reserved_60 : 1; + u64 tx_lpi_ignore_twl : 1; + u64 tx_lpi_fw : 1; + u64 tx_lpi_en : 1; + } s; + /* struct cgxx_spux_tx_lpi_timing_s cn; */ +}; + +static inline u64 CGXX_SPUX_TX_LPI_TIMING(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_TX_LPI_TIMING(u64 a) +{ + return 0x10400 + 8 * a; +} + +/** + * Register (RSL) cgx#_spu#_tx_lpi_timing2 + * + * INTERNAL: CGX SPU TX EEE LPI Timing2 Parameters Registers Reserved. + * Internal: This register specifies transmit LPI timer parameters. + */ +union cgxx_spux_tx_lpi_timing2 { + u64 u; + struct cgxx_spux_tx_lpi_timing2_s { + u64 t1u : 8; + u64 reserved_8_11 : 4; + u64 twl : 12; + u64 reserved_24_31 : 8; + u64 twl2 : 12; + u64 reserved_44_47 : 4; + u64 tbyp : 12; + u64 reserved_60_63 : 4; + } s; + /* struct cgxx_spux_tx_lpi_timing2_s cn; */ +}; + +static inline u64 CGXX_SPUX_TX_LPI_TIMING2(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_TX_LPI_TIMING2(u64 a) +{ + return 0x10440 + 8 * a; +} + +/** + * Register (RSL) cgx#_spu#_tx_mrk_cnt + * + * CGX SPU Transmitter Marker Interval Count Control Registers + */ +union cgxx_spux_tx_mrk_cnt { + u64 u; + struct cgxx_spux_tx_mrk_cnt_s { + u64 mrk_cnt : 20; + u64 reserved_20_43 : 24; + u64 by_mrk_100g : 1; + u64 reserved_45_47 : 3; + u64 ram_mrk_cnt : 8; + u64 reserved_56_63 : 8; + } s; + /* struct cgxx_spux_tx_mrk_cnt_s cn; */ +}; + +static inline u64 CGXX_SPUX_TX_MRK_CNT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_TX_MRK_CNT(u64 a) +{ + return 0x10380 + 8 * a; +} + +/** + * Register (RSL) cgx#_spu#_usx_an_adv + * + * CGX SPU USXGMII Autonegotiation Advertisement Registers Software + * programs this register with the contents of the AN-link code word base + * page to be transmitted during autonegotiation. Any write operations to + * this register prior to completion of autonegotiation should be + * followed by a renegotiation in order for the new values to take + * effect. Once autonegotiation has completed, software can examine this + * register along with CGX()_SPU()_USX_AN_ADV to determine the highest + * common denominator technology. The format for this register is from + * USXGMII Multiport specification section 1.1.2 Table 2. + */ +union cgxx_spux_usx_an_adv { + u64 u; + struct cgxx_spux_usx_an_adv_s { + u64 set : 1; + u64 reserved_1_6 : 6; + u64 eee_clk_stop_abil : 1; + u64 eee_abil : 1; + u64 spd : 3; + u64 dplx : 1; + u64 reserved_13_14 : 2; + u64 lnk_st : 1; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_spux_usx_an_adv_s cn; */ +}; + +static inline u64 CGXX_SPUX_USX_AN_ADV(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_USX_AN_ADV(u64 a) +{ + return 0x101d0 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_usx_an_control + * + * CGX SPU USXGMII Autonegotiation Control Register + */ +union cgxx_spux_usx_an_control { + u64 u; + struct cgxx_spux_usx_an_control_s { + u64 reserved_0_8 : 9; + u64 rst_an : 1; + u64 reserved_10_11 : 2; + u64 an_en : 1; + u64 reserved_13_14 : 2; + u64 an_reset : 1; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_spux_usx_an_control_s cn; */ +}; + +static inline u64 CGXX_SPUX_USX_AN_CONTROL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_USX_AN_CONTROL(u64 a) +{ + return 0x101c0 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_usx_an_expansion + * + * CGX SPU USXGMII Autonegotiation Expansion Register This register is + * only used to signal page reception. + */ +union cgxx_spux_usx_an_expansion { + u64 u; + struct cgxx_spux_usx_an_expansion_s { + u64 reserved_0 : 1; + u64 an_page_received : 1; + u64 next_page_able : 1; + u64 reserved_3_63 : 61; + } s; + /* struct cgxx_spux_usx_an_expansion_s cn; */ +}; + +static inline u64 CGXX_SPUX_USX_AN_EXPANSION(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_USX_AN_EXPANSION(u64 a) +{ + return 0x101e0 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_usx_an_flow_ctrl + * + * CGX SPU USXGMII Flow Control Registers This register is used by + * software to affect USXGMII AN hardware behavior. + */ +union cgxx_spux_usx_an_flow_ctrl { + u64 u; + struct cgxx_spux_usx_an_flow_ctrl_s { + u64 start_idle_detect : 1; + u64 reserved_1_63 : 63; + } s; + /* struct cgxx_spux_usx_an_flow_ctrl_s cn; */ +}; + +static inline u64 CGXX_SPUX_USX_AN_FLOW_CTRL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_USX_AN_FLOW_CTRL(u64 a) +{ + return 0x101e8 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_usx_an_link_timer + * + * CGX SPU USXGMII Link Timer Registers This is the link timer register. + */ +union cgxx_spux_usx_an_link_timer { + u64 u; + struct cgxx_spux_usx_an_link_timer_s { + u64 count : 16; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_spux_usx_an_link_timer_s cn; */ +}; + +static inline u64 CGXX_SPUX_USX_AN_LINK_TIMER(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_USX_AN_LINK_TIMER(u64 a) +{ + return 0x101f0 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_usx_an_lp_abil + * + * CGX SPU USXGMII Autonegotiation Link-Partner Advertisement Registers + * This register captures the contents of the latest AN link code word + * base page received from the link partner during autonegotiation. This + * is register 5 per IEEE 802.3, Clause 37. + * CGX()_SPU()_USX_AN_EXPANSION[AN_PAGE_RECEIVED] is set when this + * register is updated by hardware. + */ +union cgxx_spux_usx_an_lp_abil { + u64 u; + struct cgxx_spux_usx_an_lp_abil_s { + u64 set : 1; + u64 reserved_1_6 : 6; + u64 eee_clk_stop_abil : 1; + u64 eee_abil : 1; + u64 spd : 3; + u64 dplx : 1; + u64 reserved_13_14 : 2; + u64 lnk_st : 1; + u64 reserved_16_63 : 48; + } s; + /* struct cgxx_spux_usx_an_lp_abil_s cn; */ +}; + +static inline u64 CGXX_SPUX_USX_AN_LP_ABIL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_USX_AN_LP_ABIL(u64 a) +{ + return 0x101d8 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu#_usx_an_status + * + * CGX SPU USXGMII Autonegotiation Status Register + */ +union cgxx_spux_usx_an_status { + u64 u; + struct cgxx_spux_usx_an_status_s { + u64 extnd : 1; + u64 reserved_1 : 1; + u64 lnk_st : 1; + u64 an_abil : 1; + u64 rmt_flt : 1; + u64 an_cpt : 1; + u64 reserved_6_63 : 58; + } s; + /* struct cgxx_spux_usx_an_status_s cn; */ +}; + +static inline u64 CGXX_SPUX_USX_AN_STATUS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPUX_USX_AN_STATUS(u64 a) +{ + return 0x101c8 + 0x40000 * a; +} + +/** + * Register (RSL) cgx#_spu_dbg_control + * + * CGX SPU Debug Control Registers + */ +union cgxx_spu_dbg_control { + u64 u; + struct cgxx_spu_dbg_control_s { + u64 marker_rxp : 15; + u64 reserved_15 : 1; + u64 scramble_dis : 1; + u64 reserved_17_18 : 2; + u64 br_pmd_train_soft_en : 1; + u64 reserved_20_27 : 8; + u64 timestamp_norm_dis : 1; + u64 an_nonce_match_dis : 1; + u64 br_ber_mon_dis : 1; + u64 rf_cw_mon_erly_restart_dis : 1; + u64 us_clk_period : 12; + u64 ms_clk_period : 12; + u64 reserved_56_63 : 8; + } s; + struct cgxx_spu_dbg_control_cn96xxp1 { + u64 marker_rxp : 15; + u64 reserved_15 : 1; + u64 scramble_dis : 1; + u64 reserved_17_18 : 2; + u64 br_pmd_train_soft_en : 1; + u64 reserved_20_27 : 8; + u64 timestamp_norm_dis : 1; + u64 an_nonce_match_dis : 1; + u64 br_ber_mon_dis : 1; + u64 reserved_31 : 1; + u64 us_clk_period : 12; + u64 ms_clk_period : 12; + u64 reserved_56_63 : 8; + } cn96xxp1; + /* struct cgxx_spu_dbg_control_s cn96xxp3; */ + /* struct cgxx_spu_dbg_control_cn96xxp1 cnf95xxp1; */ + /* struct cgxx_spu_dbg_control_s cnf95xxp2; */ +}; + +static inline u64 CGXX_SPU_DBG_CONTROL(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPU_DBG_CONTROL(void) +{ + return 0x10300; +} + +/** + * Register (RSL) cgx#_spu_sds#_skew_status + * + * CGX SPU SerDes Lane Skew Status Registers This register provides + * SerDes lane skew status. One register per physical SerDes lane. + */ +union cgxx_spu_sdsx_skew_status { + u64 u; + struct cgxx_spu_sdsx_skew_status_s { + u64 skew_status : 32; + u64 reserved_32_63 : 32; + } s; + /* struct cgxx_spu_sdsx_skew_status_s cn; */ +}; + +static inline u64 CGXX_SPU_SDSX_SKEW_STATUS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPU_SDSX_SKEW_STATUS(u64 a) +{ + return 0x10340 + 8 * a; +} + +/** + * Register (RSL) cgx#_spu_sds#_states + * + * CGX SPU SerDes States Registers This register provides SerDes lane + * states. One register per physical SerDes lane. + */ +union cgxx_spu_sdsx_states { + u64 u; + struct cgxx_spu_sdsx_states_s { + u64 bx_sync_sm : 4; + u64 br_sh_cnt : 11; + u64 br_block_lock : 1; + u64 br_sh_invld_cnt : 7; + u64 reserved_23 : 1; + u64 fec_sync_cnt : 4; + u64 fec_block_sync : 1; + u64 reserved_29 : 1; + u64 an_rx_sm : 2; + u64 an_arb_sm : 3; + u64 reserved_35 : 1; + u64 train_lock_bad_markers : 3; + u64 train_lock_found_1st_marker : 1; + u64 train_frame_lock : 1; + u64 train_code_viol : 1; + u64 train_sm : 3; + u64 reserved_45_47 : 3; + u64 am_lock_sm : 2; + u64 am_lock_invld_cnt : 2; + u64 reserved_52_63 : 12; + } s; + /* struct cgxx_spu_sdsx_states_s cn; */ +}; + +static inline u64 CGXX_SPU_SDSX_STATES(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPU_SDSX_STATES(u64 a) +{ + return 0x10360 + 8 * a; +} + +/** + * Register (RSL) cgx#_spu_usxgmii_control + * + * CGX SPU Common USXGMII Control Register This register is the common + * control register that enables USXGMII Mode. The fields in this + * register are preserved across any LMAC soft-resets. For an LMAC in + * soft- reset state in USXGMII mode, the CGX will transmit Remote Fault + * BASE-R blocks. + */ +union cgxx_spu_usxgmii_control { + u64 u; + struct cgxx_spu_usxgmii_control_s { + u64 enable : 1; + u64 usxgmii_type : 3; + u64 sds_id : 2; + u64 reserved_6_63 : 58; + } s; + /* struct cgxx_spu_usxgmii_control_s cn; */ +}; + +static inline u64 CGXX_SPU_USXGMII_CONTROL(void) + __attribute__ ((pure, always_inline)); +static inline u64 CGXX_SPU_USXGMII_CONTROL(void) +{ + return 0x10920; +} + +#endif /* __CSRS_CGX_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-lmt.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-lmt.h new file mode 100644 index 000000000..625470b2d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-lmt.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Marvell International Ltd. + * + * https://spdx.org/licenses + */ +#ifndef __CSRS_LMT_H__ +#define __CSRS_LMT_H__ + +/** + * @file + * + * Configuration and status register (CSR) address and type definitions for + * LMT. + * + * This file is auto generated. Do not edit. + * + */ + +/** + * Register (RVU_PFVF_BAR2) lmt_lf_lmtcancel + * + * RVU VF LMT Cancel Register + */ +union lmt_lf_lmtcancel { + u64 u; + struct lmt_lf_lmtcancel_s { + u64 data : 64; + } s; + /* struct lmt_lf_lmtcancel_s cn; */ +}; + +static inline u64 LMT_LF_LMTCANCEL(void) + __attribute__ ((pure, always_inline)); +static inline u64 LMT_LF_LMTCANCEL(void) +{ + return 0x400; +} + +/** + * Register (RVU_PFVF_BAR2) lmt_lf_lmtline# + * + * RVU VF LMT Line Registers + */ +union lmt_lf_lmtlinex { + u64 u; + struct lmt_lf_lmtlinex_s { + u64 data : 64; + } s; + /* struct lmt_lf_lmtlinex_s cn; */ +}; + +static inline u64 LMT_LF_LMTLINEX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 LMT_LF_LMTLINEX(u64 a) +{ + return 0 + 8 * a; +} + +#endif /* __CSRS_LMT_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-mio_emm.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-mio_emm.h new file mode 100644 index 000000000..a5a474083 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-mio_emm.h @@ -0,0 +1,1193 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Marvell International Ltd. + * + * https://spdx.org/licenses + */ +#ifndef __CSRS_MIO_EMM_H__ +#define __CSRS_MIO_EMM_H__ + +/** + * @file + * + * Configuration and status register (CSR) address and type definitions for + * MIO_EMM. + * + * This file is auto generated. Do not edit. + * + */ + +/** + * Enumeration mio_emm_bar_e + * + * eMMC Base Address Register Enumeration Enumerates the base address + * registers. + */ +#define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN8 (0x87e009000000ll) +#define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN8_SIZE 0x800000ull +#define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN9 (0x87e009000000ll) +#define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN9_SIZE 0x10000ull +#define MIO_EMM_BAR_E_MIO_EMM_PF_BAR4 (0x87e009f00000ll) +#define MIO_EMM_BAR_E_MIO_EMM_PF_BAR4_SIZE 0x100000ull + +/** + * Enumeration mio_emm_int_vec_e + * + * eMMC MSI-X Vector Enumeration Enumerates the MSI-X interrupt vectors. + */ +#define MIO_EMM_INT_VEC_E_DMA_INT_DONE (8) +#define MIO_EMM_INT_VEC_E_DMA_INT_FIFO (7) +#define MIO_EMM_INT_VEC_E_EMM_BUF_DONE (0) +#define MIO_EMM_INT_VEC_E_EMM_CMD_DONE (1) +#define MIO_EMM_INT_VEC_E_EMM_CMD_ERR (3) +#define MIO_EMM_INT_VEC_E_EMM_DMA_DONE (2) +#define MIO_EMM_INT_VEC_E_EMM_DMA_ERR (4) +#define MIO_EMM_INT_VEC_E_EMM_SWITCH_DONE (5) +#define MIO_EMM_INT_VEC_E_EMM_SWITCH_ERR (6) +#define MIO_EMM_INT_VEC_E_NCB_FLT (9) +#define MIO_EMM_INT_VEC_E_NCB_RAS (0xa) + +/** + * Register (RSL) mio_emm_access_wdog + * + * eMMC Access Watchdog Register + */ +union mio_emm_access_wdog { + u64 u; + struct mio_emm_access_wdog_s { + u64 clk_cnt : 32; + u64 reserved_32_63 : 32; + } s; + /* struct mio_emm_access_wdog_s cn; */ +}; + +static inline u64 MIO_EMM_ACCESS_WDOG(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_ACCESS_WDOG(void) +{ + return 0x20f0; +} + +/** + * Register (RSL) mio_emm_buf_dat + * + * eMMC Data Buffer Access Register + */ +union mio_emm_buf_dat { + u64 u; + struct mio_emm_buf_dat_s { + u64 dat : 64; + } s; + /* struct mio_emm_buf_dat_s cn; */ +}; + +static inline u64 MIO_EMM_BUF_DAT(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_BUF_DAT(void) +{ + return 0x20e8; +} + +/** + * Register (RSL) mio_emm_buf_idx + * + * eMMC Data Buffer Address Register + */ +union mio_emm_buf_idx { + u64 u; + struct mio_emm_buf_idx_s { + u64 offset : 6; + u64 buf_num : 1; + u64 reserved_7_15 : 9; + u64 inc : 1; + u64 reserved_17_63 : 47; + } s; + /* struct mio_emm_buf_idx_s cn; */ +}; + +static inline u64 MIO_EMM_BUF_IDX(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_BUF_IDX(void) +{ + return 0x20e0; +} + +/** + * Register (RSL) mio_emm_calb + * + * eMMC Calbration Register This register initiates delay line + * characterization. + */ +union mio_emm_calb { + u64 u; + struct mio_emm_calb_s { + u64 start : 1; + u64 reserved_1_63 : 63; + } s; + /* struct mio_emm_calb_s cn; */ +}; + +static inline u64 MIO_EMM_CALB(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_CALB(void) +{ + return 0x20c0; +} + +/** + * Register (RSL) mio_emm_cfg + * + * eMMC Configuration Register + */ +union mio_emm_cfg { + u64 u; + struct mio_emm_cfg_s { + u64 bus_ena : 4; + u64 reserved_4_63 : 60; + } s; + /* struct mio_emm_cfg_s cn; */ +}; + +static inline u64 MIO_EMM_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_CFG(void) +{ + return 0x2000; +} + +/** + * Register (RSL) mio_emm_cmd + * + * eMMC Command Register + */ +union mio_emm_cmd { + u64 u; + struct mio_emm_cmd_s { + u64 arg : 32; + u64 cmd_idx : 6; + u64 rtype_xor : 3; + u64 ctype_xor : 2; + u64 reserved_43_48 : 6; + u64 offset : 6; + u64 dbuf : 1; + u64 reserved_56_58 : 3; + u64 cmd_val : 1; + u64 bus_id : 2; + u64 skip_busy : 1; + u64 reserved_63 : 1; + } s; + /* struct mio_emm_cmd_s cn; */ +}; + +static inline u64 MIO_EMM_CMD(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_CMD(void) +{ + return 0x2058; +} + +/** + * Register (RSL) mio_emm_comp + * + * eMMC Compensation Register + */ +union mio_emm_comp { + u64 u; + struct mio_emm_comp_s { + u64 nctl : 3; + u64 reserved_3_7 : 5; + u64 pctl : 3; + u64 reserved_11_63 : 53; + } s; + /* struct mio_emm_comp_s cn; */ +}; + +static inline u64 MIO_EMM_COMP(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_COMP(void) +{ + return 0x2040; +} + +/** + * Register (RSL) mio_emm_debug + * + * eMMC Debug Register + */ +union mio_emm_debug { + u64 u; + struct mio_emm_debug_s { + u64 clk_on : 1; + u64 reserved_1_7 : 7; + u64 cmd_sm : 4; + u64 data_sm : 4; + u64 dma_sm : 4; + u64 emmc_clk_disable : 1; + u64 rdsync_rst : 1; + u64 reserved_22_63 : 42; + } s; + struct mio_emm_debug_cn96xxp1 { + u64 clk_on : 1; + u64 reserved_1_7 : 7; + u64 cmd_sm : 4; + u64 data_sm : 4; + u64 dma_sm : 4; + u64 reserved_20_63 : 44; + } cn96xxp1; + /* struct mio_emm_debug_s cn96xxp3; */ + /* struct mio_emm_debug_cn96xxp1 cnf95xx; */ +}; + +static inline u64 MIO_EMM_DEBUG(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DEBUG(void) +{ + return 0x20f8; +} + +/** + * Register (RSL) mio_emm_dma + * + * eMMC External DMA Configuration Register + */ +union mio_emm_dma { + u64 u; + struct mio_emm_dma_s { + u64 card_addr : 32; + u64 block_cnt : 16; + u64 multi : 1; + u64 rw : 1; + u64 rel_wr : 1; + u64 thres : 6; + u64 dat_null : 1; + u64 sector : 1; + u64 dma_val : 1; + u64 bus_id : 2; + u64 skip_busy : 1; + u64 extra_args : 1; + } s; + struct mio_emm_dma_cn8 { + u64 card_addr : 32; + u64 block_cnt : 16; + u64 multi : 1; + u64 rw : 1; + u64 rel_wr : 1; + u64 thres : 6; + u64 dat_null : 1; + u64 sector : 1; + u64 dma_val : 1; + u64 bus_id : 2; + u64 skip_busy : 1; + u64 reserved_63 : 1; + } cn8; + struct mio_emm_dma_cn9 { + u64 card_addr : 32; + u64 block_cnt : 16; + u64 multi : 1; + u64 rw : 1; + u64 reserved_50 : 1; + u64 thres : 6; + u64 dat_null : 1; + u64 sector : 1; + u64 dma_val : 1; + u64 bus_id : 2; + u64 skip_busy : 1; + u64 extra_args : 1; + } cn9; +}; + +static inline u64 MIO_EMM_DMA(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA(void) +{ + return 0x2050; +} + +/** + * Register (RSL) mio_emm_dma_adr + * + * eMMC DMA Address Register This register sets the address for eMMC/SD + * flash transfers to/from memory. Sixty-four-bit operations must be used + * to access this register. This register is updated by the DMA hardware + * and can be reloaded by the values placed in the MIO_EMM_DMA_FIFO_ADR. + */ +union mio_emm_dma_adr { + u64 u; + struct mio_emm_dma_adr_s { + u64 adr : 53; + u64 reserved_53_63 : 11; + } s; + struct mio_emm_dma_adr_cn8 { + u64 adr : 49; + u64 reserved_49_63 : 15; + } cn8; + /* struct mio_emm_dma_adr_s cn9; */ +}; + +static inline u64 MIO_EMM_DMA_ADR(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_ADR(void) +{ + return 0x188; +} + +/** + * Register (RSL) mio_emm_dma_arg + * + * eMMC External DMA Extra Arguments Register + */ +union mio_emm_dma_arg { + u64 u; + struct mio_emm_dma_arg_s { + u64 cmd23_args : 8; + u64 force_pgm : 1; + u64 context_id : 4; + u64 tag_req : 1; + u64 pack_cmd : 1; + u64 rel_wr : 1; + u64 alt_cmd : 6; + u64 skip_blk_cmd : 1; + u64 reserved_23_31 : 9; + u64 alt_cmd_arg : 32; + } s; + /* struct mio_emm_dma_arg_s cn; */ +}; + +static inline u64 MIO_EMM_DMA_ARG(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_ARG(void) +{ + return 0x2090; +} + +/** + * Register (RSL) mio_emm_dma_cfg + * + * eMMC DMA Configuration Register This register controls the internal + * DMA engine used with the eMMC/SD flash controller. Sixty- four-bit + * operations must be used to access this register. This register is + * updated by the hardware DMA engine and can also be reloaded by writes + * to the MIO_EMM_DMA_FIFO_CMD register. + */ +union mio_emm_dma_cfg { + u64 u; + struct mio_emm_dma_cfg_s { + u64 reserved_0_35 : 36; + u64 size : 20; + u64 endian : 1; + u64 swap8 : 1; + u64 swap16 : 1; + u64 swap32 : 1; + u64 reserved_60 : 1; + u64 clr : 1; + u64 rw : 1; + u64 en : 1; + } s; + /* struct mio_emm_dma_cfg_s cn; */ +}; + +static inline u64 MIO_EMM_DMA_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_CFG(void) +{ + return 0x180; +} + +/** + * Register (RSL) mio_emm_dma_fifo_adr + * + * eMMC Internal DMA FIFO Address Register This register specifies the + * internal address that is loaded into the eMMC internal DMA FIFO. The + * FIFO is used to queue up operations for the + * MIO_EMM_DMA_CFG/MIO_EMM_DMA_ADR when the DMA completes successfully. + */ +union mio_emm_dma_fifo_adr { + u64 u; + struct mio_emm_dma_fifo_adr_s { + u64 reserved_0_2 : 3; + u64 adr : 50; + u64 reserved_53_63 : 11; + } s; + struct mio_emm_dma_fifo_adr_cn8 { + u64 reserved_0_2 : 3; + u64 adr : 46; + u64 reserved_49_63 : 15; + } cn8; + /* struct mio_emm_dma_fifo_adr_s cn9; */ +}; + +static inline u64 MIO_EMM_DMA_FIFO_ADR(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_FIFO_ADR(void) +{ + return 0x170; +} + +/** + * Register (RSL) mio_emm_dma_fifo_cfg + * + * eMMC Internal DMA FIFO Configuration Register This register controls + * DMA FIFO operations. + */ +union mio_emm_dma_fifo_cfg { + u64 u; + struct mio_emm_dma_fifo_cfg_s { + u64 count : 5; + u64 reserved_5_7 : 3; + u64 int_lvl : 5; + u64 reserved_13_15 : 3; + u64 clr : 1; + u64 reserved_17_63 : 47; + } s; + /* struct mio_emm_dma_fifo_cfg_s cn; */ +}; + +static inline u64 MIO_EMM_DMA_FIFO_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_FIFO_CFG(void) +{ + return 0x160; +} + +/** + * Register (RSL) mio_emm_dma_fifo_cmd + * + * eMMC Internal DMA FIFO Command Register This register specifies a + * command that is loaded into the eMMC internal DMA FIFO. The FIFO is + * used to queue up operations for the MIO_EMM_DMA_CFG/MIO_EMM_DMA_ADR + * when the DMA completes successfully. Writes to this register store + * both the MIO_EMM_DMA_FIFO_CMD and the MIO_EMM_DMA_FIFO_ADR contents + * into the FIFO and increment the MIO_EMM_DMA_FIFO_CFG[COUNT] field. + * Note: This register has a similar format to MIO_EMM_DMA_CFG with the + * exception that the EN and CLR fields are absent. These are supported + * in MIO_EMM_DMA_FIFO_CFG. + */ +union mio_emm_dma_fifo_cmd { + u64 u; + struct mio_emm_dma_fifo_cmd_s { + u64 reserved_0_35 : 36; + u64 size : 20; + u64 endian : 1; + u64 swap8 : 1; + u64 swap16 : 1; + u64 swap32 : 1; + u64 intdis : 1; + u64 reserved_61 : 1; + u64 rw : 1; + u64 reserved_63 : 1; + } s; + /* struct mio_emm_dma_fifo_cmd_s cn; */ +}; + +static inline u64 MIO_EMM_DMA_FIFO_CMD(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_FIFO_CMD(void) +{ + return 0x178; +} + +/** + * Register (RSL) mio_emm_dma_int + * + * eMMC DMA Interrupt Register Sixty-four-bit operations must be used to + * access this register. + */ +union mio_emm_dma_int { + u64 u; + struct mio_emm_dma_int_s { + u64 done : 1; + u64 fifo : 1; + u64 reserved_2_63 : 62; + } s; + /* struct mio_emm_dma_int_s cn; */ +}; + +static inline u64 MIO_EMM_DMA_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_INT(void) +{ + return 0x190; +} + +/** + * Register (RSL) mio_emm_dma_int_ena_w1c + * + * eMMC DMA Interrupt Enable Clear Register This register clears + * interrupt enable bits. + */ +union mio_emm_dma_int_ena_w1c { + u64 u; + struct mio_emm_dma_int_ena_w1c_s { + u64 done : 1; + u64 fifo : 1; + u64 reserved_2_63 : 62; + } s; + /* struct mio_emm_dma_int_ena_w1c_s cn; */ +}; + +static inline u64 MIO_EMM_DMA_INT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_INT_ENA_W1C(void) +{ + return 0x1a8; +} + +/** + * Register (RSL) mio_emm_dma_int_ena_w1s + * + * eMMC DMA Interrupt Enable Set Register This register sets interrupt + * enable bits. + */ +union mio_emm_dma_int_ena_w1s { + u64 u; + struct mio_emm_dma_int_ena_w1s_s { + u64 done : 1; + u64 fifo : 1; + u64 reserved_2_63 : 62; + } s; + /* struct mio_emm_dma_int_ena_w1s_s cn; */ +}; + +static inline u64 MIO_EMM_DMA_INT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_INT_ENA_W1S(void) +{ + return 0x1a0; +} + +/** + * Register (RSL) mio_emm_dma_int_w1s + * + * eMMC DMA Interrupt Set Register This register sets interrupt bits. + */ +union mio_emm_dma_int_w1s { + u64 u; + struct mio_emm_dma_int_w1s_s { + u64 done : 1; + u64 fifo : 1; + u64 reserved_2_63 : 62; + } s; + /* struct mio_emm_dma_int_w1s_s cn; */ +}; + +static inline u64 MIO_EMM_DMA_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_DMA_INT_W1S(void) +{ + return 0x198; +} + +/** + * Register (RSL) mio_emm_int + * + * eMMC Interrupt Register + */ +union mio_emm_int { + u64 u; + struct mio_emm_int_s { + u64 buf_done : 1; + u64 cmd_done : 1; + u64 dma_done : 1; + u64 cmd_err : 1; + u64 dma_err : 1; + u64 switch_done : 1; + u64 switch_err : 1; + u64 ncb_flt : 1; + u64 ncb_ras : 1; + u64 reserved_9_63 : 55; + } s; + struct mio_emm_int_cn8 { + u64 buf_done : 1; + u64 cmd_done : 1; + u64 dma_done : 1; + u64 cmd_err : 1; + u64 dma_err : 1; + u64 switch_done : 1; + u64 switch_err : 1; + u64 reserved_7_63 : 57; + } cn8; + /* struct mio_emm_int_s cn9; */ +}; + +static inline u64 MIO_EMM_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_INT(void) +{ + return 0x2078; +} + +/** + * Register (RSL) mio_emm_int_ena_w1c + * + * eMMC Interrupt Enable Clear Register This register clears interrupt + * enable bits. + */ +union mio_emm_int_ena_w1c { + u64 u; + struct mio_emm_int_ena_w1c_s { + u64 buf_done : 1; + u64 cmd_done : 1; + u64 dma_done : 1; + u64 cmd_err : 1; + u64 dma_err : 1; + u64 switch_done : 1; + u64 switch_err : 1; + u64 ncb_flt : 1; + u64 ncb_ras : 1; + u64 reserved_9_63 : 55; + } s; + struct mio_emm_int_ena_w1c_cn8 { + u64 buf_done : 1; + u64 cmd_done : 1; + u64 dma_done : 1; + u64 cmd_err : 1; + u64 dma_err : 1; + u64 switch_done : 1; + u64 switch_err : 1; + u64 reserved_7_63 : 57; + } cn8; + /* struct mio_emm_int_ena_w1c_s cn9; */ +}; + +static inline u64 MIO_EMM_INT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_INT_ENA_W1C(void) +{ + return 0x20b8; +} + +/** + * Register (RSL) mio_emm_int_ena_w1s + * + * eMMC Interrupt Enable Set Register This register sets interrupt enable + * bits. + */ +union mio_emm_int_ena_w1s { + u64 u; + struct mio_emm_int_ena_w1s_s { + u64 buf_done : 1; + u64 cmd_done : 1; + u64 dma_done : 1; + u64 cmd_err : 1; + u64 dma_err : 1; + u64 switch_done : 1; + u64 switch_err : 1; + u64 ncb_flt : 1; + u64 ncb_ras : 1; + u64 reserved_9_63 : 55; + } s; + struct mio_emm_int_ena_w1s_cn8 { + u64 buf_done : 1; + u64 cmd_done : 1; + u64 dma_done : 1; + u64 cmd_err : 1; + u64 dma_err : 1; + u64 switch_done : 1; + u64 switch_err : 1; + u64 reserved_7_63 : 57; + } cn8; + /* struct mio_emm_int_ena_w1s_s cn9; */ +}; + +static inline u64 MIO_EMM_INT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_INT_ENA_W1S(void) +{ + return 0x20b0; +} + +/** + * Register (RSL) mio_emm_int_w1s + * + * eMMC Interrupt Set Register This register sets interrupt bits. + */ +union mio_emm_int_w1s { + u64 u; + struct mio_emm_int_w1s_s { + u64 buf_done : 1; + u64 cmd_done : 1; + u64 dma_done : 1; + u64 cmd_err : 1; + u64 dma_err : 1; + u64 switch_done : 1; + u64 switch_err : 1; + u64 ncb_flt : 1; + u64 ncb_ras : 1; + u64 reserved_9_63 : 55; + } s; + struct mio_emm_int_w1s_cn8 { + u64 buf_done : 1; + u64 cmd_done : 1; + u64 dma_done : 1; + u64 cmd_err : 1; + u64 dma_err : 1; + u64 switch_done : 1; + u64 switch_err : 1; + u64 reserved_7_63 : 57; + } cn8; + /* struct mio_emm_int_w1s_s cn9; */ +}; + +static inline u64 MIO_EMM_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_INT_W1S(void) +{ + return 0x2080; +} + +/** + * Register (RSL) mio_emm_io_ctl + * + * eMMC I/O Control Register + */ +union mio_emm_io_ctl { + u64 u; + struct mio_emm_io_ctl_s { + u64 slew : 1; + u64 reserved_1 : 1; + u64 drive : 2; + u64 reserved_4_63 : 60; + } s; + /* struct mio_emm_io_ctl_s cn; */ +}; + +static inline u64 MIO_EMM_IO_CTL(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_IO_CTL(void) +{ + return 0x2040; +} + +/** + * Register (RSL) mio_emm_mode# + * + * eMMC Operating Mode Register + */ +union mio_emm_modex { + u64 u; + struct mio_emm_modex_s { + u64 clk_lo : 16; + u64 clk_hi : 16; + u64 power_class : 4; + u64 clk_swap : 1; + u64 reserved_37_39 : 3; + u64 bus_width : 3; + u64 reserved_43_47 : 5; + u64 hs_timing : 1; + u64 hs200_timing : 1; + u64 hs400_timing : 1; + u64 reserved_51_63 : 13; + } s; + struct mio_emm_modex_cn8 { + u64 clk_lo : 16; + u64 clk_hi : 16; + u64 power_class : 4; + u64 reserved_36_39 : 4; + u64 bus_width : 3; + u64 reserved_43_47 : 5; + u64 hs_timing : 1; + u64 reserved_49_63 : 15; + } cn8; + struct mio_emm_modex_cn96xxp1 { + u64 clk_lo : 16; + u64 clk_hi : 16; + u64 power_class : 4; + u64 reserved_36_39 : 4; + u64 bus_width : 3; + u64 reserved_43_47 : 5; + u64 hs_timing : 1; + u64 hs200_timing : 1; + u64 hs400_timing : 1; + u64 reserved_51_63 : 13; + } cn96xxp1; + /* struct mio_emm_modex_s cn96xxp3; */ + /* struct mio_emm_modex_s cnf95xx; */ +}; + +static inline u64 MIO_EMM_MODEX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_MODEX(u64 a) +{ + return 0x2008 + 8 * a; +} + +/** + * Register (RSL) mio_emm_msix_pba# + * + * eMMC MSI-X Pending Bit Array Registers This register is the MSI-X PBA + * table; the bit number is indexed by the MIO_EMM_INT_VEC_E enumeration. + */ +union mio_emm_msix_pbax { + u64 u; + struct mio_emm_msix_pbax_s { + u64 pend : 64; + } s; + /* struct mio_emm_msix_pbax_s cn; */ +}; + +static inline u64 MIO_EMM_MSIX_PBAX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_MSIX_PBAX(u64 a) +{ + return 0xf0000 + 8 * a; +} + +/** + * Register (RSL) mio_emm_msix_vec#_addr + * + * eMMC MSI-X Vector-Table Address Register This register is the MSI-X + * vector table, indexed by the MIO_EMM_INT_VEC_E enumeration. + */ +union mio_emm_msix_vecx_addr { + u64 u; + struct mio_emm_msix_vecx_addr_s { + u64 secvec : 1; + u64 reserved_1 : 1; + u64 addr : 51; + u64 reserved_53_63 : 11; + } s; + struct mio_emm_msix_vecx_addr_cn8 { + u64 secvec : 1; + u64 reserved_1 : 1; + u64 addr : 47; + u64 reserved_49_63 : 15; + } cn8; + /* struct mio_emm_msix_vecx_addr_s cn9; */ +}; + +static inline u64 MIO_EMM_MSIX_VECX_ADDR(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_MSIX_VECX_ADDR(u64 a) +{ + return 0 + 0x10 * a; +} + +/** + * Register (RSL) mio_emm_msix_vec#_ctl + * + * eMMC MSI-X Vector-Table Control and Data Register This register is the + * MSI-X vector table, indexed by the MIO_EMM_INT_VEC_E enumeration. + */ +union mio_emm_msix_vecx_ctl { + u64 u; + struct mio_emm_msix_vecx_ctl_s { + u64 data : 32; + u64 mask : 1; + u64 reserved_33_63 : 31; + } s; + struct mio_emm_msix_vecx_ctl_cn8 { + u64 data : 20; + u64 reserved_20_31 : 12; + u64 mask : 1; + u64 reserved_33_63 : 31; + } cn8; + /* struct mio_emm_msix_vecx_ctl_s cn9; */ +}; + +static inline u64 MIO_EMM_MSIX_VECX_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_MSIX_VECX_CTL(u64 a) +{ + return 8 + 0x10 * a; +} + +/** + * Register (RSL) mio_emm_rca + * + * eMMC Relative Card Address Register + */ +union mio_emm_rca { + u64 u; + struct mio_emm_rca_s { + u64 card_rca : 16; + u64 reserved_16_63 : 48; + } s; + /* struct mio_emm_rca_s cn; */ +}; + +static inline u64 MIO_EMM_RCA(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_RCA(void) +{ + return 0x20a0; +} + +/** + * Register (RSL) mio_emm_rsp_hi + * + * eMMC Response Data High Register + */ +union mio_emm_rsp_hi { + u64 u; + struct mio_emm_rsp_hi_s { + u64 dat : 64; + } s; + /* struct mio_emm_rsp_hi_s cn; */ +}; + +static inline u64 MIO_EMM_RSP_HI(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_RSP_HI(void) +{ + return 0x2070; +} + +/** + * Register (RSL) mio_emm_rsp_lo + * + * eMMC Response Data Low Register + */ +union mio_emm_rsp_lo { + u64 u; + struct mio_emm_rsp_lo_s { + u64 dat : 64; + } s; + /* struct mio_emm_rsp_lo_s cn; */ +}; + +static inline u64 MIO_EMM_RSP_LO(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_RSP_LO(void) +{ + return 0x2068; +} + +/** + * Register (RSL) mio_emm_rsp_sts + * + * eMMC Response Status Register + */ +union mio_emm_rsp_sts { + u64 u; + struct mio_emm_rsp_sts_s { + u64 cmd_done : 1; + u64 cmd_idx : 6; + u64 cmd_type : 2; + u64 rsp_type : 3; + u64 rsp_val : 1; + u64 rsp_bad_sts : 1; + u64 rsp_crc_err : 1; + u64 rsp_timeout : 1; + u64 stp_val : 1; + u64 stp_bad_sts : 1; + u64 stp_crc_err : 1; + u64 stp_timeout : 1; + u64 rsp_busybit : 1; + u64 blk_crc_err : 1; + u64 blk_timeout : 1; + u64 dbuf : 1; + u64 reserved_24_27 : 4; + u64 dbuf_err : 1; + u64 reserved_29_54 : 26; + u64 acc_timeout : 1; + u64 dma_pend : 1; + u64 dma_val : 1; + u64 switch_val : 1; + u64 cmd_val : 1; + u64 bus_id : 2; + u64 reserved_62_63 : 2; + } s; + /* struct mio_emm_rsp_sts_s cn; */ +}; + +static inline u64 MIO_EMM_RSP_STS(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_RSP_STS(void) +{ + return 0x2060; +} + +/** + * Register (RSL) mio_emm_sample + * + * eMMC Sampling Register + */ +union mio_emm_sample { + u64 u; + struct mio_emm_sample_s { + u64 dat_cnt : 10; + u64 reserved_10_15 : 6; + u64 cmd_cnt : 10; + u64 reserved_26_63 : 38; + } s; + /* struct mio_emm_sample_s cn; */ +}; + +static inline u64 MIO_EMM_SAMPLE(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_SAMPLE(void) +{ + return 0x2090; +} + +/** + * Register (RSL) mio_emm_sts_mask + * + * eMMC Status Mask Register + */ +union mio_emm_sts_mask { + u64 u; + struct mio_emm_sts_mask_s { + u64 sts_msk : 32; + u64 reserved_32_63 : 32; + } s; + /* struct mio_emm_sts_mask_s cn; */ +}; + +static inline u64 MIO_EMM_STS_MASK(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_STS_MASK(void) +{ + return 0x2098; +} + +/** + * Register (RSL) mio_emm_switch + * + * eMMC Operating Mode Switch Register This register allows software to + * change eMMC related parameters associated with a specific BUS_ID. The + * MIO_EMM_MODE() registers contain the current setting for each BUS. + * This register is also used to switch the [CLK_HI] and [CLK_LO] + * settings associated with the common EMMC_CLK. These settings can only + * be changed when [BUS_ID] = 0. + */ +union mio_emm_switch { + u64 u; + struct mio_emm_switch_s { + u64 clk_lo : 16; + u64 clk_hi : 16; + u64 power_class : 4; + u64 clk_swap : 1; + u64 reserved_37_39 : 3; + u64 bus_width : 3; + u64 reserved_43_47 : 5; + u64 hs_timing : 1; + u64 hs200_timing : 1; + u64 hs400_timing : 1; + u64 reserved_51_55 : 5; + u64 switch_err2 : 1; + u64 switch_err1 : 1; + u64 switch_err0 : 1; + u64 switch_exe : 1; + u64 bus_id : 2; + u64 reserved_62_63 : 2; + } s; + struct mio_emm_switch_cn8 { + u64 clk_lo : 16; + u64 clk_hi : 16; + u64 power_class : 4; + u64 reserved_36_39 : 4; + u64 bus_width : 3; + u64 reserved_43_47 : 5; + u64 hs_timing : 1; + u64 reserved_49_55 : 7; + u64 switch_err2 : 1; + u64 switch_err1 : 1; + u64 switch_err0 : 1; + u64 switch_exe : 1; + u64 bus_id : 2; + u64 reserved_62_63 : 2; + } cn8; + struct mio_emm_switch_cn96xxp1 { + u64 clk_lo : 16; + u64 clk_hi : 16; + u64 power_class : 4; + u64 reserved_36_39 : 4; + u64 bus_width : 3; + u64 reserved_43_47 : 5; + u64 hs_timing : 1; + u64 hs200_timing : 1; + u64 hs400_timing : 1; + u64 reserved_51_55 : 5; + u64 switch_err2 : 1; + u64 switch_err1 : 1; + u64 switch_err0 : 1; + u64 switch_exe : 1; + u64 bus_id : 2; + u64 reserved_62_63 : 2; + } cn96xxp1; + /* struct mio_emm_switch_s cn96xxp3; */ + /* struct mio_emm_switch_s cnf95xx; */ +}; + +static inline u64 MIO_EMM_SWITCH(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_SWITCH(void) +{ + return 0x2048; +} + +/** + * Register (RSL) mio_emm_tap + * + * eMMC TAP Delay Register This register indicates the delay line + * characteristics. + */ +union mio_emm_tap { + u64 u; + struct mio_emm_tap_s { + u64 delay : 8; + u64 reserved_8_63 : 56; + } s; + /* struct mio_emm_tap_s cn; */ +}; + +static inline u64 MIO_EMM_TAP(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_TAP(void) +{ + return 0x20c8; +} + +/** + * Register (RSL) mio_emm_timing + * + * eMMC Timing Register This register determines the number of tap delays + * the EMM_DAT, EMM_DS, and EMM_CMD lines are transmitted or received in + * relation to EMM_CLK. These values should only be changed when the eMMC + * bus is idle. + */ +union mio_emm_timing { + u64 u; + struct mio_emm_timing_s { + u64 data_out_tap : 6; + u64 reserved_6_15 : 10; + u64 data_in_tap : 6; + u64 reserved_22_31 : 10; + u64 cmd_out_tap : 6; + u64 reserved_38_47 : 10; + u64 cmd_in_tap : 6; + u64 reserved_54_63 : 10; + } s; + /* struct mio_emm_timing_s cn; */ +}; + +static inline u64 MIO_EMM_TIMING(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_TIMING(void) +{ + return 0x20d0; +} + +/** + * Register (RSL) mio_emm_wdog + * + * eMMC Watchdog Register + */ +union mio_emm_wdog { + u64 u; + struct mio_emm_wdog_s { + u64 clk_cnt : 26; + u64 reserved_26_63 : 38; + } s; + /* struct mio_emm_wdog_s cn; */ +}; + +static inline u64 MIO_EMM_WDOG(void) + __attribute__ ((pure, always_inline)); +static inline u64 MIO_EMM_WDOG(void) +{ + return 0x2088; +} + +#endif /* __CSRS_MIO_EMM_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-nix.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-nix.h new file mode 100644 index 000000000..2908f2504 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-nix.h @@ -0,0 +1,10404 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Marvell International Ltd. + * + * https://spdx.org/licenses + */ +#ifndef __CSRS_NIX_H__ +#define __CSRS_NIX_H__ + +/** + * @file + * + * Configuration and status register (CSR) address and type definitions for + * NIX. + * + * This file is auto generated. Do not edit. + * + */ + +/** + * Enumeration nix_af_int_vec_e + * + * NIX Admin Function Interrupt Vector Enumeration Enumerates the NIX AF + * MSI-X interrupt vectors. + */ +#define NIX_AF_INT_VEC_E_AF_ERR (3) +#define NIX_AF_INT_VEC_E_AQ_DONE (2) +#define NIX_AF_INT_VEC_E_GEN (1) +#define NIX_AF_INT_VEC_E_POISON (4) +#define NIX_AF_INT_VEC_E_RVU (0) + +/** + * Enumeration nix_aq_comp_e + * + * NIX Completion Enumeration Enumerates the values of + * NIX_AQ_RES_S[COMPCODE]. + */ +#define NIX_AQ_COMP_E_CTX_FAULT (4) +#define NIX_AQ_COMP_E_CTX_POISON (3) +#define NIX_AQ_COMP_E_GOOD (1) +#define NIX_AQ_COMP_E_LOCKERR (5) +#define NIX_AQ_COMP_E_NOTDONE (0) +#define NIX_AQ_COMP_E_SQB_ALLOC_FAIL (6) +#define NIX_AQ_COMP_E_SWERR (2) + +/** + * Enumeration nix_aq_ctype_e + * + * NIX Context Type Enumeration Enumerates NIX_AQ_INST_S[CTYPE] values. + */ +#define NIX_AQ_CTYPE_E_CQ (2) +#define NIX_AQ_CTYPE_E_DYNO (5) +#define NIX_AQ_CTYPE_E_MCE (3) +#define NIX_AQ_CTYPE_E_RQ (0) +#define NIX_AQ_CTYPE_E_RSS (4) +#define NIX_AQ_CTYPE_E_SQ (1) + +/** + * Enumeration nix_aq_instop_e + * + * NIX Admin Queue Opcode Enumeration Enumerates NIX_AQ_INST_S[OP] + * values. + */ +#define NIX_AQ_INSTOP_E_INIT (1) +#define NIX_AQ_INSTOP_E_LOCK (4) +#define NIX_AQ_INSTOP_E_NOP (0) +#define NIX_AQ_INSTOP_E_READ (3) +#define NIX_AQ_INSTOP_E_UNLOCK (5) +#define NIX_AQ_INSTOP_E_WRITE (2) + +/** + * Enumeration nix_chan_e + * + * NIX Channel Number Enumeration Enumerates the receive and transmit + * channels, and values of NIX_RX_PARSE_S[CHAN], + * NIX_SQ_CTX_S[DEFAULT_CHAN]. CNXXXX implements a subset of these + * channels. Specifically, only channels for links enumerated by + * NIX_LINK_E are implemented. Internal: P2X/X2P channel enumeration for + * t9x. + */ +#define NIX_CHAN_E_CGXX_LMACX_CHX(a, b, c) \ + (0x800 + 0x100 * (a) + 0x10 * (b) + (c)) +#define NIX_CHAN_E_LBKX_CHX(a, b) (0 + 0x100 * (a) + (b)) +#define NIX_CHAN_E_RX(a) (0 + 0x100 * (a)) +#define NIX_CHAN_E_SDP_CHX(a) (0x700 + (a)) + +/** + * Enumeration nix_colorresult_e + * + * NIX Color Result Enumeration Enumerates the values of + * NIX_MEM_RESULT_S[COLOR], NIX_AF_TL1()_MD_DEBUG1[COLOR] and + * NIX_AF_TL1()_MD_DEBUG1[COLOR]. + */ +#define NIX_COLORRESULT_E_GREEN (0) +#define NIX_COLORRESULT_E_RED_DROP (3) +#define NIX_COLORRESULT_E_RED_SEND (2) +#define NIX_COLORRESULT_E_YELLOW (1) + +/** + * Enumeration nix_cqerrint_e + * + * NIX Completion Queue Interrupt Enumeration Enumerates the bit index of + * NIX_CQ_CTX_S[CQ_ERR_INT,CQ_ERR_INT_ENA]. + */ +#define NIX_CQERRINT_E_CQE_FAULT (2) +#define NIX_CQERRINT_E_DOOR_ERR (0) +#define NIX_CQERRINT_E_WR_FULL (1) + +/** + * Enumeration nix_intf_e + * + * NIX Interface Number Enumeration Enumerates the bit index of + * NIX_AF_STATUS[CALIBRATE_STATUS]. + */ +#define NIX_INTF_E_CGXX(a) (0 + (a)) +#define NIX_INTF_E_LBKX(a) (3 + (a)) +#define NIX_INTF_E_SDP (4) + +/** + * Enumeration nix_lf_int_vec_e + * + * NIX Local Function Interrupt Vector Enumeration Enumerates the NIX + * MSI-X interrupt vectors per LF. + */ +#define NIX_LF_INT_VEC_E_CINTX(a) (0x40 + (a)) +#define NIX_LF_INT_VEC_E_ERR_INT (0x81) +#define NIX_LF_INT_VEC_E_GINT (0x80) +#define NIX_LF_INT_VEC_E_POISON (0x82) +#define NIX_LF_INT_VEC_E_QINTX(a) (0 + (a)) + +/** + * Enumeration nix_link_e + * + * NIX Link Number Enumeration Enumerates the receive and transmit links, + * and LINK index of NIX_AF_RX_LINK()_CFG, NIX_AF_RX_LINK()_WRR_CFG, + * NIX_AF_TX_LINK()_NORM_CREDIT, NIX_AF_TX_LINK()_HW_XOFF and + * NIX_AF_TL3_TL2()_LINK()_CFG. + */ +#define NIX_LINK_E_CGXX_LMACX(a, b) (0 + 4 * (a) + (b)) +#define NIX_LINK_E_LBKX(a) (0xc + (a)) +#define NIX_LINK_E_MC (0xe) +#define NIX_LINK_E_SDP (0xd) + +/** + * Enumeration nix_lsoalg_e + * + * NIX Large Send Offload Algorithm Enumeration Enumerates + * NIX_AF_LSO_FORMAT()_FIELD()[ALG] values. Specifies algorithm for + * modifying the associated LSO packet field. + */ +#define NIX_LSOALG_E_ADD_OFFSET (3) +#define NIX_LSOALG_E_ADD_PAYLEN (2) +#define NIX_LSOALG_E_ADD_SEGNUM (1) +#define NIX_LSOALG_E_NOP (0) +#define NIX_LSOALG_E_TCP_FLAGS (4) + +/** + * Enumeration nix_maxsqesz_e + * + * NIX Maximum SQE Size Enumeration Enumerates the values of + * NIX_SQ_CTX_S[MAX_SQE_SIZE]. + */ +#define NIX_MAXSQESZ_E_W16 (0) +#define NIX_MAXSQESZ_E_W8 (1) + +/** + * Enumeration nix_mdtype_e + * + * NIX Meta Descriptor Type Enumeration Enumerates values of + * NIX_AF_MDQ()_MD_DEBUG[MD_TYPE]. + */ +#define NIX_MDTYPE_E_FLUSH (1) +#define NIX_MDTYPE_E_PMD (2) +#define NIX_MDTYPE_E_RSVD (0) + +/** + * Enumeration nix_mnqerr_e + * + * NIX Meta-Descriptor Enqueue Error Enumeration Enumerates + * NIX_LF_MNQ_ERR_DBG[ERRCODE] values. + */ +#define NIX_MNQERR_E_CQ_QUERY_ERR (6) +#define NIX_MNQERR_E_LSO_ERR (5) +#define NIX_MNQERR_E_MAXLEN_ERR (8) +#define NIX_MNQERR_E_MAX_SQE_SIZE_ERR (7) +#define NIX_MNQERR_E_SQB_FAULT (2) +#define NIX_MNQERR_E_SQB_POISON (3) +#define NIX_MNQERR_E_SQE_SIZEM1_ZERO (9) +#define NIX_MNQERR_E_SQ_CTX_FAULT (0) +#define NIX_MNQERR_E_SQ_CTX_POISON (1) +#define NIX_MNQERR_E_TOTAL_ERR (4) + +/** + * Enumeration nix_ndc_rx_port_e + * + * NIX Receive NDC Port Enumeration Enumerates NIX receive NDC + * (NDC_IDX_E::NIX()_RX) ports and the PORT index of + * NDC_AF_PORT()_RT()_RW()_REQ_PC and NDC_AF_PORT()_RT()_RW()_LAT_PC. + */ +#define NIX_NDC_RX_PORT_E_AQ (0) +#define NIX_NDC_RX_PORT_E_CINT (2) +#define NIX_NDC_RX_PORT_E_CQ (1) +#define NIX_NDC_RX_PORT_E_MC (3) +#define NIX_NDC_RX_PORT_E_PKT (4) +#define NIX_NDC_RX_PORT_E_RQ (5) + +/** + * Enumeration nix_ndc_tx_port_e + * + * NIX Transmit NDC Port Enumeration Enumerates NIX transmit NDC + * (NDC_IDX_E::NIX()_TX) ports and the PORT index of + * NDC_AF_PORT()_RT()_RW()_REQ_PC and NDC_AF_PORT()_RT()_RW()_LAT_PC. + */ +#define NIX_NDC_TX_PORT_E_DEQ (3) +#define NIX_NDC_TX_PORT_E_DMA (4) +#define NIX_NDC_TX_PORT_E_ENQ (1) +#define NIX_NDC_TX_PORT_E_LMT (0) +#define NIX_NDC_TX_PORT_E_MNQ (2) +#define NIX_NDC_TX_PORT_E_XQE (5) + +/** + * Enumeration nix_re_opcode_e + * + * NIX Receive Error Opcode Enumeration Enumerates + * NIX_RX_PARSE_S[ERRCODE] values when NIX_RX_PARSE_S[ERRLEV] = + * NPC_ERRLEV_E::RE. + */ +#define NIX_RE_OPCODE_E_OL2_LENMISM (0x12) +#define NIX_RE_OPCODE_E_OVERSIZE (0x11) +#define NIX_RE_OPCODE_E_RE_DMAPKT (0xf) +#define NIX_RE_OPCODE_E_RE_FCS (7) +#define NIX_RE_OPCODE_E_RE_FCS_RCV (8) +#define NIX_RE_OPCODE_E_RE_JABBER (2) +#define NIX_RE_OPCODE_E_RE_NONE (0) +#define NIX_RE_OPCODE_E_RE_PARTIAL (1) +#define NIX_RE_OPCODE_E_RE_RX_CTL (0xb) +#define NIX_RE_OPCODE_E_RE_SKIP (0xc) +#define NIX_RE_OPCODE_E_RE_TERMINATE (9) +#define NIX_RE_OPCODE_E_UNDERSIZE (0x10) + +/** + * Enumeration nix_redalg_e + * + * NIX Red Algorithm Enumeration Enumerates the different algorithms of + * NIX_SEND_EXT_S[SHP_RA]. + */ +#define NIX_REDALG_E_DISCARD (3) +#define NIX_REDALG_E_SEND (1) +#define NIX_REDALG_E_STALL (2) +#define NIX_REDALG_E_STD (0) + +/** + * Enumeration nix_rqint_e + * + * NIX Receive Queue Interrupt Enumeration Enumerates the bit index of + * NIX_RQ_CTX_S[RQ_INT,RQ_INT_ENA]. + */ +#define NIX_RQINT_E_DROP (0) +#define NIX_RQINT_E_RX(a) (0 + (a)) +#define NIX_RQINT_E_RED (1) + +/** + * Enumeration nix_rx_actionop_e + * + * NIX Receive Action Opcode Enumeration Enumerates the values of + * NIX_RX_ACTION_S[OP]. + */ +#define NIX_RX_ACTIONOP_E_DROP (0) +#define NIX_RX_ACTIONOP_E_MCAST (3) +#define NIX_RX_ACTIONOP_E_MIRROR (6) +#define NIX_RX_ACTIONOP_E_PF_FUNC_DROP (5) +#define NIX_RX_ACTIONOP_E_RSS (4) +#define NIX_RX_ACTIONOP_E_UCAST (1) +#define NIX_RX_ACTIONOP_E_UCAST_IPSEC (2) + +/** + * Enumeration nix_rx_mcop_e + * + * NIX Receive Multicast/Mirror Opcode Enumeration Enumerates the values + * of NIX_RX_MCE_S[OP]. + */ +#define NIX_RX_MCOP_E_RQ (0) +#define NIX_RX_MCOP_E_RSS (1) + +/** + * Enumeration nix_rx_perrcode_e + * + * NIX Receive Protocol Error Code Enumeration Enumerates + * NIX_RX_PARSE_S[ERRCODE] values when NIX_RX_PARSE_S[ERRLEV] = + * NPC_ERRLEV_E::NIX. + */ +#define NIX_RX_PERRCODE_E_BUFS_OFLOW (0xa) +#define NIX_RX_PERRCODE_E_DATA_FAULT (8) +#define NIX_RX_PERRCODE_E_IL3_LEN (0x20) +#define NIX_RX_PERRCODE_E_IL4_CHK (0x22) +#define NIX_RX_PERRCODE_E_IL4_LEN (0x21) +#define NIX_RX_PERRCODE_E_IL4_PORT (0x23) +#define NIX_RX_PERRCODE_E_MCAST_FAULT (4) +#define NIX_RX_PERRCODE_E_MCAST_POISON (6) +#define NIX_RX_PERRCODE_E_MEMOUT (9) +#define NIX_RX_PERRCODE_E_MIRROR_FAULT (5) +#define NIX_RX_PERRCODE_E_MIRROR_POISON (7) +#define NIX_RX_PERRCODE_E_NPC_RESULT_ERR (2) +#define NIX_RX_PERRCODE_E_OL3_LEN (0x10) +#define NIX_RX_PERRCODE_E_OL4_CHK (0x12) +#define NIX_RX_PERRCODE_E_OL4_LEN (0x11) +#define NIX_RX_PERRCODE_E_OL4_PORT (0x13) + +/** + * Enumeration nix_send_status_e + * + * NIX Send Completion Status Enumeration Enumerates values of + * NIX_SEND_COMP_S[STATUS] and NIX_LF_SEND_ERR_DBG[ERRCODE]. + */ +#define NIX_SEND_STATUS_E_DATA_FAULT (0x16) +#define NIX_SEND_STATUS_E_DATA_POISON (0x17) +#define NIX_SEND_STATUS_E_GOOD (0) +#define NIX_SEND_STATUS_E_INVALID_SUBDC (0x14) +#define NIX_SEND_STATUS_E_JUMP_FAULT (7) +#define NIX_SEND_STATUS_E_JUMP_POISON (8) +#define NIX_SEND_STATUS_E_LOCK_VIOL (0x21) +#define NIX_SEND_STATUS_E_NPC_DROP_ACTION (0x20) +#define NIX_SEND_STATUS_E_NPC_MCAST_ABORT (0x24) +#define NIX_SEND_STATUS_E_NPC_MCAST_CHAN_ERR (0x23) +#define NIX_SEND_STATUS_E_NPC_UCAST_CHAN_ERR (0x22) +#define NIX_SEND_STATUS_E_NPC_VTAG_PTR_ERR (0x25) +#define NIX_SEND_STATUS_E_NPC_VTAG_SIZE_ERR (0x26) +#define NIX_SEND_STATUS_E_SEND_CRC_ERR (0x10) +#define NIX_SEND_STATUS_E_SEND_EXT_ERR (6) +#define NIX_SEND_STATUS_E_SEND_HDR_ERR (5) +#define NIX_SEND_STATUS_E_SEND_IMM_ERR (0x11) +#define NIX_SEND_STATUS_E_SEND_MEM_ERR (0x13) +#define NIX_SEND_STATUS_E_SEND_MEM_FAULT (0x27) +#define NIX_SEND_STATUS_E_SEND_SG_ERR (0x12) +#define NIX_SEND_STATUS_E_SQB_FAULT (3) +#define NIX_SEND_STATUS_E_SQB_POISON (4) +#define NIX_SEND_STATUS_E_SQ_CTX_FAULT (1) +#define NIX_SEND_STATUS_E_SQ_CTX_POISON (2) +#define NIX_SEND_STATUS_E_SUBDC_ORDER_ERR (0x15) + +/** + * Enumeration nix_sendcrcalg_e + * + * NIX Send CRC Algorithm Enumeration Enumerates the CRC algorithm used, + * see NIX_SEND_CRC_S[ALG]. + */ +#define NIX_SENDCRCALG_E_CRC32 (0) +#define NIX_SENDCRCALG_E_CRC32C (1) +#define NIX_SENDCRCALG_E_ONES16 (2) + +/** + * Enumeration nix_sendl3type_e + * + * NIX Send Layer 3 Header Type Enumeration Enumerates values of + * NIX_SEND_HDR_S[OL3TYPE], NIX_SEND_HDR_S[IL3TYPE]. Internal: Encoding + * matches DPDK TX IP types: \ PKT_TX_IP_CKSUM (1ULL \<\< 54) + * PKT_TX_IPV4 (1ULL \<\< 55) PKT_TX_IPV6 (1ULL \<\< + * 56) PKT_TX_OUTER_IP_CKSUM(1ULL \<\< 58) PKT_TX_OUTER_IPV4 (1ULL + * \<\< 59) PKT_TX_OUTER_IPV6 (1ULL \<\< 60) \ + */ +#define NIX_SENDL3TYPE_E_IP4 (2) +#define NIX_SENDL3TYPE_E_IP4_CKSUM (3) +#define NIX_SENDL3TYPE_E_IP6 (4) +#define NIX_SENDL3TYPE_E_NONE (0) + +/** + * Enumeration nix_sendl4type_e + * + * NIX Send Layer 4 Header Type Enumeration Enumerates values of + * NIX_SEND_HDR_S[OL4TYPE], NIX_SEND_HDR_S[IL4TYPE]. Internal: Encoding + * matches DPDK TX L4 types. \ PKT_TX_L4_NO_CKSUM (0ULL \<\< 52) + * // Disable L4 cksum of TX pkt. PKT_TX_TCP_CKSUM (1ULL \<\< 52) // + * TCP cksum of TX pkt. computed by nic. PKT_TX_SCTP_CKSUM (2ULL \<\< + * 52) // SCTP cksum of TX pkt. computed by nic. PKT_TX_UDP_CKSUM + * (3ULL \<\< 52) // UDP cksum of TX pkt. computed by nic. \ + */ +#define NIX_SENDL4TYPE_E_NONE (0) +#define NIX_SENDL4TYPE_E_SCTP_CKSUM (2) +#define NIX_SENDL4TYPE_E_TCP_CKSUM (1) +#define NIX_SENDL4TYPE_E_UDP_CKSUM (3) + +/** + * Enumeration nix_sendldtype_e + * + * NIX Send Load Type Enumeration Enumerates the load transaction types + * for reading segment bytes specified by NIX_SEND_SG_S[LD_TYPE] and + * NIX_SEND_JUMP_S[LD_TYPE]. Internal: The hardware implementation + * treats undefined encodings as LDD load type. + */ +#define NIX_SENDLDTYPE_E_LDD (0) +#define NIX_SENDLDTYPE_E_LDT (1) +#define NIX_SENDLDTYPE_E_LDWB (2) + +/** + * Enumeration nix_sendmemalg_e + * + * NIX Memory Modify Algorithm Enumeration Enumerates the different + * algorithms for modifying memory; see NIX_SEND_MEM_S[ALG]. mbufs_freed + * is the number of gather buffers freed to NPA for the send descriptor. + * See NIX_SEND_HDR_S[DF] and NIX_SEND_SG_S[I*]. + */ +#define NIX_SENDMEMALG_E_ADD (8) +#define NIX_SENDMEMALG_E_ADDLEN (0xa) +#define NIX_SENDMEMALG_E_ADDMBUF (0xc) +#define NIX_SENDMEMALG_E_SET (0) +#define NIX_SENDMEMALG_E_SETRSLT (2) +#define NIX_SENDMEMALG_E_SETTSTMP (1) +#define NIX_SENDMEMALG_E_SUB (9) +#define NIX_SENDMEMALG_E_SUBLEN (0xb) +#define NIX_SENDMEMALG_E_SUBMBUF (0xd) + +/** + * Enumeration nix_sendmemdsz_e + * + * NIX Memory Data Size Enumeration Enumerates the datum size for + * modifying memory; see NIX_SEND_MEM_S[DSZ]. + */ +#define NIX_SENDMEMDSZ_E_B16 (2) +#define NIX_SENDMEMDSZ_E_B32 (1) +#define NIX_SENDMEMDSZ_E_B64 (0) +#define NIX_SENDMEMDSZ_E_B8 (3) + +/** + * Enumeration nix_sqint_e + * + * NIX Send Queue Interrupt Enumeration Enumerates the bit index of + * NIX_SQ_CTX_S[SQ_INT,SQ_INT_ENA]. + */ +#define NIX_SQINT_E_LMT_ERR (0) +#define NIX_SQINT_E_MNQ_ERR (1) +#define NIX_SQINT_E_SEND_ERR (2) +#define NIX_SQINT_E_SQB_ALLOC_FAIL (3) + +/** + * Enumeration nix_sqoperr_e + * + * NIX SQ Operation Error Enumeration Enumerates + * NIX_LF_SQ_OP_ERR_DBG[ERRCODE] values. + */ +#define NIX_SQOPERR_E_MAX_SQE_SIZE_ERR (4) +#define NIX_SQOPERR_E_SQB_FAULT (7) +#define NIX_SQOPERR_E_SQB_NULL (6) +#define NIX_SQOPERR_E_SQE_OFLOW (5) +#define NIX_SQOPERR_E_SQE_SIZEM1_ZERO (8) +#define NIX_SQOPERR_E_SQ_CTX_FAULT (1) +#define NIX_SQOPERR_E_SQ_CTX_POISON (2) +#define NIX_SQOPERR_E_SQ_DISABLED (3) +#define NIX_SQOPERR_E_SQ_OOR (0) + +/** + * Enumeration nix_stat_lf_rx_e + * + * NIX Local Function Receive Statistics Enumeration Enumerates the last + * index of NIX_AF_LF()_RX_STAT() and NIX_LF_RX_STAT(). + */ +#define NIX_STAT_LF_RX_E_RX_BCAST (2) +#define NIX_STAT_LF_RX_E_RX_DROP (4) +#define NIX_STAT_LF_RX_E_RX_DROP_OCTS (5) +#define NIX_STAT_LF_RX_E_RX_DRP_BCAST (8) +#define NIX_STAT_LF_RX_E_RX_DRP_L3BCAST (0xa) +#define NIX_STAT_LF_RX_E_RX_DRP_L3MCAST (0xb) +#define NIX_STAT_LF_RX_E_RX_DRP_MCAST (9) +#define NIX_STAT_LF_RX_E_RX_ERR (7) +#define NIX_STAT_LF_RX_E_RX_FCS (6) +#define NIX_STAT_LF_RX_E_RX_MCAST (3) +#define NIX_STAT_LF_RX_E_RX_OCTS (0) +#define NIX_STAT_LF_RX_E_RX_UCAST (1) + +/** + * Enumeration nix_stat_lf_tx_e + * + * NIX Local Function Transmit Statistics Enumeration Enumerates the + * index of NIX_AF_LF()_TX_STAT() and NIX_LF_TX_STAT(). These statistics + * do not account for packet replication due to NIX_TX_ACTION_S[OP] = + * NIX_TX_ACTIONOP_E::MCAST. + */ +#define NIX_STAT_LF_TX_E_TX_BCAST (1) +#define NIX_STAT_LF_TX_E_TX_DROP (3) +#define NIX_STAT_LF_TX_E_TX_MCAST (2) +#define NIX_STAT_LF_TX_E_TX_OCTS (4) +#define NIX_STAT_LF_TX_E_TX_UCAST (0) + +/** + * Enumeration nix_stype_e + * + * NIX SQB Caching Type Enumeration Enumerates the values of + * NIX_SQ_CTX_S[SQE_STYPE]. + */ +#define NIX_STYPE_E_STF (0) +#define NIX_STYPE_E_STP (2) +#define NIX_STYPE_E_STT (1) + +/** + * Enumeration nix_subdc_e + * + * NIX Subdescriptor Operation Enumeration Enumerates send and receive + * subdescriptor codes. The codes differentiate subdescriptors within a + * NIX send or receive descriptor, excluding NIX_SEND_HDR_S for send and + * NIX_CQE_HDR_S/NIX_WQE_HDR_S for receive, which are determined by their + * position as the first subdescriptor, and NIX_RX_PARSE_S, which is + * determined by its position as the second subdescriptor. + */ +#define NIX_SUBDC_E_CRC (2) +#define NIX_SUBDC_E_EXT (1) +#define NIX_SUBDC_E_IMM (3) +#define NIX_SUBDC_E_JUMP (6) +#define NIX_SUBDC_E_MEM (5) +#define NIX_SUBDC_E_NOP (0) +#define NIX_SUBDC_E_SG (4) +#define NIX_SUBDC_E_SOD (0xf) +#define NIX_SUBDC_E_WORK (7) + +/** + * Enumeration nix_tx_actionop_e + * + * NIX Transmit Action Opcode Enumeration Enumerates the values of + * NIX_TX_ACTION_S[OP]. + */ +#define NIX_TX_ACTIONOP_E_DROP (0) +#define NIX_TX_ACTIONOP_E_DROP_VIOL (5) +#define NIX_TX_ACTIONOP_E_MCAST (3) +#define NIX_TX_ACTIONOP_E_UCAST_CHAN (2) +#define NIX_TX_ACTIONOP_E_UCAST_DEFAULT (1) + +/** + * Enumeration nix_tx_vtagop_e + * + * NIX Transmit Vtag Opcode Enumeration Enumerates the values of + * NIX_TX_VTAG_ACTION_S[VTAG0_OP,VTAG1_OP]. + */ +#define NIX_TX_VTAGOP_E_INSERT (1) +#define NIX_TX_VTAGOP_E_NOP (0) +#define NIX_TX_VTAGOP_E_REPLACE (2) + +/** + * Enumeration nix_txlayer_e + * + * NIX Transmit Layer Enumeration Enumerates the values of + * NIX_AF_LSO_FORMAT()_FIELD()[LAYER]. + */ +#define NIX_TXLAYER_E_IL3 (2) +#define NIX_TXLAYER_E_IL4 (3) +#define NIX_TXLAYER_E_OL3 (0) +#define NIX_TXLAYER_E_OL4 (1) + +/** + * Enumeration nix_vtagsize_e + * + * NIX Vtag Size Enumeration Enumerates the values of + * NIX_AF_TX_VTAG_DEF()_CTL[SIZE] and NIX_AF_LF()_RX_VTAG_TYPE()[SIZE]. + */ +#define NIX_VTAGSIZE_E_T4 (0) +#define NIX_VTAGSIZE_E_T8 (1) + +/** + * Enumeration nix_xqe_type_e + * + * NIX WQE/CQE Type Enumeration Enumerates the values of + * NIX_WQE_HDR_S[WQE_TYPE], NIX_CQE_HDR_S[CQE_TYPE]. + */ +#define NIX_XQE_TYPE_E_INVALID (0) +#define NIX_XQE_TYPE_E_RX (1) +#define NIX_XQE_TYPE_E_RX_IPSECD (4) +#define NIX_XQE_TYPE_E_RX_IPSECH (3) +#define NIX_XQE_TYPE_E_RX_IPSECS (2) +#define NIX_XQE_TYPE_E_SEND (8) + +/** + * Enumeration nix_xqesz_e + * + * NIX WQE/CQE Size Enumeration Enumerates the values of + * NIX_AF_LF()_CFG[XQE_SIZE]. + */ +#define NIX_XQESZ_E_W16 (1) +#define NIX_XQESZ_E_W64 (0) + +/** + * Structure nix_aq_inst_s + * + * NIX Admin Queue Instruction Structure This structure specifies the AQ + * instruction. Instructions and associated software structures are + * stored in memory as little-endian unless NIX_AF_CFG[AF_BE] is set. + * Hardware reads of NIX_AQ_INST_S do not allocate into LLC. Hardware + * reads and writes of the context structure selected by [CTYPE], [LF] + * and [CINDEX] use the NDC and LLC caching style configured for that + * context. For example: * When [CTYPE] = NIX_AQ_CTYPE_E::RQ: use + * NIX_AF_LF()_RSS_CFG[CACHING] and NIX_AF_LF()_RSS_CFG[WAY_MASK]. * When + * [CTYPE] = NIX_AQ_CTYPE_E::MCE: use NIX_AF_RX_MCAST_CFG[CACHING] and + * NIX_AF_RX_MCAST_CFG[WAY_MASK]. + */ +union nix_aq_inst_s { + u64 u[2]; + struct nix_aq_inst_s_s { + u64 op : 4; + u64 ctype : 4; + u64 lf : 7; + u64 reserved_15_23 : 9; + u64 cindex : 20; + u64 reserved_44_62 : 19; + u64 doneint : 1; + u64 res_addr : 64; + } s; + /* struct nix_aq_inst_s_s cn; */ +}; + +/** + * Structure nix_aq_res_s + * + * NIX Admin Queue Result Structure NIX writes this structure after it + * completes the NIX_AQ_INST_S instruction. The result structure is + * exactly 16 bytes, and each instruction completion produces exactly one + * result structure. Results and associated software structures are + * stored in memory as little-endian unless NIX_AF_CFG[AF_BE] is set. + * When [OP] = NIX_AQ_INSTOP_E::INIT, WRITE or READ, this structure is + * immediately followed by context read or write data. See + * NIX_AQ_INSTOP_E. Hardware writes of NIX_AQ_RES_S and context data + * always allocate into LLC. Hardware reads of context data do not + * allocate into LLC. + */ +union nix_aq_res_s { + u64 u[2]; + struct nix_aq_res_s_s { + u64 op : 4; + u64 ctype : 4; + u64 compcode : 8; + u64 doneint : 1; + u64 reserved_17_63 : 47; + u64 reserved_64_127 : 64; + } s; + /* struct nix_aq_res_s_s cn; */ +}; + +/** + * Structure nix_cint_hw_s + * + * NIX Completion Interrupt Context Hardware Structure This structure + * contains context state maintained by hardware for each completion + * interrupt (CINT) in NDC/LLC/DRAM. Software accesses this structure + * with the NIX_LF_CINT()* registers. Hardware maintains a table of + * NIX_AF_CONST2[CINTS] contiguous NIX_CINT_HW_S structures per LF + * starting at AF IOVA NIX_AF_LF()_CINTS_BASE. Always stored in byte + * invariant little-endian format (LE8). + */ +union nix_cint_hw_s { + u64 u[2]; + struct nix_cint_hw_s_s { + u64 ecount : 32; + u64 qcount : 16; + u64 intr : 1; + u64 ena : 1; + u64 timer_idx : 8; + u64 reserved_58_63 : 6; + u64 ecount_wait : 32; + u64 qcount_wait : 16; + u64 time_wait : 8; + u64 reserved_120_127 : 8; + } s; + /* struct nix_cint_hw_s_s cn; */ +}; + +/** + * Structure nix_cq_ctx_s + * + * NIX Completion Queue Context Structure This structure contains context + * state maintained by hardware for each CQ in NDC/LLC/DRAM. Software + * uses the same structure format to read and write an CQ context with + * the NIX admin queue. + */ +union nix_cq_ctx_s { + u64 u[4]; + struct nix_cq_ctx_s_s { + u64 base : 64; + u64 reserved_64_67 : 4; + u64 bp_ena : 1; + u64 reserved_69_71 : 3; + u64 bpid : 9; + u64 reserved_81_83 : 3; + u64 qint_idx : 7; + u64 cq_err : 1; + u64 cint_idx : 7; + u64 avg_con : 9; + u64 wrptr : 20; + u64 tail : 20; + u64 head : 20; + u64 avg_level : 8; + u64 update_time : 16; + u64 bp : 8; + u64 drop : 8; + u64 drop_ena : 1; + u64 ena : 1; + u64 reserved_210_211 : 2; + u64 substream : 20; + u64 caching : 1; + u64 reserved_233_235 : 3; + u64 qsize : 4; + u64 cq_err_int : 8; + u64 cq_err_int_ena : 8; + } s; + /* struct nix_cq_ctx_s_s cn; */ +}; + +/** + * Structure nix_cqe_hdr_s + * + * NIX Completion Queue Entry Header Structure This 64-bit structure + * defines the first word of every CQE. It is immediately followed by + * NIX_RX_PARSE_S in a receive CQE, and by NIX_SEND_COMP_S in a send + * completion CQE. Stored in memory as little-endian unless + * NIX_AF_LF()_CFG[BE] is set. + */ +union nix_cqe_hdr_s { + u64 u; + struct nix_cqe_hdr_s_s { + u64 tag : 32; + u64 q : 20; + u64 reserved_52_57 : 6; + u64 node : 2; + u64 cqe_type : 4; + } s; + /* struct nix_cqe_hdr_s_s cn; */ +}; + +/** + * Structure nix_inst_hdr_s + * + * NIX Instruction Header Structure This structure defines the + * instruction header that precedes the packet header supplied to NPC for + * packets to be transmitted by NIX. + */ +union nix_inst_hdr_s { + u64 u; + struct nix_inst_hdr_s_s { + u64 pf_func : 16; + u64 sq : 20; + u64 reserved_36_63 : 28; + } s; + /* struct nix_inst_hdr_s_s cn; */ +}; + +/** + * Structure nix_iova_s + * + * NIX I/O Virtual Address Structure + */ +union nix_iova_s { + u64 u; + struct nix_iova_s_s { + u64 addr : 64; + } s; + /* struct nix_iova_s_s cn; */ +}; + +/** + * Structure nix_ipsec_dyno_s + * + * INTERNAL: NIX IPSEC Dynamic Ordering Counter Structure Internal: Not + * used; no IPSEC fast-path. + */ +union nix_ipsec_dyno_s { + u32 u; + struct nix_ipsec_dyno_s_s { + u32 count : 32; + } s; + /* struct nix_ipsec_dyno_s_s cn; */ +}; + +/** + * Structure nix_mem_result_s + * + * NIX Memory Value Structure When + * NIX_SEND_MEM_S[ALG]=NIX_SENDMEMALG_E::SETRSLT, the value written to + * memory is formed with this structure. + */ +union nix_mem_result_s { + u64 u; + struct nix_mem_result_s_s { + u64 v : 1; + u64 color : 2; + u64 reserved_3_63 : 61; + } s; + /* struct nix_mem_result_s_s cn; */ +}; + +/** + * Structure nix_op_q_wdata_s + * + * NIX Statistics Operation Write Data Structure This structure specifies + * the write data format of an atomic 64-bit load-and-add of some + * NIX_LF_RQ_OP_*, NIX_LF_SQ_OP* and NIX_LF_CQ_OP* registers. + */ +union nix_op_q_wdata_s { + u64 u; + struct nix_op_q_wdata_s_s { + u64 reserved_0_31 : 32; + u64 q : 20; + u64 reserved_52_63 : 12; + } s; + /* struct nix_op_q_wdata_s_s cn; */ +}; + +/** + * Structure nix_qint_hw_s + * + * NIX Queue Interrupt Context Hardware Structure This structure contains + * context state maintained by hardware for each queue interrupt (QINT) + * in NDC/LLC/DRAM. Software accesses this structure with the + * NIX_LF_QINT()* registers. Hardware maintains a table of + * NIX_AF_CONST2[QINTS] contiguous NIX_QINT_HW_S structures per LF + * starting at IOVA NIX_AF_LF()_QINTS_BASE. Always stored in byte + * invariant little-endian format (LE8). + */ +union nix_qint_hw_s { + u32 u; + struct nix_qint_hw_s_s { + u32 count : 22; + u32 reserved_22_30 : 9; + u32 ena : 1; + } s; + /* struct nix_qint_hw_s_s cn; */ +}; + +/** + * Structure nix_rq_ctx_hw_s + * + * NIX Receive Queue Context Structure This structure contains context + * state maintained by hardware for each RQ in NDC/LLC/DRAM. Software + * uses the equivalent NIX_RQ_CTX_S structure format to read and write an + * RQ context with the NIX admin queue. Always stored in byte invariant + * little-endian format (LE8). + */ +union nix_rq_ctx_hw_s { + u64 u[16]; + struct nix_rq_ctx_hw_s_s { + u64 ena : 1; + u64 sso_ena : 1; + u64 ipsech_ena : 1; + u64 ena_wqwd : 1; + u64 cq : 20; + u64 substream : 20; + u64 wqe_aura : 20; + u64 spb_aura : 20; + u64 lpb_aura : 20; + u64 sso_grp : 10; + u64 sso_tt : 2; + u64 pb_caching : 2; + u64 wqe_caching : 1; + u64 xqe_drop_ena : 1; + u64 spb_drop_ena : 1; + u64 lpb_drop_ena : 1; + u64 wqe_skip : 2; + u64 reserved_124_127 : 4; + u64 reserved_128_139 : 12; + u64 spb_sizem1 : 6; + u64 reserved_146_150 : 5; + u64 spb_ena : 1; + u64 lpb_sizem1 : 12; + u64 first_skip : 7; + u64 reserved_171 : 1; + u64 later_skip : 6; + u64 xqe_imm_size : 6; + u64 reserved_184_189 : 6; + u64 xqe_imm_copy : 1; + u64 xqe_hdr_split : 1; + u64 xqe_drop : 8; + u64 xqe_pass : 8; + u64 wqe_pool_drop : 8; + u64 wqe_pool_pass : 8; + u64 spb_aura_drop : 8; + u64 spb_aura_pass : 8; + u64 spb_pool_drop : 8; + u64 spb_pool_pass : 8; + u64 lpb_aura_drop : 8; + u64 lpb_aura_pass : 8; + u64 lpb_pool_drop : 8; + u64 lpb_pool_pass : 8; + u64 reserved_288_319 : 32; + u64 ltag : 24; + u64 good_utag : 8; + u64 bad_utag : 8; + u64 flow_tagw : 6; + u64 reserved_366_383 : 18; + u64 octs : 48; + u64 reserved_432_447 : 16; + u64 pkts : 48; + u64 reserved_496_511 : 16; + u64 drop_octs : 48; + u64 reserved_560_575 : 16; + u64 drop_pkts : 48; + u64 reserved_624_639 : 16; + u64 re_pkts : 48; + u64 reserved_688_702 : 15; + u64 ena_copy : 1; + u64 reserved_704_739 : 36; + u64 rq_int : 8; + u64 rq_int_ena : 8; + u64 qint_idx : 7; + u64 reserved_763_767 : 5; + u64 reserved_768_831 : 64; + u64 reserved_832_895 : 64; + u64 reserved_896_959 : 64; + u64 reserved_960_1023 : 64; + } s; + /* struct nix_rq_ctx_hw_s_s cn; */ +}; + +/** + * Structure nix_rq_ctx_s + * + * NIX Receive Queue Context Structure This structure specifies the + * format used by software to read and write an RQ context with the NIX + * admin queue. + */ +union nix_rq_ctx_s { + u64 u[16]; + struct nix_rq_ctx_s_s { + u64 ena : 1; + u64 sso_ena : 1; + u64 ipsech_ena : 1; + u64 ena_wqwd : 1; + u64 cq : 20; + u64 substream : 20; + u64 wqe_aura : 20; + u64 spb_aura : 20; + u64 lpb_aura : 20; + u64 sso_grp : 10; + u64 sso_tt : 2; + u64 pb_caching : 2; + u64 wqe_caching : 1; + u64 xqe_drop_ena : 1; + u64 spb_drop_ena : 1; + u64 lpb_drop_ena : 1; + u64 reserved_122_127 : 6; + u64 reserved_128_139 : 12; + u64 spb_sizem1 : 6; + u64 wqe_skip : 2; + u64 reserved_148_150 : 3; + u64 spb_ena : 1; + u64 lpb_sizem1 : 12; + u64 first_skip : 7; + u64 reserved_171 : 1; + u64 later_skip : 6; + u64 xqe_imm_size : 6; + u64 reserved_184_189 : 6; + u64 xqe_imm_copy : 1; + u64 xqe_hdr_split : 1; + u64 xqe_drop : 8; + u64 xqe_pass : 8; + u64 wqe_pool_drop : 8; + u64 wqe_pool_pass : 8; + u64 spb_aura_drop : 8; + u64 spb_aura_pass : 8; + u64 spb_pool_drop : 8; + u64 spb_pool_pass : 8; + u64 lpb_aura_drop : 8; + u64 lpb_aura_pass : 8; + u64 lpb_pool_drop : 8; + u64 lpb_pool_pass : 8; + u64 reserved_288_291 : 4; + u64 rq_int : 8; + u64 rq_int_ena : 8; + u64 qint_idx : 7; + u64 reserved_315_319 : 5; + u64 ltag : 24; + u64 good_utag : 8; + u64 bad_utag : 8; + u64 flow_tagw : 6; + u64 reserved_366_383 : 18; + u64 octs : 48; + u64 reserved_432_447 : 16; + u64 pkts : 48; + u64 reserved_496_511 : 16; + u64 drop_octs : 48; + u64 reserved_560_575 : 16; + u64 drop_pkts : 48; + u64 reserved_624_639 : 16; + u64 re_pkts : 48; + u64 reserved_688_703 : 16; + u64 reserved_704_767 : 64; + u64 reserved_768_831 : 64; + u64 reserved_832_895 : 64; + u64 reserved_896_959 : 64; + u64 reserved_960_1023 : 64; + } s; + /* struct nix_rq_ctx_s_s cn; */ +}; + +/** + * Structure nix_rsse_s + * + * NIX Receive Side Scaling Entry Structure This structure specifies the + * format of each hardware entry in the NIX RSS tables in NDC/LLC/DRAM. + * See NIX_AF_LF()_RSS_BASE and NIX_AF_LF()_RSS_GRP(). Software uses the + * same structure format to read and write an RSS table entry with the + * NIX admin queue. + */ +union nix_rsse_s { + u32 u; + struct nix_rsse_s_s { + u32 rq : 20; + u32 reserved_20_31 : 12; + } s; + /* struct nix_rsse_s_s cn; */ +}; + +/** + * Structure nix_rx_action_s + * + * NIX Receive Action Structure This structure defines the format of + * NPC_RESULT_S[ACTION] for a receive packet. + */ +union nix_rx_action_s { + u64 u; + struct nix_rx_action_s_s { + u64 op : 4; + u64 pf_func : 16; + u64 index : 20; + u64 match_id : 16; + u64 flow_key_alg : 5; + u64 reserved_61_63 : 3; + } s; + /* struct nix_rx_action_s_s cn; */ +}; + +/** + * Structure nix_rx_imm_s + * + * NIX Receive Immediate Subdescriptor Structure The receive immediate + * subdescriptor indicates that bytes immediately following this + * NIX_RX_IMM_S (after skipping [APAD] bytes) were saved from the + * received packet. The next subdescriptor following this NIX_RX_IMM_S + * (when one exists) will follow the immediate bytes, after rounding up + * the address to a multiple of 16 bytes. + */ +union nix_rx_imm_s { + u64 u; + struct nix_rx_imm_s_s { + u64 size : 16; + u64 apad : 3; + u64 reserved_19_59 : 41; + u64 subdc : 4; + } s; + /* struct nix_rx_imm_s_s cn; */ +}; + +/** + * Structure nix_rx_mce_s + * + * NIX Receive Multicast/Mirror Entry Structure This structure specifies + * the format of entries in the NIX receive multicast/mirror table + * maintained by hardware in NDC/LLC/DRAM. See NIX_AF_RX_MCAST_BASE and + * NIX_AF_RX_MCAST_CFG. Note the table may contain both multicast and + * mirror replication lists. Software uses the same structure format to + * read and write a multicast/mirror table entry with the NIX admin + * queue. + */ +union nix_rx_mce_s { + u64 u; + struct nix_rx_mce_s_s { + u64 op : 2; + u64 reserved_2 : 1; + u64 eol : 1; + u64 index : 20; + u64 reserved_24_31 : 8; + u64 pf_func : 16; + u64 next : 16; + } s; + /* struct nix_rx_mce_s_s cn; */ +}; + +/** + * Structure nix_rx_parse_s + * + * NIX Receive Parse Structure This structure contains the receive packet + * parse result. It immediately follows NIX_CQE_HDR_S in a receive CQE, + * or NIX_WQE_HDR_S in a receive WQE. Stored in memory as little-endian + * unless NIX_AF_LF()_CFG[BE] is set. Header layers are always 2-byte + * aligned, so all header pointers in this structure ([EOH_PTR], [LAPTR] + * through [LHPTR], [VTAG*_PTR]) are even. + */ +union nix_rx_parse_s { + u64 u[7]; + struct nix_rx_parse_s_s { + u64 chan : 12; + u64 desc_sizem1 : 5; + u64 imm_copy : 1; + u64 express : 1; + u64 wqwd : 1; + u64 errlev : 4; + u64 errcode : 8; + u64 latype : 4; + u64 lbtype : 4; + u64 lctype : 4; + u64 ldtype : 4; + u64 letype : 4; + u64 lftype : 4; + u64 lgtype : 4; + u64 lhtype : 4; + u64 pkt_lenm1 : 16; + u64 l2m : 1; + u64 l2b : 1; + u64 l3m : 1; + u64 l3b : 1; + u64 vtag0_valid : 1; + u64 vtag0_gone : 1; + u64 vtag1_valid : 1; + u64 vtag1_gone : 1; + u64 pkind : 6; + u64 reserved_94_95 : 2; + u64 vtag0_tci : 16; + u64 vtag1_tci : 16; + u64 laflags : 8; + u64 lbflags : 8; + u64 lcflags : 8; + u64 ldflags : 8; + u64 leflags : 8; + u64 lfflags : 8; + u64 lgflags : 8; + u64 lhflags : 8; + u64 eoh_ptr : 8; + u64 wqe_aura : 20; + u64 pb_aura : 20; + u64 match_id : 16; + u64 laptr : 8; + u64 lbptr : 8; + u64 lcptr : 8; + u64 ldptr : 8; + u64 leptr : 8; + u64 lfptr : 8; + u64 lgptr : 8; + u64 lhptr : 8; + u64 vtag0_ptr : 8; + u64 vtag1_ptr : 8; + u64 flow_key_alg : 5; + u64 reserved_341_383 : 43; + u64 reserved_384_447 : 64; + } s; + /* struct nix_rx_parse_s_s cn; */ +}; + +/** + * Structure nix_rx_sg_s + * + * NIX Receive Scatter/Gather Subdescriptor Structure The receive + * scatter/gather subdescriptor specifies one to three segments of packet + * data bytes. There may be multiple NIX_RX_SG_Ss in each NIX receive + * descriptor. NIX_RX_SG_S is immediately followed by one NIX_IOVA_S + * word when [SEGS] = 1, three NIX_IOVA_S words when [SEGS] \>= 2. Each + * NIX_IOVA_S word specifies the LF IOVA of first packet data byte in the + * corresponding segment; first NIX_IOVA_S word for segment 1, second + * word for segment 2, third word for segment 3. Note the third word is + * present when [SEGS] \>= 2 but only valid when [SEGS] = 3. + */ +union nix_rx_sg_s { + u64 u; + struct nix_rx_sg_s_s { + u64 seg1_size : 16; + u64 seg2_size : 16; + u64 seg3_size : 16; + u64 segs : 2; + u64 reserved_50_59 : 10; + u64 subdc : 4; + } s; + /* struct nix_rx_sg_s_s cn; */ +}; + +/** + * Structure nix_rx_vtag_action_s + * + * NIX Receive Vtag Action Structure This structure defines the format of + * NPC_RESULT_S[VTAG_ACTION] for a receive packet. It specifies up to two + * Vtags (e.g. C-VLAN/S-VLAN tags, 802.1BR E-TAG) for optional capture + * and/or stripping. + */ +union nix_rx_vtag_action_s { + u64 u; + struct nix_rx_vtag_action_s_s { + u64 vtag0_relptr : 8; + u64 vtag0_lid : 3; + u64 reserved_11 : 1; + u64 vtag0_type : 3; + u64 vtag0_valid : 1; + u64 reserved_16_31 : 16; + u64 vtag1_relptr : 8; + u64 vtag1_lid : 3; + u64 reserved_43 : 1; + u64 vtag1_type : 3; + u64 vtag1_valid : 1; + u64 reserved_48_63 : 16; + } s; + /* struct nix_rx_vtag_action_s_s cn; */ +}; + +/** + * Structure nix_send_comp_s + * + * NIX Send Completion Structure This structure immediately follows + * NIX_CQE_HDR_S in a send completion CQE. + */ +union nix_send_comp_s { + u64 u; + struct nix_send_comp_s_s { + u64 status : 8; + u64 sqe_id : 16; + u64 reserved_24_63 : 40; + } s; + /* struct nix_send_comp_s_s cn; */ +}; + +/** + * Structure nix_send_crc_s + * + * NIX Send CRC Subdescriptor Structure The send CRC subdescriptor + * specifies a CRC calculation be performed during transmission. Ignored + * when present in a send descriptor with NIX_SEND_EXT_S[LSO] set. There + * may be up to two NIX_SEND_CRC_Ss per send descriptor. NIX_SEND_CRC_S + * constraints: * When present, NIX_SEND_CRC_S subdescriptors must + * precede all NIX_SEND_SG_S, NIX_SEND_IMM_S and NIX_SEND_MEM_S + * subdescriptors in the send descriptor. * NIX_SEND_CRC_S subdescriptors + * must follow the same order as their checksum and insert regions in the + * packet, i.e. the checksum and insert regions of a NIX_SEND_CRC_S must + * come after the checksum and insert regions of a preceding + * NIX_SEND_CRC_S. There must be no overlap between any NIX_SEND_CRC_S + * checksum and insert regions. * If either + * NIX_SEND_HDR_S[OL4TYPE,IL4TYPE] = NIX_SENDL4TYPE_E::SCTP_CKSUM, the + * SCTP checksum region and NIX_SEND_CRC_S insert region must not + * overlap, and likewise the NIX_SEND_CRC_S checksum region and SCTP + * insert region must not overlap. * If either + * NIX_SEND_HDR_S[OL3TYPE,IL3TYPE] = NIX_SENDL3TYPE_E::IP4_CKSUM, the + * IPv4 header checksum region and NIX_SEND_CRC_S insert region must not + * overlap. * Any checksums inserted by + * NIX_SEND_HDR_S[OL3TYPE,OL4TYPE,IL3TYPE,IL4TYPE] must be outside of the + * NIX_SEND_CRC_S checksum and insert regions. Hardware adjusts [START], + * [SIZE] and [INSERT] as needed to account for any VLAN inserted by + * NIX_SEND_EXT_S[VLAN*] or Vtag inserted by NIX_TX_VTAG_ACTION_S. + */ +union nix_send_crc_s { + u64 u[2]; + struct nix_send_crc_s_s { + u64 size : 16; + u64 start : 16; + u64 insert : 16; + u64 reserved_48_57 : 10; + u64 alg : 2; + u64 subdc : 4; + u64 iv : 32; + u64 reserved_96_127 : 32; + } s; + /* struct nix_send_crc_s_s cn; */ +}; + +/** + * Structure nix_send_ext_s + * + * NIX Send Extended Header Subdescriptor Structure The send extended + * header specifies LSO, VLAN insertion, timestamp and/or scheduling + * services on the packet. If present, it must immediately follow + * NIX_SEND_HDR_S. All fields are assumed to be zero when this + * subdescriptor is not present. + */ +union nix_send_ext_s { + u64 u[2]; + struct nix_send_ext_s_s { + u64 lso_mps : 14; + u64 lso : 1; + u64 tstmp : 1; + u64 lso_sb : 8; + u64 lso_format : 5; + u64 reserved_29_31 : 3; + u64 shp_chg : 9; + u64 shp_dis : 1; + u64 shp_ra : 2; + u64 markptr : 8; + u64 markform : 7; + u64 mark_en : 1; + u64 subdc : 4; + u64 vlan0_ins_ptr : 8; + u64 vlan0_ins_tci : 16; + u64 vlan1_ins_ptr : 8; + u64 vlan1_ins_tci : 16; + u64 vlan0_ins_ena : 1; + u64 vlan1_ins_ena : 1; + u64 reserved_114_127 : 14; + } s; + /* struct nix_send_ext_s_s cn; */ +}; + +/** + * Structure nix_send_hdr_s + * + * NIX Send Header Subdescriptor Structure The send header is the first + * subdescriptor of every send descriptor. + */ +union nix_send_hdr_s { + u64 u[2]; + struct nix_send_hdr_s_s { + u64 total : 18; + u64 reserved_18 : 1; + u64 df : 1; + u64 aura : 20; + u64 sizem1 : 3; + u64 pnc : 1; + u64 sq : 20; + u64 ol3ptr : 8; + u64 ol4ptr : 8; + u64 il3ptr : 8; + u64 il4ptr : 8; + u64 ol3type : 4; + u64 ol4type : 4; + u64 il3type : 4; + u64 il4type : 4; + u64 sqe_id : 16; + } s; + /* struct nix_send_hdr_s_s cn; */ +}; + +/** + * Structure nix_send_imm_s + * + * NIX Send Immediate Subdescriptor Structure The send immediate + * subdescriptor requests that bytes immediately following this + * NIX_SEND_IMM_S (after skipping [APAD] bytes) are to be included in the + * packet data. The next subdescriptor following this NIX_SEND_IMM_S + * (when one exists) will follow the immediate bytes, after rounding up + * the address to a multiple of 16 bytes. There may be multiple + * NIX_SEND_IMM_S in one NIX send descriptor. A NIX_SEND_IMM_S is ignored + * in a NIX send descriptor if the sum of all prior + * NIX_SEND_SG_S[SEG*_SIZE]s and NIX_SEND_IMM_S[SIZE]s meets or exceeds + * NIX_SEND_HDR_S[TOTAL]. When NIX_SEND_EXT_S[LSO] is set in the + * descriptor, all NIX_SEND_IMM_S bytes must be included in the first + * NIX_SEND_EXT_S[LSO_SB] bytes of the source packet. + */ +union nix_send_imm_s { + u64 u; + struct nix_send_imm_s_s { + u64 size : 16; + u64 apad : 3; + u64 reserved_19_59 : 41; + u64 subdc : 4; + } s; + /* struct nix_send_imm_s_s cn; */ +}; + +/** + * Structure nix_send_jump_s + * + * NIX Send Jump Subdescriptor Structure The send jump subdescriptor + * selects a new address for fetching the remaining subdescriptors of a + * send descriptor. This allows software to create a send descriptor + * longer than SQE size selected by NIX_SQ_CTX_S[MAX_SQE_SIZE]. There + * can be only one NIX_SEND_JUMP_S subdescriptor in a send descriptor. If + * present, it must immediately follow NIX_SEND_HDR_S if NIX_SEND_EXT_S + * is not present, else it must immediately follow NIX_SEND_EXT_S. In + * either case, it must terminate the SQE enqueued by software. + */ +union nix_send_jump_s { + u64 u[2]; + struct nix_send_jump_s_s { + u64 sizem1 : 7; + u64 reserved_7_13 : 7; + u64 ld_type : 2; + u64 aura : 20; + u64 reserved_36_58 : 23; + u64 f : 1; + u64 subdc : 4; + u64 addr : 64; + } s; + /* struct nix_send_jump_s_s cn; */ +}; + +/** + * Structure nix_send_mem_s + * + * NIX Send Memory Subdescriptor Structure The send memory subdescriptor + * atomically sets, increments or decrements a memory location. + * NIX_SEND_MEM_S subdescriptors must follow all NIX_SEND_SG_S and + * NIX_SEND_IMM_S subdescriptors in the NIX send descriptor. NIX will not + * initiate the memory update for this subdescriptor until after it has + * completed all LLC/DRAM fetches that service all prior NIX_SEND_SG_S + * subdescriptors. The memory update is executed once, even if the packet + * is replicated due to NIX_TX_ACTION_S[OP] = NIX_TX_ACTIONOP_E::MCAST. + * Performance is best if a memory decrement by one is used rather than + * any other memory set/increment/decrement. (Less internal bus bandwidth + * is used with memory decrements by one.) When NIX_SEND_EXT_S[LSO] is + * set in the descriptor, NIX executes the memory update only while + * processing the last LSO segment, after processing prior segments. + */ +union nix_send_mem_s { + u64 u[2]; + struct nix_send_mem_s_s { + u64 offset : 16; + u64 reserved_16_52 : 37; + u64 wmem : 1; + u64 dsz : 2; + u64 alg : 4; + u64 subdc : 4; + u64 addr : 64; + } s; + /* struct nix_send_mem_s_s cn; */ +}; + +/** + * Structure nix_send_sg_s + * + * NIX Send Scatter/Gather Subdescriptor Structure The send + * scatter/gather subdescriptor requests one to three segments of packet + * data bytes to be transmitted. There may be multiple NIX_SEND_SG_Ss in + * each NIX send descriptor. NIX_SEND_SG_S is immediately followed by + * one NIX_IOVA_S word when [SEGS] = 1, three NIX_IOVA_S words when + * [SEGS] \>= 2. Each NIX_IOVA_S word specifies the LF IOVA of first + * packet data byte in the corresponding segment; first NIX_IOVA_S word + * for segment 1, second word for segment 2, third word for segment 3. + * Note the third word is present when [SEGS] \>= 2 but only valid when + * [SEGS] = 3. If the sum of all prior NIX_SEND_SG_S[SEG*_SIZE]s and + * NIX_SEND_IMM_S[SIZE]s meets or exceeds NIX_SEND_HDR_S[TOTAL], this + * subdescriptor will not contribute any packet data but may free buffers + * to NPA (see [I1]). + */ +union nix_send_sg_s { + u64 u; + struct nix_send_sg_s_s { + u64 seg1_size : 16; + u64 seg2_size : 16; + u64 seg3_size : 16; + u64 segs : 2; + u64 reserved_50_54 : 5; + u64 i1 : 1; + u64 i2 : 1; + u64 i3 : 1; + u64 ld_type : 2; + u64 subdc : 4; + } s; + /* struct nix_send_sg_s_s cn; */ +}; + +/** + * Structure nix_send_work_s + * + * NIX Send Work Subdescriptor Structure This subdescriptor adds work to + * the SSO. At most one NIX_SEND_WORK_S subdescriptor can exist in the + * NIX send descriptor. If a NIX_SEND_WORK_S exists in the descriptor, it + * must be the last subdescriptor. NIX will not initiate the work add for + * this subdescriptor until after (1) it has completed all LLC/DRAM + * fetches that service all prior NIX_SEND_SG_S subdescriptors, (2) it + * has fetched all subdescriptors in the descriptor, and (3) all + * NIX_SEND_MEM_S[WMEM]=1 LLC/DRAM updates have completed. Provided the + * path of descriptors from the SQ through NIX to an output FIFO is + * unmodified between the descriptors (as should normally be the case, + * but it is possible for software to change the path), NIX also (1) will + * submit the SSO add works from all descriptors in the SQ in order, and + * (2) will not submit an SSO work add until after all prior descriptors + * in the SQ have completed their NIX_SEND_SG_S processing, and (3) will + * not submit an SSO work add until after it has fetched all + * subdescriptors from prior descriptors in the SQ. When + * NIX_SEND_EXT_S[LSO] is set in the descriptor, NIX executes the + * NIX_SEND_WORK_S work add only while processing the last LSO segment, + * after processing prior segments. Hardware ignores NIX_SEND_WORK_S + * when NIX_SQ_CTX_S[SSO_ENA] is clear. + */ +union nix_send_work_s { + u64 u[2]; + struct nix_send_work_s_s { + u64 tag : 32; + u64 tt : 2; + u64 grp : 10; + u64 reserved_44_59 : 16; + u64 subdc : 4; + u64 addr : 64; + } s; + /* struct nix_send_work_s_s cn; */ +}; + +/** + * Structure nix_sq_ctx_hw_s + * + * NIX SQ Context Hardware Structure This structure contains context + * state maintained by hardware for each SQ in NDC/LLC/DRAM. Software + * uses the equivalent NIX_SQ_CTX_S structure format to read and write an + * SQ context with the NIX admin queue. Always stored in byte invariant + * little-endian format (LE8). + */ +union nix_sq_ctx_hw_s { + u64 u[16]; + struct nix_sq_ctx_hw_s_s { + u64 ena : 1; + u64 substream : 20; + u64 max_sqe_size : 2; + u64 sqe_way_mask : 16; + u64 sqb_aura : 20; + u64 gbl_rsvd1 : 5; + u64 cq_id : 20; + u64 cq_ena : 1; + u64 qint_idx : 6; + u64 gbl_rsvd2 : 1; + u64 sq_int : 8; + u64 sq_int_ena : 8; + u64 xoff : 1; + u64 sqe_stype : 2; + u64 gbl_rsvd : 17; + u64 head_sqb : 64; + u64 head_offset : 6; + u64 sqb_dequeue_count : 16; + u64 default_chan : 12; + u64 sdp_mcast : 1; + u64 sso_ena : 1; + u64 dse_rsvd1 : 28; + u64 sqb_enqueue_count : 16; + u64 tail_offset : 6; + u64 lmt_dis : 1; + u64 smq_rr_quantum : 24; + u64 dnq_rsvd1 : 17; + u64 tail_sqb : 64; + u64 next_sqb : 64; + u64 mnq_dis : 1; + u64 smq : 9; + u64 smq_pend : 1; + u64 smq_next_sq : 20; + u64 smq_next_sq_vld : 1; + u64 scm1_rsvd2 : 32; + u64 smenq_sqb : 64; + u64 smenq_offset : 6; + u64 cq_limit : 8; + u64 smq_rr_count : 25; + u64 scm_lso_rem : 18; + u64 scm_dq_rsvd0 : 7; + u64 smq_lso_segnum : 8; + u64 vfi_lso_total : 18; + u64 vfi_lso_sizem1 : 3; + u64 vfi_lso_sb : 8; + u64 vfi_lso_mps : 14; + u64 vfi_lso_vlan0_ins_ena : 1; + u64 vfi_lso_vlan1_ins_ena : 1; + u64 vfi_lso_vld : 1; + u64 smenq_next_sqb_vld : 1; + u64 scm_dq_rsvd1 : 9; + u64 smenq_next_sqb : 64; + u64 seb_rsvd1 : 64; + u64 drop_pkts : 48; + u64 drop_octs_lsw : 16; + u64 drop_octs_msw : 32; + u64 pkts_lsw : 32; + u64 pkts_msw : 16; + u64 octs : 48; + } s; + /* struct nix_sq_ctx_hw_s_s cn; */ +}; + +/** + * Structure nix_sq_ctx_s + * + * NIX Send Queue Context Structure This structure specifies the format + * used by software with the NIX admin queue to read and write a send + * queue's NIX_SQ_CTX_HW_S structure maintained by hardware in + * NDC/LLC/DRAM. The SQ statistics ([OCTS], [PKTS], [DROP_OCTS], + * [DROP_PKTS]) do not account for packet replication due to + * NIX_TX_ACTION_S[OP] = NIX_TX_ACTIONOP_E::MCAST. + */ +union nix_sq_ctx_s { + u64 u[16]; + struct nix_sq_ctx_s_s { + u64 ena : 1; + u64 qint_idx : 6; + u64 substream : 20; + u64 sdp_mcast : 1; + u64 cq : 20; + u64 sqe_way_mask : 16; + u64 smq : 9; + u64 cq_ena : 1; + u64 xoff : 1; + u64 sso_ena : 1; + u64 smq_rr_quantum : 24; + u64 default_chan : 12; + u64 sqb_count : 16; + u64 smq_rr_count : 25; + u64 sqb_aura : 20; + u64 sq_int : 8; + u64 sq_int_ena : 8; + u64 sqe_stype : 2; + u64 reserved_191 : 1; + u64 max_sqe_size : 2; + u64 cq_limit : 8; + u64 lmt_dis : 1; + u64 mnq_dis : 1; + u64 smq_next_sq : 20; + u64 smq_lso_segnum : 8; + u64 tail_offset : 6; + u64 smenq_offset : 6; + u64 head_offset : 6; + u64 smenq_next_sqb_vld : 1; + u64 smq_pend : 1; + u64 smq_next_sq_vld : 1; + u64 reserved_253_255 : 3; + u64 next_sqb : 64; + u64 tail_sqb : 64; + u64 smenq_sqb : 64; + u64 smenq_next_sqb : 64; + u64 head_sqb : 64; + u64 reserved_576_583 : 8; + u64 vfi_lso_total : 18; + u64 vfi_lso_sizem1 : 3; + u64 vfi_lso_sb : 8; + u64 vfi_lso_mps : 14; + u64 vfi_lso_vlan0_ins_ena : 1; + u64 vfi_lso_vlan1_ins_ena : 1; + u64 vfi_lso_vld : 1; + u64 reserved_630_639 : 10; + u64 scm_lso_rem : 18; + u64 reserved_658_703 : 46; + u64 octs : 48; + u64 reserved_752_767 : 16; + u64 pkts : 48; + u64 reserved_816_831 : 16; + u64 reserved_832_895 : 64; + u64 drop_octs : 48; + u64 reserved_944_959 : 16; + u64 drop_pkts : 48; + u64 reserved_1008_1023 : 16; + } s; + /* struct nix_sq_ctx_s_s cn; */ +}; + +/** + * Structure nix_tx_action_s + * + * NIX Transmit Action Structure This structure defines the format of + * NPC_RESULT_S[ACTION] for a transmit packet. + */ +union nix_tx_action_s { + u64 u; + struct nix_tx_action_s_s { + u64 op : 4; + u64 reserved_4_11 : 8; + u64 index : 20; + u64 match_id : 16; + u64 reserved_48_63 : 16; + } s; + /* struct nix_tx_action_s_s cn; */ +}; + +/** + * Structure nix_tx_vtag_action_s + * + * NIX Transmit Vtag Action Structure This structure defines the format + * of NPC_RESULT_S[VTAG_ACTION] for a transmit packet. It specifies the + * optional insertion or replacement of up to two Vtags (e.g. + * C-VLAN/S-VLAN tags, 802.1BR E-TAG). If two Vtags are specified: * The + * Vtag 0 byte offset from packet start (see [VTAG0_RELPTR]) must be less + * than or equal to the Vtag 1 byte offset. * Hardware executes the Vtag + * 0 action first, Vtag 1 action second. * If Vtag 0 is inserted, + * hardware adjusts the Vtag 1 byte offset accordingly. Thus, if the two + * offsets are equal in the structure, hardware inserts Vtag 1 + * immediately after Vtag 0 in the packet. A Vtag must not be inserted + * or replaced within an outer or inner L3/L4 header, but may be inserted + * or replaced within an outer L4 payload. + */ +union nix_tx_vtag_action_s { + u64 u; + struct nix_tx_vtag_action_s_s { + u64 vtag0_relptr : 8; + u64 vtag0_lid : 3; + u64 reserved_11 : 1; + u64 vtag0_op : 2; + u64 reserved_14_15 : 2; + u64 vtag0_def : 10; + u64 reserved_26_31 : 6; + u64 vtag1_relptr : 8; + u64 vtag1_lid : 3; + u64 reserved_43 : 1; + u64 vtag1_op : 2; + u64 reserved_46_47 : 2; + u64 vtag1_def : 10; + u64 reserved_58_63 : 6; + } s; + /* struct nix_tx_vtag_action_s_s cn; */ +}; + +/** + * Structure nix_wqe_hdr_s + * + * NIX Work Queue Entry Header Structure This 64-bit structure defines + * the first word of every receive WQE generated by NIX. It is + * immediately followed by NIX_RX_PARSE_S. Stored in memory as little- + * endian unless NIX_AF_LF()_CFG[BE] is set. + */ +union nix_wqe_hdr_s { + u64 u; + struct nix_wqe_hdr_s_s { + u64 tag : 32; + u64 tt : 2; + u64 grp : 10; + u64 node : 2; + u64 q : 14; + u64 wqe_type : 4; + } s; + /* struct nix_wqe_hdr_s_s cn; */ +}; + +/** + * Register (RVU_PF_BAR0) nix#_af_aq_base + * + * NIX AF Admin Queue Base Address Register + */ +union nixx_af_aq_base { + u64 u; + struct nixx_af_aq_base_s { + u64 reserved_0_6 : 7; + u64 base_addr : 46; + u64 reserved_53_63 : 11; + } s; + /* struct nixx_af_aq_base_s cn; */ +}; + +static inline u64 NIXX_AF_AQ_BASE(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_AQ_BASE(void) +{ + return 0x410; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_aq_cfg + * + * NIX AF Admin Queue Configuration Register + */ +union nixx_af_aq_cfg { + u64 u; + struct nixx_af_aq_cfg_s { + u64 qsize : 4; + u64 reserved_4_63 : 60; + } s; + /* struct nixx_af_aq_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_AQ_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_AQ_CFG(void) +{ + return 0x400; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_aq_done + * + * NIX AF Admin Queue Done Count Register + */ +union nixx_af_aq_done { + u64 u; + struct nixx_af_aq_done_s { + u64 done : 20; + u64 reserved_20_63 : 44; + } s; + /* struct nixx_af_aq_done_s cn; */ +}; + +static inline u64 NIXX_AF_AQ_DONE(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_AQ_DONE(void) +{ + return 0x450; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_aq_done_ack + * + * NIX AF Admin Queue Done Count Ack Register This register is written by + * software to acknowledge interrupts. + */ +union nixx_af_aq_done_ack { + u64 u; + struct nixx_af_aq_done_ack_s { + u64 done_ack : 20; + u64 reserved_20_63 : 44; + } s; + /* struct nixx_af_aq_done_ack_s cn; */ +}; + +static inline u64 NIXX_AF_AQ_DONE_ACK(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_AQ_DONE_ACK(void) +{ + return 0x460; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_aq_done_ena_w1c + * + * NIX AF Admin Queue Done Interrupt Enable Clear Register + */ +union nixx_af_aq_done_ena_w1c { + u64 u; + struct nixx_af_aq_done_ena_w1c_s { + u64 done : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_af_aq_done_ena_w1c_s cn; */ +}; + +static inline u64 NIXX_AF_AQ_DONE_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_AQ_DONE_ENA_W1C(void) +{ + return 0x498; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_aq_done_ena_w1s + * + * NIX AF Admin Queue Done Interrupt Enable Set Register + */ +union nixx_af_aq_done_ena_w1s { + u64 u; + struct nixx_af_aq_done_ena_w1s_s { + u64 done : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_af_aq_done_ena_w1s_s cn; */ +}; + +static inline u64 NIXX_AF_AQ_DONE_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_AQ_DONE_ENA_W1S(void) +{ + return 0x490; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_aq_done_int + * + * INTERNAL: NIX AF Admin Queue Done Interrupt Register + */ +union nixx_af_aq_done_int { + u64 u; + struct nixx_af_aq_done_int_s { + u64 done : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_af_aq_done_int_s cn; */ +}; + +static inline u64 NIXX_AF_AQ_DONE_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_AQ_DONE_INT(void) +{ + return 0x480; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_aq_done_int_w1s + * + * INTERNAL: NIX AF Admin Queue Done Interrupt Set Register + */ +union nixx_af_aq_done_int_w1s { + u64 u; + struct nixx_af_aq_done_int_w1s_s { + u64 done : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_af_aq_done_int_w1s_s cn; */ +}; + +static inline u64 NIXX_AF_AQ_DONE_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_AQ_DONE_INT_W1S(void) +{ + return 0x488; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_aq_done_timer + * + * NIX AF Admin Queue Done Interrupt Timer Register + */ +union nixx_af_aq_done_timer { + u64 u; + struct nixx_af_aq_done_timer_s { + u64 count : 16; + u64 reserved_16_63 : 48; + } s; + /* struct nixx_af_aq_done_timer_s cn; */ +}; + +static inline u64 NIXX_AF_AQ_DONE_TIMER(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_AQ_DONE_TIMER(void) +{ + return 0x470; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_aq_done_wait + * + * NIX AF Admin Queue Done Interrupt Coalescing Wait Register Specifies + * the queue interrupt coalescing settings. + */ +union nixx_af_aq_done_wait { + u64 u; + struct nixx_af_aq_done_wait_s { + u64 num_wait : 20; + u64 reserved_20_31 : 12; + u64 time_wait : 16; + u64 reserved_48_63 : 16; + } s; + /* struct nixx_af_aq_done_wait_s cn; */ +}; + +static inline u64 NIXX_AF_AQ_DONE_WAIT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_AQ_DONE_WAIT(void) +{ + return 0x440; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_aq_door + * + * NIX AF Admin Queue Doorbell Register Software writes to this register + * to enqueue entries to AQ. + */ +union nixx_af_aq_door { + u64 u; + struct nixx_af_aq_door_s { + u64 count : 16; + u64 reserved_16_63 : 48; + } s; + /* struct nixx_af_aq_door_s cn; */ +}; + +static inline u64 NIXX_AF_AQ_DOOR(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_AQ_DOOR(void) +{ + return 0x430; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_aq_status + * + * NIX AF Admin Queue Status Register + */ +union nixx_af_aq_status { + u64 u; + struct nixx_af_aq_status_s { + u64 reserved_0_3 : 4; + u64 head_ptr : 20; + u64 reserved_24_35 : 12; + u64 tail_ptr : 20; + u64 reserved_56_61 : 6; + u64 aq_busy : 1; + u64 aq_err : 1; + } s; + struct nixx_af_aq_status_cn { + u64 reserved_0_3 : 4; + u64 head_ptr : 20; + u64 reserved_24_31 : 8; + u64 reserved_32_35 : 4; + u64 tail_ptr : 20; + u64 reserved_56_61 : 6; + u64 aq_busy : 1; + u64 aq_err : 1; + } cn; +}; + +static inline u64 NIXX_AF_AQ_STATUS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_AQ_STATUS(void) +{ + return 0x420; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_avg_delay + * + * NIX AF Queue Average Delay Register + */ +union nixx_af_avg_delay { + u64 u; + struct nixx_af_avg_delay_s { + u64 avg_dly : 19; + u64 reserved_19_23 : 5; + u64 avg_timer : 16; + u64 reserved_40_63 : 24; + } s; + /* struct nixx_af_avg_delay_s cn; */ +}; + +static inline u64 NIXX_AF_AVG_DELAY(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_AVG_DELAY(void) +{ + return 0xe0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_bar2_alias# + * + * NIX Admin Function BAR2 Alias Registers These registers alias to the + * NIX BAR2 registers for the PF and function selected by + * NIX_AF_BAR2_SEL[PF_FUNC]. Internal: Not implemented. Placeholder for + * bug33464. + */ +union nixx_af_bar2_aliasx { + u64 u; + struct nixx_af_bar2_aliasx_s { + u64 data : 64; + } s; + /* struct nixx_af_bar2_aliasx_s cn; */ +}; + +static inline u64 NIXX_AF_BAR2_ALIASX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_BAR2_ALIASX(u64 a) +{ + return 0x9100000 + 8 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_bar2_sel + * + * NIX Admin Function BAR2 Select Register This register configures BAR2 + * accesses from the NIX_AF_BAR2_ALIAS() registers in BAR0. Internal: Not + * implemented. Placeholder for bug33464. + */ +union nixx_af_bar2_sel { + u64 u; + struct nixx_af_bar2_sel_s { + u64 alias_pf_func : 16; + u64 alias_ena : 1; + u64 reserved_17_63 : 47; + } s; + /* struct nixx_af_bar2_sel_s cn; */ +}; + +static inline u64 NIXX_AF_BAR2_SEL(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_BAR2_SEL(void) +{ + return 0x9000000; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_blk_rst + * + * NIX AF Block Reset Register + */ +union nixx_af_blk_rst { + u64 u; + struct nixx_af_blk_rst_s { + u64 rst : 1; + u64 reserved_1_62 : 62; + u64 busy : 1; + } s; + /* struct nixx_af_blk_rst_s cn; */ +}; + +static inline u64 NIXX_AF_BLK_RST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_BLK_RST(void) +{ + return 0xb0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_cfg + * + * NIX AF General Configuration Register + */ +union nixx_af_cfg { + u64 u; + struct nixx_af_cfg_s { + u64 force_cond_clk_en : 1; + u64 force_rx_gbl_clk_en : 1; + u64 force_rx_strm_clk_en : 1; + u64 force_cqm_clk_en : 1; + u64 force_seb_clk_en : 1; + u64 force_sqm_clk_en : 1; + u64 force_pse_clk_en : 1; + u64 reserved_7 : 1; + u64 af_be : 1; + u64 calibrate_x2p : 1; + u64 force_intf_clk_en : 1; + u64 reserved_11_63 : 53; + } s; + /* struct nixx_af_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_CFG(void) +{ + return 0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_cint_delay + * + * NIX AF Completion Interrupt Delay Register + */ +union nixx_af_cint_delay { + u64 u; + struct nixx_af_cint_delay_s { + u64 cint_dly : 10; + u64 reserved_10_15 : 6; + u64 cint_timer : 16; + u64 reserved_32_63 : 32; + } s; + /* struct nixx_af_cint_delay_s cn; */ +}; + +static inline u64 NIXX_AF_CINT_DELAY(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_CINT_DELAY(void) +{ + return 0xf0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_cint_timer# + * + * NIX AF Completion Interrupt Timer Registers + */ +union nixx_af_cint_timerx { + u64 u; + struct nixx_af_cint_timerx_s { + u64 expir_time : 16; + u64 cint : 7; + u64 reserved_23 : 1; + u64 lf : 8; + u64 active : 1; + u64 reserved_33_63 : 31; + } s; + /* struct nixx_af_cint_timerx_s cn; */ +}; + +static inline u64 NIXX_AF_CINT_TIMERX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_CINT_TIMERX(u64 a) +{ + return 0x1a40 + 0x40000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_const + * + * NIX AF Constants Register This register contains constants for + * software discovery. + */ +union nixx_af_const { + u64 u; + struct nixx_af_const_s { + u64 cgx_lmac_channels : 8; + u64 cgx_lmacs : 4; + u64 num_cgx : 4; + u64 lbk_channels : 8; + u64 num_lbk : 4; + u64 num_sdp : 4; + u64 reserved_32_47 : 16; + u64 links : 8; + u64 intfs : 4; + u64 reserved_60_63 : 4; + } s; + /* struct nixx_af_const_s cn; */ +}; + +static inline u64 NIXX_AF_CONST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_CONST(void) +{ + return 0x20; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_const1 + * + * NIX AF Constants 1 Register This register contains constants for + * software discovery. + */ +union nixx_af_const1 { + u64 u; + struct nixx_af_const1_s { + u64 sdp_channels : 12; + u64 rx_bpids : 12; + u64 lf_tx_stats : 8; + u64 lf_rx_stats : 8; + u64 lso_format_fields : 8; + u64 lso_formats : 8; + u64 reserved_56_63 : 8; + } s; + /* struct nixx_af_const1_s cn; */ +}; + +static inline u64 NIXX_AF_CONST1(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_CONST1(void) +{ + return 0x28; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_const2 + * + * NIX AF Constants 2 Register This register contains constants for + * software discovery. + */ +union nixx_af_const2 { + u64 u; + struct nixx_af_const2_s { + u64 lfs : 12; + u64 qints : 12; + u64 cints : 12; + u64 reserved_36_63 : 28; + } s; + /* struct nixx_af_const2_s cn; */ +}; + +static inline u64 NIXX_AF_CONST2(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_CONST2(void) +{ + return 0x30; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_const3 + * + * NIX AF Constants 2 Register This register contains constants for + * software discovery. + */ +union nixx_af_const3 { + u64 u; + struct nixx_af_const3_s { + u64 sq_ctx_log2bytes : 4; + u64 rq_ctx_log2bytes : 4; + u64 cq_ctx_log2bytes : 4; + u64 rsse_log2bytes : 4; + u64 mce_log2bytes : 4; + u64 qint_log2bytes : 4; + u64 cint_log2bytes : 4; + u64 dyno_log2bytes : 4; + u64 reserved_32_63 : 32; + } s; + /* struct nixx_af_const3_s cn; */ +}; + +static inline u64 NIXX_AF_CONST3(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_CONST3(void) +{ + return 0x38; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_cq_const + * + * NIX AF CQ Constants Register This register contains constants for + * software discovery. + */ +union nixx_af_cq_const { + u64 u; + struct nixx_af_cq_const_s { + u64 queues_per_lf : 24; + u64 reserved_24_63 : 40; + } s; + /* struct nixx_af_cq_const_s cn; */ +}; + +static inline u64 NIXX_AF_CQ_CONST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_CQ_CONST(void) +{ + return 0x48; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_cqm_bp_test + * + * INTERNAL: NIX AF CQM Backpressure Test Registers + */ +union nixx_af_cqm_bp_test { + u64 u; + struct nixx_af_cqm_bp_test_s { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 24; + u64 enable : 12; + u64 reserved_52_63 : 12; + } s; + /* struct nixx_af_cqm_bp_test_s cn; */ +}; + +static inline u64 NIXX_AF_CQM_BP_TEST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_CQM_BP_TEST(void) +{ + return 0x48c0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_cqm_eco + * + * INTERNAL: AF CQM ECO Register + */ +union nixx_af_cqm_eco { + u64 u; + struct nixx_af_cqm_eco_s { + u64 eco_rw : 64; + } s; + /* struct nixx_af_cqm_eco_s cn; */ +}; + +static inline u64 NIXX_AF_CQM_ECO(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_CQM_ECO(void) +{ + return 0x590; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_csi_eco + * + * INTERNAL: AF CSI ECO Register + */ +union nixx_af_csi_eco { + u64 u; + struct nixx_af_csi_eco_s { + u64 eco_rw : 64; + } s; + /* struct nixx_af_csi_eco_s cn; */ +}; + +static inline u64 NIXX_AF_CSI_ECO(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_CSI_ECO(void) +{ + return 0x580; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_err_int + * + * NIX Admin Function Error Interrupt Register + */ +union nixx_af_err_int { + u64 u; + struct nixx_af_err_int_s { + u64 rx_mcast_data_fault : 1; + u64 rx_mirror_data_fault : 1; + u64 rx_mcast_wqe_fault : 1; + u64 rx_mirror_wqe_fault : 1; + u64 rx_mce_fault : 1; + u64 rx_mce_list_err : 1; + u64 rx_unmapped_pf_func : 1; + u64 reserved_7_11 : 5; + u64 aq_door_err : 1; + u64 aq_res_fault : 1; + u64 aq_inst_fault : 1; + u64 reserved_15_63 : 49; + } s; + /* struct nixx_af_err_int_s cn; */ +}; + +static inline u64 NIXX_AF_ERR_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_ERR_INT(void) +{ + return 0x180; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_err_int_ena_w1c + * + * NIX Admin Function Error Interrupt Enable Clear Register This register + * clears interrupt enable bits. + */ +union nixx_af_err_int_ena_w1c { + u64 u; + struct nixx_af_err_int_ena_w1c_s { + u64 rx_mcast_data_fault : 1; + u64 rx_mirror_data_fault : 1; + u64 rx_mcast_wqe_fault : 1; + u64 rx_mirror_wqe_fault : 1; + u64 rx_mce_fault : 1; + u64 rx_mce_list_err : 1; + u64 rx_unmapped_pf_func : 1; + u64 reserved_7_11 : 5; + u64 aq_door_err : 1; + u64 aq_res_fault : 1; + u64 aq_inst_fault : 1; + u64 reserved_15_63 : 49; + } s; + /* struct nixx_af_err_int_ena_w1c_s cn; */ +}; + +static inline u64 NIXX_AF_ERR_INT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_ERR_INT_ENA_W1C(void) +{ + return 0x198; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_err_int_ena_w1s + * + * NIX Admin Function Error Interrupt Enable Set Register This register + * sets interrupt enable bits. + */ +union nixx_af_err_int_ena_w1s { + u64 u; + struct nixx_af_err_int_ena_w1s_s { + u64 rx_mcast_data_fault : 1; + u64 rx_mirror_data_fault : 1; + u64 rx_mcast_wqe_fault : 1; + u64 rx_mirror_wqe_fault : 1; + u64 rx_mce_fault : 1; + u64 rx_mce_list_err : 1; + u64 rx_unmapped_pf_func : 1; + u64 reserved_7_11 : 5; + u64 aq_door_err : 1; + u64 aq_res_fault : 1; + u64 aq_inst_fault : 1; + u64 reserved_15_63 : 49; + } s; + /* struct nixx_af_err_int_ena_w1s_s cn; */ +}; + +static inline u64 NIXX_AF_ERR_INT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_ERR_INT_ENA_W1S(void) +{ + return 0x190; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_err_int_w1s + * + * NIX Admin Function Error Interrupt Set Register This register sets + * interrupt bits. + */ +union nixx_af_err_int_w1s { + u64 u; + struct nixx_af_err_int_w1s_s { + u64 rx_mcast_data_fault : 1; + u64 rx_mirror_data_fault : 1; + u64 rx_mcast_wqe_fault : 1; + u64 rx_mirror_wqe_fault : 1; + u64 rx_mce_fault : 1; + u64 rx_mce_list_err : 1; + u64 rx_unmapped_pf_func : 1; + u64 reserved_7_11 : 5; + u64 aq_door_err : 1; + u64 aq_res_fault : 1; + u64 aq_inst_fault : 1; + u64 reserved_15_63 : 49; + } s; + /* struct nixx_af_err_int_w1s_s cn; */ +}; + +static inline u64 NIXX_AF_ERR_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_ERR_INT_W1S(void) +{ + return 0x188; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_expr_tx_fifo_status + * + * INTERNAL: NIX AF Express Transmit FIFO Status Register Internal: + * 802.3br frame preemption/express path is defeatured. Old definition: + * Status of FIFO which transmits express packets to CGX and LBK. + */ +union nixx_af_expr_tx_fifo_status { + u64 u; + struct nixx_af_expr_tx_fifo_status_s { + u64 count : 12; + u64 reserved_12_63 : 52; + } s; + /* struct nixx_af_expr_tx_fifo_status_s cn; */ +}; + +static inline u64 NIXX_AF_EXPR_TX_FIFO_STATUS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_EXPR_TX_FIFO_STATUS(void) +{ + return 0x640; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_gen_int + * + * NIX AF General Interrupt Register + */ +union nixx_af_gen_int { + u64 u; + struct nixx_af_gen_int_s { + u64 rx_mcast_drop : 1; + u64 rx_mirror_drop : 1; + u64 reserved_2 : 1; + u64 tl1_drain : 1; + u64 smq_flush_done : 1; + u64 reserved_5_63 : 59; + } s; + /* struct nixx_af_gen_int_s cn; */ +}; + +static inline u64 NIXX_AF_GEN_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_GEN_INT(void) +{ + return 0x160; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_gen_int_ena_w1c + * + * NIX AF General Interrupt Enable Clear Register This register clears + * interrupt enable bits. + */ +union nixx_af_gen_int_ena_w1c { + u64 u; + struct nixx_af_gen_int_ena_w1c_s { + u64 rx_mcast_drop : 1; + u64 rx_mirror_drop : 1; + u64 reserved_2 : 1; + u64 tl1_drain : 1; + u64 smq_flush_done : 1; + u64 reserved_5_63 : 59; + } s; + /* struct nixx_af_gen_int_ena_w1c_s cn; */ +}; + +static inline u64 NIXX_AF_GEN_INT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_GEN_INT_ENA_W1C(void) +{ + return 0x178; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_gen_int_ena_w1s + * + * NIX AF General Interrupt Enable Set Register This register sets + * interrupt enable bits. + */ +union nixx_af_gen_int_ena_w1s { + u64 u; + struct nixx_af_gen_int_ena_w1s_s { + u64 rx_mcast_drop : 1; + u64 rx_mirror_drop : 1; + u64 reserved_2 : 1; + u64 tl1_drain : 1; + u64 smq_flush_done : 1; + u64 reserved_5_63 : 59; + } s; + /* struct nixx_af_gen_int_ena_w1s_s cn; */ +}; + +static inline u64 NIXX_AF_GEN_INT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_GEN_INT_ENA_W1S(void) +{ + return 0x170; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_gen_int_w1s + * + * NIX AF General Interrupt Set Register This register sets interrupt + * bits. + */ +union nixx_af_gen_int_w1s { + u64 u; + struct nixx_af_gen_int_w1s_s { + u64 rx_mcast_drop : 1; + u64 rx_mirror_drop : 1; + u64 reserved_2 : 1; + u64 tl1_drain : 1; + u64 smq_flush_done : 1; + u64 reserved_5_63 : 59; + } s; + /* struct nixx_af_gen_int_w1s_s cn; */ +}; + +static inline u64 NIXX_AF_GEN_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_GEN_INT_W1S(void) +{ + return 0x168; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_cfg + * + * NIX AF Local Function Configuration Registers + */ +union nixx_af_lfx_cfg { + u64 u; + struct nixx_af_lfx_cfg_s { + u64 npa_pf_func : 16; + u64 sso_pf_func : 16; + u64 be : 1; + u64 xqe_size : 2; + u64 reserved_35_63 : 29; + } s; + /* struct nixx_af_lfx_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_CFG(u64 a) +{ + return 0x4000 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_cints_base + * + * NIX AF Local Function Completion Interrupts Base Address Registers + * This register specifies the base AF IOVA of LF's completion interrupt + * context table in NDC/LLC/DRAM. The table consists of + * NIX_AF_CONST2[CINTS] contiguous NIX_CINT_HW_S structures. After + * writing to this register, software should read it back to ensure that + * the write has completed before accessing any NIX_LF_CINT()_* + * registers. + */ +union nixx_af_lfx_cints_base { + u64 u; + struct nixx_af_lfx_cints_base_s { + u64 reserved_0_6 : 7; + u64 addr : 46; + u64 reserved_53_63 : 11; + } s; + /* struct nixx_af_lfx_cints_base_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_CINTS_BASE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_CINTS_BASE(u64 a) +{ + return 0x4130 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_cints_cfg + * + * NIX AF Local Function Completion Interrupts Configuration Registers + * This register controls access to the LF's completion interrupt context + * table in NDC/LLC/DRAM. The table consists of NIX_AF_CONST2[CINTS] + * contiguous NIX_CINT_HW_S structures. The size of each structure is 1 + * \<\< NIX_AF_CONST3[CINT_LOG2BYTES]. After writing to this register, + * software should read it back to ensure that the write has completed + * before accessing any NIX_LF_CINT()_* registers. + */ +union nixx_af_lfx_cints_cfg { + u64 u; + struct nixx_af_lfx_cints_cfg_s { + u64 reserved_0_19 : 20; + u64 way_mask : 16; + u64 caching : 1; + u64 reserved_37_63 : 27; + } s; + /* struct nixx_af_lfx_cints_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_CINTS_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_CINTS_CFG(u64 a) +{ + return 0x4120 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_cqs_base + * + * NIX AF Local Function Completion Queues Base Address Register This + * register specifies the base AF IOVA of the LF's CQ context table. The + * table consists of NIX_AF_LF()_CQS_CFG[MAX_QUEUESM1]+1 contiguous + * NIX_CQ_CTX_S structures. + */ +union nixx_af_lfx_cqs_base { + u64 u; + struct nixx_af_lfx_cqs_base_s { + u64 reserved_0_6 : 7; + u64 addr : 46; + u64 reserved_53_63 : 11; + } s; + /* struct nixx_af_lfx_cqs_base_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_CQS_BASE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_CQS_BASE(u64 a) +{ + return 0x4070 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_cqs_cfg + * + * NIX AF Local Function Completion Queues Configuration Register This + * register configures completion queues in the LF. + */ +union nixx_af_lfx_cqs_cfg { + u64 u; + struct nixx_af_lfx_cqs_cfg_s { + u64 max_queuesm1 : 20; + u64 way_mask : 16; + u64 caching : 1; + u64 reserved_37_63 : 27; + } s; + /* struct nixx_af_lfx_cqs_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_CQS_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_CQS_CFG(u64 a) +{ + return 0x4060 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_lock# + * + * NIX AF Local Function Lockdown Registers Internal: The NIX lockdown + * depth of 32 bytes is shallow compared to 96 bytes for NIC and meant + * for outer MAC and/or VLAN (optionally preceded by a small number of + * skip bytes). NPC's MCAM can be used for deeper protocol-aware + * lockdown. + */ +union nixx_af_lfx_lockx { + u64 u; + struct nixx_af_lfx_lockx_s { + u64 data : 32; + u64 bit_ena : 32; + } s; + /* struct nixx_af_lfx_lockx_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_LOCKX(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_LOCKX(u64 a, u64 b) +{ + return 0x4300 + 0x20000 * a + 8 * b; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_qints_base + * + * NIX AF Local Function Queue Interrupts Base Address Registers This + * register specifies the base AF IOVA of LF's queue interrupt context + * table in NDC/LLC/DRAM. The table consists of NIX_AF_CONST2[QINTS] + * contiguous NIX_QINT_HW_S structures. After writing to this register, + * software should read it back to ensure that the write has completed + * before accessing any NIX_LF_QINT()_* registers. + */ +union nixx_af_lfx_qints_base { + u64 u; + struct nixx_af_lfx_qints_base_s { + u64 reserved_0_6 : 7; + u64 addr : 46; + u64 reserved_53_63 : 11; + } s; + /* struct nixx_af_lfx_qints_base_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_QINTS_BASE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_QINTS_BASE(u64 a) +{ + return 0x4110 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_qints_cfg + * + * NIX AF Local Function Queue Interrupts Configuration Registers This + * register controls access to the LF's queue interrupt context table in + * NDC/LLC/DRAM. The table consists of NIX_AF_CONST2[QINTS] contiguous + * NIX_QINT_HW_S structures. The size of each structure is 1 \<\< + * NIX_AF_CONST3[QINT_LOG2BYTES]. After writing to this register, + * software should read it back to ensure that the write has completed + * before accessing any NIX_LF_QINT()_* registers. + */ +union nixx_af_lfx_qints_cfg { + u64 u; + struct nixx_af_lfx_qints_cfg_s { + u64 reserved_0_19 : 20; + u64 way_mask : 16; + u64 caching : 1; + u64 reserved_37_63 : 27; + } s; + /* struct nixx_af_lfx_qints_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_QINTS_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_QINTS_CFG(u64 a) +{ + return 0x4100 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_rqs_base + * + * NIX AF Local Function Receive Queues Base Address Register This + * register specifies the base AF IOVA of the LF's RQ context table. The + * table consists of NIX_AF_LF()_RQS_CFG[MAX_QUEUESM1]+1 contiguous + * NIX_RQ_CTX_S structures. + */ +union nixx_af_lfx_rqs_base { + u64 u; + struct nixx_af_lfx_rqs_base_s { + u64 reserved_0_6 : 7; + u64 addr : 46; + u64 reserved_53_63 : 11; + } s; + /* struct nixx_af_lfx_rqs_base_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_RQS_BASE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_RQS_BASE(u64 a) +{ + return 0x4050 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_rqs_cfg + * + * NIX AF Local Function Receive Queues Configuration Register This + * register configures receive queues in the LF. + */ +union nixx_af_lfx_rqs_cfg { + u64 u; + struct nixx_af_lfx_rqs_cfg_s { + u64 max_queuesm1 : 20; + u64 way_mask : 16; + u64 caching : 1; + u64 reserved_37_63 : 27; + } s; + /* struct nixx_af_lfx_rqs_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_RQS_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_RQS_CFG(u64 a) +{ + return 0x4040 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_rss_base + * + * NIX AF Local Function Receive Size Scaling Table Base Address Register + * This register specifies the base AF IOVA of the RSS table per LF. The + * table is present when NIX_AF_LF()_RSS_CFG[ENA] is set and consists of + * 1 \<\< (NIX_AF_LF()_RSS_CFG[SIZE] + 8) contiguous NIX_RSSE_S + * structures, where the size of each structure is 1 \<\< + * NIX_AF_CONST3[RSSE_LOG2BYTES]. See NIX_AF_LF()_RSS_GRP(). + */ +union nixx_af_lfx_rss_base { + u64 u; + struct nixx_af_lfx_rss_base_s { + u64 reserved_0_6 : 7; + u64 addr : 46; + u64 reserved_53_63 : 11; + } s; + /* struct nixx_af_lfx_rss_base_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_RSS_BASE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_RSS_BASE(u64 a) +{ + return 0x40d0 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_rss_cfg + * + * NIX AF Local Function Receive Size Scaling Table Configuration + * Register See NIX_AF_LF()_RSS_BASE and NIX_AF_LF()_RSS_GRP(). + */ +union nixx_af_lfx_rss_cfg { + u64 u; + struct nixx_af_lfx_rss_cfg_s { + u64 size : 4; + u64 ena : 1; + u64 adder_is_tag_lsb : 1; + u64 reserved_6_19 : 14; + u64 way_mask : 16; + u64 caching : 1; + u64 reserved_37_63 : 27; + } s; + struct nixx_af_lfx_rss_cfg_cn96xxp1 { + u64 size : 4; + u64 ena : 1; + u64 reserved_5_19 : 15; + u64 way_mask : 16; + u64 caching : 1; + u64 reserved_37_63 : 27; + } cn96xxp1; + /* struct nixx_af_lfx_rss_cfg_s cn96xxp3; */ + /* struct nixx_af_lfx_rss_cfg_cn96xxp1 cnf95xx; */ +}; + +static inline u64 NIXX_AF_LFX_RSS_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_RSS_CFG(u64 a) +{ + return 0x40c0 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_rss_grp# + * + * NIX AF Local Function Receive Side Scaling Group Registers A receive + * packet targets a LF's RSS group when its NIX_RX_ACTION_S[OP] = + * NIX_RX_ACTIONOP_E::RSS, or its target multicast list has an entry with + * NIX_RX_MCE_S[OP] = NIX_RX_MCOP_E::RSS. The RSS group index (this + * register's last index) is NIX_RX_ACTION_S[INDEX] or + * NIX_RX_MCE_S[INDEX]. The RSS computation is as follows: * The + * packet's flow_tag (see NIX_LF_RX_SECRET()) and RSS group are used to + * select a NIX_RSSE_S entry in the LF's RSS table (see [SIZEM1]). * + * NIX_RSSE_S selects the packet's destination RQ. + */ +union nixx_af_lfx_rss_grpx { + u64 u; + struct nixx_af_lfx_rss_grpx_s { + u64 offset : 11; + u64 reserved_11_15 : 5; + u64 sizem1 : 3; + u64 reserved_19_63 : 45; + } s; + /* struct nixx_af_lfx_rss_grpx_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_RSS_GRPX(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_RSS_GRPX(u64 a, u64 b) +{ + return 0x4600 + 0x20000 * a + 8 * b; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_rx_cfg + * + * NIX AF Local Function Receive Configuration Register + */ +union nixx_af_lfx_rx_cfg { + u64 u; + struct nixx_af_lfx_rx_cfg_s { + u64 reserved_0_31 : 32; + u64 drop_re : 1; + u64 lenerr_en : 1; + u64 ip6_udp_opt : 1; + u64 dis_apad : 1; + u64 csum_il4 : 1; + u64 csum_ol4 : 1; + u64 len_il4 : 1; + u64 len_il3 : 1; + u64 len_ol4 : 1; + u64 len_ol3 : 1; + u64 reserved_42_63 : 22; + } s; + struct nixx_af_lfx_rx_cfg_cn96xxp1 { + u64 reserved_0_31 : 32; + u64 reserved_32 : 1; + u64 lenerr_en : 1; + u64 ip6_udp_opt : 1; + u64 dis_apad : 1; + u64 csum_il4 : 1; + u64 csum_ol4 : 1; + u64 len_il4 : 1; + u64 len_il3 : 1; + u64 len_ol4 : 1; + u64 len_ol3 : 1; + u64 reserved_42_63 : 22; + } cn96xxp1; + /* struct nixx_af_lfx_rx_cfg_s cn96xxp3; */ + /* struct nixx_af_lfx_rx_cfg_s cnf95xx; */ +}; + +static inline u64 NIXX_AF_LFX_RX_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_RX_CFG(u64 a) +{ + return 0x40a0 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_cfg0 + * + * INTERNAL: NIX AF LF Receive IPSEC Configuration Registers Internal: + * Not used; no IPSEC fast-path. + */ +union nixx_af_lfx_rx_ipsec_cfg0 { + u64 u; + struct nixx_af_lfx_rx_ipsec_cfg0_s { + u64 lenm1_max : 14; + u64 reserved_14_15 : 2; + u64 sa_pow2_size : 4; + u64 tag_const : 24; + u64 tt : 2; + u64 defcpt : 1; + u64 hshcpt : 1; + u64 reserved_48_63 : 16; + } s; + /* struct nixx_af_lfx_rx_ipsec_cfg0_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_RX_IPSEC_CFG0(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_RX_IPSEC_CFG0(u64 a) +{ + return 0x4140 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_cfg1 + * + * INTERNAL: NIX AF LF Receive IPSEC Security Association Configuration + * Register Internal: Not used; no IPSEC fast-path. + */ +union nixx_af_lfx_rx_ipsec_cfg1 { + u64 u; + struct nixx_af_lfx_rx_ipsec_cfg1_s { + u64 sa_idx_max : 32; + u64 sa_idx_w : 5; + u64 reserved_37_63 : 27; + } s; + /* struct nixx_af_lfx_rx_ipsec_cfg1_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_RX_IPSEC_CFG1(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_RX_IPSEC_CFG1(u64 a) +{ + return 0x4148 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_dyno_base + * + * INTERNAL: NIX AF LF Receive IPSEC Dynamic Ordering Base Address + * Registers Internal: Not used; no IPSEC fast-path. + */ +union nixx_af_lfx_rx_ipsec_dyno_base { + u64 u; + struct nixx_af_lfx_rx_ipsec_dyno_base_s { + u64 reserved_0_6 : 7; + u64 addr : 46; + u64 reserved_53_63 : 11; + } s; + /* struct nixx_af_lfx_rx_ipsec_dyno_base_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_RX_IPSEC_DYNO_BASE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_RX_IPSEC_DYNO_BASE(u64 a) +{ + return 0x4158 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_dyno_cfg + * + * INTERNAL: NIX AF LF Receive IPSEC Dynamic Ordering Base Address + * Registers Internal: Not used; no IPSEC fast-path. + */ +union nixx_af_lfx_rx_ipsec_dyno_cfg { + u64 u; + struct nixx_af_lfx_rx_ipsec_dyno_cfg_s { + u64 dyno_idx_w : 4; + u64 dyno_ena : 1; + u64 reserved_5_19 : 15; + u64 way_mask : 16; + u64 caching : 1; + u64 reserved_37_63 : 27; + } s; + /* struct nixx_af_lfx_rx_ipsec_dyno_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_RX_IPSEC_DYNO_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_RX_IPSEC_DYNO_CFG(u64 a) +{ + return 0x4150 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_sa_base + * + * INTERNAL: NIX AF LF Receive IPSEC Security Association Base Address + * Register Internal: Not used; no IPSEC fast-path. + */ +union nixx_af_lfx_rx_ipsec_sa_base { + u64 u; + struct nixx_af_lfx_rx_ipsec_sa_base_s { + u64 reserved_0_6 : 7; + u64 addr : 46; + u64 reserved_53_63 : 11; + } s; + /* struct nixx_af_lfx_rx_ipsec_sa_base_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_RX_IPSEC_SA_BASE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_RX_IPSEC_SA_BASE(u64 a) +{ + return 0x4170 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_rx_stat# + * + * NIX AF Local Function Receive Statistics Registers The last dimension + * indicates which statistic, and is enumerated by NIX_STAT_LF_RX_E. + */ +union nixx_af_lfx_rx_statx { + u64 u; + struct nixx_af_lfx_rx_statx_s { + u64 stat : 48; + u64 reserved_48_63 : 16; + } s; + /* struct nixx_af_lfx_rx_statx_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_RX_STATX(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_RX_STATX(u64 a, u64 b) +{ + return 0x4500 + 0x20000 * a + 8 * b; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_rx_vtag_type# + * + * NIX AF Local Function Receive Vtag Type Registers These registers + * specify optional Vtag (e.g. VLAN, E-TAG) actions for received packets. + * Indexed by NIX_RX_VTAG_ACTION_S[VTAG*_TYPE]. + */ +union nixx_af_lfx_rx_vtag_typex { + u64 u; + struct nixx_af_lfx_rx_vtag_typex_s { + u64 size : 1; + u64 reserved_1_3 : 3; + u64 strip : 1; + u64 capture : 1; + u64 reserved_6_63 : 58; + } s; + /* struct nixx_af_lfx_rx_vtag_typex_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_RX_VTAG_TYPEX(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_RX_VTAG_TYPEX(u64 a, u64 b) +{ + return 0x4200 + 0x20000 * a + 8 * b; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_sqs_base + * + * NIX AF Local Function Send Queues Base Address Register This register + * specifies the base AF IOVA of the LF's SQ context table. The table + * consists of NIX_AF_LF()_SQS_CFG[MAX_QUEUESM1]+1 contiguous + * NIX_SQ_CTX_HW_S structures. + */ +union nixx_af_lfx_sqs_base { + u64 u; + struct nixx_af_lfx_sqs_base_s { + u64 reserved_0_6 : 7; + u64 addr : 46; + u64 reserved_53_63 : 11; + } s; + /* struct nixx_af_lfx_sqs_base_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_SQS_BASE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_SQS_BASE(u64 a) +{ + return 0x4030 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_sqs_cfg + * + * NIX AF Local Function Send Queues Configuration Register This register + * configures send queues in the LF. + */ +union nixx_af_lfx_sqs_cfg { + u64 u; + struct nixx_af_lfx_sqs_cfg_s { + u64 max_queuesm1 : 20; + u64 way_mask : 16; + u64 caching : 1; + u64 reserved_37_63 : 27; + } s; + /* struct nixx_af_lfx_sqs_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_SQS_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_SQS_CFG(u64 a) +{ + return 0x4020 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_tx_cfg + * + * NIX AF Local Function Transmit Configuration Register + */ +union nixx_af_lfx_tx_cfg { + u64 u; + struct nixx_af_lfx_tx_cfg_s { + u64 vlan0_ins_etype : 16; + u64 vlan1_ins_etype : 16; + u64 send_tstmp_ena : 1; + u64 lock_viol_cqe_ena : 1; + u64 lock_ena : 1; + u64 reserved_35_63 : 29; + } s; + /* struct nixx_af_lfx_tx_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_TX_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_TX_CFG(u64 a) +{ + return 0x4080 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_tx_cfg2 + * + * NIX AF Local Function Transmit Configuration Register + */ +union nixx_af_lfx_tx_cfg2 { + u64 u; + struct nixx_af_lfx_tx_cfg2_s { + u64 lmt_ena : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_af_lfx_tx_cfg2_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_TX_CFG2(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_TX_CFG2(u64 a) +{ + return 0x4028 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_tx_parse_cfg + * + * NIX AF Local Function Transmit Parse Configuration Register + */ +union nixx_af_lfx_tx_parse_cfg { + u64 u; + struct nixx_af_lfx_tx_parse_cfg_s { + u64 pkind : 6; + u64 reserved_6_63 : 58; + } s; + /* struct nixx_af_lfx_tx_parse_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_TX_PARSE_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_TX_PARSE_CFG(u64 a) +{ + return 0x4090 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_tx_stat# + * + * NIX AF Local Function Transmit Statistics Registers The last dimension + * indicates which statistic, and is enumerated by NIX_STAT_LF_TX_E. + */ +union nixx_af_lfx_tx_statx { + u64 u; + struct nixx_af_lfx_tx_statx_s { + u64 stat : 48; + u64 reserved_48_63 : 16; + } s; + /* struct nixx_af_lfx_tx_statx_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_TX_STATX(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_TX_STATX(u64 a, u64 b) +{ + return 0x4400 + 0x20000 * a + 8 * b; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf#_tx_status + * + * NIX AF LF Transmit Status Register + */ +union nixx_af_lfx_tx_status { + u64 u; + struct nixx_af_lfx_tx_status_s { + u64 sq_ctx_err : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_af_lfx_tx_status_s cn; */ +}; + +static inline u64 NIXX_AF_LFX_TX_STATUS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LFX_TX_STATUS(u64 a) +{ + return 0x4180 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lf_rst + * + * NIX Admin Function LF Reset Register + */ +union nixx_af_lf_rst { + u64 u; + struct nixx_af_lf_rst_s { + u64 lf : 8; + u64 reserved_8_11 : 4; + u64 exec : 1; + u64 reserved_13_63 : 51; + } s; + /* struct nixx_af_lf_rst_s cn; */ +}; + +static inline u64 NIXX_AF_LF_RST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LF_RST(void) +{ + return 0x150; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lso_cfg + * + * NIX AF Large Send Offload Configuration Register + */ +union nixx_af_lso_cfg { + u64 u; + struct nixx_af_lso_cfg_s { + u64 tcp_lsf : 16; + u64 tcp_msf : 16; + u64 tcp_fsf : 16; + u64 reserved_48_62 : 15; + u64 enable : 1; + } s; + /* struct nixx_af_lso_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_LSO_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LSO_CFG(void) +{ + return 0xa8; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_lso_format#_field# + * + * NIX AF Large Send Offload Format Field Registers These registers + * specify LSO packet modification formats. Each format may modify up to + * eight packet fields with the following constraints: * If fewer than + * eight fields are modified, [ALG] must be NIX_LSOALG_E::NOP in the + * unused field registers. * Modified fields must be specified in + * contiguous field registers starting with NIX_AF_LSO_FORMAT()_FIELD(0). + * * Modified fields cannot overlap. * Multiple fields with the same + * [LAYER] value must be specified in ascending [OFFSET] order. * Fields + * in different layers must be specified in ascending [LAYER] order. + */ +union nixx_af_lso_formatx_fieldx { + u64 u; + struct nixx_af_lso_formatx_fieldx_s { + u64 offset : 8; + u64 layer : 2; + u64 reserved_10_11 : 2; + u64 sizem1 : 2; + u64 reserved_14_15 : 2; + u64 alg : 3; + u64 reserved_19_63 : 45; + } s; + /* struct nixx_af_lso_formatx_fieldx_s cn; */ +}; + +static inline u64 NIXX_AF_LSO_FORMATX_FIELDX(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_LSO_FORMATX_FIELDX(u64 a, u64 b) +{ + return 0x1b00 + 0x10000 * a + 8 * b; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_mark_format#_ctl + * + * NIX AF Packet Marking Format Registers Describes packet marking + * calculations for YELLOW and for NIX_COLORRESULT_E::RED_SEND packets. + * NIX_SEND_EXT_S[MARKFORM] selects the CSR used for the packet + * descriptor. All the packet marking offset calculations assume big- + * endian bits within a byte. For example, if NIX_SEND_EXT_S[MARKPTR] is + * 3 and [OFFSET] is 5 and the packet is YELLOW, the NIX marking hardware + * would do this: _ byte[3]\<2:0\> |= [Y_VAL]\<3:1\> _ + * byte[3]\<2:0\> &= ~[Y_MASK]\<3:1\> _ byte[4]\<7\> |= [Y_VAL]\<0\> + * _ byte[4]\<7\> &= ~[Y_MASK]\<0\> where byte[3] is the third byte + * in the packet, and byte[4] the fourth. For another example, if + * NIX_SEND_EXT_S[MARKPTR] is 3 and [OFFSET] is 0 and the packet is + * NIX_COLORRESULT_E::RED_SEND, _ byte[3]\<7:4\> |= [R_VAL]\<3:0\> _ + * byte[3]\<7:4\> &= ~[R_MASK]\<3:0\> + */ +union nixx_af_mark_formatx_ctl { + u64 u; + struct nixx_af_mark_formatx_ctl_s { + u64 r_val : 4; + u64 r_mask : 4; + u64 y_val : 4; + u64 y_mask : 4; + u64 offset : 3; + u64 reserved_19_63 : 45; + } s; + /* struct nixx_af_mark_formatx_ctl_s cn; */ +}; + +static inline u64 NIXX_AF_MARK_FORMATX_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_MARK_FORMATX_CTL(u64 a) +{ + return 0x900 + 0x40000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_mc_mirror_const + * + * NIX AF Multicast/Mirror Constants Register This register contains + * constants for software discovery. + */ +union nixx_af_mc_mirror_const { + u64 u; + struct nixx_af_mc_mirror_const_s { + u64 buf_size : 16; + u64 reserved_16_63 : 48; + } s; + /* struct nixx_af_mc_mirror_const_s cn; */ +}; + +static inline u64 NIXX_AF_MC_MIRROR_CONST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_MC_MIRROR_CONST(void) +{ + return 0x98; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_mdq#_cir + * + * NIX AF Meta Descriptor Queue Committed Information Rate Registers This + * register has the same bit fields as NIX_AF_TL1()_CIR. + */ +union nixx_af_mdqx_cir { + u64 u; + struct nixx_af_mdqx_cir_s { + u64 enable : 1; + u64 rate_mantissa : 8; + u64 rate_exponent : 4; + u64 rate_divider_exponent : 4; + u64 reserved_17_28 : 12; + u64 burst_mantissa : 8; + u64 burst_exponent : 4; + u64 reserved_41_63 : 23; + } s; + /* struct nixx_af_mdqx_cir_s cn; */ +}; + +static inline u64 NIXX_AF_MDQX_CIR(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_MDQX_CIR(u64 a) +{ + return 0x1420 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_mdq#_md_debug + * + * NIX AF Meta Descriptor Queue Meta Descriptor State Debug Registers + * This register provides access to the meta descriptor at the front of + * the MDQ. An MDQ can hold up to 8 packet meta descriptors (PMD) and one + * flush meta descriptor (FMD). + */ +union nixx_af_mdqx_md_debug { + u64 u; + struct nixx_af_mdqx_md_debug_s { + u64 pkt_len : 16; + u64 red_algo_override : 2; + u64 shp_dis : 1; + u64 reserved_19 : 1; + u64 shp_chg : 9; + u64 reserved_29_31 : 3; + u64 sqm_pkt_id : 13; + u64 reserved_45_60 : 16; + u64 md_type : 2; + u64 reserved_63 : 1; + } s; + /* struct nixx_af_mdqx_md_debug_s cn; */ +}; + +static inline u64 NIXX_AF_MDQX_MD_DEBUG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_MDQX_MD_DEBUG(u64 a) +{ + return 0x14c0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_mdq#_parent + * + * NIX AF Meta Descriptor Queue Topology Registers + */ +union nixx_af_mdqx_parent { + u64 u; + struct nixx_af_mdqx_parent_s { + u64 reserved_0_15 : 16; + u64 parent : 9; + u64 reserved_25_63 : 39; + } s; + /* struct nixx_af_mdqx_parent_s cn; */ +}; + +static inline u64 NIXX_AF_MDQX_PARENT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_MDQX_PARENT(u64 a) +{ + return 0x1480 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_mdq#_pir + * + * NIX AF Meta Descriptor Queue Peak Information Rate Registers This + * register has the same bit fields as NIX_AF_TL1()_CIR. + */ +union nixx_af_mdqx_pir { + u64 u; + struct nixx_af_mdqx_pir_s { + u64 enable : 1; + u64 rate_mantissa : 8; + u64 rate_exponent : 4; + u64 rate_divider_exponent : 4; + u64 reserved_17_28 : 12; + u64 burst_mantissa : 8; + u64 burst_exponent : 4; + u64 reserved_41_63 : 23; + } s; + /* struct nixx_af_mdqx_pir_s cn; */ +}; + +static inline u64 NIXX_AF_MDQX_PIR(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_MDQX_PIR(u64 a) +{ + return 0x1430 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_mdq#_pointers + * + * INTERNAL: NIX AF Meta Descriptor 4 Linked List Pointers Debug Register + * This register has the same bit fields as NIX_AF_TL4()_POINTERS. + */ +union nixx_af_mdqx_pointers { + u64 u; + struct nixx_af_mdqx_pointers_s { + u64 next : 9; + u64 reserved_9_15 : 7; + u64 prev : 9; + u64 reserved_25_63 : 39; + } s; + /* struct nixx_af_mdqx_pointers_s cn; */ +}; + +static inline u64 NIXX_AF_MDQX_POINTERS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_MDQX_POINTERS(u64 a) +{ + return 0x1460 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_mdq#_ptr_fifo + * + * INTERNAL: NIX Meta Descriptor Queue Pointer FIFO State Debug Registers + */ +union nixx_af_mdqx_ptr_fifo { + u64 u; + struct nixx_af_mdqx_ptr_fifo_s { + u64 tail : 4; + u64 head : 4; + u64 p_con : 1; + u64 reserved_9_63 : 55; + } s; + /* struct nixx_af_mdqx_ptr_fifo_s cn; */ +}; + +static inline u64 NIXX_AF_MDQX_PTR_FIFO(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_MDQX_PTR_FIFO(u64 a) +{ + return 0x14d0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_mdq#_sched_state + * + * NIX AF Meta Descriptor Queue Scheduling Control State Registers This + * register has the same bit fields as NIX_AF_TL2()_SCHED_STATE. + */ +union nixx_af_mdqx_sched_state { + u64 u; + struct nixx_af_mdqx_sched_state_s { + u64 rr_count : 25; + u64 reserved_25_63 : 39; + } s; + /* struct nixx_af_mdqx_sched_state_s cn; */ +}; + +static inline u64 NIXX_AF_MDQX_SCHED_STATE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_MDQX_SCHED_STATE(u64 a) +{ + return 0x1440 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_mdq#_schedule + * + * NIX AF Meta Descriptor Queue Scheduling Control Registers This + * register has the same bit fields as NIX_AF_TL2()_SCHEDULE. + */ +union nixx_af_mdqx_schedule { + u64 u; + struct nixx_af_mdqx_schedule_s { + u64 rr_quantum : 24; + u64 prio : 4; + u64 reserved_28_63 : 36; + } s; + /* struct nixx_af_mdqx_schedule_s cn; */ +}; + +static inline u64 NIXX_AF_MDQX_SCHEDULE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_MDQX_SCHEDULE(u64 a) +{ + return 0x1400 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_mdq#_shape + * + * NIX AF Meta Descriptor Queue Shaping Control Registers This register + * has the same bit fields as NIX_AF_TL3()_SHAPE. + */ +union nixx_af_mdqx_shape { + u64 u; + struct nixx_af_mdqx_shape_s { + u64 adjust : 9; + u64 red_algo : 2; + u64 red_disable : 1; + u64 yellow_disable : 1; + u64 reserved_13_23 : 11; + u64 length_disable : 1; + u64 schedule_list : 2; + u64 reserved_27_63 : 37; + } s; + /* struct nixx_af_mdqx_shape_s cn; */ +}; + +static inline u64 NIXX_AF_MDQX_SHAPE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_MDQX_SHAPE(u64 a) +{ + return 0x1410 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_mdq#_shape_state + * + * NIX AF Meta Descriptor Queue Shaping State Registers This register has + * the same bit fields as NIX_AF_TL2()_SHAPE_STATE. This register must + * not be written during normal operation. + */ +union nixx_af_mdqx_shape_state { + u64 u; + struct nixx_af_mdqx_shape_state_s { + u64 cir_accum : 26; + u64 pir_accum : 26; + u64 color : 2; + u64 reserved_54_63 : 10; + } s; + /* struct nixx_af_mdqx_shape_state_s cn; */ +}; + +static inline u64 NIXX_AF_MDQX_SHAPE_STATE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_MDQX_SHAPE_STATE(u64 a) +{ + return 0x1450 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_mdq#_sw_xoff + * + * NIX AF Meta Descriptor Controlled XOFF Registers This register has the + * same bit fields as NIX_AF_TL1()_SW_XOFF + */ +union nixx_af_mdqx_sw_xoff { + u64 u; + struct nixx_af_mdqx_sw_xoff_s { + u64 xoff : 1; + u64 drain : 1; + u64 reserved_2 : 1; + u64 drain_irq : 1; + u64 reserved_4_63 : 60; + } s; + /* struct nixx_af_mdqx_sw_xoff_s cn; */ +}; + +static inline u64 NIXX_AF_MDQX_SW_XOFF(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_MDQX_SW_XOFF(u64 a) +{ + return 0x1470 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_mdq_const + * + * NIX AF Meta Descriptor Queue Constants Register This register contains + * constants for software discovery. + */ +union nixx_af_mdq_const { + u64 u; + struct nixx_af_mdq_const_s { + u64 count : 16; + u64 reserved_16_63 : 48; + } s; + /* struct nixx_af_mdq_const_s cn; */ +}; + +static inline u64 NIXX_AF_MDQ_CONST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_MDQ_CONST(void) +{ + return 0x90; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_ndc_cfg + * + * NIX AF General Configuration Register + */ +union nixx_af_ndc_cfg { + u64 u; + struct nixx_af_ndc_cfg_s { + u64 ndc_ign_pois : 1; + u64 byp_sq : 1; + u64 byp_sqb : 1; + u64 byp_cqs : 1; + u64 byp_cints : 1; + u64 byp_dyno : 1; + u64 byp_mce : 1; + u64 byp_rqc : 1; + u64 byp_rsse : 1; + u64 byp_mc_data : 1; + u64 byp_mc_wqe : 1; + u64 byp_mr_data : 1; + u64 byp_mr_wqe : 1; + u64 byp_qints : 1; + u64 reserved_14_63 : 50; + } s; + /* struct nixx_af_ndc_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_NDC_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_NDC_CFG(void) +{ + return 0x18; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_ndc_rx_sync + * + * NIX AF Receive NDC Sync Register Used to synchronize the NIX receive + * NDC (NDC_IDX_E::NIX()_RX). + */ +union nixx_af_ndc_rx_sync { + u64 u; + struct nixx_af_ndc_rx_sync_s { + u64 lf : 8; + u64 reserved_8_11 : 4; + u64 exec : 1; + u64 reserved_13_63 : 51; + } s; + /* struct nixx_af_ndc_rx_sync_s cn; */ +}; + +static inline u64 NIXX_AF_NDC_RX_SYNC(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_NDC_RX_SYNC(void) +{ + return 0x3e0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_ndc_tx_sync + * + * NIX AF NDC_TX Sync Register Used to synchronize the NIX transmit NDC + * (NDC_IDX_E::NIX()_TX). + */ +union nixx_af_ndc_tx_sync { + u64 u; + struct nixx_af_ndc_tx_sync_s { + u64 lf : 8; + u64 reserved_8_11 : 4; + u64 exec : 1; + u64 reserved_13_63 : 51; + } s; + /* struct nixx_af_ndc_tx_sync_s cn; */ +}; + +static inline u64 NIXX_AF_NDC_TX_SYNC(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_NDC_TX_SYNC(void) +{ + return 0x3f0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_norm_tx_fifo_status + * + * NIX AF Normal Transmit FIFO Status Register Status of FIFO which + * transmits normal packets to CGX and LBK. + */ +union nixx_af_norm_tx_fifo_status { + u64 u; + struct nixx_af_norm_tx_fifo_status_s { + u64 count : 12; + u64 reserved_12_63 : 52; + } s; + /* struct nixx_af_norm_tx_fifo_status_s cn; */ +}; + +static inline u64 NIXX_AF_NORM_TX_FIFO_STATUS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_NORM_TX_FIFO_STATUS(void) +{ + return 0x648; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pq#_dbg_arb_link_exp + * + * INTERNAL: NIX AF PQ Arb Link EXPRESS Debug Register + */ +union nixx_af_pqx_dbg_arb_link_exp { + u64 u; + struct nixx_af_pqx_dbg_arb_link_exp_s { + u64 req : 1; + u64 act_c_con : 1; + u64 cnt : 2; + u64 reserved_4_5 : 2; + u64 rr_mask : 1; + u64 reserved_7_63 : 57; + } s; + /* struct nixx_af_pqx_dbg_arb_link_exp_s cn; */ +}; + +static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_EXP(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_EXP(u64 a) +{ + return 0xce8 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pq#_dbg_arb_link_nrm + * + * INTERNAL: NIX AF PQ Arb Link NORMAL Debug Register + */ +union nixx_af_pqx_dbg_arb_link_nrm { + u64 u; + struct nixx_af_pqx_dbg_arb_link_nrm_s { + u64 req : 1; + u64 act_c_con : 1; + u64 cnt : 2; + u64 reserved_4_5 : 2; + u64 rr_mask : 1; + u64 reserved_7_63 : 57; + } s; + /* struct nixx_af_pqx_dbg_arb_link_nrm_s cn; */ +}; + +static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_NRM(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_NRM(u64 a) +{ + return 0xce0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pq#_dbg_arb_link_sdp + * + * INTERNAL: NIX AF PQ Arb Link SDP Debug Register + */ +union nixx_af_pqx_dbg_arb_link_sdp { + u64 u; + struct nixx_af_pqx_dbg_arb_link_sdp_s { + u64 req : 1; + u64 act_c_con : 1; + u64 cnt : 2; + u64 reserved_4_5 : 2; + u64 rr_mask : 1; + u64 reserved_7_63 : 57; + } s; + /* struct nixx_af_pqx_dbg_arb_link_sdp_s cn; */ +}; + +static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_SDP(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_SDP(u64 a) +{ + return 0xcf0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pq_arb_crd_rdy_debug + * + * INTERNAL: NIX AF PQ_ARB Node Credit Ready Registers NIX AF PQ ARB + * Credit ready register + */ +union nixx_af_pq_arb_crd_rdy_debug { + u64 u; + struct nixx_af_pq_arb_crd_rdy_debug_s { + u64 node_crd_rdy : 28; + u64 reserved_28_63 : 36; + } s; + /* struct nixx_af_pq_arb_crd_rdy_debug_s cn; */ +}; + +static inline u64 NIXX_AF_PQ_ARB_CRD_RDY_DEBUG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PQ_ARB_CRD_RDY_DEBUG(void) +{ + return 0xf10; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pq_arb_dwrr_msk_debug + * + * INTERNAL: NIX AF PQ_ARB DWRR mask set read only debug Registers + */ +union nixx_af_pq_arb_dwrr_msk_debug { + u64 u; + struct nixx_af_pq_arb_dwrr_msk_debug_s { + u64 node_dwrr_mask_set : 28; + u64 reserved_28_63 : 36; + } s; + /* struct nixx_af_pq_arb_dwrr_msk_debug_s cn; */ +}; + +static inline u64 NIXX_AF_PQ_ARB_DWRR_MSK_DEBUG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PQ_ARB_DWRR_MSK_DEBUG(void) +{ + return 0xf30; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pq_arb_node_gnt_debug + * + * INTERNAL: NIX AF PQ_ARB Node Grant vector Registers + */ +union nixx_af_pq_arb_node_gnt_debug { + u64 u; + struct nixx_af_pq_arb_node_gnt_debug_s { + u64 node_grant_vec : 28; + u64 reserved_28_63 : 36; + } s; + /* struct nixx_af_pq_arb_node_gnt_debug_s cn; */ +}; + +static inline u64 NIXX_AF_PQ_ARB_NODE_GNT_DEBUG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PQ_ARB_NODE_GNT_DEBUG(void) +{ + return 0xf20; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pq_arb_node_req_debug + * + * INTERNAL: NIX AF PQ_ARB Node Request Debug Registers NIX AF PQ ARB + * Node Request Debug register + */ +union nixx_af_pq_arb_node_req_debug { + u64 u; + struct nixx_af_pq_arb_node_req_debug_s { + u64 node_req : 28; + u64 reserved_28_63 : 36; + } s; + /* struct nixx_af_pq_arb_node_req_debug_s cn; */ +}; + +static inline u64 NIXX_AF_PQ_ARB_NODE_REQ_DEBUG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PQ_ARB_NODE_REQ_DEBUG(void) +{ + return 0xf00; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pq_arb_shape_vld_dbg + * + * INTERNAL: NIX AF PQ_ARB shape valid set Register + */ +union nixx_af_pq_arb_shape_vld_dbg { + u64 u; + struct nixx_af_pq_arb_shape_vld_dbg_s { + u64 node_shape_vld_set : 28; + u64 reserved_28_63 : 36; + } s; + /* struct nixx_af_pq_arb_shape_vld_dbg_s cn; */ +}; + +static inline u64 NIXX_AF_PQ_ARB_SHAPE_VLD_DBG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PQ_ARB_SHAPE_VLD_DBG(void) +{ + return 0xf40; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pq_dbg_arb_0 + * + * INTERNAL: NIX AF PQ Arb Debug 0 Register + */ +union nixx_af_pq_dbg_arb_0 { + u64 u; + struct nixx_af_pq_dbg_arb_0_s { + u64 rr_mask_clr : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_af_pq_dbg_arb_0_s cn; */ +}; + +static inline u64 NIXX_AF_PQ_DBG_ARB_0(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PQ_DBG_ARB_0(void) +{ + return 0xcf8; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pq_lnk_#_dwrr_msk_dbg + * + * INTERNAL: NIX AF PQ_ARB Physical Link DWRR MASK Registers + */ +union nixx_af_pq_lnk_x_dwrr_msk_dbg { + u64 u; + struct nixx_af_pq_lnk_x_dwrr_msk_dbg_s { + u64 link_dwrr_mask_set : 28; + u64 reserved_28_63 : 36; + } s; + /* struct nixx_af_pq_lnk_x_dwrr_msk_dbg_s cn; */ +}; + +static inline u64 NIXX_AF_PQ_LNK_X_DWRR_MSK_DBG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PQ_LNK_X_DWRR_MSK_DBG(u64 a) +{ + return 0x1100 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pse_400_rate_divider + * + * INTERNAL: NIX AF PSE 400 Rate Divider Register + */ +union nixx_af_pse_400_rate_divider { + u64 u; + struct nixx_af_pse_400_rate_divider_s { + u64 rate_div_cfg : 9; + u64 reserved_9_63 : 55; + } s; + /* struct nixx_af_pse_400_rate_divider_s cn; */ +}; + +static inline u64 NIXX_AF_PSE_400_RATE_DIVIDER(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PSE_400_RATE_DIVIDER(void) +{ + return 0x830; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pse_active_cycles_pc + * + * NIX AF Active Cycles Register These registers are indexed by the + * conditional clock domain number. + */ +union nixx_af_pse_active_cycles_pc { + u64 u; + struct nixx_af_pse_active_cycles_pc_s { + u64 act_cyc : 64; + } s; + /* struct nixx_af_pse_active_cycles_pc_s cn; */ +}; + +static inline u64 NIXX_AF_PSE_ACTIVE_CYCLES_PC(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PSE_ACTIVE_CYCLES_PC(void) +{ + return 0x8c0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pse_bp_test0 + * + * INTERNAL: NIX AF PSE Backpressure Test 0 Register + */ +union nixx_af_pse_bp_test0 { + u64 u; + struct nixx_af_pse_bp_test0_s { + u64 lfsr_freq : 12; + u64 reserved_12_63 : 52; + } s; + struct nixx_af_pse_bp_test0_cn96xxp1 { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 8; + u64 reserved_24_59 : 36; + u64 enable : 4; + } cn96xxp1; + struct nixx_af_pse_bp_test0_cn96xxp3 { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 reserved_16_19 : 4; + u64 bp_cfg : 12; + u64 reserved_32_55 : 24; + u64 reserved_56_57 : 2; + u64 enable : 6; + } cn96xxp3; + /* struct nixx_af_pse_bp_test0_cn96xxp1 cnf95xxp1; */ + struct nixx_af_pse_bp_test0_cnf95xxp2 { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 8; + u64 reserved_24_31 : 8; + u64 reserved_32_55 : 24; + u64 reserved_56_59 : 4; + u64 enable : 4; + } cnf95xxp2; +}; + +static inline u64 NIXX_AF_PSE_BP_TEST0(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PSE_BP_TEST0(void) +{ + return 0x840; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pse_bp_test1 + * + * INTERNAL: NIX AF PSE Backpressure Test 1 Register + */ +union nixx_af_pse_bp_test1 { + u64 u; + struct nixx_af_pse_bp_test1_s { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 10; + u64 reserved_26_63 : 38; + } s; + struct nixx_af_pse_bp_test1_cn96xxp1 { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 8; + u64 reserved_24_59 : 36; + u64 enable : 4; + } cn96xxp1; + struct nixx_af_pse_bp_test1_cn96xxp3 { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 10; + u64 reserved_26_31 : 6; + u64 reserved_32_55 : 24; + u64 reserved_56_58 : 3; + u64 enable : 5; + } cn96xxp3; + /* struct nixx_af_pse_bp_test1_cn96xxp1 cnf95xxp1; */ + struct nixx_af_pse_bp_test1_cnf95xxp2 { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 8; + u64 reserved_24_31 : 8; + u64 reserved_32_55 : 24; + u64 reserved_56_59 : 4; + u64 enable : 4; + } cnf95xxp2; +}; + +static inline u64 NIXX_AF_PSE_BP_TEST1(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PSE_BP_TEST1(void) +{ + return 0x850; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pse_bp_test2 + * + * INTERNAL: NIX AF PSE Backpressure Test 2 Register + */ +union nixx_af_pse_bp_test2 { + u64 u; + struct nixx_af_pse_bp_test2_s { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 10; + u64 reserved_26_63 : 38; + } s; + struct nixx_af_pse_bp_test2_cn96xxp1 { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 8; + u64 reserved_24_59 : 36; + u64 enable : 4; + } cn96xxp1; + struct nixx_af_pse_bp_test2_cn96xxp3 { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 10; + u64 reserved_26_31 : 6; + u64 reserved_32_55 : 24; + u64 reserved_56_58 : 3; + u64 enable : 5; + } cn96xxp3; + /* struct nixx_af_pse_bp_test2_cn96xxp1 cnf95xxp1; */ + struct nixx_af_pse_bp_test2_cnf95xxp2 { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 8; + u64 reserved_24_31 : 8; + u64 reserved_32_55 : 24; + u64 reserved_56_59 : 4; + u64 enable : 4; + } cnf95xxp2; +}; + +static inline u64 NIXX_AF_PSE_BP_TEST2(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PSE_BP_TEST2(void) +{ + return 0x860; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pse_bp_test3 + * + * INTERNAL: NIX AF PSE Backpressure Test 3 Register + */ +union nixx_af_pse_bp_test3 { + u64 u; + struct nixx_af_pse_bp_test3_s { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 10; + u64 reserved_26_63 : 38; + } s; + struct nixx_af_pse_bp_test3_cn96xxp1 { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 8; + u64 reserved_24_59 : 36; + u64 enable : 4; + } cn96xxp1; + struct nixx_af_pse_bp_test3_cn96xxp3 { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 10; + u64 reserved_26_31 : 6; + u64 reserved_32_55 : 24; + u64 reserved_56_58 : 3; + u64 enable : 5; + } cn96xxp3; + /* struct nixx_af_pse_bp_test3_cn96xxp1 cnf95xxp1; */ + struct nixx_af_pse_bp_test3_cnf95xxp2 { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 8; + u64 reserved_24_31 : 8; + u64 reserved_32_55 : 24; + u64 reserved_56_59 : 4; + u64 enable : 4; + } cnf95xxp2; +}; + +static inline u64 NIXX_AF_PSE_BP_TEST3(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PSE_BP_TEST3(void) +{ + return 0x870; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pse_channel_level + * + * NIX AF PSE Channel Level Register + */ +union nixx_af_pse_channel_level { + u64 u; + struct nixx_af_pse_channel_level_s { + u64 bp_level : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_af_pse_channel_level_s cn; */ +}; + +static inline u64 NIXX_AF_PSE_CHANNEL_LEVEL(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PSE_CHANNEL_LEVEL(void) +{ + return 0x800; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pse_const + * + * NIX AF PSE Constants Register This register contains constants for + * software discovery. + */ +union nixx_af_pse_const { + u64 u; + struct nixx_af_pse_const_s { + u64 levels : 4; + u64 reserved_4_7 : 4; + u64 mark_formats : 8; + u64 reserved_16_63 : 48; + } s; + /* struct nixx_af_pse_const_s cn; */ +}; + +static inline u64 NIXX_AF_PSE_CONST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PSE_CONST(void) +{ + return 0x60; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pse_eco + * + * INTERNAL: AF PSE ECO Register + */ +union nixx_af_pse_eco { + u64 u; + struct nixx_af_pse_eco_s { + u64 eco_rw : 64; + } s; + /* struct nixx_af_pse_eco_s cn; */ +}; + +static inline u64 NIXX_AF_PSE_ECO(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PSE_ECO(void) +{ + return 0x5d0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pse_expr_bp_test + * + * INTERNAL: NIX AF PSE Express Backpressure Test Register Internal: + * 802.3br frame preemption/express path is defeatured. + */ +union nixx_af_pse_expr_bp_test { + u64 u; + struct nixx_af_pse_expr_bp_test_s { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 32; + u64 enable : 16; + } s; + /* struct nixx_af_pse_expr_bp_test_s cn; */ +}; + +static inline u64 NIXX_AF_PSE_EXPR_BP_TEST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PSE_EXPR_BP_TEST(void) +{ + return 0x890; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pse_norm_bp_test + * + * INTERNAL: NIX AF PSE Normal Backpressure Test Register + */ +union nixx_af_pse_norm_bp_test { + u64 u; + struct nixx_af_pse_norm_bp_test_s { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 32; + u64 reserved_48_63 : 16; + } s; + struct nixx_af_pse_norm_bp_test_cn96xxp1 { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 32; + u64 enable : 16; + } cn96xxp1; + struct nixx_af_pse_norm_bp_test_cn96xxp3 { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 12; + u64 reserved_28_57 : 30; + u64 enable : 6; + } cn96xxp3; + /* struct nixx_af_pse_norm_bp_test_cn96xxp1 cnf95xx; */ +}; + +static inline u64 NIXX_AF_PSE_NORM_BP_TEST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PSE_NORM_BP_TEST(void) +{ + return 0x880; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_pse_shaper_cfg + * + * NIX AF PSE Shaper Configuration Register + */ +union nixx_af_pse_shaper_cfg { + u64 u; + struct nixx_af_pse_shaper_cfg_s { + u64 red_send_as_yellow : 1; + u64 color_aware : 1; + u64 reserved_2_63 : 62; + } s; + /* struct nixx_af_pse_shaper_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_PSE_SHAPER_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_PSE_SHAPER_CFG(void) +{ + return 0x810; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_ras + * + * NIX AF RAS Interrupt Register This register is intended for delivery + * of RAS events to the SCP, so should be ignored by OS drivers. + */ +union nixx_af_ras { + u64 u; + struct nixx_af_ras_s { + u64 rx_mce_poison : 1; + u64 rx_mcast_wqe_poison : 1; + u64 rx_mirror_wqe_poison : 1; + u64 rx_mcast_data_poison : 1; + u64 rx_mirror_data_poison : 1; + u64 reserved_5_31 : 27; + u64 aq_ctx_poison : 1; + u64 aq_res_poison : 1; + u64 aq_inst_poison : 1; + u64 reserved_35_63 : 29; + } s; + /* struct nixx_af_ras_s cn; */ +}; + +static inline u64 NIXX_AF_RAS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RAS(void) +{ + return 0x1a0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_ras_ena_w1c + * + * NIX AF RAS Interrupt Enable Clear Register This register clears + * interrupt enable bits. + */ +union nixx_af_ras_ena_w1c { + u64 u; + struct nixx_af_ras_ena_w1c_s { + u64 rx_mce_poison : 1; + u64 rx_mcast_wqe_poison : 1; + u64 rx_mirror_wqe_poison : 1; + u64 rx_mcast_data_poison : 1; + u64 rx_mirror_data_poison : 1; + u64 reserved_5_31 : 27; + u64 aq_ctx_poison : 1; + u64 aq_res_poison : 1; + u64 aq_inst_poison : 1; + u64 reserved_35_63 : 29; + } s; + /* struct nixx_af_ras_ena_w1c_s cn; */ +}; + +static inline u64 NIXX_AF_RAS_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RAS_ENA_W1C(void) +{ + return 0x1b8; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_ras_ena_w1s + * + * NIX AF RAS Interrupt Enable Set Register This register sets interrupt + * enable bits. + */ +union nixx_af_ras_ena_w1s { + u64 u; + struct nixx_af_ras_ena_w1s_s { + u64 rx_mce_poison : 1; + u64 rx_mcast_wqe_poison : 1; + u64 rx_mirror_wqe_poison : 1; + u64 rx_mcast_data_poison : 1; + u64 rx_mirror_data_poison : 1; + u64 reserved_5_31 : 27; + u64 aq_ctx_poison : 1; + u64 aq_res_poison : 1; + u64 aq_inst_poison : 1; + u64 reserved_35_63 : 29; + } s; + /* struct nixx_af_ras_ena_w1s_s cn; */ +}; + +static inline u64 NIXX_AF_RAS_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RAS_ENA_W1S(void) +{ + return 0x1b0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_ras_w1s + * + * NIX AF RAS Interrupt Set Register This register sets interrupt bits. + */ +union nixx_af_ras_w1s { + u64 u; + struct nixx_af_ras_w1s_s { + u64 rx_mce_poison : 1; + u64 rx_mcast_wqe_poison : 1; + u64 rx_mirror_wqe_poison : 1; + u64 rx_mcast_data_poison : 1; + u64 rx_mirror_data_poison : 1; + u64 reserved_5_31 : 27; + u64 aq_ctx_poison : 1; + u64 aq_res_poison : 1; + u64 aq_inst_poison : 1; + u64 reserved_35_63 : 29; + } s; + /* struct nixx_af_ras_w1s_s cn; */ +}; + +static inline u64 NIXX_AF_RAS_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RAS_W1S(void) +{ + return 0x1a8; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_reb_bp_test# + * + * INTERNAL: NIX AF REB Backpressure Test Registers + */ +union nixx_af_reb_bp_testx { + u64 u; + struct nixx_af_reb_bp_testx_s { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 8; + u64 reserved_24_47 : 24; + u64 enable : 4; + u64 reserved_52_63 : 12; + } s; + /* struct nixx_af_reb_bp_testx_s cn; */ +}; + +static inline u64 NIXX_AF_REB_BP_TESTX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_REB_BP_TESTX(u64 a) +{ + return 0x4840 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rq_const + * + * NIX AF RQ Constants Register This register contains constants for + * software discovery. + */ +union nixx_af_rq_const { + u64 u; + struct nixx_af_rq_const_s { + u64 queues_per_lf : 24; + u64 reserved_24_63 : 40; + } s; + /* struct nixx_af_rq_const_s cn; */ +}; + +static inline u64 NIXX_AF_RQ_CONST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RQ_CONST(void) +{ + return 0x50; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rqm_bp_test + * + * INTERNAL: NIX AF REB Backpressure Test Registers + */ +union nixx_af_rqm_bp_test { + u64 u; + struct nixx_af_rqm_bp_test_s { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 16; + u64 reserved_32_47 : 16; + u64 enable : 8; + u64 reserved_56_63 : 8; + } s; + /* struct nixx_af_rqm_bp_test_s cn; */ +}; + +static inline u64 NIXX_AF_RQM_BP_TEST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RQM_BP_TEST(void) +{ + return 0x4880; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rqm_eco + * + * INTERNAL: AF RQM ECO Register + */ +union nixx_af_rqm_eco { + u64 u; + struct nixx_af_rqm_eco_s { + u64 eco_rw : 64; + } s; + /* struct nixx_af_rqm_eco_s cn; */ +}; + +static inline u64 NIXX_AF_RQM_ECO(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RQM_ECO(void) +{ + return 0x5a0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rvu_int + * + * NIX AF RVU Interrupt Register This register contains RVU error + * interrupt summary bits. + */ +union nixx_af_rvu_int { + u64 u; + struct nixx_af_rvu_int_s { + u64 unmapped_slot : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_af_rvu_int_s cn; */ +}; + +static inline u64 NIXX_AF_RVU_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RVU_INT(void) +{ + return 0x1c0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rvu_int_ena_w1c + * + * NIX AF RVU Interrupt Enable Clear Register This register clears + * interrupt enable bits. + */ +union nixx_af_rvu_int_ena_w1c { + u64 u; + struct nixx_af_rvu_int_ena_w1c_s { + u64 unmapped_slot : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_af_rvu_int_ena_w1c_s cn; */ +}; + +static inline u64 NIXX_AF_RVU_INT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RVU_INT_ENA_W1C(void) +{ + return 0x1d8; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rvu_int_ena_w1s + * + * NIX AF RVU Interrupt Enable Set Register This register sets interrupt + * enable bits. + */ +union nixx_af_rvu_int_ena_w1s { + u64 u; + struct nixx_af_rvu_int_ena_w1s_s { + u64 unmapped_slot : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_af_rvu_int_ena_w1s_s cn; */ +}; + +static inline u64 NIXX_AF_RVU_INT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RVU_INT_ENA_W1S(void) +{ + return 0x1d0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rvu_int_w1s + * + * NIX AF RVU Interrupt Set Register This register sets interrupt bits. + */ +union nixx_af_rvu_int_w1s { + u64 u; + struct nixx_af_rvu_int_w1s_s { + u64 unmapped_slot : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_af_rvu_int_w1s_s cn; */ +}; + +static inline u64 NIXX_AF_RVU_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RVU_INT_W1S(void) +{ + return 0x1c8; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rvu_lf_cfg_debug + * + * NIX Privileged LF Configuration Debug Register This debug register + * allows software to lookup the reverse mapping from VF/PF slot to LF. + * The forward mapping is programmed with NIX_PRIV_LF()_CFG. + */ +union nixx_af_rvu_lf_cfg_debug { + u64 u; + struct nixx_af_rvu_lf_cfg_debug_s { + u64 lf : 12; + u64 lf_valid : 1; + u64 exec : 1; + u64 reserved_14_15 : 2; + u64 slot : 8; + u64 pf_func : 16; + u64 reserved_40_63 : 24; + } s; + /* struct nixx_af_rvu_lf_cfg_debug_s cn; */ +}; + +static inline u64 NIXX_AF_RVU_LF_CFG_DEBUG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RVU_LF_CFG_DEBUG(void) +{ + return 0x8000030; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_active_cycles_pc# + * + * NIX AF Active Cycles Register These registers are indexed by the + * conditional clock domain number. + */ +union nixx_af_rx_active_cycles_pcx { + u64 u; + struct nixx_af_rx_active_cycles_pcx_s { + u64 act_cyc : 64; + } s; + /* struct nixx_af_rx_active_cycles_pcx_s cn; */ +}; + +static inline u64 NIXX_AF_RX_ACTIVE_CYCLES_PCX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_ACTIVE_CYCLES_PCX(u64 a) +{ + return 0x4800 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_bpid#_status + * + * NIX AF Receive Backpressure ID Status Registers + */ +union nixx_af_rx_bpidx_status { + u64 u; + struct nixx_af_rx_bpidx_status_s { + u64 aura_cnt : 32; + u64 cq_cnt : 32; + } s; + /* struct nixx_af_rx_bpidx_status_s cn; */ +}; + +static inline u64 NIXX_AF_RX_BPIDX_STATUS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_BPIDX_STATUS(u64 a) +{ + return 0x1a20 + 0x20000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_cfg + * + * NIX AF Receive Configuration Register + */ +union nixx_af_rx_cfg { + u64 u; + struct nixx_af_rx_cfg_s { + u64 cbp_ena : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_af_rx_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_RX_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_CFG(void) +{ + return 0xd0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_chan#_cfg + * + * NIX AF Receive Channel Configuration Registers + */ +union nixx_af_rx_chanx_cfg { + u64 u; + struct nixx_af_rx_chanx_cfg_s { + u64 bpid : 9; + u64 reserved_9_15 : 7; + u64 bp_ena : 1; + u64 sw_xoff : 1; + u64 imp : 1; + u64 reserved_19_63 : 45; + } s; + /* struct nixx_af_rx_chanx_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_RX_CHANX_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_CHANX_CFG(u64 a) +{ + return 0x1a30 + 0x8000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_cpt#_credit + * + * INTERNAL: NIX AF Receive CPT Credit Register Internal: Not used; no + * IPSEC fast-path. + */ +union nixx_af_rx_cptx_credit { + u64 u; + struct nixx_af_rx_cptx_credit_s { + u64 inst_cred_cnt : 22; + u64 reserved_22_63 : 42; + } s; + /* struct nixx_af_rx_cptx_credit_s cn; */ +}; + +static inline u64 NIXX_AF_RX_CPTX_CREDIT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_CPTX_CREDIT(u64 a) +{ + return 0x360 + 8 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_cpt#_inst_qsel + * + * INTERNAL: NIX AF Receive CPT Instruction Queue Select Register + * Internal: Not used; no IPSEC fast-path. + */ +union nixx_af_rx_cptx_inst_qsel { + u64 u; + struct nixx_af_rx_cptx_inst_qsel_s { + u64 slot : 8; + u64 pf_func : 16; + u64 reserved_24_63 : 40; + } s; + /* struct nixx_af_rx_cptx_inst_qsel_s cn; */ +}; + +static inline u64 NIXX_AF_RX_CPTX_INST_QSEL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_CPTX_INST_QSEL(u64 a) +{ + return 0x320 + 8 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_def_iip4 + * + * NIX AF Receive Inner IPv4 Header Definition Register Defines layer + * information in NPC_RESULT_S to identify an inner IPv4 header. + * Typically the same as NPC_AF_PCK_DEF_IIP4. + */ +union nixx_af_rx_def_iip4 { + u64 u; + struct nixx_af_rx_def_iip4_s { + u64 ltype_mask : 4; + u64 ltype_match : 4; + u64 lid : 3; + u64 reserved_11_63 : 53; + } s; + /* struct nixx_af_rx_def_iip4_s cn; */ +}; + +static inline u64 NIXX_AF_RX_DEF_IIP4(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_DEF_IIP4(void) +{ + return 0x220; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_def_iip6 + * + * NIX AF Receive Inner IPv6 Header Definition Register Defines layer + * information in NPC_RESULT_S to identify an inner IPv6 header. + */ +union nixx_af_rx_def_iip6 { + u64 u; + struct nixx_af_rx_def_iip6_s { + u64 ltype_mask : 4; + u64 ltype_match : 4; + u64 lid : 3; + u64 reserved_11_63 : 53; + } s; + /* struct nixx_af_rx_def_iip6_s cn; */ +}; + +static inline u64 NIXX_AF_RX_DEF_IIP6(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_DEF_IIP6(void) +{ + return 0x240; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_def_ipsec# + * + * INTERNAL: NIX AF Receive IPSEC Header Definition Registers Internal: + * Not used; no IPSEC fast-path. + */ +union nixx_af_rx_def_ipsecx { + u64 u; + struct nixx_af_rx_def_ipsecx_s { + u64 ltype_mask : 4; + u64 ltype_match : 4; + u64 lid : 3; + u64 reserved_11 : 1; + u64 spi_offset : 4; + u64 spi_nz : 1; + u64 reserved_17_63 : 47; + } s; + /* struct nixx_af_rx_def_ipsecx_s cn; */ +}; + +static inline u64 NIXX_AF_RX_DEF_IPSECX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_DEF_IPSECX(u64 a) +{ + return 0x2b0 + 8 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_def_isctp + * + * NIX AF Receive Inner SCTP Header Definition Register Defines layer + * information in NPC_RESULT_S to identify an inner SCTP header. + */ +union nixx_af_rx_def_isctp { + u64 u; + struct nixx_af_rx_def_isctp_s { + u64 ltype_mask : 4; + u64 ltype_match : 4; + u64 lid : 3; + u64 reserved_11_63 : 53; + } s; + /* struct nixx_af_rx_def_isctp_s cn; */ +}; + +static inline u64 NIXX_AF_RX_DEF_ISCTP(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_DEF_ISCTP(void) +{ + return 0x2a0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_def_itcp + * + * NIX AF Receive Inner TCP Header Definition Register Defines layer + * information in NPC_RESULT_S to identify an inner TCP header. + */ +union nixx_af_rx_def_itcp { + u64 u; + struct nixx_af_rx_def_itcp_s { + u64 ltype_mask : 4; + u64 ltype_match : 4; + u64 lid : 3; + u64 reserved_11_63 : 53; + } s; + /* struct nixx_af_rx_def_itcp_s cn; */ +}; + +static inline u64 NIXX_AF_RX_DEF_ITCP(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_DEF_ITCP(void) +{ + return 0x260; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_def_iudp + * + * NIX AF Receive Inner UDP Header Definition Register Defines layer + * information in NPC_RESULT_S to identify an inner UDP header. + */ +union nixx_af_rx_def_iudp { + u64 u; + struct nixx_af_rx_def_iudp_s { + u64 ltype_mask : 4; + u64 ltype_match : 4; + u64 lid : 3; + u64 reserved_11_63 : 53; + } s; + /* struct nixx_af_rx_def_iudp_s cn; */ +}; + +static inline u64 NIXX_AF_RX_DEF_IUDP(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_DEF_IUDP(void) +{ + return 0x280; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_def_oip4 + * + * NIX AF Receive Outer IPv4 Header Definition Register Defines layer + * information in NPC_RESULT_S to identify an outer IPv4 L3 header. + * Typically the same as NPC_AF_PCK_DEF_OIP4. + */ +union nixx_af_rx_def_oip4 { + u64 u; + struct nixx_af_rx_def_oip4_s { + u64 ltype_mask : 4; + u64 ltype_match : 4; + u64 lid : 3; + u64 reserved_11_63 : 53; + } s; + /* struct nixx_af_rx_def_oip4_s cn; */ +}; + +static inline u64 NIXX_AF_RX_DEF_OIP4(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_DEF_OIP4(void) +{ + return 0x210; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_def_oip6 + * + * NIX AF Receive Outer IPv6 Header Definition Register Defines layer + * information in NPC_RESULT_S to identify an outer IPv6 header. + * Typically the same as NPC_AF_PCK_DEF_OIP6. + */ +union nixx_af_rx_def_oip6 { + u64 u; + struct nixx_af_rx_def_oip6_s { + u64 ltype_mask : 4; + u64 ltype_match : 4; + u64 lid : 3; + u64 reserved_11_63 : 53; + } s; + /* struct nixx_af_rx_def_oip6_s cn; */ +}; + +static inline u64 NIXX_AF_RX_DEF_OIP6(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_DEF_OIP6(void) +{ + return 0x230; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_def_ol2 + * + * NIX AF Receive Outer L2 Header Definition Register Defines layer + * information in NPC_RESULT_S to identify an outer L2/Ethernet header. + * Typically the same as NPC_AF_PCK_DEF_OL2. + */ +union nixx_af_rx_def_ol2 { + u64 u; + struct nixx_af_rx_def_ol2_s { + u64 ltype_mask : 4; + u64 ltype_match : 4; + u64 lid : 3; + u64 reserved_11_63 : 53; + } s; + /* struct nixx_af_rx_def_ol2_s cn; */ +}; + +static inline u64 NIXX_AF_RX_DEF_OL2(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_DEF_OL2(void) +{ + return 0x200; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_def_osctp + * + * NIX AF Receive Outer SCTP Header Definition Register Defines layer + * information in NPC_RESULT_S to identify an outer SCTP header. + */ +union nixx_af_rx_def_osctp { + u64 u; + struct nixx_af_rx_def_osctp_s { + u64 ltype_mask : 4; + u64 ltype_match : 4; + u64 lid : 3; + u64 reserved_11_63 : 53; + } s; + /* struct nixx_af_rx_def_osctp_s cn; */ +}; + +static inline u64 NIXX_AF_RX_DEF_OSCTP(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_DEF_OSCTP(void) +{ + return 0x290; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_def_otcp + * + * NIX AF Receive Outer TCP Header Definition Register Defines layer + * information in NPC_RESULT_S to identify an outer TCP header. + */ +union nixx_af_rx_def_otcp { + u64 u; + struct nixx_af_rx_def_otcp_s { + u64 ltype_mask : 4; + u64 ltype_match : 4; + u64 lid : 3; + u64 reserved_11_63 : 53; + } s; + /* struct nixx_af_rx_def_otcp_s cn; */ +}; + +static inline u64 NIXX_AF_RX_DEF_OTCP(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_DEF_OTCP(void) +{ + return 0x250; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_def_oudp + * + * NIX AF Receive Outer UDP Header Definition Register Defines layer + * information in NPC_RESULT_S to identify an outer UDP header. + */ +union nixx_af_rx_def_oudp { + u64 u; + struct nixx_af_rx_def_oudp_s { + u64 ltype_mask : 4; + u64 ltype_match : 4; + u64 lid : 3; + u64 reserved_11_63 : 53; + } s; + /* struct nixx_af_rx_def_oudp_s cn; */ +}; + +static inline u64 NIXX_AF_RX_DEF_OUDP(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_DEF_OUDP(void) +{ + return 0x270; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_flow_key_alg#_field# + * + * NIX AF Receive Flow Key Algorithm Field Registers A flow key algorithm + * defines how the 40-byte FLOW_KEY is formed from the received packet + * header. FLOW_KEY is formed using up to five header fields (this + * register's last index) with up to 16 bytes per field. Header fields + * must not overlap in FLOW_KEY. The algorithm (index {a} (ALG) of these + * registers) is selected by NIX_RX_ACTION_S[FLOW_KEY_ALG] from the + * packet's NPC_RESULT_S[ACTION]. Internal: 40-byte FLOW_KEY is wide + * enough to support an IPv6 5-tuple that includes a VXLAN/GENEVE/NVGRE + * tunnel ID, e.g: _ Source IP: 16B. _ Dest IP: 16B. _ Source port: 2B. _ + * Dest port: 2B. _ Tunnel VNI/VSI: 3B. _ Total: 39B. + */ +union nixx_af_rx_flow_key_algx_fieldx { + u64 u; + struct nixx_af_rx_flow_key_algx_fieldx_s { + u64 key_offset : 6; + u64 ln_mask : 1; + u64 fn_mask : 1; + u64 hdr_offset : 8; + u64 bytesm1 : 5; + u64 lid : 3; + u64 reserved_24 : 1; + u64 ena : 1; + u64 sel_chan : 1; + u64 ltype_mask : 4; + u64 ltype_match : 4; + u64 reserved_35_63 : 29; + } s; + /* struct nixx_af_rx_flow_key_algx_fieldx_s cn; */ +}; + +static inline u64 NIXX_AF_RX_FLOW_KEY_ALGX_FIELDX(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_FLOW_KEY_ALGX_FIELDX(u64 a, u64 b) +{ + return 0x1800 + 0x40000 * a + 8 * b; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_ipsec_gen_cfg + * + * INTERNAL: NIX AF Receive IPSEC General Configuration Register + * Internal: Not used; no IPSEC fast-path. + */ +union nixx_af_rx_ipsec_gen_cfg { + u64 u; + struct nixx_af_rx_ipsec_gen_cfg_s { + u64 param2 : 16; + u64 param1 : 16; + u64 opcode : 16; + u64 egrp : 3; + u64 reserved_51_63 : 13; + } s; + /* struct nixx_af_rx_ipsec_gen_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_RX_IPSEC_GEN_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_IPSEC_GEN_CFG(void) +{ + return 0x300; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_link#_cfg + * + * NIX AF Receive Link Configuration Registers Index enumerated by + * NIX_LINK_E. + */ +union nixx_af_rx_linkx_cfg { + u64 u; + struct nixx_af_rx_linkx_cfg_s { + u64 minlen : 16; + u64 maxlen : 16; + u64 reserved_32_63 : 32; + } s; + /* struct nixx_af_rx_linkx_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_RX_LINKX_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_LINKX_CFG(u64 a) +{ + return 0x540 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_link#_sl#_spkt_cnt + * + * INTERNAL: NIX Receive Software Sync Link Packet Count Registers For + * diagnostic use only for debug of NIX_AF_RX_SW_SYNC[ENA] function. LINK + * index is enumerated by NIX_LINK_E. For the internal multicast/mirror + * link (NIX_LINK_E::MC), SL index is zero for multicast replay, one for + * mirror replay. SL index one is reserved for all other links. + * Internal: 802.3br frame preemption/express path is defeatured. Old + * definition of SL index: SL index is zero for non-express packets, one + * for express packets. For the internal NIX_LINK_E::MC, SL index is zero + * for multicast replay, one for mirror replay. + */ +union nixx_af_rx_linkx_slx_spkt_cnt { + u64 u; + struct nixx_af_rx_linkx_slx_spkt_cnt_s { + u64 in_cnt : 20; + u64 reserved_20_31 : 12; + u64 out_cnt : 20; + u64 reserved_52_63 : 12; + } s; + /* struct nixx_af_rx_linkx_slx_spkt_cnt_s cn; */ +}; + +static inline u64 NIXX_AF_RX_LINKX_SLX_SPKT_CNT(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_LINKX_SLX_SPKT_CNT(u64 a, u64 b) +{ + return 0x500 + 0x10000 * a + 8 * b; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_link#_wrr_cfg + * + * NIX AF Receive Link Weighted Round Robin Configuration Registers Index + * enumerated by NIX_LINK_E. + */ +union nixx_af_rx_linkx_wrr_cfg { + u64 u; + struct nixx_af_rx_linkx_wrr_cfg_s { + u64 weight : 8; + u64 reserved_8_63 : 56; + } s; + /* struct nixx_af_rx_linkx_wrr_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_RX_LINKX_WRR_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_LINKX_WRR_CFG(u64 a) +{ + return 0x560 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_mcast_base + * + * NIX AF Receive Multicast/Mirror Table Base Address Register This + * register specifies the base AF IOVA of the receive multicast/mirror + * table in NDC/LLC/DRAM. The table consists of 1 \<\< + * (NIX_AF_RX_MCAST_CFG[SIZE] + 8) contiguous NIX_RX_MCE_S structures. + * The size of each structure is 1 \<\< NIX_AF_CONST3[MCE_LOG2BYTES]. + * The table contains multicast/mirror replication lists. Each list + * consists of linked entries with NIX_RX_MCE_S[EOL] = 1 in the last + * entry. All lists must reside within the table size specified by + * NIX_AF_RX_MCAST_CFG[SIZE]. A mirror replication list will typically + * consist of two entries, but that is not checked or enforced by + * hardware. A receive packet is multicast when the action returned by + * NPC has NIX_RX_ACTION_S[OP] = NIX_RX_ACTIONOP_E::MCAST. A receive + * packet is mirrored when the action returned by NPC has + * NIX_RX_ACTION_S[OP] = NIX_RX_ACTIONOP_E::MIRROR. In both cases, + * NIX_RX_ACTION_S[INDEX] specifies the index of the replication list's + * first NIX_RX_MCE_S in the table, and a linked entry with + * NIX_RX_MCE_S[EOL] = 1 indicates the end of list. If a mirrored flow + * is part of a multicast replication list, software should include the + * two mirror entries in that list. Internal: A multicast list may have + * multiple entries for the same LF (e.g. for future RoCE/IB multicast). + */ +union nixx_af_rx_mcast_base { + u64 u; + struct nixx_af_rx_mcast_base_s { + u64 reserved_0_6 : 7; + u64 addr : 46; + u64 reserved_53_63 : 11; + } s; + /* struct nixx_af_rx_mcast_base_s cn; */ +}; + +static inline u64 NIXX_AF_RX_MCAST_BASE(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_MCAST_BASE(void) +{ + return 0x100; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_mcast_buf_base + * + * NIX AF Receive Multicast Buffer Base Address Register This register + * specifies the base AF IOVA of the receive multicast buffers in + * NDC/LLC/DRAM. These buffers are used to temporarily store packets + * whose action returned by NPC has NIX_RX_ACTION_S[OP] = + * NIX_RX_ACTIONOP_E::MCAST. The number of buffers is configured by + * NIX_AF_RX_MCAST_BUF_CFG[SIZE]. If the number of free buffers is + * insufficient for a received multicast packet, hardware tail drops the + * packet and sets NIX_AF_GEN_INT[RX_MCAST_DROP]. Hardware prioritizes + * the processing of RX mirror packets over RX multicast packets. + */ +union nixx_af_rx_mcast_buf_base { + u64 u; + struct nixx_af_rx_mcast_buf_base_s { + u64 reserved_0_6 : 7; + u64 addr : 46; + u64 reserved_53_63 : 11; + } s; + /* struct nixx_af_rx_mcast_buf_base_s cn; */ +}; + +static inline u64 NIXX_AF_RX_MCAST_BUF_BASE(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_MCAST_BUF_BASE(void) +{ + return 0x120; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_mcast_buf_cfg + * + * NIX AF Receive Multicast Buffer Configuration Register See + * NIX_AF_RX_MCAST_BUF_BASE. + */ +union nixx_af_rx_mcast_buf_cfg { + u64 u; + struct nixx_af_rx_mcast_buf_cfg_s { + u64 size : 4; + u64 way_mask : 16; + u64 caching : 1; + u64 reserved_21_23 : 3; + u64 npc_replay_pkind : 6; + u64 reserved_30_31 : 2; + u64 free_buf_level : 11; + u64 reserved_43_61 : 19; + u64 busy : 1; + u64 ena : 1; + } s; + struct nixx_af_rx_mcast_buf_cfg_cn96xxp1 { + u64 size : 4; + u64 way_mask : 16; + u64 caching : 1; + u64 reserved_21_23 : 3; + u64 npc_replay_pkind : 6; + u64 reserved_30_31 : 2; + u64 free_buf_level : 11; + u64 reserved_43_61 : 19; + u64 reserved_62 : 1; + u64 ena : 1; + } cn96xxp1; + /* struct nixx_af_rx_mcast_buf_cfg_s cn96xxp3; */ + struct nixx_af_rx_mcast_buf_cfg_cnf95xxp1 { + u64 size : 4; + u64 way_mask : 16; + u64 caching : 1; + u64 reserved_21_23 : 3; + u64 npc_replay_pkind : 6; + u64 reserved_30_31 : 2; + u64 free_buf_level : 11; + u64 reserved_43_62 : 20; + u64 ena : 1; + } cnf95xxp1; + /* struct nixx_af_rx_mcast_buf_cfg_s cnf95xxp2; */ +}; + +static inline u64 NIXX_AF_RX_MCAST_BUF_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_MCAST_BUF_CFG(void) +{ + return 0x130; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_mcast_cfg + * + * NIX AF Receive Multicast/Mirror Table Configuration Register See + * NIX_AF_RX_MCAST_BASE. + */ +union nixx_af_rx_mcast_cfg { + u64 u; + struct nixx_af_rx_mcast_cfg_s { + u64 size : 4; + u64 max_list_lenm1 : 8; + u64 reserved_12_19 : 8; + u64 way_mask : 16; + u64 caching : 1; + u64 reserved_37_63 : 27; + } s; + /* struct nixx_af_rx_mcast_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_RX_MCAST_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_MCAST_CFG(void) +{ + return 0x110; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_mirror_buf_base + * + * NIX AF Receive Mirror Buffer Base Address Register This register + * specifies the base AF IOVA of the receive mirror buffers in + * NDC/LLC/DRAM. These buffers are used to temporarily store packets + * whose action returned by NPC has NIX_RX_ACTION_S[OP] = + * NIX_RX_ACTIONOP_E::MIRROR. The number of buffers is configured by + * NIX_AF_RX_MIRROR_BUF_CFG[SIZE]. If the number of free buffers is + * insufficient for a received multicast packet, hardware tail drops the + * packet and sets NIX_AF_GEN_INT[RX_MIRROR_DROP]. Hardware prioritizes + * the processing of RX mirror packets over RX multicast packets. + */ +union nixx_af_rx_mirror_buf_base { + u64 u; + struct nixx_af_rx_mirror_buf_base_s { + u64 reserved_0_6 : 7; + u64 addr : 46; + u64 reserved_53_63 : 11; + } s; + /* struct nixx_af_rx_mirror_buf_base_s cn; */ +}; + +static inline u64 NIXX_AF_RX_MIRROR_BUF_BASE(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_MIRROR_BUF_BASE(void) +{ + return 0x140; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_mirror_buf_cfg + * + * NIX AF Receive Mirror Buffer Configuration Register See + * NIX_AF_RX_MIRROR_BUF_BASE. + */ +union nixx_af_rx_mirror_buf_cfg { + u64 u; + struct nixx_af_rx_mirror_buf_cfg_s { + u64 size : 4; + u64 way_mask : 16; + u64 caching : 1; + u64 reserved_21_23 : 3; + u64 npc_replay_pkind : 6; + u64 reserved_30_31 : 2; + u64 free_buf_level : 11; + u64 reserved_43_61 : 19; + u64 busy : 1; + u64 ena : 1; + } s; + struct nixx_af_rx_mirror_buf_cfg_cn96xxp1 { + u64 size : 4; + u64 way_mask : 16; + u64 caching : 1; + u64 reserved_21_23 : 3; + u64 npc_replay_pkind : 6; + u64 reserved_30_31 : 2; + u64 free_buf_level : 11; + u64 reserved_43_61 : 19; + u64 reserved_62 : 1; + u64 ena : 1; + } cn96xxp1; + /* struct nixx_af_rx_mirror_buf_cfg_s cn96xxp3; */ + struct nixx_af_rx_mirror_buf_cfg_cnf95xxp1 { + u64 size : 4; + u64 way_mask : 16; + u64 caching : 1; + u64 reserved_21_23 : 3; + u64 npc_replay_pkind : 6; + u64 reserved_30_31 : 2; + u64 free_buf_level : 11; + u64 reserved_43_62 : 20; + u64 ena : 1; + } cnf95xxp1; + /* struct nixx_af_rx_mirror_buf_cfg_s cnf95xxp2; */ +}; + +static inline u64 NIXX_AF_RX_MIRROR_BUF_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_MIRROR_BUF_CFG(void) +{ + return 0x148; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_npc_mc_drop + * + * NIX AF Multicast Drop Statistics Register The counter increments for + * every dropped MC packet marked by the NPC. + */ +union nixx_af_rx_npc_mc_drop { + u64 u; + struct nixx_af_rx_npc_mc_drop_s { + u64 stat : 48; + u64 reserved_48_63 : 16; + } s; + /* struct nixx_af_rx_npc_mc_drop_s cn; */ +}; + +static inline u64 NIXX_AF_RX_NPC_MC_DROP(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_NPC_MC_DROP(void) +{ + return 0x4710; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_npc_mc_rcv + * + * NIX AF Multicast Receive Statistics Register The counter increments + * for every received MC packet marked by the NPC. + */ +union nixx_af_rx_npc_mc_rcv { + u64 u; + struct nixx_af_rx_npc_mc_rcv_s { + u64 stat : 48; + u64 reserved_48_63 : 16; + } s; + /* struct nixx_af_rx_npc_mc_rcv_s cn; */ +}; + +static inline u64 NIXX_AF_RX_NPC_MC_RCV(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_NPC_MC_RCV(void) +{ + return 0x4700; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_npc_mirror_drop + * + * NIX AF Mirror Drop Statistics Register The counter increments for + * every dropped MIRROR packet marked by the NPC. + */ +union nixx_af_rx_npc_mirror_drop { + u64 u; + struct nixx_af_rx_npc_mirror_drop_s { + u64 stat : 48; + u64 reserved_48_63 : 16; + } s; + /* struct nixx_af_rx_npc_mirror_drop_s cn; */ +}; + +static inline u64 NIXX_AF_RX_NPC_MIRROR_DROP(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_NPC_MIRROR_DROP(void) +{ + return 0x4730; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_npc_mirror_rcv + * + * NIX AF Mirror Receive Statistics Register The counter increments for + * every received MIRROR packet marked by the NPC. + */ +union nixx_af_rx_npc_mirror_rcv { + u64 u; + struct nixx_af_rx_npc_mirror_rcv_s { + u64 stat : 48; + u64 reserved_48_63 : 16; + } s; + /* struct nixx_af_rx_npc_mirror_rcv_s cn; */ +}; + +static inline u64 NIXX_AF_RX_NPC_MIRROR_RCV(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_NPC_MIRROR_RCV(void) +{ + return 0x4720; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_rx_sw_sync + * + * NIX AF Receive Software Sync Register + */ +union nixx_af_rx_sw_sync { + u64 u; + struct nixx_af_rx_sw_sync_s { + u64 ena : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_af_rx_sw_sync_s cn; */ +}; + +static inline u64 NIXX_AF_RX_SW_SYNC(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_RX_SW_SYNC(void) +{ + return 0x550; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_sdp_hw_xoff# + * + * NIX AF SDP Transmit Link Hardware Controlled XOFF Registers . + */ +union nixx_af_sdp_hw_xoffx { + u64 u; + struct nixx_af_sdp_hw_xoffx_s { + u64 chan_xoff : 64; + } s; + /* struct nixx_af_sdp_hw_xoffx_s cn; */ +}; + +static inline u64 NIXX_AF_SDP_HW_XOFFX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SDP_HW_XOFFX(u64 a) +{ + return 0xac0 + 8 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_sdp_link_credit + * + * NIX AF Transmit Link SDP Credit Register This register tracks SDP link + * credits. + */ +union nixx_af_sdp_link_credit { + u64 u; + struct nixx_af_sdp_link_credit_s { + u64 reserved_0 : 1; + u64 cc_enable : 1; + u64 cc_packet_cnt : 10; + u64 cc_unit_cnt : 20; + u64 reserved_32_62 : 31; + u64 pse_pkt_id_lmt : 1; + } s; + struct nixx_af_sdp_link_credit_cn96xx { + u64 reserved_0 : 1; + u64 cc_enable : 1; + u64 cc_packet_cnt : 10; + u64 cc_unit_cnt : 20; + u64 reserved_32_62 : 31; + u64 reserved_63 : 1; + } cn96xx; + /* struct nixx_af_sdp_link_credit_s cnf95xx; */ +}; + +static inline u64 NIXX_AF_SDP_LINK_CREDIT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SDP_LINK_CREDIT(void) +{ + return 0xa40; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_sdp_sw_xoff# + * + * INTERNAL: NIX AF SDP Transmit Link Software Controlled XOFF Registers + * Internal: Defeatured registers. Software should use + * NIX_AF_TL4()_SW_XOFF registers instead. + */ +union nixx_af_sdp_sw_xoffx { + u64 u; + struct nixx_af_sdp_sw_xoffx_s { + u64 chan_xoff : 64; + } s; + /* struct nixx_af_sdp_sw_xoffx_s cn; */ +}; + +static inline u64 NIXX_AF_SDP_SW_XOFFX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SDP_SW_XOFFX(u64 a) +{ + return 0xa60 + 8 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_sdp_tx_fifo_status + * + * NIX AF SDP Transmit FIFO Status Register Status of FIFO which + * transmits packets to SDP. + */ +union nixx_af_sdp_tx_fifo_status { + u64 u; + struct nixx_af_sdp_tx_fifo_status_s { + u64 count : 12; + u64 reserved_12_63 : 52; + } s; + /* struct nixx_af_sdp_tx_fifo_status_s cn; */ +}; + +static inline u64 NIXX_AF_SDP_TX_FIFO_STATUS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SDP_TX_FIFO_STATUS(void) +{ + return 0x650; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_seb_active_cycles_pc# + * + * NIX AF Active Cycles Register These registers are indexed by the + * conditional clock domain number. + */ +union nixx_af_seb_active_cycles_pcx { + u64 u; + struct nixx_af_seb_active_cycles_pcx_s { + u64 act_cyc : 64; + } s; + /* struct nixx_af_seb_active_cycles_pcx_s cn; */ +}; + +static inline u64 NIXX_AF_SEB_ACTIVE_CYCLES_PCX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SEB_ACTIVE_CYCLES_PCX(u64 a) +{ + return 0x6c0 + 8 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_seb_bp_test + * + * INTERNAL: NIX AF SEB Backpressure Test Register + */ +union nixx_af_seb_bp_test { + u64 u; + struct nixx_af_seb_bp_test_s { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 14; + u64 reserved_30_47 : 18; + u64 enable : 7; + u64 reserved_55_63 : 9; + } s; + /* struct nixx_af_seb_bp_test_s cn; */ +}; + +static inline u64 NIXX_AF_SEB_BP_TEST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SEB_BP_TEST(void) +{ + return 0x630; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_seb_cfg + * + * NIX SEB Configuration Register + */ +union nixx_af_seb_cfg { + u64 u; + struct nixx_af_seb_cfg_s { + u64 sg_ndc_sel : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_af_seb_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_SEB_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SEB_CFG(void) +{ + return 0x5f0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_seb_eco + * + * INTERNAL: AF SEB ECO Register + */ +union nixx_af_seb_eco { + u64 u; + struct nixx_af_seb_eco_s { + u64 eco_rw : 64; + } s; + /* struct nixx_af_seb_eco_s cn; */ +}; + +static inline u64 NIXX_AF_SEB_ECO(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SEB_ECO(void) +{ + return 0x5c0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_seb_pipe_bp_test# + * + * INTERNAL: NIX AF SEB Pipe Backpressure Test Registers + */ +union nixx_af_seb_pipe_bp_testx { + u64 u; + struct nixx_af_seb_pipe_bp_testx_s { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 24; + u64 reserved_40_47 : 8; + u64 enable : 12; + u64 reserved_60_63 : 4; + } s; + /* struct nixx_af_seb_pipe_bp_testx_s cn; */ +}; + +static inline u64 NIXX_AF_SEB_PIPE_BP_TESTX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SEB_PIPE_BP_TESTX(u64 a) +{ + return 0x600 + 0x10 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_seb_pipeb_bp_test# + * + * INTERNAL: NIX AF SEB Pipe Backpressure Test Registers + */ +union nixx_af_seb_pipeb_bp_testx { + u64 u; + struct nixx_af_seb_pipeb_bp_testx_s { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 18; + u64 reserved_34_47 : 14; + u64 enable : 9; + u64 reserved_57_63 : 7; + } s; + /* struct nixx_af_seb_pipeb_bp_testx_s cn; */ +}; + +static inline u64 NIXX_AF_SEB_PIPEB_BP_TESTX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SEB_PIPEB_BP_TESTX(u64 a) +{ + return 0x608 + 0x10 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_seb_wd_tick_divider + * + * INTERNAL: NIX AF SEB TSTMP Watchdog Tick Divider Register + */ +union nixx_af_seb_wd_tick_divider { + u64 u; + struct nixx_af_seb_wd_tick_divider_s { + u64 tick_div_cfg : 7; + u64 reserved_7_63 : 57; + } s; + /* struct nixx_af_seb_wd_tick_divider_s cn; */ +}; + +static inline u64 NIXX_AF_SEB_WD_TICK_DIVIDER(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SEB_WD_TICK_DIVIDER(void) +{ + return 0x6f0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_smq#_cfg + * + * NIX AF SQM PSE Queue Configuration Registers + */ +union nixx_af_smqx_cfg { + u64 u; + struct nixx_af_smqx_cfg_s { + u64 minlen : 7; + u64 desc_shp_ctl_dis : 1; + u64 maxlen : 16; + u64 lf : 7; + u64 reserved_31_35 : 5; + u64 max_vtag_ins : 3; + u64 rr_minlen : 9; + u64 express : 1; + u64 flush : 1; + u64 enq_xoff : 1; + u64 pri_thr : 6; + u64 reserved_57_63 : 7; + } s; + /* struct nixx_af_smqx_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_SMQX_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SMQX_CFG(u64 a) +{ + return 0x700 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_smq#_head + * + * NIX AF SQM SMQ Head Register These registers track the head of the SMQ + * linked list. + */ +union nixx_af_smqx_head { + u64 u; + struct nixx_af_smqx_head_s { + u64 sq_idx : 20; + u64 valid : 1; + u64 reserved_21_63 : 43; + } s; + /* struct nixx_af_smqx_head_s cn; */ +}; + +static inline u64 NIXX_AF_SMQX_HEAD(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SMQX_HEAD(u64 a) +{ + return 0x710 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_smq#_nxt_head + * + * NIX AF SQM SMQ Next Head Register These registers track the next head + * of the SMQ linked list. + */ +union nixx_af_smqx_nxt_head { + u64 u; + struct nixx_af_smqx_nxt_head_s { + u64 sq_idx : 20; + u64 valid : 1; + u64 reserved_21_63 : 43; + } s; + /* struct nixx_af_smqx_nxt_head_s cn; */ +}; + +static inline u64 NIXX_AF_SMQX_NXT_HEAD(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SMQX_NXT_HEAD(u64 a) +{ + return 0x740 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_smq#_status + * + * NIX AF SQM SMQ Status Register These registers track the status of the + * SMQ FIFO. + */ +union nixx_af_smqx_status { + u64 u; + struct nixx_af_smqx_status_s { + u64 level : 7; + u64 reserved_7_63 : 57; + } s; + /* struct nixx_af_smqx_status_s cn; */ +}; + +static inline u64 NIXX_AF_SMQX_STATUS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SMQX_STATUS(u64 a) +{ + return 0x730 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_smq#_tail + * + * NIX AF SQM SMQ Head Register These registers track the tail of SMQ + * linked list. + */ +union nixx_af_smqx_tail { + u64 u; + struct nixx_af_smqx_tail_s { + u64 sq_idx : 20; + u64 valid : 1; + u64 reserved_21_63 : 43; + } s; + /* struct nixx_af_smqx_tail_s cn; */ +}; + +static inline u64 NIXX_AF_SMQX_TAIL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SMQX_TAIL(u64 a) +{ + return 0x720 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_sq_const + * + * NIX AF SQ Constants Register This register contains constants for + * software discovery. + */ +union nixx_af_sq_const { + u64 u; + struct nixx_af_sq_const_s { + u64 queues_per_lf : 24; + u64 smq_depth : 10; + u64 sqb_size : 16; + u64 reserved_50_63 : 14; + } s; + /* struct nixx_af_sq_const_s cn; */ +}; + +static inline u64 NIXX_AF_SQ_CONST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SQ_CONST(void) +{ + return 0x40; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_sqm_active_cycles_pc + * + * NIX AF SQM Active Cycles Register These registers are indexed by the + * conditional clock domain number. + */ +union nixx_af_sqm_active_cycles_pc { + u64 u; + struct nixx_af_sqm_active_cycles_pc_s { + u64 act_cyc : 64; + } s; + /* struct nixx_af_sqm_active_cycles_pc_s cn; */ +}; + +static inline u64 NIXX_AF_SQM_ACTIVE_CYCLES_PC(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SQM_ACTIVE_CYCLES_PC(void) +{ + return 0x770; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_sqm_bp_test# + * + * INTERNAL: NIX AF SQM Backpressure Test Register + */ +union nixx_af_sqm_bp_testx { + u64 u; + struct nixx_af_sqm_bp_testx_s { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 8; + u64 reserved_24_59 : 36; + u64 enable : 4; + } s; + /* struct nixx_af_sqm_bp_testx_s cn; */ +}; + +static inline u64 NIXX_AF_SQM_BP_TESTX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SQM_BP_TESTX(u64 a) +{ + return 0x760 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_sqm_dbg_ctl_status + * + * NIX AF SQM Debug Register This register is for SQM diagnostic use + * only. + */ +union nixx_af_sqm_dbg_ctl_status { + u64 u; + struct nixx_af_sqm_dbg_ctl_status_s { + u64 tm1 : 8; + u64 tm2 : 1; + u64 tm3 : 4; + u64 tm4 : 1; + u64 tm5 : 1; + u64 tm6 : 1; + u64 tm7 : 4; + u64 tm8 : 1; + u64 tm9 : 1; + u64 tm10 : 1; + u64 tm11 : 1; + u64 tm12 : 1; + u64 tm13 : 1; + u64 reserved_26_63 : 38; + } s; + struct nixx_af_sqm_dbg_ctl_status_cn96xxp1 { + u64 tm1 : 8; + u64 tm2 : 1; + u64 tm3 : 4; + u64 tm4 : 1; + u64 tm5 : 1; + u64 tm6 : 1; + u64 tm7 : 4; + u64 tm8 : 1; + u64 tm9 : 1; + u64 reserved_22_63 : 42; + } cn96xxp1; + /* struct nixx_af_sqm_dbg_ctl_status_s cn96xxp3; */ + /* struct nixx_af_sqm_dbg_ctl_status_cn96xxp1 cnf95xxp1; */ + struct nixx_af_sqm_dbg_ctl_status_cnf95xxp2 { + u64 tm1 : 8; + u64 tm2 : 1; + u64 tm3 : 4; + u64 tm4 : 1; + u64 tm5 : 1; + u64 tm6 : 1; + u64 tm7 : 4; + u64 tm8 : 1; + u64 tm9 : 1; + u64 reserved_22 : 1; + u64 reserved_23 : 1; + u64 reserved_24 : 1; + u64 reserved_25 : 1; + u64 reserved_26_63 : 38; + } cnf95xxp2; +}; + +static inline u64 NIXX_AF_SQM_DBG_CTL_STATUS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SQM_DBG_CTL_STATUS(void) +{ + return 0x750; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_sqm_eco + * + * INTERNAL: AF SQM ECO Register + */ +union nixx_af_sqm_eco { + u64 u; + struct nixx_af_sqm_eco_s { + u64 eco_rw : 64; + } s; + /* struct nixx_af_sqm_eco_s cn; */ +}; + +static inline u64 NIXX_AF_SQM_ECO(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_SQM_ECO(void) +{ + return 0x5b0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_status + * + * NIX AF General Status Register + */ +union nixx_af_status { + u64 u; + struct nixx_af_status_s { + u64 blk_busy : 10; + u64 calibrate_done : 1; + u64 reserved_11_15 : 5; + u64 calibrate_status : 15; + u64 reserved_31_63 : 33; + } s; + /* struct nixx_af_status_s cn; */ +}; + +static inline u64 NIXX_AF_STATUS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_STATUS(void) +{ + return 0x10; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tcp_timer + * + * NIX TCP Timer Register + */ +union nixx_af_tcp_timer { + u64 u; + struct nixx_af_tcp_timer_s { + u64 dur_counter : 16; + u64 lf_counter : 8; + u64 reserved_24_31 : 8; + u64 duration : 16; + u64 reserved_48_62 : 15; + u64 ena : 1; + } s; + /* struct nixx_af_tcp_timer_s cn; */ +}; + +static inline u64 NIXX_AF_TCP_TIMER(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TCP_TIMER(void) +{ + return 0x1e0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_cir + * + * NIX AF Transmit Level 1 Committed Information Rate Register + */ +union nixx_af_tl1x_cir { + u64 u; + struct nixx_af_tl1x_cir_s { + u64 enable : 1; + u64 rate_mantissa : 8; + u64 rate_exponent : 4; + u64 rate_divider_exponent : 4; + u64 reserved_17_28 : 12; + u64 burst_mantissa : 8; + u64 burst_exponent : 4; + u64 reserved_41_63 : 23; + } s; + /* struct nixx_af_tl1x_cir_s cn; */ +}; + +static inline u64 NIXX_AF_TL1X_CIR(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_CIR(u64 a) +{ + return 0xc20 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_dropped_bytes + * + * NIX AF Transmit Level 1 Dropped Bytes Registers This register has the + * same bit fields as NIX_AF_TL1()_GREEN_BYTES. + */ +union nixx_af_tl1x_dropped_bytes { + u64 u; + struct nixx_af_tl1x_dropped_bytes_s { + u64 count : 48; + u64 reserved_48_63 : 16; + } s; + /* struct nixx_af_tl1x_dropped_bytes_s cn; */ +}; + +static inline u64 NIXX_AF_TL1X_DROPPED_BYTES(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_DROPPED_BYTES(u64 a) +{ + return 0xd30 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_dropped_packets + * + * NIX AF Transmit Level 1 Dropped Packets Registers This register has + * the same bit fields as NIX_AF_TL1()_GREEN_PACKETS. + */ +union nixx_af_tl1x_dropped_packets { + u64 u; + struct nixx_af_tl1x_dropped_packets_s { + u64 count : 40; + u64 reserved_40_63 : 24; + } s; + /* struct nixx_af_tl1x_dropped_packets_s cn; */ +}; + +static inline u64 NIXX_AF_TL1X_DROPPED_PACKETS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_DROPPED_PACKETS(u64 a) +{ + return 0xd20 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_green + * + * INTERNAL: NIX Transmit Level 1 Green State Debug Register + */ +union nixx_af_tl1x_green { + u64 u; + struct nixx_af_tl1x_green_s { + u64 tail : 8; + u64 reserved_8_9 : 2; + u64 head : 8; + u64 reserved_18_19 : 2; + u64 active_vec : 20; + u64 rr_active : 1; + u64 reserved_41_63 : 23; + } s; + /* struct nixx_af_tl1x_green_s cn; */ +}; + +static inline u64 NIXX_AF_TL1X_GREEN(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_GREEN(u64 a) +{ + return 0xc90 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_green_bytes + * + * NIX AF Transmit Level 1 Green Sent Bytes Registers + */ +union nixx_af_tl1x_green_bytes { + u64 u; + struct nixx_af_tl1x_green_bytes_s { + u64 count : 48; + u64 reserved_48_63 : 16; + } s; + /* struct nixx_af_tl1x_green_bytes_s cn; */ +}; + +static inline u64 NIXX_AF_TL1X_GREEN_BYTES(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_GREEN_BYTES(u64 a) +{ + return 0xd90 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_green_packets + * + * NIX AF Transmit Level 1 Green Sent Packets Registers + */ +union nixx_af_tl1x_green_packets { + u64 u; + struct nixx_af_tl1x_green_packets_s { + u64 count : 40; + u64 reserved_40_63 : 24; + } s; + /* struct nixx_af_tl1x_green_packets_s cn; */ +}; + +static inline u64 NIXX_AF_TL1X_GREEN_PACKETS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_GREEN_PACKETS(u64 a) +{ + return 0xd80 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_md_debug0 + * + * NIX AF Transmit Level 1 Meta Descriptor Debug 0 Registers + * NIX_AF_TL1()_MD_DEBUG0, NIX_AF_TL1()_MD_DEBUG1, NIX_AF_TL1()_MD_DEBUG2 + * and NIX_AF_TL1()_MD_DEBUG3 provide access to the TLn queue meta + * descriptor. A TLn queue can hold up to two packet meta descriptors + * (PMD) and one flush meta descriptor (FMD): * PMD0 state is accessed + * with [PMD0_VLD], [PMD0_LENGTH] and NIX_AF_TL1()_MD_DEBUG1. * PMD1 is + * accessed with [PMD1_VLD], [PMD1_LENGTH] and NIX_AF_TL1()_MD_DEBUG2. * + * FMD is accessed with NIX_AF_TL1()_MD_DEBUG3. + */ +union nixx_af_tl1x_md_debug0 { + u64 u; + struct nixx_af_tl1x_md_debug0_s { + u64 pmd0_length : 16; + u64 pmd1_length : 16; + u64 pmd0_vld : 1; + u64 pmd1_vld : 1; + u64 reserved_34_45 : 12; + u64 drain_pri : 1; + u64 drain : 1; + u64 c_con : 1; + u64 p_con : 1; + u64 reserved_50_51 : 2; + u64 child : 10; + u64 reserved_62 : 1; + u64 pmd_count : 1; + } s; + /* struct nixx_af_tl1x_md_debug0_s cn96xxp1; */ + struct nixx_af_tl1x_md_debug0_cn96xxp3 { + u64 pmd0_length : 16; + u64 reserved_16_31 : 16; + u64 pmd0_vld : 1; + u64 reserved_33 : 1; + u64 reserved_34_45 : 12; + u64 reserved_46 : 1; + u64 reserved_47 : 1; + u64 c_con : 1; + u64 p_con : 1; + u64 reserved_50_51 : 2; + u64 child : 10; + u64 reserved_62 : 1; + u64 reserved_63 : 1; + } cn96xxp3; + /* struct nixx_af_tl1x_md_debug0_s cnf95xx; */ +}; + +static inline u64 NIXX_AF_TL1X_MD_DEBUG0(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_MD_DEBUG0(u64 a) +{ + return 0xcc0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_md_debug1 + * + * NIX AF Transmit Level 1 Meta Descriptor Debug 1 Registers Packet meta + * descriptor 0 debug. See NIX_AF_TL1()_MD_DEBUG0. + */ +union nixx_af_tl1x_md_debug1 { + u64 u; + struct nixx_af_tl1x_md_debug1_s { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 uid : 4; + u64 reserved_23 : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } s; + struct nixx_af_tl1x_md_debug1_cn96xxp1 { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 uid : 4; + u64 drain : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } cn96xxp1; + struct nixx_af_tl1x_md_debug1_cn96xxp3 { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 reserved_19_22 : 4; + u64 flush : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } cn96xxp3; + /* struct nixx_af_tl1x_md_debug1_cn96xxp1 cnf95xx; */ +}; + +static inline u64 NIXX_AF_TL1X_MD_DEBUG1(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_MD_DEBUG1(u64 a) +{ + return 0xcc8 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_md_debug2 + * + * NIX AF Transmit Level 1 Meta Descriptor Debug 2 Registers Packet meta + * descriptor 1 debug. See NIX_AF_TL1()_MD_DEBUG0. + */ +union nixx_af_tl1x_md_debug2 { + u64 u; + struct nixx_af_tl1x_md_debug2_s { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 uid : 4; + u64 reserved_23 : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } s; + struct nixx_af_tl1x_md_debug2_cn96xxp1 { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 uid : 4; + u64 drain : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } cn96xxp1; + struct nixx_af_tl1x_md_debug2_cn96xxp3 { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 reserved_19_22 : 4; + u64 flush : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } cn96xxp3; + /* struct nixx_af_tl1x_md_debug2_cn96xxp1 cnf95xx; */ +}; + +static inline u64 NIXX_AF_TL1X_MD_DEBUG2(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_MD_DEBUG2(u64 a) +{ + return 0xcd0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_md_debug3 + * + * NIX AF Transmit Level 1 Meta Descriptor Debug 3 Registers Flush meta + * descriptor debug. See NIX_AF_TL1()_MD_DEBUG0. + */ +union nixx_af_tl1x_md_debug3 { + u64 u; + struct nixx_af_tl1x_md_debug3_s { + u64 reserved_0_36 : 37; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } s; + /* struct nixx_af_tl1x_md_debug3_s cn96xxp1; */ + struct nixx_af_tl1x_md_debug3_cn96xxp3 { + u64 reserved_0_36 : 37; + u64 reserved_37_38 : 2; + u64 reserved_39_51 : 13; + u64 reserved_52_61 : 10; + u64 reserved_62 : 1; + u64 reserved_63 : 1; + } cn96xxp3; + /* struct nixx_af_tl1x_md_debug3_s cnf95xx; */ +}; + +static inline u64 NIXX_AF_TL1X_MD_DEBUG3(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_MD_DEBUG3(u64 a) +{ + return 0xcd8 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_red + * + * INTERNAL: NIX Transmit Level 1 Red State Debug Register This register + * has the same bit fields as NIX_AF_TL1()_YELLOW. + */ +union nixx_af_tl1x_red { + u64 u; + struct nixx_af_tl1x_red_s { + u64 tail : 8; + u64 reserved_8_9 : 2; + u64 head : 8; + u64 reserved_18_63 : 46; + } s; + /* struct nixx_af_tl1x_red_s cn; */ +}; + +static inline u64 NIXX_AF_TL1X_RED(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_RED(u64 a) +{ + return 0xcb0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_red_bytes + * + * NIX AF Transmit Level 1 Red Sent Bytes Registers This register has the + * same bit fields as NIX_AF_TL1()_GREEN_BYTES. + */ +union nixx_af_tl1x_red_bytes { + u64 u; + struct nixx_af_tl1x_red_bytes_s { + u64 count : 48; + u64 reserved_48_63 : 16; + } s; + /* struct nixx_af_tl1x_red_bytes_s cn; */ +}; + +static inline u64 NIXX_AF_TL1X_RED_BYTES(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_RED_BYTES(u64 a) +{ + return 0xd50 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_red_packets + * + * NIX AF Transmit Level 1 Red Sent Packets Registers This register has + * the same bit fields as NIX_AF_TL1()_GREEN_PACKETS. + */ +union nixx_af_tl1x_red_packets { + u64 u; + struct nixx_af_tl1x_red_packets_s { + u64 count : 40; + u64 reserved_40_63 : 24; + } s; + /* struct nixx_af_tl1x_red_packets_s cn; */ +}; + +static inline u64 NIXX_AF_TL1X_RED_PACKETS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_RED_PACKETS(u64 a) +{ + return 0xd40 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_schedule + * + * NIX AF Transmit Level 1 Scheduling Control Register + */ +union nixx_af_tl1x_schedule { + u64 u; + struct nixx_af_tl1x_schedule_s { + u64 rr_quantum : 24; + u64 reserved_24_63 : 40; + } s; + /* struct nixx_af_tl1x_schedule_s cn; */ +}; + +static inline u64 NIXX_AF_TL1X_SCHEDULE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_SCHEDULE(u64 a) +{ + return 0xc00 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_shape + * + * NIX AF Transmit Level 1 Shaping Control Register + */ +union nixx_af_tl1x_shape { + u64 u; + struct nixx_af_tl1x_shape_s { + u64 adjust : 9; + u64 reserved_9_23 : 15; + u64 length_disable : 1; + u64 reserved_25_63 : 39; + } s; + struct nixx_af_tl1x_shape_cn { + u64 adjust : 9; + u64 reserved_9_17 : 9; + u64 reserved_18_23 : 6; + u64 length_disable : 1; + u64 reserved_25_63 : 39; + } cn; +}; + +static inline u64 NIXX_AF_TL1X_SHAPE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_SHAPE(u64 a) +{ + return 0xc10 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_shape_state + * + * NIX AF Transmit Level 1 Shape State Register This register must not be + * written during normal operation. + */ +union nixx_af_tl1x_shape_state { + u64 u; + struct nixx_af_tl1x_shape_state_s { + u64 cir_accum : 26; + u64 reserved_26_51 : 26; + u64 color : 1; + u64 reserved_53_63 : 11; + } s; + /* struct nixx_af_tl1x_shape_state_s cn; */ +}; + +static inline u64 NIXX_AF_TL1X_SHAPE_STATE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_SHAPE_STATE(u64 a) +{ + return 0xc50 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_sw_xoff + * + * NIX AF Transmit Level 1 Software Controlled XOFF Registers + */ +union nixx_af_tl1x_sw_xoff { + u64 u; + struct nixx_af_tl1x_sw_xoff_s { + u64 xoff : 1; + u64 drain : 1; + u64 reserved_2 : 1; + u64 drain_irq : 1; + u64 reserved_4_63 : 60; + } s; + /* struct nixx_af_tl1x_sw_xoff_s cn; */ +}; + +static inline u64 NIXX_AF_TL1X_SW_XOFF(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_SW_XOFF(u64 a) +{ + return 0xc70 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_topology + * + * NIX AF Transmit Level 1 Topology Registers + */ +union nixx_af_tl1x_topology { + u64 u; + struct nixx_af_tl1x_topology_s { + u64 reserved_0 : 1; + u64 rr_prio : 4; + u64 reserved_5_31 : 27; + u64 prio_anchor : 8; + u64 reserved_40_63 : 24; + } s; + /* struct nixx_af_tl1x_topology_s cn; */ +}; + +static inline u64 NIXX_AF_TL1X_TOPOLOGY(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_TOPOLOGY(u64 a) +{ + return 0xc80 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_yellow + * + * INTERNAL: NIX Transmit Level 1 Yellow State Debug Register + */ +union nixx_af_tl1x_yellow { + u64 u; + struct nixx_af_tl1x_yellow_s { + u64 tail : 8; + u64 reserved_8_9 : 2; + u64 head : 8; + u64 reserved_18_63 : 46; + } s; + /* struct nixx_af_tl1x_yellow_s cn; */ +}; + +static inline u64 NIXX_AF_TL1X_YELLOW(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_YELLOW(u64 a) +{ + return 0xca0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_yellow_bytes + * + * NIX AF Transmit Level 1 Yellow Sent Bytes Registers This register has + * the same bit fields as NIX_AF_TL1()_GREEN_BYTES. + */ +union nixx_af_tl1x_yellow_bytes { + u64 u; + struct nixx_af_tl1x_yellow_bytes_s { + u64 count : 48; + u64 reserved_48_63 : 16; + } s; + /* struct nixx_af_tl1x_yellow_bytes_s cn; */ +}; + +static inline u64 NIXX_AF_TL1X_YELLOW_BYTES(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_YELLOW_BYTES(u64 a) +{ + return 0xd70 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1#_yellow_packets + * + * NIX AF Transmit Level 1 Yellow Sent Packets Registers This register + * has the same bit fields as NIX_AF_TL1()_GREEN_PACKETS. + */ +union nixx_af_tl1x_yellow_packets { + u64 u; + struct nixx_af_tl1x_yellow_packets_s { + u64 count : 40; + u64 reserved_40_63 : 24; + } s; + /* struct nixx_af_tl1x_yellow_packets_s cn; */ +}; + +static inline u64 NIXX_AF_TL1X_YELLOW_PACKETS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1X_YELLOW_PACKETS(u64 a) +{ + return 0xd60 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl1_const + * + * NIX AF Transmit Level 1 Constants Register This register contains + * constants for software discovery. + */ +union nixx_af_tl1_const { + u64 u; + struct nixx_af_tl1_const_s { + u64 count : 16; + u64 reserved_16_63 : 48; + } s; + /* struct nixx_af_tl1_const_s cn; */ +}; + +static inline u64 NIXX_AF_TL1_CONST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL1_CONST(void) +{ + return 0x70; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl2#_cir + * + * NIX AF Transmit Level 2 Committed Information Rate Registers This + * register has the same bit fields as NIX_AF_TL1()_CIR. + */ +union nixx_af_tl2x_cir { + u64 u; + struct nixx_af_tl2x_cir_s { + u64 enable : 1; + u64 rate_mantissa : 8; + u64 rate_exponent : 4; + u64 rate_divider_exponent : 4; + u64 reserved_17_28 : 12; + u64 burst_mantissa : 8; + u64 burst_exponent : 4; + u64 reserved_41_63 : 23; + } s; + /* struct nixx_af_tl2x_cir_s cn; */ +}; + +static inline u64 NIXX_AF_TL2X_CIR(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL2X_CIR(u64 a) +{ + return 0xe20 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl2#_green + * + * INTERNAL: NIX Transmit Level 2 Green State Debug Register This + * register has the same bit fields as NIX_AF_TL1()_GREEN. + */ +union nixx_af_tl2x_green { + u64 u; + struct nixx_af_tl2x_green_s { + u64 tail : 8; + u64 reserved_8_9 : 2; + u64 head : 8; + u64 reserved_18_19 : 2; + u64 active_vec : 20; + u64 rr_active : 1; + u64 reserved_41_63 : 23; + } s; + /* struct nixx_af_tl2x_green_s cn; */ +}; + +static inline u64 NIXX_AF_TL2X_GREEN(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL2X_GREEN(u64 a) +{ + return 0xe90 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl2#_md_debug0 + * + * NIX AF Transmit Level 2 Meta Descriptor Debug 0 Registers See + * NIX_AF_TL1()_MD_DEBUG0 + */ +union nixx_af_tl2x_md_debug0 { + u64 u; + struct nixx_af_tl2x_md_debug0_s { + u64 pmd0_length : 16; + u64 pmd1_length : 16; + u64 pmd0_vld : 1; + u64 pmd1_vld : 1; + u64 reserved_34_45 : 12; + u64 drain_pri : 1; + u64 drain : 1; + u64 c_con : 1; + u64 p_con : 1; + u64 reserved_50_51 : 2; + u64 child : 10; + u64 reserved_62 : 1; + u64 pmd_count : 1; + } s; + /* struct nixx_af_tl2x_md_debug0_s cn96xxp1; */ + struct nixx_af_tl2x_md_debug0_cn96xxp3 { + u64 pmd0_length : 16; + u64 reserved_16_31 : 16; + u64 pmd0_vld : 1; + u64 reserved_33 : 1; + u64 reserved_34_45 : 12; + u64 reserved_46 : 1; + u64 reserved_47 : 1; + u64 c_con : 1; + u64 p_con : 1; + u64 reserved_50_51 : 2; + u64 child : 10; + u64 reserved_62 : 1; + u64 reserved_63 : 1; + } cn96xxp3; + /* struct nixx_af_tl2x_md_debug0_s cnf95xx; */ +}; + +static inline u64 NIXX_AF_TL2X_MD_DEBUG0(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL2X_MD_DEBUG0(u64 a) +{ + return 0xec0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl2#_md_debug1 + * + * NIX AF Transmit Level 2 Meta Descriptor Debug 1 Registers Packet meta + * descriptor 0 debug. See NIX_AF_TL1()_MD_DEBUG0. + */ +union nixx_af_tl2x_md_debug1 { + u64 u; + struct nixx_af_tl2x_md_debug1_s { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 uid : 4; + u64 reserved_23 : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } s; + struct nixx_af_tl2x_md_debug1_cn96xxp1 { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 uid : 4; + u64 drain : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } cn96xxp1; + struct nixx_af_tl2x_md_debug1_cn96xxp3 { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 reserved_19_22 : 4; + u64 flush : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } cn96xxp3; + /* struct nixx_af_tl2x_md_debug1_cn96xxp1 cnf95xx; */ +}; + +static inline u64 NIXX_AF_TL2X_MD_DEBUG1(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL2X_MD_DEBUG1(u64 a) +{ + return 0xec8 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl2#_md_debug2 + * + * NIX AF Transmit Level 2 Meta Descriptor Debug 2 Registers Packet meta + * descriptor 1 debug. See NIX_AF_TL1()_MD_DEBUG0. + */ +union nixx_af_tl2x_md_debug2 { + u64 u; + struct nixx_af_tl2x_md_debug2_s { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 uid : 4; + u64 reserved_23 : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } s; + struct nixx_af_tl2x_md_debug2_cn96xxp1 { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 uid : 4; + u64 drain : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } cn96xxp1; + struct nixx_af_tl2x_md_debug2_cn96xxp3 { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 reserved_19_22 : 4; + u64 flush : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } cn96xxp3; + /* struct nixx_af_tl2x_md_debug2_cn96xxp1 cnf95xx; */ +}; + +static inline u64 NIXX_AF_TL2X_MD_DEBUG2(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL2X_MD_DEBUG2(u64 a) +{ + return 0xed0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl2#_md_debug3 + * + * NIX AF Transmit Level 2 Meta Descriptor Debug 3 Registers Flush meta + * descriptor debug. See NIX_AF_TL1()_MD_DEBUG0. + */ +union nixx_af_tl2x_md_debug3 { + u64 u; + struct nixx_af_tl2x_md_debug3_s { + u64 reserved_0_36 : 37; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } s; + /* struct nixx_af_tl2x_md_debug3_s cn96xxp1; */ + struct nixx_af_tl2x_md_debug3_cn96xxp3 { + u64 reserved_0_36 : 37; + u64 reserved_37_38 : 2; + u64 reserved_39_51 : 13; + u64 reserved_52_61 : 10; + u64 reserved_62 : 1; + u64 reserved_63 : 1; + } cn96xxp3; + /* struct nixx_af_tl2x_md_debug3_s cnf95xx; */ +}; + +static inline u64 NIXX_AF_TL2X_MD_DEBUG3(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL2X_MD_DEBUG3(u64 a) +{ + return 0xed8 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl2#_parent + * + * NIX AF Transmit Level 2 Parent Registers + */ +union nixx_af_tl2x_parent { + u64 u; + struct nixx_af_tl2x_parent_s { + u64 reserved_0_15 : 16; + u64 parent : 5; + u64 reserved_21_63 : 43; + } s; + /* struct nixx_af_tl2x_parent_s cn; */ +}; + +static inline u64 NIXX_AF_TL2X_PARENT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL2X_PARENT(u64 a) +{ + return 0xe88 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl2#_pir + * + * NIX AF Transmit Level 2 Peak Information Rate Registers This register + * has the same bit fields as NIX_AF_TL1()_CIR. + */ +union nixx_af_tl2x_pir { + u64 u; + struct nixx_af_tl2x_pir_s { + u64 enable : 1; + u64 rate_mantissa : 8; + u64 rate_exponent : 4; + u64 rate_divider_exponent : 4; + u64 reserved_17_28 : 12; + u64 burst_mantissa : 8; + u64 burst_exponent : 4; + u64 reserved_41_63 : 23; + } s; + /* struct nixx_af_tl2x_pir_s cn; */ +}; + +static inline u64 NIXX_AF_TL2X_PIR(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL2X_PIR(u64 a) +{ + return 0xe30 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl2#_pointers + * + * INTERNAL: NIX Transmit Level 2 Linked List Pointers Debug Register + */ +union nixx_af_tl2x_pointers { + u64 u; + struct nixx_af_tl2x_pointers_s { + u64 next : 8; + u64 reserved_8_15 : 8; + u64 prev : 8; + u64 reserved_24_63 : 40; + } s; + /* struct nixx_af_tl2x_pointers_s cn; */ +}; + +static inline u64 NIXX_AF_TL2X_POINTERS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL2X_POINTERS(u64 a) +{ + return 0xe60 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl2#_red + * + * INTERNAL: NIX Transmit Level 2 Red State Debug Register This register + * has the same bit fields as NIX_AF_TL1()_RED. + */ +union nixx_af_tl2x_red { + u64 u; + struct nixx_af_tl2x_red_s { + u64 tail : 8; + u64 reserved_8_9 : 2; + u64 head : 8; + u64 reserved_18_63 : 46; + } s; + /* struct nixx_af_tl2x_red_s cn; */ +}; + +static inline u64 NIXX_AF_TL2X_RED(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL2X_RED(u64 a) +{ + return 0xeb0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl2#_sched_state + * + * NIX AF Transmit Level 2 Scheduling Control State Registers + */ +union nixx_af_tl2x_sched_state { + u64 u; + struct nixx_af_tl2x_sched_state_s { + u64 rr_count : 25; + u64 reserved_25_63 : 39; + } s; + /* struct nixx_af_tl2x_sched_state_s cn; */ +}; + +static inline u64 NIXX_AF_TL2X_SCHED_STATE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL2X_SCHED_STATE(u64 a) +{ + return 0xe40 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl2#_schedule + * + * NIX AF Transmit Level 2 Scheduling Control Registers + */ +union nixx_af_tl2x_schedule { + u64 u; + struct nixx_af_tl2x_schedule_s { + u64 rr_quantum : 24; + u64 prio : 4; + u64 reserved_28_63 : 36; + } s; + /* struct nixx_af_tl2x_schedule_s cn; */ +}; + +static inline u64 NIXX_AF_TL2X_SCHEDULE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL2X_SCHEDULE(u64 a) +{ + return 0xe00 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl2#_shape + * + * NIX AF Transmit Level 2 Shaping Control Registers + */ +union nixx_af_tl2x_shape { + u64 u; + struct nixx_af_tl2x_shape_s { + u64 adjust : 9; + u64 red_algo : 2; + u64 red_disable : 1; + u64 yellow_disable : 1; + u64 reserved_13_23 : 11; + u64 length_disable : 1; + u64 schedule_list : 2; + u64 reserved_27_63 : 37; + } s; + /* struct nixx_af_tl2x_shape_s cn; */ +}; + +static inline u64 NIXX_AF_TL2X_SHAPE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL2X_SHAPE(u64 a) +{ + return 0xe10 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl2#_shape_state + * + * NIX AF Transmit Level 2 Shape State Registers This register must not + * be written during normal operation. + */ +union nixx_af_tl2x_shape_state { + u64 u; + struct nixx_af_tl2x_shape_state_s { + u64 cir_accum : 26; + u64 pir_accum : 26; + u64 color : 2; + u64 reserved_54_63 : 10; + } s; + /* struct nixx_af_tl2x_shape_state_s cn; */ +}; + +static inline u64 NIXX_AF_TL2X_SHAPE_STATE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL2X_SHAPE_STATE(u64 a) +{ + return 0xe50 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl2#_sw_xoff + * + * NIX AF Transmit Level 2 Software Controlled XOFF Registers This + * register has the same bit fields as NIX_AF_TL1()_SW_XOFF. + */ +union nixx_af_tl2x_sw_xoff { + u64 u; + struct nixx_af_tl2x_sw_xoff_s { + u64 xoff : 1; + u64 drain : 1; + u64 reserved_2 : 1; + u64 drain_irq : 1; + u64 reserved_4_63 : 60; + } s; + /* struct nixx_af_tl2x_sw_xoff_s cn; */ +}; + +static inline u64 NIXX_AF_TL2X_SW_XOFF(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL2X_SW_XOFF(u64 a) +{ + return 0xe70 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl2#_topology + * + * NIX AF Transmit Level 2 Topology Registers + */ +union nixx_af_tl2x_topology { + u64 u; + struct nixx_af_tl2x_topology_s { + u64 reserved_0 : 1; + u64 rr_prio : 4; + u64 reserved_5_31 : 27; + u64 prio_anchor : 8; + u64 reserved_40_63 : 24; + } s; + /* struct nixx_af_tl2x_topology_s cn; */ +}; + +static inline u64 NIXX_AF_TL2X_TOPOLOGY(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL2X_TOPOLOGY(u64 a) +{ + return 0xe80 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl2#_yellow + * + * INTERNAL: NIX Transmit Level 2 Yellow State Debug Register This + * register has the same bit fields as NIX_AF_TL1()_YELLOW. + */ +union nixx_af_tl2x_yellow { + u64 u; + struct nixx_af_tl2x_yellow_s { + u64 tail : 8; + u64 reserved_8_9 : 2; + u64 head : 8; + u64 reserved_18_63 : 46; + } s; + /* struct nixx_af_tl2x_yellow_s cn; */ +}; + +static inline u64 NIXX_AF_TL2X_YELLOW(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL2X_YELLOW(u64 a) +{ + return 0xea0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl2_const + * + * NIX AF Transmit Level 2 Constants Register This register contains + * constants for software discovery. + */ +union nixx_af_tl2_const { + u64 u; + struct nixx_af_tl2_const_s { + u64 count : 16; + u64 reserved_16_63 : 48; + } s; + /* struct nixx_af_tl2_const_s cn; */ +}; + +static inline u64 NIXX_AF_TL2_CONST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL2_CONST(void) +{ + return 0x78; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3#_cir + * + * NIX AF Transmit Level 3 Committed Information Rate Registers This + * register has the same bit fields as NIX_AF_TL1()_CIR. + */ +union nixx_af_tl3x_cir { + u64 u; + struct nixx_af_tl3x_cir_s { + u64 enable : 1; + u64 rate_mantissa : 8; + u64 rate_exponent : 4; + u64 rate_divider_exponent : 4; + u64 reserved_17_28 : 12; + u64 burst_mantissa : 8; + u64 burst_exponent : 4; + u64 reserved_41_63 : 23; + } s; + /* struct nixx_af_tl3x_cir_s cn; */ +}; + +static inline u64 NIXX_AF_TL3X_CIR(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3X_CIR(u64 a) +{ + return 0x1020 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3#_green + * + * INTERNAL: NIX Transmit Level 3 Green State Debug Register + */ +union nixx_af_tl3x_green { + u64 u; + struct nixx_af_tl3x_green_s { + u64 tail : 9; + u64 reserved_9 : 1; + u64 head : 9; + u64 reserved_19 : 1; + u64 active_vec : 20; + u64 rr_active : 1; + u64 reserved_41_63 : 23; + } s; + /* struct nixx_af_tl3x_green_s cn; */ +}; + +static inline u64 NIXX_AF_TL3X_GREEN(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3X_GREEN(u64 a) +{ + return 0x1090 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3#_md_debug0 + * + * NIX AF Transmit Level 3 Meta Descriptor Debug 0 Registers See + * NIX_AF_TL1()_MD_DEBUG0. + */ +union nixx_af_tl3x_md_debug0 { + u64 u; + struct nixx_af_tl3x_md_debug0_s { + u64 pmd0_length : 16; + u64 pmd1_length : 16; + u64 pmd0_vld : 1; + u64 pmd1_vld : 1; + u64 reserved_34_45 : 12; + u64 drain_pri : 1; + u64 drain : 1; + u64 c_con : 1; + u64 p_con : 1; + u64 reserved_50_51 : 2; + u64 child : 10; + u64 reserved_62 : 1; + u64 pmd_count : 1; + } s; + /* struct nixx_af_tl3x_md_debug0_s cn96xxp1; */ + struct nixx_af_tl3x_md_debug0_cn96xxp3 { + u64 pmd0_length : 16; + u64 reserved_16_31 : 16; + u64 pmd0_vld : 1; + u64 reserved_33 : 1; + u64 reserved_34_45 : 12; + u64 reserved_46 : 1; + u64 reserved_47 : 1; + u64 c_con : 1; + u64 p_con : 1; + u64 reserved_50_51 : 2; + u64 child : 10; + u64 reserved_62 : 1; + u64 reserved_63 : 1; + } cn96xxp3; + /* struct nixx_af_tl3x_md_debug0_s cnf95xx; */ +}; + +static inline u64 NIXX_AF_TL3X_MD_DEBUG0(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3X_MD_DEBUG0(u64 a) +{ + return 0x10c0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3#_md_debug1 + * + * NIX AF Transmit Level 3 Meta Descriptor Debug 1 Registers Packet meta + * descriptor 0 debug. See NIX_AF_TL1()_MD_DEBUG0. + */ +union nixx_af_tl3x_md_debug1 { + u64 u; + struct nixx_af_tl3x_md_debug1_s { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 uid : 4; + u64 reserved_23 : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } s; + struct nixx_af_tl3x_md_debug1_cn96xxp1 { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 uid : 4; + u64 drain : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } cn96xxp1; + struct nixx_af_tl3x_md_debug1_cn96xxp3 { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 reserved_19_22 : 4; + u64 flush : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } cn96xxp3; + /* struct nixx_af_tl3x_md_debug1_cn96xxp1 cnf95xx; */ +}; + +static inline u64 NIXX_AF_TL3X_MD_DEBUG1(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3X_MD_DEBUG1(u64 a) +{ + return 0x10c8 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3#_md_debug2 + * + * NIX AF Transmit Level 3 Meta Descriptor Debug 2 Registers Packet meta + * descriptor 1 debug. See NIX_AF_TL1()_MD_DEBUG0. + */ +union nixx_af_tl3x_md_debug2 { + u64 u; + struct nixx_af_tl3x_md_debug2_s { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 uid : 4; + u64 reserved_23 : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } s; + struct nixx_af_tl3x_md_debug2_cn96xxp1 { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 uid : 4; + u64 drain : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } cn96xxp1; + struct nixx_af_tl3x_md_debug2_cn96xxp3 { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 reserved_19_22 : 4; + u64 flush : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } cn96xxp3; + /* struct nixx_af_tl3x_md_debug2_cn96xxp1 cnf95xx; */ +}; + +static inline u64 NIXX_AF_TL3X_MD_DEBUG2(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3X_MD_DEBUG2(u64 a) +{ + return 0x10d0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3#_md_debug3 + * + * NIX AF Transmit Level 3 Meta Descriptor Debug 3 Registers Flush meta + * descriptor debug. See NIX_AF_TL1()_MD_DEBUG0. + */ +union nixx_af_tl3x_md_debug3 { + u64 u; + struct nixx_af_tl3x_md_debug3_s { + u64 reserved_0_36 : 37; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } s; + /* struct nixx_af_tl3x_md_debug3_s cn96xxp1; */ + struct nixx_af_tl3x_md_debug3_cn96xxp3 { + u64 reserved_0_36 : 37; + u64 reserved_37_38 : 2; + u64 reserved_39_51 : 13; + u64 reserved_52_61 : 10; + u64 reserved_62 : 1; + u64 reserved_63 : 1; + } cn96xxp3; + /* struct nixx_af_tl3x_md_debug3_s cnf95xx; */ +}; + +static inline u64 NIXX_AF_TL3X_MD_DEBUG3(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3X_MD_DEBUG3(u64 a) +{ + return 0x10d8 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3#_parent + * + * NIX AF Transmit Level 3 Parent Registers + */ +union nixx_af_tl3x_parent { + u64 u; + struct nixx_af_tl3x_parent_s { + u64 reserved_0_15 : 16; + u64 parent : 8; + u64 reserved_24_63 : 40; + } s; + /* struct nixx_af_tl3x_parent_s cn; */ +}; + +static inline u64 NIXX_AF_TL3X_PARENT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3X_PARENT(u64 a) +{ + return 0x1088 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3#_pir + * + * NIX AF Transmit Level 3 Peak Information Rate Registers This register + * has the same bit fields as NIX_AF_TL1()_CIR. + */ +union nixx_af_tl3x_pir { + u64 u; + struct nixx_af_tl3x_pir_s { + u64 enable : 1; + u64 rate_mantissa : 8; + u64 rate_exponent : 4; + u64 rate_divider_exponent : 4; + u64 reserved_17_28 : 12; + u64 burst_mantissa : 8; + u64 burst_exponent : 4; + u64 reserved_41_63 : 23; + } s; + /* struct nixx_af_tl3x_pir_s cn; */ +}; + +static inline u64 NIXX_AF_TL3X_PIR(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3X_PIR(u64 a) +{ + return 0x1030 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3#_pointers + * + * INTERNAL: NIX Transmit Level 3 Linked List Pointers Debug Register + * This register has the same bit fields as NIX_AF_TL2()_POINTERS. + */ +union nixx_af_tl3x_pointers { + u64 u; + struct nixx_af_tl3x_pointers_s { + u64 next : 8; + u64 reserved_8_15 : 8; + u64 prev : 8; + u64 reserved_24_63 : 40; + } s; + /* struct nixx_af_tl3x_pointers_s cn; */ +}; + +static inline u64 NIXX_AF_TL3X_POINTERS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3X_POINTERS(u64 a) +{ + return 0x1060 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3#_red + * + * INTERNAL: NIX Transmit Level 3 Red State Debug Register This register + * has the same bit fields as NIX_AF_TL3()_YELLOW. + */ +union nixx_af_tl3x_red { + u64 u; + struct nixx_af_tl3x_red_s { + u64 tail : 9; + u64 reserved_9 : 1; + u64 head : 9; + u64 reserved_19_63 : 45; + } s; + /* struct nixx_af_tl3x_red_s cn; */ +}; + +static inline u64 NIXX_AF_TL3X_RED(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3X_RED(u64 a) +{ + return 0x10b0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3#_sched_state + * + * NIX AF Transmit Level 3 Scheduling Control State Registers This + * register has the same bit fields as NIX_AF_TL2()_SCHED_STATE. + */ +union nixx_af_tl3x_sched_state { + u64 u; + struct nixx_af_tl3x_sched_state_s { + u64 rr_count : 25; + u64 reserved_25_63 : 39; + } s; + /* struct nixx_af_tl3x_sched_state_s cn; */ +}; + +static inline u64 NIXX_AF_TL3X_SCHED_STATE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3X_SCHED_STATE(u64 a) +{ + return 0x1040 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3#_schedule + * + * NIX AF Transmit Level 3 Scheduling Control Registers This register has + * the same bit fields as NIX_AF_TL2()_SCHEDULE. + */ +union nixx_af_tl3x_schedule { + u64 u; + struct nixx_af_tl3x_schedule_s { + u64 rr_quantum : 24; + u64 prio : 4; + u64 reserved_28_63 : 36; + } s; + /* struct nixx_af_tl3x_schedule_s cn; */ +}; + +static inline u64 NIXX_AF_TL3X_SCHEDULE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3X_SCHEDULE(u64 a) +{ + return 0x1000 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3#_shape + * + * NIX AF Transmit Level 3 Shaping Control Registers + */ +union nixx_af_tl3x_shape { + u64 u; + struct nixx_af_tl3x_shape_s { + u64 adjust : 9; + u64 red_algo : 2; + u64 red_disable : 1; + u64 yellow_disable : 1; + u64 reserved_13_23 : 11; + u64 length_disable : 1; + u64 schedule_list : 2; + u64 reserved_27_63 : 37; + } s; + /* struct nixx_af_tl3x_shape_s cn; */ +}; + +static inline u64 NIXX_AF_TL3X_SHAPE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3X_SHAPE(u64 a) +{ + return 0x1010 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3#_shape_state + * + * NIX AF Transmit Level 3 Shaping State Registers This register has the + * same bit fields as NIX_AF_TL2()_SHAPE_STATE. This register must not be + * written during normal operation. + */ +union nixx_af_tl3x_shape_state { + u64 u; + struct nixx_af_tl3x_shape_state_s { + u64 cir_accum : 26; + u64 pir_accum : 26; + u64 color : 2; + u64 reserved_54_63 : 10; + } s; + /* struct nixx_af_tl3x_shape_state_s cn; */ +}; + +static inline u64 NIXX_AF_TL3X_SHAPE_STATE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3X_SHAPE_STATE(u64 a) +{ + return 0x1050 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3#_sw_xoff + * + * NIX AF Transmit Level 3 Software Controlled XOFF Registers This + * register has the same bit fields as NIX_AF_TL1()_SW_XOFF + */ +union nixx_af_tl3x_sw_xoff { + u64 u; + struct nixx_af_tl3x_sw_xoff_s { + u64 xoff : 1; + u64 drain : 1; + u64 reserved_2 : 1; + u64 drain_irq : 1; + u64 reserved_4_63 : 60; + } s; + /* struct nixx_af_tl3x_sw_xoff_s cn; */ +}; + +static inline u64 NIXX_AF_TL3X_SW_XOFF(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3X_SW_XOFF(u64 a) +{ + return 0x1070 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3#_topology + * + * NIX AF Transmit Level 3 Topology Registers + */ +union nixx_af_tl3x_topology { + u64 u; + struct nixx_af_tl3x_topology_s { + u64 reserved_0 : 1; + u64 rr_prio : 4; + u64 reserved_5_31 : 27; + u64 prio_anchor : 9; + u64 reserved_41_63 : 23; + } s; + /* struct nixx_af_tl3x_topology_s cn; */ +}; + +static inline u64 NIXX_AF_TL3X_TOPOLOGY(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3X_TOPOLOGY(u64 a) +{ + return 0x1080 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3#_yellow + * + * INTERNAL: NIX Transmit Level 3 Yellow State Debug Register + */ +union nixx_af_tl3x_yellow { + u64 u; + struct nixx_af_tl3x_yellow_s { + u64 tail : 9; + u64 reserved_9 : 1; + u64 head : 9; + u64 reserved_19_63 : 45; + } s; + /* struct nixx_af_tl3x_yellow_s cn; */ +}; + +static inline u64 NIXX_AF_TL3X_YELLOW(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3X_YELLOW(u64 a) +{ + return 0x10a0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3_const + * + * NIX AF Transmit Level 3 Constants Register This register contains + * constants for software discovery. + */ +union nixx_af_tl3_const { + u64 u; + struct nixx_af_tl3_const_s { + u64 count : 16; + u64 reserved_16_63 : 48; + } s; + /* struct nixx_af_tl3_const_s cn; */ +}; + +static inline u64 NIXX_AF_TL3_CONST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3_CONST(void) +{ + return 0x80; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3_tl2#_bp_status + * + * NIX AF Transmit Level 3/2 Backpressure Status Registers + */ +union nixx_af_tl3_tl2x_bp_status { + u64 u; + struct nixx_af_tl3_tl2x_bp_status_s { + u64 hw_xoff : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_af_tl3_tl2x_bp_status_s cn; */ +}; + +static inline u64 NIXX_AF_TL3_TL2X_BP_STATUS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3_TL2X_BP_STATUS(u64 a) +{ + return 0x1610 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3_tl2#_cfg + * + * NIX AF Transmit Level 3/2 Configuration Registers + */ +union nixx_af_tl3_tl2x_cfg { + u64 u; + struct nixx_af_tl3_tl2x_cfg_s { + u64 express : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_af_tl3_tl2x_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_TL3_TL2X_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3_TL2X_CFG(u64 a) +{ + return 0x1600 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl3_tl2#_link#_cfg + * + * NIX AF Transmit Level 3/2 Link Configuration Registers These registers + * specify the links and associated channels that a given TL3 or TL2 + * queue (depending on NIX_AF_PSE_CHANNEL_LEVEL[BP_LEVEL]) can transmit + * on. Each TL3/TL2 queue can be enabled to transmit on and be + * backpressured by one or more links and associated channels. The last + * index (LINK) is enumerated by NIX_LINK_E. + */ +union nixx_af_tl3_tl2x_linkx_cfg { + u64 u; + struct nixx_af_tl3_tl2x_linkx_cfg_s { + u64 relchan : 8; + u64 reserved_8_11 : 4; + u64 ena : 1; + u64 bp_ena : 1; + u64 reserved_14_63 : 50; + } s; + /* struct nixx_af_tl3_tl2x_linkx_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_TL3_TL2X_LINKX_CFG(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL3_TL2X_LINKX_CFG(u64 a, u64 b) +{ + return 0x1700 + 0x10000 * a + 8 * b; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4#_bp_status + * + * NIX AF Transmit Level 4 Backpressure Status Registers + */ +union nixx_af_tl4x_bp_status { + u64 u; + struct nixx_af_tl4x_bp_status_s { + u64 hw_xoff : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_af_tl4x_bp_status_s cn; */ +}; + +static inline u64 NIXX_AF_TL4X_BP_STATUS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4X_BP_STATUS(u64 a) +{ + return 0xb00 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4#_cir + * + * NIX AF Transmit Level 4 Committed Information Rate Registers This + * register has the same bit fields as NIX_AF_TL1()_CIR. + */ +union nixx_af_tl4x_cir { + u64 u; + struct nixx_af_tl4x_cir_s { + u64 enable : 1; + u64 rate_mantissa : 8; + u64 rate_exponent : 4; + u64 rate_divider_exponent : 4; + u64 reserved_17_28 : 12; + u64 burst_mantissa : 8; + u64 burst_exponent : 4; + u64 reserved_41_63 : 23; + } s; + /* struct nixx_af_tl4x_cir_s cn; */ +}; + +static inline u64 NIXX_AF_TL4X_CIR(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4X_CIR(u64 a) +{ + return 0x1220 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4#_green + * + * INTERNAL: NIX Transmit Level 4 Green State Debug Register This + * register has the same bit fields as NIX_AF_TL3()_GREEN. + */ +union nixx_af_tl4x_green { + u64 u; + struct nixx_af_tl4x_green_s { + u64 tail : 9; + u64 reserved_9 : 1; + u64 head : 9; + u64 reserved_19 : 1; + u64 active_vec : 20; + u64 rr_active : 1; + u64 reserved_41_63 : 23; + } s; + /* struct nixx_af_tl4x_green_s cn; */ +}; + +static inline u64 NIXX_AF_TL4X_GREEN(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4X_GREEN(u64 a) +{ + return 0x1290 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4#_md_debug0 + * + * NIX AF Transmit Level 4 Meta Descriptor Debug 0 Registers See + * NIX_AF_TL1()_MD_DEBUG0. + */ +union nixx_af_tl4x_md_debug0 { + u64 u; + struct nixx_af_tl4x_md_debug0_s { + u64 pmd0_length : 16; + u64 pmd1_length : 16; + u64 pmd0_vld : 1; + u64 pmd1_vld : 1; + u64 reserved_34_45 : 12; + u64 drain_pri : 1; + u64 drain : 1; + u64 c_con : 1; + u64 p_con : 1; + u64 reserved_50_51 : 2; + u64 child : 10; + u64 reserved_62 : 1; + u64 pmd_count : 1; + } s; + /* struct nixx_af_tl4x_md_debug0_s cn96xxp1; */ + struct nixx_af_tl4x_md_debug0_cn96xxp3 { + u64 pmd0_length : 16; + u64 reserved_16_31 : 16; + u64 pmd0_vld : 1; + u64 reserved_33 : 1; + u64 reserved_34_45 : 12; + u64 reserved_46 : 1; + u64 reserved_47 : 1; + u64 c_con : 1; + u64 p_con : 1; + u64 reserved_50_51 : 2; + u64 child : 10; + u64 reserved_62 : 1; + u64 reserved_63 : 1; + } cn96xxp3; + /* struct nixx_af_tl4x_md_debug0_s cnf95xx; */ +}; + +static inline u64 NIXX_AF_TL4X_MD_DEBUG0(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4X_MD_DEBUG0(u64 a) +{ + return 0x12c0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4#_md_debug1 + * + * NIX AF Transmit Level 4 Meta Descriptor Debug 1 Registers Packet meta + * descriptor 0 debug. See NIX_AF_TL1()_MD_DEBUG0. + */ +union nixx_af_tl4x_md_debug1 { + u64 u; + struct nixx_af_tl4x_md_debug1_s { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 uid : 4; + u64 reserved_23 : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } s; + struct nixx_af_tl4x_md_debug1_cn96xxp1 { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 uid : 4; + u64 drain : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } cn96xxp1; + struct nixx_af_tl4x_md_debug1_cn96xxp3 { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 reserved_19_22 : 4; + u64 flush : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } cn96xxp3; + /* struct nixx_af_tl4x_md_debug1_cn96xxp1 cnf95xx; */ +}; + +static inline u64 NIXX_AF_TL4X_MD_DEBUG1(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4X_MD_DEBUG1(u64 a) +{ + return 0x12c8 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4#_md_debug2 + * + * NIX AF Transmit Level 4 Meta Descriptor Debug 2 Registers Packet meta + * descriptor 1 debug. See NIX_AF_TL1()_MD_DEBUG0. + */ +union nixx_af_tl4x_md_debug2 { + u64 u; + struct nixx_af_tl4x_md_debug2_s { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 uid : 4; + u64 reserved_23 : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } s; + struct nixx_af_tl4x_md_debug2_cn96xxp1 { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 uid : 4; + u64 drain : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } cn96xxp1; + struct nixx_af_tl4x_md_debug2_cn96xxp3 { + u64 reserved_0_5 : 6; + u64 red_algo_override : 2; + u64 cir_dis : 1; + u64 pir_dis : 1; + u64 adjust : 9; + u64 reserved_19_22 : 4; + u64 flush : 1; + u64 bubble : 1; + u64 color : 2; + u64 pse_pkt_id : 9; + u64 reserved_36 : 1; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } cn96xxp3; + /* struct nixx_af_tl4x_md_debug2_cn96xxp1 cnf95xx; */ +}; + +static inline u64 NIXX_AF_TL4X_MD_DEBUG2(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4X_MD_DEBUG2(u64 a) +{ + return 0x12d0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4#_md_debug3 + * + * NIX AF Transmit Level 4 Meta Descriptor Debug 3 Registers Flush meta + * descriptor debug. See NIX_AF_TL1()_MD_DEBUG0. + */ +union nixx_af_tl4x_md_debug3 { + u64 u; + struct nixx_af_tl4x_md_debug3_s { + u64 reserved_0_36 : 37; + u64 tx_pkt_p2x : 2; + u64 sqm_pkt_id : 13; + u64 mdq_idx : 10; + u64 reserved_62 : 1; + u64 vld : 1; + } s; + /* struct nixx_af_tl4x_md_debug3_s cn96xxp1; */ + struct nixx_af_tl4x_md_debug3_cn96xxp3 { + u64 reserved_0_36 : 37; + u64 reserved_37_38 : 2; + u64 reserved_39_51 : 13; + u64 reserved_52_61 : 10; + u64 reserved_62 : 1; + u64 reserved_63 : 1; + } cn96xxp3; + /* struct nixx_af_tl4x_md_debug3_s cnf95xx; */ +}; + +static inline u64 NIXX_AF_TL4X_MD_DEBUG3(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4X_MD_DEBUG3(u64 a) +{ + return 0x12d8 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4#_parent + * + * NIX AF Transmit Level 4 Parent Registers + */ +union nixx_af_tl4x_parent { + u64 u; + struct nixx_af_tl4x_parent_s { + u64 reserved_0_15 : 16; + u64 parent : 8; + u64 reserved_24_63 : 40; + } s; + /* struct nixx_af_tl4x_parent_s cn; */ +}; + +static inline u64 NIXX_AF_TL4X_PARENT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4X_PARENT(u64 a) +{ + return 0x1288 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4#_pir + * + * NIX AF Transmit Level 4 Peak Information Rate Registers This register + * has the same bit fields as NIX_AF_TL1()_CIR. + */ +union nixx_af_tl4x_pir { + u64 u; + struct nixx_af_tl4x_pir_s { + u64 enable : 1; + u64 rate_mantissa : 8; + u64 rate_exponent : 4; + u64 rate_divider_exponent : 4; + u64 reserved_17_28 : 12; + u64 burst_mantissa : 8; + u64 burst_exponent : 4; + u64 reserved_41_63 : 23; + } s; + /* struct nixx_af_tl4x_pir_s cn; */ +}; + +static inline u64 NIXX_AF_TL4X_PIR(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4X_PIR(u64 a) +{ + return 0x1230 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4#_pointers + * + * INTERNAL: NIX Transmit Level 4 Linked List Pointers Debug Register + * This register has the same bit fields as NIX_AF_TL2()_POINTERS. + */ +union nixx_af_tl4x_pointers { + u64 u; + struct nixx_af_tl4x_pointers_s { + u64 next : 9; + u64 reserved_9_15 : 7; + u64 prev : 9; + u64 reserved_25_63 : 39; + } s; + /* struct nixx_af_tl4x_pointers_s cn; */ +}; + +static inline u64 NIXX_AF_TL4X_POINTERS(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4X_POINTERS(u64 a) +{ + return 0x1260 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4#_red + * + * INTERNAL: NIX Transmit Level 4 Red State Debug Register This register + * has the same bit fields as NIX_AF_TL3()_YELLOW. + */ +union nixx_af_tl4x_red { + u64 u; + struct nixx_af_tl4x_red_s { + u64 tail : 9; + u64 reserved_9 : 1; + u64 head : 9; + u64 reserved_19_63 : 45; + } s; + /* struct nixx_af_tl4x_red_s cn; */ +}; + +static inline u64 NIXX_AF_TL4X_RED(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4X_RED(u64 a) +{ + return 0x12b0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4#_sched_state + * + * NIX AF Transmit Level 4 Scheduling Control State Registers This + * register has the same bit fields as NIX_AF_TL2()_SCHED_STATE. + */ +union nixx_af_tl4x_sched_state { + u64 u; + struct nixx_af_tl4x_sched_state_s { + u64 rr_count : 25; + u64 reserved_25_63 : 39; + } s; + /* struct nixx_af_tl4x_sched_state_s cn; */ +}; + +static inline u64 NIXX_AF_TL4X_SCHED_STATE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4X_SCHED_STATE(u64 a) +{ + return 0x1240 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4#_schedule + * + * NIX AF Transmit Level 4 Scheduling Control Registers This register has + * the same bit fields as NIX_AF_TL2()_SCHEDULE. + */ +union nixx_af_tl4x_schedule { + u64 u; + struct nixx_af_tl4x_schedule_s { + u64 rr_quantum : 24; + u64 prio : 4; + u64 reserved_28_63 : 36; + } s; + /* struct nixx_af_tl4x_schedule_s cn; */ +}; + +static inline u64 NIXX_AF_TL4X_SCHEDULE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4X_SCHEDULE(u64 a) +{ + return 0x1200 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4#_sdp_link_cfg + * + * NIX AF Transmit Level 4 Link Configuration Registers These registers + * specify which TL4 queues transmit to and are optionally backpressured + * by SDP. + */ +union nixx_af_tl4x_sdp_link_cfg { + u64 u; + struct nixx_af_tl4x_sdp_link_cfg_s { + u64 relchan : 8; + u64 reserved_8_11 : 4; + u64 ena : 1; + u64 bp_ena : 1; + u64 reserved_14_63 : 50; + } s; + /* struct nixx_af_tl4x_sdp_link_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_TL4X_SDP_LINK_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4X_SDP_LINK_CFG(u64 a) +{ + return 0xb10 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4#_shape + * + * NIX AF Transmit Level 4 Shaping Control Registers This register has + * the same bit fields as NIX_AF_TL2()_SHAPE. + */ +union nixx_af_tl4x_shape { + u64 u; + struct nixx_af_tl4x_shape_s { + u64 adjust : 9; + u64 red_algo : 2; + u64 red_disable : 1; + u64 yellow_disable : 1; + u64 reserved_13_23 : 11; + u64 length_disable : 1; + u64 schedule_list : 2; + u64 reserved_27_63 : 37; + } s; + /* struct nixx_af_tl4x_shape_s cn; */ +}; + +static inline u64 NIXX_AF_TL4X_SHAPE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4X_SHAPE(u64 a) +{ + return 0x1210 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4#_shape_state + * + * NIX AF Transmit Level 4 Shaping State Registers This register has the + * same bit fields as NIX_AF_TL2()_SHAPE_STATE. This register must not be + * written during normal operation. + */ +union nixx_af_tl4x_shape_state { + u64 u; + struct nixx_af_tl4x_shape_state_s { + u64 cir_accum : 26; + u64 pir_accum : 26; + u64 color : 2; + u64 reserved_54_63 : 10; + } s; + /* struct nixx_af_tl4x_shape_state_s cn; */ +}; + +static inline u64 NIXX_AF_TL4X_SHAPE_STATE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4X_SHAPE_STATE(u64 a) +{ + return 0x1250 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4#_sw_xoff + * + * NIX AF Transmit Level 4 Software Controlled XOFF Registers This + * register has the same bit fields as NIX_AF_TL1()_SW_XOFF + */ +union nixx_af_tl4x_sw_xoff { + u64 u; + struct nixx_af_tl4x_sw_xoff_s { + u64 xoff : 1; + u64 drain : 1; + u64 reserved_2 : 1; + u64 drain_irq : 1; + u64 reserved_4_63 : 60; + } s; + /* struct nixx_af_tl4x_sw_xoff_s cn; */ +}; + +static inline u64 NIXX_AF_TL4X_SW_XOFF(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4X_SW_XOFF(u64 a) +{ + return 0x1270 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4#_topology + * + * NIX AF Transmit Level 4 Topology Registers + */ +union nixx_af_tl4x_topology { + u64 u; + struct nixx_af_tl4x_topology_s { + u64 reserved_0 : 1; + u64 rr_prio : 4; + u64 reserved_5_31 : 27; + u64 prio_anchor : 9; + u64 reserved_41_63 : 23; + } s; + /* struct nixx_af_tl4x_topology_s cn; */ +}; + +static inline u64 NIXX_AF_TL4X_TOPOLOGY(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4X_TOPOLOGY(u64 a) +{ + return 0x1280 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4#_yellow + * + * INTERNAL: NIX Transmit Level 4 Yellow State Debug Register This + * register has the same bit fields as NIX_AF_TL3()_YELLOW + */ +union nixx_af_tl4x_yellow { + u64 u; + struct nixx_af_tl4x_yellow_s { + u64 tail : 9; + u64 reserved_9 : 1; + u64 head : 9; + u64 reserved_19_63 : 45; + } s; + /* struct nixx_af_tl4x_yellow_s cn; */ +}; + +static inline u64 NIXX_AF_TL4X_YELLOW(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4X_YELLOW(u64 a) +{ + return 0x12a0 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tl4_const + * + * NIX AF Transmit Level 4 Constants Register This register contains + * constants for software discovery. + */ +union nixx_af_tl4_const { + u64 u; + struct nixx_af_tl4_const_s { + u64 count : 16; + u64 reserved_16_63 : 48; + } s; + /* struct nixx_af_tl4_const_s cn; */ +}; + +static inline u64 NIXX_AF_TL4_CONST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TL4_CONST(void) +{ + return 0x88; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tx_link#_expr_credit + * + * INTERNAL: NIX AF Transmit Link Express Credit Registers Internal: + * 802.3br frame preemption/express path is defeatured. Old definition: + * These registers track credits per link for express packets that may + * potentially preempt normal packets. Link index enumerated by + * NIX_LINK_E. + */ +union nixx_af_tx_linkx_expr_credit { + u64 u; + struct nixx_af_tx_linkx_expr_credit_s { + u64 reserved_0 : 1; + u64 cc_enable : 1; + u64 cc_packet_cnt : 10; + u64 cc_unit_cnt : 20; + u64 reserved_32_63 : 32; + } s; + /* struct nixx_af_tx_linkx_expr_credit_s cn; */ +}; + +static inline u64 NIXX_AF_TX_LINKX_EXPR_CREDIT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TX_LINKX_EXPR_CREDIT(u64 a) +{ + return 0xa10 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tx_link#_hw_xoff + * + * NIX AF Transmit Link Hardware Controlled XOFF Registers Link index + * enumerated by NIX_LINK_E. + */ +union nixx_af_tx_linkx_hw_xoff { + u64 u; + struct nixx_af_tx_linkx_hw_xoff_s { + u64 chan_xoff : 64; + } s; + /* struct nixx_af_tx_linkx_hw_xoff_s cn; */ +}; + +static inline u64 NIXX_AF_TX_LINKX_HW_XOFF(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TX_LINKX_HW_XOFF(u64 a) +{ + return 0xa30 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tx_link#_norm_credit + * + * NIX AF Transmit Link Normal Credit Registers These registers track + * credits per link for normal packets sent to CGX and LBK. Link index + * enumerated by NIX_LINK_E. + */ +union nixx_af_tx_linkx_norm_credit { + u64 u; + struct nixx_af_tx_linkx_norm_credit_s { + u64 reserved_0 : 1; + u64 cc_enable : 1; + u64 cc_packet_cnt : 10; + u64 cc_unit_cnt : 20; + u64 reserved_32_63 : 32; + } s; + /* struct nixx_af_tx_linkx_norm_credit_s cn; */ +}; + +static inline u64 NIXX_AF_TX_LINKX_NORM_CREDIT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TX_LINKX_NORM_CREDIT(u64 a) +{ + return 0xa00 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tx_link#_sw_xoff + * + * INTERNAL: NIX AF Transmit Link Software Controlled XOFF Registers + * Link index enumerated by NIX_LINK_E. Internal: Defeatured registers. + * Software should instead use NIX_AF_TL3()_SW_XOFF registers when + * NIX_AF_PSE_CHANNEL_LEVEL[BP_LEVEL] is set and NIX_AF_TL2()_SW_XOFF + * registers when NIX_AF_PSE_CHANNEL_LEVEL[BP_LEVEL] is clear. + */ +union nixx_af_tx_linkx_sw_xoff { + u64 u; + struct nixx_af_tx_linkx_sw_xoff_s { + u64 chan_xoff : 64; + } s; + /* struct nixx_af_tx_linkx_sw_xoff_s cn; */ +}; + +static inline u64 NIXX_AF_TX_LINKX_SW_XOFF(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TX_LINKX_SW_XOFF(u64 a) +{ + return 0xa20 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tx_mcast# + * + * NIX AF Transmit Multicast Registers These registers access transmit + * multicast table entries used to specify multicast replication lists. + * Each list consists of linked entries with [EOL] = 1 in the last entry. + * A transmit packet is multicast when the action returned by NPC has + * NIX_TX_ACTION_S[OP] = NIX_TX_ACTIONOP_E::MCAST. NIX_TX_ACTION_S[INDEX] + * points to the start of the multicast replication list, and [EOL] = 1 + * indicates the end of list. + */ +union nixx_af_tx_mcastx { + u64 u; + struct nixx_af_tx_mcastx_s { + u64 channel : 12; + u64 eol : 1; + u64 reserved_13_15 : 3; + u64 next : 16; + u64 reserved_32_63 : 32; + } s; + /* struct nixx_af_tx_mcastx_s cn; */ +}; + +static inline u64 NIXX_AF_TX_MCASTX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TX_MCASTX(u64 a) +{ + return 0x1900 + 0x8000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tx_npc_capture_config + * + * NIX AF Transmit NPC Response Capture Configuration Register Configures + * the NPC response capture logic for transmit packets. When enabled, + * allows NPC responses for selected packets to be captured in + * NIX_AF_TX_NPC_CAPTURE_INFO and NIX_AF_TX_NPC_CAPTURE_RESP(). + */ +union nixx_af_tx_npc_capture_config { + u64 u; + struct nixx_af_tx_npc_capture_config_s { + u64 en : 1; + u64 continuous : 1; + u64 lso_segnum_en : 1; + u64 sqe_id_en : 1; + u64 sq_id_en : 1; + u64 lf_id_en : 1; + u64 reserved_6_11 : 6; + u64 lso_segnum : 8; + u64 sqe_id : 16; + u64 sq_id : 20; + u64 lf_id : 8; + } s; + /* struct nixx_af_tx_npc_capture_config_s cn; */ +}; + +static inline u64 NIXX_AF_TX_NPC_CAPTURE_CONFIG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TX_NPC_CAPTURE_CONFIG(void) +{ + return 0x660; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tx_npc_capture_info + * + * NIX AF Transmit NPC Response Capture Information Register This + * register contains captured NPC response information for a transmit + * packet. See NIX_AF_TX_NPC_CAPTURE_CONFIG. + */ +union nixx_af_tx_npc_capture_info { + u64 u; + struct nixx_af_tx_npc_capture_info_s { + u64 vld : 1; + u64 reserved_1_11 : 11; + u64 lso_segnum : 8; + u64 sqe_id : 16; + u64 sq_id : 20; + u64 lf_id : 8; + } s; + /* struct nixx_af_tx_npc_capture_info_s cn; */ +}; + +static inline u64 NIXX_AF_TX_NPC_CAPTURE_INFO(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TX_NPC_CAPTURE_INFO(void) +{ + return 0x668; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tx_npc_capture_resp# + * + * NIX AF Transmit NPC Capture Response Registers These registers contain + * the captured NPC response for a transmit packet when + * NIX_AF_TX_NPC_CAPTURE_INFO[VLD] is set. See also + * NIX_AF_TX_NPC_CAPTURE_CONFIG. + */ +union nixx_af_tx_npc_capture_respx { + u64 u; + struct nixx_af_tx_npc_capture_respx_s { + u64 data : 64; + } s; + /* struct nixx_af_tx_npc_capture_respx_s cn; */ +}; + +static inline u64 NIXX_AF_TX_NPC_CAPTURE_RESPX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TX_NPC_CAPTURE_RESPX(u64 a) +{ + return 0x680 + 8 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tx_tstmp_cfg + * + * NIX AF Transmit Timestamp Configuration Register + */ +union nixx_af_tx_tstmp_cfg { + u64 u; + struct nixx_af_tx_tstmp_cfg_s { + u64 tstmp_wd_period : 4; + u64 reserved_4_7 : 4; + u64 express : 16; + u64 reserved_24_63 : 40; + } s; + /* struct nixx_af_tx_tstmp_cfg_s cn; */ +}; + +static inline u64 NIXX_AF_TX_TSTMP_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TX_TSTMP_CFG(void) +{ + return 0xc0; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tx_vtag_def#_ctl + * + * NIX AF Transmit Vtag Definition Control Registers The transmit Vtag + * definition table specifies Vtag layers (e.g. VLAN, E-TAG) to + * optionally insert or replace in the TX packet header. Indexed by + * NIX_TX_VTAG_ACTION_S[VTAG*_DEF]. + */ +union nixx_af_tx_vtag_defx_ctl { + u64 u; + struct nixx_af_tx_vtag_defx_ctl_s { + u64 size : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_af_tx_vtag_defx_ctl_s cn; */ +}; + +static inline u64 NIXX_AF_TX_VTAG_DEFX_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TX_VTAG_DEFX_CTL(u64 a) +{ + return 0x1a00 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_af_tx_vtag_def#_data + * + * NIX AF Transmit Vtag Definition Data Registers See + * NIX_AF_TX_VTAG_DEF()_CTL. + */ +union nixx_af_tx_vtag_defx_data { + u64 u; + struct nixx_af_tx_vtag_defx_data_s { + u64 data : 64; + } s; + /* struct nixx_af_tx_vtag_defx_data_s cn; */ +}; + +static inline u64 NIXX_AF_TX_VTAG_DEFX_DATA(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_AF_TX_VTAG_DEFX_DATA(u64 a) +{ + return 0x1a10 + 0x10000 * a; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_cfg + * + * NIX LF Configuration Register + */ +union nixx_lf_cfg { + u64 u; + struct nixx_lf_cfg_s { + u64 tcp_timer_int_ena : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_lf_cfg_s cn; */ +}; + +static inline u64 NIXX_LF_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_CFG(void) +{ + return 0x100; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_cint#_cnt + * + * NIX LF Completion Interrupt Count Registers + */ +union nixx_lf_cintx_cnt { + u64 u; + struct nixx_lf_cintx_cnt_s { + u64 ecount : 32; + u64 qcount : 16; + u64 reserved_48_63 : 16; + } s; + /* struct nixx_lf_cintx_cnt_s cn; */ +}; + +static inline u64 NIXX_LF_CINTX_CNT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_CINTX_CNT(u64 a) +{ + return 0xd00 + 0x1000 * a; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_cint#_ena_w1c + * + * NIX LF Completion Interrupt Enable Clear Registers This register + * clears interrupt enable bits. + */ +union nixx_lf_cintx_ena_w1c { + u64 u; + struct nixx_lf_cintx_ena_w1c_s { + u64 intr : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_lf_cintx_ena_w1c_s cn; */ +}; + +static inline u64 NIXX_LF_CINTX_ENA_W1C(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_CINTX_ENA_W1C(u64 a) +{ + return 0xd50 + 0x1000 * a; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_cint#_ena_w1s + * + * NIX LF Completion Interrupt Enable Set Registers This register sets + * interrupt enable bits. + */ +union nixx_lf_cintx_ena_w1s { + u64 u; + struct nixx_lf_cintx_ena_w1s_s { + u64 intr : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_lf_cintx_ena_w1s_s cn; */ +}; + +static inline u64 NIXX_LF_CINTX_ENA_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_CINTX_ENA_W1S(u64 a) +{ + return 0xd40 + 0x1000 * a; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_cint#_int + * + * NIX LF Completion Interrupt Registers + */ +union nixx_lf_cintx_int { + u64 u; + struct nixx_lf_cintx_int_s { + u64 intr : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_lf_cintx_int_s cn; */ +}; + +static inline u64 NIXX_LF_CINTX_INT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_CINTX_INT(u64 a) +{ + return 0xd20 + 0x1000 * a; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_cint#_int_w1s + * + * NIX LF Completion Interrupt Set Registers This register sets interrupt + * bits. + */ +union nixx_lf_cintx_int_w1s { + u64 u; + struct nixx_lf_cintx_int_w1s_s { + u64 intr : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_lf_cintx_int_w1s_s cn; */ +}; + +static inline u64 NIXX_LF_CINTX_INT_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_CINTX_INT_W1S(u64 a) +{ + return 0xd30 + 0x1000 * a; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_cint#_wait + * + * NIX LF Completion Interrupt Count Registers + */ +union nixx_lf_cintx_wait { + u64 u; + struct nixx_lf_cintx_wait_s { + u64 ecount_wait : 32; + u64 qcount_wait : 16; + u64 time_wait : 8; + u64 reserved_56_63 : 8; + } s; + /* struct nixx_lf_cintx_wait_s cn; */ +}; + +static inline u64 NIXX_LF_CINTX_WAIT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_CINTX_WAIT(u64 a) +{ + return 0xd10 + 0x1000 * a; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_cq_op_door + * + * NIX LF CQ Doorbell Operation Register A write to this register + * dequeues CQEs from a CQ ring within the LF. A read is RAZ. RSL + * accesses to this register are RAZ/WI. + */ +union nixx_lf_cq_op_door { + u64 u; + struct nixx_lf_cq_op_door_s { + u64 count : 16; + u64 reserved_16_31 : 16; + u64 cq : 20; + u64 reserved_52_63 : 12; + } s; + /* struct nixx_lf_cq_op_door_s cn; */ +}; + +static inline u64 NIXX_LF_CQ_OP_DOOR(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_CQ_OP_DOOR(void) +{ + return 0xb30; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_cq_op_int + * + * NIX LF Completion Queue Interrupt Operation Register A 64-bit atomic + * load-and-add to this register reads CQ interrupts and interrupt + * enables. A write optionally sets or clears interrupts and interrupt + * enables. A read is RAZ. RSL accesses to this register are RAZ/WI. + */ +union nixx_lf_cq_op_int { + u64 u; + struct nixx_lf_cq_op_int_s { + u64 cq_err_int : 8; + u64 cq_err_int_ena : 8; + u64 reserved_16_41 : 26; + u64 op_err : 1; + u64 setop : 1; + u64 cq : 20; + } s; + /* struct nixx_lf_cq_op_int_s cn; */ +}; + +static inline u64 NIXX_LF_CQ_OP_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_CQ_OP_INT(void) +{ + return 0xb00; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_cq_op_status + * + * NIX LF Completion Queue Status Operation Register A 64-bit atomic + * load-and-add to this register reads NIX_CQ_CTX_S[HEAD,TAIL]. The + * atomic write data has format NIX_OP_Q_WDATA_S and selects the CQ + * within LF. All other accesses to this register (e.g. reads and + * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI. + */ +union nixx_lf_cq_op_status { + u64 u; + struct nixx_lf_cq_op_status_s { + u64 tail : 20; + u64 head : 20; + u64 reserved_40_45 : 6; + u64 cq_err : 1; + u64 reserved_47_62 : 16; + u64 op_err : 1; + } s; + /* struct nixx_lf_cq_op_status_s cn; */ +}; + +static inline u64 NIXX_LF_CQ_OP_STATUS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_CQ_OP_STATUS(void) +{ + return 0xb40; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_err_int + * + * NIX LF Error Interrupt Register + */ +union nixx_lf_err_int { + u64 u; + struct nixx_lf_err_int_s { + u64 sqb_fault : 1; + u64 sq_ctx_fault : 1; + u64 rq_ctx_fault : 1; + u64 cq_ctx_fault : 1; + u64 reserved_4 : 1; + u64 rsse_fault : 1; + u64 ipsec_dyno_fault : 1; + u64 sq_disabled : 1; + u64 sq_oor : 1; + u64 send_jump_fault : 1; + u64 send_sg_fault : 1; + u64 rq_disabled : 1; + u64 rq_oor : 1; + u64 rx_wqe_fault : 1; + u64 rss_err : 1; + u64 reserved_15_19 : 5; + u64 dyno_err : 1; + u64 reserved_21_23 : 3; + u64 cq_disabled : 1; + u64 cq_oor : 1; + u64 reserved_26_27 : 2; + u64 qint_fault : 1; + u64 cint_fault : 1; + u64 reserved_30_63 : 34; + } s; + /* struct nixx_lf_err_int_s cn; */ +}; + +static inline u64 NIXX_LF_ERR_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_ERR_INT(void) +{ + return 0x220; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_err_int_ena_w1c + * + * NIX LF Error Interrupt Enable Clear Register This register clears + * interrupt enable bits. + */ +union nixx_lf_err_int_ena_w1c { + u64 u; + struct nixx_lf_err_int_ena_w1c_s { + u64 sqb_fault : 1; + u64 sq_ctx_fault : 1; + u64 rq_ctx_fault : 1; + u64 cq_ctx_fault : 1; + u64 reserved_4 : 1; + u64 rsse_fault : 1; + u64 ipsec_dyno_fault : 1; + u64 sq_disabled : 1; + u64 sq_oor : 1; + u64 send_jump_fault : 1; + u64 send_sg_fault : 1; + u64 rq_disabled : 1; + u64 rq_oor : 1; + u64 rx_wqe_fault : 1; + u64 rss_err : 1; + u64 reserved_15_19 : 5; + u64 dyno_err : 1; + u64 reserved_21_23 : 3; + u64 cq_disabled : 1; + u64 cq_oor : 1; + u64 reserved_26_27 : 2; + u64 qint_fault : 1; + u64 cint_fault : 1; + u64 reserved_30_63 : 34; + } s; + /* struct nixx_lf_err_int_ena_w1c_s cn; */ +}; + +static inline u64 NIXX_LF_ERR_INT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_ERR_INT_ENA_W1C(void) +{ + return 0x230; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_err_int_ena_w1s + * + * NIX LF Error Interrupt Enable Set Register This register sets + * interrupt enable bits. + */ +union nixx_lf_err_int_ena_w1s { + u64 u; + struct nixx_lf_err_int_ena_w1s_s { + u64 sqb_fault : 1; + u64 sq_ctx_fault : 1; + u64 rq_ctx_fault : 1; + u64 cq_ctx_fault : 1; + u64 reserved_4 : 1; + u64 rsse_fault : 1; + u64 ipsec_dyno_fault : 1; + u64 sq_disabled : 1; + u64 sq_oor : 1; + u64 send_jump_fault : 1; + u64 send_sg_fault : 1; + u64 rq_disabled : 1; + u64 rq_oor : 1; + u64 rx_wqe_fault : 1; + u64 rss_err : 1; + u64 reserved_15_19 : 5; + u64 dyno_err : 1; + u64 reserved_21_23 : 3; + u64 cq_disabled : 1; + u64 cq_oor : 1; + u64 reserved_26_27 : 2; + u64 qint_fault : 1; + u64 cint_fault : 1; + u64 reserved_30_63 : 34; + } s; + /* struct nixx_lf_err_int_ena_w1s_s cn; */ +}; + +static inline u64 NIXX_LF_ERR_INT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_ERR_INT_ENA_W1S(void) +{ + return 0x238; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_err_int_w1s + * + * NIX LF Error Interrupt Set Register This register sets interrupt bits. + */ +union nixx_lf_err_int_w1s { + u64 u; + struct nixx_lf_err_int_w1s_s { + u64 sqb_fault : 1; + u64 sq_ctx_fault : 1; + u64 rq_ctx_fault : 1; + u64 cq_ctx_fault : 1; + u64 reserved_4 : 1; + u64 rsse_fault : 1; + u64 ipsec_dyno_fault : 1; + u64 sq_disabled : 1; + u64 sq_oor : 1; + u64 send_jump_fault : 1; + u64 send_sg_fault : 1; + u64 rq_disabled : 1; + u64 rq_oor : 1; + u64 rx_wqe_fault : 1; + u64 rss_err : 1; + u64 reserved_15_19 : 5; + u64 dyno_err : 1; + u64 reserved_21_23 : 3; + u64 cq_disabled : 1; + u64 cq_oor : 1; + u64 reserved_26_27 : 2; + u64 qint_fault : 1; + u64 cint_fault : 1; + u64 reserved_30_63 : 34; + } s; + /* struct nixx_lf_err_int_w1s_s cn; */ +}; + +static inline u64 NIXX_LF_ERR_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_ERR_INT_W1S(void) +{ + return 0x228; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_gint + * + * NIX LF General Interrupt Register + */ +union nixx_lf_gint { + u64 u; + struct nixx_lf_gint_s { + u64 drop : 1; + u64 tcp_timer : 1; + u64 reserved_2_63 : 62; + } s; + /* struct nixx_lf_gint_s cn; */ +}; + +static inline u64 NIXX_LF_GINT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_GINT(void) +{ + return 0x200; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_gint_ena_w1c + * + * NIX LF General Interrupt Enable Clear Register This register clears + * interrupt enable bits. + */ +union nixx_lf_gint_ena_w1c { + u64 u; + struct nixx_lf_gint_ena_w1c_s { + u64 drop : 1; + u64 tcp_timer : 1; + u64 reserved_2_63 : 62; + } s; + /* struct nixx_lf_gint_ena_w1c_s cn; */ +}; + +static inline u64 NIXX_LF_GINT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_GINT_ENA_W1C(void) +{ + return 0x210; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_gint_ena_w1s + * + * NIX LF General Interrupt Enable Set Register This register sets + * interrupt enable bits. + */ +union nixx_lf_gint_ena_w1s { + u64 u; + struct nixx_lf_gint_ena_w1s_s { + u64 drop : 1; + u64 tcp_timer : 1; + u64 reserved_2_63 : 62; + } s; + /* struct nixx_lf_gint_ena_w1s_s cn; */ +}; + +static inline u64 NIXX_LF_GINT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_GINT_ENA_W1S(void) +{ + return 0x218; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_gint_w1s + * + * NIX LF General Interrupt Set Register This register sets interrupt + * bits. + */ +union nixx_lf_gint_w1s { + u64 u; + struct nixx_lf_gint_w1s_s { + u64 drop : 1; + u64 tcp_timer : 1; + u64 reserved_2_63 : 62; + } s; + /* struct nixx_lf_gint_w1s_s cn; */ +}; + +static inline u64 NIXX_LF_GINT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_GINT_W1S(void) +{ + return 0x208; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_mnq_err_dbg + * + * NIX LF Meta-descriptor Enqueue Error Debug Register This register + * captures debug info for an error detected during send meta-descriptor + * enqueue from an SQ to an SMQ. Hardware sets [VALID] when the debug + * info is captured, and subsequent errors are not captured until + * software clears [VALID] by writing a one to it. + */ +union nixx_lf_mnq_err_dbg { + u64 u; + struct nixx_lf_mnq_err_dbg_s { + u64 errcode : 8; + u64 sq : 20; + u64 sqe_id : 16; + u64 valid : 1; + u64 reserved_45_63 : 19; + } s; + /* struct nixx_lf_mnq_err_dbg_s cn; */ +}; + +static inline u64 NIXX_LF_MNQ_ERR_DBG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_MNQ_ERR_DBG(void) +{ + return 0x270; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_op_ipsec_dyno_cnt + * + * INTERNAL: NIX LF IPSEC Dynamic Ordering Counter Operation Register + * Internal: Not used; no IPSEC fast-path. All accesses are RAZ/WI. + */ +union nixx_lf_op_ipsec_dyno_cnt { + u64 u; + struct nixx_lf_op_ipsec_dyno_cnt_s { + u64 count : 32; + u64 reserved_32_46 : 15; + u64 storeop : 1; + u64 dyno_sel : 15; + u64 op_err : 1; + } s; + /* struct nixx_lf_op_ipsec_dyno_cnt_s cn; */ +}; + +static inline u64 NIXX_LF_OP_IPSEC_DYNO_CNT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_OP_IPSEC_DYNO_CNT(void) +{ + return 0x980; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_op_send# + * + * NIX LF Send Operation Registers An LMTST (or large store from CPT) to + * this address enqueues one or more SQEs to a send queue. + * NIX_SEND_HDR_S[SQ] in the first SQE selects the send queue.The maximum + * size of each SQE is specified by NIX_SQ_CTX_S[MAX_SQE_SIZE]. A read + * to this address is RAZ. An RSL access to this address will fault. + * The endianness of the instruction write data is controlled by + * NIX_AF_LF()_CFG[BE]. When a NIX_SEND_JUMP_S is not present in the + * SQE, the SQE consists of the entire send descriptor. When a + * NIX_SEND_JUMP_S is present in the SQE, the SQE must contain exactly + * the portion of the send descriptor up to and including the + * NIX_SEND_JUMP_S, and the remainder of the send descriptor must be at + * LF IOVA NIX_SEND_JUMP_S[ADDR] in LLC/DRAM. Software must ensure that + * all LLC/DRAM locations that will be referenced by NIX while processing + * this descriptor, including all packet data and post-jump + * subdescriptors contain the latest updates before issuing the LMTST. A + * DMB instruction may be required prior to the LMTST to ensure this. A + * DMB following the LMTST may be useful if SQ descriptor ordering + * matters and more than one CPU core is simultaneously enqueueing to the + * same SQ. + */ +union nixx_lf_op_sendx { + u64 u; + struct nixx_lf_op_sendx_s { + u64 data : 64; + } s; + /* struct nixx_lf_op_sendx_s cn; */ +}; + +static inline u64 NIXX_LF_OP_SENDX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_OP_SENDX(u64 a) +{ + return 0x800 + 8 * a; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_qint#_cnt + * + * NIX LF Queue Interrupt Count Registers + */ +union nixx_lf_qintx_cnt { + u64 u; + struct nixx_lf_qintx_cnt_s { + u64 count : 22; + u64 reserved_22_63 : 42; + } s; + /* struct nixx_lf_qintx_cnt_s cn; */ +}; + +static inline u64 NIXX_LF_QINTX_CNT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_QINTX_CNT(u64 a) +{ + return 0xc00 + 0x1000 * a; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_qint#_ena_w1c + * + * NIX LF Queue Interrupt Enable Clear Registers This register clears + * interrupt enable bits. + */ +union nixx_lf_qintx_ena_w1c { + u64 u; + struct nixx_lf_qintx_ena_w1c_s { + u64 intr : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_lf_qintx_ena_w1c_s cn; */ +}; + +static inline u64 NIXX_LF_QINTX_ENA_W1C(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_QINTX_ENA_W1C(u64 a) +{ + return 0xc30 + 0x1000 * a; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_qint#_ena_w1s + * + * NIX LF Queue Interrupt Enable Set Registers This register sets + * interrupt enable bits. + */ +union nixx_lf_qintx_ena_w1s { + u64 u; + struct nixx_lf_qintx_ena_w1s_s { + u64 intr : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_lf_qintx_ena_w1s_s cn; */ +}; + +static inline u64 NIXX_LF_QINTX_ENA_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_QINTX_ENA_W1S(u64 a) +{ + return 0xc20 + 0x1000 * a; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_qint#_int + * + * NIX LF Queue Interrupt Registers + */ +union nixx_lf_qintx_int { + u64 u; + struct nixx_lf_qintx_int_s { + u64 intr : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_lf_qintx_int_s cn; */ +}; + +static inline u64 NIXX_LF_QINTX_INT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_QINTX_INT(u64 a) +{ + return 0xc10 + 0x1000 * a; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_qint#_int_w1s + * + * INTERNAL: NIX LF Queue Interrupt Set Registers + */ +union nixx_lf_qintx_int_w1s { + u64 u; + struct nixx_lf_qintx_int_w1s_s { + u64 intr : 1; + u64 reserved_1_63 : 63; + } s; + /* struct nixx_lf_qintx_int_w1s_s cn; */ +}; + +static inline u64 NIXX_LF_QINTX_INT_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_QINTX_INT_W1S(u64 a) +{ + return 0xc18 + 0x1000 * a; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_ras + * + * NIX LF RAS Interrupt Register + */ +union nixx_lf_ras { + u64 u; + struct nixx_lf_ras_s { + u64 sqb_poison : 1; + u64 sq_ctx_poison : 1; + u64 rq_ctx_poison : 1; + u64 cq_ctx_poison : 1; + u64 reserved_4 : 1; + u64 rsse_poison : 1; + u64 ipsec_dyno_poison : 1; + u64 send_jump_poison : 1; + u64 send_sg_poison : 1; + u64 qint_poison : 1; + u64 cint_poison : 1; + u64 reserved_11_63 : 53; + } s; + /* struct nixx_lf_ras_s cn; */ +}; + +static inline u64 NIXX_LF_RAS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_RAS(void) +{ + return 0x240; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_ras_ena_w1c + * + * NIX LF RAS Interrupt Enable Clear Register This register clears + * interrupt enable bits. + */ +union nixx_lf_ras_ena_w1c { + u64 u; + struct nixx_lf_ras_ena_w1c_s { + u64 sqb_poison : 1; + u64 sq_ctx_poison : 1; + u64 rq_ctx_poison : 1; + u64 cq_ctx_poison : 1; + u64 reserved_4 : 1; + u64 rsse_poison : 1; + u64 ipsec_dyno_poison : 1; + u64 send_jump_poison : 1; + u64 send_sg_poison : 1; + u64 qint_poison : 1; + u64 cint_poison : 1; + u64 reserved_11_63 : 53; + } s; + /* struct nixx_lf_ras_ena_w1c_s cn; */ +}; + +static inline u64 NIXX_LF_RAS_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_RAS_ENA_W1C(void) +{ + return 0x250; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_ras_ena_w1s + * + * NIX LF RAS Interrupt Enable Set Register This register sets interrupt + * enable bits. + */ +union nixx_lf_ras_ena_w1s { + u64 u; + struct nixx_lf_ras_ena_w1s_s { + u64 sqb_poison : 1; + u64 sq_ctx_poison : 1; + u64 rq_ctx_poison : 1; + u64 cq_ctx_poison : 1; + u64 reserved_4 : 1; + u64 rsse_poison : 1; + u64 ipsec_dyno_poison : 1; + u64 send_jump_poison : 1; + u64 send_sg_poison : 1; + u64 qint_poison : 1; + u64 cint_poison : 1; + u64 reserved_11_63 : 53; + } s; + /* struct nixx_lf_ras_ena_w1s_s cn; */ +}; + +static inline u64 NIXX_LF_RAS_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_RAS_ENA_W1S(void) +{ + return 0x258; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_ras_w1s + * + * NIX LF RAS Interrupt Set Register This register sets interrupt bits. + */ +union nixx_lf_ras_w1s { + u64 u; + struct nixx_lf_ras_w1s_s { + u64 sqb_poison : 1; + u64 sq_ctx_poison : 1; + u64 rq_ctx_poison : 1; + u64 cq_ctx_poison : 1; + u64 reserved_4 : 1; + u64 rsse_poison : 1; + u64 ipsec_dyno_poison : 1; + u64 send_jump_poison : 1; + u64 send_sg_poison : 1; + u64 qint_poison : 1; + u64 cint_poison : 1; + u64 reserved_11_63 : 53; + } s; + /* struct nixx_lf_ras_w1s_s cn; */ +}; + +static inline u64 NIXX_LF_RAS_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_RAS_W1S(void) +{ + return 0x248; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_drop_octs + * + * NIX LF Receive Queue Dropped Octets Operation Register A 64-bit atomic + * load-and-add to this register reads NIX_RQ_CTX_S[DROP_OCTS]. The + * atomic write data has format NIX_OP_Q_WDATA_S and selects the RQ + * within LF. All other accesses to this register (e.g. reads and + * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI. + */ +union nixx_lf_rq_op_drop_octs { + u64 u; + struct nixx_lf_rq_op_drop_octs_s { + u64 cnt : 48; + u64 reserved_48_62 : 15; + u64 op_err : 1; + } s; + /* struct nixx_lf_rq_op_drop_octs_s cn; */ +}; + +static inline u64 NIXX_LF_RQ_OP_DROP_OCTS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_RQ_OP_DROP_OCTS(void) +{ + return 0x930; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_drop_pkts + * + * NIX LF Receive Queue Dropped Packets Operation Register A 64-bit + * atomic load-and-add to this register reads NIX_RQ_CTX_S[DROP_PKTS]. + * The atomic write data has format NIX_OP_Q_WDATA_S and selects the RQ + * within LF. All other accesses to this register (e.g. reads and + * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI. + */ +union nixx_lf_rq_op_drop_pkts { + u64 u; + struct nixx_lf_rq_op_drop_pkts_s { + u64 cnt : 48; + u64 reserved_48_62 : 15; + u64 op_err : 1; + } s; + /* struct nixx_lf_rq_op_drop_pkts_s cn; */ +}; + +static inline u64 NIXX_LF_RQ_OP_DROP_PKTS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_RQ_OP_DROP_PKTS(void) +{ + return 0x940; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_int + * + * NIX LF Receive Queue Interrupt Operation Register A 64-bit atomic + * load-and-add to this register reads RQ interrupts and interrupt + * enables. A 64-bit write optionally sets or clears interrupts and + * interrupt enables. All other accesses to this register (e.g. reads, + * 128-bit accesses) are RAZ/WI. RSL accesses to this register are + * RAZ/WI. + */ +union nixx_lf_rq_op_int { + u64 u; + struct nixx_lf_rq_op_int_s { + u64 rq_int : 8; + u64 rq_int_ena : 8; + u64 reserved_16_41 : 26; + u64 op_err : 1; + u64 setop : 1; + u64 rq : 20; + } s; + /* struct nixx_lf_rq_op_int_s cn; */ +}; + +static inline u64 NIXX_LF_RQ_OP_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_RQ_OP_INT(void) +{ + return 0x900; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_octs + * + * NIX LF Receive Queue Octets Operation Register A 64-bit atomic load- + * and-add to this register reads NIX_RQ_CTX_S[OCTS]. The atomic write + * data has format NIX_OP_Q_WDATA_S and selects the RQ within LF. All + * other accesses to this register (e.g. reads and writes) are RAZ/WI. + * RSL accesses to this register are RAZ/WI. + */ +union nixx_lf_rq_op_octs { + u64 u; + struct nixx_lf_rq_op_octs_s { + u64 cnt : 48; + u64 reserved_48_62 : 15; + u64 op_err : 1; + } s; + /* struct nixx_lf_rq_op_octs_s cn; */ +}; + +static inline u64 NIXX_LF_RQ_OP_OCTS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_RQ_OP_OCTS(void) +{ + return 0x910; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_pkts + * + * NIX LF Receive Queue Packets Operation Register A 64-bit atomic load- + * and-add to this register reads NIX_RQ_CTX_S[PKTS]. The atomic write + * data has format NIX_OP_Q_WDATA_S and selects the RQ within LF. All + * other accesses to this register (e.g. reads and writes) are RAZ/WI. + * RSL accesses to this register are RAZ/WI. + */ +union nixx_lf_rq_op_pkts { + u64 u; + struct nixx_lf_rq_op_pkts_s { + u64 cnt : 48; + u64 reserved_48_62 : 15; + u64 op_err : 1; + } s; + /* struct nixx_lf_rq_op_pkts_s cn; */ +}; + +static inline u64 NIXX_LF_RQ_OP_PKTS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_RQ_OP_PKTS(void) +{ + return 0x920; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_re_pkts + * + * NIX LF Receive Queue Errored Packets Operation Register A 64-bit + * atomic load-and-add to this register reads NIX_RQ_CTX_S[RE_PKTS]. The + * atomic write data has format NIX_OP_Q_WDATA_S and selects the RQ + * within LF. All other accesses to this register (e.g. reads and + * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI. + */ +union nixx_lf_rq_op_re_pkts { + u64 u; + struct nixx_lf_rq_op_re_pkts_s { + u64 cnt : 48; + u64 reserved_48_62 : 15; + u64 op_err : 1; + } s; + /* struct nixx_lf_rq_op_re_pkts_s cn; */ +}; + +static inline u64 NIXX_LF_RQ_OP_RE_PKTS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_RQ_OP_RE_PKTS(void) +{ + return 0x950; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_rx_secret# + * + * NIX LF Receive Secret Key Registers + */ +union nixx_lf_rx_secretx { + u64 u; + struct nixx_lf_rx_secretx_s { + u64 key : 64; + } s; + /* struct nixx_lf_rx_secretx_s cn; */ +}; + +static inline u64 NIXX_LF_RX_SECRETX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_RX_SECRETX(u64 a) +{ + return 0 + 8 * a; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_rx_stat# + * + * NIX LF Receive Statistics Registers The last dimension indicates which + * statistic, and is enumerated by NIX_STAT_LF_RX_E. + */ +union nixx_lf_rx_statx { + u64 u; + struct nixx_lf_rx_statx_s { + u64 stat : 48; + u64 reserved_48_63 : 16; + } s; + /* struct nixx_lf_rx_statx_s cn; */ +}; + +static inline u64 NIXX_LF_RX_STATX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_RX_STATX(u64 a) +{ + return 0x400 + 8 * a; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_send_err_dbg + * + * NIX LF Send Error Debug Register This register captures debug info an + * error detected on packet send after a meta-descriptor is granted by + * PSE. Hardware sets [VALID] when the debug info is captured, and + * subsequent errors are not captured until software clears [VALID] by + * writing a one to it. + */ +union nixx_lf_send_err_dbg { + u64 u; + struct nixx_lf_send_err_dbg_s { + u64 errcode : 8; + u64 sq : 20; + u64 sqe_id : 16; + u64 valid : 1; + u64 reserved_45_63 : 19; + } s; + /* struct nixx_lf_send_err_dbg_s cn; */ +}; + +static inline u64 NIXX_LF_SEND_ERR_DBG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_SEND_ERR_DBG(void) +{ + return 0x280; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_drop_octs + * + * NIX LF Send Queue Dropped Octets Operation Register A 64-bit atomic + * load-and-add to this register reads NIX_SQ_CTX_S[DROP_OCTS]. The + * atomic write data has format NIX_OP_Q_WDATA_S and selects the SQ + * within LF. All other accesses to this register (e.g. reads and + * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI. + */ +union nixx_lf_sq_op_drop_octs { + u64 u; + struct nixx_lf_sq_op_drop_octs_s { + u64 cnt : 48; + u64 reserved_48_62 : 15; + u64 op_err : 1; + } s; + /* struct nixx_lf_sq_op_drop_octs_s cn; */ +}; + +static inline u64 NIXX_LF_SQ_OP_DROP_OCTS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_SQ_OP_DROP_OCTS(void) +{ + return 0xa40; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_drop_pkts + * + * NIX LF Send Queue Dropped Packets Operation Register A 64-bit atomic + * load-and-add to this register reads NIX_SQ_CTX_S[DROP_PKTS]. The + * atomic write data has format NIX_OP_Q_WDATA_S and selects the SQ + * within LF. All other accesses to this register (e.g. reads and + * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI. + */ +union nixx_lf_sq_op_drop_pkts { + u64 u; + struct nixx_lf_sq_op_drop_pkts_s { + u64 cnt : 48; + u64 reserved_48_62 : 15; + u64 op_err : 1; + } s; + /* struct nixx_lf_sq_op_drop_pkts_s cn; */ +}; + +static inline u64 NIXX_LF_SQ_OP_DROP_PKTS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_SQ_OP_DROP_PKTS(void) +{ + return 0xa50; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_err_dbg + * + * NIX LF SQ Operation Error Debug Register This register captures debug + * info for an error detected on LMT store to NIX_LF_OP_SEND() or when a + * NIX_LF_SQ_OP_* register is accessed. Hardware sets [VALID] when the + * debug info is captured, and subsequent errors are not captured until + * software clears [VALID] by writing a one to it. + */ +union nixx_lf_sq_op_err_dbg { + u64 u; + struct nixx_lf_sq_op_err_dbg_s { + u64 errcode : 8; + u64 sq : 20; + u64 sqe_id : 16; + u64 valid : 1; + u64 reserved_45_63 : 19; + } s; + /* struct nixx_lf_sq_op_err_dbg_s cn; */ +}; + +static inline u64 NIXX_LF_SQ_OP_ERR_DBG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_SQ_OP_ERR_DBG(void) +{ + return 0x260; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_int + * + * NIX LF Send Queue Interrupt Operation Register A 64-bit atomic load- + * and-add to this register reads SQ interrupts, interrupt enables and + * XOFF status. A write optionally sets or clears interrupts, interrupt + * enables and XOFF status. A read is RAZ. RSL accesses to this register + * are RAZ/WI. + */ +union nixx_lf_sq_op_int { + u64 u; + struct nixx_lf_sq_op_int_s { + u64 sq_int : 8; + u64 sq_int_ena : 8; + u64 xoff : 1; + u64 reserved_17_41 : 25; + u64 op_err : 1; + u64 setop : 1; + u64 sq : 20; + } s; + /* struct nixx_lf_sq_op_int_s cn; */ +}; + +static inline u64 NIXX_LF_SQ_OP_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_SQ_OP_INT(void) +{ + return 0xa00; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_octs + * + * NIX LF Send Queue Octets Operation Register A 64-bit atomic load-and- + * add to this register reads NIX_SQ_CTX_S[OCTS]. The atomic write data + * has format NIX_OP_Q_WDATA_S and selects the SQ within LF. All other + * accesses to this register (e.g. reads and writes) are RAZ/WI. RSL + * accesses to this register are RAZ/WI. + */ +union nixx_lf_sq_op_octs { + u64 u; + struct nixx_lf_sq_op_octs_s { + u64 cnt : 48; + u64 reserved_48_62 : 15; + u64 op_err : 1; + } s; + /* struct nixx_lf_sq_op_octs_s cn; */ +}; + +static inline u64 NIXX_LF_SQ_OP_OCTS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_SQ_OP_OCTS(void) +{ + return 0xa10; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_pkts + * + * NIX LF Send Queue Packets Operation Register A 64-bit atomic load-and- + * add to this register reads NIX_SQ_CTX_S[PKTS]. The atomic write data + * has format NIX_OP_Q_WDATA_S and selects the SQ within LF. All other + * accesses to this register (e.g. reads and writes) are RAZ/WI. RSL + * accesses to this register are RAZ/WI. + */ +union nixx_lf_sq_op_pkts { + u64 u; + struct nixx_lf_sq_op_pkts_s { + u64 cnt : 48; + u64 reserved_48_62 : 15; + u64 op_err : 1; + } s; + /* struct nixx_lf_sq_op_pkts_s cn; */ +}; + +static inline u64 NIXX_LF_SQ_OP_PKTS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_SQ_OP_PKTS(void) +{ + return 0xa20; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_status + * + * NIX LF Send Queue Status Operation Register A 64-bit atomic load-and- + * add to this register reads status fields in NIX_SQ_CTX_S. The atomic + * write data has format NIX_OP_Q_WDATA_S and selects the SQ within LF. + * Completion of the load-and-add operation also ensures that all + * previously issued LMT stores to NIX_LF_OP_SEND() have completed. All + * other accesses to this register (e.g. reads and writes) are RAZ/WI. + * RSL accesses to this register are RAZ/WI. + */ +union nixx_lf_sq_op_status { + u64 u; + struct nixx_lf_sq_op_status_s { + u64 sqb_count : 16; + u64 reserved_16_19 : 4; + u64 head_offset : 6; + u64 reserved_26_27 : 2; + u64 tail_offset : 6; + u64 reserved_34_62 : 29; + u64 op_err : 1; + } s; + struct nixx_lf_sq_op_status_cn { + u64 sqb_count : 16; + u64 reserved_16_19 : 4; + u64 head_offset : 6; + u64 reserved_26_27 : 2; + u64 tail_offset : 6; + u64 reserved_34_35 : 2; + u64 reserved_36_62 : 27; + u64 op_err : 1; + } cn; +}; + +static inline u64 NIXX_LF_SQ_OP_STATUS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_SQ_OP_STATUS(void) +{ + return 0xa30; +} + +/** + * Register (RVU_PFVF_BAR2) nix#_lf_tx_stat# + * + * NIX LF Transmit Statistics Registers The last dimension indicates + * which statistic, and is enumerated by NIX_STAT_LF_TX_E. + */ +union nixx_lf_tx_statx { + u64 u; + struct nixx_lf_tx_statx_s { + u64 stat : 48; + u64 reserved_48_63 : 16; + } s; + /* struct nixx_lf_tx_statx_s cn; */ +}; + +static inline u64 NIXX_LF_TX_STATX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_LF_TX_STATX(u64 a) +{ + return 0x300 + 8 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_priv_af_int_cfg + * + * NIX Privileged Admin Function Interrupt Configuration Register + */ +union nixx_priv_af_int_cfg { + u64 u; + struct nixx_priv_af_int_cfg_s { + u64 msix_offset : 11; + u64 reserved_11 : 1; + u64 msix_size : 8; + u64 reserved_20_63 : 44; + } s; + /* struct nixx_priv_af_int_cfg_s cn; */ +}; + +static inline u64 NIXX_PRIV_AF_INT_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_PRIV_AF_INT_CFG(void) +{ + return 0x8000000; +} + +/** + * Register (RVU_PF_BAR0) nix#_priv_lf#_cfg + * + * NIX Privileged Local Function Configuration Registers These registers + * allow each NIX local function (LF) to be provisioned to a VF/PF for + * RVU. See also NIX_AF_RVU_LF_CFG_DEBUG. Software should read this + * register after write to ensure that the LF is mapped to [PF_FUNC] + * before issuing transactions to the mapped PF and function. [SLOT] + * must be zero. Internal: Hardware ignores [SLOT] and always assumes + * 0x0. + */ +union nixx_priv_lfx_cfg { + u64 u; + struct nixx_priv_lfx_cfg_s { + u64 slot : 8; + u64 pf_func : 16; + u64 reserved_24_62 : 39; + u64 ena : 1; + } s; + /* struct nixx_priv_lfx_cfg_s cn; */ +}; + +static inline u64 NIXX_PRIV_LFX_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_PRIV_LFX_CFG(u64 a) +{ + return 0x8000010 + 0x100 * a; +} + +/** + * Register (RVU_PF_BAR0) nix#_priv_lf#_int_cfg + * + * NIX Privileged LF Interrupt Configuration Registers + */ +union nixx_priv_lfx_int_cfg { + u64 u; + struct nixx_priv_lfx_int_cfg_s { + u64 msix_offset : 11; + u64 reserved_11 : 1; + u64 msix_size : 8; + u64 reserved_20_63 : 44; + } s; + /* struct nixx_priv_lfx_int_cfg_s cn; */ +}; + +static inline u64 NIXX_PRIV_LFX_INT_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NIXX_PRIV_LFX_INT_CFG(u64 a) +{ + return 0x8000020 + 0x100 * a; +} + +#endif /* __CSRS_NIX_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-npa.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-npa.h new file mode 100644 index 000000000..b70c91bf0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-npa.h @@ -0,0 +1,2294 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Marvell International Ltd. + * + * https://spdx.org/licenses + */ +#ifndef __CSRS_NPA_H__ +#define __CSRS_NPA_H__ + +/** + * @file + * + * Configuration and status register (CSR) address and type definitions for + * NPA. + * + * This file is auto generated. Do not edit. + * + */ + +/** + * Enumeration npa_af_int_vec_e + * + * NPA Admin Function Interrupt Vector Enumeration Enumerates the NPA AF + * MSI-X interrupt vectors. + */ +#define NPA_AF_INT_VEC_E_AF_ERR (3) +#define NPA_AF_INT_VEC_E_AQ_DONE (2) +#define NPA_AF_INT_VEC_E_GEN (1) +#define NPA_AF_INT_VEC_E_POISON (4) +#define NPA_AF_INT_VEC_E_RVU (0) + +/** + * Enumeration npa_aq_comp_e + * + * NPA Admin Queue Completion Enumeration Enumerates the values of + * NPA_AQ_RES_S[COMPCODE]. + */ +#define NPA_AQ_COMP_E_CTX_FAULT (4) +#define NPA_AQ_COMP_E_CTX_POISON (3) +#define NPA_AQ_COMP_E_GOOD (1) +#define NPA_AQ_COMP_E_LOCKERR (5) +#define NPA_AQ_COMP_E_NOTDONE (0) +#define NPA_AQ_COMP_E_SWERR (2) + +/** + * Enumeration npa_aq_ctype_e + * + * NPA Admin Queue Context Type Enumeration Enumerates + * NPA_AQ_INST_S[CTYPE] values. + */ +#define NPA_AQ_CTYPE_E_AURA (0) +#define NPA_AQ_CTYPE_E_POOL (1) + +/** + * Enumeration npa_aq_instop_e + * + * NPA Admin Queue Opcode Enumeration Enumerates NPA_AQ_INST_S[OP] + * values. + */ +#define NPA_AQ_INSTOP_E_INIT (1) +#define NPA_AQ_INSTOP_E_LOCK (4) +#define NPA_AQ_INSTOP_E_NOP (0) +#define NPA_AQ_INSTOP_E_READ (3) +#define NPA_AQ_INSTOP_E_UNLOCK (5) +#define NPA_AQ_INSTOP_E_WRITE (2) + +/** + * Enumeration npa_aura_err_int_e + * + * NPA Aura Error Interrupt Enumeration Enumerates the bit index of + * NPA_AURA_S[ERR_INT], and NPA_AURA_S[ERR_INT_ENA]. + */ +#define NPA_AURA_ERR_INT_E_AURA_ADD_OVER (1) +#define NPA_AURA_ERR_INT_E_AURA_ADD_UNDER (2) +#define NPA_AURA_ERR_INT_E_AURA_FREE_UNDER (0) +#define NPA_AURA_ERR_INT_E_POOL_DIS (3) +#define NPA_AURA_ERR_INT_E_RX(a) (0 + (a)) + +/** + * Enumeration npa_bpintf_e + * + * NPA Backpressure Interface Enumeration Enumerates index of + * NPA_AURA_S[BP_ENA]. + */ +#define NPA_BPINTF_E_NIXX_RX(a) (0 + (a)) + +/** + * Enumeration npa_inpq_e + * + * NPA Input Queue Enumeration Enumerates ALLOC/FREE input queues from + * coprocessors. + */ +#define NPA_INPQ_E_AURA_OP (0xe) +#define NPA_INPQ_E_BPHY (7) +#define NPA_INPQ_E_DPI (6) +#define NPA_INPQ_E_INTERNAL_RSV (0xf) +#define NPA_INPQ_E_NIXX_RX(a) (0 + 2 * (a)) +#define NPA_INPQ_E_NIXX_TX(a) (1 + 2 * (a)) +#define NPA_INPQ_E_RX(a) (0 + (a)) +#define NPA_INPQ_E_SSO (4) +#define NPA_INPQ_E_TIM (5) + +/** + * Enumeration npa_lf_int_vec_e + * + * NPA Local Function Interrupt Vector Enumeration Enumerates the NPA + * MSI-X interrupt vectors per LF. + */ +#define NPA_LF_INT_VEC_E_ERR_INT (0x40) +#define NPA_LF_INT_VEC_E_POISON (0x41) +#define NPA_LF_INT_VEC_E_QINTX(a) (0 + (a)) + +/** + * Enumeration npa_ndc0_port_e + * + * NPA NDC0 Port Enumeration Enumerates NPA NDC0 (NDC_IDX_E::NPA_U(0)) + * ports and the PORT index of NDC_AF_PORT()_RT()_RW()_REQ_PC and + * NDC_AF_PORT()_RT()_RW()_LAT_PC. + */ +#define NPA_NDC0_PORT_E_AURA0 (0) +#define NPA_NDC0_PORT_E_AURA1 (1) +#define NPA_NDC0_PORT_E_POOL0 (2) +#define NPA_NDC0_PORT_E_POOL1 (3) +#define NPA_NDC0_PORT_E_STACK0 (4) +#define NPA_NDC0_PORT_E_STACK1 (5) + +/** + * Enumeration npa_pool_err_int_e + * + * NPA Pool Error Interrupt Enumeration Enumerates the bit index of + * NPA_POOL_S[ERR_INT] and NPA_POOL_S[ERR_INT_ENA]. + */ +#define NPA_POOL_ERR_INT_E_OVFLS (0) +#define NPA_POOL_ERR_INT_E_PERR (2) +#define NPA_POOL_ERR_INT_E_RX(a) (0 + (a)) +#define NPA_POOL_ERR_INT_E_RANGE (1) + +/** + * Structure npa_aq_inst_s + * + * NPA Admin Queue Instruction Structure This structure specifies the AQ + * instruction. Instructions and associated software structures are + * stored in memory as little-endian unless NPA_AF_GEN_CFG[AF_BE] is set. + * Hardware reads of NPA_AQ_INST_S do not allocate into LLC. Hardware + * reads and writes of the context structure selected by [CTYPE], [LF] + * and [CINDEX] use the NDC and LLC caching style configured for that + * context, i.e.: * NPA_AURA_HW_S reads and writes use + * NPA_AF_LF()_AURAS_CFG[CACHING] and NPA_AF_LF()_AURAS_CFG[WAY_MASK]. * + * NPA_POOL_HW_S reads and writes use NPA_AURA_HW_S[POOL_CACHING] and + * NPA_AURA_HW_S[POOL_WAY_MASK]. + */ +union npa_aq_inst_s { + u64 u[2]; + struct npa_aq_inst_s_s { + u64 op : 4; + u64 ctype : 4; + u64 lf : 9; + u64 reserved_17_23 : 7; + u64 cindex : 20; + u64 reserved_44_62 : 19; + u64 doneint : 1; + u64 res_addr : 64; + } s; + /* struct npa_aq_inst_s_s cn; */ +}; + +/** + * Structure npa_aq_res_s + * + * NPA Admin Queue Result Structure NPA writes this structure after it + * completes the NPA_AQ_INST_S instruction. The result structure is + * exactly 16 bytes, and each instruction completion produces exactly one + * result structure. Results and associated software structures are + * stored in memory as little-endian unless NPA_AF_GEN_CFG[AF_BE] is set. + * When [OP] = NPA_AQ_INSTOP_E::INIT, WRITE or READ, this structure is + * immediately followed by context read or write data. See + * NPA_AQ_INSTOP_E. Hardware writes of NPA_AQ_RES_S and context data + * always allocate into LLC. Hardware reads of context data do not + * allocate into LLC. + */ +union npa_aq_res_s { + u64 u[2]; + struct npa_aq_res_s_s { + u64 op : 4; + u64 ctype : 4; + u64 compcode : 8; + u64 doneint : 1; + u64 reserved_17_63 : 47; + u64 reserved_64_127 : 64; + } s; + /* struct npa_aq_res_s_s cn; */ +}; + +/** + * Structure npa_aura_op_wdata_s + * + * NPA Aura Operation Write Data Structure This structure specifies the + * write data format of a 64-bit atomic load-and-add to + * NPA_LF_AURA_OP_ALLOC() and NPA_LF_POOL_OP_PC, and a 128-bit atomic + * CASP operation to NPA_LF_AURA_OP_ALLOC(). + */ +union npa_aura_op_wdata_s { + u64 u; + struct npa_aura_op_wdata_s_s { + u64 aura : 20; + u64 reserved_20_62 : 43; + u64 drop : 1; + } s; + /* struct npa_aura_op_wdata_s_s cn; */ +}; + +/** + * Structure npa_aura_s + * + * NPA Aura Context Structure This structure specifies the format used by + * software with the NPA admin queue to read and write an aura's + * NPA_AURA_HW_S structure maintained by hardware in LLC/DRAM. + */ +union npa_aura_s { + u64 u[8]; + struct npa_aura_s_s { + u64 pool_addr : 64; + u64 ena : 1; + u64 reserved_65_66 : 2; + u64 pool_caching : 1; + u64 pool_way_mask : 16; + u64 avg_con : 9; + u64 reserved_93 : 1; + u64 pool_drop_ena : 1; + u64 aura_drop_ena : 1; + u64 bp_ena : 2; + u64 reserved_98_103 : 6; + u64 aura_drop : 8; + u64 shift : 6; + u64 reserved_118_119 : 2; + u64 avg_level : 8; + u64 count : 36; + u64 reserved_164_167 : 4; + u64 nix0_bpid : 9; + u64 reserved_177_179 : 3; + u64 nix1_bpid : 9; + u64 reserved_189_191 : 3; + u64 limit : 36; + u64 reserved_228_231 : 4; + u64 bp : 8; + u64 reserved_240_243 : 4; + u64 fc_ena : 1; + u64 fc_up_crossing : 1; + u64 fc_stype : 2; + u64 fc_hyst_bits : 4; + u64 reserved_252_255 : 4; + u64 fc_addr : 64; + u64 pool_drop : 8; + u64 update_time : 16; + u64 err_int : 8; + u64 err_int_ena : 8; + u64 thresh_int : 1; + u64 thresh_int_ena : 1; + u64 thresh_up : 1; + u64 reserved_363 : 1; + u64 thresh_qint_idx : 7; + u64 reserved_371 : 1; + u64 err_qint_idx : 7; + u64 reserved_379_383 : 5; + u64 thresh : 36; + u64 reserved_420_447 : 28; + u64 reserved_448_511 : 64; + } s; + /* struct npa_aura_s_s cn; */ +}; + +/** + * Structure npa_pool_s + * + * NPA Pool Context Structure This structure specifies the format used by + * software with the NPA admin queue to read and write a pool's + * NPA_POOL_HW_S structure maintained by hardware in LLC/DRAM. + */ +union npa_pool_s { + u64 u[16]; + struct npa_pool_s_s { + u64 stack_base : 64; + u64 ena : 1; + u64 nat_align : 1; + u64 reserved_66_67 : 2; + u64 stack_caching : 1; + u64 reserved_69_71 : 3; + u64 stack_way_mask : 16; + u64 buf_offset : 12; + u64 reserved_100_103 : 4; + u64 buf_size : 11; + u64 reserved_115_127 : 13; + u64 stack_max_pages : 32; + u64 stack_pages : 32; + u64 op_pc : 48; + u64 reserved_240_255 : 16; + u64 stack_offset : 4; + u64 reserved_260_263 : 4; + u64 shift : 6; + u64 reserved_270_271 : 2; + u64 avg_level : 8; + u64 avg_con : 9; + u64 fc_ena : 1; + u64 fc_stype : 2; + u64 fc_hyst_bits : 4; + u64 fc_up_crossing : 1; + u64 reserved_297_299 : 3; + u64 update_time : 16; + u64 reserved_316_319 : 4; + u64 fc_addr : 64; + u64 ptr_start : 64; + u64 ptr_end : 64; + u64 reserved_512_535 : 24; + u64 err_int : 8; + u64 err_int_ena : 8; + u64 thresh_int : 1; + u64 thresh_int_ena : 1; + u64 thresh_up : 1; + u64 reserved_555 : 1; + u64 thresh_qint_idx : 7; + u64 reserved_563 : 1; + u64 err_qint_idx : 7; + u64 reserved_571_575 : 5; + u64 thresh : 36; + u64 reserved_612_639 : 28; + u64 reserved_640_703 : 64; + u64 reserved_704_767 : 64; + u64 reserved_768_831 : 64; + u64 reserved_832_895 : 64; + u64 reserved_896_959 : 64; + u64 reserved_960_1023 : 64; + } s; + /* struct npa_pool_s_s cn; */ +}; + +/** + * Structure npa_qint_hw_s + * + * NPA Queue Interrupt Context Hardware Structure This structure contains + * context state maintained by hardware for each queue interrupt (QINT) + * in NDC/LLC/DRAM. Software accesses this structure with the + * NPA_LF_QINT()_* registers. Hardware maintains a table of + * NPA_AF_CONST[QINTS] contiguous NPA_QINT_HW_S structures per LF + * starting at IOVA NPA_AF_LF()_QINTS_BASE. Always stored in byte + * invariant little-endian format (LE8). + */ +union npa_qint_hw_s { + u32 u; + struct npa_qint_hw_s_s { + u32 count : 22; + u32 reserved_22_30 : 9; + u32 ena : 1; + } s; + /* struct npa_qint_hw_s_s cn; */ +}; + +/** + * Register (RVU_PF_BAR0) npa_af_active_cycles_pc + * + * NPA AF Active Cycles Register + */ +union npa_af_active_cycles_pc { + u64 u; + struct npa_af_active_cycles_pc_s { + u64 act_cyc : 64; + } s; + /* struct npa_af_active_cycles_pc_s cn; */ +}; + +static inline u64 NPA_AF_ACTIVE_CYCLES_PC(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_ACTIVE_CYCLES_PC(void) +{ + return 0xf0; +} + +/** + * Register (RVU_PF_BAR0) npa_af_aq_base + * + * NPA AF Admin Queue Base Address Register + */ +union npa_af_aq_base { + u64 u; + struct npa_af_aq_base_s { + u64 reserved_0_6 : 7; + u64 base_addr : 46; + u64 reserved_53_63 : 11; + } s; + /* struct npa_af_aq_base_s cn; */ +}; + +static inline u64 NPA_AF_AQ_BASE(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_AQ_BASE(void) +{ + return 0x610; +} + +/** + * Register (RVU_PF_BAR0) npa_af_aq_cfg + * + * NPA AF Admin Queue Configuration Register + */ +union npa_af_aq_cfg { + u64 u; + struct npa_af_aq_cfg_s { + u64 qsize : 4; + u64 reserved_4_63 : 60; + } s; + /* struct npa_af_aq_cfg_s cn; */ +}; + +static inline u64 NPA_AF_AQ_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_AQ_CFG(void) +{ + return 0x600; +} + +/** + * Register (RVU_PF_BAR0) npa_af_aq_done + * + * NPA AF AQ Done Count Register + */ +union npa_af_aq_done { + u64 u; + struct npa_af_aq_done_s { + u64 done : 20; + u64 reserved_20_63 : 44; + } s; + /* struct npa_af_aq_done_s cn; */ +}; + +static inline u64 NPA_AF_AQ_DONE(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_AQ_DONE(void) +{ + return 0x650; +} + +/** + * Register (RVU_PF_BAR0) npa_af_aq_done_ack + * + * NPA AF AQ Done Count Ack Register This register is written by software + * to acknowledge interrupts. + */ +union npa_af_aq_done_ack { + u64 u; + struct npa_af_aq_done_ack_s { + u64 done_ack : 20; + u64 reserved_20_63 : 44; + } s; + /* struct npa_af_aq_done_ack_s cn; */ +}; + +static inline u64 NPA_AF_AQ_DONE_ACK(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_AQ_DONE_ACK(void) +{ + return 0x660; +} + +/** + * Register (RVU_PF_BAR0) npa_af_aq_done_ena_w1c + * + * NPA AF AQ Done Interrupt Enable Clear Register This register clears + * interrupt enable bits. + */ +union npa_af_aq_done_ena_w1c { + u64 u; + struct npa_af_aq_done_ena_w1c_s { + u64 done : 1; + u64 reserved_1_63 : 63; + } s; + /* struct npa_af_aq_done_ena_w1c_s cn; */ +}; + +static inline u64 NPA_AF_AQ_DONE_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_AQ_DONE_ENA_W1C(void) +{ + return 0x698; +} + +/** + * Register (RVU_PF_BAR0) npa_af_aq_done_ena_w1s + * + * NPA AF AQ Done Interrupt Enable Set Register This register sets + * interrupt enable bits. + */ +union npa_af_aq_done_ena_w1s { + u64 u; + struct npa_af_aq_done_ena_w1s_s { + u64 done : 1; + u64 reserved_1_63 : 63; + } s; + /* struct npa_af_aq_done_ena_w1s_s cn; */ +}; + +static inline u64 NPA_AF_AQ_DONE_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_AQ_DONE_ENA_W1S(void) +{ + return 0x690; +} + +/** + * Register (RVU_PF_BAR0) npa_af_aq_done_int + * + * NPA AF AQ Done Interrupt Register + */ +union npa_af_aq_done_int { + u64 u; + struct npa_af_aq_done_int_s { + u64 done : 1; + u64 reserved_1_63 : 63; + } s; + /* struct npa_af_aq_done_int_s cn; */ +}; + +static inline u64 NPA_AF_AQ_DONE_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_AQ_DONE_INT(void) +{ + return 0x680; +} + +/** + * Register (RVU_PF_BAR0) npa_af_aq_done_int_w1s + * + * INTERNAL: NPA AF AQ Done Interrupt Set Register + */ +union npa_af_aq_done_int_w1s { + u64 u; + struct npa_af_aq_done_int_w1s_s { + u64 done : 1; + u64 reserved_1_63 : 63; + } s; + /* struct npa_af_aq_done_int_w1s_s cn; */ +}; + +static inline u64 NPA_AF_AQ_DONE_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_AQ_DONE_INT_W1S(void) +{ + return 0x688; +} + +/** + * Register (RVU_PF_BAR0) npa_af_aq_done_timer + * + * NPA AF Admin Queue Done Interrupt Timer Register Used to debug the + * queue interrupt coalescing timer. + */ +union npa_af_aq_done_timer { + u64 u; + struct npa_af_aq_done_timer_s { + u64 count : 16; + u64 reserved_16_63 : 48; + } s; + /* struct npa_af_aq_done_timer_s cn; */ +}; + +static inline u64 NPA_AF_AQ_DONE_TIMER(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_AQ_DONE_TIMER(void) +{ + return 0x670; +} + +/** + * Register (RVU_PF_BAR0) npa_af_aq_done_wait + * + * NPA AF AQ Done Interrupt Coalescing Wait Register Specifies the queue + * interrupt coalescing settings. + */ +union npa_af_aq_done_wait { + u64 u; + struct npa_af_aq_done_wait_s { + u64 num_wait : 20; + u64 reserved_20_31 : 12; + u64 time_wait : 16; + u64 reserved_48_63 : 16; + } s; + /* struct npa_af_aq_done_wait_s cn; */ +}; + +static inline u64 NPA_AF_AQ_DONE_WAIT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_AQ_DONE_WAIT(void) +{ + return 0x640; +} + +/** + * Register (RVU_PF_BAR0) npa_af_aq_door + * + * NPA AF Admin Queue Doorbell Register Software writes to this register + * to enqueue one or more entries to AQ. + */ +union npa_af_aq_door { + u64 u; + struct npa_af_aq_door_s { + u64 count : 16; + u64 reserved_16_63 : 48; + } s; + /* struct npa_af_aq_door_s cn; */ +}; + +static inline u64 NPA_AF_AQ_DOOR(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_AQ_DOOR(void) +{ + return 0x630; +} + +/** + * Register (RVU_PF_BAR0) npa_af_aq_status + * + * NPA AF Admin Queue Status Register + */ +union npa_af_aq_status { + u64 u; + struct npa_af_aq_status_s { + u64 reserved_0_3 : 4; + u64 head_ptr : 20; + u64 reserved_24_35 : 12; + u64 tail_ptr : 20; + u64 reserved_56_61 : 6; + u64 aq_busy : 1; + u64 aq_err : 1; + } s; + struct npa_af_aq_status_cn { + u64 reserved_0_3 : 4; + u64 head_ptr : 20; + u64 reserved_24_31 : 8; + u64 reserved_32_35 : 4; + u64 tail_ptr : 20; + u64 reserved_56_61 : 6; + u64 aq_busy : 1; + u64 aq_err : 1; + } cn; +}; + +static inline u64 NPA_AF_AQ_STATUS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_AQ_STATUS(void) +{ + return 0x620; +} + +/** + * Register (RVU_PF_BAR0) npa_af_avg_delay + * + * NPA AF Queue Average Delay Register + */ +union npa_af_avg_delay { + u64 u; + struct npa_af_avg_delay_s { + u64 avg_dly : 19; + u64 reserved_19_23 : 5; + u64 avg_timer : 16; + u64 reserved_40_62 : 23; + u64 avg_timer_dis : 1; + } s; + /* struct npa_af_avg_delay_s cn; */ +}; + +static inline u64 NPA_AF_AVG_DELAY(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_AVG_DELAY(void) +{ + return 0x100; +} + +/** + * Register (RVU_PF_BAR0) npa_af_bar2_alias# + * + * INTERNAL: NPA Admin Function BAR2 Alias Registers These registers + * alias to the NPA BAR2 registers for the PF and function selected by + * NPA_AF_BAR2_SEL[PF_FUNC]. Internal: Not implemented. Placeholder for + * bug33464. + */ +union npa_af_bar2_aliasx { + u64 u; + struct npa_af_bar2_aliasx_s { + u64 data : 64; + } s; + /* struct npa_af_bar2_aliasx_s cn; */ +}; + +static inline u64 NPA_AF_BAR2_ALIASX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_BAR2_ALIASX(u64 a) +{ + return 0x9100000 + 8 * a; +} + +/** + * Register (RVU_PF_BAR0) npa_af_bar2_sel + * + * INTERNAL: NPA Admin Function BAR2 Select Register This register + * configures BAR2 accesses from the NPA_AF_BAR2_ALIAS() registers in + * BAR0. Internal: Not implemented. Placeholder for bug33464. + */ +union npa_af_bar2_sel { + u64 u; + struct npa_af_bar2_sel_s { + u64 alias_pf_func : 16; + u64 alias_ena : 1; + u64 reserved_17_63 : 47; + } s; + /* struct npa_af_bar2_sel_s cn; */ +}; + +static inline u64 NPA_AF_BAR2_SEL(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_BAR2_SEL(void) +{ + return 0x9000000; +} + +/** + * Register (RVU_PF_BAR0) npa_af_blk_rst + * + * NPA AF Block Reset Register + */ +union npa_af_blk_rst { + u64 u; + struct npa_af_blk_rst_s { + u64 rst : 1; + u64 reserved_1_62 : 62; + u64 busy : 1; + } s; + /* struct npa_af_blk_rst_s cn; */ +}; + +static inline u64 NPA_AF_BLK_RST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_BLK_RST(void) +{ + return 0; +} + +/** + * Register (RVU_PF_BAR0) npa_af_bp_test + * + * INTERNAL: NPA AF Backpressure Test Register + */ +union npa_af_bp_test { + u64 u; + struct npa_af_bp_test_s { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 32; + u64 enable : 16; + } s; + /* struct npa_af_bp_test_s cn; */ +}; + +static inline u64 NPA_AF_BP_TEST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_BP_TEST(void) +{ + return 0x200; +} + +/** + * Register (RVU_PF_BAR0) npa_af_const + * + * NPA AF Constants Register This register contains constants for + * software discovery. + */ +union npa_af_const { + u64 u; + struct npa_af_const_s { + u64 stack_page_bytes : 8; + u64 stack_page_ptrs : 8; + u64 lfs : 12; + u64 qints : 12; + u64 num_ndc : 3; + u64 reserved_43_63 : 21; + } s; + /* struct npa_af_const_s cn; */ +}; + +static inline u64 NPA_AF_CONST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_CONST(void) +{ + return 0x10; +} + +/** + * Register (RVU_PF_BAR0) npa_af_const1 + * + * NPA AF Constants Register 1 This register contains constants for + * software discovery. + */ +union npa_af_const1 { + u64 u; + struct npa_af_const1_s { + u64 aura_log2bytes : 4; + u64 pool_log2bytes : 4; + u64 qint_log2bytes : 4; + u64 reserved_12_63 : 52; + } s; + /* struct npa_af_const1_s cn; */ +}; + +static inline u64 NPA_AF_CONST1(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_CONST1(void) +{ + return 0x18; +} + +/** + * Register (RVU_PF_BAR0) npa_af_dtx_filter_ctl + * + * NPA AF DTX LF Filter Control Register + */ +union npa_af_dtx_filter_ctl { + u64 u; + struct npa_af_dtx_filter_ctl_s { + u64 ena : 1; + u64 reserved_1_3 : 3; + u64 lf : 7; + u64 reserved_11_63 : 53; + } s; + /* struct npa_af_dtx_filter_ctl_s cn; */ +}; + +static inline u64 NPA_AF_DTX_FILTER_CTL(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_DTX_FILTER_CTL(void) +{ + return 0x10040; +} + +/** + * Register (RVU_PF_BAR0) npa_af_eco + * + * INTERNAL: NPA AF ECO Register + */ +union npa_af_eco { + u64 u; + struct npa_af_eco_s { + u64 eco_rw : 32; + u64 reserved_32_63 : 32; + } s; + /* struct npa_af_eco_s cn; */ +}; + +static inline u64 NPA_AF_ECO(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_ECO(void) +{ + return 0x300; +} + +/** + * Register (RVU_PF_BAR0) npa_af_err_int + * + * NPA Admin Function Error Interrupt Register + */ +union npa_af_err_int { + u64 u; + struct npa_af_err_int_s { + u64 reserved_0_11 : 12; + u64 aq_door_err : 1; + u64 aq_res_fault : 1; + u64 aq_inst_fault : 1; + u64 reserved_15_63 : 49; + } s; + /* struct npa_af_err_int_s cn; */ +}; + +static inline u64 NPA_AF_ERR_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_ERR_INT(void) +{ + return 0x180; +} + +/** + * Register (RVU_PF_BAR0) npa_af_err_int_ena_w1c + * + * NPA Admin Function Error Interrupt Enable Clear Register This register + * clears interrupt enable bits. + */ +union npa_af_err_int_ena_w1c { + u64 u; + struct npa_af_err_int_ena_w1c_s { + u64 reserved_0_11 : 12; + u64 aq_door_err : 1; + u64 aq_res_fault : 1; + u64 aq_inst_fault : 1; + u64 reserved_15_63 : 49; + } s; + /* struct npa_af_err_int_ena_w1c_s cn; */ +}; + +static inline u64 NPA_AF_ERR_INT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_ERR_INT_ENA_W1C(void) +{ + return 0x198; +} + +/** + * Register (RVU_PF_BAR0) npa_af_err_int_ena_w1s + * + * NPA Admin Function Error Interrupt Enable Set Register This register + * sets interrupt enable bits. + */ +union npa_af_err_int_ena_w1s { + u64 u; + struct npa_af_err_int_ena_w1s_s { + u64 reserved_0_11 : 12; + u64 aq_door_err : 1; + u64 aq_res_fault : 1; + u64 aq_inst_fault : 1; + u64 reserved_15_63 : 49; + } s; + /* struct npa_af_err_int_ena_w1s_s cn; */ +}; + +static inline u64 NPA_AF_ERR_INT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_ERR_INT_ENA_W1S(void) +{ + return 0x190; +} + +/** + * Register (RVU_PF_BAR0) npa_af_err_int_w1s + * + * NPA Admin Function Error Interrupt Set Register This register sets + * interrupt bits. + */ +union npa_af_err_int_w1s { + u64 u; + struct npa_af_err_int_w1s_s { + u64 reserved_0_11 : 12; + u64 aq_door_err : 1; + u64 aq_res_fault : 1; + u64 aq_inst_fault : 1; + u64 reserved_15_63 : 49; + } s; + /* struct npa_af_err_int_w1s_s cn; */ +}; + +static inline u64 NPA_AF_ERR_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_ERR_INT_W1S(void) +{ + return 0x188; +} + +/** + * Register (RVU_PF_BAR0) npa_af_gen_cfg + * + * NPA AF General Configuration Register This register provides NPA + * control and status information. + */ +union npa_af_gen_cfg { + u64 u; + struct npa_af_gen_cfg_s { + u64 reserved_0 : 1; + u64 af_be : 1; + u64 reserved_2 : 1; + u64 force_cond_clk_en : 1; + u64 force_intf_clk_en : 1; + u64 reserved_5_9 : 5; + u64 ocla_bp : 1; + u64 reserved_11 : 1; + u64 ratem1 : 4; + u64 reserved_16_63 : 48; + } s; + /* struct npa_af_gen_cfg_s cn; */ +}; + +static inline u64 NPA_AF_GEN_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_GEN_CFG(void) +{ + return 0x30; +} + +/** + * Register (RVU_PF_BAR0) npa_af_gen_int + * + * NPA AF General Interrupt Register This register contains general error + * interrupt summary bits. + */ +union npa_af_gen_int { + u64 u; + struct npa_af_gen_int_s { + u64 free_dis : 16; + u64 alloc_dis : 16; + u64 unmapped_pf_func : 1; + u64 reserved_33_63 : 31; + } s; + /* struct npa_af_gen_int_s cn; */ +}; + +static inline u64 NPA_AF_GEN_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_GEN_INT(void) +{ + return 0x140; +} + +/** + * Register (RVU_PF_BAR0) npa_af_gen_int_ena_w1c + * + * NPA AF General Interrupt Enable Clear Register This register clears + * interrupt enable bits. + */ +union npa_af_gen_int_ena_w1c { + u64 u; + struct npa_af_gen_int_ena_w1c_s { + u64 free_dis : 16; + u64 alloc_dis : 16; + u64 unmapped_pf_func : 1; + u64 reserved_33_63 : 31; + } s; + /* struct npa_af_gen_int_ena_w1c_s cn; */ +}; + +static inline u64 NPA_AF_GEN_INT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_GEN_INT_ENA_W1C(void) +{ + return 0x158; +} + +/** + * Register (RVU_PF_BAR0) npa_af_gen_int_ena_w1s + * + * NPA AF General Interrupt Enable Set Register This register sets + * interrupt enable bits. + */ +union npa_af_gen_int_ena_w1s { + u64 u; + struct npa_af_gen_int_ena_w1s_s { + u64 free_dis : 16; + u64 alloc_dis : 16; + u64 unmapped_pf_func : 1; + u64 reserved_33_63 : 31; + } s; + /* struct npa_af_gen_int_ena_w1s_s cn; */ +}; + +static inline u64 NPA_AF_GEN_INT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_GEN_INT_ENA_W1S(void) +{ + return 0x150; +} + +/** + * Register (RVU_PF_BAR0) npa_af_gen_int_w1s + * + * NPA AF General Interrupt Set Register This register sets interrupt + * bits. + */ +union npa_af_gen_int_w1s { + u64 u; + struct npa_af_gen_int_w1s_s { + u64 free_dis : 16; + u64 alloc_dis : 16; + u64 unmapped_pf_func : 1; + u64 reserved_33_63 : 31; + } s; + /* struct npa_af_gen_int_w1s_s cn; */ +}; + +static inline u64 NPA_AF_GEN_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_GEN_INT_W1S(void) +{ + return 0x148; +} + +/** + * Register (RVU_PF_BAR0) npa_af_inp_ctl + * + * NPA AF Input Control Register + */ +union npa_af_inp_ctl { + u64 u; + struct npa_af_inp_ctl_s { + u64 free_dis : 16; + u64 alloc_dis : 16; + u64 reserved_32_63 : 32; + } s; + /* struct npa_af_inp_ctl_s cn; */ +}; + +static inline u64 NPA_AF_INP_CTL(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_INP_CTL(void) +{ + return 0xd0; +} + +/** + * Register (RVU_PF_BAR0) npa_af_lf#_auras_cfg + * + * NPA AF Local Function Auras Configuration Registers + */ +union npa_af_lfx_auras_cfg { + u64 u; + struct npa_af_lfx_auras_cfg_s { + u64 way_mask : 16; + u64 loc_aura_size : 4; + u64 loc_aura_offset : 14; + u64 caching : 1; + u64 be : 1; + u64 rmt_aura_size : 4; + u64 rmt_aura_offset : 14; + u64 rmt_lf : 7; + u64 reserved_61_63 : 3; + } s; + struct npa_af_lfx_auras_cfg_cn96xxp1 { + u64 way_mask : 16; + u64 loc_aura_size : 4; + u64 loc_aura_offset : 14; + u64 caching : 1; + u64 reserved_35 : 1; + u64 rmt_aura_size : 4; + u64 rmt_aura_offset : 14; + u64 rmt_lf : 7; + u64 reserved_61_63 : 3; + } cn96xxp1; + /* struct npa_af_lfx_auras_cfg_s cn96xxp3; */ + /* struct npa_af_lfx_auras_cfg_s cnf95xx; */ +}; + +static inline u64 NPA_AF_LFX_AURAS_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_LFX_AURAS_CFG(u64 a) +{ + return 0x4000 + 0x40000 * a; +} + +/** + * Register (RVU_PF_BAR0) npa_af_lf#_loc_auras_base + * + * NPA AF Local Function Auras Base Registers + */ +union npa_af_lfx_loc_auras_base { + u64 u; + struct npa_af_lfx_loc_auras_base_s { + u64 reserved_0_6 : 7; + u64 addr : 46; + u64 reserved_53_63 : 11; + } s; + /* struct npa_af_lfx_loc_auras_base_s cn; */ +}; + +static inline u64 NPA_AF_LFX_LOC_AURAS_BASE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_LFX_LOC_AURAS_BASE(u64 a) +{ + return 0x4010 + 0x40000 * a; +} + +/** + * Register (RVU_PF_BAR0) npa_af_lf#_qints_base + * + * NPA AF Local Function Queue Interrupts Base Registers + */ +union npa_af_lfx_qints_base { + u64 u; + struct npa_af_lfx_qints_base_s { + u64 reserved_0_6 : 7; + u64 addr : 46; + u64 reserved_53_63 : 11; + } s; + /* struct npa_af_lfx_qints_base_s cn; */ +}; + +static inline u64 NPA_AF_LFX_QINTS_BASE(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_LFX_QINTS_BASE(u64 a) +{ + return 0x4110 + 0x40000 * a; +} + +/** + * Register (RVU_PF_BAR0) npa_af_lf#_qints_cfg + * + * NPA AF Local Function Queue Interrupts Configuration Registers This + * register controls access to the LF's queue interrupt context table in + * LLC/DRAM. The table consists of NPA_AF_CONST[QINTS] contiguous + * NPA_QINT_HW_S structures. The size of each structure is 1 \<\< + * NPA_AF_CONST1[QINT_LOG2BYTES] bytes. + */ +union npa_af_lfx_qints_cfg { + u64 u; + struct npa_af_lfx_qints_cfg_s { + u64 reserved_0_19 : 20; + u64 way_mask : 16; + u64 caching : 2; + u64 reserved_38_63 : 26; + } s; + /* struct npa_af_lfx_qints_cfg_s cn; */ +}; + +static inline u64 NPA_AF_LFX_QINTS_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_LFX_QINTS_CFG(u64 a) +{ + return 0x4100 + 0x40000 * a; +} + +/** + * Register (RVU_PF_BAR0) npa_af_lf_rst + * + * NPA Admin Function LF Reset Register + */ +union npa_af_lf_rst { + u64 u; + struct npa_af_lf_rst_s { + u64 lf : 8; + u64 reserved_8_11 : 4; + u64 exec : 1; + u64 reserved_13_63 : 51; + } s; + /* struct npa_af_lf_rst_s cn; */ +}; + +static inline u64 NPA_AF_LF_RST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_LF_RST(void) +{ + return 0x20; +} + +/** + * Register (RVU_PF_BAR0) npa_af_ndc_cfg + * + * NDC AF General Configuration Register This register provides NDC + * control. + */ +union npa_af_ndc_cfg { + u64 u; + struct npa_af_ndc_cfg_s { + u64 ndc_bypass : 1; + u64 ndc_ign_pois : 1; + u64 byp_aura : 1; + u64 byp_pool : 1; + u64 byp_stack : 1; + u64 byp_qint : 1; + u64 reserved_6_63 : 58; + } s; + /* struct npa_af_ndc_cfg_s cn; */ +}; + +static inline u64 NPA_AF_NDC_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_NDC_CFG(void) +{ + return 0x40; +} + +/** + * Register (RVU_PF_BAR0) npa_af_ndc_sync + * + * NPA AF NDC Sync Register Used to synchronize the NPA NDC. + */ +union npa_af_ndc_sync { + u64 u; + struct npa_af_ndc_sync_s { + u64 lf : 8; + u64 reserved_8_11 : 4; + u64 exec : 1; + u64 reserved_13_63 : 51; + } s; + /* struct npa_af_ndc_sync_s cn; */ +}; + +static inline u64 NPA_AF_NDC_SYNC(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_NDC_SYNC(void) +{ + return 0x50; +} + +/** + * Register (RVU_PF_BAR0) npa_af_ras + * + * NPA AF RAS Interrupt Register This register is intended for delivery + * of RAS events to the SCP, so should be ignored by OS drivers. + */ +union npa_af_ras { + u64 u; + struct npa_af_ras_s { + u64 reserved_0_31 : 32; + u64 aq_ctx_poison : 1; + u64 aq_res_poison : 1; + u64 aq_inst_poison : 1; + u64 reserved_35_63 : 29; + } s; + /* struct npa_af_ras_s cn; */ +}; + +static inline u64 NPA_AF_RAS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_RAS(void) +{ + return 0x1a0; +} + +/** + * Register (RVU_PF_BAR0) npa_af_ras_ena_w1c + * + * NPA AF RAS Interrupt Enable Clear Register This register clears + * interrupt enable bits. + */ +union npa_af_ras_ena_w1c { + u64 u; + struct npa_af_ras_ena_w1c_s { + u64 reserved_0_31 : 32; + u64 aq_ctx_poison : 1; + u64 aq_res_poison : 1; + u64 aq_inst_poison : 1; + u64 reserved_35_63 : 29; + } s; + /* struct npa_af_ras_ena_w1c_s cn; */ +}; + +static inline u64 NPA_AF_RAS_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_RAS_ENA_W1C(void) +{ + return 0x1b8; +} + +/** + * Register (RVU_PF_BAR0) npa_af_ras_ena_w1s + * + * NPA AF RAS Interrupt Enable Set Register This register sets interrupt + * enable bits. + */ +union npa_af_ras_ena_w1s { + u64 u; + struct npa_af_ras_ena_w1s_s { + u64 reserved_0_31 : 32; + u64 aq_ctx_poison : 1; + u64 aq_res_poison : 1; + u64 aq_inst_poison : 1; + u64 reserved_35_63 : 29; + } s; + /* struct npa_af_ras_ena_w1s_s cn; */ +}; + +static inline u64 NPA_AF_RAS_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_RAS_ENA_W1S(void) +{ + return 0x1b0; +} + +/** + * Register (RVU_PF_BAR0) npa_af_ras_w1s + * + * NPA AF RAS Interrupt Set Register This register sets interrupt bits. + */ +union npa_af_ras_w1s { + u64 u; + struct npa_af_ras_w1s_s { + u64 reserved_0_31 : 32; + u64 aq_ctx_poison : 1; + u64 aq_res_poison : 1; + u64 aq_inst_poison : 1; + u64 reserved_35_63 : 29; + } s; + /* struct npa_af_ras_w1s_s cn; */ +}; + +static inline u64 NPA_AF_RAS_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_RAS_W1S(void) +{ + return 0x1a8; +} + +/** + * Register (RVU_PF_BAR0) npa_af_rvu_int + * + * NPA AF RVU Interrupt Register This register contains RVU error + * interrupt summary bits. + */ +union npa_af_rvu_int { + u64 u; + struct npa_af_rvu_int_s { + u64 unmapped_slot : 1; + u64 reserved_1_63 : 63; + } s; + /* struct npa_af_rvu_int_s cn; */ +}; + +static inline u64 NPA_AF_RVU_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_RVU_INT(void) +{ + return 0x160; +} + +/** + * Register (RVU_PF_BAR0) npa_af_rvu_int_ena_w1c + * + * NPA AF RVU Interrupt Enable Clear Register This register clears + * interrupt enable bits. + */ +union npa_af_rvu_int_ena_w1c { + u64 u; + struct npa_af_rvu_int_ena_w1c_s { + u64 unmapped_slot : 1; + u64 reserved_1_63 : 63; + } s; + /* struct npa_af_rvu_int_ena_w1c_s cn; */ +}; + +static inline u64 NPA_AF_RVU_INT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_RVU_INT_ENA_W1C(void) +{ + return 0x178; +} + +/** + * Register (RVU_PF_BAR0) npa_af_rvu_int_ena_w1s + * + * NPA AF RVU Interrupt Enable Set Register This register sets interrupt + * enable bits. + */ +union npa_af_rvu_int_ena_w1s { + u64 u; + struct npa_af_rvu_int_ena_w1s_s { + u64 unmapped_slot : 1; + u64 reserved_1_63 : 63; + } s; + /* struct npa_af_rvu_int_ena_w1s_s cn; */ +}; + +static inline u64 NPA_AF_RVU_INT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_RVU_INT_ENA_W1S(void) +{ + return 0x170; +} + +/** + * Register (RVU_PF_BAR0) npa_af_rvu_int_w1s + * + * NPA AF RVU Interrupt Set Register This register sets interrupt bits. + */ +union npa_af_rvu_int_w1s { + u64 u; + struct npa_af_rvu_int_w1s_s { + u64 unmapped_slot : 1; + u64 reserved_1_63 : 63; + } s; + /* struct npa_af_rvu_int_w1s_s cn; */ +}; + +static inline u64 NPA_AF_RVU_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_RVU_INT_W1S(void) +{ + return 0x168; +} + +/** + * Register (RVU_PF_BAR0) npa_af_rvu_lf_cfg_debug + * + * NPA Privileged LF Configuration Debug Register This debug register + * allows software to lookup the reverse mapping from VF/PF slot to LF. + * The forward mapping is programmed with NPA_PRIV_LF()_CFG. + */ +union npa_af_rvu_lf_cfg_debug { + u64 u; + struct npa_af_rvu_lf_cfg_debug_s { + u64 lf : 12; + u64 lf_valid : 1; + u64 exec : 1; + u64 reserved_14_15 : 2; + u64 slot : 8; + u64 pf_func : 16; + u64 reserved_40_63 : 24; + } s; + /* struct npa_af_rvu_lf_cfg_debug_s cn; */ +}; + +static inline u64 NPA_AF_RVU_LF_CFG_DEBUG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_AF_RVU_LF_CFG_DEBUG(void) +{ + return 0x10030; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_aura_op_alloc# + * + * NPA Aura Allocate Operation Registers These registers are used to + * allocate one or two pointers from a given aura's pool. A 64-bit atomic + * load-and-add to NPA_LF_AURA_OP_ALLOC(0) allocates a single pointer. A + * 128-bit atomic CASP operation to NPA_LF_AURA_OP_ALLOC(0..1) allocates + * two pointers. The atomic write data format is NPA_AURA_OP_WDATA_S. For + * CASP, the first SWAP word in the write data contains + * NPA_AURA_OP_WDATA_S and the remaining write data words are ignored. + * All other accesses to this register (e.g. reads and writes) are + * RAZ/WI. RSL accesses to this register are RAZ/WI. + */ +union npa_lf_aura_op_allocx { + u64 u; + struct npa_lf_aura_op_allocx_s { + u64 addr : 64; + } s; + /* struct npa_lf_aura_op_allocx_s cn; */ +}; + +static inline u64 NPA_LF_AURA_OP_ALLOCX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_AURA_OP_ALLOCX(u64 a) +{ + return 0x10 + 8 * a; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_aura_op_cnt + * + * NPA LF Aura Count Register A 64-bit atomic load-and-add to this + * register returns a given aura's count. A write sets or adds the aura's + * count. A read is RAZ. RSL accesses to this register are RAZ/WI. + */ +union npa_lf_aura_op_cnt { + u64 u; + struct npa_lf_aura_op_cnt_s { + u64 count : 36; + u64 reserved_36_41 : 6; + u64 op_err : 1; + u64 cnt_add : 1; + u64 aura : 20; + } s; + /* struct npa_lf_aura_op_cnt_s cn; */ +}; + +static inline u64 NPA_LF_AURA_OP_CNT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_AURA_OP_CNT(void) +{ + return 0x30; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_aura_op_free0 + * + * NPA LF Aura Free Operation Register 0 A 128-bit write (STP) to + * NPA_LF_AURA_OP_FREE0 and NPA_LF_AURA_OP_FREE1 frees a pointer into a + * given aura's pool. All other accesses to these registers (e.g. reads + * and 64-bit writes) are RAZ/WI. RSL accesses to this register are + * RAZ/WI. + */ +union npa_lf_aura_op_free0 { + u64 u; + struct npa_lf_aura_op_free0_s { + u64 addr : 64; + } s; + /* struct npa_lf_aura_op_free0_s cn; */ +}; + +static inline u64 NPA_LF_AURA_OP_FREE0(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_AURA_OP_FREE0(void) +{ + return 0x20; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_aura_op_free1 + * + * NPA LF Aura Free Operation Register 1 See NPA_LF_AURA_OP_FREE0. RSL + * accesses to this register are RAZ/WI. + */ +union npa_lf_aura_op_free1 { + u64 u; + struct npa_lf_aura_op_free1_s { + u64 aura : 20; + u64 reserved_20_62 : 43; + u64 fabs : 1; + } s; + /* struct npa_lf_aura_op_free1_s cn; */ +}; + +static inline u64 NPA_LF_AURA_OP_FREE1(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_AURA_OP_FREE1(void) +{ + return 0x28; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_aura_op_int + * + * NPA LF Aura Interrupt Operation Register A 64-bit atomic load-and-add + * to this register reads + * NPA_AURA_HW_S[ERR_INT,ERR_INT_ENA,THRESH_INT,THRESH_INT_ENA]. A write + * optionally sets or clears these fields. A read is RAZ. RSL accesses + * to this register are RAZ/WI. + */ +union npa_lf_aura_op_int { + u64 u; + struct npa_lf_aura_op_int_s { + u64 err_int : 8; + u64 err_int_ena : 8; + u64 thresh_int : 1; + u64 thresh_int_ena : 1; + u64 reserved_18_41 : 24; + u64 op_err : 1; + u64 setop : 1; + u64 aura : 20; + } s; + /* struct npa_lf_aura_op_int_s cn; */ +}; + +static inline u64 NPA_LF_AURA_OP_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_AURA_OP_INT(void) +{ + return 0x60; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_aura_op_limit + * + * NPA LF Aura Allocation Limit Register A 64-bit atomic load-and-add to + * this register returns a given aura's limit. A write sets the aura's + * limit. A read is RAZ. RSL accesses to this register are RAZ/WI. + */ +union npa_lf_aura_op_limit { + u64 u; + struct npa_lf_aura_op_limit_s { + u64 limit : 36; + u64 reserved_36_41 : 6; + u64 op_err : 1; + u64 reserved_43 : 1; + u64 aura : 20; + } s; + /* struct npa_lf_aura_op_limit_s cn; */ +}; + +static inline u64 NPA_LF_AURA_OP_LIMIT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_AURA_OP_LIMIT(void) +{ + return 0x50; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_aura_op_thresh + * + * NPA LF Aura Threshold Operation Register A 64-bit atomic load-and-add + * to this register reads NPA_AURA_HW_S[THRESH_UP,THRESH]. A write to the + * register writes NPA_AURA_HW_S[THRESH_UP,THRESH] and recomputes + * NPA_AURA_HW_S[THRESH_INT]. A read is RAZ. RSL accesses to this + * register are RAZ/WI. + */ +union npa_lf_aura_op_thresh { + u64 u; + struct npa_lf_aura_op_thresh_s { + u64 thresh : 36; + u64 reserved_36_41 : 6; + u64 op_err : 1; + u64 thresh_up : 1; + u64 aura : 20; + } s; + /* struct npa_lf_aura_op_thresh_s cn; */ +}; + +static inline u64 NPA_LF_AURA_OP_THRESH(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_AURA_OP_THRESH(void) +{ + return 0x70; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_err_int + * + * NPA LF Error Interrupt Register + */ +union npa_lf_err_int { + u64 u; + struct npa_lf_err_int_s { + u64 aura_dis : 1; + u64 aura_oor : 1; + u64 reserved_2 : 1; + u64 rmt_req_oor : 1; + u64 reserved_4_11 : 8; + u64 aura_fault : 1; + u64 pool_fault : 1; + u64 stack_fault : 1; + u64 qint_fault : 1; + u64 reserved_16_63 : 48; + } s; + /* struct npa_lf_err_int_s cn; */ +}; + +static inline u64 NPA_LF_ERR_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_ERR_INT(void) +{ + return 0x200; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_err_int_ena_w1c + * + * NPA LF Error Interrupt Enable Clear Register This register clears + * interrupt enable bits. + */ +union npa_lf_err_int_ena_w1c { + u64 u; + struct npa_lf_err_int_ena_w1c_s { + u64 aura_dis : 1; + u64 aura_oor : 1; + u64 reserved_2 : 1; + u64 rmt_req_oor : 1; + u64 reserved_4_11 : 8; + u64 aura_fault : 1; + u64 pool_fault : 1; + u64 stack_fault : 1; + u64 qint_fault : 1; + u64 reserved_16_63 : 48; + } s; + /* struct npa_lf_err_int_ena_w1c_s cn; */ +}; + +static inline u64 NPA_LF_ERR_INT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_ERR_INT_ENA_W1C(void) +{ + return 0x210; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_err_int_ena_w1s + * + * NPA LF Error Interrupt Enable Set Register This register sets + * interrupt enable bits. + */ +union npa_lf_err_int_ena_w1s { + u64 u; + struct npa_lf_err_int_ena_w1s_s { + u64 aura_dis : 1; + u64 aura_oor : 1; + u64 reserved_2 : 1; + u64 rmt_req_oor : 1; + u64 reserved_4_11 : 8; + u64 aura_fault : 1; + u64 pool_fault : 1; + u64 stack_fault : 1; + u64 qint_fault : 1; + u64 reserved_16_63 : 48; + } s; + /* struct npa_lf_err_int_ena_w1s_s cn; */ +}; + +static inline u64 NPA_LF_ERR_INT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_ERR_INT_ENA_W1S(void) +{ + return 0x218; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_err_int_w1s + * + * NPA LF Error Interrupt Set Register This register sets interrupt bits. + */ +union npa_lf_err_int_w1s { + u64 u; + struct npa_lf_err_int_w1s_s { + u64 aura_dis : 1; + u64 aura_oor : 1; + u64 reserved_2 : 1; + u64 rmt_req_oor : 1; + u64 reserved_4_11 : 8; + u64 aura_fault : 1; + u64 pool_fault : 1; + u64 stack_fault : 1; + u64 qint_fault : 1; + u64 reserved_16_63 : 48; + } s; + /* struct npa_lf_err_int_w1s_s cn; */ +}; + +static inline u64 NPA_LF_ERR_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_ERR_INT_W1S(void) +{ + return 0x208; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_pool_op_available + * + * NPA LF Pool Available Count Operation Register A 64-bit atomic load- + * and-add to this register returns a given pool's free pointer count. + * Reads and writes are RAZ/WI. RSL accesses to this register are + * RAZ/WI. + */ +union npa_lf_pool_op_available { + u64 u; + struct npa_lf_pool_op_available_s { + u64 count : 36; + u64 reserved_36_41 : 6; + u64 op_err : 1; + u64 reserved_43 : 1; + u64 aura : 20; + } s; + /* struct npa_lf_pool_op_available_s cn; */ +}; + +static inline u64 NPA_LF_POOL_OP_AVAILABLE(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_POOL_OP_AVAILABLE(void) +{ + return 0x110; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_pool_op_int + * + * NPA LF Pool Interrupt Operation Register A 64-bit atomic load-and-add + * to this register reads + * NPA_POOL_S[ERR_INT,ERR_INT_ENA,THRESH_INT,THRESH_INT_ENA]. A write + * optionally sets or clears these fields. A read is RAZ. RSL accesses + * to this register are RAZ/WI. + */ +union npa_lf_pool_op_int { + u64 u; + struct npa_lf_pool_op_int_s { + u64 err_int : 8; + u64 err_int_ena : 8; + u64 thresh_int : 1; + u64 thresh_int_ena : 1; + u64 reserved_18_41 : 24; + u64 op_err : 1; + u64 setop : 1; + u64 aura : 20; + } s; + /* struct npa_lf_pool_op_int_s cn; */ +}; + +static inline u64 NPA_LF_POOL_OP_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_POOL_OP_INT(void) +{ + return 0x160; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_pool_op_pc + * + * NPA LF Pool Performance Count Register A 64-bit atomic load-and-add to + * this register reads NPA_POOL_S[OP_PC] from a given aura's pool. The + * aura is selected by the atomic write data, whose format is + * NPA_AURA_OP_WDATA_S. Reads and writes are RAZ/WI. RSL accesses to + * this register are RAZ/WI. + */ +union npa_lf_pool_op_pc { + u64 u; + struct npa_lf_pool_op_pc_s { + u64 op_pc : 48; + u64 op_err : 1; + u64 reserved_49_63 : 15; + } s; + /* struct npa_lf_pool_op_pc_s cn; */ +}; + +static inline u64 NPA_LF_POOL_OP_PC(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_POOL_OP_PC(void) +{ + return 0x100; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_pool_op_ptr_end0 + * + * NPA LF Pool Pointer End Operation Register 0 A 128-bit write (STP) to + * the NPA_LF_POOL_OP_PTR_END0 and NPA_LF_POOL_OP_PTR_END1 registers + * writes to a given pool's pointer end value. All other accesses to + * these registers (e.g. reads and 64-bit writes) are RAZ/WI. RSL + * accesses to this register are RAZ/WI. + */ +union npa_lf_pool_op_ptr_end0 { + u64 u; + struct npa_lf_pool_op_ptr_end0_s { + u64 ptr_end : 64; + } s; + /* struct npa_lf_pool_op_ptr_end0_s cn; */ +}; + +static inline u64 NPA_LF_POOL_OP_PTR_END0(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_POOL_OP_PTR_END0(void) +{ + return 0x130; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_pool_op_ptr_end1 + * + * NPA LF Pool Pointer End Operation Register 1 See + * NPA_LF_POOL_OP_PTR_END0. RSL accesses to this register are RAZ/WI. + */ +union npa_lf_pool_op_ptr_end1 { + u64 u; + struct npa_lf_pool_op_ptr_end1_s { + u64 aura : 20; + u64 reserved_20_63 : 44; + } s; + /* struct npa_lf_pool_op_ptr_end1_s cn; */ +}; + +static inline u64 NPA_LF_POOL_OP_PTR_END1(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_POOL_OP_PTR_END1(void) +{ + return 0x138; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_pool_op_ptr_start0 + * + * NPA LF Pool Pointer Start Operation Register 0 A 128-bit write (STP) + * to the NPA_LF_POOL_OP_PTR_START0 and NPA_LF_POOL_OP_PTR_START1 + * registers writes to a given pool's pointer start value. All other + * accesses to these registers (e.g. reads and 64-bit writes) are RAZ/WI. + * RSL accesses to this register are RAZ/WI. + */ +union npa_lf_pool_op_ptr_start0 { + u64 u; + struct npa_lf_pool_op_ptr_start0_s { + u64 ptr_start : 64; + } s; + /* struct npa_lf_pool_op_ptr_start0_s cn; */ +}; + +static inline u64 NPA_LF_POOL_OP_PTR_START0(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_POOL_OP_PTR_START0(void) +{ + return 0x120; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_pool_op_ptr_start1 + * + * NPA LF Pool Pointer Start Operation Register 1 See + * NPA_LF_POOL_OP_PTR_START0. RSL accesses to this register are RAZ/WI. + */ +union npa_lf_pool_op_ptr_start1 { + u64 u; + struct npa_lf_pool_op_ptr_start1_s { + u64 aura : 20; + u64 reserved_20_63 : 44; + } s; + /* struct npa_lf_pool_op_ptr_start1_s cn; */ +}; + +static inline u64 NPA_LF_POOL_OP_PTR_START1(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_POOL_OP_PTR_START1(void) +{ + return 0x128; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_pool_op_thresh + * + * NPA LF Pool Threshold Operation Register A 64-bit atomic load-and-add + * to this register reads NPA_POOL_S[THRESH_UP,THRESH]. A write to the + * register writes NPA_POOL_S[THRESH_UP,THRESH]. A read is RAZ. RSL + * accesses to this register are RAZ/WI. + */ +union npa_lf_pool_op_thresh { + u64 u; + struct npa_lf_pool_op_thresh_s { + u64 thresh : 36; + u64 reserved_36_41 : 6; + u64 op_err : 1; + u64 thresh_up : 1; + u64 aura : 20; + } s; + /* struct npa_lf_pool_op_thresh_s cn; */ +}; + +static inline u64 NPA_LF_POOL_OP_THRESH(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_POOL_OP_THRESH(void) +{ + return 0x170; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_qint#_cnt + * + * NPA LF Queue Interrupt Count Registers + */ +union npa_lf_qintx_cnt { + u64 u; + struct npa_lf_qintx_cnt_s { + u64 count : 22; + u64 reserved_22_63 : 42; + } s; + /* struct npa_lf_qintx_cnt_s cn; */ +}; + +static inline u64 NPA_LF_QINTX_CNT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_QINTX_CNT(u64 a) +{ + return 0x300 + 0x1000 * a; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_qint#_ena_w1c + * + * NPA LF Queue Interrupt Enable Clear Registers This register clears + * interrupt enable bits. + */ +union npa_lf_qintx_ena_w1c { + u64 u; + struct npa_lf_qintx_ena_w1c_s { + u64 intr : 1; + u64 reserved_1_63 : 63; + } s; + /* struct npa_lf_qintx_ena_w1c_s cn; */ +}; + +static inline u64 NPA_LF_QINTX_ENA_W1C(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_QINTX_ENA_W1C(u64 a) +{ + return 0x330 + 0x1000 * a; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_qint#_ena_w1s + * + * NPA LF Queue Interrupt Enable Set Registers This register sets + * interrupt enable bits. + */ +union npa_lf_qintx_ena_w1s { + u64 u; + struct npa_lf_qintx_ena_w1s_s { + u64 intr : 1; + u64 reserved_1_63 : 63; + } s; + /* struct npa_lf_qintx_ena_w1s_s cn; */ +}; + +static inline u64 NPA_LF_QINTX_ENA_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_QINTX_ENA_W1S(u64 a) +{ + return 0x320 + 0x1000 * a; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_qint#_int + * + * NPA LF Queue Interrupt Registers + */ +union npa_lf_qintx_int { + u64 u; + struct npa_lf_qintx_int_s { + u64 intr : 1; + u64 reserved_1_63 : 63; + } s; + /* struct npa_lf_qintx_int_s cn; */ +}; + +static inline u64 NPA_LF_QINTX_INT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_QINTX_INT(u64 a) +{ + return 0x310 + 0x1000 * a; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_qint#_int_w1s + * + * INTERNAL: NPA LF Queue Interrupt Set Registers + */ +union npa_lf_qintx_int_w1s { + u64 u; + struct npa_lf_qintx_int_w1s_s { + u64 intr : 1; + u64 reserved_1_63 : 63; + } s; + /* struct npa_lf_qintx_int_w1s_s cn; */ +}; + +static inline u64 NPA_LF_QINTX_INT_W1S(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_QINTX_INT_W1S(u64 a) +{ + return 0x318 + 0x1000 * a; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_ras + * + * NPA LF RAS Interrupt Register + */ +union npa_lf_ras { + u64 u; + struct npa_lf_ras_s { + u64 aura_poison : 1; + u64 pool_poison : 1; + u64 stack_poison : 1; + u64 qint_poison : 1; + u64 reserved_4_63 : 60; + } s; + /* struct npa_lf_ras_s cn; */ +}; + +static inline u64 NPA_LF_RAS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_RAS(void) +{ + return 0x220; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_ras_ena_w1c + * + * NPA LF RAS Interrupt Enable Clear Register This register clears + * interrupt enable bits. + */ +union npa_lf_ras_ena_w1c { + u64 u; + struct npa_lf_ras_ena_w1c_s { + u64 aura_poison : 1; + u64 pool_poison : 1; + u64 stack_poison : 1; + u64 qint_poison : 1; + u64 reserved_4_63 : 60; + } s; + /* struct npa_lf_ras_ena_w1c_s cn; */ +}; + +static inline u64 NPA_LF_RAS_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_RAS_ENA_W1C(void) +{ + return 0x230; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_ras_ena_w1s + * + * NPA LF RAS Interrupt Enable Set Register This register sets interrupt + * enable bits. + */ +union npa_lf_ras_ena_w1s { + u64 u; + struct npa_lf_ras_ena_w1s_s { + u64 aura_poison : 1; + u64 pool_poison : 1; + u64 stack_poison : 1; + u64 qint_poison : 1; + u64 reserved_4_63 : 60; + } s; + /* struct npa_lf_ras_ena_w1s_s cn; */ +}; + +static inline u64 NPA_LF_RAS_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_RAS_ENA_W1S(void) +{ + return 0x238; +} + +/** + * Register (RVU_PFVF_BAR2) npa_lf_ras_w1s + * + * NPA LF RAS Interrupt Set Register This register sets interrupt bits. + */ +union npa_lf_ras_w1s { + u64 u; + struct npa_lf_ras_w1s_s { + u64 aura_poison : 1; + u64 pool_poison : 1; + u64 stack_poison : 1; + u64 qint_poison : 1; + u64 reserved_4_63 : 60; + } s; + /* struct npa_lf_ras_w1s_s cn; */ +}; + +static inline u64 NPA_LF_RAS_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_LF_RAS_W1S(void) +{ + return 0x228; +} + +/** + * Register (RVU_PF_BAR0) npa_priv_af_int_cfg + * + * NPA Privileged AF Interrupt Configuration Register + */ +union npa_priv_af_int_cfg { + u64 u; + struct npa_priv_af_int_cfg_s { + u64 msix_offset : 11; + u64 reserved_11 : 1; + u64 msix_size : 8; + u64 reserved_20_63 : 44; + } s; + /* struct npa_priv_af_int_cfg_s cn; */ +}; + +static inline u64 NPA_PRIV_AF_INT_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_PRIV_AF_INT_CFG(void) +{ + return 0x10000; +} + +/** + * Register (RVU_PF_BAR0) npa_priv_lf#_cfg + * + * NPA Privileged Local Function Configuration Registers These registers + * allow each NPA local function (LF) to be provisioned to a VF/PF slot + * for RVU. See also NPA_AF_RVU_LF_CFG_DEBUG. Software should read this + * register after write to ensure that the LF is mapped to [PF_FUNC] + * before issuing transactions to the mapped PF and function. [SLOT] + * must be zero. Internal: Hardware ignores [SLOT] and always assumes + * 0x0. + */ +union npa_priv_lfx_cfg { + u64 u; + struct npa_priv_lfx_cfg_s { + u64 slot : 8; + u64 pf_func : 16; + u64 reserved_24_62 : 39; + u64 ena : 1; + } s; + /* struct npa_priv_lfx_cfg_s cn; */ +}; + +static inline u64 NPA_PRIV_LFX_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_PRIV_LFX_CFG(u64 a) +{ + return 0x10010 + 0x100 * a; +} + +/** + * Register (RVU_PF_BAR0) npa_priv_lf#_int_cfg + * + * NPA Privileged LF Interrupt Configuration Registers + */ +union npa_priv_lfx_int_cfg { + u64 u; + struct npa_priv_lfx_int_cfg_s { + u64 msix_offset : 11; + u64 reserved_11 : 1; + u64 msix_size : 8; + u64 reserved_20_63 : 44; + } s; + /* struct npa_priv_lfx_int_cfg_s cn; */ +}; + +static inline u64 NPA_PRIV_LFX_INT_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPA_PRIV_LFX_INT_CFG(u64 a) +{ + return 0x10020 + 0x100 * a; +} + +#endif /* __CSRS_NPA_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-npc.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-npc.h new file mode 100644 index 000000000..c1c4baabe --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-npc.h @@ -0,0 +1,1629 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Marvell International Ltd. + * + * https://spdx.org/licenses + */ +#ifndef __CSRS_NPC_H__ +#define __CSRS_NPC_H__ + +/** + * @file + * + * Configuration and status register (CSR) address and type definitions for + * NPC. + * + * This file is auto generated. Do not edit. + * + */ + +/** + * Enumeration npc_errlev_e + * + * NPC Error Level Enumeration Enumerates the lowest protocol layer + * containing an error. + */ +#define NPC_ERRLEV_E_LA (1) +#define NPC_ERRLEV_E_LB (2) +#define NPC_ERRLEV_E_LC (3) +#define NPC_ERRLEV_E_LD (4) +#define NPC_ERRLEV_E_LE (5) +#define NPC_ERRLEV_E_LF (6) +#define NPC_ERRLEV_E_LG (7) +#define NPC_ERRLEV_E_LH (8) +#define NPC_ERRLEV_E_NIX (0xf) +#define NPC_ERRLEV_E_RX(a) (0 + (a)) +#define NPC_ERRLEV_E_RE (0) + +/** + * Enumeration npc_intf_e + * + * NPC Interface Enumeration Enumerates the NPC interfaces. + */ +#define NPC_INTF_E_NIXX_RX(a) (0 + 2 * (a)) +#define NPC_INTF_E_NIXX_TX(a) (1 + 2 * (a)) + +/** + * Enumeration npc_lid_e + * + * NPC Layer ID Enumeration Enumerates layers parsed by NPC. + */ +#define NPC_LID_E_LA (0) +#define NPC_LID_E_LB (1) +#define NPC_LID_E_LC (2) +#define NPC_LID_E_LD (3) +#define NPC_LID_E_LE (4) +#define NPC_LID_E_LF (5) +#define NPC_LID_E_LG (6) +#define NPC_LID_E_LH (7) + +/** + * Enumeration npc_lkupop_e + * + * NPC Lookup Operation Enumeration Enumerates the lookup operation for + * NPC_AF_LKUP_CTL[OP]. + */ +#define NPC_LKUPOP_E_KEY (1) +#define NPC_LKUPOP_E_PKT (0) + +/** + * Enumeration npc_mcamkeyw_e + * + * NPC MCAM Search Key Width Enumeration + */ +#define NPC_MCAMKEYW_E_X1 (0) +#define NPC_MCAMKEYW_E_X2 (1) +#define NPC_MCAMKEYW_E_X4 (2) + +/** + * Structure npc_layer_info_s + * + * NPC Layer Parse Information Structure This structure specifies the + * format of NPC_RESULT_S[LA,LB,...,LH]. + */ +union npc_layer_info_s { + u32 u; + struct npc_layer_info_s_s { + u32 lptr : 8; + u32 flags : 8; + u32 ltype : 4; + u32 reserved_20_31 : 12; + } s; + /* struct npc_layer_info_s_s cn; */ +}; + +/** + * Structure npc_layer_kex_s + * + * NPC Layer MCAM Search Key Extract Structure This structure specifies + * the format of each of the NPC_PARSE_KEX_S[LA,LB,...,LH] fields. It + * contains the subset of NPC_LAYER_INFO_S fields that can be included in + * the MCAM search key. See NPC_PARSE_KEX_S and NPC_AF_INTF()_KEX_CFG. + */ +union npc_layer_kex_s { + u32 u; + struct npc_layer_kex_s_s { + u32 flags : 8; + u32 ltype : 4; + u32 reserved_12_31 : 20; + } s; + /* struct npc_layer_kex_s_s cn; */ +}; + +/** + * Structure npc_mcam_key_x1_s + * + * NPC MCAM Search Key X1 Structure This structure specifies the MCAM + * search key format used by an interface when + * NPC_AF_INTF()_KEX_CFG[KEYW] = NPC_MCAMKEYW_E::X1. + */ +union npc_mcam_key_x1_s { + u64 u[3]; + struct npc_mcam_key_x1_s_s { + u64 intf : 2; + u64 reserved_2_63 : 62; + u64 kw0 : 64; + u64 kw1 : 48; + u64 reserved_176_191 : 16; + } s; + /* struct npc_mcam_key_x1_s_s cn; */ +}; + +/** + * Structure npc_mcam_key_x2_s + * + * NPC MCAM Search Key X2 Structure This structure specifies the MCAM + * search key format used by an interface when + * NPC_AF_INTF()_KEX_CFG[KEYW] = NPC_MCAMKEYW_E::X2. + */ +union npc_mcam_key_x2_s { + u64 u[5]; + struct npc_mcam_key_x2_s_s { + u64 intf : 2; + u64 reserved_2_63 : 62; + u64 kw0 : 64; + u64 kw1 : 64; + u64 kw2 : 64; + u64 kw3 : 32; + u64 reserved_288_319 : 32; + } s; + /* struct npc_mcam_key_x2_s_s cn; */ +}; + +/** + * Structure npc_mcam_key_x4_s + * + * NPC MCAM Search Key X4 Structure This structure specifies the MCAM + * search key format used by an interface when + * NPC_AF_INTF()_KEX_CFG[KEYW] = NPC_MCAMKEYW_E::X4. + */ +union npc_mcam_key_x4_s { + u64 u[8]; + struct npc_mcam_key_x4_s_s { + u64 intf : 2; + u64 reserved_2_63 : 62; + u64 kw0 : 64; + u64 kw1 : 64; + u64 kw2 : 64; + u64 kw3 : 64; + u64 kw4 : 64; + u64 kw5 : 64; + u64 kw6 : 64; + } s; + /* struct npc_mcam_key_x4_s_s cn; */ +}; + +/** + * Structure npc_parse_kex_s + * + * NPC Parse Key Extract Structure This structure contains the subset of + * NPC_RESULT_S fields that can be included in the MCAM search key. See + * NPC_AF_INTF()_KEX_CFG. + */ +union npc_parse_kex_s { + u64 u[2]; + struct npc_parse_kex_s_s { + u64 chan : 12; + u64 errlev : 4; + u64 errcode : 8; + u64 l2m : 1; + u64 l2b : 1; + u64 l3m : 1; + u64 l3b : 1; + u64 la : 12; + u64 lb : 12; + u64 lc : 12; + u64 ld : 12; + u64 le : 12; + u64 lf : 12; + u64 lg : 12; + u64 lh : 12; + u64 reserved_124_127 : 4; + } s; + /* struct npc_parse_kex_s_s cn; */ +}; + +/** + * Structure npc_result_s + * + * NPC Result Structure This structure contains a packet's parse and flow + * identification information. + */ +union npc_result_s { + u64 u[6]; + struct npc_result_s_s { + u64 intf : 2; + u64 pkind : 6; + u64 chan : 12; + u64 errlev : 4; + u64 errcode : 8; + u64 l2m : 1; + u64 l2b : 1; + u64 l3m : 1; + u64 l3b : 1; + u64 eoh_ptr : 8; + u64 reserved_44_63 : 20; + u64 action : 64; + u64 vtag_action : 64; + u64 la : 20; + u64 lb : 20; + u64 lc : 20; + u64 reserved_252_255 : 4; + u64 ld : 20; + u64 le : 20; + u64 lf : 20; + u64 reserved_316_319 : 4; + u64 lg : 20; + u64 lh : 20; + u64 reserved_360_383 : 24; + } s; + /* struct npc_result_s_s cn; */ +}; + +/** + * Register (RVU_PF_BAR0) npc_af_active_pc + * + * NPC Interrupt-Timer Configuration Register + */ +union npc_af_active_pc { + u64 u; + struct npc_af_active_pc_s { + u64 active_pc : 64; + } s; + /* struct npc_af_active_pc_s cn; */ +}; + +static inline u64 NPC_AF_ACTIVE_PC(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_ACTIVE_PC(void) +{ + return 0x10; +} + +/** + * Register (RVU_PF_BAR0) npc_af_blk_rst + * + * NPC AF Block Reset Register + */ +union npc_af_blk_rst { + u64 u; + struct npc_af_blk_rst_s { + u64 rst : 1; + u64 reserved_1_62 : 62; + u64 busy : 1; + } s; + /* struct npc_af_blk_rst_s cn; */ +}; + +static inline u64 NPC_AF_BLK_RST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_BLK_RST(void) +{ + return 0x40; +} + +/** + * Register (RVU_PF_BAR0) npc_af_cfg + * + * NPC AF General Configuration Register + */ +union npc_af_cfg { + u64 u; + struct npc_af_cfg_s { + u64 reserved_0_1 : 2; + u64 cclk_force : 1; + u64 force_intf_clk_en : 1; + u64 reserved_4_63 : 60; + } s; + /* struct npc_af_cfg_s cn; */ +}; + +static inline u64 NPC_AF_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_CFG(void) +{ + return 0; +} + +/** + * Register (RVU_PF_BAR0) npc_af_const + * + * NPC AF Constants Register This register contains constants for + * software discovery. + */ +union npc_af_const { + u64 u; + struct npc_af_const_s { + u64 intfs : 4; + u64 lids : 4; + u64 kpus : 5; + u64 reserved_13_15 : 3; + u64 mcam_bank_width : 10; + u64 reserved_26_27 : 2; + u64 mcam_bank_depth : 16; + u64 mcam_banks : 4; + u64 match_stats : 16; + } s; + /* struct npc_af_const_s cn; */ +}; + +static inline u64 NPC_AF_CONST(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_CONST(void) +{ + return 0x20; +} + +/** + * Register (RVU_PF_BAR0) npc_af_const1 + * + * NPC AF Constants 1 Register This register contains constants for + * software discovery. + */ +union npc_af_const1 { + u64 u; + struct npc_af_const1_s { + u64 kpu_entries : 12; + u64 pkinds : 8; + u64 cpi_size : 16; + u64 reserved_36_63 : 28; + } s; + /* struct npc_af_const1_s cn; */ +}; + +static inline u64 NPC_AF_CONST1(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_CONST1(void) +{ + return 0x30; +} + +/** + * Register (RVU_PF_BAR0) npc_af_cpi#_cfg + * + * NPC AF Channel Parse Index Table Registers + */ +union npc_af_cpix_cfg { + u64 u; + struct npc_af_cpix_cfg_s { + u64 padd : 4; + u64 reserved_4_63 : 60; + } s; + /* struct npc_af_cpix_cfg_s cn; */ +}; + +static inline u64 NPC_AF_CPIX_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_CPIX_CFG(u64 a) +{ + return 0x200000 + 8 * a; +} + +/** + * Register (RVU_PF_BAR0) npc_af_dbg_ctl + * + * NPC AF Debug Control Register This register controls the capture of + * debug information in NPC_AF_KPU()_DBG, NPC_AF_MCAM_DBG, + * NPC_AF_DBG_DATA() and NPC_AF_DBG_RESULT(). + */ +union npc_af_dbg_ctl { + u64 u; + struct npc_af_dbg_ctl_s { + u64 continuous : 1; + u64 lkup_dbg : 1; + u64 intf_dbg : 4; + u64 reserved_6_63 : 58; + } s; + /* struct npc_af_dbg_ctl_s cn; */ +}; + +static inline u64 NPC_AF_DBG_CTL(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_DBG_CTL(void) +{ + return 0x3000000; +} + +/** + * Register (RVU_PF_BAR0) npc_af_dbg_data# + * + * NPC AF Debug Data Registers These registers contain the packet header + * data of the last packet/lookup whose debug information is captured by + * NPC_AF_DBG_CTL[INTF_DBG,LKUP_DBG]. + */ +union npc_af_dbg_datax { + u64 u; + struct npc_af_dbg_datax_s { + u64 data : 64; + } s; + /* struct npc_af_dbg_datax_s cn; */ +}; + +static inline u64 NPC_AF_DBG_DATAX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_DBG_DATAX(u64 a) +{ + return 0x3001400 + 0x10 * a; +} + +/** + * Register (RVU_PF_BAR0) npc_af_dbg_result# + * + * NPC AF Debug Result Registers These registers contain the result data + * of the last packet/lookup whose debug information is captured by + * NPC_AF_DBG_CTL[INTF_DBG,LKUP_DBG]. Internal: FIXME - add note about + * coherency of data in continuous packet capture mode. + */ +union npc_af_dbg_resultx { + u64 u; + struct npc_af_dbg_resultx_s { + u64 data : 64; + } s; + /* struct npc_af_dbg_resultx_s cn; */ +}; + +static inline u64 NPC_AF_DBG_RESULTX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_DBG_RESULTX(u64 a) +{ + return 0x3001800 + 0x10 * a; +} + +/** + * Register (RVU_PF_BAR0) npc_af_dbg_status + * + * NPC AF Debug Status Register + */ +union npc_af_dbg_status { + u64 u; + struct npc_af_dbg_status_s { + u64 done : 1; + u64 reserved_1_63 : 63; + } s; + /* struct npc_af_dbg_status_s cn; */ +}; + +static inline u64 NPC_AF_DBG_STATUS(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_DBG_STATUS(void) +{ + return 0x3000010; +} + +/** + * Register (RVU_PF_BAR0) npc_af_dv_fc_scratch + * + * INTERNAL: NPC AF Scratch Register Internal: This register is for + * internal DV purpose. + */ +union npc_af_dv_fc_scratch { + u64 u; + struct npc_af_dv_fc_scratch_s { + u64 it : 64; + } s; + /* struct npc_af_dv_fc_scratch_s cn; */ +}; + +static inline u64 NPC_AF_DV_FC_SCRATCH(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_DV_FC_SCRATCH(void) +{ + return 0x60; +} + +/** + * Register (RVU_PF_BAR0) npc_af_eco0 + * + * INTERNAL: ECO 0 Register + */ +union npc_af_eco0 { + u64 u; + struct npc_af_eco0_s { + u64 eco_rw : 32; + u64 reserved_32_63 : 32; + } s; + /* struct npc_af_eco0_s cn; */ +}; + +static inline u64 NPC_AF_ECO0(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_ECO0(void) +{ + return 0x200; +} + +/** + * Register (RVU_PF_BAR0) npc_af_ikpu_err_ctl + * + * NPC AF Initial KPU Error Control Registers Similar to + * NPC_AF_KPU()_ERR_CTL, but specifies values captured in + * NPC_RESULT_S[ERRLEV,ERRCODE] for errors detected by the PKIND-based + * initial actions from NPC_AF_PKIND()_ACTION0 and + * NPC_AF_PKIND()_ACTION1. [DP_OFFSET_ERRCODE] from this register is + * never used. + */ +union npc_af_ikpu_err_ctl { + u64 u; + struct npc_af_ikpu_err_ctl_s { + u64 errlev : 4; + u64 dp_offset_errcode : 8; + u64 ptr_advance_errcode : 8; + u64 var_len_offset_errcode : 8; + u64 reserved_28_63 : 36; + } s; + /* struct npc_af_ikpu_err_ctl_s cn; */ +}; + +static inline u64 NPC_AF_IKPU_ERR_CTL(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_IKPU_ERR_CTL(void) +{ + return 0x3000080; +} + +/** + * Register (RVU_PF_BAR0) npc_af_intf#_kex_cfg + * + * NPC AF Interface Key Extract Configuration Registers + */ +union npc_af_intfx_kex_cfg { + u64 u; + struct npc_af_intfx_kex_cfg_s { + u64 parse_nibble_ena : 31; + u64 reserved_31 : 1; + u64 keyw : 3; + u64 reserved_35_63 : 29; + } s; + /* struct npc_af_intfx_kex_cfg_s cn; */ +}; + +static inline u64 NPC_AF_INTFX_KEX_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_INTFX_KEX_CFG(u64 a) +{ + return 0x1010 + 0x100 * a; +} + +/** + * Register (RVU_PF_BAR0) npc_af_intf#_ldata#_flags#_cfg + * + * NPC AF Interface Layer Data Flags Configuration Registers These + * registers control the extraction of layer data (LDATA) into the MCAM + * search key for each interface based on the FLAGS\<3:0\> bits of two + * layers selected by NPC_AF_KEX_LDATA()_FLAGS_CFG. + */ +union npc_af_intfx_ldatax_flagsx_cfg { + u64 u; + struct npc_af_intfx_ldatax_flagsx_cfg_s { + u64 key_offset : 6; + u64 reserved_6 : 1; + u64 ena : 1; + u64 hdr_offset : 8; + u64 bytesm1 : 4; + u64 reserved_20_63 : 44; + } s; + /* struct npc_af_intfx_ldatax_flagsx_cfg_s cn; */ +}; + +static inline u64 NPC_AF_INTFX_LDATAX_FLAGSX_CFG(u64 a, u64 b, u64 c) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_INTFX_LDATAX_FLAGSX_CFG(u64 a, u64 b, u64 c) +{ + return 0x980000 + 0x10000 * a + 0x1000 * b + 8 * c; +} + +/** + * Register (RVU_PF_BAR0) npc_af_intf#_lid#_lt#_ld#_cfg + * + * NPC AF Interface Layer Data Extract Configuration Registers These + * registers control the extraction of layer data (LDATA) into the MCAM + * search key for each interface. Up to two LDATA fields can be extracted + * per layer (LID(0..7) indexed by NPC_LID_E), with up to 16 bytes per + * LDATA field. For each layer, the corresponding NPC_LAYER_INFO_S[LTYPE] + * value in NPC_RESULT_S is used as the LTYPE(0..15) index and select the + * associated LDATA(0..1) registers. NPC_LAYER_INFO_S[LTYPE]=0x0 means + * the corresponding layer not parsed (invalid), so software should keep + * NPC_AF_INTF()_LID()_LT(0)_LD()_CFG[ENA] clear to disable extraction + * when LTYPE is zero. + */ +union npc_af_intfx_lidx_ltx_ldx_cfg { + u64 u; + struct npc_af_intfx_lidx_ltx_ldx_cfg_s { + u64 key_offset : 6; + u64 flags_ena : 1; + u64 ena : 1; + u64 hdr_offset : 8; + u64 bytesm1 : 4; + u64 reserved_20_63 : 44; + } s; + /* struct npc_af_intfx_lidx_ltx_ldx_cfg_s cn; */ +}; + +static inline u64 NPC_AF_INTFX_LIDX_LTX_LDX_CFG(u64 a, u64 b, u64 c, u64 d) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_INTFX_LIDX_LTX_LDX_CFG(u64 a, u64 b, u64 c, u64 d) +{ + return 0x900000 + 0x10000 * a + 0x1000 * b + 0x20 * c + 8 * d; +} + +/** + * Register (RVU_PF_BAR0) npc_af_intf#_miss_act + * + * NPC AF Interface MCAM Miss Action Data Registers When a combination of + * NPC_AF_MCAME()_BANK()_CAM()_* and NPC_AF_MCAME()_BANK()_CFG[ENA] + * yields an MCAM miss for a packet, this register specifies the packet's + * match action captured in NPC_RESULT_S[ACTION]. + */ +union npc_af_intfx_miss_act { + u64 u; + struct npc_af_intfx_miss_act_s { + u64 action : 64; + } s; + /* struct npc_af_intfx_miss_act_s cn; */ +}; + +static inline u64 NPC_AF_INTFX_MISS_ACT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_INTFX_MISS_ACT(u64 a) +{ + return 0x1a00000 + 0x10 * a; +} + +/** + * Register (RVU_PF_BAR0) npc_af_intf#_miss_stat_act + * + * NPC AF Interface MCAM Miss Stat Action Data Registers Used to + * optionally increment a NPC_AF_MATCH_STAT() counter when a packet + * misses an MCAM entry. + */ +union npc_af_intfx_miss_stat_act { + u64 u; + struct npc_af_intfx_miss_stat_act_s { + u64 stat_sel : 9; + u64 ena : 1; + u64 reserved_10_63 : 54; + } s; + /* struct npc_af_intfx_miss_stat_act_s cn; */ +}; + +static inline u64 NPC_AF_INTFX_MISS_STAT_ACT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_INTFX_MISS_STAT_ACT(u64 a) +{ + return 0x1880040 + 8 * a; +} + +/** + * Register (RVU_PF_BAR0) npc_af_intf#_miss_tag_act + * + * NPC AF Interface MCAM Miss VTag Action Data Registers When a + * combination of NPC_AF_MCAME()_BANK()_CAM()_* and + * NPC_AF_MCAME()_BANK()_CFG[ENA] yields an MCAM miss for a packet, this + * register specifies the packet's match Vtag action captured in + * NPC_RESULT_S[VTAG_ACTION]. + */ +union npc_af_intfx_miss_tag_act { + u64 u; + struct npc_af_intfx_miss_tag_act_s { + u64 vtag_action : 64; + } s; + /* struct npc_af_intfx_miss_tag_act_s cn; */ +}; + +static inline u64 NPC_AF_INTFX_MISS_TAG_ACT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_INTFX_MISS_TAG_ACT(u64 a) +{ + return 0x1b00008 + 0x10 * a; +} + +/** + * Register (RVU_PF_BAR0) npc_af_intf#_stat + * + * NPC AF Interface Statistics Registers Statistics per interface. Index + * enumerated by NPC_INTF_E. + */ +union npc_af_intfx_stat { + u64 u; + struct npc_af_intfx_stat_s { + u64 count : 48; + u64 reserved_48_63 : 16; + } s; + /* struct npc_af_intfx_stat_s cn; */ +}; + +static inline u64 NPC_AF_INTFX_STAT(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_INTFX_STAT(u64 a) +{ + return 0x2000800 + 0x10 * a; +} + +/** + * Register (RVU_PF_BAR0) npc_af_kcam_scrub_ctl + * + * NPC AF KCAM Scrub Control Register + */ +union npc_af_kcam_scrub_ctl { + u64 u; + struct npc_af_kcam_scrub_ctl_s { + u64 ena : 1; + u64 reserved_1_7 : 7; + u64 lp_dis : 1; + u64 reserved_9_15 : 7; + u64 toth : 4; + u64 reserved_20_63 : 44; + } s; + /* struct npc_af_kcam_scrub_ctl_s cn; */ +}; + +static inline u64 NPC_AF_KCAM_SCRUB_CTL(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_KCAM_SCRUB_CTL(void) +{ + return 0xb0; +} + +/** + * Register (RVU_PF_BAR0) npc_af_kex_ldata#_flags_cfg + * + * NPC AF Key Extract Layer Data Flags Configuration Register + */ +union npc_af_kex_ldatax_flags_cfg { + u64 u; + struct npc_af_kex_ldatax_flags_cfg_s { + u64 lid : 3; + u64 reserved_3_63 : 61; + } s; + /* struct npc_af_kex_ldatax_flags_cfg_s cn; */ +}; + +static inline u64 NPC_AF_KEX_LDATAX_FLAGS_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_KEX_LDATAX_FLAGS_CFG(u64 a) +{ + return 0x800 + 8 * a; +} + +/** + * Register (RVU_PF_BAR0) npc_af_kpu#_cfg + * + * NPC AF KPU Configuration Registers + */ +union npc_af_kpux_cfg { + u64 u; + struct npc_af_kpux_cfg_s { + u64 ena : 1; + u64 reserved_1_63 : 63; + } s; + /* struct npc_af_kpux_cfg_s cn; */ +}; + +static inline u64 NPC_AF_KPUX_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_KPUX_CFG(u64 a) +{ + return 0x500 + 8 * a; +} + +/** + * Register (RVU_PF_BAR0) npc_af_kpu#_dbg + * + * NPC AF KPU Debug Registers This register contains information for the + * last packet/lookup for which debug is enabled by + * NPC_AF_DBG_CTL[INTF_DBG,LKUP_DBG]. The register contents are undefined + * when debug information is captured for a software key lookup + * (NPC_AF_LKUP_CTL[OP] = NPC_LKUPOP_E::KEY). + */ +union npc_af_kpux_dbg { + u64 u; + struct npc_af_kpux_dbg_s { + u64 hit_entry : 8; + u64 byp : 1; + u64 reserved_9_63 : 55; + } s; + /* struct npc_af_kpux_dbg_s cn; */ +}; + +static inline u64 NPC_AF_KPUX_DBG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_KPUX_DBG(u64 a) +{ + return 0x3000020 + 0x100 * a; +} + +/** + * Register (RVU_PF_BAR0) npc_af_kpu#_entry#_action0 + * + * NPC AF KPU Entry Action Data 0 Registers When a KPU's search data + * matches a KPU CAM entry in NPC_AF_KPU()_ENTRY()_CAM(), the + * corresponding entry action in NPC_AF_KPU()_ENTRY()_ACTION0 and + * NPC_AF_KPU()_ENTRY()_ACTION1 specifies the next state and operations + * to perform before exiting the KPU. + */ +union npc_af_kpux_entryx_action0 { + u64 u; + struct npc_af_kpux_entryx_action0_s { + u64 var_len_shift : 3; + u64 var_len_right : 1; + u64 var_len_mask : 8; + u64 var_len_offset : 8; + u64 ptr_advance : 8; + u64 capture_flags : 8; + u64 capture_ltype : 4; + u64 capture_lid : 3; + u64 reserved_43 : 1; + u64 next_state : 8; + u64 parse_done : 1; + u64 capture_ena : 1; + u64 byp_count : 3; + u64 reserved_57_63 : 7; + } s; + /* struct npc_af_kpux_entryx_action0_s cn; */ +}; + +static inline u64 NPC_AF_KPUX_ENTRYX_ACTION0(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_KPUX_ENTRYX_ACTION0(u64 a, u64 b) +{ + return 0x100020 + 0x4000 * a + 0x40 * b; +} + +/** + * Register (RVU_PF_BAR0) npc_af_kpu#_entry#_action1 + * + * NPC AF KPU Entry Action Data 0 Registers See + * NPC_AF_KPU()_ENTRY()_ACTION0. + */ +union npc_af_kpux_entryx_action1 { + u64 u; + struct npc_af_kpux_entryx_action1_s { + u64 dp0_offset : 8; + u64 dp1_offset : 8; + u64 dp2_offset : 8; + u64 errcode : 8; + u64 errlev : 4; + u64 reserved_36_63 : 28; + } s; + /* struct npc_af_kpux_entryx_action1_s cn; */ +}; + +static inline u64 NPC_AF_KPUX_ENTRYX_ACTION1(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_KPUX_ENTRYX_ACTION1(u64 a, u64 b) +{ + return 0x100028 + 0x4000 * a + 0x40 * b; +} + +/** + * Register (RVU_PF_BAR0) npc_af_kpu#_entry#_cam# + * + * NPC AF KPU Entry CAM Registers KPU comparison ternary data. The field + * values in NPC_AF_KPU()_ENTRY()_CAM() are ternary, where each data bit + * of the search key matches as follows: _ [CAM(1)]\=0, + * [CAM(0)]\=0: Always match; search key data\ don't care. _ + * [CAM(1)]\=0, [CAM(0)]\=1: Match when search key data\ == + * 0. _ [CAM(1)]\=1, [CAM(0)]\=0: Match when search key data\ + * == 1. _ [CAM(1)]\=1, [CAM(0)]\=1: Reserved. The reserved + * combination is not allowed. Hardware suppresses any write to CAM(0) or + * CAM(1) that would result in the reserved combination for any CAM bit. + * The reset value for all non-reserved fields is all zeros for CAM(1) + * and all ones for CAM(0), matching a search key of all zeros. Software + * must program a default entry for each KPU, e.g. by programming each + * KPU's last entry {b} (NPC_AF_KPU()_ENTRY({b})_CAM()) to always match + * all bits. + */ +union npc_af_kpux_entryx_camx { + u64 u; + struct npc_af_kpux_entryx_camx_s { + u64 dp0_data : 16; + u64 dp1_data : 16; + u64 dp2_data : 16; + u64 state : 8; + u64 reserved_56_63 : 8; + } s; + /* struct npc_af_kpux_entryx_camx_s cn; */ +}; + +static inline u64 NPC_AF_KPUX_ENTRYX_CAMX(u64 a, u64 b, u64 c) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_KPUX_ENTRYX_CAMX(u64 a, u64 b, u64 c) +{ + return 0x100000 + 0x4000 * a + 0x40 * b + 8 * c; +} + +/** + * Register (RVU_PF_BAR0) npc_af_kpu#_entry_dis# + * + * NPC AF KPU Entry Disable Registers See NPC_AF_KPU()_ENTRY()_ACTION0. + */ +union npc_af_kpux_entry_disx { + u64 u; + struct npc_af_kpux_entry_disx_s { + u64 dis : 64; + } s; + /* struct npc_af_kpux_entry_disx_s cn; */ +}; + +static inline u64 NPC_AF_KPUX_ENTRY_DISX(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_KPUX_ENTRY_DISX(u64 a, u64 b) +{ + return 0x180000 + 0x40 * a + 8 * b; +} + +/** + * Register (RVU_PF_BAR0) npc_af_kpu#_err_ctl + * + * NPC AF KPU Error Control Registers This register specifies values + * captured in NPC_RESULT_S[ERRLEV,ERRCODE] when errors are detected by a + * KPU. + */ +union npc_af_kpux_err_ctl { + u64 u; + struct npc_af_kpux_err_ctl_s { + u64 errlev : 4; + u64 dp_offset_errcode : 8; + u64 ptr_advance_errcode : 8; + u64 var_len_offset_errcode : 8; + u64 reserved_28_63 : 36; + } s; + /* struct npc_af_kpux_err_ctl_s cn; */ +}; + +static inline u64 NPC_AF_KPUX_ERR_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_KPUX_ERR_CTL(u64 a) +{ + return 0x30000a0 + 0x100 * a; +} + +/** + * Register (RVU_PF_BAR0) npc_af_kpu_diag + * + * INTERNAL : NPC AF Debug Result Registers + */ +union npc_af_kpu_diag { + u64 u; + struct npc_af_kpu_diag_s { + u64 skip_dis : 1; + u64 reserved_1_63 : 63; + } s; + /* struct npc_af_kpu_diag_s cn; */ +}; + +static inline u64 NPC_AF_KPU_DIAG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_KPU_DIAG(void) +{ + return 0x3002000; +} + +/** + * Register (RVU_PF_BAR0) npc_af_lkup_ctl + * + * NPC AF Software Lookup Control Registers + */ +union npc_af_lkup_ctl { + u64 u; + struct npc_af_lkup_ctl_s { + u64 intf : 2; + u64 pkind : 6; + u64 chan : 12; + u64 hdr_sizem1 : 8; + u64 op : 3; + u64 exec : 1; + u64 reserved_32_63 : 32; + } s; + /* struct npc_af_lkup_ctl_s cn; */ +}; + +static inline u64 NPC_AF_LKUP_CTL(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_LKUP_CTL(void) +{ + return 0x2000000; +} + +/** + * Register (RVU_PF_BAR0) npc_af_lkup_data# + * + * NPC AF Software Lookup Data Registers + */ +union npc_af_lkup_datax { + u64 u; + struct npc_af_lkup_datax_s { + u64 data : 64; + } s; + /* struct npc_af_lkup_datax_s cn; */ +}; + +static inline u64 NPC_AF_LKUP_DATAX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_LKUP_DATAX(u64 a) +{ + return 0x2000200 + 0x10 * a; +} + +/** + * Register (RVU_PF_BAR0) npc_af_lkup_result# + * + * NPC AF Software Lookup Result Registers + */ +union npc_af_lkup_resultx { + u64 u; + struct npc_af_lkup_resultx_s { + u64 data : 64; + } s; + /* struct npc_af_lkup_resultx_s cn; */ +}; + +static inline u64 NPC_AF_LKUP_RESULTX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_LKUP_RESULTX(u64 a) +{ + return 0x2000400 + 0x10 * a; +} + +/** + * Register (RVU_PF_BAR0) npc_af_match_stat# + * + * NPC AF Match Statistics Registers + */ +union npc_af_match_statx { + u64 u; + struct npc_af_match_statx_s { + u64 count : 48; + u64 reserved_48_63 : 16; + } s; + /* struct npc_af_match_statx_s cn; */ +}; + +static inline u64 NPC_AF_MATCH_STATX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_MATCH_STATX(u64 a) +{ + return 0x1880008 + 0x100 * a; +} + +/** + * Register (RVU_PF_BAR0) npc_af_mcam_bank#_hit# + * + * NPC AF MCAM Bank Hit Registers + */ +union npc_af_mcam_bankx_hitx { + u64 u; + struct npc_af_mcam_bankx_hitx_s { + u64 hit : 64; + } s; + /* struct npc_af_mcam_bankx_hitx_s cn; */ +}; + +static inline u64 NPC_AF_MCAM_BANKX_HITX(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_MCAM_BANKX_HITX(u64 a, u64 b) +{ + return 0x1c80000 + 0x100 * a + 0x10 * b; +} + +/** + * Register (RVU_PF_BAR0) npc_af_mcam_dbg + * + * NPC AF MCAM Debug Register This register contains information for the + * last packet/lookup for which debug is enabled by + * NPC_AF_DBG_CTL[INTF_DBG,LKUP_DBG]. + */ +union npc_af_mcam_dbg { + u64 u; + struct npc_af_mcam_dbg_s { + u64 hit_entry : 10; + u64 reserved_10_11 : 2; + u64 hit_bank : 2; + u64 reserved_14_15 : 2; + u64 miss : 1; + u64 reserved_17_63 : 47; + } s; + /* struct npc_af_mcam_dbg_s cn; */ +}; + +static inline u64 NPC_AF_MCAM_DBG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_MCAM_DBG(void) +{ + return 0x3001000; +} + +/** + * Register (RVU_PF_BAR0) npc_af_mcam_scrub_ctl + * + * NPC AF MCAM Scrub Control Register + */ +union npc_af_mcam_scrub_ctl { + u64 u; + struct npc_af_mcam_scrub_ctl_s { + u64 ena : 1; + u64 reserved_1_7 : 7; + u64 lp_dis : 1; + u64 reserved_9_15 : 7; + u64 toth : 4; + u64 reserved_20_63 : 44; + } s; + /* struct npc_af_mcam_scrub_ctl_s cn; */ +}; + +static inline u64 NPC_AF_MCAM_SCRUB_CTL(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_MCAM_SCRUB_CTL(void) +{ + return 0xa0; +} + +/** + * Register (RVU_PF_BAR0) npc_af_mcame#_bank#_action + * + * NPC AF MCAM Entry Bank Action Data Registers Specifies a packet's + * match action captured in NPC_RESULT_S[ACTION]. When an interface is + * configured to use the NPC_MCAM_KEY_X2_S search key format + * (NPC_AF_INTF()_KEX_CFG[KEYW] = NPC_MCAMKEYW_E::X2), * + * NPC_AF_MCAME()_BANK(0)_ACTION/_TAG_ACT/_STAT_ACT are used if the + * search key matches NPC_AF_MCAME()_BANK(0..1)_CAM()_W*. * + * NPC_AF_MCAME()_BANK(2)_ACTION/_TAG_ACT/_STAT_ACT are used if the + * search key matches NPC_AF_MCAME()_BANK(2..3)_CAM()_W*. * + * NPC_AF_MCAME()_BANK(1,3)_ACTION/_TAG_ACT/_STAT_ACT are not used. When + * an interface is configured to use the NPC_MCAM_KEY_X4_S search key + * format (NPC_AF_INTF()_KEX_CFG[KEYW] = NPC_MCAMKEYW_E::X4): * + * NPC_AF_MCAME()_BANK(0)_ACTION/_TAG_ACT/_STAT_ACT are used if the + * search key matches NPC_AF_MCAME()_BANK(0..3)_CAM()_W*. * + * NPC_AF_MCAME()_BANK(1..3)_ACTION/_TAG_ACT/_STAT_ACT are not used. + */ +union npc_af_mcamex_bankx_action { + u64 u; + struct npc_af_mcamex_bankx_action_s { + u64 action : 64; + } s; + /* struct npc_af_mcamex_bankx_action_s cn; */ +}; + +static inline u64 NPC_AF_MCAMEX_BANKX_ACTION(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_MCAMEX_BANKX_ACTION(u64 a, u64 b) +{ + return 0x1900000 + 0x100 * a + 0x10 * b; +} + +/** + * Register (RVU_PF_BAR0) npc_af_mcame#_bank#_cam#_intf + * + * NPC AF MCAM Entry Bank CAM Data Interface Registers MCAM comparison + * ternary data interface word. The field values in + * NPC_AF_MCAME()_BANK()_CAM()_INTF, NPC_AF_MCAME()_BANK()_CAM()_W0 and + * NPC_AF_MCAME()_BANK()_CAM()_W1 are ternary, where each data bit of + * the search key matches as follows: _ [CAM(1)]\=0, [CAM(0)]\=0: + * Always match; search key data\ don't care. _ [CAM(1)]\=0, + * [CAM(0)]\=1: Match when search key data\ == 0. _ + * [CAM(1)]\=1, [CAM(0)]\=0: Match when search key data\ == + * 1. _ [CAM(1)]\=1, [CAM(0)]\=1: Reserved. The reserved + * combination is not allowed. Hardware suppresses any write to CAM(0) or + * CAM(1) that would result in the reserved combination for any CAM bit. + * The reset value for all non-reserved fields in + * NPC_AF_MCAME()_BANK()_CAM()_INTF, NPC_AF_MCAME()_BANK()_CAM()_W0 and + * NPC_AF_MCAME()_BANK()_CAM()_W1 is all zeros for CAM(1) and all ones + * for CAM(0), matching a search key of all zeros. When an interface is + * configured to use the NPC_MCAM_KEY_X1_S search key format + * (NPC_AF_INTF()_KEX_CFG[KEYW] = NPC_MCAMKEYW_E::X1), the four banks of + * every MCAM entry are used as individual entries, each of which is + * independently compared with the search key as follows: _ + * NPC_AF_MCAME()_BANK()_CAM()_INTF[INTF] corresponds to + * NPC_MCAM_KEY_X1_S[INTF]. _ NPC_AF_MCAME()_BANK()_CAM()_W0[MD] + * corresponds to NPC_MCAM_KEY_X1_S[KW0]. _ + * NPC_AF_MCAME()_BANK()_CAM()_W1[MD] corresponds to + * NPC_MCAM_KEY_X1_S[KW1]. When an interface is configured to use the + * NPC_MCAM_KEY_X2_S search key format (NPC_AF_INTF()_KEX_CFG[KEYW] = + * NPC_MCAMKEYW_E::X2), banks 0-1 of every MCAM entry are used as one + * double-wide entry, banks 2-3 as a second double-wide entry, and each + * double-wide entry is independently compared with the search key as + * follows: _ NPC_AF_MCAME()_BANK(0,2)_CAM()_INTF[INTF] corresponds to + * NPC_MCAM_KEY_X2_S[INTF]. _ NPC_AF_MCAME()_BANK(0,2)_CAM()_W0[MD] + * corresponds to NPC_MCAM_KEY_X2_S[KW0]. _ + * NPC_AF_MCAME()_BANK(0,2)_CAM()_W1[MD] corresponds to + * NPC_MCAM_KEY_X2_S[KW1]\<47:0\>. _ + * NPC_AF_MCAME()_BANK(1,3)_CAM()_INTF[INTF] corresponds to + * NPC_MCAM_KEY_X2_S[INTF]. _ + * NPC_AF_MCAME()_BANK(1,3)_CAM()_W0[MD]\<15:0\> corresponds to + * NPC_MCAM_KEY_X2_S[KW1]\<63:48\>. _ + * NPC_AF_MCAME()_BANK(1,3)_CAM()_W0[MD]\<63:16\> corresponds to + * NPC_MCAM_KEY_X2_S[KW2]\<47:0\>. _ + * NPC_AF_MCAME()_BANK(1,3)_CAM()_W1[MD]\<15:0\> corresponds to + * NPC_MCAM_KEY_X2_S[KW2]\<63:48\>. _ + * NPC_AF_MCAME()_BANK(1,3)_CAM()_W1[MD]\<47:16\> corresponds to + * NPC_MCAM_KEY_X2_S[KW3]\<31:0\>. When an interface is configured to + * use the NPC_MCAM_KEY_X4_S search key format + * (NPC_AF_INTF()_KEX_CFG[KEYW] = NPC_MCAMKEYW_E::X4), the four banks of + * every MCAM entry are used as a single quad-wide entry that is compared + * with the search key as follows: _ + * NPC_AF_MCAME()_BANK(0)_CAM()_INTF[INTF] corresponds to + * NPC_MCAM_KEY_X4_S[INTF]. _ NPC_AF_MCAME()_BANK(0)_CAM()_W0[MD] + * corresponds to NPC_MCAM_KEY_X4_S[KW0]. _ + * NPC_AF_MCAME()_BANK(0)_CAM()_W1[MD] corresponds to + * NPC_MCAM_KEY_X4_S[KW1]\<47:0\>. _ + * NPC_AF_MCAME()_BANK(1)_CAM()_INTF[INTF] corresponds to + * NPC_MCAM_KEY_X4_S[INTF]. _ NPC_AF_MCAME()_BANK(1)_CAM()_W0[MD]\<15:0\> + * corresponds to NPC_MCAM_KEY_X4_S[KW1]\<63:48\>. _ + * NPC_AF_MCAME()_BANK(1)_CAM()_W0[MD]\<63:16\> corresponds to + * NPC_MCAM_KEY_X4_S[KW2]\<47:0\>. _ + * NPC_AF_MCAME()_BANK(1)_CAM()_W1[MD]\<15:0\> corresponds to + * NPC_MCAM_KEY_X4_S[KW2]\<63:48\>. _ + * NPC_AF_MCAME()_BANK(1)_CAM()_W1[MD]\<47:16\> corresponds to + * NPC_MCAM_KEY_X4_S[KW3]\<31:0\>. _ + * NPC_AF_MCAME()_BANK(2)_CAM()_INTF[INTF] corresponds to + * NPC_MCAM_KEY_X4_S[INTF]. _ NPC_AF_MCAME()_BANK(2)_CAM()_W0[MD]\<31:0\> + * corresponds to NPC_MCAM_KEY_X4_S[KW3]\<63:32\>. _ + * NPC_AF_MCAME()_BANK(2)_CAM()_W0[MD]\<63:32\> corresponds to + * NPC_MCAM_KEY_X4_S[KW4]\<31:0\>. _ + * NPC_AF_MCAME()_BANK(2)_CAM()_W1[MD]\<31:0\> corresponds to + * NPC_MCAM_KEY_X4_S[KW4]\<63:32\>. _ + * NPC_AF_MCAME()_BANK(2)_CAM()_W1[MD]\<47:32\> corresponds to + * NPC_MCAM_KEY_X4_S[KW5]\<15:0\>. _ + * NPC_AF_MCAME()_BANK(3)_CAM()_INTF[INTF] corresponds to + * NPC_MCAM_KEY_X4_S[INTF]. _ NPC_AF_MCAME()_BANK(3)_CAM()_W0[MD]\<47:0\> + * corresponds to NPC_MCAM_KEY_X4_S[KW5]\<63:16\>. _ + * NPC_AF_MCAME()_BANK(3)_CAM()_W0[MD]\<63:48\> corresponds to + * NPC_MCAM_KEY_X4_S[KW6]\<15:0\>. _ NPC_AF_MCAME()_BANK(3)_CAM()_W1[MD] + * corresponds to NPC_MCAM_KEY_X4_S[KW6]\<63:16\>. Note that for the X2 + * and X4 formats, a wide entry will not match unless the INTF fields + * from the associated two or four banks match the INTF value from the + * search key. For the X1 and X2 formats, a match in a lower-numbered + * bank takes priority over a match in any higher numbered banks. Within + * each bank, the lowest numbered matching entry takes priority over any + * higher numbered entry. + */ +union npc_af_mcamex_bankx_camx_intf { + u64 u; + struct npc_af_mcamex_bankx_camx_intf_s { + u64 intf : 2; + u64 reserved_2_63 : 62; + } s; + /* struct npc_af_mcamex_bankx_camx_intf_s cn; */ +}; + +static inline u64 NPC_AF_MCAMEX_BANKX_CAMX_INTF(u64 a, u64 b, u64 c) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_MCAMEX_BANKX_CAMX_INTF(u64 a, u64 b, u64 c) +{ + return 0x1000000 + 0x400 * a + 0x40 * b + 8 * c; +} + +/** + * Register (RVU_PF_BAR0) npc_af_mcame#_bank#_cam#_w0 + * + * NPC AF MCAM Entry Bank CAM Data Word 0 Registers MCAM comparison + * ternary data word 0. See NPC_AF_MCAME()_BANK()_CAM()_INTF. + */ +union npc_af_mcamex_bankx_camx_w0 { + u64 u; + struct npc_af_mcamex_bankx_camx_w0_s { + u64 md : 64; + } s; + /* struct npc_af_mcamex_bankx_camx_w0_s cn; */ +}; + +static inline u64 NPC_AF_MCAMEX_BANKX_CAMX_W0(u64 a, u64 b, u64 c) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_MCAMEX_BANKX_CAMX_W0(u64 a, u64 b, u64 c) +{ + return 0x1000010 + 0x400 * a + 0x40 * b + 8 * c; +} + +/** + * Register (RVU_PF_BAR0) npc_af_mcame#_bank#_cam#_w1 + * + * NPC AF MCAM Entry Bank Data Word 1 Registers MCAM comparison ternary + * data word 1. See NPC_AF_MCAME()_BANK()_CAM()_INTF. + */ +union npc_af_mcamex_bankx_camx_w1 { + u64 u; + struct npc_af_mcamex_bankx_camx_w1_s { + u64 md : 48; + u64 reserved_48_63 : 16; + } s; + /* struct npc_af_mcamex_bankx_camx_w1_s cn; */ +}; + +static inline u64 NPC_AF_MCAMEX_BANKX_CAMX_W1(u64 a, u64 b, u64 c) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_MCAMEX_BANKX_CAMX_W1(u64 a, u64 b, u64 c) +{ + return 0x1000020 + 0x400 * a + 0x40 * b + 8 * c; +} + +/** + * Register (RVU_PF_BAR0) npc_af_mcame#_bank#_cfg + * + * NPC AF MCAM Entry Bank Configuration Registers + */ +union npc_af_mcamex_bankx_cfg { + u64 u; + struct npc_af_mcamex_bankx_cfg_s { + u64 ena : 1; + u64 reserved_1_63 : 63; + } s; + /* struct npc_af_mcamex_bankx_cfg_s cn; */ +}; + +static inline u64 NPC_AF_MCAMEX_BANKX_CFG(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_MCAMEX_BANKX_CFG(u64 a, u64 b) +{ + return 0x1800000 + 0x100 * a + 0x10 * b; +} + +/** + * Register (RVU_PF_BAR0) npc_af_mcame#_bank#_stat_act + * + * NPC AF MCAM Entry Bank Statistics Action Registers Used to optionally + * increment a NPC_AF_MATCH_STAT() counter when a packet matches an MCAM + * entry. See also NPC_AF_MCAME()_BANK()_ACTION. + */ +union npc_af_mcamex_bankx_stat_act { + u64 u; + struct npc_af_mcamex_bankx_stat_act_s { + u64 stat_sel : 9; + u64 ena : 1; + u64 reserved_10_63 : 54; + } s; + /* struct npc_af_mcamex_bankx_stat_act_s cn; */ +}; + +static inline u64 NPC_AF_MCAMEX_BANKX_STAT_ACT(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_MCAMEX_BANKX_STAT_ACT(u64 a, u64 b) +{ + return 0x1880000 + 0x100 * a + 0x10 * b; +} + +/** + * Register (RVU_PF_BAR0) npc_af_mcame#_bank#_tag_act + * + * NPC AF MCAM Entry Bank VTag Action Data Registers Specifies a packet's + * match Vtag action captured in NPC_RESULT_S[VTAG_ACTION]. See also + * NPC_AF_MCAME()_BANK()_ACTION. + */ +union npc_af_mcamex_bankx_tag_act { + u64 u; + struct npc_af_mcamex_bankx_tag_act_s { + u64 vtag_action : 64; + } s; + /* struct npc_af_mcamex_bankx_tag_act_s cn; */ +}; + +static inline u64 NPC_AF_MCAMEX_BANKX_TAG_ACT(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_MCAMEX_BANKX_TAG_ACT(u64 a, u64 b) +{ + return 0x1900008 + 0x100 * a + 0x10 * b; +} + +/** + * Register (RVU_PF_BAR0) npc_af_pck_cfg + * + * NPC AF Protocol Check Configuration Register + */ +union npc_af_pck_cfg { + u64 u; + struct npc_af_pck_cfg_s { + u64 reserved_0 : 1; + u64 iip4_cksum : 1; + u64 oip4_cksum : 1; + u64 reserved_3 : 1; + u64 l3b : 1; + u64 l3m : 1; + u64 l2b : 1; + u64 l2m : 1; + u64 reserved_8_23 : 16; + u64 iip4_cksum_errcode : 8; + u64 oip4_cksum_errcode : 8; + u64 reserved_40_63 : 24; + } s; + /* struct npc_af_pck_cfg_s cn; */ +}; + +static inline u64 NPC_AF_PCK_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_PCK_CFG(void) +{ + return 0x600; +} + +/** + * Register (RVU_PF_BAR0) npc_af_pck_def_iip4 + * + * NPC AF Protocol Check Inner IPv4 Definition Register Provides layer + * information used by the protocol checker to identify an inner IPv4 + * header. + */ +union npc_af_pck_def_iip4 { + u64 u; + struct npc_af_pck_def_iip4_s { + u64 ltype_mask : 4; + u64 ltype_match : 4; + u64 lid : 3; + u64 reserved_11_63 : 53; + } s; + /* struct npc_af_pck_def_iip4_s cn; */ +}; + +static inline u64 NPC_AF_PCK_DEF_IIP4(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_PCK_DEF_IIP4(void) +{ + return 0x640; +} + +/** + * Register (RVU_PF_BAR0) npc_af_pck_def_oip4 + * + * NPC AF Protocol Check Outer IPv4 Definition Register Provides layer + * information used by the protocol checker to identify an outer IPv4 + * header. + */ +union npc_af_pck_def_oip4 { + u64 u; + struct npc_af_pck_def_oip4_s { + u64 ltype_mask : 4; + u64 ltype_match : 4; + u64 lid : 3; + u64 reserved_11_63 : 53; + } s; + /* struct npc_af_pck_def_oip4_s cn; */ +}; + +static inline u64 NPC_AF_PCK_DEF_OIP4(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_PCK_DEF_OIP4(void) +{ + return 0x620; +} + +/** + * Register (RVU_PF_BAR0) npc_af_pck_def_oip6 + * + * NPC AF Protocol Check Outer IPv6 Definition Register Provides layer + * information used by the protocol checker to identify an outer IPv6 + * header. [LID] must have the same value as NPC_AF_PCK_DEF_OIP4[LID]. + */ +union npc_af_pck_def_oip6 { + u64 u; + struct npc_af_pck_def_oip6_s { + u64 ltype_mask : 4; + u64 ltype_match : 4; + u64 lid : 3; + u64 reserved_11_63 : 53; + } s; + /* struct npc_af_pck_def_oip6_s cn; */ +}; + +static inline u64 NPC_AF_PCK_DEF_OIP6(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_PCK_DEF_OIP6(void) +{ + return 0x630; +} + +/** + * Register (RVU_PF_BAR0) npc_af_pck_def_ol2 + * + * NPC AF Protocol Check Outer L2 Definition Register Provides layer + * information used by the protocol checker to identify an outer L2 + * header. + */ +union npc_af_pck_def_ol2 { + u64 u; + struct npc_af_pck_def_ol2_s { + u64 ltype_mask : 4; + u64 ltype_match : 4; + u64 lid : 3; + u64 reserved_11_63 : 53; + } s; + /* struct npc_af_pck_def_ol2_s cn; */ +}; + +static inline u64 NPC_AF_PCK_DEF_OL2(void) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_PCK_DEF_OL2(void) +{ + return 0x610; +} + +/** + * Register (RVU_PF_BAR0) npc_af_pkind#_action0 + * + * NPC AF Port Kind Action Data 0 Registers NPC_AF_PKIND()_ACTION0 and + * NPC_AF_PKIND()_ACTION1 specify the initial parse state and operations + * to perform before entering KPU 0. + */ +union npc_af_pkindx_action0 { + u64 u; + struct npc_af_pkindx_action0_s { + u64 var_len_shift : 3; + u64 var_len_right : 1; + u64 var_len_mask : 8; + u64 var_len_offset : 8; + u64 ptr_advance : 8; + u64 capture_flags : 8; + u64 capture_ltype : 4; + u64 capture_lid : 3; + u64 reserved_43 : 1; + u64 next_state : 8; + u64 parse_done : 1; + u64 capture_ena : 1; + u64 byp_count : 3; + u64 reserved_57_63 : 7; + } s; + /* struct npc_af_pkindx_action0_s cn; */ +}; + +static inline u64 NPC_AF_PKINDX_ACTION0(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_PKINDX_ACTION0(u64 a) +{ + return 0x80000 + 0x40 * a; +} + +/** + * Register (RVU_PF_BAR0) npc_af_pkind#_action1 + * + * NPC AF Port Kind Action Data 1 Registers NPC_AF_PKIND()_ACTION0 and + * NPC_AF_PKIND()_ACTION1 specify the initial parse state and operations + * to perform before entering KPU 0. + */ +union npc_af_pkindx_action1 { + u64 u; + struct npc_af_pkindx_action1_s { + u64 dp0_offset : 8; + u64 dp1_offset : 8; + u64 dp2_offset : 8; + u64 errcode : 8; + u64 errlev : 4; + u64 reserved_36_63 : 28; + } s; + /* struct npc_af_pkindx_action1_s cn; */ +}; + +static inline u64 NPC_AF_PKINDX_ACTION1(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_PKINDX_ACTION1(u64 a) +{ + return 0x80008 + 0x40 * a; +} + +/** + * Register (RVU_PF_BAR0) npc_af_pkind#_cpi_def# + * + * NPC AF Port Kind Channel Parse Index Definition Registers These + * registers specify the layer information and algorithm to compute a + * packet's channel parse index (CPI), which provides a port to channel + * adder for calculating NPC_RESULT_S[CHAN]. There are two CPI + * definitions per port kind, allowing the CPI computation to use two + * possible layer definitions in the parsed packet, e.g. DiffServ DSCP + * from either IPv4 or IPv6 header. CPI pseudocode: \ for (i = 0; + * i \< 2; i++) { cpi_def = NPC_AF_PKIND()_CPI_DEF(i); LX = LA, LB, + * ..., or LH as selected by cpi_def[LID]; if (cpi_def[ENA] && + * ((cpi_def[LTYPE_MATCH] & cpi_def[LTYPE_MASK]) == + * (NPC_RESULT_S[LX[LTYPE]] & cpi_def[LTYPE_MASK])) && + * ((cpi_def[FLAGS_MATCH] & cpi_def[FLAGS_MASK]) == + * (NPC_RESULT_S[LX[FLAGS]] & cpi_def[FLAGS_MASK]))) { // Found + * matching layer nibble_offset = (2*NPC_RESULT_S[LX[LPTR]]) + + * cpi_def[ADD_OFFSET]; add_byte = byte at nibble_offset from start + * of packet; cpi_add = (add_byte & cpi_def[ADD_MASK]) \>\> + * cpi_def[ADD_SHIFT]; cpi = cpi_def[CPI_BASE] + cpi_add; + * NPC_RESULT_S[CHAN] += NPC_AF_CPI(cpi)_CFG[PADD]; break; } } + * \ + */ +union npc_af_pkindx_cpi_defx { + u64 u; + struct npc_af_pkindx_cpi_defx_s { + u64 cpi_base : 10; + u64 reserved_10_11 : 2; + u64 add_shift : 3; + u64 reserved_15 : 1; + u64 add_mask : 8; + u64 add_offset : 8; + u64 flags_mask : 8; + u64 flags_match : 8; + u64 ltype_mask : 4; + u64 ltype_match : 4; + u64 lid : 3; + u64 reserved_59_62 : 4; + u64 ena : 1; + } s; + /* struct npc_af_pkindx_cpi_defx_s cn; */ +}; + +static inline u64 NPC_AF_PKINDX_CPI_DEFX(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 NPC_AF_PKINDX_CPI_DEFX(u64 a, u64 b) +{ + return 0x80020 + 0x40 * a + 8 * b; +} + +#endif /* __CSRS_NPC_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-rvu.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-rvu.h new file mode 100644 index 000000000..f4e0de602 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/csrs-rvu.h @@ -0,0 +1,2276 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Marvell International Ltd. + * + * https://spdx.org/licenses + */ +#ifndef __CSRS_RVU_H__ +#define __CSRS_RVU_H__ + +/** + * @file + * + * Configuration and status register (CSR) address and type definitions for + * RVU. + * + * This file is auto generated. Do not edit. + * + */ + +/** + * Enumeration rvu_af_int_vec_e + * + * RVU Admin Function Interrupt Vector Enumeration Enumerates the MSI-X + * interrupt vectors. Internal: RVU maintains the state of these vectors + * internally, and generates GIB messages for it without accessing the + * MSI-X table region in LLC/DRAM. + */ +#define RVU_AF_INT_VEC_E_GEN (3) +#define RVU_AF_INT_VEC_E_MBOX (4) +#define RVU_AF_INT_VEC_E_PFFLR (1) +#define RVU_AF_INT_VEC_E_PFME (2) +#define RVU_AF_INT_VEC_E_POISON (0) + +/** + * Enumeration rvu_bar_e + * + * RVU Base Address Register Enumeration Enumerates the base address + * registers. Internal: For documentation only. + */ +#define RVU_BAR_E_RVU_PFX_BAR0(a) (0x840000000000ll + 0x1000000000ll * (a)) +#define RVU_BAR_E_RVU_PFX_BAR0_SIZE 0x10000000ull +#define RVU_BAR_E_RVU_PFX_FUNCX_BAR2(a, b) \ + (0x840200000000ll + 0x1000000000ll * (a) + 0x2000000ll * (b)) +#define RVU_BAR_E_RVU_PFX_FUNCX_BAR2_SIZE 0x100000ull +#define RVU_BAR_E_RVU_PFX_FUNCX_BAR4(a, b) \ + (0x840400000000ll + 0x1000000000ll * (a) + 0x2000000ll * (b)) +#define RVU_BAR_E_RVU_PFX_FUNCX_BAR4_SIZE 0x10000ull + +/** + * Enumeration rvu_block_addr_e + * + * RVU Block Address Enumeration Enumerates addressing of RVU resource + * blocks within each RVU BAR, i.e. values of RVU_FUNC_ADDR_S[BLOCK] and + * RVU_AF_ADDR_S[BLOCK]. CNXXXX may not implement all enumerated blocks. + * Software can read RVU_PF/RVU_VF_BLOCK_ADDR()_DISC[IMP] to discover + * which blocks are implemented and enabled. + */ +#define RVU_BLOCK_ADDR_E_CPTX(a) (0xa + (a)) +#define RVU_BLOCK_ADDR_E_LMT (1) +#define RVU_BLOCK_ADDR_E_NDCX(a) (0xc + (a)) +#define RVU_BLOCK_ADDR_E_NIXX(a) (4 + (a)) +#define RVU_BLOCK_ADDR_E_NPA (3) +#define RVU_BLOCK_ADDR_E_NPC (6) +#define RVU_BLOCK_ADDR_E_RX(a) (0 + (a)) +#define RVU_BLOCK_ADDR_E_REEX(a) (0x14 + (a)) +#define RVU_BLOCK_ADDR_E_RVUM (0) +#define RVU_BLOCK_ADDR_E_SSO (7) +#define RVU_BLOCK_ADDR_E_SSOW (8) +#define RVU_BLOCK_ADDR_E_TIM (9) + +/** + * Enumeration rvu_block_type_e + * + * RVU Block Type Enumeration Enumerates values of + * RVU_PF/RVU_VF_BLOCK_ADDR()_DISC[BTYPE]. + */ +#define RVU_BLOCK_TYPE_E_CPT (9) +#define RVU_BLOCK_TYPE_E_DDF (0xb) +#define RVU_BLOCK_TYPE_E_LMT (2) +#define RVU_BLOCK_TYPE_E_NDC (0xa) +#define RVU_BLOCK_TYPE_E_NIX (3) +#define RVU_BLOCK_TYPE_E_NPA (4) +#define RVU_BLOCK_TYPE_E_NPC (5) +#define RVU_BLOCK_TYPE_E_RAD (0xd) +#define RVU_BLOCK_TYPE_E_REE (0xe) +#define RVU_BLOCK_TYPE_E_RVUM (0) +#define RVU_BLOCK_TYPE_E_SSO (6) +#define RVU_BLOCK_TYPE_E_SSOW (7) +#define RVU_BLOCK_TYPE_E_TIM (8) +#define RVU_BLOCK_TYPE_E_ZIP (0xc) + +/** + * Enumeration rvu_bus_lf_e + * + * INTERNAL: RVU Bus LF Range Enumeration Enumerates the LF range for + * the RVU bus. Internal: This is an enum used in csr3 virtual equations. + */ +#define RVU_BUS_LF_E_RVU_BUS_LFX(a) (0 + 0x2000000 * (a)) + +/** + * Enumeration rvu_bus_lf_slot_e + * + * INTERNAL: RVU Bus LF Slot Range Enumeration Enumerates the LF and + * Slot range for the RVU bus. Internal: This is an enum used in csr3 + * virtual equations. + */ +#define RVU_BUS_LF_SLOT_E_RVU_BUS_LFX_SLOTX(a, b) \ + (0 + 0x2000000 * (a) + 0x1000 * (b)) + +/** + * Enumeration rvu_bus_pf_e + * + * INTERNAL: RVU Bus PF Range Enumeration Enumerates the PF range for + * the RVU bus. Internal: This is an enum used in csr3 virtual equations. + */ +#define RVU_BUS_PF_E_RVU_BUS_PFX(a) (0ll + 0x1000000000ll * (a)) + +/** + * Enumeration rvu_bus_pfvf_e + * + * INTERNAL: RVU Bus PFVF Range Enumeration Enumerates the PF and VF + * ranges for the RVU bus. Internal: This is an enum used in csr3 virtual + * equations. + */ +#define RVU_BUS_PFVF_E_RVU_BUS_PFX(a) (0 + 0x2000000 * (a)) +#define RVU_BUS_PFVF_E_RVU_BUS_VFX(a) (0 + 0x2000000 * (a)) + +/** + * Enumeration rvu_busbar_e + * + * INTERNAL: RVU Bus Base Address Region Enumeration Enumerates the base + * address region for the RVU bus. Internal: This is an enum used in csr3 + * virtual equations. + */ +#define RVU_BUSBAR_E_RVU_BUSBAR0 (0) +#define RVU_BUSBAR_E_RVU_BUSBAR2 (0x200000000ll) + +/** + * Enumeration rvu_busdid_e + * + * INTERNAL: RVU Bus DID Enumeration Enumerates the DID offset for the + * RVU bus. Internal: This is an enum used in csr3 virtual equations. + */ +#define RVU_BUSDID_E_RVU_BUSDID (0x840000000000ll) + +/** + * Enumeration rvu_pf_int_vec_e + * + * RVU PF Interrupt Vector Enumeration Enumerates the MSI-X interrupt + * vectors. + */ +#define RVU_PF_INT_VEC_E_AFPF_MBOX (6) +#define RVU_PF_INT_VEC_E_VFFLRX(a) (0 + (a)) +#define RVU_PF_INT_VEC_E_VFMEX(a) (2 + (a)) +#define RVU_PF_INT_VEC_E_VFPF_MBOXX(a) (4 + (a)) + +/** + * Enumeration rvu_vf_int_vec_e + * + * RVU VF Interrupt Vector Enumeration Enumerates the MSI-X interrupt + * vectors. + */ +#define RVU_VF_INT_VEC_E_MBOX (0) + +/** + * Structure rvu_af_addr_s + * + * RVU Admin Function Register Address Structure Address format for + * accessing shared Admin Function (AF) registers in RVU PF BAR0. These + * registers may be accessed by all RVU PFs whose + * RVU_PRIV_PF()_CFG[AF_ENA] bit is set. + */ +union rvu_af_addr_s { + u64 u; + struct rvu_af_addr_s_s { + u64 addr : 28; + u64 block : 5; + u64 reserved_33_63 : 31; + } s; + /* struct rvu_af_addr_s_s cn; */ +}; + +/** + * Structure rvu_func_addr_s + * + * RVU Function-unique Address Structure Address format for accessing + * function-unique registers in RVU PF/FUNC BAR2. + */ +union rvu_func_addr_s { + u32 u; + struct rvu_func_addr_s_s { + u32 addr : 12; + u32 lf_slot : 8; + u32 block : 5; + u32 reserved_25_31 : 7; + } s; + /* struct rvu_func_addr_s_s cn; */ +}; + +/** + * Structure rvu_msix_vec_s + * + * RVU MSI-X Vector Structure Format of entries in the RVU MSI-X table + * region in LLC/DRAM. See RVU_PRIV_PF()_MSIX_CFG. + */ +union rvu_msix_vec_s { + u64 u[2]; + struct rvu_msix_vec_s_s { + u64 addr : 64; + u64 data : 32; + u64 mask : 1; + u64 pend : 1; + u64 reserved_98_127 : 30; + } s; + /* struct rvu_msix_vec_s_s cn; */ +}; + +/** + * Structure rvu_pf_func_s + * + * RVU PF Function Identification Structure Identifies an RVU PF/VF, and + * format of *_PRIV_LF()_CFG[PF_FUNC] in RVU resource blocks, e.g. + * NPA_PRIV_LF()_CFG[PF_FUNC]. Internal: Also used for PF/VF + * identification on inter-coprocessor hardware interfaces (NPA, SSO, + * CPT, ...). + */ +union rvu_pf_func_s { + u32 u; + struct rvu_pf_func_s_s { + u32 func : 10; + u32 pf : 6; + u32 reserved_16_31 : 16; + } s; + /* struct rvu_pf_func_s_s cn; */ +}; + +/** + * Register (RVU_PF_BAR0) rvu_af_afpf#_mbox# + * + * RVU Admin Function AF/PF Mailbox Registers + */ +union rvu_af_afpfx_mboxx { + u64 u; + struct rvu_af_afpfx_mboxx_s { + u64 data : 64; + } s; + /* struct rvu_af_afpfx_mboxx_s cn; */ +}; + +static inline u64 RVU_AF_AFPFX_MBOXX(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_AFPFX_MBOXX(u64 a, u64 b) +{ + return 0x2000 + 0x10 * a + 8 * b; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_bar2_alias# + * + * INTERNAL: RVU Admin Function BAR2 Alias Registers These registers + * alias to the RVU BAR2 registers for the PF and function selected by + * RVU_AF_BAR2_SEL[PF_FUNC]. Internal: Not implemented. Placeholder for + * bug33464. + */ +union rvu_af_bar2_aliasx { + u64 u; + struct rvu_af_bar2_aliasx_s { + u64 data : 64; + } s; + /* struct rvu_af_bar2_aliasx_s cn; */ +}; + +static inline u64 RVU_AF_BAR2_ALIASX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_BAR2_ALIASX(u64 a) +{ + return 0x9100000 + 8 * a; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_bar2_sel + * + * INTERNAL: RVU Admin Function BAR2 Select Register This register + * configures BAR2 accesses from the RVU_AF_BAR2_ALIAS() registers in + * BAR0. Internal: Not implemented. Placeholder for bug33464. + */ +union rvu_af_bar2_sel { + u64 u; + struct rvu_af_bar2_sel_s { + u64 alias_pf_func : 16; + u64 alias_ena : 1; + u64 reserved_17_63 : 47; + } s; + /* struct rvu_af_bar2_sel_s cn; */ +}; + +static inline u64 RVU_AF_BAR2_SEL(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_BAR2_SEL(void) +{ + return 0x9000000; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_blk_rst + * + * RVU Master Admin Function Block Reset Register + */ +union rvu_af_blk_rst { + u64 u; + struct rvu_af_blk_rst_s { + u64 rst : 1; + u64 reserved_1_62 : 62; + u64 busy : 1; + } s; + /* struct rvu_af_blk_rst_s cn; */ +}; + +static inline u64 RVU_AF_BLK_RST(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_BLK_RST(void) +{ + return 0x30; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_bp_test + * + * INTERNAL: RVUM Backpressure Test Registers + */ +union rvu_af_bp_test { + u64 u; + struct rvu_af_bp_test_s { + u64 lfsr_freq : 12; + u64 reserved_12_15 : 4; + u64 bp_cfg : 16; + u64 enable : 8; + u64 reserved_40_63 : 24; + } s; + /* struct rvu_af_bp_test_s cn; */ +}; + +static inline u64 RVU_AF_BP_TEST(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_BP_TEST(void) +{ + return 0x4000; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_eco + * + * INTERNAL: RVU Admin Function ECO Register + */ +union rvu_af_eco { + u64 u; + struct rvu_af_eco_s { + u64 eco_rw : 32; + u64 reserved_32_63 : 32; + } s; + /* struct rvu_af_eco_s cn; */ +}; + +static inline u64 RVU_AF_ECO(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_ECO(void) +{ + return 0x20; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_gen_int + * + * RVU Admin Function General Interrupt Register This register contains + * General interrupt summary bits. + */ +union rvu_af_gen_int { + u64 u; + struct rvu_af_gen_int_s { + u64 unmapped : 1; + u64 msix_fault : 1; + u64 reserved_2_63 : 62; + } s; + /* struct rvu_af_gen_int_s cn; */ +}; + +static inline u64 RVU_AF_GEN_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_GEN_INT(void) +{ + return 0x120; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_gen_int_ena_w1c + * + * RVU Admin Function General Interrupt Enable Clear Register This + * register clears interrupt enable bits. + */ +union rvu_af_gen_int_ena_w1c { + u64 u; + struct rvu_af_gen_int_ena_w1c_s { + u64 unmapped : 1; + u64 msix_fault : 1; + u64 reserved_2_63 : 62; + } s; + /* struct rvu_af_gen_int_ena_w1c_s cn; */ +}; + +static inline u64 RVU_AF_GEN_INT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_GEN_INT_ENA_W1C(void) +{ + return 0x138; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_gen_int_ena_w1s + * + * RVU Admin Function General Interrupt Enable Set Register This register + * sets interrupt enable bits. + */ +union rvu_af_gen_int_ena_w1s { + u64 u; + struct rvu_af_gen_int_ena_w1s_s { + u64 unmapped : 1; + u64 msix_fault : 1; + u64 reserved_2_63 : 62; + } s; + /* struct rvu_af_gen_int_ena_w1s_s cn; */ +}; + +static inline u64 RVU_AF_GEN_INT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_GEN_INT_ENA_W1S(void) +{ + return 0x130; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_gen_int_w1s + * + * RVU Admin Function General Interrupt Set Register This register sets + * interrupt bits. + */ +union rvu_af_gen_int_w1s { + u64 u; + struct rvu_af_gen_int_w1s_s { + u64 unmapped : 1; + u64 msix_fault : 1; + u64 reserved_2_63 : 62; + } s; + /* struct rvu_af_gen_int_w1s_s cn; */ +}; + +static inline u64 RVU_AF_GEN_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_GEN_INT_W1S(void) +{ + return 0x128; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_hwvf_rst + * + * RVU Admin Function Hardware VF Reset Register + */ +union rvu_af_hwvf_rst { + u64 u; + struct rvu_af_hwvf_rst_s { + u64 hwvf : 8; + u64 reserved_8_11 : 4; + u64 exec : 1; + u64 reserved_13_63 : 51; + } s; + /* struct rvu_af_hwvf_rst_s cn; */ +}; + +static inline u64 RVU_AF_HWVF_RST(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_HWVF_RST(void) +{ + return 0x2850; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_msixtr_base + * + * RVU Admin Function MSI-X Table Region Base-Address Register + */ +union rvu_af_msixtr_base { + u64 u; + struct rvu_af_msixtr_base_s { + u64 reserved_0_6 : 7; + u64 addr : 46; + u64 reserved_53_63 : 11; + } s; + /* struct rvu_af_msixtr_base_s cn; */ +}; + +static inline u64 RVU_AF_MSIXTR_BASE(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_MSIXTR_BASE(void) +{ + return 0x10; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_pf#_vf_bar4_addr + * + * RVU Admin Function PF/VF BAR4 Address Registers + */ +union rvu_af_pfx_vf_bar4_addr { + u64 u; + struct rvu_af_pfx_vf_bar4_addr_s { + u64 reserved_0_15 : 16; + u64 addr : 48; + } s; + /* struct rvu_af_pfx_vf_bar4_addr_s cn; */ +}; + +static inline u64 RVU_AF_PFX_VF_BAR4_ADDR(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_PFX_VF_BAR4_ADDR(u64 a) +{ + return 0x1000 + 0x10 * a; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_pf_bar4_addr + * + * RVU Admin Function PF BAR4 Address Registers + */ +union rvu_af_pf_bar4_addr { + u64 u; + struct rvu_af_pf_bar4_addr_s { + u64 reserved_0_15 : 16; + u64 addr : 48; + } s; + /* struct rvu_af_pf_bar4_addr_s cn; */ +}; + +static inline u64 RVU_AF_PF_BAR4_ADDR(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_PF_BAR4_ADDR(void) +{ + return 0x40; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_pf_rst + * + * RVU Admin Function PF Reset Register + */ +union rvu_af_pf_rst { + u64 u; + struct rvu_af_pf_rst_s { + u64 pf : 4; + u64 reserved_4_11 : 8; + u64 exec : 1; + u64 reserved_13_63 : 51; + } s; + /* struct rvu_af_pf_rst_s cn; */ +}; + +static inline u64 RVU_AF_PF_RST(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_PF_RST(void) +{ + return 0x2840; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_pfaf_mbox_int + * + * RVU Admin Function PF to AF Mailbox Interrupt Registers + */ +union rvu_af_pfaf_mbox_int { + u64 u; + struct rvu_af_pfaf_mbox_int_s { + u64 mbox : 16; + u64 reserved_16_63 : 48; + } s; + /* struct rvu_af_pfaf_mbox_int_s cn; */ +}; + +static inline u64 RVU_AF_PFAF_MBOX_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_PFAF_MBOX_INT(void) +{ + return 0x2880; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_pfaf_mbox_int_ena_w1c + * + * RVU Admin Function PF to AF Mailbox Interrupt Enable Clear Registers + * This register clears interrupt enable bits. + */ +union rvu_af_pfaf_mbox_int_ena_w1c { + u64 u; + struct rvu_af_pfaf_mbox_int_ena_w1c_s { + u64 mbox : 16; + u64 reserved_16_63 : 48; + } s; + /* struct rvu_af_pfaf_mbox_int_ena_w1c_s cn; */ +}; + +static inline u64 RVU_AF_PFAF_MBOX_INT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_PFAF_MBOX_INT_ENA_W1C(void) +{ + return 0x2898; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_pfaf_mbox_int_ena_w1s + * + * RVU Admin Function PF to AF Mailbox Interrupt Enable Set Registers + * This register sets interrupt enable bits. + */ +union rvu_af_pfaf_mbox_int_ena_w1s { + u64 u; + struct rvu_af_pfaf_mbox_int_ena_w1s_s { + u64 mbox : 16; + u64 reserved_16_63 : 48; + } s; + /* struct rvu_af_pfaf_mbox_int_ena_w1s_s cn; */ +}; + +static inline u64 RVU_AF_PFAF_MBOX_INT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_PFAF_MBOX_INT_ENA_W1S(void) +{ + return 0x2890; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_pfaf_mbox_int_w1s + * + * RVU Admin Function PF to AF Mailbox Interrupt Set Registers This + * register sets interrupt bits. + */ +union rvu_af_pfaf_mbox_int_w1s { + u64 u; + struct rvu_af_pfaf_mbox_int_w1s_s { + u64 mbox : 16; + u64 reserved_16_63 : 48; + } s; + /* struct rvu_af_pfaf_mbox_int_w1s_s cn; */ +}; + +static inline u64 RVU_AF_PFAF_MBOX_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_PFAF_MBOX_INT_W1S(void) +{ + return 0x2888; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_pfflr_int + * + * RVU Admin Function PF Function Level Reset Interrupt Registers + */ +union rvu_af_pfflr_int { + u64 u; + struct rvu_af_pfflr_int_s { + u64 flr : 16; + u64 reserved_16_63 : 48; + } s; + /* struct rvu_af_pfflr_int_s cn; */ +}; + +static inline u64 RVU_AF_PFFLR_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_PFFLR_INT(void) +{ + return 0x28a0; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_pfflr_int_ena_w1c + * + * RVU Admin Function PF Function Level Reset Interrupt Enable Clear + * Registers This register clears interrupt enable bits. + */ +union rvu_af_pfflr_int_ena_w1c { + u64 u; + struct rvu_af_pfflr_int_ena_w1c_s { + u64 flr : 16; + u64 reserved_16_63 : 48; + } s; + /* struct rvu_af_pfflr_int_ena_w1c_s cn; */ +}; + +static inline u64 RVU_AF_PFFLR_INT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_PFFLR_INT_ENA_W1C(void) +{ + return 0x28b8; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_pfflr_int_ena_w1s + * + * RVU Admin Function PF Function Level Reset Interrupt Enable Set + * Registers This register sets interrupt enable bits. + */ +union rvu_af_pfflr_int_ena_w1s { + u64 u; + struct rvu_af_pfflr_int_ena_w1s_s { + u64 flr : 16; + u64 reserved_16_63 : 48; + } s; + /* struct rvu_af_pfflr_int_ena_w1s_s cn; */ +}; + +static inline u64 RVU_AF_PFFLR_INT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_PFFLR_INT_ENA_W1S(void) +{ + return 0x28b0; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_pfflr_int_w1s + * + * RVU Admin Function PF Function Level Reset Interrupt Set Registers + * This register sets interrupt bits. + */ +union rvu_af_pfflr_int_w1s { + u64 u; + struct rvu_af_pfflr_int_w1s_s { + u64 flr : 16; + u64 reserved_16_63 : 48; + } s; + /* struct rvu_af_pfflr_int_w1s_s cn; */ +}; + +static inline u64 RVU_AF_PFFLR_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_PFFLR_INT_W1S(void) +{ + return 0x28a8; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_pfme_int + * + * RVU Admin Function PF Bus Master Enable Interrupt Registers + */ +union rvu_af_pfme_int { + u64 u; + struct rvu_af_pfme_int_s { + u64 me : 16; + u64 reserved_16_63 : 48; + } s; + /* struct rvu_af_pfme_int_s cn; */ +}; + +static inline u64 RVU_AF_PFME_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_PFME_INT(void) +{ + return 0x28c0; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_pfme_int_ena_w1c + * + * RVU Admin Function PF Bus Master Enable Interrupt Enable Clear + * Registers This register clears interrupt enable bits. + */ +union rvu_af_pfme_int_ena_w1c { + u64 u; + struct rvu_af_pfme_int_ena_w1c_s { + u64 me : 16; + u64 reserved_16_63 : 48; + } s; + /* struct rvu_af_pfme_int_ena_w1c_s cn; */ +}; + +static inline u64 RVU_AF_PFME_INT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_PFME_INT_ENA_W1C(void) +{ + return 0x28d8; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_pfme_int_ena_w1s + * + * RVU Admin Function PF Bus Master Enable Interrupt Enable Set Registers + * This register sets interrupt enable bits. + */ +union rvu_af_pfme_int_ena_w1s { + u64 u; + struct rvu_af_pfme_int_ena_w1s_s { + u64 me : 16; + u64 reserved_16_63 : 48; + } s; + /* struct rvu_af_pfme_int_ena_w1s_s cn; */ +}; + +static inline u64 RVU_AF_PFME_INT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_PFME_INT_ENA_W1S(void) +{ + return 0x28d0; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_pfme_int_w1s + * + * RVU Admin Function PF Bus Master Enable Interrupt Set Registers This + * register sets interrupt bits. + */ +union rvu_af_pfme_int_w1s { + u64 u; + struct rvu_af_pfme_int_w1s_s { + u64 me : 16; + u64 reserved_16_63 : 48; + } s; + /* struct rvu_af_pfme_int_w1s_s cn; */ +}; + +static inline u64 RVU_AF_PFME_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_PFME_INT_W1S(void) +{ + return 0x28c8; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_pfme_status + * + * RVU Admin Function PF Bus Master Enable Status Registers + */ +union rvu_af_pfme_status { + u64 u; + struct rvu_af_pfme_status_s { + u64 me : 16; + u64 reserved_16_63 : 48; + } s; + /* struct rvu_af_pfme_status_s cn; */ +}; + +static inline u64 RVU_AF_PFME_STATUS(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_PFME_STATUS(void) +{ + return 0x2800; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_pftrpend + * + * RVU Admin Function PF Transaction Pending Registers + */ +union rvu_af_pftrpend { + u64 u; + struct rvu_af_pftrpend_s { + u64 trpend : 16; + u64 reserved_16_63 : 48; + } s; + /* struct rvu_af_pftrpend_s cn; */ +}; + +static inline u64 RVU_AF_PFTRPEND(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_PFTRPEND(void) +{ + return 0x2810; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_pftrpend_w1s + * + * RVU Admin Function PF Transaction Pending Set Registers This register + * reads or sets bits. + */ +union rvu_af_pftrpend_w1s { + u64 u; + struct rvu_af_pftrpend_w1s_s { + u64 trpend : 16; + u64 reserved_16_63 : 48; + } s; + /* struct rvu_af_pftrpend_w1s_s cn; */ +}; + +static inline u64 RVU_AF_PFTRPEND_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_PFTRPEND_W1S(void) +{ + return 0x2820; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_ras + * + * RVU Admin Function RAS Interrupt Register This register is intended + * for delivery of RAS events to the SCP, so should be ignored by OS + * drivers. + */ +union rvu_af_ras { + u64 u; + struct rvu_af_ras_s { + u64 msix_poison : 1; + u64 reserved_1_63 : 63; + } s; + /* struct rvu_af_ras_s cn; */ +}; + +static inline u64 RVU_AF_RAS(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_RAS(void) +{ + return 0x100; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_ras_ena_w1c + * + * RVU Admin Function RAS Interrupt Enable Clear Register This register + * clears interrupt enable bits. + */ +union rvu_af_ras_ena_w1c { + u64 u; + struct rvu_af_ras_ena_w1c_s { + u64 msix_poison : 1; + u64 reserved_1_63 : 63; + } s; + /* struct rvu_af_ras_ena_w1c_s cn; */ +}; + +static inline u64 RVU_AF_RAS_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_RAS_ENA_W1C(void) +{ + return 0x118; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_ras_ena_w1s + * + * RVU Admin Function RAS Interrupt Enable Set Register This register + * sets interrupt enable bits. + */ +union rvu_af_ras_ena_w1s { + u64 u; + struct rvu_af_ras_ena_w1s_s { + u64 msix_poison : 1; + u64 reserved_1_63 : 63; + } s; + /* struct rvu_af_ras_ena_w1s_s cn; */ +}; + +static inline u64 RVU_AF_RAS_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_RAS_ENA_W1S(void) +{ + return 0x110; +} + +/** + * Register (RVU_PF_BAR0) rvu_af_ras_w1s + * + * RVU Admin Function RAS Interrupt Set Register This register sets + * interrupt bits. + */ +union rvu_af_ras_w1s { + u64 u; + struct rvu_af_ras_w1s_s { + u64 msix_poison : 1; + u64 reserved_1_63 : 63; + } s; + /* struct rvu_af_ras_w1s_s cn; */ +}; + +static inline u64 RVU_AF_RAS_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_AF_RAS_W1S(void) +{ + return 0x108; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_block_addr#_disc + * + * RVU PF Block Address Discovery Registers These registers allow each PF + * driver to discover block resources that are provisioned to its PF. The + * register's BLOCK_ADDR index is enumerated by RVU_BLOCK_ADDR_E. + */ +union rvu_pf_block_addrx_disc { + u64 u; + struct rvu_pf_block_addrx_disc_s { + u64 num_lfs : 9; + u64 reserved_9_10 : 2; + u64 imp : 1; + u64 rid : 8; + u64 btype : 8; + u64 reserved_28_63 : 36; + } s; + /* struct rvu_pf_block_addrx_disc_s cn; */ +}; + +static inline u64 RVU_PF_BLOCK_ADDRX_DISC(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_BLOCK_ADDRX_DISC(u64 a) +{ + return 0x200 + 8 * a; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_int + * + * RVU PF Interrupt Registers + */ +union rvu_pf_int { + u64 u; + struct rvu_pf_int_s { + u64 mbox : 1; + u64 reserved_1_63 : 63; + } s; + /* struct rvu_pf_int_s cn; */ +}; + +static inline u64 RVU_PF_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_INT(void) +{ + return 0xc20; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_int_ena_w1c + * + * RVU PF Interrupt Enable Clear Register This register clears interrupt + * enable bits. + */ +union rvu_pf_int_ena_w1c { + u64 u; + struct rvu_pf_int_ena_w1c_s { + u64 mbox : 1; + u64 reserved_1_63 : 63; + } s; + /* struct rvu_pf_int_ena_w1c_s cn; */ +}; + +static inline u64 RVU_PF_INT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_INT_ENA_W1C(void) +{ + return 0xc38; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_int_ena_w1s + * + * RVU PF Interrupt Enable Set Register This register sets interrupt + * enable bits. + */ +union rvu_pf_int_ena_w1s { + u64 u; + struct rvu_pf_int_ena_w1s_s { + u64 mbox : 1; + u64 reserved_1_63 : 63; + } s; + /* struct rvu_pf_int_ena_w1s_s cn; */ +}; + +static inline u64 RVU_PF_INT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_INT_ENA_W1S(void) +{ + return 0xc30; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_int_w1s + * + * RVU PF Interrupt Set Register This register sets interrupt bits. + */ +union rvu_pf_int_w1s { + u64 u; + struct rvu_pf_int_w1s_s { + u64 mbox : 1; + u64 reserved_1_63 : 63; + } s; + /* struct rvu_pf_int_w1s_s cn; */ +}; + +static inline u64 RVU_PF_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_INT_W1S(void) +{ + return 0xc28; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_msix_pba# + * + * RVU PF MSI-X Pending-Bit-Array Registers This register is the MSI-X PF + * PBA table. + */ +union rvu_pf_msix_pbax { + u64 u; + struct rvu_pf_msix_pbax_s { + u64 pend : 64; + } s; + /* struct rvu_pf_msix_pbax_s cn; */ +}; + +static inline u64 RVU_PF_MSIX_PBAX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_MSIX_PBAX(u64 a) +{ + return 0xf0000 + 8 * a; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_msix_vec#_addr + * + * RVU PF MSI-X Vector-Table Address Registers These registers and + * RVU_PF_MSIX_VEC()_CTL form the PF MSI-X vector table. The number of + * MSI-X vectors for a given PF is specified by + * RVU_PRIV_PF()_MSIX_CFG[PF_MSIXT_SIZEM1] (plus 1). Software must do a + * read after any writes to the MSI-X vector table to ensure that the + * writes have completed before interrupts are generated to the modified + * vectors. + */ +union rvu_pf_msix_vecx_addr { + u64 u; + struct rvu_pf_msix_vecx_addr_s { + u64 secvec : 1; + u64 reserved_1 : 1; + u64 addr : 51; + u64 reserved_53_63 : 11; + } s; + /* struct rvu_pf_msix_vecx_addr_s cn; */ +}; + +static inline u64 RVU_PF_MSIX_VECX_ADDR(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_MSIX_VECX_ADDR(u64 a) +{ + return 0x80000 + 0x10 * a; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_msix_vec#_ctl + * + * RVU PF MSI-X Vector-Table Control and Data Registers These registers + * and RVU_PF_MSIX_VEC()_ADDR form the PF MSI-X vector table. + */ +union rvu_pf_msix_vecx_ctl { + u64 u; + struct rvu_pf_msix_vecx_ctl_s { + u64 data : 32; + u64 mask : 1; + u64 reserved_33_63 : 31; + } s; + /* struct rvu_pf_msix_vecx_ctl_s cn; */ +}; + +static inline u64 RVU_PF_MSIX_VECX_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_MSIX_VECX_CTL(u64 a) +{ + return 0x80008 + 0x10 * a; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_pfaf_mbox# + * + * RVU PF/AF Mailbox Registers + */ +union rvu_pf_pfaf_mboxx { + u64 u; + struct rvu_pf_pfaf_mboxx_s { + u64 data : 64; + } s; + /* struct rvu_pf_pfaf_mboxx_s cn; */ +}; + +static inline u64 RVU_PF_PFAF_MBOXX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_PFAF_MBOXX(u64 a) +{ + return 0xc00 + 8 * a; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_vf#_pfvf_mbox# + * + * RVU PF/VF Mailbox Registers + */ +union rvu_pf_vfx_pfvf_mboxx { + u64 u; + struct rvu_pf_vfx_pfvf_mboxx_s { + u64 data : 64; + } s; + /* struct rvu_pf_vfx_pfvf_mboxx_s cn; */ +}; + +static inline u64 RVU_PF_VFX_PFVF_MBOXX(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_VFX_PFVF_MBOXX(u64 a, u64 b) +{ + return 0 + 0x1000 * a + 8 * b; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_vf_bar4_addr + * + * RVU PF VF BAR4 Address Registers + */ +union rvu_pf_vf_bar4_addr { + u64 u; + struct rvu_pf_vf_bar4_addr_s { + u64 reserved_0_15 : 16; + u64 addr : 48; + } s; + /* struct rvu_pf_vf_bar4_addr_s cn; */ +}; + +static inline u64 RVU_PF_VF_BAR4_ADDR(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_VF_BAR4_ADDR(void) +{ + return 0x10; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_vfflr_int# + * + * RVU PF VF Function Level Reset Interrupt Registers + */ +union rvu_pf_vfflr_intx { + u64 u; + struct rvu_pf_vfflr_intx_s { + u64 flr : 64; + } s; + /* struct rvu_pf_vfflr_intx_s cn; */ +}; + +static inline u64 RVU_PF_VFFLR_INTX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_VFFLR_INTX(u64 a) +{ + return 0x900 + 8 * a; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_vfflr_int_ena_w1c# + * + * RVU PF VF Function Level Reset Interrupt Enable Clear Registers This + * register clears interrupt enable bits. + */ +union rvu_pf_vfflr_int_ena_w1cx { + u64 u; + struct rvu_pf_vfflr_int_ena_w1cx_s { + u64 flr : 64; + } s; + /* struct rvu_pf_vfflr_int_ena_w1cx_s cn; */ +}; + +static inline u64 RVU_PF_VFFLR_INT_ENA_W1CX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_VFFLR_INT_ENA_W1CX(u64 a) +{ + return 0x960 + 8 * a; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_vfflr_int_ena_w1s# + * + * RVU PF VF Function Level Reset Interrupt Enable Set Registers This + * register sets interrupt enable bits. + */ +union rvu_pf_vfflr_int_ena_w1sx { + u64 u; + struct rvu_pf_vfflr_int_ena_w1sx_s { + u64 flr : 64; + } s; + /* struct rvu_pf_vfflr_int_ena_w1sx_s cn; */ +}; + +static inline u64 RVU_PF_VFFLR_INT_ENA_W1SX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_VFFLR_INT_ENA_W1SX(u64 a) +{ + return 0x940 + 8 * a; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_vfflr_int_w1s# + * + * RVU PF VF Function Level Reset Interrupt Set Registers This register + * sets interrupt bits. + */ +union rvu_pf_vfflr_int_w1sx { + u64 u; + struct rvu_pf_vfflr_int_w1sx_s { + u64 flr : 64; + } s; + /* struct rvu_pf_vfflr_int_w1sx_s cn; */ +}; + +static inline u64 RVU_PF_VFFLR_INT_W1SX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_VFFLR_INT_W1SX(u64 a) +{ + return 0x920 + 8 * a; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_vfme_int# + * + * RVU PF VF Bus Master Enable Interrupt Registers + */ +union rvu_pf_vfme_intx { + u64 u; + struct rvu_pf_vfme_intx_s { + u64 me : 64; + } s; + /* struct rvu_pf_vfme_intx_s cn; */ +}; + +static inline u64 RVU_PF_VFME_INTX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_VFME_INTX(u64 a) +{ + return 0x980 + 8 * a; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_vfme_int_ena_w1c# + * + * RVU PF VF Bus Master Enable Interrupt Enable Clear Registers This + * register clears interrupt enable bits. + */ +union rvu_pf_vfme_int_ena_w1cx { + u64 u; + struct rvu_pf_vfme_int_ena_w1cx_s { + u64 me : 64; + } s; + /* struct rvu_pf_vfme_int_ena_w1cx_s cn; */ +}; + +static inline u64 RVU_PF_VFME_INT_ENA_W1CX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_VFME_INT_ENA_W1CX(u64 a) +{ + return 0x9e0 + 8 * a; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_vfme_int_ena_w1s# + * + * RVU PF VF Bus Master Enable Interrupt Enable Set Registers This + * register sets interrupt enable bits. + */ +union rvu_pf_vfme_int_ena_w1sx { + u64 u; + struct rvu_pf_vfme_int_ena_w1sx_s { + u64 me : 64; + } s; + /* struct rvu_pf_vfme_int_ena_w1sx_s cn; */ +}; + +static inline u64 RVU_PF_VFME_INT_ENA_W1SX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_VFME_INT_ENA_W1SX(u64 a) +{ + return 0x9c0 + 8 * a; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_vfme_int_w1s# + * + * RVU PF VF Bus Master Enable Interrupt Set Registers This register sets + * interrupt bits. + */ +union rvu_pf_vfme_int_w1sx { + u64 u; + struct rvu_pf_vfme_int_w1sx_s { + u64 me : 64; + } s; + /* struct rvu_pf_vfme_int_w1sx_s cn; */ +}; + +static inline u64 RVU_PF_VFME_INT_W1SX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_VFME_INT_W1SX(u64 a) +{ + return 0x9a0 + 8 * a; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_vfme_status# + * + * RVU PF VF Bus Master Enable Status Registers + */ +union rvu_pf_vfme_statusx { + u64 u; + struct rvu_pf_vfme_statusx_s { + u64 me : 64; + } s; + /* struct rvu_pf_vfme_statusx_s cn; */ +}; + +static inline u64 RVU_PF_VFME_STATUSX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_VFME_STATUSX(u64 a) +{ + return 0x800 + 8 * a; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_vfpf_mbox_int# + * + * RVU VF to PF Mailbox Interrupt Registers + */ +union rvu_pf_vfpf_mbox_intx { + u64 u; + struct rvu_pf_vfpf_mbox_intx_s { + u64 mbox : 64; + } s; + /* struct rvu_pf_vfpf_mbox_intx_s cn; */ +}; + +static inline u64 RVU_PF_VFPF_MBOX_INTX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_VFPF_MBOX_INTX(u64 a) +{ + return 0x880 + 8 * a; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_vfpf_mbox_int_ena_w1c# + * + * RVU VF to PF Mailbox Interrupt Enable Clear Registers This register + * clears interrupt enable bits. + */ +union rvu_pf_vfpf_mbox_int_ena_w1cx { + u64 u; + struct rvu_pf_vfpf_mbox_int_ena_w1cx_s { + u64 mbox : 64; + } s; + /* struct rvu_pf_vfpf_mbox_int_ena_w1cx_s cn; */ +}; + +static inline u64 RVU_PF_VFPF_MBOX_INT_ENA_W1CX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_VFPF_MBOX_INT_ENA_W1CX(u64 a) +{ + return 0x8e0 + 8 * a; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_vfpf_mbox_int_ena_w1s# + * + * RVU VF to PF Mailbox Interrupt Enable Set Registers This register sets + * interrupt enable bits. + */ +union rvu_pf_vfpf_mbox_int_ena_w1sx { + u64 u; + struct rvu_pf_vfpf_mbox_int_ena_w1sx_s { + u64 mbox : 64; + } s; + /* struct rvu_pf_vfpf_mbox_int_ena_w1sx_s cn; */ +}; + +static inline u64 RVU_PF_VFPF_MBOX_INT_ENA_W1SX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_VFPF_MBOX_INT_ENA_W1SX(u64 a) +{ + return 0x8c0 + 8 * a; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_vfpf_mbox_int_w1s# + * + * RVU VF to PF Mailbox Interrupt Set Registers This register sets + * interrupt bits. + */ +union rvu_pf_vfpf_mbox_int_w1sx { + u64 u; + struct rvu_pf_vfpf_mbox_int_w1sx_s { + u64 mbox : 64; + } s; + /* struct rvu_pf_vfpf_mbox_int_w1sx_s cn; */ +}; + +static inline u64 RVU_PF_VFPF_MBOX_INT_W1SX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_VFPF_MBOX_INT_W1SX(u64 a) +{ + return 0x8a0 + 8 * a; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_vftrpend# + * + * RVU PF VF Transaction Pending Registers + */ +union rvu_pf_vftrpendx { + u64 u; + struct rvu_pf_vftrpendx_s { + u64 trpend : 64; + } s; + /* struct rvu_pf_vftrpendx_s cn; */ +}; + +static inline u64 RVU_PF_VFTRPENDX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_VFTRPENDX(u64 a) +{ + return 0x820 + 8 * a; +} + +/** + * Register (RVU_PF_BAR2) rvu_pf_vftrpend_w1s# + * + * RVU PF VF Transaction Pending Set Registers This register reads or + * sets bits. + */ +union rvu_pf_vftrpend_w1sx { + u64 u; + struct rvu_pf_vftrpend_w1sx_s { + u64 trpend : 64; + } s; + /* struct rvu_pf_vftrpend_w1sx_s cn; */ +}; + +static inline u64 RVU_PF_VFTRPEND_W1SX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PF_VFTRPEND_W1SX(u64 a) +{ + return 0x840 + 8 * a; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_active_pc + * + * RVU Active Program Counter Register + */ +union rvu_priv_active_pc { + u64 u; + struct rvu_priv_active_pc_s { + u64 active_pc : 64; + } s; + /* struct rvu_priv_active_pc_s cn; */ +}; + +static inline u64 RVU_PRIV_ACTIVE_PC(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_ACTIVE_PC(void) +{ + return 0x8000030; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_block_type#_rev + * + * RVU Privileged Block Type Revision Registers These registers are used + * by configuration software to specify the revision ID of each block + * type enumerated by RVU_BLOCK_TYPE_E, to assist VF/PF software + * discovery. + */ +union rvu_priv_block_typex_rev { + u64 u; + struct rvu_priv_block_typex_rev_s { + u64 rid : 8; + u64 reserved_8_63 : 56; + } s; + /* struct rvu_priv_block_typex_rev_s cn; */ +}; + +static inline u64 RVU_PRIV_BLOCK_TYPEX_REV(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_BLOCK_TYPEX_REV(u64 a) +{ + return 0x8000400 + 8 * a; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_clk_cfg + * + * RVU Privileged General Configuration Register + */ +union rvu_priv_clk_cfg { + u64 u; + struct rvu_priv_clk_cfg_s { + u64 blk_clken : 1; + u64 ncbi_clken : 1; + u64 reserved_2_63 : 62; + } s; + /* struct rvu_priv_clk_cfg_s cn; */ +}; + +static inline u64 RVU_PRIV_CLK_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_CLK_CFG(void) +{ + return 0x8000020; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_const + * + * RVU Privileged Constants Register This register contains constants for + * software discovery. + */ +union rvu_priv_const { + u64 u; + struct rvu_priv_const_s { + u64 max_msix : 20; + u64 hwvfs : 12; + u64 pfs : 8; + u64 max_vfs_per_pf : 8; + u64 reserved_48_63 : 16; + } s; + /* struct rvu_priv_const_s cn; */ +}; + +static inline u64 RVU_PRIV_CONST(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_CONST(void) +{ + return 0x8000000; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_gen_cfg + * + * RVU Privileged General Configuration Register + */ +union rvu_priv_gen_cfg { + u64 u; + struct rvu_priv_gen_cfg_s { + u64 lock : 1; + u64 reserved_1_63 : 63; + } s; + /* struct rvu_priv_gen_cfg_s cn; */ +}; + +static inline u64 RVU_PRIV_GEN_CFG(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_GEN_CFG(void) +{ + return 0x8000010; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_hwvf#_cpt#_cfg + * + * RVU Privileged Hardware VF CPT Configuration Registers Similar to + * RVU_PRIV_HWVF()_NIX()_CFG, but for CPT({a}) block. + */ +union rvu_priv_hwvfx_cptx_cfg { + u64 u; + struct rvu_priv_hwvfx_cptx_cfg_s { + u64 num_lfs : 9; + u64 reserved_9_63 : 55; + } s; + /* struct rvu_priv_hwvfx_cptx_cfg_s cn; */ +}; + +static inline u64 RVU_PRIV_HWVFX_CPTX_CFG(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_HWVFX_CPTX_CFG(u64 a, u64 b) +{ + return 0x8001350 + 0x10000 * a + 8 * b; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_hwvf#_int_cfg + * + * RVU Privileged Hardware VF Interrupt Configuration Registers + */ +union rvu_priv_hwvfx_int_cfg { + u64 u; + struct rvu_priv_hwvfx_int_cfg_s { + u64 msix_offset : 11; + u64 reserved_11 : 1; + u64 msix_size : 8; + u64 reserved_20_63 : 44; + } s; + /* struct rvu_priv_hwvfx_int_cfg_s cn; */ +}; + +static inline u64 RVU_PRIV_HWVFX_INT_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_HWVFX_INT_CFG(u64 a) +{ + return 0x8001280 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_hwvf#_nix#_cfg + * + * RVU Privileged Hardware VF NIX Configuration Registers These registers + * are used to assist VF software discovery. For each HWVF, if the HWVF + * is mapped to a VF by RVU_PRIV_PF()_CFG[FIRST_HWVF,NVF], software + * writes NIX block's resource configuration for the VF in this register. + * The VF driver can read RVU_VF_BLOCK_ADDR()_DISC to discover the + * configuration. + */ +union rvu_priv_hwvfx_nixx_cfg { + u64 u; + struct rvu_priv_hwvfx_nixx_cfg_s { + u64 has_lf : 1; + u64 reserved_1_63 : 63; + } s; + /* struct rvu_priv_hwvfx_nixx_cfg_s cn; */ +}; + +static inline u64 RVU_PRIV_HWVFX_NIXX_CFG(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_HWVFX_NIXX_CFG(u64 a, u64 b) +{ + return 0x8001300 + 0x10000 * a + 8 * b; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_hwvf#_npa_cfg + * + * RVU Privileged Hardware VF NPA Configuration Registers Similar to + * RVU_PRIV_HWVF()_NIX()_CFG, but for NPA block. + */ +union rvu_priv_hwvfx_npa_cfg { + u64 u; + struct rvu_priv_hwvfx_npa_cfg_s { + u64 has_lf : 1; + u64 reserved_1_63 : 63; + } s; + /* struct rvu_priv_hwvfx_npa_cfg_s cn; */ +}; + +static inline u64 RVU_PRIV_HWVFX_NPA_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_HWVFX_NPA_CFG(u64 a) +{ + return 0x8001310 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_hwvf#_sso_cfg + * + * RVU Privileged Hardware VF SSO Configuration Registers Similar to + * RVU_PRIV_HWVF()_NIX()_CFG, but for SSO block. + */ +union rvu_priv_hwvfx_sso_cfg { + u64 u; + struct rvu_priv_hwvfx_sso_cfg_s { + u64 num_lfs : 9; + u64 reserved_9_63 : 55; + } s; + /* struct rvu_priv_hwvfx_sso_cfg_s cn; */ +}; + +static inline u64 RVU_PRIV_HWVFX_SSO_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_HWVFX_SSO_CFG(u64 a) +{ + return 0x8001320 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_hwvf#_ssow_cfg + * + * RVU Privileged Hardware VF SSO Work Slot Configuration Registers + * Similar to RVU_PRIV_HWVF()_NIX()_CFG, but for SSOW block. + */ +union rvu_priv_hwvfx_ssow_cfg { + u64 u; + struct rvu_priv_hwvfx_ssow_cfg_s { + u64 num_lfs : 9; + u64 reserved_9_63 : 55; + } s; + /* struct rvu_priv_hwvfx_ssow_cfg_s cn; */ +}; + +static inline u64 RVU_PRIV_HWVFX_SSOW_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_HWVFX_SSOW_CFG(u64 a) +{ + return 0x8001330 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_hwvf#_tim_cfg + * + * RVU Privileged Hardware VF SSO Work Slot Configuration Registers + * Similar to RVU_PRIV_HWVF()_NIX()_CFG, but for TIM block. + */ +union rvu_priv_hwvfx_tim_cfg { + u64 u; + struct rvu_priv_hwvfx_tim_cfg_s { + u64 num_lfs : 9; + u64 reserved_9_63 : 55; + } s; + /* struct rvu_priv_hwvfx_tim_cfg_s cn; */ +}; + +static inline u64 RVU_PRIV_HWVFX_TIM_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_HWVFX_TIM_CFG(u64 a) +{ + return 0x8001340 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_pf#_cfg + * + * RVU Privileged PF Configuration Registers + */ +union rvu_priv_pfx_cfg { + u64 u; + struct rvu_priv_pfx_cfg_s { + u64 first_hwvf : 12; + u64 nvf : 8; + u64 ena : 1; + u64 af_ena : 1; + u64 me_flr_ena : 1; + u64 pf_vf_io_bar4 : 1; + u64 reserved_24_63 : 40; + } s; + struct rvu_priv_pfx_cfg_cn96xxp1 { + u64 first_hwvf : 12; + u64 nvf : 8; + u64 ena : 1; + u64 af_ena : 1; + u64 me_flr_ena : 1; + u64 reserved_23_63 : 41; + } cn96xxp1; + /* struct rvu_priv_pfx_cfg_s cn96xxp3; */ + /* struct rvu_priv_pfx_cfg_cn96xxp1 cnf95xx; */ +}; + +static inline u64 RVU_PRIV_PFX_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_PFX_CFG(u64 a) +{ + return 0x8000100 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_pf#_cpt#_cfg + * + * RVU Privileged PF CPT Configuration Registers Similar to + * RVU_PRIV_PF()_NIX()_CFG, but for CPT({a}) block. + */ +union rvu_priv_pfx_cptx_cfg { + u64 u; + struct rvu_priv_pfx_cptx_cfg_s { + u64 num_lfs : 9; + u64 reserved_9_63 : 55; + } s; + /* struct rvu_priv_pfx_cptx_cfg_s cn; */ +}; + +static inline u64 RVU_PRIV_PFX_CPTX_CFG(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_PFX_CPTX_CFG(u64 a, u64 b) +{ + return 0x8000350 + 0x10000 * a + 8 * b; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_pf#_id_cfg + * + * RVU Privileged PF ID Configuration Registers + */ +union rvu_priv_pfx_id_cfg { + u64 u; + struct rvu_priv_pfx_id_cfg_s { + u64 pf_devid : 8; + u64 vf_devid : 8; + u64 class_code : 24; + u64 reserved_40_63 : 24; + } s; + /* struct rvu_priv_pfx_id_cfg_s cn; */ +}; + +static inline u64 RVU_PRIV_PFX_ID_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_PFX_ID_CFG(u64 a) +{ + return 0x8000120 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_pf#_int_cfg + * + * RVU Privileged PF Interrupt Configuration Registers + */ +union rvu_priv_pfx_int_cfg { + u64 u; + struct rvu_priv_pfx_int_cfg_s { + u64 msix_offset : 11; + u64 reserved_11 : 1; + u64 msix_size : 8; + u64 reserved_20_63 : 44; + } s; + /* struct rvu_priv_pfx_int_cfg_s cn; */ +}; + +static inline u64 RVU_PRIV_PFX_INT_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_PFX_INT_CFG(u64 a) +{ + return 0x8000200 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_pf#_msix_cfg + * + * RVU Privileged PF MSI-X Configuration Registers These registers + * specify MSI-X table sizes and locations for RVU PFs and associated + * VFs. Hardware maintains all RVU MSI-X tables in a contiguous memory + * region in LLC/DRAM called the MSI-X table region. The table region's + * base AF IOVA is specified by RVU_AF_MSIXTR_BASE, and its size as a + * multiple of 16-byte RVU_MSIX_VEC_S structures must be less than or + * equal to RVU_PRIV_CONST[MAX_MSIX]. A PF's MSI-X table consists of the + * following range of RVU_MSIX_VEC_S structures in the table region: * + * First index: [PF_MSIXT_OFFSET]. * Last index: [PF_MSIXT_OFFSET] + + * [PF_MSIXT_SIZEM1]. If a PF has enabled VFs (associated + * RVU_PRIV_PF()_CFG[NVF] is nonzero), then each VF's MSI-X table + * consumes the following range of RVU_MSIX_VEC_S structures: * First + * index: [VF_MSIXT_OFFSET] + N*([VF_MSIXT_SIZEM1] + 1). * Last index: + * [VF_MSIXT_OFFSET] + N*([VF_MSIXT_SIZEM1] + 1) + [VF_MSIXT_SIZEM1]. + * N=0 for the first VF, N=1 for the second VF, etc. Different PFs and + * VFs must have non-overlapping vector ranges, and the last index of any + * range must be less than RVU_PRIV_CONST[MAX_MSIX]. + */ +union rvu_priv_pfx_msix_cfg { + u64 u; + struct rvu_priv_pfx_msix_cfg_s { + u64 vf_msixt_sizem1 : 12; + u64 vf_msixt_offset : 20; + u64 pf_msixt_sizem1 : 12; + u64 pf_msixt_offset : 20; + } s; + /* struct rvu_priv_pfx_msix_cfg_s cn; */ +}; + +static inline u64 RVU_PRIV_PFX_MSIX_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_PFX_MSIX_CFG(u64 a) +{ + return 0x8000110 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_pf#_nix#_cfg + * + * RVU Privileged PF NIX Configuration Registers These registers are used + * to assist PF software discovery. For each enabled RVU PF, software + * writes the block's resource configuration for the PF in this register. + * The PF driver can read RVU_PF_BLOCK_ADDR()_DISC to discover the + * configuration. + */ +union rvu_priv_pfx_nixx_cfg { + u64 u; + struct rvu_priv_pfx_nixx_cfg_s { + u64 has_lf : 1; + u64 reserved_1_63 : 63; + } s; + /* struct rvu_priv_pfx_nixx_cfg_s cn; */ +}; + +static inline u64 RVU_PRIV_PFX_NIXX_CFG(u64 a, u64 b) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_PFX_NIXX_CFG(u64 a, u64 b) +{ + return 0x8000300 + 0x10000 * a + 8 * b; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_pf#_npa_cfg + * + * RVU Privileged PF NPA Configuration Registers Similar to + * RVU_PRIV_PF()_NIX()_CFG, but for NPA block. + */ +union rvu_priv_pfx_npa_cfg { + u64 u; + struct rvu_priv_pfx_npa_cfg_s { + u64 has_lf : 1; + u64 reserved_1_63 : 63; + } s; + /* struct rvu_priv_pfx_npa_cfg_s cn; */ +}; + +static inline u64 RVU_PRIV_PFX_NPA_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_PFX_NPA_CFG(u64 a) +{ + return 0x8000310 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_pf#_sso_cfg + * + * RVU Privileged PF SSO Configuration Registers Similar to + * RVU_PRIV_PF()_NIX()_CFG, but for SSO block. + */ +union rvu_priv_pfx_sso_cfg { + u64 u; + struct rvu_priv_pfx_sso_cfg_s { + u64 num_lfs : 9; + u64 reserved_9_63 : 55; + } s; + /* struct rvu_priv_pfx_sso_cfg_s cn; */ +}; + +static inline u64 RVU_PRIV_PFX_SSO_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_PFX_SSO_CFG(u64 a) +{ + return 0x8000320 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_pf#_ssow_cfg + * + * RVU Privileged PF SSO Work Slot Configuration Registers Similar to + * RVU_PRIV_PF()_NIX()_CFG, but for SSOW block. + */ +union rvu_priv_pfx_ssow_cfg { + u64 u; + struct rvu_priv_pfx_ssow_cfg_s { + u64 num_lfs : 9; + u64 reserved_9_63 : 55; + } s; + /* struct rvu_priv_pfx_ssow_cfg_s cn; */ +}; + +static inline u64 RVU_PRIV_PFX_SSOW_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_PFX_SSOW_CFG(u64 a) +{ + return 0x8000330 + 0x10000 * a; +} + +/** + * Register (RVU_PF_BAR0) rvu_priv_pf#_tim_cfg + * + * RVU Privileged PF SSO Work Slot Configuration Registers Similar to + * RVU_PRIV_PF()_NIX()_CFG, but for TIM block. + */ +union rvu_priv_pfx_tim_cfg { + u64 u; + struct rvu_priv_pfx_tim_cfg_s { + u64 num_lfs : 9; + u64 reserved_9_63 : 55; + } s; + /* struct rvu_priv_pfx_tim_cfg_s cn; */ +}; + +static inline u64 RVU_PRIV_PFX_TIM_CFG(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_PRIV_PFX_TIM_CFG(u64 a) +{ + return 0x8000340 + 0x10000 * a; +} + +/** + * Register (RVU_VF_BAR2) rvu_vf_block_addr#_disc + * + * RVU VF Block Address Discovery Registers These registers allow each VF + * driver to discover block resources that are provisioned to its VF. The + * register's BLOCK_ADDR index is enumerated by RVU_BLOCK_ADDR_E. + */ +union rvu_vf_block_addrx_disc { + u64 u; + struct rvu_vf_block_addrx_disc_s { + u64 num_lfs : 9; + u64 reserved_9_10 : 2; + u64 imp : 1; + u64 rid : 8; + u64 btype : 8; + u64 reserved_28_63 : 36; + } s; + /* struct rvu_vf_block_addrx_disc_s cn; */ +}; + +static inline u64 RVU_VF_BLOCK_ADDRX_DISC(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_VF_BLOCK_ADDRX_DISC(u64 a) +{ + return 0x200 + 8 * a; +} + +/** + * Register (RVU_VF_BAR2) rvu_vf_int + * + * RVU VF Interrupt Registers + */ +union rvu_vf_int { + u64 u; + struct rvu_vf_int_s { + u64 mbox : 1; + u64 reserved_1_63 : 63; + } s; + /* struct rvu_vf_int_s cn; */ +}; + +static inline u64 RVU_VF_INT(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_VF_INT(void) +{ + return 0x20; +} + +/** + * Register (RVU_VF_BAR2) rvu_vf_int_ena_w1c + * + * RVU VF Interrupt Enable Clear Register This register clears interrupt + * enable bits. + */ +union rvu_vf_int_ena_w1c { + u64 u; + struct rvu_vf_int_ena_w1c_s { + u64 mbox : 1; + u64 reserved_1_63 : 63; + } s; + /* struct rvu_vf_int_ena_w1c_s cn; */ +}; + +static inline u64 RVU_VF_INT_ENA_W1C(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_VF_INT_ENA_W1C(void) +{ + return 0x38; +} + +/** + * Register (RVU_VF_BAR2) rvu_vf_int_ena_w1s + * + * RVU VF Interrupt Enable Set Register This register sets interrupt + * enable bits. + */ +union rvu_vf_int_ena_w1s { + u64 u; + struct rvu_vf_int_ena_w1s_s { + u64 mbox : 1; + u64 reserved_1_63 : 63; + } s; + /* struct rvu_vf_int_ena_w1s_s cn; */ +}; + +static inline u64 RVU_VF_INT_ENA_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_VF_INT_ENA_W1S(void) +{ + return 0x30; +} + +/** + * Register (RVU_VF_BAR2) rvu_vf_int_w1s + * + * RVU VF Interrupt Set Register This register sets interrupt bits. + */ +union rvu_vf_int_w1s { + u64 u; + struct rvu_vf_int_w1s_s { + u64 mbox : 1; + u64 reserved_1_63 : 63; + } s; + /* struct rvu_vf_int_w1s_s cn; */ +}; + +static inline u64 RVU_VF_INT_W1S(void) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_VF_INT_W1S(void) +{ + return 0x28; +} + +/** + * Register (RVU_VF_BAR2) rvu_vf_msix_pba# + * + * RVU VF MSI-X Pending-Bit-Array Registers This register is the MSI-X VF + * PBA table. + */ +union rvu_vf_msix_pbax { + u64 u; + struct rvu_vf_msix_pbax_s { + u64 pend : 64; + } s; + /* struct rvu_vf_msix_pbax_s cn; */ +}; + +static inline u64 RVU_VF_MSIX_PBAX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_VF_MSIX_PBAX(u64 a) +{ + return 0xf0000 + 8 * a; +} + +/** + * Register (RVU_VF_BAR2) rvu_vf_msix_vec#_addr + * + * RVU VF MSI-X Vector-Table Address Registers These registers and + * RVU_VF_MSIX_VEC()_CTL form the VF MSI-X vector table. The number of + * MSI-X vectors for a given VF is specified by + * RVU_PRIV_PF()_MSIX_CFG[VF_MSIXT_SIZEM1] (plus 1). Software must do a + * read after any writes to the MSI-X vector table to ensure that the + * writes have completed before interrupts are generated to the modified + * vectors. + */ +union rvu_vf_msix_vecx_addr { + u64 u; + struct rvu_vf_msix_vecx_addr_s { + u64 secvec : 1; + u64 reserved_1 : 1; + u64 addr : 51; + u64 reserved_53_63 : 11; + } s; + /* struct rvu_vf_msix_vecx_addr_s cn; */ +}; + +static inline u64 RVU_VF_MSIX_VECX_ADDR(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_VF_MSIX_VECX_ADDR(u64 a) +{ + return 0x80000 + 0x10 * a; +} + +/** + * Register (RVU_VF_BAR2) rvu_vf_msix_vec#_ctl + * + * RVU VF MSI-X Vector-Table Control and Data Registers These registers + * and RVU_VF_MSIX_VEC()_ADDR form the VF MSI-X vector table. + */ +union rvu_vf_msix_vecx_ctl { + u64 u; + struct rvu_vf_msix_vecx_ctl_s { + u64 data : 32; + u64 mask : 1; + u64 reserved_33_63 : 31; + } s; + /* struct rvu_vf_msix_vecx_ctl_s cn; */ +}; + +static inline u64 RVU_VF_MSIX_VECX_CTL(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_VF_MSIX_VECX_CTL(u64 a) +{ + return 0x80008 + 0x10 * a; +} + +/** + * Register (RVU_VF_BAR2) rvu_vf_vfpf_mbox# + * + * RVU VF/PF Mailbox Registers + */ +union rvu_vf_vfpf_mboxx { + u64 u; + struct rvu_vf_vfpf_mboxx_s { + u64 data : 64; + } s; + /* struct rvu_vf_vfpf_mboxx_s cn; */ +}; + +static inline u64 RVU_VF_VFPF_MBOXX(u64 a) + __attribute__ ((pure, always_inline)); +static inline u64 RVU_VF_VFPF_MBOXX(u64 a) +{ + return 0 + 8 * a; +} + +#endif /* __CSRS_RVU_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx2/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/gpio.h new file mode 100644 index 000000000..3943ffd95 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/gpio.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx2/smc-id.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/smc-id.h new file mode 100644 index 000000000..93a81b295 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/smc-id.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#ifndef __SMC_ID_H__ +#define __SMC_ID_H__ + +/* SMC function IDs for general purpose queries */ + +#define OCTEONTX2_SVC_CALL_COUNT 0xc200ff00 +#define OCTEONTX2_SVC_UID 0xc200ff01 + +#define OCTEONTX2_SVC_VERSION 0xc200ff03 + +/* OcteonTX Service Calls version numbers */ +#define OCTEONTX2_VERSION_MAJOR 0x1 +#define OCTEONTX2_VERSION_MINOR 0x0 + +/* x1 - node number */ +#define OCTEONTX2_DRAM_SIZE 0xc2000301 +#define OCTEONTX2_NODE_COUNT 0xc2000601 +#define OCTEONTX2_DISABLE_RVU_LFS 0xc2000b01 + +#define OCTEONTX2_CONFIG_OOO 0xc2000b04 + +/* fail safe */ +#define OCTEONTX2_FSAFE_PR_BOOT_SUCCESS 0xc2000b02 + +#endif /* __SMC_ID_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx2/smc.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/smc.h new file mode 100644 index 000000000..8e719a2aa --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/smc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#ifndef __SMC_H__ +#define __SMC_H__ + +#include + +ssize_t smc_configure_ooo(unsigned int val); +ssize_t smc_dram_size(unsigned int node); +ssize_t smc_disable_rvu_lfs(unsigned int node); +ssize_t smc_flsf_fw_booted(void); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-octeontx2/soc.h b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/soc.h new file mode 100644 index 000000000..9cf6628da --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-octeontx2/soc.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2019 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#ifndef __SOC_H__ +#define __SOC_H__ + +/* Product PARTNUM */ +#define CN81XX 0xA2 +#define CN83XX 0xA3 +#define CN96XX 0xB2 +#define CN95XX 0xB3 + +/* Register defines */ + +#define otx_is_soc(soc) (read_partnum() == (soc)) +#define otx_is_board(model) (!strcmp(read_board_name(), model)) +#define otx_is_platform(platform) (read_platform() == (platform)) + +enum platform_t { + PLATFORM_HW = 0, + PLATFORM_EMULATOR = 1, + PLATFORM_ASIM = 3, +}; + +int read_platform(void); +u8 read_partnum(void); +const char *read_board_name(void); + +#endif /* __SOC_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap3/am35x_def.h b/roms/u-boot/arch/arm/include/asm/arch-omap3/am35x_def.h new file mode 100644 index 000000000..33f6db199 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap3/am35x_def.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * am35x_def.h - TI's AM35x specific definitions. + * + * Based on arch/arm/include/asm/arch-omap3/cpu.h + * + * Author: Ajay Kumar Gupta + * + * Copyright (c) 2010 Texas Instruments Incorporated + */ + +#ifndef _AM35X_DEF_H_ +#define _AM35X_DEF_H_ + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ + +/* LVL_INTR_CLEAR bits */ +#define USBOTGSS_INT_CLR (1 << 4) + +/* IP_SW_RESET bits */ +#define USBOTGSS_SW_RST (1 << 0) /* reset USBOTG */ +#define CPGMACSS_SW_RST (1 << 1) /* reset CPGMAC */ + +/* DEVCONF2 bits */ +#define CONF2_PHY_GPIOMODE (1 << 23) +#define CONF2_OTGMODE (3 << 14) +#define CONF2_NO_OVERRIDE (0 << 14) +#define CONF2_FORCE_HOST (1 << 14) +#define CONF2_FORCE_DEVICE (2 << 14) +#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14) +#define CONF2_SESENDEN (1 << 13) +#define CONF2_VBDTCTEN (1 << 12) +#define CONF2_REFFREQ_24MHZ (2 << 8) +#define CONF2_REFFREQ_26MHZ (7 << 8) +#define CONF2_REFFREQ_13MHZ (6 << 8) +#define CONF2_REFFREQ (0xf << 8) +#define CONF2_PHYCLKGD (1 << 7) +#define CONF2_VBUSSENSE (1 << 6) +#define CONF2_PHY_PLLON (1 << 5) +#define CONF2_RESET (1 << 4) +#define CONF2_PHYPWRDN (1 << 3) +#define CONF2_OTGPWRDN (1 << 2) +#define CONF2_DATPOL (1 << 1) + +/* General register mappings of system control module */ +#define AM35X_SCM_GEN_BASE 0x48002270 +struct am35x_scm_general { + u32 res1[0xC4]; /* 0x000 - 0x30C */ + u32 devconf2; /* 0x310 */ + u32 devconf3; /* 0x314 */ + u32 res2[0x2]; /* 0x318 - 0x31C */ + u32 cba_priority; /* 0x320 */ + u32 lvl_intr_clr; /* 0x324 */ + u32 ip_sw_reset; /* 0x328 */ + u32 ipss_clk_ctrl; /* 0x32C */ +}; +#define am35x_scm_general_regs ((struct am35x_scm_general *)AM35X_SCM_GEN_BASE) + +#define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000 + +#endif /*__ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +#endif /* _AM35X_DEF_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap3/clock.h b/roms/u-boot/arch/arm/include/asm/arch-omap3/clock.h new file mode 100644 index 000000000..ac537fcd3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap3/clock.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, + * Richard Woodruff + */ +#ifndef _CLOCKS_H_ +#define _CLOCKS_H_ + +#define LDELAY 12000000 + +#define S12M 12000000 +#define S13M 13000000 +#define S19_2M 19200000 +#define S24M 24000000 +#define S26M 26000000 +#define S38_4M 38400000 + +#define FCK_IVA2_ON 0x00000001 +#define FCK_CORE1_ON 0x03fffe29 +#define ICK_CORE1_ON 0x3ffffffb +#define ICK_CORE2_ON 0x0000001f +#define FCK_WKUP_ON 0x000000e9 +#define ICK_WKUP_ON 0x0000003f +#define FCK_DSS_ON 0x00000005 +#define ICK_DSS_ON 0x00000001 +#define FCK_CAM_ON 0x00000001 +#define ICK_CAM_ON 0x00000001 + +/* Used to index into DPLL parameter tables */ +typedef struct { + unsigned int m; + unsigned int n; + unsigned int fsel; + unsigned int m2; +} dpll_param; + +struct dpll_per_36x_param { + unsigned int sys_clk; + unsigned int m; + unsigned int n; + unsigned int m2; + unsigned int m3; + unsigned int m4; + unsigned int m5; + unsigned int m6; + unsigned int m2div; +}; + +/* Following functions are exported from lowlevel_init.S */ +extern dpll_param *get_mpu_dpll_param(void); +extern dpll_param *get_iva_dpll_param(void); +extern dpll_param *get_core_dpll_param(void); +extern dpll_param *get_per_dpll_param(void); +extern dpll_param *get_per2_dpll_param(void); + +extern dpll_param *get_36x_mpu_dpll_param(void); +extern dpll_param *get_36x_iva_dpll_param(void); +extern dpll_param *get_36x_core_dpll_param(void); +extern dpll_param *get_36x_per_dpll_param(void); +extern dpll_param *get_36x_per2_dpll_param(void); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap3/clocks_omap3.h b/roms/u-boot/arch/arm/include/asm/arch-omap3/clocks_omap3.h new file mode 100644 index 000000000..48bb391f3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap3/clocks_omap3.h @@ -0,0 +1,347 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, + * Richard Woodruff + */ +#ifndef _CLOCKS_OMAP3_H_ +#define _CLOCKS_OMAP3_H_ + +#define PLL_STOP 1 /* PER & IVA */ +#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ +#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ +#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ + +/* + * The following configurations are OPP and SysClk value independant + * and hence are defined here. All the other DPLL related values are + * tabulated in lowlevel_init.S. + */ + +/* CORE DPLL */ +#define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ +#define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ +#define CORE_FUSB_DIV 2 /* 41.5MHz: */ +#define CORE_L4_DIV 2 /* 83MHz : L4 */ +#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ +#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ +#define GFX_DIV_36X 5 /* 200MHz : CM_CLKSEL_GFX */ +#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ + +/* PER DPLL */ +#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ +#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ +#define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */ +#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ + +#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50)) + +/* MPU DPLL */ + +#define MPU_M_12_ES1 0x0FE +#define MPU_N_12_ES1 0x07 +#define MPU_FSEL_12_ES1 0x05 +#define MPU_M2_12_ES1 0x01 + +#define MPU_M_12_ES2 0x0FA +#define MPU_N_12_ES2 0x05 +#define MPU_FSEL_12_ES2 0x07 +#define MPU_M2_ES2 0x01 + +#define MPU_M_12 0x085 +#define MPU_N_12 0x05 +#define MPU_FSEL_12 0x07 +#define MPU_M2_12 0x01 + +#define MPU_M_13_ES1 0x17D +#define MPU_N_13_ES1 0x0C +#define MPU_FSEL_13_ES1 0x03 +#define MPU_M2_13_ES1 0x01 + +#define MPU_M_13_ES2 0x258 +#define MPU_N_13_ES2 0x0C +#define MPU_FSEL_13_ES2 0x03 +#define MPU_M2_13_ES2 0x01 + +#define MPU_M_13 0x10A +#define MPU_N_13 0x0C +#define MPU_FSEL_13 0x03 +#define MPU_M2_13 0x01 + +#define MPU_M_19P2_ES1 0x179 +#define MPU_N_19P2_ES1 0x12 +#define MPU_FSEL_19P2_ES1 0x04 +#define MPU_M2_19P2_ES1 0x01 + +#define MPU_M_19P2_ES2 0x271 +#define MPU_N_19P2_ES2 0x17 +#define MPU_FSEL_19P2_ES2 0x03 +#define MPU_M2_19P2_ES2 0x01 + +#define MPU_M_19P2 0x14C +#define MPU_N_19P2 0x17 +#define MPU_FSEL_19P2 0x03 +#define MPU_M2_19P2 0x01 + +#define MPU_M_26_ES1 0x17D +#define MPU_N_26_ES1 0x19 +#define MPU_FSEL_26_ES1 0x03 +#define MPU_M2_26_ES1 0x01 + +#define MPU_M_26_ES2 0x0FA +#define MPU_N_26_ES2 0x0C +#define MPU_FSEL_26_ES2 0x07 +#define MPU_M2_26_ES2 0x01 + +#define MPU_M_26 0x085 +#define MPU_N_26 0x0C +#define MPU_FSEL_26 0x07 +#define MPU_M2_26 0x01 + +#define MPU_M_38P4_ES1 0x1FA +#define MPU_N_38P4_ES1 0x32 +#define MPU_FSEL_38P4_ES1 0x03 +#define MPU_M2_38P4_ES1 0x01 + +#define MPU_M_38P4_ES2 0x271 +#define MPU_N_38P4_ES2 0x2F +#define MPU_FSEL_38P4_ES2 0x03 +#define MPU_M2_38P4_ES2 0x01 + +#define MPU_M_38P4 0x14C +#define MPU_N_38P4 0x2F +#define MPU_FSEL_38P4 0x03 +#define MPU_M2_38P4 0x01 + +/* IVA DPLL */ + +#define IVA_M_12_ES1 0x07D +#define IVA_N_12_ES1 0x05 +#define IVA_FSEL_12_ES1 0x07 +#define IVA_M2_12_ES1 0x01 + +#define IVA_M_12_ES2 0x0B4 +#define IVA_N_12_ES2 0x05 +#define IVA_FSEL_12_ES2 0x07 +#define IVA_M2_12_ES2 0x01 + +#define IVA_M_12 0x085 +#define IVA_N_12 0x05 +#define IVA_FSEL_12 0x07 +#define IVA_M2_12 0x01 + +#define IVA_M_13_ES1 0x0FA +#define IVA_N_13_ES1 0x0C +#define IVA_FSEL_13_ES1 0x03 +#define IVA_M2_13_ES1 0x01 + +#define IVA_M_13_ES2 0x168 +#define IVA_N_13_ES2 0x0C +#define IVA_FSEL_13_ES2 0x03 +#define IVA_M2_13_ES2 0x01 + +#define IVA_M_13 0x10A +#define IVA_N_13 0x0C +#define IVA_FSEL_13 0x03 +#define IVA_M2_13 0x01 + +#define IVA_M_19P2_ES1 0x082 +#define IVA_N_19P2_ES1 0x09 +#define IVA_FSEL_19P2_ES1 0x07 +#define IVA_M2_19P2_ES1 0x01 + +#define IVA_M_19P2_ES2 0x0E1 +#define IVA_N_19P2_ES2 0x0B +#define IVA_FSEL_19P2_ES2 0x06 +#define IVA_M2_19P2_ES2 0x01 + +#define IVA_M_19P2 0x14C +#define IVA_N_19P2 0x17 +#define IVA_FSEL_19P2 0x03 +#define IVA_M2_19P2 0x01 + +#define IVA_M_26_ES1 0x07D +#define IVA_N_26_ES1 0x0C +#define IVA_FSEL_26_ES1 0x07 +#define IVA_M2_26_ES1 0x01 + +#define IVA_M_26_ES2 0x0B4 +#define IVA_N_26_ES2 0x0C +#define IVA_FSEL_26_ES2 0x07 +#define IVA_M2_26_ES2 0x01 + +#define IVA_M_26 0x085 +#define IVA_N_26 0x0C +#define IVA_FSEL_26 0x07 +#define IVA_M2_26 0x01 + +#define IVA_M_38P4_ES1 0x13F +#define IVA_N_38P4_ES1 0x30 +#define IVA_FSEL_38P4_ES1 0x03 +#define IVA_M2_38P4_ES1 0x01 + +#define IVA_M_38P4_ES2 0x0E1 +#define IVA_N_38P4_ES2 0x17 +#define IVA_FSEL_38P4_ES2 0x06 +#define IVA_M2_38P4_ES2 0x01 + +#define IVA_M_38P4 0x14C +#define IVA_N_38P4 0x2F +#define IVA_FSEL_38P4 0x03 +#define IVA_M2_38P4 0x01 + +/* CORE DPLL */ + +#define CORE_M_12 0xA6 +#define CORE_N_12 0x05 +#define CORE_FSEL_12 0x07 +#define CORE_M2_12 0x01 /* M3 of 2 */ + +#define CORE_M_12_ES1 0x19F +#define CORE_N_12_ES1 0x0E +#define CORE_FSL_12_ES1 0x03 +#define CORE_M2_12_ES1 0x1 /* M3 of 2 */ + +#define CORE_M_13 0x14C +#define CORE_N_13 0x0C +#define CORE_FSEL_13 0x03 +#define CORE_M2_13 0x01 /* M3 of 2 */ + +#define CORE_M_13_ES1 0x1B2 +#define CORE_N_13_ES1 0x10 +#define CORE_FSL_13_ES1 0x03 +#define CORE_M2_13_ES1 0x01 /* M3 of 2 */ + +#define CORE_M_19P2 0x19F +#define CORE_N_19P2 0x17 +#define CORE_FSEL_19P2 0x03 +#define CORE_M2_19P2 0x01 /* M3 of 2 */ + +#define CORE_M_19P2_ES1 0x19F +#define CORE_N_19P2_ES1 0x17 +#define CORE_FSL_19P2_ES1 0x03 +#define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */ + +#define CORE_M_26 0xA6 +#define CORE_N_26 0x0C +#define CORE_FSEL_26 0x07 +#define CORE_M2_26 0x01 /* M3 of 2 */ + +#define CORE_M_26_ES1 0x1B2 +#define CORE_N_26_ES1 0x21 +#define CORE_FSL_26_ES1 0x03 +#define CORE_M2_26_ES1 0x01 /* M3 of 2 */ + +#define CORE_M_38P4 0x19F +#define CORE_N_38P4 0x2F +#define CORE_FSEL_38P4 0x03 +#define CORE_M2_38P4 0x01 /* M3 of 2 */ + +#define CORE_M_38P4_ES1 0x19F +#define CORE_N_38P4_ES1 0x2F +#define CORE_FSL_38P4_ES1 0x03 +#define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */ + +/* PER DPLL */ + +#define PER_M_12 0xD8 +#define PER_N_12 0x05 +#define PER_FSEL_12 0x07 +#define PER_M2_12 0x09 + +#define PER_M_13 0x1B0 +#define PER_N_13 0x0C +#define PER_FSEL_13 0x03 +#define PER_M2_13 0x09 + +#define PER_M_19P2 0xE1 +#define PER_N_19P2 0x09 +#define PER_FSEL_19P2 0x07 +#define PER_M2_19P2 0x09 + +#define PER_M_26 0xD8 +#define PER_N_26 0x0C +#define PER_FSEL_26 0x07 +#define PER_M2_26 0x09 + +#define PER_M_38P4 0xE1 +#define PER_N_38P4 0x13 +#define PER_FSEL_38P4 0x07 +#define PER_M2_38P4 0x09 + +/* PER2 DPLL */ +#define PER2_M_12 0x78 +#define PER2_N_12 0x0B +#define PER2_FSEL_12 0x03 +#define PER2_M2_12 0x01 + +#define PER2_M_13 0x78 +#define PER2_N_13 0x0C +#define PER2_FSEL_13 0x03 +#define PER2_M2_13 0x01 + +#define PER2_M_19P2 0x2EE +#define PER2_N_19P2 0x0B +#define PER2_FSEL_19P2 0x06 +#define PER2_M2_19P2 0x0A + +#define PER2_M_26 0x78 +#define PER2_N_26 0x0C +#define PER2_FSEL_26 0x03 +#define PER2_M2_26 0x01 + +#define PER2_M_38P4 0x2EE +#define PER2_N_38P4 0x0B +#define PER2_FSEL_38P4 0x06 +#define PER2_M2_38P4 0x0A + +/* 36XX PER DPLL */ + +#define PER_36XX_M_12 0x1B0 +#define PER_36XX_N_12 0x05 +#define PER_36XX_FSEL_12 0x07 +#define PER_36XX_M2_12 0x09 + +#define PER_36XX_M_13 0x360 +#define PER_36XX_N_13 0x0C +#define PER_36XX_FSEL_13 0x03 +#define PER_36XX_M2_13 0x09 + +#define PER_36XX_M_19P2 0x1C2 +#define PER_36XX_N_19P2 0x09 +#define PER_36XX_FSEL_19P2 0x07 +#define PER_36XX_M2_19P2 0x09 + +#define PER_36XX_M_26 0x1B0 +#define PER_36XX_N_26 0x0C +#define PER_36XX_FSEL_26 0x07 +#define PER_36XX_M2_26 0x09 + +#define PER_36XX_M_38P4 0x1C2 +#define PER_36XX_N_38P4 0x13 +#define PER_36XX_FSEL_38P4 0x07 +#define PER_36XX_M2_38P4 0x09 + +/* 36XX PER2 DPLL */ + +#define PER2_36XX_M_12 0x50 +#define PER2_36XX_N_12 0x00 +#define PER2_36XX_M2_12 0x08 + +#define PER2_36XX_M_13 0x1BB +#define PER2_36XX_N_13 0x05 +#define PER2_36XX_M2_13 0x08 + +#define PER2_36XX_M_19P2 0x32 +#define PER2_36XX_N_19P2 0x00 +#define PER2_36XX_M2_19P2 0x08 + +#define PER2_36XX_M_26 0x1BB +#define PER2_36XX_N_26 0x0B +#define PER2_36XX_M2_26 0x08 + +#define PER2_36XX_M_38P4 0x19 +#define PER2_36XX_N_38P4 0x00 +#define PER2_36XX_M2_38P4 0x08 + +#endif /* endif _CLOCKS_OMAP3_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap3/cpu.h b/roms/u-boot/arch/arm/include/asm/arch-omap3/cpu.h new file mode 100644 index 000000000..3f0182e76 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap3/cpu.h @@ -0,0 +1,504 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, + */ + +#ifndef _CPU_H +#define _CPU_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +/* Register offsets of common modules */ +/* Control */ +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct ctrl { + u8 res1[0xC0]; + u16 gpmc_nadv_ale; /* 0xC0 */ + u16 gpmc_noe; /* 0xC2 */ + u16 gpmc_nwe; /* 0xC4 */ + u8 res2[0x22A]; + u32 status; /* 0x2F0 */ + u32 gpstatus; /* 0x2F4 */ + u8 res3[0x08]; + u32 rpubkey_0; /* 0x300 */ + u32 rpubkey_1; /* 0x304 */ + u32 rpubkey_2; /* 0x308 */ + u32 rpubkey_3; /* 0x30C */ + u32 rpubkey_4; /* 0x310 */ + u8 res4[0x04]; + u32 randkey_0; /* 0x318 */ + u32 randkey_1; /* 0x31C */ + u32 randkey_2; /* 0x320 */ + u32 randkey_3; /* 0x324 */ + u8 res5[0x124]; + u32 ctrl_omap_stat; /* 0x44C */ +}; +#else /* __ASSEMBLY__ */ +#define CONTROL_STATUS 0x2F0 +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct ctrl_id { + u8 res1[0x4]; + u32 idcode; /* 0x04 */ + u32 prod_id; /* 0x08 */ + u32 sku_id; /* 0x0c */ + u8 res2[0x08]; + u32 die_id_0; /* 0x18 */ + u32 die_id_1; /* 0x1C */ + u32 die_id_2; /* 0x20 */ + u32 die_id_3; /* 0x24 */ +}; +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +/* boot pin mask */ +#define SYSBOOT_MASK 0x1F + +/* device speed */ +#define SKUID_CLK_MASK 0xf +#define SKUID_CLK_600MHZ 0x0 +#define SKUID_CLK_720MHZ 0x8 + +#define GPMC_BASE (OMAP34XX_GPMC_BASE) +#define GPMC_CONFIG_CS0 0x60 +#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) + +#ifndef __KERNEL_STRICT_NAMES +#ifdef __ASSEMBLY__ +#define GPMC_CONFIG1 0x00 +#define GPMC_CONFIG2 0x04 +#define GPMC_CONFIG3 0x08 +#define GPMC_CONFIG4 0x0C +#define GPMC_CONFIG5 0x10 +#define GPMC_CONFIG6 0x14 +#define GPMC_CONFIG7 0x18 +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +/* GPMC Mapping */ +#define FLASH_BASE 0x10000000 /* NOR flash, */ + /* aligned to 256 Meg */ +#define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */ + /* aligned to 64 Meg */ +#define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */ + /* aligned to 256 Meg */ +#define DEBUG_BASE 0x08000000 /* debug board */ +#define NAND_BASE 0x30000000 /* NAND addr */ + /* (actual size small port) */ +#define ONENAND_MAP 0x20000000 /* OneNand addr */ + /* (actual size small port) */ +/* SMS */ +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct sms { + u8 res1[0x10]; + u32 sysconfig; /* 0x10 */ + u8 res2[0x34]; + u32 rg_att0; /* 0x48 */ + u8 res3[0x84]; + u32 class_arb0; /* 0xD0 */ +}; +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +#define BURSTCOMPLETE_GROUP7 (0x1 << 31) + +/* SDRC */ +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct sdrc_cs { + u32 mcfg; /* 0x80 || 0xB0 */ + u32 mr; /* 0x84 || 0xB4 */ + u8 res1[0x4]; + u32 emr2; /* 0x8C || 0xBC */ + u8 res2[0x14]; + u32 rfr_ctrl; /* 0x84 || 0xD4 */ + u32 manual; /* 0xA8 || 0xD8 */ + u8 res3[0x4]; +}; + +struct sdrc_actim { + u32 ctrla; /* 0x9C || 0xC4 */ + u32 ctrlb; /* 0xA0 || 0xC8 */ +}; + +struct sdrc { + u8 res1[0x10]; + u32 sysconfig; /* 0x10 */ + u32 status; /* 0x14 */ + u8 res2[0x28]; + u32 cs_cfg; /* 0x40 */ + u32 sharing; /* 0x44 */ + u8 res3[0x18]; + u32 dlla_ctrl; /* 0x60 */ + u32 dlla_status; /* 0x64 */ + u32 dllb_ctrl; /* 0x68 */ + u32 dllb_status; /* 0x6C */ + u32 power; /* 0x70 */ + u8 res4[0xC]; + struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */ +}; + +/* EMIF4 */ +typedef struct emif4 { + unsigned int emif_mod_id_rev; + unsigned int sdram_sts; + unsigned int sdram_config; + unsigned int res1; + unsigned int sdram_refresh_ctrl; + unsigned int sdram_refresh_ctrl_shdw; + unsigned int sdram_time1; + unsigned int sdram_time1_shdw; + unsigned int sdram_time2; + unsigned int sdram_time2_shdw; + unsigned int sdram_time3; + unsigned int sdram_time3_shdw; + unsigned char res2[8]; + unsigned int sdram_pwr_mgmt; + unsigned int sdram_pwr_mgmt_shdw; + unsigned char res3[32]; + unsigned int sdram_iodft_tlgc; + unsigned char res4[128]; + unsigned int ddr_phyctrl1; + unsigned int ddr_phyctrl1_shdw; + unsigned int ddr_phyctrl2; +} emif4_t; + +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +#define DLLPHASE_90 (0x1 << 1) +#define LOADDLL (0x1 << 2) +#define ENADLL (0x1 << 3) +#define DLL_DELAY_MASK 0xFF00 +#define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8)) + +#define PAGEPOLICY_HIGH (0x1 << 0) +#define SRFRONRESET (0x1 << 7) +#define PWDNEN (0x1 << 2) +#define WAKEUPPROC (0x1 << 26) + +#define DDR_SDRAM (0x1 << 0) +#define DEEPPD (0x1 << 3) +#define B32NOT16 (0x1 << 4) +#define BANKALLOCATION (0x2 << 6) +#define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */ +#define ADDRMUXLEGACY (0x1 << 19) +#define CASWIDTH_10BITS (0x5 << 20) +#define RASWIDTH_13BITS (0x2 << 24) +#define BURSTLENGTH4 (0x2 << 0) +#define CASL3 (0x3 << 4) +#define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C) +#define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4) +#define ARE_ARCV_1 (0x1 << 0) +#define ARCV (0x4e2 << 8) /* Autorefresh count */ +#define OMAP34XX_SDRC_CS0 0x80000000 +#define OMAP34XX_SDRC_CS1 0xA0000000 +#define CMD_NOP 0x0 +#define CMD_PRECHARGE 0x1 +#define CMD_AUTOREFRESH 0x2 +#define CMD_ENTR_PWRDOWN 0x3 +#define CMD_EXIT_PWRDOWN 0x4 +#define CMD_ENTR_SRFRSH 0x5 +#define CMD_CKE_HIGH 0x6 +#define CMD_CKE_LOW 0x7 +#define SOFTRESET (0x1 << 1) +#define SMART_IDLE (0x2 << 3) +#define REF_ON_IDLE (0x1 << 6) + +/* DMA */ +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct dma4_chan { + u32 ccr; + u32 clnk_ctrl; + u32 cicr; + u32 csr; + u32 csdp; + u32 cen; + u32 cfn; + u32 cssa; + u32 cdsa; + u32 csel; + u32 csfl; + u32 cdel; + u32 cdfl; + u32 csac; + u32 cdac; + u32 ccen; + u32 ccfn; + u32 color; +}; + +struct dma4 { + u32 revision; + u8 res1[0x4]; + u32 irqstatus_l[0x4]; + u32 irqenable_l[0x4]; + u32 sysstatus; + u32 ocp_sysconfig; + u8 res2[0x34]; + u32 caps_0; + u8 res3[0x4]; + u32 caps_2; + u32 caps_3; + u32 caps_4; + u32 gcr; + u8 res4[0x4]; + struct dma4_chan chan[32]; +}; + +#endif /*__ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +/* timer regs offsets (32 bit regs) */ + +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct gptimer { + u32 tidr; /* 0x00 r */ + u8 res[0xc]; + u32 tiocp_cfg; /* 0x10 rw */ + u32 tistat; /* 0x14 r */ + u32 tisr; /* 0x18 rw */ + u32 tier; /* 0x1c rw */ + u32 twer; /* 0x20 rw */ + u32 tclr; /* 0x24 rw */ + u32 tcrr; /* 0x28 rw */ + u32 tldr; /* 0x2c rw */ + u32 ttgr; /* 0x30 rw */ + u32 twpc; /* 0x34 r*/ + u32 tmar; /* 0x38 rw*/ + u32 tcar1; /* 0x3c r */ + u32 tcicr; /* 0x40 rw */ + u32 tcar2; /* 0x44 r */ +}; +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +/* enable sys_clk NO-prescale /1 */ +#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) + +/* Watchdog */ +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct watchdog { + u8 res1[0x34]; + u32 wwps; /* 0x34 r */ + u8 res2[0x10]; + u32 wspr; /* 0x48 rw */ +}; +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* PRCM */ +#define PRCM_BASE 0x48004000 + +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct prcm { + u32 fclken_iva2; /* 0x00 */ + u32 clken_pll_iva2; /* 0x04 */ + u8 res1[0x1c]; + u32 idlest_pll_iva2; /* 0x24 */ + u8 res2[0x18]; + u32 clksel1_pll_iva2 ; /* 0x40 */ + u32 clksel2_pll_iva2; /* 0x44 */ + u8 res3[0x8bc]; + u32 clken_pll_mpu; /* 0x904 */ + u8 res4[0x1c]; + u32 idlest_pll_mpu; /* 0x924 */ + u8 res5[0x18]; + u32 clksel1_pll_mpu; /* 0x940 */ + u32 clksel2_pll_mpu; /* 0x944 */ + u8 res6[0xb8]; + u32 fclken1_core; /* 0xa00 */ + u32 res_fclken2_core; + u32 fclken3_core; /* 0xa08 */ + u8 res7[0x4]; + u32 iclken1_core; /* 0xa10 */ + u32 iclken2_core; /* 0xa14 */ + u32 iclken3_core; /* 0xa18 */ + u8 res8[0x24]; + u32 clksel_core; /* 0xa40 */ + u8 res9[0xbc]; + u32 fclken_gfx; /* 0xb00 */ + u8 res10[0xc]; + u32 iclken_gfx; /* 0xb10 */ + u8 res11[0x2c]; + u32 clksel_gfx; /* 0xb40 */ + u8 res12[0xbc]; + u32 fclken_wkup; /* 0xc00 */ + u8 res13[0xc]; + u32 iclken_wkup; /* 0xc10 */ + u8 res14[0xc]; + u32 idlest_wkup; /* 0xc20 */ + u8 res15[0x1c]; + u32 clksel_wkup; /* 0xc40 */ + u8 res16[0xbc]; + u32 clken_pll; /* 0xd00 */ + u32 clken2_pll; /* 0xd04 */ + u8 res17[0x18]; + u32 idlest_ckgen; /* 0xd20 */ + u32 idlest2_ckgen; /* 0xd24 */ + u8 res18[0x18]; + u32 clksel1_pll; /* 0xd40 */ + u32 clksel2_pll; /* 0xd44 */ + u32 clksel3_pll; /* 0xd48 */ + u32 clksel4_pll; /* 0xd4c */ + u32 clksel5_pll; /* 0xd50 */ + u8 res19[0xac]; + u32 fclken_dss; /* 0xe00 */ + u8 res20[0xc]; + u32 iclken_dss; /* 0xe10 */ + u8 res21[0x2c]; + u32 clksel_dss; /* 0xe40 */ + u8 res22[0xbc]; + u32 fclken_cam; /* 0xf00 */ + u8 res23[0xc]; + u32 iclken_cam; /* 0xf10 */ + u8 res24[0x2c]; + u32 clksel_cam; /* 0xf40 */ + u8 res25[0xbc]; + u32 fclken_per; /* 0x1000 */ + u8 res26[0xc]; + u32 iclken_per; /* 0x1010 */ + u8 res27[0x2c]; + u32 clksel_per; /* 0x1040 */ + u8 res28[0xfc]; + u32 clksel1_emu; /* 0x1140 */ + u8 res29[0x2bc]; + u32 fclken_usbhost; /* 0x1400 */ + u8 res30[0xc]; + u32 iclken_usbhost; /* 0x1410 */ +}; +#else /* __ASSEMBLY__ */ +#define CM_CLKSEL_CORE 0x48004a40 +#define CM_CLKSEL_GFX 0x48004b40 +#define CM_CLKSEL_WKUP 0x48004c40 +#define CM_CLKEN_PLL 0x48004d00 +#define CM_CLKSEL1_PLL 0x48004d40 +#define CM_CLKSEL1_EMU 0x48005140 +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +#define PRM_BASE 0x48306000 + +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct prm { + u8 res1[0xd40]; + u32 clksel; /* 0xd40 */ + u8 res2[0x50c]; + u32 rstctrl; /* 0x1250 */ + u8 res3[0x1c]; + u32 clksrc_ctrl; /* 0x1270 */ +}; +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +#define PRM_RSTCTRL 0x48307250 +#define PRM_RSTCTRL_RESET 0x04 +#define PRM_RSTST 0x48307258 +#define PRM_RSTST_WARM_RESET_MASK 0x7D2 +#define SYSCLKDIV_1 (0x1 << 6) +#define SYSCLKDIV_2 (0x1 << 7) + +#define CLKSEL_GPT1 (0x1 << 0) + +#define EN_GPT1 (0x1 << 0) +#define EN_32KSYNC (0x1 << 2) + +#define ST_WDT2 (0x1 << 5) + +#define ST_MPU_CLK (0x1 << 0) + +#define ST_CORE_CLK (0x1 << 0) + +#define ST_PERIPH_CLK (0x1 << 1) + +#define ST_IVA2_CLK (0x1 << 0) + +#define RESETDONE (0x1 << 0) + +#define TCLR_ST (0x1 << 0) +#define TCLR_AR (0x1 << 1) +#define TCLR_PRE (0x1 << 5) + +/* SMX-APE */ +#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) +#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) +#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) +#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) + +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct pm { + u8 res1[0x48]; + u32 req_info_permission_0; /* 0x48 */ + u8 res2[0x4]; + u32 read_permission_0; /* 0x50 */ + u8 res3[0x4]; + u32 wirte_permission_0; /* 0x58 */ + u8 res4[0x4]; + u32 addr_match_1; /* 0x58 */ + u8 res5[0x4]; + u32 req_info_permission_1; /* 0x68 */ + u8 res6[0x14]; + u32 addr_match_2; /* 0x80 */ +}; +#endif /*__ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +/* Permission values for registers -Full fledged permissions to all */ +#define UNLOCK_1 0xFFFFFFFF +#define UNLOCK_2 0x00000000 +#define UNLOCK_3 0x0000FFFF + +#define NOT_EARLY 0 + +/* I2C base */ +#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000) +#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) +#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) + +/* MUSB base */ +#define MUSB_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000) + +/* OMAP3 GPIO registers */ +#define OMAP_GPIO_REVISION 0x0000 +#define OMAP_GPIO_SYSCONFIG 0x0010 +#define OMAP_GPIO_SYSSTATUS 0x0014 +#define OMAP_GPIO_IRQSTATUS1 0x0018 +#define OMAP_GPIO_IRQSTATUS2 0x0028 +#define OMAP_GPIO_IRQENABLE2 0x002c +#define OMAP_GPIO_IRQENABLE1 0x001c +#define OMAP_GPIO_WAKE_EN 0x0020 +#define OMAP_GPIO_CTRL 0x0030 +#define OMAP_GPIO_OE 0x0034 +#define OMAP_GPIO_DATAIN 0x0038 +#define OMAP_GPIO_DATAOUT 0x003c +#define OMAP_GPIO_LEVELDETECT0 0x0040 +#define OMAP_GPIO_LEVELDETECT1 0x0044 +#define OMAP_GPIO_RISINGDETECT 0x0048 +#define OMAP_GPIO_FALLINGDETECT 0x004c +#define OMAP_GPIO_DEBOUNCE_EN 0x0050 +#define OMAP_GPIO_DEBOUNCE_VAL 0x0054 +#define OMAP_GPIO_CLEARIRQENABLE1 0x0060 +#define OMAP_GPIO_SETIRQENABLE1 0x0064 +#define OMAP_GPIO_CLEARWKUENA 0x0080 +#define OMAP_GPIO_SETWKUENA 0x0084 +#define OMAP_GPIO_CLEARDATAOUT 0x0090 +#define OMAP_GPIO_SETDATAOUT 0x0094 + +#endif /* _CPU_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap3/dma.h b/roms/u-boot/arch/arm/include/asm/arch-omap3/dma.h new file mode 100644 index 000000000..d26e490d2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap3/dma.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef __SDMA_H +#define __SDMA_H + +/* Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz + */ + +/* Functions */ +void omap3_dma_init(void); +int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst, + uint32_t sze); +int omap3_dma_start_transfer(uint32_t chan); +int omap3_dma_wait_for_transfer(uint32_t chan); +int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config); +int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config); + +/* Register settings */ +#define CSDP_DATA_TYPE_8BIT 0x0 +#define CSDP_DATA_TYPE_16BIT 0x1 +#define CSDP_DATA_TYPE_32BIT 0x2 +#define CSDP_SRC_BURST_SINGLE (0x0 << 7) +#define CSDP_SRC_BURST_EN_16BYTES (0x1 << 7) +#define CSDP_SRC_BURST_EN_32BYTES (0x2 << 7) +#define CSDP_SRC_BURST_EN_64BYTES (0x3 << 7) +#define CSDP_DST_BURST_SINGLE (0x0 << 14) +#define CSDP_DST_BURST_EN_16BYTES (0x1 << 14) +#define CSDP_DST_BURST_EN_32BYTES (0x2 << 14) +#define CSDP_DST_BURST_EN_64BYTES (0x3 << 14) +#define CSDP_DST_ENDIAN_LOCK_ADAPT (0x0 << 18) +#define CSDP_DST_ENDIAN_LOCK_LOCK (0x1 << 18) +#define CSDP_DST_ENDIAN_LITTLE (0x0 << 19) +#define CSDP_DST_ENDIAN_BIG (0x1 << 19) +#define CSDP_SRC_ENDIAN_LOCK_ADAPT (0x0 << 20) +#define CSDP_SRC_ENDIAN_LOCK_LOCK (0x1 << 20) +#define CSDP_SRC_ENDIAN_LITTLE (0x0 << 21) +#define CSDP_SRC_ENDIAN_BIG (0x1 << 21) + +#define CCR_READ_PRIORITY_LOW (0x0 << 6) +#define CCR_READ_PRIORITY_HIGH (0x1 << 6) +#define CCR_ENABLE_DISABLED (0x0 << 7) +#define CCR_ENABLE_ENABLE (0x1 << 7) +#define CCR_SRC_AMODE_CONSTANT (0x0 << 12) +#define CCR_SRC_AMODE_POST_INC (0x1 << 12) +#define CCR_SRC_AMODE_SINGLE_IDX (0x2 << 12) +#define CCR_SRC_AMODE_DOUBLE_IDX (0x3 << 12) +#define CCR_DST_AMODE_CONSTANT (0x0 << 14) +#define CCR_DST_AMODE_POST_INC (0x1 << 14) +#define CCR_DST_AMODE_SINGLE_IDX (0x2 << 14) +#define CCR_DST_AMODE_SOUBLE_IDX (0x3 << 14) + +#define CCR_RD_ACTIVE_MASK (1 << 9) +#define CCR_WR_ACTIVE_MASK (1 << 10) + +#define CSR_TRANS_ERR (1 << 8) +#define CSR_SUPERVISOR_ERR (1 << 10) +#define CSR_MISALIGNED_ADRS_ERR (1 << 11) + +/* others */ +#define CHAN_NR_MIN 0 +#define CHAN_NR_MAX 31 + +#endif /* __SDMA_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap3/dss.h b/roms/u-boot/arch/arm/include/asm/arch-omap3/dss.h new file mode 100644 index 000000000..8bf6b4895 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap3/dss.h @@ -0,0 +1,233 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, + * Syed Mohammed Khasim + * + * Referred to Linux Kernel DSS driver files for OMAP3 by + * Tomi Valkeinen from drivers/video/omap2/dss/ + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 and any + * later version the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef DSS_H +#define DSS_H + +/* DSS Base Registers */ +#define OMAP3_DSS_BASE 0x48050000 +#define OMAP3_DISPC_BASE 0x48050400 +#define OMAP3_VENC_BASE 0x48050C00 + +/* DSS Registers */ +struct dss_regs { + u32 revision; /* 0x00 */ + u8 res1[12]; /* 0x04 */ + u32 sysconfig; /* 0x10 */ + u32 sysstatus; /* 0x14 */ + u32 irqstatus; /* 0x18 */ + u8 res2[36]; /* 0x1C */ + u32 control; /* 0x40 */ + u32 sdi_control; /* 0x44 */ + u32 pll_control; /* 0x48 */ +}; + +/* DISPC Registers */ +struct dispc_regs { + u32 revision; /* 0x00 */ + u8 res1[12]; /* 0x04 */ + u32 sysconfig; /* 0x10 */ + u32 sysstatus; /* 0x14 */ + u32 irqstatus; /* 0x18 */ + u32 irqenable; /* 0x1C */ + u8 res2[32]; /* 0x20 */ + u32 control; /* 0x40 */ + u32 config; /* 0x44 */ + u32 reserve_2; /* 0x48 */ + u32 default_color0; /* 0x4C */ + u32 default_color1; /* 0x50 */ + u32 trans_color0; /* 0x54 */ + u32 trans_color1; /* 0x58 */ + u32 line_status; /* 0x5C */ + u32 line_number; /* 0x60 */ + u32 timing_h; /* 0x64 */ + u32 timing_v; /* 0x68 */ + u32 pol_freq; /* 0x6C */ + u32 divisor; /* 0x70 */ + u32 global_alpha; /* 0x74 */ + u32 size_dig; /* 0x78 */ + u32 size_lcd; /* 0x7C */ + u32 gfx_ba0; /* 0x80 */ + u32 gfx_ba1; /* 0x84 */ + u32 gfx_position; /* 0x88 */ + u32 gfx_size; /* 0x8C */ + u8 unused[16]; /* 0x90 */ + u32 gfx_attributes; /* 0xA0 */ + u32 gfx_fifo_threshold; /* 0xA4 */ + u32 gfx_fifo_size_status; /* 0xA8 */ + u32 gfx_row_inc; /* 0xAC */ + u32 gfx_pixel_inc; /* 0xB0 */ + u32 gfx_window_skip; /* 0xB4 */ + u32 gfx_table_ba; /* 0xB8 */ +}; + +/* VENC Registers */ +struct venc_regs { + u32 rev_id; /* 0x00 */ + u32 status; /* 0x04 */ + u32 f_control; /* 0x08 */ + u32 reserve_1; /* 0x0C */ + u32 vidout_ctrl; /* 0x10 */ + u32 sync_ctrl; /* 0x14 */ + u32 reserve_2; /* 0x18 */ + u32 llen; /* 0x1C */ + u32 flens; /* 0x20 */ + u32 hfltr_ctrl; /* 0x24 */ + u32 cc_carr_wss_carr; /* 0x28 */ + u32 c_phase; /* 0x2C */ + u32 gain_u; /* 0x30 */ + u32 gain_v; /* 0x34 */ + u32 gain_y; /* 0x38 */ + u32 black_level; /* 0x3C */ + u32 blank_level; /* 0x40 */ + u32 x_color; /* 0x44 */ + u32 m_control; /* 0x48 */ + u32 bstamp_wss_data; /* 0x4C */ + u32 s_carr; /* 0x50 */ + u32 line21; /* 0x54 */ + u32 ln_sel; /* 0x58 */ + u32 l21__wc_ctl; /* 0x5C */ + u32 htrigger_vtrigger; /* 0x60 */ + u32 savid__eavid; /* 0x64 */ + u32 flen__fal; /* 0x68 */ + u32 lal__phase_reset; /* 0x6C */ + u32 hs_int_start_stop_x; /* 0x70 */ + u32 hs_ext_start_stop_x; /* 0x74 */ + u32 vs_int_start_x; /* 0x78 */ + u32 vs_int_stop_x__vs_int_start_y; /* 0x7C */ + u32 vs_int_stop_y__vs_ext_start_x; /* 0x80 */ + u32 vs_ext_stop_x__vs_ext_start_y; /* 0x84 */ + u32 vs_ext_stop_y; /* 0x88 */ + u32 reserve_3; /* 0x8C */ + u32 avid_start_stop_x; /* 0x90 */ + u32 avid_start_stop_y; /* 0x94 */ + u32 reserve_4; /* 0x98 */ + u32 reserve_5; /* 0x9C */ + u32 fid_int_start_x__fid_int_start_y; /* 0xA0 */ + u32 fid_int_offset_y__fid_ext_start_x; /* 0xA4 */ + u32 fid_ext_start_y__fid_ext_offset_y; /* 0xA8 */ + u32 reserve_6; /* 0xAC */ + u32 tvdetgp_int_start_stop_x; /* 0xB0 */ + u32 tvdetgp_int_start_stop_y; /* 0xB4 */ + u32 gen_ctrl; /* 0xB8 */ + u32 reserve_7; /* 0xBC */ + u32 reserve_8; /* 0xC0 */ + u32 output_control; /* 0xC4 */ + u32 dac_b__dac_c; /* 0xC8 */ + u32 height_width; /* 0xCC */ +}; + +/* Few Register Offsets */ +#define TFTSTN_SHIFT 3 +#define DATALINES_SHIFT 8 + +#define GFX_ENABLE 1 +#define GFX_FORMAT_SHIFT 1 +#define LOADMODE_SHIFT 1 + +#define DSS_SOFTRESET (1 << 1) +#define DSS_RESETDONE 1 + +/* Enabling Display controller */ +#define LCD_ENABLE 1 +#define DIG_ENABLE (1 << 1) +#define GO_LCD (1 << 5) +#define GO_DIG (1 << 6) +#define GP_OUT0 (1 << 15) +#define GP_OUT1 (1 << 16) + +/* Configure VENC DSS Params */ +#define VENC_CLK_ENABLE (1 << 3) +#define DAC_DEMEN (1 << 4) +#define DAC_POWERDN (1 << 5) +#define VENC_OUT_SEL (1 << 6) +#define DIG_LPP_SHIFT 16 + +/* LCD display type */ +#define PASSIVE_DISPLAY 0 +#define ACTIVE_DISPLAY 1 + +/* TFTDATALINES */ +#define LCD_INTERFACE_12_BIT 0 +#define LCD_INTERFACE_16_BIT 1 +#define LCD_INTERFACE_18_BIT 2 +#define LCD_INTERFACE_24_BIT 3 + +/* Polarity */ +#define DSS_IVS (1 << 12) +#define DSS_IHS (1 << 13) +#define DSS_IPC (1 << 14) +#define DSS_IEO (1 << 15) +#define DSS_ONOFF (1 << 17) + +/* GFX format */ +#define GFXFORMAT_BITMAP1 (0x0 << 1) +#define GFXFORMAT_BITMAP2 (0x1 << 1) +#define GFXFORMAT_BITMAP4 (0x2 << 1) +#define GFXFORMAT_BITMAP8 (0x3 << 1) +#define GFXFORMAT_RGB12 (0x4 << 1) +#define GFXFORMAT_ARGB16 (0x5 << 1) +#define GFXFORMAT_RGB16 (0x6 << 1) +#define GFXFORMAT_RGB24_UNPACKED (0x8 << 1) +#define GFXFORMAT_RGB24_PACKED (0x9 << 1) +#define GFXFORMAT_ARGB32 (0xC << 1) +#define GFXFORMAT_RGBA32 (0xD << 1) +#define GFXFORMAT_RGBx32 (0xE << 1) + +/* Panel Configuration */ +struct panel_config { + u32 timing_h; + u32 timing_v; + u32 pol_freq; + u32 divisor; + u32 lcd_size; + u32 panel_type; + u32 data_lines; + u32 load_mode; + u32 panel_color; + u32 gfx_format; + void *frame_buffer; +}; + +#define DSS_HBP(bp) (((bp) - 1) << 20) +#define DSS_HFP(fp) (((fp) - 1) << 8) +#define DSS_HSW(sw) ((sw) - 1) +#define DSS_VBP(bp) ((bp) << 20) +#define DSS_VFP(fp) ((fp) << 8) +#define DSS_VSW(sw) ((sw) - 1) + +#define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw)) +#define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw)) +#define PANEL_LCD_SIZE(xres, yres) ((yres - 1) << 16 | (xres - 1)) + +/* Generic DSS Functions */ +void omap3_dss_venc_config(const struct venc_regs *venc_cfg, + u32 height, u32 width); +void omap3_dss_panel_config(const struct panel_config *panel_cfg); +void omap3_dss_enable(void); + +#endif /* DSS_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap3/ehci.h b/roms/u-boot/arch/arm/include/asm/arch-omap3/ehci.h new file mode 100644 index 000000000..fa839ef80 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap3/ehci.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 + * Alexander Holler + * + * Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37 + * + * See there for additional Copyrights. + */ +#ifndef _OMAP3_EHCI_H_ +#define _OMAP3_EHCI_H_ + +/* USB/EHCI registers */ +#define OMAP_USBTLL_BASE 0x48062000UL +#define OMAP_UHH_BASE 0x48064000UL +#define OMAP_EHCI_BASE 0x48064800UL + +/* TLL Register Set */ +#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) +#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) +#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) +#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) +#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1 + +/* UHH Register Set */ +#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1) +#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8) +#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3) +#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2) +#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12) +#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2) + +#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_CACTIVITY | \ + OMAP_UHH_SYSCONFIG_SIDLEMODE | \ + OMAP_UHH_SYSCONFIG_ENAWAKEUP | \ + OMAP_UHH_SYSCONFIG_MIDLEMODE) + +#endif /* _OMAP3_EHCI_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap3/emac_defs.h b/roms/u-boot/arch/arm/include/asm/arch-omap3/emac_defs.h new file mode 100644 index 000000000..0f4b93499 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap3/emac_defs.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Based on: + * + * ---------------------------------------------------------------------------- + * + * dm644x_emac.h + * + * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM + * + * Copyright (C) 2005 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + * Modifications: + * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot. + */ + +#ifndef _AM3517_EMAC_H_ +#define _AM3517_EMAC_H_ + +#define EMAC_BASE_ADDR 0x5C010000 +#define EMAC_WRAPPER_BASE_ADDR 0x5C000000 +#define EMAC_WRAPPER_RAM_ADDR 0x5C020000 +#define EMAC_MDIO_BASE_ADDR 0x5C030000 +#define EMAC_HW_RAM_ADDR 0x01E20000 + +#define EMAC_MDIO_BUS_FREQ 166000000 /* 166 MHZ check */ +#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 2.0 MHz */ + +/* SOFTRESET macro definition interferes with emac_regs structure definition */ +#undef SOFTRESET + +typedef volatile unsigned int dv_reg; +typedef volatile unsigned int *dv_reg_p; + +#define DAVINCI_EMAC_VERSION2 + +#endif /* _AM3517_EMAC_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap3/emif4.h b/roms/u-boot/arch/arm/include/asm/arch-omap3/emif4.h new file mode 100644 index 000000000..bac43b231 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap3/emif4.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Auther: + * Vaibhav Hiremath + * + * Copyright (C) 2010 + * Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef _EMIF_H_ +#define _EMIF_H_ + +/* + * Configuration values + */ +#define EMIF4_TIM1_T_RP (0x3 << 25) +#define EMIF4_TIM1_T_RCD (0x3 << 21) +#define EMIF4_TIM1_T_WR (0x3 << 17) +#define EMIF4_TIM1_T_RAS (0x8 << 12) +#define EMIF4_TIM1_T_RC (0xA << 6) +#define EMIF4_TIM1_T_RRD (0x2 << 3) +#define EMIF4_TIM1_T_WTR (0x2) + +#define EMIF4_TIM2_T_XP (0x2 << 28) +#define EMIF4_TIM2_T_ODT (0x0 << 25) +#define EMIF4_TIM2_T_XSNR (0x1C << 16) +#define EMIF4_TIM2_T_XSRD (0xC8 << 6) +#define EMIF4_TIM2_T_RTP (0x1 << 3) +#define EMIF4_TIM2_T_CKE (0x2) + +#define EMIF4_TIM3_T_RFC (0x25 << 4) +#define EMIF4_TIM3_T_RAS_MAX (0x7) + +#define EMIF4_PWR_IDLE_MODE (0x2 << 30) +#define EMIF4_PWR_DPD_DIS (0x0 << 10) +#define EMIF4_PWR_DPD_EN (0x1 << 10) +#define EMIF4_PWR_LP_MODE (0x0 << 8) +#define EMIF4_PWR_PM_TIM (0x0) + +#define EMIF4_INITREF_DIS (0x0 << 31) +#define EMIF4_REFRESH_RATE (0x50F) + +#define EMIF4_CFG_SDRAM_TYP (0x2 << 29) +#define EMIF4_CFG_IBANK_POS (0x0 << 27) +#define EMIF4_CFG_DDR_TERM (0x0 << 24) +#define EMIF4_CFG_DDR2_DDQS (0x1 << 23) +#define EMIF4_CFG_DDR_DIS_DLL (0x0 << 20) +#define EMIF4_CFG_SDR_DRV (0x0 << 18) +#define EMIF4_CFG_NARROW_MD (0x0 << 14) +#define EMIF4_CFG_CL (0x5 << 10) +#define EMIF4_CFG_ROWSIZE (0x0 << 7) +#define EMIF4_CFG_IBANK (0x3 << 4) +#define EMIF4_CFG_EBANK (0x0 << 3) +#define EMIF4_CFG_PGSIZE (0x2) + +/* + * EMIF4 PHY Control 1 register configuration + */ +#define EMIF4_DDR1_EXT_STRB_EN (0x1 << 7) +#define EMIF4_DDR1_EXT_STRB_DIS (0x0 << 7) +#define EMIF4_DDR1_PWRDN_DIS (0x0 << 6) +#define EMIF4_DDR1_PWRDN_EN (0x1 << 6) +#define EMIF4_DDR1_READ_LAT (0x6 << 0) + +#endif /* endif _EMIF_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap3/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-omap3/gpio.h new file mode 100644 index 000000000..ee092f929 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap3/gpio.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This work is derived from the linux 2.6.27 kernel source + * To fetch, use the kernel repository + * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git + * Use the v2.6.27 tag. + * + * Below is the original's header including its copyright + * + * linux/arch/arm/plat-omap/gpio.c + * + * Support functions for OMAP GPIO + * + * Copyright (C) 2003-2005 Nokia Corporation + * Written by Juha Yrjölä + */ +#ifndef _GPIO_OMAP3_H +#define _GPIO_OMAP3_H + +#include + +#define OMAP_MAX_GPIO 192 + +#define OMAP34XX_GPIO1_BASE 0x48310000 +#define OMAP34XX_GPIO2_BASE 0x49050000 +#define OMAP34XX_GPIO3_BASE 0x49052000 +#define OMAP34XX_GPIO4_BASE 0x49054000 +#define OMAP34XX_GPIO5_BASE 0x49056000 +#define OMAP34XX_GPIO6_BASE 0x49058000 + +#endif /* _GPIO_OMAP3_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap3/i2c.h b/roms/u-boot/arch/arm/include/asm/arch-omap3/i2c.h new file mode 100644 index 000000000..b04c01265 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap3/i2c.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2004-2008 + * Texas Instruments, + */ +#ifndef _OMAP3_I2C_H_ +#define _OMAP3_I2C_H_ + +#define I2C_DEFAULT_BASE I2C_BASE1 + +#endif /* _OMAP3_I2C_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap3/mem.h b/roms/u-boot/arch/arm/include/asm/arch-omap3/mem.h new file mode 100644 index 000000000..7adc134a7 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap3/mem.h @@ -0,0 +1,488 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, + * Richard Woodruff + */ + +#ifndef _MEM_H_ +#define _MEM_H_ + +#define CS0 0x0 +#define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */ + +#ifndef __ASSEMBLY__ +enum { + STACKED = 0, + IP_DDR = 1, + COMBO_DDR = 2, + IP_SDR = 3, +}; +#endif /* __ASSEMBLY__ */ + +#define EARLY_INIT 1 + +/* + * For a full explanation of these registers and values please see + * the Technical Reference Manual (TRM) for any of the processors in + * this family. + */ + +/* Slower full frequency range default timings for x32 operation*/ +#define SDRC_SHARING 0x00000100 +#define SDRC_MR_0_SDR 0x00000031 + +/* + * SDRC autorefresh control values. This register consists of autorefresh + * enable at bits 0:1 and an autorefresh counter value in bits 8:23. The + * counter is a result of ( tREFI / tCK ) - 50. + */ +#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01 +#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */ +#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ +#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */ + +#define DLL_OFFSET 0 +#define DLL_WRITEDDRCLKX2DIS 1 +#define DLL_ENADLL 1 +#define DLL_LOCKDLL 0 +#define DLL_DLLPHASE_72 0 +#define DLL_DLLPHASE_90 1 + +/* rkw - need to find of 90/72 degree recommendation for speed like before */ +#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ + (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) + +/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */ +#define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */ +#define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */ +#define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */ +#define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */ +#define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */ +#define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */ +#define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */ +#define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */ + +#define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal) \ + ACTIM_CTRLA_TRFC(trfc) | \ + ACTIM_CTRLA_TRC(trc) | \ + ACTIM_CTRLA_TRAS(tras) | \ + ACTIM_CTRLA_TRP(trp) | \ + ACTIM_CTRLA_TRCD(trcd) | \ + ACTIM_CTRLA_TRRD(trrd) | \ + ACTIM_CTRLA_TDPL(tdpl) | \ + ACTIM_CTRLA_TDAL(tdal) + +/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */ +#define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */ +#define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */ +#define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */ +#define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */ + +#define ACTIM_CTRLB(twtr, tcke, txp, txsr) \ + ACTIM_CTRLB_TWTR(twtr) | \ + ACTIM_CTRLB_TCKE(tcke) | \ + ACTIM_CTRLB_TXP(txp) | \ + ACTIM_CTRLB_TXSR(txsr) + +/* + * Values used in the MCFG register. Only values we use today + * are defined and the rest can be found in the TRM. Unless otherwise + * noted all fields are one bit. + */ +#define V_MCFG_RAMTYPE_DDR (0x1) +#define V_MCFG_DEEPPD_EN (0x1 << 3) +#define V_MCFG_B32NOT16_32 (0x1 << 4) +#define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */ +#define V_MCFG_RAMSIZE(ramsize) ((((ramsize) >> 20)/2) << 8) /* 8:17 */ +#define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19) +#define V_MCFG_CASWIDTH(caswidth) (((caswidth)-5) << 20) /* 20:22 */ +#define V_MCFG_CASWIDTH_10B V_MCFG_CASWIDTH(10) +#define V_MCFG_RASWIDTH(raswidth) (((raswidth)-11) << 24) /* 24:26 */ + +/* Macro to construct MCFG */ +#define MCFG(ramsize, raswidth) \ + V_MCFG_RASWIDTH(raswidth) | V_MCFG_CASWIDTH_10B | \ + V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(ramsize) | \ + V_MCFG_BANKALLOCATION_RBC | V_MCFG_B32NOT16_32 | \ + V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR + +/* Hynix part of Overo (165MHz optimized) 6.06ns */ +#define HYNIX_TDAL_165 6 +#define HYNIX_TDPL_165 3 +#define HYNIX_TRRD_165 2 +#define HYNIX_TRCD_165 3 +#define HYNIX_TRP_165 3 +#define HYNIX_TRAS_165 7 +#define HYNIX_TRC_165 10 +#define HYNIX_TRFC_165 21 +#define HYNIX_V_ACTIMA_165 \ + ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165, \ + HYNIX_TRAS_165, HYNIX_TRP_165, \ + HYNIX_TRCD_165, HYNIX_TRRD_165, \ + HYNIX_TDPL_165, HYNIX_TDAL_165) + +#define HYNIX_TWTR_165 1 +#define HYNIX_TCKE_165 1 +#define HYNIX_TXP_165 2 +#define HYNIX_XSR_165 24 +#define HYNIX_V_ACTIMB_165 \ + ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165, \ + HYNIX_TXP_165, HYNIX_XSR_165) + +#define HYNIX_RASWIDTH_165 13 +#define HYNIX_V_MCFG_165(size) MCFG((size), HYNIX_RASWIDTH_165) + +/* Hynix part of AM/DM37xEVM (200MHz optimized) */ +#define HYNIX_TDAL_200 6 +#define HYNIX_TDPL_200 3 +#define HYNIX_TRRD_200 2 +#define HYNIX_TRCD_200 4 +#define HYNIX_TRP_200 3 +#define HYNIX_TRAS_200 8 +#define HYNIX_TRC_200 11 +#define HYNIX_TRFC_200 18 +#define HYNIX_V_ACTIMA_200 \ + ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \ + HYNIX_TRAS_200, HYNIX_TRP_200, \ + HYNIX_TRCD_200, HYNIX_TRRD_200, \ + HYNIX_TDPL_200, HYNIX_TDAL_200) + +#define HYNIX_TWTR_200 2 +#define HYNIX_TCKE_200 1 +#define HYNIX_TXP_200 1 +#define HYNIX_XSR_200 28 +#define HYNIX_V_ACTIMB_200 \ + ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \ + HYNIX_TXP_200, HYNIX_XSR_200) + +#define HYNIX_RASWIDTH_200 14 +#define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200) + +/* Infineon part of 3430SDP (165MHz optimized) 6.06ns */ +#define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */ + /* 15/6 + 18/6 = 5.5 -> 6 */ +#define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ +#define INFINEON_TRRD_165 2 /* 12/6 = 2 */ +#define INFINEON_TRCD_165 3 /* 18/6 = 3 */ +#define INFINEON_TRP_165 3 /* 18/6 = 3 */ +#define INFINEON_TRAS_165 7 /* 42/6 = 7 */ +#define INFINEON_TRC_165 10 /* 60/6 = 10 */ +#define INFINEON_TRFC_165 12 /* 72/6 = 12 */ + +#define INFINEON_V_ACTIMA_165 \ + ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \ + INFINEON_TRAS_165, INFINEON_TRP_165, \ + INFINEON_TRCD_165, INFINEON_TRRD_165, \ + INFINEON_TDPL_165, INFINEON_TDAL_165) + +#define INFINEON_TWTR_165 1 +#define INFINEON_TCKE_165 2 +#define INFINEON_TXP_165 2 +#define INFINEON_XSR_165 20 /* 120/6 = 20 */ + +#define INFINEON_V_ACTIMB_165 \ + ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \ + INFINEON_TXP_165, INFINEON_XSR_165) + +/* Micron part of 3430 EVM (165MHz optimized) 6.06ns */ +#define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */ + /* 15/6 + 18/6 = 5.5 -> 6 */ +#define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ +#define MICRON_TRRD_165 2 /* 12/6 = 2 */ +#define MICRON_TRCD_165 3 /* 18/6 = 3 */ +#define MICRON_TRP_165 3 /* 18/6 = 3 */ +#define MICRON_TRAS_165 7 /* 42/6 = 7 */ +#define MICRON_TRC_165 10 /* 60/6 = 10 */ +#define MICRON_TRFC_165 21 /* 125/6 = 21 */ + +#define MICRON_V_ACTIMA_165 \ + ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \ + MICRON_TRAS_165, MICRON_TRP_165, \ + MICRON_TRCD_165, MICRON_TRRD_165, \ + MICRON_TDPL_165, MICRON_TDAL_165) + +#define MICRON_TWTR_165 1 +#define MICRON_TCKE_165 1 +#define MICRON_XSR_165 23 /* 138/6 = 23 */ +#define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */ + +#define MICRON_V_ACTIMB_165 \ + ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \ + MICRON_TXP_165, MICRON_XSR_165) + +#define MICRON_RASWIDTH_165 13 +#define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165) + +#define MICRON_BL_165 0x2 +#define MICRON_SIL_165 0x0 +#define MICRON_CASL_165 0x3 +#define MICRON_WBST_165 0x0 +#define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \ + (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \ + (MICRON_BL_165)) + +/* Micron part (200MHz optimized) 5 ns */ +#define MICRON_TDAL_200 6 +#define MICRON_TDPL_200 3 +#define MICRON_TRRD_200 2 +#define MICRON_TRCD_200 3 +#define MICRON_TRP_200 3 +#define MICRON_TRAS_200 8 +#define MICRON_TRC_200 11 +#define MICRON_TRFC_200 15 +#define MICRON_V_ACTIMA_200 \ + ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \ + MICRON_TRAS_200, MICRON_TRP_200, \ + MICRON_TRCD_200, MICRON_TRRD_200, \ + MICRON_TDPL_200, MICRON_TDAL_200) + +#define MICRON_TWTR_200 2 +#define MICRON_TCKE_200 4 +#define MICRON_TXP_200 2 +#define MICRON_XSR_200 23 +#define MICRON_V_ACTIMB_200 \ + ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \ + MICRON_TXP_200, MICRON_XSR_200) + +#define MICRON_RASWIDTH_200 14 +#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200) + +/* Samsung K4X51163PG - FGC6 (165MHz optimized) 6.06ns - from 2010.90 src */ +#define SAMSUNG_TDAL_165 5 +#define SAMSUNG_TDPL_165 2 +#define SAMSUNG_TRRD_165 2 +#define SAMSUNG_TRCD_165 3 +#define SAMSUNG_TRP_165 3 +#define SAMSUNG_TRAS_165 7 +#define SAMSUNG_TRC_165 10 +#define SAMSUNG_TRFC_165 12 + +#define SAMSUNG_V_ACTIMA_165 \ + ACTIM_CTRLA(SAMSUNG_TRFC_165, SAMSUNG_TRC_165, \ + SAMSUNG_TRAS_165, SAMSUNG_TRP_165, \ + SAMSUNG_TRCD_165, SAMSUNG_TRRD_165, \ + SAMSUNG_TDPL_165, SAMSUNG_TDAL_165) + +#define SAMSUNG_TWTR_165 1 +#define SAMSUNG_TCKE_165 2 +#define SAMSUNG_XSR_165 20 +#define SAMSUNG_TXP_165 5 + +#define SAMSUNG_V_ACTIMB_165 \ + ACTIM_CTRLB(SAMSUNG_TWTR_165, SAMSUNG_TCKE_165, \ + SAMSUNG_TXP_165, SAMSUNG_XSR_165) + +#define SAMSUNG_RASWIDTH_165 14 +#define SAMSUNG_V_MCFG_165(size) \ + V_MCFG_RASWIDTH(SAMSUNG_RASWIDTH_165) | V_MCFG_CASWIDTH_10B | \ + V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(size) | \ + V_MCFG_BANKALLOCATION_RBC | V_MCFG_RAMTYPE_DDR + +/* TODO: find which register these were taken from */ + +#define SAMSUNG_BL_165 0x2 +#define SAMSUNG_SIL_165 0x0 +#define SAMSUNG_CASL_165 0x3 +#define SAMSUNG_WBST_165 0x0 +#define SAMSUNG_V_MR_165 ((SAMSUNG_WBST_165 << 9) | \ + (SAMSUNG_CASL_165 << 4) | (SAMSUNG_SIL_165 << 3) | \ + (SAMSUNG_BL_165)) + +#define SAMSUNG_SHARING 0x00003700 + +/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */ +#define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */ + /* 15/6 + 18/6 = 5.5 -> 6 */ +#define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ +#define NUMONYX_TRRD_165 2 /* 12/6 = 2 */ +#define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */ +#define NUMONYX_TRP_165 3 /* 18/6 = 3 */ +#define NUMONYX_TRAS_165 7 /* 42/6 = 7 */ +#define NUMONYX_TRC_165 10 /* 60/6 = 10 */ +#define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */ + +#define NUMONYX_V_ACTIMA_165 \ + ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \ + NUMONYX_TRAS_165, NUMONYX_TRP_165, \ + NUMONYX_TRCD_165, NUMONYX_TRRD_165, \ + NUMONYX_TDPL_165, NUMONYX_TDAL_165) + +#define NUMONYX_TWTR_165 2 +#define NUMONYX_TCKE_165 2 +#define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */ +#define NUMONYX_XSR_165 34 /* 1.0 + 1.1 = 2.1 -> 3 */ + +#define NUMONYX_V_ACTIMB_165 \ + ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \ + NUMONYX_TXP_165, NUMONYX_XSR_165) + +#define NUMONYX_RASWIDTH_165 15 +#define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165) + +/* NUMONYX part of IGEP v2 (200MHz optimized) 5 ns */ +#define NUMONYX_TDAL_200 6 /* Twr/Tck + Trp/tck */ + /* 15/5 + 15/5 = 3 + 3 -> 6 */ +#define NUMONYX_TDPL_200 3 /* 15/5 = 3 -> 3 (Twr) */ +#define NUMONYX_TRRD_200 2 /* 10/5 = 2 */ +#define NUMONYX_TRCD_200 4 /* 16.2/5 = 3.24 -> 4 */ +#define NUMONYX_TRP_200 3 /* 15/5 = 3 */ +#define NUMONYX_TRAS_200 8 /* 40/5 = 8 */ +#define NUMONYX_TRC_200 11 /* 55/5 = 11 */ +#define NUMONYX_TRFC_200 28 /* 140/5 = 28 */ + +#define NUMONYX_V_ACTIMA_200 \ + ACTIM_CTRLA(NUMONYX_TRFC_200, NUMONYX_TRC_200, \ + NUMONYX_TRAS_200, NUMONYX_TRP_200, \ + NUMONYX_TRCD_200, NUMONYX_TRRD_200, \ + NUMONYX_TDPL_200, NUMONYX_TDAL_200) + +#define NUMONYX_TWTR_200 2 +#define NUMONYX_TCKE_200 2 +#define NUMONYX_TXP_200 3 +#define NUMONYX_XSR_200 40 + +#define NUMONYX_V_ACTIMB_200 \ + ACTIM_CTRLB(NUMONYX_TWTR_200, NUMONYX_TCKE_200, \ + NUMONYX_TXP_200, NUMONYX_XSR_200) + +#define NUMONYX_RASWIDTH_200 15 +#define NUMONYX_V_MCFG_200(size) MCFG((size), NUMONYX_RASWIDTH_200) + +/* + * GPMC settings - + * Definitions is as per the following format + * #define _GPMC_CONFIG + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should + * go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * STNOR - Intel Strata Flash + * SMNAND - Samsung NAND + * MPDB - H4 MPDB board + * SBNOR - Sibley NOR + * MNAND - Micron Large page x16 NAND + * ONNAND - Samsung One NAND + * + * include/configs/file.h contains the defn - for all CS we are interested + * #define OMAP34XX_GPMC_CSx PART + * #define OMAP34XX_GPMC_CSx_SIZE Size + * #define OMAP34XX_GPMC_CSx_MAP Map + * Where: + * x - CS number + * PART - Part Name as defined above + * SIZE - how big is the mapping to be + * GPMC_SIZE_128M - 0x8 + * GPMC_SIZE_64M - 0xC + * GPMC_SIZE_32M - 0xE + * GPMC_SIZE_16M - 0xF + * MAP - Map this CS to which address(GPMC address space)- Absolute address + * >>24 before being used. + */ +#define GPMC_SIZE_256M 0x0 +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#define GPMC_BASEADDR_MASK 0x3F + +#define GPMC_CS_ENABLE 0x1 + +#define M_NAND_GPMC_CONFIG1 0x00001800 +#define M_NAND_GPMC_CONFIG2 0x00141400 +#define M_NAND_GPMC_CONFIG3 0x00141400 +#define M_NAND_GPMC_CONFIG4 0x0F010F01 +#define M_NAND_GPMC_CONFIG5 0x010C1414 +#define M_NAND_GPMC_CONFIG6 0x1f0f0A80 +#define M_NAND_GPMC_CONFIG7 0x00000C44 + +#define STNOR_GPMC_CONFIG1 0x3 +#define STNOR_GPMC_CONFIG2 0x00151501 +#define STNOR_GPMC_CONFIG3 0x00060602 +#define STNOR_GPMC_CONFIG4 0x11091109 +#define STNOR_GPMC_CONFIG5 0x01141F1F +#define STNOR_GPMC_CONFIG6 0x000004c4 + +#define SIBNOR_GPMC_CONFIG1 0x1200 +#define SIBNOR_GPMC_CONFIG2 0x001f1f00 +#define SIBNOR_GPMC_CONFIG3 0x00080802 +#define SIBNOR_GPMC_CONFIG4 0x1C091C09 +#define SIBNOR_GPMC_CONFIG5 0x01131F1F +#define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 + +#define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 +#define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 +#define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 +#define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 +#define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F +#define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 + +#define MPDB_GPMC_CONFIG1 0x00011000 +#define MPDB_GPMC_CONFIG2 0x001f1f01 +#define MPDB_GPMC_CONFIG3 0x00080803 +#define MPDB_GPMC_CONFIG4 0x1c0b1c0a +#define MPDB_GPMC_CONFIG5 0x041f1F1F +#define MPDB_GPMC_CONFIG6 0x1F0F04C4 + +#define P2_GPMC_CONFIG1 0x0 +#define P2_GPMC_CONFIG2 0x0 +#define P2_GPMC_CONFIG3 0x0 +#define P2_GPMC_CONFIG4 0x0 +#define P2_GPMC_CONFIG5 0x0 +#define P2_GPMC_CONFIG6 0x0 + +#define ONENAND_GPMC_CONFIG1 0x00001200 +#define ONENAND_GPMC_CONFIG2 0x000F0F01 +#define ONENAND_GPMC_CONFIG3 0x00030301 +#define ONENAND_GPMC_CONFIG4 0x0F040F04 +#define ONENAND_GPMC_CONFIG5 0x010F1010 +#define ONENAND_GPMC_CONFIG6 0x1F060000 + +#define NET_GPMC_CONFIG1 0x00001000 +#define NET_GPMC_CONFIG2 0x001e1e01 +#define NET_GPMC_CONFIG3 0x00080300 +#define NET_GPMC_CONFIG4 0x1c091c09 +#define NET_GPMC_CONFIG5 0x04181f1f +#define NET_GPMC_CONFIG6 0x00000FCF +#define NET_GPMC_CONFIG7 0x00000f6c + +/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */ +#define NET_LAN9221_GPMC_CONFIG1 0x00001000 +#define NET_LAN9221_GPMC_CONFIG2 0x00060700 +#define NET_LAN9221_GPMC_CONFIG3 0x00020201 +#define NET_LAN9221_GPMC_CONFIG4 0x06000700 +#define NET_LAN9221_GPMC_CONFIG5 0x0006090A +#define NET_LAN9221_GPMC_CONFIG6 0x87030000 +#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c + + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#define DBG_MPDB 6 +#define DBG_MPDB_BASE DEBUG_BASE + +#ifndef __ASSEMBLY__ + +/* Function prototypes */ +void mem_init(void); + +u32 is_mem_sdr(void); +u32 mem_ok(u32 cs); + +u32 get_sdr_cs_size(u32); +u32 get_sdr_cs_offset(u32); + +#endif /* __ASSEMBLY__ */ + +#endif /* endif _MEM_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/roms/u-boot/arch/arm/include/asm/arch-omap3/mmc_host_def.h new file mode 100644 index 000000000..39a7cba0f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap3/mmc_host_def.h @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MMC_HOST_DEF_H +#define MMC_HOST_DEF_H + +#include + +/* T2 Register definitions */ +#define T2_BASE 0x48002000 + +typedef struct t2 { + unsigned char res1[0x274]; /* 0x000 */ + unsigned int devconf0; /* 0x274 */ + unsigned char res2[0x060]; /* 0x278 */ + unsigned int devconf1; /* 0x2D8 */ + unsigned char res3[0x16C]; /* 0x2DC */ + unsigned int ctl_prog_io1; /* 0x448 */ + unsigned char res4[0x0D4]; /* 0x44C */ + unsigned int pbias_lite; /* 0x520 */ +} t2_t; + +#define MMCSDIO1ADPCLKISEL (1 << 24) +#define MMCSDIO2ADPCLKISEL (1 << 6) + +#define EN_MMC1 (1 << 24) +#define EN_MMC2 (1 << 25) +#define EN_MMC3 (1 << 30) + +#define PBIASLITEPWRDNZ0 (1 << 1) +#define PBIASSPEEDCTRL0 (1 << 2) +#define PBIASLITEPWRDNZ1 (1 << 9) +#define PBIASLITEVMODE1 (1 << 8) +#define PBIASLITEVMODE0 (1 << 0) + +#define CTLPROGIO1SPEEDCTRL (1 << 20) + +/* + * OMAP HSMMC register definitions + */ +#define OMAP_HSMMC1_BASE 0x4809C000 +#define OMAP_HSMMC2_BASE 0x480B4000 +#define OMAP_HSMMC3_BASE 0x480AD000 + + +#endif /* MMC_HOST_DEF_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap3/musb.h b/roms/u-boot/arch/arm/include/asm/arch-omap3/musb.h new file mode 100644 index 000000000..cb3f5d89d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap3/musb.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Ilya Yanok, + */ + +#ifndef __ASM_ARCH_OMAP3_MUSB_H +#define __ASM_ARCH_OMAP3_MUSB_H +void am35x_musb_reset(struct udevice *dev); +void am35x_musb_phy_power(struct udevice *dev, u8 on); +void am35x_musb_clear_irq(struct udevice *dev); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap3/mux.h b/roms/u-boot/arch/arm/include/asm/arch-omap3/mux.h new file mode 100644 index 000000000..2ed520d4b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap3/mux.h @@ -0,0 +1,497 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, + * Syed Mohammed Khasim + */ +#ifndef _MUX_H_ +#define _MUX_H_ + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * SB_LOW - Standby mode configuration: Output low-level + * SB_HI - Standby mode configuration: Output high-level + * SB_HIZ - Standby mode configuration: Output hi-impedence + * SB_PD - Standby mode pull-down enabled + * SB_PU - Standby mode pull-up enabled + * WKEN - Wakeup input enabled + * M0 - Mode 0 + */ + +#define IEN (1 << 8) + +#define IDIS (0 << 8) +#define PTU (1 << 4) +#define PTD (0 << 4) +#define EN (1 << 3) +#define DIS (0 << 3) + +#define SB_LOW (1 << 9) +#define SB_HI (5 << 9) +#define SB_HIZ (2 << 9) +#define SB_PD (1 << 12) +#define SB_PU (3 << 12) +#define WKEN (1 << 14) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 + +/* + * To get the actual address the offset has to be added + * to OMAP34XX_CTRL_BASE + */ + +/*SDRC*/ +#define CONTROL_PADCONF_SDRC_D0 0x0030 +#define CONTROL_PADCONF_SDRC_D1 0x0032 +#define CONTROL_PADCONF_SDRC_D2 0x0034 +#define CONTROL_PADCONF_SDRC_D3 0x0036 +#define CONTROL_PADCONF_SDRC_D4 0x0038 +#define CONTROL_PADCONF_SDRC_D5 0x003A +#define CONTROL_PADCONF_SDRC_D6 0x003C +#define CONTROL_PADCONF_SDRC_D7 0x003E +#define CONTROL_PADCONF_SDRC_D8 0x0040 +#define CONTROL_PADCONF_SDRC_D9 0x0042 +#define CONTROL_PADCONF_SDRC_D10 0x0044 +#define CONTROL_PADCONF_SDRC_D11 0x0046 +#define CONTROL_PADCONF_SDRC_D12 0x0048 +#define CONTROL_PADCONF_SDRC_D13 0x004A +#define CONTROL_PADCONF_SDRC_D14 0x004C +#define CONTROL_PADCONF_SDRC_D15 0x004E +#define CONTROL_PADCONF_SDRC_D16 0x0050 +#define CONTROL_PADCONF_SDRC_D17 0x0052 +#define CONTROL_PADCONF_SDRC_D18 0x0054 +#define CONTROL_PADCONF_SDRC_D19 0x0056 +#define CONTROL_PADCONF_SDRC_D20 0x0058 +#define CONTROL_PADCONF_SDRC_D21 0x005A +#define CONTROL_PADCONF_SDRC_D22 0x005C +#define CONTROL_PADCONF_SDRC_D23 0x005E +#define CONTROL_PADCONF_SDRC_D24 0x0060 +#define CONTROL_PADCONF_SDRC_D25 0x0062 +#define CONTROL_PADCONF_SDRC_D26 0x0064 +#define CONTROL_PADCONF_SDRC_D27 0x0066 +#define CONTROL_PADCONF_SDRC_D28 0x0068 +#define CONTROL_PADCONF_SDRC_D29 0x006A +#define CONTROL_PADCONF_SDRC_D30 0x006C +#define CONTROL_PADCONF_SDRC_D31 0x006E +#define CONTROL_PADCONF_SDRC_CLK 0x0070 +#define CONTROL_PADCONF_SDRC_DQS0 0x0072 +#define CONTROL_PADCONF_SDRC_DQS1 0x0074 +#define CONTROL_PADCONF_SDRC_DQS2 0x0076 +#define CONTROL_PADCONF_SDRC_DQS3 0x0078 +#define CONTROL_PADCONF_SDRC_BA0 0x05A0 +#define CONTROL_PADCONF_SDRC_BA1 0x05A2 +#define CONTROL_PADCONF_SDRC_A0 0x05A4 +#define CONTROL_PADCONF_SDRC_A1 0x05A6 +#define CONTROL_PADCONF_SDRC_A2 0x05A8 +#define CONTROL_PADCONF_SDRC_A3 0x05AA +#define CONTROL_PADCONF_SDRC_A4 0x05AC +#define CONTROL_PADCONF_SDRC_A5 0x05AE +#define CONTROL_PADCONF_SDRC_A6 0x05B0 +#define CONTROL_PADCONF_SDRC_A7 0x05B2 +#define CONTROL_PADCONF_SDRC_A8 0x05B4 +#define CONTROL_PADCONF_SDRC_A9 0x05B6 +#define CONTROL_PADCONF_SDRC_A10 0x05B8 +#define CONTROL_PADCONF_SDRC_A11 0x05BA +#define CONTROL_PADCONF_SDRC_A12 0x05BC +#define CONTROL_PADCONF_SDRC_A13 0x05BE +#define CONTROL_PADCONF_SDRC_A14 0x05C0 +#define CONTROL_PADCONF_SDRC_NCS0 0x05C2 +#define CONTROL_PADCONF_SDRC_NCS1 0x05C4 +#define CONTROL_PADCONF_SDRC_NCLK 0x05C6 +#define CONTROL_PADCONF_SDRC_NRAS 0x05C8 +#define CONTROL_PADCONF_SDRC_NCAS 0x05CA +#define CONTROL_PADCONF_SDRC_NWE 0x05CC +#define CONTROL_PADCONF_SDRC_DM0 0x05CE +#define CONTROL_PADCONF_SDRC_DM1 0x05D0 +#define CONTROL_PADCONF_SDRC_DM2 0x05D2 +#define CONTROL_PADCONF_SDRC_DM3 0x05D4 +/*GPMC*/ +#define CONTROL_PADCONF_GPMC_A1 0x007A +#define CONTROL_PADCONF_GPMC_A2 0x007C +#define CONTROL_PADCONF_GPMC_A3 0x007E +#define CONTROL_PADCONF_GPMC_A4 0x0080 +#define CONTROL_PADCONF_GPMC_A5 0x0082 +#define CONTROL_PADCONF_GPMC_A6 0x0084 +#define CONTROL_PADCONF_GPMC_A7 0x0086 +#define CONTROL_PADCONF_GPMC_A8 0x0088 +#define CONTROL_PADCONF_GPMC_A9 0x008A +#define CONTROL_PADCONF_GPMC_A10 0x008C +#define CONTROL_PADCONF_GPMC_A11 0x0264 +#define CONTROL_PADCONF_GPMC_D0 0x008E +#define CONTROL_PADCONF_GPMC_D1 0x0090 +#define CONTROL_PADCONF_GPMC_D2 0x0092 +#define CONTROL_PADCONF_GPMC_D3 0x0094 +#define CONTROL_PADCONF_GPMC_D4 0x0096 +#define CONTROL_PADCONF_GPMC_D5 0x0098 +#define CONTROL_PADCONF_GPMC_D6 0x009A +#define CONTROL_PADCONF_GPMC_D7 0x009C +#define CONTROL_PADCONF_GPMC_D8 0x009E +#define CONTROL_PADCONF_GPMC_D9 0x00A0 +#define CONTROL_PADCONF_GPMC_D10 0x00A2 +#define CONTROL_PADCONF_GPMC_D11 0x00A4 +#define CONTROL_PADCONF_GPMC_D12 0x00A6 +#define CONTROL_PADCONF_GPMC_D13 0x00A8 +#define CONTROL_PADCONF_GPMC_D14 0x00AA +#define CONTROL_PADCONF_GPMC_D15 0x00AC +#define CONTROL_PADCONF_GPMC_NCS0 0x00AE +#define CONTROL_PADCONF_GPMC_NCS1 0x00B0 +#define CONTROL_PADCONF_GPMC_NCS2 0x00B2 +#define CONTROL_PADCONF_GPMC_NCS3 0x00B4 +#define CONTROL_PADCONF_GPMC_NCS4 0x00B6 +#define CONTROL_PADCONF_GPMC_NCS5 0x00B8 +#define CONTROL_PADCONF_GPMC_NCS6 0x00BA +#define CONTROL_PADCONF_GPMC_NCS7 0x00BC +#define CONTROL_PADCONF_GPMC_CLK 0x00BE +#define CONTROL_PADCONF_GPMC_NADV_ALE 0x00C0 +#define CONTROL_PADCONF_GPMC_NOE 0x00C2 +#define CONTROL_PADCONF_GPMC_NWE 0x00C4 +#define CONTROL_PADCONF_GPMC_NBE0_CLE 0x00C6 +#define CONTROL_PADCONF_GPMC_NBE1 0x00C8 +#define CONTROL_PADCONF_GPMC_NWP 0x00CA +#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC +#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE +#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0 +#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2 +/*DSS*/ +#define CONTROL_PADCONF_DSS_PCLK 0x00D4 +#define CONTROL_PADCONF_DSS_HSYNC 0x00D6 +#define CONTROL_PADCONF_DSS_VSYNC 0x00D8 +#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA +#define CONTROL_PADCONF_DSS_DATA0 0x00DC +#define CONTROL_PADCONF_DSS_DATA1 0x00DE +#define CONTROL_PADCONF_DSS_DATA2 0x00E0 +#define CONTROL_PADCONF_DSS_DATA3 0x00E2 +#define CONTROL_PADCONF_DSS_DATA4 0x00E4 +#define CONTROL_PADCONF_DSS_DATA5 0x00E6 +#define CONTROL_PADCONF_DSS_DATA6 0x00E8 +#define CONTROL_PADCONF_DSS_DATA7 0x00EA +#define CONTROL_PADCONF_DSS_DATA8 0x00EC +#define CONTROL_PADCONF_DSS_DATA9 0x00EE +#define CONTROL_PADCONF_DSS_DATA10 0x00F0 +#define CONTROL_PADCONF_DSS_DATA11 0x00F2 +#define CONTROL_PADCONF_DSS_DATA12 0x00F4 +#define CONTROL_PADCONF_DSS_DATA13 0x00F6 +#define CONTROL_PADCONF_DSS_DATA14 0x00F8 +#define CONTROL_PADCONF_DSS_DATA15 0x00FA +#define CONTROL_PADCONF_DSS_DATA16 0x00FC +#define CONTROL_PADCONF_DSS_DATA17 0x00FE +#define CONTROL_PADCONF_DSS_DATA18 0x0100 +#define CONTROL_PADCONF_DSS_DATA19 0x0102 +#define CONTROL_PADCONF_DSS_DATA20 0x0104 +#define CONTROL_PADCONF_DSS_DATA21 0x0106 +#define CONTROL_PADCONF_DSS_DATA22 0x0108 +#define CONTROL_PADCONF_DSS_DATA23 0x010A +/*CAMERA*/ +#define CONTROL_PADCONF_CAM_HS 0x010C +#define CONTROL_PADCONF_CAM_VS 0x010E +#define CONTROL_PADCONF_CAM_XCLKA 0x0110 +#define CONTROL_PADCONF_CAM_PCLK 0x0112 +#define CONTROL_PADCONF_CAM_FLD 0x0114 +#define CONTROL_PADCONF_CAM_D0 0x0116 +#define CONTROL_PADCONF_CAM_D1 0x0118 +#define CONTROL_PADCONF_CAM_D2 0x011A +#define CONTROL_PADCONF_CAM_D3 0x011C +#define CONTROL_PADCONF_CAM_D4 0x011E +#define CONTROL_PADCONF_CAM_D5 0x0120 +#define CONTROL_PADCONF_CAM_D6 0x0122 +#define CONTROL_PADCONF_CAM_D7 0x0124 +#define CONTROL_PADCONF_CAM_D8 0x0126 +#define CONTROL_PADCONF_CAM_D9 0x0128 +#define CONTROL_PADCONF_CAM_D10 0x012A +#define CONTROL_PADCONF_CAM_D11 0x012C +#define CONTROL_PADCONF_CAM_XCLKB 0x012E +#define CONTROL_PADCONF_CAM_WEN 0x0130 +#define CONTROL_PADCONF_CAM_STROBE 0x0132 +#define CONTROL_PADCONF_CSI2_DX0 0x0134 +#define CONTROL_PADCONF_CSI2_DY0 0x0136 +#define CONTROL_PADCONF_CSI2_DX1 0x0138 +#define CONTROL_PADCONF_CSI2_DY1 0x013A +/*Audio Interface */ +#define CONTROL_PADCONF_MCBSP2_FSX 0x013C +#define CONTROL_PADCONF_MCBSP2_CLKX 0x013E +#define CONTROL_PADCONF_MCBSP2_DR 0x0140 +#define CONTROL_PADCONF_MCBSP2_DX 0x0142 +#define CONTROL_PADCONF_MMC1_CLK 0x0144 +#define CONTROL_PADCONF_MMC1_CMD 0x0146 +#define CONTROL_PADCONF_MMC1_DAT0 0x0148 +#define CONTROL_PADCONF_MMC1_DAT1 0x014A +#define CONTROL_PADCONF_MMC1_DAT2 0x014C +#define CONTROL_PADCONF_MMC1_DAT3 0x014E +#define CONTROL_PADCONF_MMC1_DAT4 0x0150 +#define CONTROL_PADCONF_MMC1_DAT5 0x0152 +#define CONTROL_PADCONF_MMC1_DAT6 0x0154 +#define CONTROL_PADCONF_MMC1_DAT7 0x0156 +/*Wireless LAN */ +#define CONTROL_PADCONF_MMC2_CLK 0x0158 +#define CONTROL_PADCONF_MMC2_CMD 0x015A +#define CONTROL_PADCONF_MMC2_DAT0 0x015C +#define CONTROL_PADCONF_MMC2_DAT1 0x015E +#define CONTROL_PADCONF_MMC2_DAT2 0x0160 +#define CONTROL_PADCONF_MMC2_DAT3 0x0162 +#define CONTROL_PADCONF_MMC2_DAT4 0x0164 +#define CONTROL_PADCONF_MMC2_DAT5 0x0166 +#define CONTROL_PADCONF_MMC2_DAT6 0x0168 +#define CONTROL_PADCONF_MMC2_DAT7 0x016A +/*Bluetooth*/ +#define CONTROL_PADCONF_MCBSP3_DX 0x016C +#define CONTROL_PADCONF_MCBSP3_DR 0x016E +#define CONTROL_PADCONF_MCBSP3_CLKX 0x0170 +#define CONTROL_PADCONF_MCBSP3_FSX 0x0172 +#define CONTROL_PADCONF_UART2_CTS 0x0174 +#define CONTROL_PADCONF_UART2_RTS 0x0176 +#define CONTROL_PADCONF_UART2_TX 0x0178 +#define CONTROL_PADCONF_UART2_RX 0x017A +/*Modem Interface */ +#define CONTROL_PADCONF_UART1_TX 0x017C +#define CONTROL_PADCONF_UART1_RTS 0x017E +#define CONTROL_PADCONF_UART1_CTS 0x0180 +#define CONTROL_PADCONF_UART1_RX 0x0182 +#define CONTROL_PADCONF_MCBSP4_CLKX 0x0184 +#define CONTROL_PADCONF_MCBSP4_DR 0x0186 +#define CONTROL_PADCONF_MCBSP4_DX 0x0188 +#define CONTROL_PADCONF_MCBSP4_FSX 0x018A +#define CONTROL_PADCONF_MCBSP1_CLKR 0x018C +#define CONTROL_PADCONF_MCBSP1_FSR 0x018E +#define CONTROL_PADCONF_MCBSP1_DX 0x0190 +#define CONTROL_PADCONF_MCBSP1_DR 0x0192 +#define CONTROL_PADCONF_MCBSP_CLKS 0x0194 +#define CONTROL_PADCONF_MCBSP1_FSX 0x0196 +#define CONTROL_PADCONF_MCBSP1_CLKX 0x0198 +/*Serial Interface*/ +#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A +#define CONTROL_PADCONF_UART3_RTS_SD 0x019C +#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E +#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0 +#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2 +#define CONTROL_PADCONF_HSUSB0_STP 0x01A4 +#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6 +#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8 +#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA +#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC +#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE +#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0 +#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2 +#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4 +#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6 +#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8 +#define CONTROL_PADCONF_I2C1_SCL 0x01BA +#define CONTROL_PADCONF_I2C1_SDA 0x01BC +#define CONTROL_PADCONF_I2C2_SCL 0x01BE +#define CONTROL_PADCONF_I2C2_SDA 0x01C0 +#define CONTROL_PADCONF_I2C3_SCL 0x01C2 +#define CONTROL_PADCONF_I2C3_SDA 0x01C4 +#define CONTROL_PADCONF_I2C4_SCL 0x0A00 +#define CONTROL_PADCONF_I2C4_SDA 0x0A02 +#define CONTROL_PADCONF_HDQ_SIO 0x01C6 +#define CONTROL_PADCONF_MCSPI1_CLK 0x01C8 +#define CONTROL_PADCONF_MCSPI1_SIMO 0x01CA +#define CONTROL_PADCONF_MCSPI1_SOMI 0x01CC +#define CONTROL_PADCONF_MCSPI1_CS0 0x01CE +#define CONTROL_PADCONF_MCSPI1_CS1 0x01D0 +#define CONTROL_PADCONF_MCSPI1_CS2 0x01D2 +#define CONTROL_PADCONF_MCSPI1_CS3 0x01D4 +#define CONTROL_PADCONF_MCSPI2_CLK 0x01D6 +#define CONTROL_PADCONF_MCSPI2_SIMO 0x01D8 +#define CONTROL_PADCONF_MCSPI2_SOMI 0x01DA +#define CONTROL_PADCONF_MCSPI2_CS0 0x01DC +#define CONTROL_PADCONF_MCSPI2_CS1 0x01DE +/*Control and debug */ +#define CONTROL_PADCONF_SYS_32K 0x0A04 +#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 +#define CONTROL_PADCONF_SYS_NIRQ 0x01E0 +#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A +#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C +#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E +#define CONTROL_PADCONF_SYS_BOOT3 0x0A10 +#define CONTROL_PADCONF_SYS_BOOT4 0x0A12 +#define CONTROL_PADCONF_SYS_BOOT5 0x0A14 +#define CONTROL_PADCONF_SYS_BOOT6 0x0A16 +#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 +#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A +#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 +#define CONTROL_PADCONF_JTAG_NTRST 0x0A1C +#define CONTROL_PADCONF_JTAG_TCK 0x0A1E +#define CONTROL_PADCONF_JTAG_TMS 0x0A20 +#define CONTROL_PADCONF_JTAG_TDI 0x0A22 +#define CONTROL_PADCONF_JTAG_EMU0 0x0A24 +#define CONTROL_PADCONF_JTAG_EMU1 0x0A26 +#define CONTROL_PADCONF_ETK_CLK 0x0A28 +#define CONTROL_PADCONF_ETK_CTL 0x0A2A +#define CONTROL_PADCONF_ETK_D0 0x0A2C +#define CONTROL_PADCONF_ETK_D1 0x0A2E +#define CONTROL_PADCONF_ETK_D2 0x0A30 +#define CONTROL_PADCONF_ETK_D3 0x0A32 +#define CONTROL_PADCONF_ETK_D4 0x0A34 +#define CONTROL_PADCONF_ETK_D5 0x0A36 +#define CONTROL_PADCONF_ETK_D6 0x0A38 +#define CONTROL_PADCONF_ETK_D7 0x0A3A +#define CONTROL_PADCONF_ETK_D8 0x0A3C +#define CONTROL_PADCONF_ETK_D9 0x0A3E +#define CONTROL_PADCONF_ETK_D10 0x0A40 +#define CONTROL_PADCONF_ETK_D11 0x0A42 +#define CONTROL_PADCONF_ETK_D12 0x0A44 +#define CONTROL_PADCONF_ETK_D13 0x0A46 +#define CONTROL_PADCONF_ETK_D14 0x0A48 +#define CONTROL_PADCONF_ETK_D15 0x0A4A +#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8 +#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA +#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC +#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE +#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0 +#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2 +#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4 +#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6 +#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8 +#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA +#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC +#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE +#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0 +#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2 +#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4 +#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6 +#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 +#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA +#define CONTROL_PADCONF_JTAG_RTCK 0x0A4E +#define CONTROL_PADCONF_JTAG_TDO 0x0A50 +/*Die to Die */ +#define CONTROL_PADCONF_D2D_MCAD0 0x01E4 +#define CONTROL_PADCONF_D2D_MCAD1 0x01E6 +#define CONTROL_PADCONF_D2D_MCAD2 0x01E8 +#define CONTROL_PADCONF_D2D_MCAD3 0x01EA +#define CONTROL_PADCONF_D2D_MCAD4 0x01EC +#define CONTROL_PADCONF_D2D_MCAD5 0x01EE +#define CONTROL_PADCONF_D2D_MCAD6 0x01F0 +#define CONTROL_PADCONF_D2D_MCAD7 0x01F2 +#define CONTROL_PADCONF_D2D_MCAD8 0x01F4 +#define CONTROL_PADCONF_D2D_MCAD9 0x01F6 +#define CONTROL_PADCONF_D2D_MCAD10 0x01F8 +#define CONTROL_PADCONF_D2D_MCAD11 0x01FA +#define CONTROL_PADCONF_D2D_MCAD12 0x01FC +#define CONTROL_PADCONF_D2D_MCAD13 0x01FE +#define CONTROL_PADCONF_D2D_MCAD14 0x0200 +#define CONTROL_PADCONF_D2D_MCAD15 0x0202 +#define CONTROL_PADCONF_D2D_MCAD16 0x0204 +#define CONTROL_PADCONF_D2D_MCAD17 0x0206 +#define CONTROL_PADCONF_D2D_MCAD18 0x0208 +#define CONTROL_PADCONF_D2D_MCAD19 0x020A +#define CONTROL_PADCONF_D2D_MCAD20 0x020C +#define CONTROL_PADCONF_D2D_MCAD21 0x020E +#define CONTROL_PADCONF_D2D_MCAD22 0x0210 +#define CONTROL_PADCONF_D2D_MCAD23 0x0212 +#define CONTROL_PADCONF_D2D_MCAD24 0x0214 +#define CONTROL_PADCONF_D2D_MCAD25 0x0216 +#define CONTROL_PADCONF_D2D_MCAD26 0x0218 +#define CONTROL_PADCONF_D2D_MCAD27 0x021A +#define CONTROL_PADCONF_D2D_MCAD28 0x021C +#define CONTROL_PADCONF_D2D_MCAD29 0x021E +#define CONTROL_PADCONF_D2D_MCAD30 0x0220 +#define CONTROL_PADCONF_D2D_MCAD31 0x0222 +#define CONTROL_PADCONF_D2D_MCAD32 0x0224 +#define CONTROL_PADCONF_D2D_MCAD33 0x0226 +#define CONTROL_PADCONF_D2D_MCAD34 0x0228 +#define CONTROL_PADCONF_D2D_MCAD35 0x022A +#define CONTROL_PADCONF_D2D_MCAD36 0x022C +#define CONTROL_PADCONF_D2D_CLK26MI 0x022E +#define CONTROL_PADCONF_D2D_NRESPWRON 0x0230 +#define CONTROL_PADCONF_D2D_NRESWARM 0x0232 +#define CONTROL_PADCONF_D2D_ARM9NIRQ 0x0234 +#define CONTROL_PADCONF_D2D_UMA2P6FIQ 0x0236 +#define CONTROL_PADCONF_D2D_SPINT 0x0238 +#define CONTROL_PADCONF_D2D_FRINT 0x023A +#define CONTROL_PADCONF_D2D_DMAREQ0 0x023C +#define CONTROL_PADCONF_D2D_DMAREQ1 0x023E +#define CONTROL_PADCONF_D2D_DMAREQ2 0x0240 +#define CONTROL_PADCONF_D2D_DMAREQ3 0x0242 +#define CONTROL_PADCONF_D2D_N3GTRST 0x0244 +#define CONTROL_PADCONF_D2D_N3GTDI 0x0246 +#define CONTROL_PADCONF_D2D_N3GTDO 0x0248 +#define CONTROL_PADCONF_D2D_N3GTMS 0x024A +#define CONTROL_PADCONF_D2D_N3GTCK 0x024C +#define CONTROL_PADCONF_D2D_N3GRTCK 0x024E +#define CONTROL_PADCONF_D2D_MSTDBY 0x0250 +#define CONTROL_PADCONF_D2D_SWAKEUP 0x0A4C +#define CONTROL_PADCONF_D2D_IDLEREQ 0x0252 +#define CONTROL_PADCONF_D2D_IDLEACK 0x0254 +#define CONTROL_PADCONF_D2D_MWRITE 0x0256 +#define CONTROL_PADCONF_D2D_SWRITE 0x0258 +#define CONTROL_PADCONF_D2D_MREAD 0x025A +#define CONTROL_PADCONF_D2D_SREAD 0x025C +#define CONTROL_PADCONF_D2D_MBUSFLAG 0x025E +#define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260 +#define CONTROL_PADCONF_SDRC_CKE0 0x0262 +#define CONTROL_PADCONF_SDRC_CKE1 0x0264 + +/* AM3517 specific mux configuration */ +#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 +/* CCDC */ +#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 +#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 +#define CONTROL_PADCONF_CCDC_HD 0x01E8 +#define CONTROL_PADCONF_CCDC_VD 0x01EA +#define CONTROL_PADCONF_CCDC_WEN 0x01EC +#define CONTROL_PADCONF_CCDC_DATA0 0x01EE +#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 +#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 +#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 +#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 +#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 +#define CONTROL_PADCONF_CCDC_DATA6 0x01FA +#define CONTROL_PADCONF_CCDC_DATA7 0x01FC +/* RMII */ +#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE +#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 +#define CONTROL_PADCONF_RMII_RXD0 0x0202 +#define CONTROL_PADCONF_RMII_RXD1 0x0204 +#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 +#define CONTROL_PADCONF_RMII_RXER 0x0208 +#define CONTROL_PADCONF_RMII_TXD0 0x020A +#define CONTROL_PADCONF_RMII_TXD1 0x020C +#define CONTROL_PADCONF_RMII_TXEN 0x020E +#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 +#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 +/* CAN */ +#define CONTROL_PADCONF_HECC1_TXD 0x0214 +#define CONTROL_PADCONF_HECC1_RXD 0x0216 + +#define CONTROL_PADCONF_SYS_BOOT7 0x0218 +#define CONTROL_PADCONF_SDRC_DQS0N 0x021A +#define CONTROL_PADCONF_SDRC_DQS1N 0x021C +#define CONTROL_PADCONF_SDRC_DQS2N 0x021E +#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 +#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 +#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 +#define CONTROL_PADCONF_SYS_BOOT8 0x0226 + +/* AM/DM37xx specific */ +#define CONTROL_PADCONF_GPIO112 0x0134 +#define CONTROL_PADCONF_GPIO113 0x0136 +#define CONTROL_PADCONF_GPIO114 0x0138 +#define CONTROL_PADCONF_GPIO115 0x013A +#define CONTROL_PADCONF_GPIO127 0x0A54 +#define CONTROL_PADCONF_GPIO126 0x0A56 +#define CONTROL_PADCONF_GPIO128 0x0A58 +#define CONTROL_PADCONF_GPIO129 0x0A5A + +/* AM/DM37xx specific: gpio_127, gpio_127 and gpio_129 require configuration + * of the extended drain cells */ +#define OMAP34XX_CTRL_WKUP_CTRL (OMAP34XX_CTRL_BASE + 0x0A5C) +#define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ (1<<6) + +#define MUX_VAL(OFFSET, VALUE)\ + writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap3/omap.h b/roms/u-boot/arch/arm/include/asm/arch-omap3/omap.h new file mode 100644 index 000000000..19155a280 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap3/omap.h @@ -0,0 +1,284 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, + * Richard Woodruff + * Syed Mohammed Khasim + */ + +#ifndef _OMAP3_H_ +#define _OMAP3_H_ + +#include + +/* Stuff on L3 Interconnect */ +#define SMX_APE_BASE 0x68000000 + +/* GPMC */ +#define OMAP34XX_GPMC_BASE 0x6E000000 + +/* SMS */ +#define OMAP34XX_SMS_BASE 0x6C000000 + +/* SDRC */ +#define OMAP34XX_SDRC_BASE 0x6D000000 + +/* + * L4 Peripherals - L4 Wakeup and L4 Core now + */ +#define OMAP34XX_CORE_L4_IO_BASE 0x48000000 +#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000 +#define OMAP34XX_ID_L4_IO_BASE 0x4830A200 +#define OMAP34XX_L4_PER 0x49000000 +#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE + +/* DMA4/SDMA */ +#define OMAP34XX_DMA4_BASE 0x48056000 + +/* CONTROL */ +#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000) + +#ifndef __ASSEMBLY__ +/* Signal Integrity Parameter Control Registers */ +struct control_prog_io { + unsigned char res[0x408]; + unsigned int io2; /* 0x408 */ + unsigned char res2[0x38]; + unsigned int io0; /* 0x444 */ + unsigned int io1; /* 0x448 */ +}; +#endif /* __ASSEMBLY__ */ + +/* Bit definition for CONTROL_PROG_IO1 */ +#define PRG_I2C2_PULLUPRESX 0x00000001 + +/* Scratchpad memory */ +#define OMAP34XX_SCRATCHPAD (OMAP34XX_CTRL_BASE + 0x910) + +/* UART */ +#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000) +#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000) +#define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000) +#define OMAP34XX_UART4 (OMAP34XX_L4_PER + 0x42000) + +/* General Purpose Timers */ +#define OMAP34XX_GPT1 0x48318000 +#define OMAP34XX_GPT2 0x49032000 +#define OMAP34XX_GPT3 0x49034000 +#define OMAP34XX_GPT4 0x49036000 +#define OMAP34XX_GPT5 0x49038000 +#define OMAP34XX_GPT6 0x4903A000 +#define OMAP34XX_GPT7 0x4903C000 +#define OMAP34XX_GPT8 0x4903E000 +#define OMAP34XX_GPT9 0x49040000 +#define OMAP34XX_GPT10 0x48086000 +#define OMAP34XX_GPT11 0x48088000 +#define OMAP34XX_GPT12 0x48304000 + +/* WatchDog Timers (1 secure, 3 GP) */ +#define WD1_BASE 0x4830C000 +#define WD2_BASE 0x48314000 +#define WD3_BASE 0x49030000 + +/* 32KTIMER */ +#define SYNC_32KTIMER_BASE 0x48320000 + +#ifndef __ASSEMBLY__ + +struct s32ktimer { + unsigned char res[0x10]; + unsigned int s32k_cr; /* 0x10 */ +}; + +#define DEVICE_TYPE_SHIFT 0x8 +#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) + +#endif /* __ASSEMBLY__ */ + +#ifndef __ASSEMBLY__ +struct gpio { + unsigned char res1[0x34]; + unsigned int oe; /* 0x34 */ + unsigned int datain; /* 0x38 */ + unsigned char res2[0x54]; + unsigned int cleardataout; /* 0x90 */ + unsigned int setdataout; /* 0x94 */ +}; +#endif /* __ASSEMBLY__ */ + +#define GPIO0 (0x1 << 0) +#define GPIO1 (0x1 << 1) +#define GPIO2 (0x1 << 2) +#define GPIO3 (0x1 << 3) +#define GPIO4 (0x1 << 4) +#define GPIO5 (0x1 << 5) +#define GPIO6 (0x1 << 6) +#define GPIO7 (0x1 << 7) +#define GPIO8 (0x1 << 8) +#define GPIO9 (0x1 << 9) +#define GPIO10 (0x1 << 10) +#define GPIO11 (0x1 << 11) +#define GPIO12 (0x1 << 12) +#define GPIO13 (0x1 << 13) +#define GPIO14 (0x1 << 14) +#define GPIO15 (0x1 << 15) +#define GPIO16 (0x1 << 16) +#define GPIO17 (0x1 << 17) +#define GPIO18 (0x1 << 18) +#define GPIO19 (0x1 << 19) +#define GPIO20 (0x1 << 20) +#define GPIO21 (0x1 << 21) +#define GPIO22 (0x1 << 22) +#define GPIO23 (0x1 << 23) +#define GPIO24 (0x1 << 24) +#define GPIO25 (0x1 << 25) +#define GPIO26 (0x1 << 26) +#define GPIO27 (0x1 << 27) +#define GPIO28 (0x1 << 28) +#define GPIO29 (0x1 << 29) +#define GPIO30 (0x1 << 30) +#define GPIO31 (0x1 << 31) + +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_OFFSET0 0x40000000 +#define SRAM_OFFSET1 0x00200000 +#define SRAM_OFFSET2 0x0000F800 +#define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \ + SRAM_OFFSET2) +#define SRAM_CLK_CODE (SRAM_VECT_CODE + 64) + +#define NON_SECURE_SRAM_START 0x40208000 /* Works for GP & EMU */ +#define NON_SECURE_SRAM_END 0x40210000 +#define NON_SECURE_SRAM_IMG_END 0x4020F000 +#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K) + +#define LOW_LEVEL_SRAM_STACK 0x4020FFFC + +/* scratch area - accessible on both EMU and GP */ +#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA NON_SECURE_SRAM_START + +#define DEBUG_LED1 149 /* gpio */ +#define DEBUG_LED2 150 /* gpio */ + +#define XDR_POP 5 /* package on package part */ +#define SDR_DISCRETE 4 /* 128M memory SDR module */ +#define DDR_STACKED 3 /* stacked part on 2422 */ +#define DDR_COMBO 2 /* combo part on cpu daughter card */ +#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ + +#define DDR_100 100 /* type found on most mem d-boards */ +#define DDR_111 111 /* some combo parts */ +#define DDR_133 133 /* most combo, some mem d-boards */ +#define DDR_165 165 /* future parts */ + +#define CPU_3430 0x3430 + +/* + * 343x real hardware: + * ES1 = rev 0 + * + * ES2 onwards, the value maps to contents of IDCODE register [31:28]. + * + * Note : CPU_3XX_ES20 is used in cache.S. Please review before changing. + */ +#define CPU_3XX_ES10 0 +#define CPU_3XX_ES20 1 +#define CPU_3XX_ES21 2 +#define CPU_3XX_ES30 3 +#define CPU_3XX_ES31 4 +#define CPU_3XX_ES312 7 +#define CPU_3XX_MAX_REV 8 + +/* + * 37xx real hardware: + * ES1.0 onwards, the value maps to contents of IDCODE register [31:28]. + */ + +#define CPU_37XX_ES10 0 +#define CPU_37XX_ES11 1 +#define CPU_37XX_ES12 2 +#define CPU_37XX_MAX_REV 3 + +#define CPU_3XX_ID_SHIFT 28 + +#define WIDTH_8BIT 0x0000 +#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ + +/* + * Hawkeye values + */ +#define HAWKEYE_OMAP34XX 0xb7ae +#define HAWKEYE_AM35XX 0xb868 +#define HAWKEYE_OMAP36XX 0xb891 + +#define HAWKEYE_SHIFT 12 + +/* + * Define CPU families + */ +#define CPU_OMAP34XX 0x3400 /* OMAP34xx/OMAP35 devices */ +#define CPU_AM35XX 0x3500 /* AM35xx devices */ +#define CPU_OMAP36XX 0x3600 /* OMAP36xx devices */ + +/* + * Control status register values corresponding to cpu variants + */ +#define OMAP3503 0x5c00 +#define OMAP3515 0x1c00 +#define OMAP3525 0x4c00 +#define OMAP3530 0x0c00 + +#define AM3505 0x5c00 +#define AM3517 0x1c00 + +#define OMAP3730 0x0c00 +#define OMAP3725 0x4c00 +#define AM3715 0x1c00 +#define AM3703 0x5c00 + +#define OMAP3730_1GHZ 0x0e00 +#define OMAP3725_1GHZ 0x4e00 +#define AM3715_1GHZ 0x1e00 +#define AM3703_1GHZ 0x5e00 + +/* + * ROM code API related flags + */ +#define OMAP3_GP_ROMCODE_API_L2_INVAL 1 +#define OMAP3_GP_ROMCODE_API_WRITE_L2ACR 2 +#define OMAP3_GP_ROMCODE_API_WRITE_ACR 3 + +/* + * EMU device PPA HAL related flags + */ +#define OMAP3_EMU_HAL_API_L2_INVAL 40 +#define OMAP3_EMU_HAL_API_WRITE_ACR 42 + +#define OMAP3_EMU_HAL_START_HAL_CRITICAL 4 + +/* ABB settings */ +#define OMAP_ABB_SETTLING_TIME 30 +#define OMAP_ABB_CLOCK_CYCLES 8 + +/* ABB tranxdone mask */ +#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 26) + +#define OMAP_REBOOT_REASON_OFFSET 0x04 + +/* Boot parameters */ +#ifndef __ASSEMBLY__ +struct omap_boot_parameters { + unsigned int boot_message; + unsigned char boot_device; + unsigned char reserved; + unsigned char reset_reason; + unsigned char ch_flags; + unsigned int boot_device_descriptor; +}; + +int omap_reboot_mode(char *mode, unsigned int length); +int omap_reboot_mode_clear(void); +int omap_reboot_mode_store(char *mode); +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap3/omap3-regs.h b/roms/u-boot/arch/arm/include/asm/arch-omap3/omap3-regs.h new file mode 100644 index 000000000..7b3c6c7ab --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap3/omap3-regs.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (c) 2011 Comelit Group SpA, Luca Ceresoli + */ + +#ifndef _OMAP3_REGS_H +#define _OMAP3_REGS_H + +/* + * Register definitions for OMAP3 processors. + */ + +/* + * GPMC_CONFIG1 - GPMC_CONFIG7 + */ + +/* Values for GPMC_CONFIG1 - signal control parameters */ +#define WRAPBURST (1 << 31) +#define READMULTIPLE (1 << 30) +#define READTYPE (1 << 29) +#define WRITEMULTIPLE (1 << 28) +#define WRITETYPE (1 << 27) +#define CLKACTIVATIONTIME(x) (((x) & 3) << 25) +#define ATTACHEDDEVICEPAGELENGTH(x) (((x) & 3) << 23) +#define WAITREADMONITORING (1 << 22) +#define WAITWRITEMONITORING (1 << 21) +#define WAITMONITORINGTIME(x) (((x) & 3) << 18) +#define WAITPINSELECT(x) (((x) & 3) << 16) +#define DEVICESIZE(x) (((x) & 3) << 12) +#define DEVICESIZE_8BIT DEVICESIZE(0) +#define DEVICESIZE_16BIT DEVICESIZE(1) +#define DEVICETYPE(x) (((x) & 3) << 10) +#define DEVICETYPE_NOR DEVICETYPE(0) +#define DEVICETYPE_NAND DEVICETYPE(2) +#define MUXADDDATA (1 << 9) +#define TIMEPARAGRANULARITY (1 << 4) +#define GPMCFCLKDIVIDER(x) (((x) & 3) << 0) + +/* Values for GPMC_CONFIG2 - CS timing */ +#define CSWROFFTIME(x) (((x) & 0x1f) << 16) +#define CSRDOFFTIME(x) (((x) & 0x1f) << 8) +#define CSEXTRADELAY (1 << 7) +#define CSONTIME(x) (((x) & 0xf) << 0) + +/* Values for GPMC_CONFIG3 - nADV timing */ +#define ADVWROFFTIME(x) (((x) & 0x1f) << 16) +#define ADVRDOFFTIME(x) (((x) & 0x1f) << 8) +#define ADVEXTRADELAY (1 << 7) +#define ADVONTIME(x) (((x) & 0xf) << 0) + +/* Values for GPMC_CONFIG4 - nWE and nOE timing */ +#define WEOFFTIME(x) (((x) & 0x1f) << 24) +#define WEEXTRADELAY (1 << 23) +#define WEONTIME(x) (((x) & 0xf) << 16) +#define OEOFFTIME(x) (((x) & 0x1f) << 8) +#define OEEXTRADELAY (1 << 7) +#define OEONTIME(x) (((x) & 0xf) << 0) + +/* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */ +#define PAGEBURSTACCESSTIME(x) (((x) & 0xf) << 24) +#define RDACCESSTIME(x) (((x) & 0x1f) << 16) +#define WRCYCLETIME(x) (((x) & 0x1f) << 8) +#define RDCYCLETIME(x) (((x) & 0x1f) << 0) + +/* Values for GPMC_CONFIG6 - misc timings */ +#define WRACCESSTIME(x) (((x) & 0x1f) << 24) +#define WRDATAONADMUXBUS(x) (((x) & 0xf) << 16) +#define CYCLE2CYCLEDELAY(x) (((x) & 0xf) << 8) +#define CYCLE2CYCLESAMECSEN (1 << 7) +#define CYCLE2CYCLEDIFFCSEN (1 << 6) +#define BUSTURNAROUND(x) (((x) & 0xf) << 0) + +/* Values for GPMC_CONFIG7 - CS address mapping configuration */ +#define MASKADDRESS(x) (((x) & 0xf) << 8) +#define CSVALID (1 << 6) +#define BASEADDRESS(x) (((x) & 0x3f) << 0) + +#endif /* _OMAP3_REGS_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap3/spl.h b/roms/u-boot/arch/arm/include/asm/arch-omap3/spl.h new file mode 100644 index 000000000..86b1f4674 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap3/spl.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Texas Instruments, + */ +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_ARCH_SPL_H_ + +#define BOOT_DEVICE_NONE 0x00 +#define BOOT_DEVICE_XIP 0x01 +#define BOOT_DEVICE_NAND 0x02 +#define BOOT_DEVICE_ONENAND 0x03 +#define BOOT_DEVICE_MMC2 0x05 +#define BOOT_DEVICE_MMC1 0x06 +#define BOOT_DEVICE_XIPWAIT 0x07 +#define BOOT_DEVICE_MMC2_2 0x08 +#define BOOT_DEVICE_UART 0x10 +#define BOOT_DEVICE_USB 0x11 + +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap3/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-omap3/sys_proto.h new file mode 100644 index 000000000..32ac03351 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2004-2008 + * Texas Instruments, + * Richard Woodruff + */ +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ +#include +#include + +typedef struct { + u32 mtype; + char *board_string; + char *nand_string; +} omap3_sysinfo; + +struct emu_hal_params { + u32 num_params; + u32 param1; +}; + +/* Board SDRC timing values */ +struct board_sdrc_timings { + u32 sharing; + u32 mcfg; + u32 ctrla; + u32 ctrlb; + u32 rfr_ctrl; + u32 mr; +}; + +void prcm_init(void); +void per_clocks_enable(void); +void ehci_clocks_enable(void); + +void memif_init(void); +void sdrc_init(void); +void do_sdrc_init(u32, u32); + +void get_board_mem_timings(struct board_sdrc_timings *timings); +int identify_nand_chip(int *mfr, int *id); +void emif4_init(void); +void gpmc_init(void); +void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, + u32 base, u32 size); +void set_gpmc_cs0(int flash_type); + +void watchdog_init(void); +void set_muxconf_regs(void); + +u32 get_cpu_family(void); +u32 get_cpu_rev(void); +u32 get_sku_id(void); +u32 is_gpmc_muxed(void); +u32 get_gpmc0_type(void); +u32 get_gpmc0_width(void); +u32 is_running_in_sdram(void); +u32 is_running_in_sram(void); +u32 is_running_in_flash(void); +u32 get_device_type(void); +void secureworld_exit(void); +void try_unlock_memory(void); +u32 get_boot_type(void); +void invalidate_dcache(u32); +u32 wait_on_value(u32, u32, void *, u32); +void cancel_out(u32 *num, u32 *den, u32 den_limit); +void sdelay(unsigned long); +void make_cs1_contiguous(void); +int omap_nand_switch_ecc(uint32_t, uint32_t); +void power_init_r(void); +void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); +void omap3_set_aux_cr_secure(u32 acr); +u32 warm_reset(void); + +void save_omap_boot_params(void); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap4/clock.h b/roms/u-boot/arch/arm/include/asm/arch-omap4/clock.h new file mode 100644 index 000000000..0a626fe64 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap4/clock.h @@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments, + * + * Aneesh V + */ +#ifndef _CLOCKS_OMAP4_H_ +#define _CLOCKS_OMAP4_H_ +#include + +/* + * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per + * loop, allow for a minimum of 2 ms wait (in reality the wait will be + * much more than that) + */ +#define LDELAY 1000000 + +/* CM_DLL_CTRL */ +#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 +#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) +#define CM_DLL_CTRL_NO_OVERRIDE 0 + +/* CM_CLKMODE_DPLL */ +#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 +#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) +#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 +#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) +#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 +#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) +#define CM_CLKMODE_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) + +#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 + +#define DPLL_EN_STOP 1 +#define DPLL_EN_MN_BYPASS 4 +#define DPLL_EN_LOW_POWER_BYPASS 5 +#define DPLL_EN_FAST_RELOCK_BYPASS 6 +#define DPLL_EN_LOCK 7 + +/* CM_IDLEST_DPLL fields */ +#define ST_DPLL_CLK_MASK 1 + +/* CM_CLKSEL_DPLL */ +#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 +#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) +#define CM_CLKSEL_DPLL_M_SHIFT 8 +#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) +#define CM_CLKSEL_DPLL_N_SHIFT 0 +#define CM_CLKSEL_DPLL_N_MASK 0x7F +#define CM_CLKSEL_DCC_EN_SHIFT 22 +#define CM_CLKSEL_DCC_EN_MASK (1 << 22) + +/* CM_SYS_CLKSEL */ +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 + +/* CM_CLKSEL_CORE */ +#define CLKSEL_CORE_SHIFT 0 +#define CLKSEL_L3_SHIFT 4 +#define CLKSEL_L4_SHIFT 8 + +#define CLKSEL_CORE_X2_DIV_1 0 +#define CLKSEL_L3_CORE_DIV_2 1 +#define CLKSEL_L4_L3_DIV_2 1 + +/* CM_ABE_PLL_REF_CLKSEL */ +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 + +/* CM_BYPCLK_DPLL_IVA */ +#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 +#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 + +#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 + +/* CM_SHADOW_FREQ_CONFIG1 */ +#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 +#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 +#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 + +#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 +#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) + +#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 +#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) + +/*CM___CLKCTRL */ +#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 +#define CD_CLKCTRL_CLKTRCTRL_MASK 3 + +#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 +#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 +#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 +#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 + + +/* CM___CLKCTRL */ +#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 +#define MODULE_CLKCTRL_MODULEMODE_MASK 3 +#define MODULE_CLKCTRL_IDLEST_SHIFT 16 +#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) + +#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 +#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 +#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 + +#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 +#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 +#define MODULE_CLKCTRL_IDLEST_IDLE 2 +#define MODULE_CLKCTRL_IDLEST_DISABLED 3 + +/* CM_L4PER_GPIO4_CLKCTRL */ +#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + +/* CM_L3INIT_HSMMCn_CLKCTRL */ +#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) + +/* CM_WKUP_GPTIMER1_CLKCTRL */ +#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) + +/* CM_CAM_ISS_CLKCTRL */ +#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + +/* CM_DSS_DSS_CLKCTRL */ +#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 + +/* CM_COREAON_USB_PHY_CORE_CLKCTRL */ +#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) + +/* CM_L3INIT_USBPHY_CLKCTRL */ +#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK (1 << 8) + +/* CM_MPU_MPU_CLKCTRL */ +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) + +/* Clock frequencies */ +#define OMAP_SYS_CLK_IND_38_4_MHZ 6 + +/* PRM_VC_VAL_BYPASS */ +#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 + +/* PMIC */ +#define SMPS_I2C_SLAVE_ADDR 0x12 +/* TWL6030 SMPS */ +#define SMPS_REG_ADDR_VCORE1 0x55 +#define SMPS_REG_ADDR_VCORE2 0x5B +#define SMPS_REG_ADDR_VCORE3 0x61 +/* TWL6032 SMPS */ +#define SMPS_REG_ADDR_SMPS1 0x55 +#define SMPS_REG_ADDR_SMPS2 0x5B +#define SMPS_REG_ADDR_SMPS5 0x49 + +#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 +#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 + +/* TPS */ +#define TPS62361_I2C_SLAVE_ADDR 0x60 +#define TPS62361_REG_ADDR_SET0 0x0 +#define TPS62361_REG_ADDR_SET1 0x1 +#define TPS62361_REG_ADDR_SET2 0x2 +#define TPS62361_REG_ADDR_SET3 0x3 +#define TPS62361_REG_ADDR_CTRL 0x4 +#define TPS62361_REG_ADDR_TEMP 0x5 +#define TPS62361_REG_ADDR_RMP_CTRL 0x6 +#define TPS62361_REG_ADDR_CHIP_ID 0x8 +#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 + +#define TPS62361_BASE_VOLT_MV 500 +#define TPS62361_VSEL0_GPIO 7 + +/* AUXCLKx reg fields */ +#define AUXCLK_ENABLE_MASK (1 << 8) +#define AUXCLK_SRCSELECT_SHIFT 1 +#define AUXCLK_SRCSELECT_MASK (3 << 1) +#define AUXCLK_CLKDIV_SHIFT 16 +#define AUXCLK_CLKDIV_MASK (0xF << 16) + +#define AUXCLK_SRCSELECT_SYS_CLK 0 +#define AUXCLK_SRCSELECT_CORE_DPLL 1 +#define AUXCLK_SRCSELECT_PER_DPLL 2 +#define AUXCLK_SRCSELECT_ALTERNATE 3 + +#define AUXCLK_CLKDIV_2 1 +#define AUXCLK_CLKDIV_16 0xF + +/* ALTCLKSRC */ +#define ALTCLKSRC_MODE_MASK 3 +#define ALTCLKSRC_ENABLE_INT_MASK 4 +#define ALTCLKSRC_ENABLE_EXT_MASK 8 + +#define ALTCLKSRC_MODE_ACTIVE 1 + +#define DPLL_NO_LOCK 0 +#define DPLL_LOCK 1 + +/* Clock Defines */ +#define V_OSCK 38400000 /* Clock output from T2 */ +#define V_SCLK V_OSCK + +struct omap4_scrm_regs { + u32 revision; /* 0x0000 */ + u32 pad00[63]; + u32 clksetuptime; /* 0x0100 */ + u32 pmicsetuptime; /* 0x0104 */ + u32 pad01[2]; + u32 altclksrc; /* 0x0110 */ + u32 pad02[2]; + u32 c2cclkm; /* 0x011c */ + u32 pad03[56]; + u32 extclkreq; /* 0x0200 */ + u32 accclkreq; /* 0x0204 */ + u32 pwrreq; /* 0x0208 */ + u32 pad04[1]; + u32 auxclkreq0; /* 0x0210 */ + u32 auxclkreq1; /* 0x0214 */ + u32 auxclkreq2; /* 0x0218 */ + u32 auxclkreq3; /* 0x021c */ + u32 auxclkreq4; /* 0x0220 */ + u32 auxclkreq5; /* 0x0224 */ + u32 pad05[3]; + u32 c2cclkreq; /* 0x0234 */ + u32 pad06[54]; + u32 auxclk0; /* 0x0310 */ + u32 auxclk1; /* 0x0314 */ + u32 auxclk2; /* 0x0318 */ + u32 auxclk3; /* 0x031c */ + u32 auxclk4; /* 0x0320 */ + u32 auxclk5; /* 0x0324 */ + u32 pad07[54]; + u32 rsttime_reg; /* 0x0400 */ + u32 pad08[6]; + u32 c2crstctrl; /* 0x041c */ + u32 extpwronrstctrl; /* 0x0420 */ + u32 pad09[59]; + u32 extwarmrstst_reg; /* 0x0510 */ + u32 apewarmrstst_reg; /* 0x0514 */ + u32 pad10[1]; + u32 c2cwarmrstst_reg; /* 0x051C */ +}; +#endif /* _CLOCKS_OMAP4_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap4/cpu.h b/roms/u-boot/arch/arm/include/asm/arch-omap4/cpu.h new file mode 100644 index 000000000..4c9ed4558 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap4/cpu.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2010 + * Texas Instruments, + */ + +#ifndef _CPU_H +#define _CPU_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +#include + +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct gptimer { + u32 tidr; /* 0x00 r */ + u8 res[0xc]; + u32 tiocp_cfg; /* 0x10 rw */ + u32 tistat; /* 0x14 r */ + u32 tisr; /* 0x18 rw */ + u32 tier; /* 0x1c rw */ + u32 twer; /* 0x20 rw */ + u32 tclr; /* 0x24 rw */ + u32 tcrr; /* 0x28 rw */ + u32 tldr; /* 0x2c rw */ + u32 ttgr; /* 0x30 rw */ + u32 twpc; /* 0x34 r */ + u32 tmar; /* 0x38 rw */ + u32 tcar1; /* 0x3c r */ + u32 tcicr; /* 0x40 rw */ + u32 tcar2; /* 0x44 r */ +}; +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +/* enable sys_clk NO-prescale /1 */ +#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) + +/* Watchdog */ +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct watchdog { + u8 res1[0x34]; + u32 wwps; /* 0x34 r */ + u8 res2[0x10]; + u32 wspr; /* 0x48 rw */ +}; +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +#define TCLR_ST (0x1 << 0) +#define TCLR_AR (0x1 << 1) +#define TCLR_PRE (0x1 << 5) + +/* I2C base */ +#define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000) +#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000) +#define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000) +#define I2C_BASE4 (OMAP44XX_L4_PER_BASE + 0x350000) + +/* MUSB base */ +#define MUSB_BASE (OMAP44XX_L4_CORE_BASE + 0xAB000) + +/* OMAP4 GPIO registers */ +#define OMAP_GPIO_REVISION 0x0000 +#define OMAP_GPIO_SYSCONFIG 0x0010 +#define OMAP_GPIO_SYSSTATUS 0x0114 +#define OMAP_GPIO_IRQSTATUS1 0x0118 +#define OMAP_GPIO_IRQSTATUS2 0x0128 +#define OMAP_GPIO_IRQENABLE2 0x012c +#define OMAP_GPIO_IRQENABLE1 0x011c +#define OMAP_GPIO_WAKE_EN 0x0120 +#define OMAP_GPIO_CTRL 0x0130 +#define OMAP_GPIO_OE 0x0134 +#define OMAP_GPIO_DATAIN 0x0138 +#define OMAP_GPIO_DATAOUT 0x013c +#define OMAP_GPIO_LEVELDETECT0 0x0140 +#define OMAP_GPIO_LEVELDETECT1 0x0144 +#define OMAP_GPIO_RISINGDETECT 0x0148 +#define OMAP_GPIO_FALLINGDETECT 0x014c +#define OMAP_GPIO_DEBOUNCE_EN 0x0150 +#define OMAP_GPIO_DEBOUNCE_VAL 0x0154 +#define OMAP_GPIO_CLEARIRQENABLE1 0x0160 +#define OMAP_GPIO_SETIRQENABLE1 0x0164 +#define OMAP_GPIO_CLEARWKUENA 0x0180 +#define OMAP_GPIO_SETWKUENA 0x0184 +#define OMAP_GPIO_CLEARDATAOUT 0x0190 +#define OMAP_GPIO_SETDATAOUT 0x0194 + +/* + * PRCM + */ + +/* PRM */ +#define PRM_BASE 0x4A306000 +#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) + +#define PRM_RSTCTRL PRM_DEVICE_BASE +#define PRM_RSTCTRL_RESET 0x01 +#define PRM_RSTST (PRM_DEVICE_BASE + 0x4) +#define PRM_RSTST_WARM_RESET_MASK 0x07EA + +#endif /* _CPU_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap4/ehci.h b/roms/u-boot/arch/arm/include/asm/arch-omap4/ehci.h new file mode 100644 index 000000000..30bdaad64 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap4/ehci.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * OMAP EHCI port support + * Based on LINUX KERNEL + * drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com + * Author: Govindraj R + */ + +#ifndef _OMAP4_EHCI_H_ +#define _OMAP4_EHCI_H_ + +#define OMAP_EHCI_BASE (OMAP44XX_L4_CORE_BASE + 0x64C00) +#define OMAP_UHH_BASE (OMAP44XX_L4_CORE_BASE + 0x64000) +#define OMAP_USBTLL_BASE (OMAP44XX_L4_CORE_BASE + 0x62000) + +/* UHH, TLL and opt clocks */ +#define CM_L3INIT_HSUSBHOST_CLKCTRL 0x4A009358UL + +#define HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK (1 << 24) + +/* TLL Register Set */ +#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) +#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) +#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) +#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) +#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1 + +#define OMAP_UHH_SYSCONFIG_SOFTRESET 1 +#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2) +#define OMAP_UHH_SYSCONFIG_NOIDLE (1 << 2) +#define OMAP_UHH_SYSCONFIG_NOSTDBY (1 << 4) + +#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_NOIDLE | \ + OMAP_UHH_SYSCONFIG_NOSTDBY) + +#endif /* _OMAP4_EHCI_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap4/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-omap4/gpio.h new file mode 100644 index 000000000..aceb3e227 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap4/gpio.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This work is derived from the linux 2.6.27 kernel source + * To fetch, use the kernel repository + * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git + * Use the v2.6.27 tag. + * + * Below is the original's header including its copyright + * + * linux/arch/arm/plat-omap/gpio.c + * + * Support functions for OMAP GPIO + * + * Copyright (C) 2003-2005 Nokia Corporation + * Written by Juha Yrjölä + */ +#ifndef _GPIO_OMAP4_H +#define _GPIO_OMAP4_H + +#include + +#define OMAP_MAX_GPIO 192 + +#define OMAP44XX_GPIO1_BASE 0x4A310000 +#define OMAP44XX_GPIO2_BASE 0x48055000 +#define OMAP44XX_GPIO3_BASE 0x48057000 +#define OMAP44XX_GPIO4_BASE 0x48059000 +#define OMAP44XX_GPIO5_BASE 0x4805B000 +#define OMAP44XX_GPIO6_BASE 0x4805D000 + +#endif /* _GPIO_OMAP4_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap4/hardware.h b/roms/u-boot/arch/arm/include/asm/arch-omap4/hardware.h new file mode 100644 index 000000000..48dc80924 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap4/hardware.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * hardware.h + * + * hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef __OMAP_HARDWARE_H +#define __OMAP_HARDWARE_H + +#include + +/* + * Common hardware definitions + */ + +/* BCH Error Location Module */ +#define ELM_BASE 0x48078000 + +/* GPMC Base address */ +#define GPMC_BASE 0x50000000 + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap4/i2c.h b/roms/u-boot/arch/arm/include/asm/arch-omap4/i2c.h new file mode 100644 index 000000000..c8f2f9716 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap4/i2c.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2004-2010 + * Texas Instruments, + */ +#ifndef _OMAP4_I2C_H_ +#define _OMAP4_I2C_H_ + +#define I2C_DEFAULT_BASE I2C_BASE1 + +#endif /* _OMAP4_I2C_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap4/mem.h b/roms/u-boot/arch/arm/include/asm/arch-omap4/mem.h new file mode 100644 index 000000000..3026a002d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap4/mem.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, + * + * Author + * Mansoor Ahamed + * + * Initial Code from: + * Richard Woodruff + */ + +#ifndef _MEM_H_ +#define _MEM_H_ + +/* + * GPMC settings - + * Definitions is as per the following format + * #define _GPMC_CONFIG + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should + * go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * M_NAND - Micron NAND + * STNOR - STMicrolelctronics M29W128GL + */ +#define GPMC_SIZE_256M 0x0 +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#define M_NAND_GPMC_CONFIG1 0x00000800 +#define M_NAND_GPMC_CONFIG2 0x001e1e00 +#define M_NAND_GPMC_CONFIG3 0x001e1e00 +#define M_NAND_GPMC_CONFIG4 0x16051807 +#define M_NAND_GPMC_CONFIG5 0x00151e1e +#define M_NAND_GPMC_CONFIG6 0x16000f80 +#define M_NAND_GPMC_CONFIG7 0x00000008 + +#define STNOR_GPMC_CONFIG1 0x00001200 +#define STNOR_GPMC_CONFIG2 0x00101000 +#define STNOR_GPMC_CONFIG3 0x00030301 +#define STNOR_GPMC_CONFIG4 0x10041004 +#define STNOR_GPMC_CONFIG5 0x000C1010 +#define STNOR_GPMC_CONFIG6 0x08070280 +#define STNOR_GPMC_CONFIG7 0x00000F48 + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#endif /* endif _MEM_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/roms/u-boot/arch/arm/include/asm/arch-omap4/mmc_host_def.h new file mode 100644 index 000000000..d06779956 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap4/mmc_host_def.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MMC_HOST_DEF_H +#define MMC_HOST_DEF_H + +#include + +/* + * OMAP HSMMC register definitions + */ + +#define OMAP_HSMMC1_BASE 0x4809C000 +#define OMAP_HSMMC2_BASE 0x480B4000 +#define OMAP_HSMMC3_BASE 0x480AD000 + +#endif /* MMC_HOST_DEF_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap4/mux_omap4.h b/roms/u-boot/arch/arm/include/asm/arch-omap4/mux_omap4.h new file mode 100644 index 000000000..854203c4e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap4/mux_omap4.h @@ -0,0 +1,328 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2004-2009 + * Texas Instruments Incorporated + * Richard Woodruff + * Aneesh V + * Balaji Krishnamoorthy + */ +#ifndef _MUX_OMAP4_H_ +#define _MUX_OMAP4_H_ + +#include + +struct pad_conf_entry { + + u16 offset; + + u16 val; + +}; + +#ifdef CONFIG_OFF_PADCONF +#define OFF_PD (1 << 12) +#define OFF_PU (3 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (2 << 10) +#define OFF_IN (1 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (1 << 9) +#else +#define OFF_PD (0 << 12) +#define OFF_PU (0 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (0 << 10) +#define OFF_IN (0 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (0 << 9) +#endif + +#define IEN (1 << 8) +#define IDIS (0 << 8) +#define PTU (3 << 3) +#define PTD (1 << 3) +#define EN (1 << 3) +#define DIS (0 << 3) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 + +#define SAFE_MODE M7 + +#ifdef CONFIG_OFF_PADCONF +#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) +#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) +#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) +#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) +#else +#define OFF_IN_PD 0 +#define OFF_IN_PU 0 +#define OFF_OUT_PD 0 +#define OFF_OUT_PU 0 +#endif + +#define CORE_REVISION 0x0000 +#define CORE_HWINFO 0x0004 +#define CORE_SYSCONFIG 0x0010 +#define GPMC_AD0 0x0040 +#define GPMC_AD1 0x0042 +#define GPMC_AD2 0x0044 +#define GPMC_AD3 0x0046 +#define GPMC_AD4 0x0048 +#define GPMC_AD5 0x004A +#define GPMC_AD6 0x004C +#define GPMC_AD7 0x004E +#define GPMC_AD8 0x0050 +#define GPMC_AD9 0x0052 +#define GPMC_AD10 0x0054 +#define GPMC_AD11 0x0056 +#define GPMC_AD12 0x0058 +#define GPMC_AD13 0x005A +#define GPMC_AD14 0x005C +#define GPMC_AD15 0x005E +#define GPMC_A16 0x0060 +#define GPMC_A17 0x0062 +#define GPMC_A18 0x0064 +#define GPMC_A19 0x0066 +#define GPMC_A20 0x0068 +#define GPMC_A21 0x006A +#define GPMC_A22 0x006C +#define GPMC_A23 0x006E +#define GPMC_A24 0x0070 +#define GPMC_A25 0x0072 +#define GPMC_NCS0 0x0074 +#define GPMC_NCS1 0x0076 +#define GPMC_NCS2 0x0078 +#define GPMC_NCS3 0x007A +#define GPMC_NWP 0x007C +#define GPMC_CLK 0x007E +#define GPMC_NADV_ALE 0x0080 +#define GPMC_NOE 0x0082 +#define GPMC_NWE 0x0084 +#define GPMC_NBE0_CLE 0x0086 +#define GPMC_NBE1 0x0088 +#define GPMC_WAIT0 0x008A +#define GPMC_WAIT1 0x008C +#define C2C_DATA11 0x008E +#define C2C_DATA12 0x0090 +#define C2C_DATA13 0x0092 +#define C2C_DATA14 0x0094 +#define C2C_DATA15 0x0096 +#define HDMI_HPD 0x0098 +#define HDMI_CEC 0x009A +#define HDMI_DDC_SCL 0x009C +#define HDMI_DDC_SDA 0x009E +#define CSI21_DX0 0x00A0 +#define CSI21_DY0 0x00A2 +#define CSI21_DX1 0x00A4 +#define CSI21_DY1 0x00A6 +#define CSI21_DX2 0x00A8 +#define CSI21_DY2 0x00AA +#define CSI21_DX3 0x00AC +#define CSI21_DY3 0x00AE +#define CSI21_DX4 0x00B0 +#define CSI21_DY4 0x00B2 +#define CSI22_DX0 0x00B4 +#define CSI22_DY0 0x00B6 +#define CSI22_DX1 0x00B8 +#define CSI22_DY1 0x00BA +#define CAM_SHUTTER 0x00BC +#define CAM_STROBE 0x00BE +#define CAM_GLOBALRESET 0x00C0 +#define USBB1_ULPITLL_CLK 0x00C2 +#define USBB1_ULPITLL_STP 0x00C4 +#define USBB1_ULPITLL_DIR 0x00C6 +#define USBB1_ULPITLL_NXT 0x00C8 +#define USBB1_ULPITLL_DAT0 0x00CA +#define USBB1_ULPITLL_DAT1 0x00CC +#define USBB1_ULPITLL_DAT2 0x00CE +#define USBB1_ULPITLL_DAT3 0x00D0 +#define USBB1_ULPITLL_DAT4 0x00D2 +#define USBB1_ULPITLL_DAT5 0x00D4 +#define USBB1_ULPITLL_DAT6 0x00D6 +#define USBB1_ULPITLL_DAT7 0x00D8 +#define USBB1_HSIC_DATA 0x00DA +#define USBB1_HSIC_STROBE 0x00DC +#define USBC1_ICUSB_DP 0x00DE +#define USBC1_ICUSB_DM 0x00E0 +#define SDMMC1_CLK 0x00E2 +#define SDMMC1_CMD 0x00E4 +#define SDMMC1_DAT0 0x00E6 +#define SDMMC1_DAT1 0x00E8 +#define SDMMC1_DAT2 0x00EA +#define SDMMC1_DAT3 0x00EC +#define SDMMC1_DAT4 0x00EE +#define SDMMC1_DAT5 0x00F0 +#define SDMMC1_DAT6 0x00F2 +#define SDMMC1_DAT7 0x00F4 +#define ABE_MCBSP2_CLKX 0x00F6 +#define ABE_MCBSP2_DR 0x00F8 +#define ABE_MCBSP2_DX 0x00FA +#define ABE_MCBSP2_FSX 0x00FC +#define ABE_MCBSP1_CLKX 0x00FE +#define ABE_MCBSP1_DR 0x0100 +#define ABE_MCBSP1_DX 0x0102 +#define ABE_MCBSP1_FSX 0x0104 +#define ABE_PDM_UL_DATA 0x0106 +#define ABE_PDM_DL_DATA 0x0108 +#define ABE_PDM_FRAME 0x010A +#define ABE_PDM_LB_CLK 0x010C +#define ABE_CLKS 0x010E +#define ABE_DMIC_CLK1 0x0110 +#define ABE_DMIC_DIN1 0x0112 +#define ABE_DMIC_DIN2 0x0114 +#define ABE_DMIC_DIN3 0x0116 +#define UART2_CTS 0x0118 +#define UART2_RTS 0x011A +#define UART2_RX 0x011C +#define UART2_TX 0x011E +#define HDQ_SIO 0x0120 +#define I2C1_SCL 0x0122 +#define I2C1_SDA 0x0124 +#define I2C2_SCL 0x0126 +#define I2C2_SDA 0x0128 +#define I2C3_SCL 0x012A +#define I2C3_SDA 0x012C +#define I2C4_SCL 0x012E +#define I2C4_SDA 0x0130 +#define MCSPI1_CLK 0x0132 +#define MCSPI1_SOMI 0x0134 +#define MCSPI1_SIMO 0x0136 +#define MCSPI1_CS0 0x0138 +#define MCSPI1_CS1 0x013A +#define MCSPI1_CS2 0x013C +#define MCSPI1_CS3 0x013E +#define UART3_CTS_RCTX 0x0140 +#define UART3_RTS_SD 0x0142 +#define UART3_RX_IRRX 0x0144 +#define UART3_TX_IRTX 0x0146 +#define SDMMC5_CLK 0x0148 +#define SDMMC5_CMD 0x014A +#define SDMMC5_DAT0 0x014C +#define SDMMC5_DAT1 0x014E +#define SDMMC5_DAT2 0x0150 +#define SDMMC5_DAT3 0x0152 +#define MCSPI4_CLK 0x0154 +#define MCSPI4_SIMO 0x0156 +#define MCSPI4_SOMI 0x0158 +#define MCSPI4_CS0 0x015A +#define UART4_RX 0x015C +#define UART4_TX 0x015E +#define USBB2_ULPITLL_CLK 0x0160 +#define USBB2_ULPITLL_STP 0x0162 +#define USBB2_ULPITLL_DIR 0x0164 +#define USBB2_ULPITLL_NXT 0x0166 +#define USBB2_ULPITLL_DAT0 0x0168 +#define USBB2_ULPITLL_DAT1 0x016A +#define USBB2_ULPITLL_DAT2 0x016C +#define USBB2_ULPITLL_DAT3 0x016E +#define USBB2_ULPITLL_DAT4 0x0170 +#define USBB2_ULPITLL_DAT5 0x0172 +#define USBB2_ULPITLL_DAT6 0x0174 +#define USBB2_ULPITLL_DAT7 0x0176 +#define USBB2_HSIC_DATA 0x0178 +#define USBB2_HSIC_STROBE 0x017A +#define UNIPRO_TX0 0x017C +#define UNIPRO_TY0 0x017E +#define UNIPRO_TX1 0x0180 +#define UNIPRO_TY1 0x0182 +#define UNIPRO_TX2 0x0184 +#define UNIPRO_TY2 0x0186 +#define UNIPRO_RX0 0x0188 +#define UNIPRO_RY0 0x018A +#define UNIPRO_RX1 0x018C +#define UNIPRO_RY1 0x018E +#define UNIPRO_RX2 0x0190 +#define UNIPRO_RY2 0x0192 +#define USBA0_OTG_CE 0x0194 +#define USBA0_OTG_DP 0x0196 +#define USBA0_OTG_DM 0x0198 +#define FREF_CLK1_OUT 0x019A +#define FREF_CLK2_OUT 0x019C +#define SYS_NIRQ1 0x019E +#define SYS_NIRQ2 0x01A0 +#define SYS_BOOT0 0x01A2 +#define SYS_BOOT1 0x01A4 +#define SYS_BOOT2 0x01A6 +#define SYS_BOOT3 0x01A8 +#define SYS_BOOT4 0x01AA +#define SYS_BOOT5 0x01AC +#define DPM_EMU0 0x01AE +#define DPM_EMU1 0x01B0 +#define DPM_EMU2 0x01B2 +#define DPM_EMU3 0x01B4 +#define DPM_EMU4 0x01B6 +#define DPM_EMU5 0x01B8 +#define DPM_EMU6 0x01BA +#define DPM_EMU7 0x01BC +#define DPM_EMU8 0x01BE +#define DPM_EMU9 0x01C0 +#define DPM_EMU10 0x01C2 +#define DPM_EMU11 0x01C4 +#define DPM_EMU12 0x01C6 +#define DPM_EMU13 0x01C8 +#define DPM_EMU14 0x01CA +#define DPM_EMU15 0x01CC +#define DPM_EMU16 0x01CE +#define DPM_EMU17 0x01D0 +#define DPM_EMU18 0x01D2 +#define DPM_EMU19 0x01D4 +#define WAKEUPEVENT_0 0x01D8 +#define WAKEUPEVENT_1 0x01DC +#define WAKEUPEVENT_2 0x01E0 +#define WAKEUPEVENT_3 0x01E4 +#define WAKEUPEVENT_4 0x01E8 +#define WAKEUPEVENT_5 0x01EC +#define WAKEUPEVENT_6 0x01F0 + +#define WKUP_REVISION 0x0000 +#define WKUP_HWINFO 0x0004 +#define WKUP_SYSCONFIG 0x0010 +#define PAD0_SIM_IO 0x0040 +#define PAD1_SIM_CLK 0x0042 +#define PAD0_SIM_RESET 0x0044 +#define PAD1_SIM_CD 0x0046 +#define PAD0_SIM_PWRCTRL 0x0048 +#define PAD1_SR_SCL 0x004A +#define PAD0_SR_SDA 0x004C +#define PAD1_FREF_XTAL_IN 0x004E +#define PAD0_FREF_SLICER_IN 0x0050 +#define PAD1_FREF_CLK_IOREQ 0x0052 +#define PAD0_FREF_CLK0_OUT 0x0054 +#define PAD1_FREF_CLK3_REQ 0x0056 +#define PAD0_FREF_CLK3_OUT 0x0058 +#define PAD1_FREF_CLK4_REQ 0x005A +#define PAD0_FREF_CLK4_OUT 0x005C +#define PAD1_SYS_32K 0x005E +#define PAD0_SYS_NRESPWRON 0x0060 +#define PAD1_SYS_NRESWARM 0x0062 +#define PAD0_SYS_PWR_REQ 0x0064 +#define PAD1_SYS_PWRON_RESET 0x0066 +#define PAD0_SYS_BOOT6 0x0068 +#define PAD1_SYS_BOOT7 0x006A +#define PAD0_JTAG_NTRST 0x006C +#define PAD1_JTAG_TCK 0x006D +#define PAD0_JTAG_RTCK 0x0070 +#define PAD1_JTAG_TMS_TMSC 0x0072 +#define PAD0_JTAG_TDI 0x0074 +#define PAD1_JTAG_TDO 0x0076 +#define PADCONF_WAKEUPEVENT_0 0x007C +#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 +#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 +#define PADCONF_MODE 0x05A8 +#define CONTROL_XTAL_OSCILLATOR 0x05AC +#define CONTROL_CONTROL_I2C_2 0x0604 +#define CONTROL_CONTROL_JTAG 0x0608 +#define CONTROL_CONTROL_SYS 0x060C +#define CONTROL_SPARE_RW 0x0614 +#define CONTROL_SPARE_R 0x0618 +#define CONTROL_SPARE_R_C0 0x061C + +#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ 0x4A31E05A +#endif /* _MUX_OMAP4_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap4/omap.h b/roms/u-boot/arch/arm/include/asm/arch-omap4/omap.h new file mode 100644 index 000000000..8919088a7 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap4/omap.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments, + * + * Authors: + * Aneesh V + * + * Derived from OMAP3 work by + * Richard Woodruff + * Syed Mohammed Khasim + */ + +#ifndef _OMAP4_H_ +#define _OMAP4_H_ + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +#include + +/* + * L4 Peripherals - L4 Wakeup and L4 Core now + */ +#define OMAP44XX_L4_CORE_BASE 0x4A000000 +#define OMAP44XX_L4_WKUP_BASE 0x4A300000 +#define OMAP44XX_L4_PER_BASE 0x48000000 + +#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000 +#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000 +#define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START +#define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END + +/* CONTROL_ID_CODE */ +#define CONTROL_ID_CODE 0x4A002204 + +#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F +#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F +#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F +#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F +#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F +#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F +#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F +#define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F + +/* UART */ +#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) +#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) +#define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000) + +/* General Purpose Timers */ +#define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000) +#define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000) +#define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000) + +/* Watchdog Timer2 - MPU watchdog */ +#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) + +/* + * Hardware Register Details + */ + +/* Watchdog Timer */ +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* GP Timer */ +#define TCLR_ST (0x1 << 0) +#define TCLR_AR (0x1 << 1) +#define TCLR_PRE (0x1 << 5) + +/* Control Module */ +#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) +#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f +#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 +#define CONTROL_EFUSE_2_OVERRIDE 0x99084000 + +/* LPDDR2 IO regs */ +#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C +#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E +#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C +#define LPDDR2IO_GR10_WD_MASK (3 << 17) +#define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F + +/* CONTROL_EFUSE_2 */ +#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 + +#define MMC1_PWRDNZ (1 << 26) +#define MMC1_PBIASLITE_PWRDNZ (1 << 22) +#define MMC1_PBIASLITE_VMODE (1 << 21) + +#ifndef __ASSEMBLY__ + +struct s32ktimer { + unsigned char res[0x10]; + unsigned int s32k_cr; /* 0x10 */ +}; + +#define DEVICE_TYPE_SHIFT (0x8) +#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) + +#endif /* __ASSEMBLY__ */ + +/* + * Non-secure SRAM Addresses + * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE + * at 0x40304000(EMU base) so that our code works for both EMU and GP + */ +#define NON_SECURE_SRAM_START 0x40304000 +#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ +#define NON_SECURE_SRAM_IMG_END 0x4030C000 +#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K) +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_ROM_VECT_BASE 0x4030D000 + +/* ABB settings */ +#define OMAP_ABB_SETTLING_TIME 50 +#define OMAP_ABB_CLOCK_CYCLES 16 + +/* ABB tranxdone mask */ +#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) + +#define OMAP44XX_SAR_RAM_BASE 0x4a326000 +#define OMAP_REBOOT_REASON_OFFSET 0xA0C +#define OMAP_REBOOT_REASON_SIZE 0x0F + +/* Boot parameters */ +#ifndef __ASSEMBLY__ +struct omap_boot_parameters { + unsigned int boot_message; + unsigned int boot_device_descriptor; + unsigned char boot_device; + unsigned char reset_reason; + unsigned char ch_flags; +}; + +int omap_reboot_mode(char *mode, unsigned int length); +int omap_reboot_mode_clear(void); +int omap_reboot_mode_store(char *mode); +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap4/spl.h b/roms/u-boot/arch/arm/include/asm/arch-omap4/spl.h new file mode 100644 index 000000000..d24944af0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap4/spl.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Texas Instruments, + */ +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_ARCH_SPL_H_ + +#define BOOT_DEVICE_NONE 0x00 +#define BOOT_DEVICE_XIP 0x01 +#define BOOT_DEVICE_XIPWAIT 0x02 +#define BOOT_DEVICE_NAND 0x03 +#define BOOT_DEVICE_ONENAND 0x04 +#define BOOT_DEVICE_MMC1 0x05 +#define BOOT_DEVICE_MMC2 0x06 +#define BOOT_DEVICE_MMC2_2 0x07 +#define BOOT_DEVICE_UART 0x43 +#define BOOT_DEVICE_USB 0x45 + +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2 +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap4/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-omap4/sys_proto.h new file mode 100644 index 000000000..b2a688765 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments, + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +extern const struct emif_regs emif_regs_elpida_200_mhz_2cs; +extern const struct emif_regs emif_regs_elpida_380_mhz_1cs; +extern const struct emif_regs emif_regs_elpida_400_mhz_1cs; +extern const struct emif_regs emif_regs_elpida_400_mhz_2cs; +extern const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2; +extern const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2; +extern const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2; +#else +extern const struct lpddr2_device_details elpida_2G_S4_details; +extern const struct lpddr2_device_details elpida_4G_S4_details; +#endif + +#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +extern const struct lpddr2_device_timings jedec_default_timings; +#else +extern const struct lpddr2_device_timings elpida_2G_S4_timings; +#endif + +struct omap_sysinfo { + char *board_string; +}; +extern const struct omap_sysinfo sysinfo; + +void gpmc_init(void); +void watchdog_init(void); +u32 get_device_type(void); +void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); +void set_muxconf_regs(void); +u32 wait_on_value(u32, u32, void *, u32); +void sdelay(unsigned long); +void setup_early_clocks(void); +void prcm_init(void); +void do_board_detect(void); +void bypass_dpll(u32 const base); +void freq_update_core(void); +u32 get_sys_clk_freq(void); +u32 omap4_ddr_clk(void); +void cancel_out(u32 *num, u32 *den, u32 den_limit); +void sdram_init(void); +u32 omap_sdram_size(void); +u32 cortex_rev(void); +void save_omap_boot_params(void); +void init_omap_revision(void); +void do_io_settings(void); +void sri2c_init(void); +int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); +u32 warm_reset(void); +void force_emif_self_refresh(void); +void setup_warmreset_time(void); + +#define OMAP4_SERVICE_PL310_CONTROL_REG_SET 0x102 + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap5/clock.h b/roms/u-boot/arch/arm/include/asm/arch-omap5/clock.h new file mode 100644 index 000000000..87eb3f335 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap5/clock.h @@ -0,0 +1,416 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments, + * + * Aneesh V + * Sricharan R + */ +#ifndef _CLOCKS_OMAP5_H_ +#define _CLOCKS_OMAP5_H_ +#include + +/* + * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per + * loop, allow for a minimum of 2 ms wait (in reality the wait will be + * much more than that) + */ +#define LDELAY 1000000 + +/* CM_DLL_CTRL */ +#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 +#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) +#define CM_DLL_CTRL_NO_OVERRIDE 0 + +/* CM_CLKMODE_DPLL */ +#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 +#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) +#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 +#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) +#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 +#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) +#define CM_CLKMODE_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) + +#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 + +#define DPLL_EN_STOP 1 +#define DPLL_EN_MN_BYPASS 4 +#define DPLL_EN_LOW_POWER_BYPASS 5 +#define DPLL_EN_FAST_RELOCK_BYPASS 6 +#define DPLL_EN_LOCK 7 + +/* CM_IDLEST_DPLL fields */ +#define ST_DPLL_CLK_MASK 1 + +/* SGX */ +#define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) +#define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) + +/* CM_CLKSEL_DPLL */ +#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 +#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) +#define CM_CLKSEL_DPLL_M_SHIFT 8 +#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) +#define CM_CLKSEL_DPLL_N_SHIFT 0 +#define CM_CLKSEL_DPLL_N_MASK 0x7F +#define CM_CLKSEL_DCC_EN_SHIFT 22 +#define CM_CLKSEL_DCC_EN_MASK (1 << 22) + +/* CM_SYS_CLKSEL */ +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 + +/* CM_CLKSEL_CORE */ +#define CLKSEL_CORE_SHIFT 0 +#define CLKSEL_L3_SHIFT 4 +#define CLKSEL_L4_SHIFT 8 + +#define CLKSEL_CORE_X2_DIV_1 0 +#define CLKSEL_L3_CORE_DIV_2 1 +#define CLKSEL_L4_L3_DIV_2 1 + +/* CM_ABE_PLL_REF_CLKSEL */ +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 + +/* CM_CLKSEL_ABE_PLL_SYS */ +#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT 0 +#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK 1 +#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1 0 +#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2 1 + +/* CM_BYPCLK_DPLL_IVA */ +#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 +#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 + +#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 + +/* CM_SHADOW_FREQ_CONFIG1 */ +#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 +#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 +#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 + +#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 +#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) + +#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 +#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) + +/*CM___CLKCTRL */ +#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 +#define CD_CLKCTRL_CLKTRCTRL_MASK 3 + +#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 +#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 +#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 +#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 + + +/* CM___CLKCTRL */ +#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 +#define MODULE_CLKCTRL_MODULEMODE_MASK 3 +#define MODULE_CLKCTRL_IDLEST_SHIFT 16 +#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) + +#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 +#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 +#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 + +#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 +#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 +#define MODULE_CLKCTRL_IDLEST_IDLE 2 +#define MODULE_CLKCTRL_IDLEST_DISABLED 3 + +/* CM_L4PER_GPIO4_CLKCTRL */ +#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + +/* CM_L3INIT_HSMMCn_CLKCTRL */ +#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) +#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25) + +/* CM_L3INIT_SATA_CLKCTRL */ +#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + +/* CM_WKUP_GPTIMER1_CLKCTRL */ +#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) + +/* CM_CAM_ISS_CLKCTRL */ +#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + +/* CM_DSS_DSS_CLKCTRL */ +#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 + +/* CM_L3INIT_USBPHY_CLKCTRL */ +#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 + +/* CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OPTFCLKEN_FUNC48M_CLK (1 << 15) +#define OPTFCLKEN_HSIC480M_P2_CLK (1 << 14) +#define OPTFCLKEN_HSIC480M_P1_CLK (1 << 13) +#define OPTFCLKEN_HSIC60M_P2_CLK (1 << 12) +#define OPTFCLKEN_HSIC60M_P1_CLK (1 << 11) +#define OPTFCLKEN_UTMI_P3_CLK (1 << 10) +#define OPTFCLKEN_UTMI_P2_CLK (1 << 9) +#define OPTFCLKEN_UTMI_P1_CLK (1 << 8) +#define OPTFCLKEN_HSIC480M_P3_CLK (1 << 7) +#define OPTFCLKEN_HSIC60M_P3_CLK (1 << 6) + +/* CM_L3INIT_USB_TLL_HS_CLKCTRL */ +#define OPTFCLKEN_USB_CH0_CLK_ENABLE (1 << 8) +#define OPTFCLKEN_USB_CH1_CLK_ENABLE (1 << 9) +#define OPTFCLKEN_USB_CH2_CLK_ENABLE (1 << 10) + +/* CM_COREAON_USB_PHY_CORE_CLKCTRL */ +#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) + +/* CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL */ +#define L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK (1 << 8) + +/* CM_L3INIT_USB_OTG_SS_CLKCTRL */ +#define OTG_SS_CLKCTRL_MODULEMODE_HW (1 << 0) +#define OPTFCLKEN_REFCLK960M (1 << 8) + +/* CM_L3INIT_OCP2SCP1_CLKCTRL */ +#define OCP2SCP1_CLKCTRL_MODULEMODE_HW (1 << 0) + +/* CM_MPU_MPU_CLKCTRL */ +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24) +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26 +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) + +/* CM_WKUPAON_SCRM_CLKCTRL */ +#define OPTFCLKEN_SCRM_PER_SHIFT 9 +#define OPTFCLKEN_SCRM_PER_MASK (1 << 9) +#define OPTFCLKEN_SCRM_CORE_SHIFT 8 +#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8) + +/* CM_COREAON_IO_SRCOMP_CLKCTRL */ +#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8 +#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8) + +/* PRM_RSTTIME */ +#define RSTTIME1_SHIFT 0 +#define RSTTIME1_MASK (0x3ff << 0) + +/* Clock frequencies */ +#define OMAP_SYS_CLK_IND_38_4_MHZ 6 + +/* PRM_VC_VAL_BYPASS */ +#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 + +/* CTRL_CORE_SRCOMP_NORTH_SIDE */ +#define USB2PHY_DISCHGDET (1 << 29) +#define USB2PHY_AUTORESUME_EN (1 << 30) + +/* SMPS */ +#define SMPS_I2C_SLAVE_ADDR 0x12 +#define SMPS_REG_ADDR_12_MPU 0x23 +#define SMPS_REG_ADDR_45_IVA 0x2B +#define SMPS_REG_ADDR_8_CORE 0x37 + +/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */ +/* ES1.0 settings */ +#define VDD_MPU 1040 +#define VDD_MM 1040 +#define VDD_CORE 1040 + +#define VDD_MPU_LOW 890 +#define VDD_MM_LOW 890 +#define VDD_CORE_LOW 890 + +/* ES2.0 settings */ +#define VDD_MPU_ES2 1060 +#define VDD_MM_ES2 1025 +#define VDD_CORE_ES2 1040 + +#define VDD_MPU_ES2_HIGH 1250 +#define VDD_MM_ES2_OD 1120 + +/* Efuse register offsets for OMAP5 platform */ +#define OMAP5_ES2_EFUSE_BASE 0x4A002000 +#define OMAP5_ES2_PROD_REGBITS 16 + +/* CONTROL_STD_FUSE_OPP_VDD_CORE_3 */ +#define OMAP5_ES2_PROD_CORE_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1D8) + +/* CONTROL_STD_FUSE_OPP_VDD_MM_4 */ +#define OMAP5_ES2_PROD_MM_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1A4) +/* CONTROL_STD_FUSE_OPP_VDD_MM_5 */ +#define OMAP5_ES2_PROD_MM_OPOD_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1A8) +/* CONTROL_STD_FUSE_OPP_VDD_MPU_6 */ +#define OMAP5_ES2_PROD_MPU_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1C4) +/* CONTROL_STD_FUSE_OPP_VDD_MPU_7 */ +#define OMAP5_ES2_PROD_MPU_OPHI_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1C8) + +/* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */ +#define VDD_MPU_DRA7_NOM 1150 +#define VDD_CORE_DRA7_NOM 1150 +#define VDD_EVE_DRA7_NOM 1060 +#define VDD_GPU_DRA7_NOM 1060 +#define VDD_IVA_DRA7_NOM 1060 + +/* DRA74x/75x/72x voltage settings in mv for OPP_OD per DM */ +#define VDD_EVE_DRA7_OD 1150 +#define VDD_GPU_DRA7_OD 1150 +#define VDD_IVA_DRA7_OD 1150 + +/* DRA74x/75x/72x voltage settings in mv for OPP_HIGH per DM */ +#define VDD_EVE_DRA7_HIGH 1250 +#define VDD_GPU_DRA7_HIGH 1250 +#define VDD_IVA_DRA7_HIGH 1250 + +/* Efuse register offsets for DRA7xx platform */ +#define DRA752_EFUSE_BASE 0x4A002000 +#define DRA752_EFUSE_REGBITS 16 +/* STD_FUSE_OPP_VMIN_IVA_2 */ +#define STD_FUSE_OPP_VMIN_IVA_NOM (DRA752_EFUSE_BASE + 0x05CC) +/* STD_FUSE_OPP_VMIN_IVA_3 */ +#define STD_FUSE_OPP_VMIN_IVA_OD (DRA752_EFUSE_BASE + 0x05D0) +/* STD_FUSE_OPP_VMIN_IVA_4 */ +#define STD_FUSE_OPP_VMIN_IVA_HIGH (DRA752_EFUSE_BASE + 0x05D4) +/* STD_FUSE_OPP_VMIN_DSPEVE_2 */ +#define STD_FUSE_OPP_VMIN_DSPEVE_NOM (DRA752_EFUSE_BASE + 0x05E0) +/* STD_FUSE_OPP_VMIN_DSPEVE_3 */ +#define STD_FUSE_OPP_VMIN_DSPEVE_OD (DRA752_EFUSE_BASE + 0x05E4) +/* STD_FUSE_OPP_VMIN_DSPEVE_4 */ +#define STD_FUSE_OPP_VMIN_DSPEVE_HIGH (DRA752_EFUSE_BASE + 0x05E8) +/* STD_FUSE_OPP_VMIN_CORE_2 */ +#define STD_FUSE_OPP_VMIN_CORE_NOM (DRA752_EFUSE_BASE + 0x05F4) +/* STD_FUSE_OPP_VMIN_GPU_2 */ +#define STD_FUSE_OPP_VMIN_GPU_NOM (DRA752_EFUSE_BASE + 0x1B08) +/* STD_FUSE_OPP_VMIN_GPU_3 */ +#define STD_FUSE_OPP_VMIN_GPU_OD (DRA752_EFUSE_BASE + 0x1B0C) +/* STD_FUSE_OPP_VMIN_GPU_4 */ +#define STD_FUSE_OPP_VMIN_GPU_HIGH (DRA752_EFUSE_BASE + 0x1B10) +/* STD_FUSE_OPP_VMIN_MPU_2 */ +#define STD_FUSE_OPP_VMIN_MPU_NOM (DRA752_EFUSE_BASE + 0x1B20) +/* STD_FUSE_OPP_VMIN_MPU_3 */ +#define STD_FUSE_OPP_VMIN_MPU_OD (DRA752_EFUSE_BASE + 0x1B24) +/* STD_FUSE_OPP_VMIN_MPU_4 */ +#define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28) + +#if defined(CONFIG_DRA7_MPU_OPP_HIGH) +#define DRA7_MPU_OPP OPP_HIGH +#elif defined(CONFIG_DRA7_MPU_OPP_OD) +#define DRA7_MPU_OPP OPP_OD +#else /* OPP_NOM default */ +#define DRA7_MPU_OPP OPP_NOM +#endif + +/* OPP_NOM only available option for CORE */ +#define DRA7_CORE_OPP OPP_NOM + +#if defined(CONFIG_DRA7_DSPEVE_OPP_HIGH) +#define DRA7_DSPEVE_OPP OPP_HIGH +#elif defined(CONFIG_DRA7_DSPEVE_OPP_OD) +#define DRA7_DSPEVE_OPP OPP_OD +#else /* OPP_NOM default */ +#define DRA7_DSPEVE_OPP OPP_NOM +#endif + +#if defined(CONFIG_DRA7_IVA_OPP_HIGH) +#define DRA7_IVA_OPP OPP_HIGH +#elif defined(CONFIG_DRA7_IVA_OPP_OD) +#define DRA7_IVA_OPP OPP_OD +#else /* OPP_NOM default */ +#define DRA7_IVA_OPP OPP_NOM +#endif + +#if defined(CONFIG_DRA7_GPU_OPP_HIGH) +#define DRA7_GPU_OPP OPP_HIGH +#elif defined(CONFIG_DRA7_GPU_OPP_OD) +#define DRA7_GPU_OPP OPP_OD +#else /* OPP_NOM default */ +#define DRA7_GPU_OPP OPP_NOM +#endif + +/* Standard offset is 0.5v expressed in uv */ +#define PALMAS_SMPS_BASE_VOLT_UV 500000 + +/* Offset is 0.73V for LP873x */ +#define LP873X_BUCK_BASE_VOLT_UV 730000 + +/* Offset is 0.73V for LP87565 */ +#define LP87565_BUCK_BASE_VOLT_UV 730000 + +/* TPS659038 */ +#define TPS659038_I2C_SLAVE_ADDR 0x58 +#define TPS659038_REG_ADDR_SMPS12 0x23 +#define TPS659038_REG_ADDR_SMPS45 0x2B +#define TPS659038_REG_ADDR_SMPS6 0x2F +#define TPS659038_REG_ADDR_SMPS7 0x33 +#define TPS659038_REG_ADDR_SMPS8 0x37 + +/* TPS65917 */ +#define TPS65917_I2C_SLAVE_ADDR 0x58 +#define TPS65917_REG_ADDR_SMPS1 0x23 +#define TPS65917_REG_ADDR_SMPS2 0x27 +#define TPS65917_REG_ADDR_SMPS3 0x2F +#define TPS65917_REG_ADDR_SMPS4 0x33 + +/* LP873X */ +#define LP873X_I2C_SLAVE_ADDR 0x60 +#define LP873X_REG_ADDR_BUCK0 0x6 +#define LP873X_REG_ADDR_BUCK1 0x7 +#define LP873X_REG_ADDR_LDO1 0xA + +/* LP87565 */ +#define LP87565_I2C_SLAVE_ADDR 0x61 +#define LP87565_REG_ADDR_BUCK01 0xA +#define LP87565_REG_ADDR_BUCK23 0xE + +/* TPS */ +#define TPS62361_I2C_SLAVE_ADDR 0x60 +#define TPS62361_REG_ADDR_SET0 0x0 +#define TPS62361_REG_ADDR_SET1 0x1 +#define TPS62361_REG_ADDR_SET2 0x2 +#define TPS62361_REG_ADDR_SET3 0x3 +#define TPS62361_REG_ADDR_CTRL 0x4 +#define TPS62361_REG_ADDR_TEMP 0x5 +#define TPS62361_REG_ADDR_RMP_CTRL 0x6 +#define TPS62361_REG_ADDR_CHIP_ID 0x8 +#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 + +#define TPS62361_BASE_VOLT_MV 500 +#define TPS62361_VSEL0_GPIO 7 + +/* Defines for DPLL setup */ +#define DPLL_LOCKED_FREQ_TOLERANCE_0 0 +#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 +#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 + +#define DPLL_NO_LOCK 0 +#define DPLL_LOCK 1 + +#if defined(CONFIG_DRA7XX) +#define V_OSCK 20000000 /* Clock output from T2 */ +#else +#define V_OSCK 19200000 /* Clock output from T2 */ +#endif + +#define V_SCLK V_OSCK + +/* CKO buffer control */ +#define CKOBUFFER_CLK_ENABLE_MASK (1 << 28) + +/* AUXCLKx reg fields */ +#define AUXCLK_ENABLE_MASK (1 << 8) +#define AUXCLK_SRCSELECT_SHIFT 1 +#define AUXCLK_SRCSELECT_MASK (3 << 1) +#define AUXCLK_CLKDIV_SHIFT 16 +#define AUXCLK_CLKDIV_MASK (0xF << 16) + +#define AUXCLK_SRCSELECT_SYS_CLK 0 +#define AUXCLK_SRCSELECT_CORE_DPLL 1 +#define AUXCLK_SRCSELECT_PER_DPLL 2 +#define AUXCLK_SRCSELECT_ALTERNATE 3 + +#endif /* _CLOCKS_OMAP5_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap5/cpu.h b/roms/u-boot/arch/arm/include/asm/arch-omap5/cpu.h new file mode 100644 index 000000000..9e5655319 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap5/cpu.h @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2010 + * Texas Instruments, + * + * Aneesh V + */ + +#ifndef _CPU_H +#define _CPU_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +#include + +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +#include + +struct gptimer { + u32 tidr; /* 0x00 r */ + u8 res1[0xc]; + u32 tiocp_cfg; /* 0x10 rw */ + u8 res2[0x10]; + u32 tisr_raw; /* 0x24 r */ + u32 tisr; /* 0x28 rw */ + u32 tier; /* 0x2c rw */ + u32 ticr; /* 0x30 rw */ + u32 twer; /* 0x34 rw */ + u32 tclr; /* 0x38 rw */ + u32 tcrr; /* 0x3c rw */ + u32 tldr; /* 0x40 rw */ + u32 ttgr; /* 0x44 rw */ + u32 twpc; /* 0x48 r */ + u32 tmar; /* 0x4c rw */ + u32 tcar1; /* 0x50 r */ + u32 tcicr; /* 0x54 rw */ + u32 tcar2; /* 0x58 r */ +}; +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +/* enable sys_clk NO-prescale /1 */ +#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) + +#define WDT_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) +/* Watchdog */ +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct watchdog { + u8 res1[0x34]; + u32 wwps; /* 0x34 r */ + u8 res2[0x10]; + u32 wspr; /* 0x48 rw */ +}; +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +#define TCLR_ST (0x1 << 0) +#define TCLR_AR (0x1 << 1) +#define TCLR_PRE (0x1 << 5) + +/* I2C base */ +#define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000) +#define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000) +#define I2C_BASE3 (OMAP54XX_L4_PER_BASE + 0x60000) +#define I2C_BASE4 (OMAP54XX_L4_PER_BASE + 0x7A000) +#define I2C_BASE5 (OMAP54XX_L4_PER_BASE + 0x7C000) + +/* MUSB base */ +#define MUSB_BASE (OMAP54XX_L4_CORE_BASE + 0xAB000) + +/* OMAP4 GPIO registers */ +#define OMAP_GPIO_REVISION 0x0000 +#define OMAP_GPIO_SYSCONFIG 0x0010 +#define OMAP_GPIO_SYSSTATUS 0x0114 +#define OMAP_GPIO_IRQSTATUS1 0x0118 +#define OMAP_GPIO_IRQSTATUS2 0x0128 +#define OMAP_GPIO_IRQENABLE2 0x012c +#define OMAP_GPIO_IRQENABLE1 0x011c +#define OMAP_GPIO_WAKE_EN 0x0120 +#define OMAP_GPIO_CTRL 0x0130 +#define OMAP_GPIO_OE 0x0134 +#define OMAP_GPIO_DATAIN 0x0138 +#define OMAP_GPIO_DATAOUT 0x013c +#define OMAP_GPIO_LEVELDETECT0 0x0140 +#define OMAP_GPIO_LEVELDETECT1 0x0144 +#define OMAP_GPIO_RISINGDETECT 0x0148 +#define OMAP_GPIO_FALLINGDETECT 0x014c +#define OMAP_GPIO_DEBOUNCE_EN 0x0150 +#define OMAP_GPIO_DEBOUNCE_VAL 0x0154 +#define OMAP_GPIO_CLEARIRQENABLE1 0x0160 +#define OMAP_GPIO_SETIRQENABLE1 0x0164 +#define OMAP_GPIO_CLEARWKUENA 0x0180 +#define OMAP_GPIO_SETWKUENA 0x0184 +#define OMAP_GPIO_CLEARDATAOUT 0x0190 +#define OMAP_GPIO_SETDATAOUT 0x0194 + +/* + * PRCM + */ + +/* PRM */ +#define PRM_BASE 0x4AE06000 +#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) + +#define PRM_RSTCTRL PRM_DEVICE_BASE +#define PRM_RSTCTRL_RESET 0x01 +#define PRM_RSTST (PRM_DEVICE_BASE + 0x4) +#define PRM_RSTST_WARM_RESET_MASK 0x7FEA + +/* DRA7XX CPSW Config space */ +#define CPSW_BASE 0x48484000 +#define CPSW_MDIO_BASE 0x48485000 + +/* gmii_sel register defines */ +#define GMII1_SEL_MII 0x0 +#define GMII1_SEL_RMII 0x1 +#define GMII1_SEL_RGMII 0x2 +#define GMII2_SEL_MII (GMII1_SEL_MII << 4) +#define GMII2_SEL_RMII (GMII1_SEL_RMII << 4) +#define GMII2_SEL_RGMII (GMII1_SEL_RGMII << 4) + +#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII) +#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII) +#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII) + +#endif /* _CPU_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h b/roms/u-boot/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h new file mode 100644 index 000000000..ea2f113f9 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 + * Texas Instruments Incorporated + * + * Lokesh Vutla + */ + +#ifndef _DRA7_IODELAY_H_ +#define _DRA7_IODELAY_H_ + +#include + +/* CONFIG_REG_0 */ +#define CFG_REG_0_OFFSET 0xC +#define CFG_REG_ROM_READ_SHIFT 1 +#define CFG_REG_ROM_READ_MASK (1 << 1) +#define CFG_REG_CALIB_STRT_SHIFT 0 +#define CFG_REG_CALIB_STRT_MASK (1 << 0) +#define CFG_REG_CALIB_STRT 1 +#define CFG_REG_CALIB_END 0 +#define CFG_REG_ROM_READ_START (1 << 1) +#define CFG_REG_ROM_READ_END (0 << 1) + +/* CONFIG_REG_2 */ +#define CFG_REG_2_OFFSET 0x14 +#define CFG_REG_REFCLK_PERIOD_SHIFT 0 +#define CFG_REG_REFCLK_PERIOD_MASK (0xFFFF << 0) +#define CFG_REG_REFCLK_PERIOD 0x2EF + +/* CONFIG_REG_8 */ +#define CFG_REG_8_OFFSET 0x2C +#define CFG_IODELAY_UNLOCK_KEY 0x0000AAAA +#define CFG_IODELAY_LOCK_KEY 0x0000AAAB + +/* CONFIG_REG_3/4 */ +#define CFG_REG_3_OFFSET 0x18 +#define CFG_REG_4_OFFSET 0x1C +#define CFG_REG_DLY_CNT_SHIFT 16 +#define CFG_REG_DLY_CNT_MASK (0xFFFF << 16) +#define CFG_REG_REF_CNT_SHIFT 0 +#define CFG_REG_REF_CNT_MASK (0xFFFF << 0) + +/* CTRL_CORE_SMA_SW_0 */ +#define CTRL_ISOLATE_SHIFT 2 +#define CTRL_ISOLATE_MASK (1 << 2) +#define ISOLATE_IO 1 +#define DEISOLATE_IO 0 + +/* CTRL_CORE_SMA_SW_1 */ +#define RGMII2_ID_MODE_N_MASK (1 << 26) +#define RGMII1_ID_MODE_N_MASK (1 << 25) + +/* PRM_IO_PMCTRL */ +#define PMCTRL_ISOCLK_OVERRIDE_SHIFT 0 +#define PMCTRL_ISOCLK_OVERRIDE_MASK (1 << 0) +#define PMCTRL_ISOCLK_STATUS_SHIFT 1 +#define PMCTRL_ISOCLK_STATUS_MASK (1 << 1) +#define PMCTRL_ISOCLK_OVERRIDE_CTRL 1 +#define PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL 0 + +#define ERR_CALIBRATE_IODELAY 0x1 +#define ERR_DEISOLATE_IO 0x2 +#define ERR_ISOLATE_IO 0x4 +#define ERR_UPDATE_DELAY 0x8 +#define ERR_CPDE 0x3 +#define ERR_FPDE 0x5 + +/* CFG_XXX */ +#define CFG_X_SIGNATURE_SHIFT 12 +#define CFG_X_SIGNATURE_MASK (0x3F << 12) +#define CFG_X_LOCK_SHIFT 10 +#define CFG_X_LOCK_MASK (0x1 << 10) +#define CFG_X_COARSE_DLY_SHIFT 5 +#define CFG_X_COARSE_DLY_MASK (0x1F << 5) +#define CFG_X_FINE_DLY_SHIFT 0 +#define CFG_X_FINE_DLY_MASK (0x1F << 0) +#define CFG_X_SIGNATURE 0x29 +#define CFG_X_LOCK 1 + +void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, + struct iodelay_cfg_entry const *iodelay, + int niodelays); +void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, + struct iodelay_cfg_entry const *iodelay, + int niodelays); +int __recalibrate_iodelay_start(void); +void __recalibrate_iodelay_end(int ret); + +int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array, + int niodelays); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap5/ehci.h b/roms/u-boot/arch/arm/include/asm/arch-omap5/ehci.h new file mode 100644 index 000000000..1790b92a2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap5/ehci.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com* + * Author: Govindraj R + */ + +#ifndef _EHCI_H +#define _EHCI_H + +#define OMAP_EHCI_BASE (OMAP54XX_L4_CORE_BASE + 0x64C00) +#define OMAP_UHH_BASE (OMAP54XX_L4_CORE_BASE + 0x64000) +#define OMAP_USBTLL_BASE (OMAP54XX_L4_CORE_BASE + 0x62000) + +/* TLL Register Set */ +#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) +#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) +#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) +#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) +#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1 + +#define OMAP_UHH_SYSCONFIG_SOFTRESET 1 +#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2) +#define OMAP_UHH_SYSCONFIG_NOIDLE (1 << 2) +#define OMAP_UHH_SYSCONFIG_NOSTDBY (1 << 4) + +#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_NOIDLE | \ + OMAP_UHH_SYSCONFIG_NOSTDBY) + +#endif /* _EHCI_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap5/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-omap5/gpio.h new file mode 100644 index 000000000..1e44fb5ae --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap5/gpio.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This work is derived from the linux 2.6.27 kernel source + * To fetch, use the kernel repository + * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git + * Use the v2.6.27 tag. + * + * Below is the original's header including its copyright + * + * linux/arch/arm/plat-omap/gpio.c + * + * Support functions for OMAP GPIO + * + * Copyright (C) 2003-2005 Nokia Corporation + * Written by Juha Yrjölä + */ +#ifndef _GPIO_OMAP5_H +#define _GPIO_OMAP5_H + +#include + +#define OMAP_MAX_GPIO 256 + +#define OMAP54XX_GPIO1_BASE 0x4Ae10000 +#define OMAP54XX_GPIO2_BASE 0x48055000 +#define OMAP54XX_GPIO3_BASE 0x48057000 +#define OMAP54XX_GPIO4_BASE 0x48059000 +#define OMAP54XX_GPIO5_BASE 0x4805B000 +#define OMAP54XX_GPIO6_BASE 0x4805D000 +#define OMAP54XX_GPIO7_BASE 0x48051000 +#define OMAP54XX_GPIO8_BASE 0x48053000 + + +/* Get the GPIO index from the given bank number and bank gpio */ +#define GPIO_TO_PIN(bank, bank_gpio) (32 * (bank - 1) + (bank_gpio)) + +#endif /* _GPIO_OMAP5_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap5/hardware.h b/roms/u-boot/arch/arm/include/asm/arch-omap5/hardware.h new file mode 100644 index 000000000..b6d26e9f0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap5/hardware.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * hardware.h + * + * hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef __OMAP_HARDWARE_H +#define __OMAP_HARDWARE_H + +#include + +/* + * Common hardware definitions + */ + +/* BCH Error Location Module */ +#define ELM_BASE 0x48078000 + +/* GPMC Base address */ +#define GPMC_BASE 0x50000000 + +/* EDMA3 Base address for DRA7XX and AM57XX */ +#if defined(CONFIG_DRA7XX) +#define EDMA3_BASE 0x43300000 +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap5/i2c.h b/roms/u-boot/arch/arm/include/asm/arch-omap5/i2c.h new file mode 100644 index 000000000..9e1edcf2b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap5/i2c.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2004-2010 + * Texas Instruments, + */ +#ifndef _OMAP5_I2C_H_ +#define _OMAP5_I2C_H_ + +#define I2C_DEFAULT_BASE I2C_BASE1 + +#endif /* _OMAP5_I2C_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap5/mem.h b/roms/u-boot/arch/arm/include/asm/arch-omap5/mem.h new file mode 100644 index 000000000..bd72fb611 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap5/mem.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, + * + * Author + * Mansoor Ahamed + * + * Initial Code from: + * Richard Woodruff + */ + +#ifndef _MEM_H_ +#define _MEM_H_ + +/* + * GPMC settings - + * Definitions is as per the following format + * #define _GPMC_CONFIG + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should + * go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * M_NAND - Micron NAND + * STNOR - STMicrolelctronics M29W128GL + */ +#define GPMC_SIZE_256M 0x0 +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#define M_NAND_GPMC_CONFIG1 0x00000800 +#define M_NAND_GPMC_CONFIG2 0x001e1e00 +#define M_NAND_GPMC_CONFIG3 0x001e1e00 +#define M_NAND_GPMC_CONFIG4 0x16051807 +#define M_NAND_GPMC_CONFIG5 0x00151e1e +#define M_NAND_GPMC_CONFIG6 0x16000f80 +#define M_NAND_GPMC_CONFIG7 0x00000008 + +#define STNOR_GPMC_CONFIG1 0x00001000 +#define STNOR_GPMC_CONFIG2 0x001f1f00 +#define STNOR_GPMC_CONFIG3 0x001f1f01 +#define STNOR_GPMC_CONFIG4 0x1f011f01 +#define STNOR_GPMC_CONFIG5 0x001d1f1f +#define STNOR_GPMC_CONFIG6 0x08070280 +#define STNOR_GPMC_CONFIG7 0x00000048 + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#endif /* endif _MEM_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/roms/u-boot/arch/arm/include/asm/arch-omap5/mmc_host_def.h new file mode 100644 index 000000000..d06779956 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap5/mmc_host_def.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MMC_HOST_DEF_H +#define MMC_HOST_DEF_H + +#include + +/* + * OMAP HSMMC register definitions + */ + +#define OMAP_HSMMC1_BASE 0x4809C000 +#define OMAP_HSMMC2_BASE 0x480B4000 +#define OMAP_HSMMC3_BASE 0x480AD000 + +#endif /* MMC_HOST_DEF_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/roms/u-boot/arch/arm/include/asm/arch-omap5/mux_dra7xx.h new file mode 100644 index 000000000..c7c118ec2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap5/mux_dra7xx.h @@ -0,0 +1,356 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated + * + * Nishant Kamat + * Lokesh Vutla + */ +#ifndef _MUX_DRA7XX_H_ +#define _MUX_DRA7XX_H_ + +#include + +#define PULL_ENA (0 << 16) +#define PULL_DIS (1 << 16) +#define PULL_UP (1 << 17) +#define INPUT_EN (1 << 18) +#define SLEWCONTROL (1 << 19) + +/* Active pin states */ +#define PIN_OUTPUT (0 | PULL_DIS) +#define PIN_OUTPUT_PULLUP (PULL_UP) +#define PIN_OUTPUT_PULLDOWN (0) +#define PIN_INPUT (INPUT_EN | PULL_DIS) +#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL) +#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 +#define M8 8 +#define M9 9 +#define M10 10 +#define M11 11 +#define M12 12 +#define M13 13 +#define M14 14 +#define M15 15 + +#define MODE_SELECT (1 << 8) +#define DELAYMODE_SHIFT 4 + +#define MANUAL_MODE MODE_SELECT + +#define VIRTUAL_MODE0 (MODE_SELECT | (0x0 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE1 (MODE_SELECT | (0x1 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE2 (MODE_SELECT | (0x2 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE3 (MODE_SELECT | (0x3 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE4 (MODE_SELECT | (0x4 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE5 (MODE_SELECT | (0x5 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE6 (MODE_SELECT | (0x6 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE7 (MODE_SELECT | (0x7 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE8 (MODE_SELECT | (0x8 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE9 (MODE_SELECT | (0x9 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE10 (MODE_SELECT | (0xa << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE11 (MODE_SELECT | (0xb << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE12 (MODE_SELECT | (0xc << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE13 (MODE_SELECT | (0xd << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE14 (MODE_SELECT | (0xe << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE15 (MODE_SELECT | (0xf << DELAYMODE_SHIFT)) + +#define SAFE_MODE M15 + +#define GPMC_AD0 0x000 +#define GPMC_AD1 0x004 +#define GPMC_AD2 0x008 +#define GPMC_AD3 0x00C +#define GPMC_AD4 0x010 +#define GPMC_AD5 0x014 +#define GPMC_AD6 0x018 +#define GPMC_AD7 0x01C +#define GPMC_AD8 0x020 +#define GPMC_AD9 0x024 +#define GPMC_AD10 0x028 +#define GPMC_AD11 0x02C +#define GPMC_AD12 0x030 +#define GPMC_AD13 0x034 +#define GPMC_AD14 0x038 +#define GPMC_AD15 0x03C +#define GPMC_A0 0x040 +#define GPMC_A1 0x044 +#define GPMC_A2 0x048 +#define GPMC_A3 0x04C +#define GPMC_A4 0x050 +#define GPMC_A5 0x054 +#define GPMC_A6 0x058 +#define GPMC_A7 0x05C +#define GPMC_A8 0x060 +#define GPMC_A9 0x064 +#define GPMC_A10 0x068 +#define GPMC_A11 0x06C +#define GPMC_A12 0x070 +#define GPMC_A13 0x074 +#define GPMC_A14 0x078 +#define GPMC_A15 0x07C +#define GPMC_A16 0x080 +#define GPMC_A17 0x084 +#define GPMC_A18 0x088 +#define GPMC_A19 0x08C +#define GPMC_A20 0x090 +#define GPMC_A21 0x094 +#define GPMC_A22 0x098 +#define GPMC_A23 0x09C +#define GPMC_A24 0x0A0 +#define GPMC_A25 0x0A4 +#define GPMC_A26 0x0A8 +#define GPMC_A27 0x0AC +#define GPMC_CS1 0x0B0 +#define GPMC_CS0 0x0B4 +#define GPMC_CS2 0x0B8 +#define GPMC_CS3 0x0BC +#define GPMC_CLK 0x0C0 +#define GPMC_ADVN_ALE 0x0C4 +#define GPMC_OEN_REN 0x0C8 +#define GPMC_WEN 0x0CC +#define GPMC_BEN0 0x0D0 +#define GPMC_BEN1 0x0D4 +#define GPMC_WAIT0 0x0D8 +#define VIN1A_CLK0 0x0DC +#define VIN1B_CLK1 0x0E0 +#define VIN1A_DE0 0x0E4 +#define VIN1A_FLD0 0x0E8 +#define VIN1A_HSYNC0 0x0EC +#define VIN1A_VSYNC0 0x0F0 +#define VIN1A_D0 0x0F4 +#define VIN1A_D1 0x0F8 +#define VIN1A_D2 0x0FC +#define VIN1A_D3 0x100 +#define VIN1A_D4 0x104 +#define VIN1A_D5 0x108 +#define VIN1A_D6 0x10C +#define VIN1A_D7 0x110 +#define VIN1A_D8 0x114 +#define VIN1A_D9 0x118 +#define VIN1A_D10 0x11C +#define VIN1A_D11 0x120 +#define VIN1A_D12 0x124 +#define VIN1A_D13 0x128 +#define VIN1A_D14 0x12C +#define VIN1A_D15 0x130 +#define VIN1A_D16 0x134 +#define VIN1A_D17 0x138 +#define VIN1A_D18 0x13C +#define VIN1A_D19 0x140 +#define VIN1A_D20 0x144 +#define VIN1A_D21 0x148 +#define VIN1A_D22 0x14C +#define VIN1A_D23 0x150 +#define VIN2A_CLK0 0x154 +#define VIN2A_DE0 0x158 +#define VIN2A_FLD0 0x15C +#define VIN2A_HSYNC0 0x160 +#define VIN2A_VSYNC0 0x164 +#define VIN2A_D0 0x168 +#define VIN2A_D1 0x16C +#define VIN2A_D2 0x170 +#define VIN2A_D3 0x174 +#define VIN2A_D4 0x178 +#define VIN2A_D5 0x17C +#define VIN2A_D6 0x180 +#define VIN2A_D7 0x184 +#define VIN2A_D8 0x188 +#define VIN2A_D9 0x18C +#define VIN2A_D10 0x190 +#define VIN2A_D11 0x194 +#define VIN2A_D12 0x198 +#define VIN2A_D13 0x19C +#define VIN2A_D14 0x1A0 +#define VIN2A_D15 0x1A4 +#define VIN2A_D16 0x1A8 +#define VIN2A_D17 0x1AC +#define VIN2A_D18 0x1B0 +#define VIN2A_D19 0x1B4 +#define VIN2A_D20 0x1B8 +#define VIN2A_D21 0x1BC +#define VIN2A_D22 0x1C0 +#define VIN2A_D23 0x1C4 +#define VOUT1_CLK 0x1C8 +#define VOUT1_DE 0x1CC +#define VOUT1_FLD 0x1D0 +#define VOUT1_HSYNC 0x1D4 +#define VOUT1_VSYNC 0x1D8 +#define VOUT1_D0 0x1DC +#define VOUT1_D1 0x1E0 +#define VOUT1_D2 0x1E4 +#define VOUT1_D3 0x1E8 +#define VOUT1_D4 0x1EC +#define VOUT1_D5 0x1F0 +#define VOUT1_D6 0x1F4 +#define VOUT1_D7 0x1F8 +#define VOUT1_D8 0x1FC +#define VOUT1_D9 0x200 +#define VOUT1_D10 0x204 +#define VOUT1_D11 0x208 +#define VOUT1_D12 0x20C +#define VOUT1_D13 0x210 +#define VOUT1_D14 0x214 +#define VOUT1_D15 0x218 +#define VOUT1_D16 0x21C +#define VOUT1_D17 0x220 +#define VOUT1_D18 0x224 +#define VOUT1_D19 0x228 +#define VOUT1_D20 0x22C +#define VOUT1_D21 0x230 +#define VOUT1_D22 0x234 +#define VOUT1_D23 0x238 +#define MDIO_MCLK 0x23C +#define MDIO_D 0x240 +#define RMII_MHZ_50_CLK 0x244 +#define UART3_RXD 0x248 +#define UART3_TXD 0x24C +#define RGMII0_TXC 0x250 +#define RGMII0_TXCTL 0x254 +#define RGMII0_TXD3 0x258 +#define RGMII0_TXD2 0x25C +#define RGMII0_TXD1 0x260 +#define RGMII0_TXD0 0x264 +#define RGMII0_RXC 0x268 +#define RGMII0_RXCTL 0x26C +#define RGMII0_RXD3 0x270 +#define RGMII0_RXD2 0x274 +#define RGMII0_RXD1 0x278 +#define RGMII0_RXD0 0x27C +#define USB1_DRVVBUS 0x280 +#define USB2_DRVVBUS 0x284 +#define GPIO6_14 0x288 +#define GPIO6_15 0x28C +#define GPIO6_16 0x290 +#define XREF_CLK0 0x294 +#define XREF_CLK1 0x298 +#define XREF_CLK2 0x29C +#define XREF_CLK3 0x2A0 +#define MCASP1_ACLKX 0x2A4 +#define MCASP1_FSX 0x2A8 +#define MCASP1_ACLKR 0x2AC +#define MCASP1_FSR 0x2B0 +#define MCASP1_AXR0 0x2B4 +#define MCASP1_AXR1 0x2B8 +#define MCASP1_AXR2 0x2BC +#define MCASP1_AXR3 0x2C0 +#define MCASP1_AXR4 0x2C4 +#define MCASP1_AXR5 0x2C8 +#define MCASP1_AXR6 0x2CC +#define MCASP1_AXR7 0x2D0 +#define MCASP1_AXR8 0x2D4 +#define MCASP1_AXR9 0x2D8 +#define MCASP1_AXR10 0x2DC +#define MCASP1_AXR11 0x2E0 +#define MCASP1_AXR12 0x2E4 +#define MCASP1_AXR13 0x2E8 +#define MCASP1_AXR14 0x2EC +#define MCASP1_AXR15 0x2F0 +#define MCASP2_ACLKX 0x2F4 +#define MCASP2_FSX 0x2F8 +#define MCASP2_ACLKR 0x2FC +#define MCASP2_FSR 0x300 +#define MCASP2_AXR0 0x304 +#define MCASP2_AXR1 0x308 +#define MCASP2_AXR2 0x30C +#define MCASP2_AXR3 0x310 +#define MCASP2_AXR4 0x314 +#define MCASP2_AXR5 0x318 +#define MCASP2_AXR6 0x31C +#define MCASP2_AXR7 0x320 +#define MCASP3_ACLKX 0x324 +#define MCASP3_FSX 0x328 +#define MCASP3_AXR0 0x32C +#define MCASP3_AXR1 0x330 +#define MCASP4_ACLKX 0x334 +#define MCASP4_FSX 0x338 +#define MCASP4_AXR0 0x33C +#define MCASP4_AXR1 0x340 +#define MCASP5_ACLKX 0x344 +#define MCASP5_FSX 0x348 +#define MCASP5_AXR0 0x34C +#define MCASP5_AXR1 0x350 +#define MMC1_CLK 0x354 +#define MMC1_CMD 0x358 +#define MMC1_DAT0 0x35C +#define MMC1_DAT1 0x360 +#define MMC1_DAT2 0x364 +#define MMC1_DAT3 0x368 +#define MMC1_SDCD 0x36C +#define MMC1_SDWP 0x370 +#define GPIO6_10 0x374 +#define GPIO6_11 0x378 +#define MMC3_CLK 0x37C +#define MMC3_CMD 0x380 +#define MMC3_DAT0 0x384 +#define MMC3_DAT1 0x388 +#define MMC3_DAT2 0x38C +#define MMC3_DAT3 0x390 +#define MMC3_DAT4 0x394 +#define MMC3_DAT5 0x398 +#define MMC3_DAT6 0x39C +#define MMC3_DAT7 0x3A0 +#define SPI1_SCLK 0x3A4 +#define SPI1_D1 0x3A8 +#define SPI1_D0 0x3AC +#define SPI1_CS0 0x3B0 +#define SPI1_CS1 0x3B4 +#define SPI1_CS2 0x3B8 +#define SPI1_CS3 0x3BC +#define SPI2_SCLK 0x3C0 +#define SPI2_D1 0x3C4 +#define SPI2_D0 0x3C8 +#define SPI2_CS0 0x3CC +#define DCAN1_TX 0x3D0 +#define DCAN1_RX 0x3D4 +#define DCAN2_TX 0x3D8 +#define DCAN2_RX 0x3DC +#define UART1_RXD 0x3E0 +#define UART1_TXD 0x3E4 +#define UART1_CTSN 0x3E8 +#define UART1_RTSN 0x3EC +#define UART2_RXD 0x3F0 +#define UART2_TXD 0x3F4 +#define UART2_CTSN 0x3F8 +#define UART2_RTSN 0x3FC +#define I2C1_SDA 0x400 +#define I2C1_SCL 0x404 +#define I2C2_SDA 0x408 +#define I2C2_SCL 0x40C +#define I2C3_SDA 0x410 +#define I2C3_SCL 0x414 +#define WAKEUP0 0x418 +#define WAKEUP1 0x41C +#define WAKEUP2 0x420 +#define WAKEUP3 0x424 +#define ON_OFF 0x428 +#define RTC_PORZ 0x42C +#define TMS 0x430 +#define TDI 0x434 +#define TDO 0x438 +#define TCLK 0x43C +#define TRSTN 0x440 +#define RTCK 0x444 +#define EMU0 0x448 +#define EMU1 0x44C +#define EMU2 0x450 +#define EMU3 0x454 +#define EMU4 0x458 +#define RESETN 0x45C +#define NMIN_DSP 0x460 +#define RSTOUTN 0x464 + +#define MCAN_SEL_ALT_MASK 0x6000 +#define MCAN_SEL 0x2000 + +#endif /* _MUX_DRA7XX_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap5/mux_omap5.h b/roms/u-boot/arch/arm/include/asm/arch-omap5/mux_omap5.h new file mode 100644 index 000000000..2460646e3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap5/mux_omap5.h @@ -0,0 +1,317 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2004-2009 + * Texas Instruments Incorporated + * Richard Woodruff + * Aneesh V + * Balaji Krishnamoorthy + */ +#ifndef _MUX_OMAP5_H_ +#define _MUX_OMAP5_H_ + +#include + +#ifdef CONFIG_OFF_PADCONF +#define OFF_PD (1 << 12) +#define OFF_PU (3 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (2 << 10) +#define OFF_IN (1 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (1 << 9) +#else +#define OFF_PD (0 << 12) +#define OFF_PU (0 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (0 << 10) +#define OFF_IN (0 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (0 << 9) +#endif + +#define IEN (1 << 8) +#define IDIS (0 << 8) +#define PTU (3 << 3) +#define PTD (1 << 3) +#define EN (1 << 3) +#define DIS (0 << 3) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 + +#define SAFE_MODE M7 + +#ifdef CONFIG_OFF_PADCONF +#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) +#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) +#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) +#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) +#else +#define OFF_IN_PD 0 +#define OFF_IN_PU 0 +#define OFF_OUT_PD 0 +#define OFF_OUT_PU 0 +#endif + +#define CORE_REVISION 0x0000 +#define CORE_HWINFO 0x0004 +#define CORE_SYSCONFIG 0x0010 +#define EMMC_CLK 0x0040 +#define EMMC_CMD 0x0042 +#define EMMC_DATA0 0x0044 +#define EMMC_DATA1 0x0046 +#define EMMC_DATA2 0x0048 +#define EMMC_DATA3 0x004a +#define EMMC_DATA4 0x004c +#define EMMC_DATA5 0x004e +#define EMMC_DATA6 0x0050 +#define EMMC_DATA7 0x0052 +#define C2C_CLKOUT0 0x0054 +#define C2C_CLKOUT1 0x0056 +#define C2C_CLKIN0 0x0058 +#define C2C_CLKIN1 0x005a +#define C2C_DATAIN0 0x005c +#define C2C_DATAIN1 0x005e +#define C2C_DATAIN2 0x0060 +#define C2C_DATAIN3 0x0062 +#define C2C_DATAIN4 0x0064 +#define C2C_DATAIN5 0x0066 +#define C2C_DATAIN6 0x0068 +#define C2C_DATAIN7 0x006a +#define C2C_DATAOUT0 0x006c +#define C2C_DATAOUT1 0x006e +#define C2C_DATAOUT2 0x0070 +#define C2C_DATAOUT3 0x0072 +#define C2C_DATAOUT4 0x0074 +#define C2C_DATAOUT5 0x0076 +#define C2C_DATAOUT6 0x0078 +#define C2C_DATAOUT7 0x007a +#define C2C_DATA8 0x007c +#define C2C_DATA9 0x007e +#define C2C_DATA10 0x0080 +#define C2C_DATA11 0x0082 +#define C2C_DATA12 0x0084 +#define C2C_DATA13 0x0086 +#define C2C_DATA14 0x0088 +#define C2C_DATA15 0x008a +#define LLIA_WAKEREQOUT 0x008c +#define LLIB_WAKEREQOUT 0x008e +#define HSI1_ACREADY 0x0090 +#define HSI1_CAREADY 0x0092 +#define HSI1_ACWAKE 0x0094 +#define HSI1_CAWAKE 0x0096 +#define HSI1_ACFLAG 0x0098 +#define HSI1_ACDATA 0x009a +#define HSI1_CAFLAG 0x009c +#define HSI1_CADATA 0x009e +#define UART1_TX 0x00a0 +#define UART1_CTS 0x00a2 +#define UART1_RX 0x00a4 +#define UART1_RTS 0x00a6 +#define HSI2_CAREADY 0x00a8 +#define HSI2_ACREADY 0x00aa +#define HSI2_CAWAKE 0x00ac +#define HSI2_ACWAKE 0x00ae +#define HSI2_CAFLAG 0x00b0 +#define HSI2_CADATA 0x00b2 +#define HSI2_ACFLAG 0x00b4 +#define HSI2_ACDATA 0x00b6 +#define UART2_RTS 0x00b8 +#define UART2_CTS 0x00ba +#define UART2_RX 0x00bc +#define UART2_TX 0x00be +#define USBB1_HSIC_STROBE 0x00c0 +#define USBB1_HSIC_DATA 0x00c2 +#define USBB2_HSIC_STROBE 0x00c4 +#define USBB2_HSIC_DATA 0x00c6 +#define TIMER10_PWM_EVT 0x00c8 +#define DSIPORTA_TE0 0x00ca +#define DSIPORTA_LANE0X 0x00cc +#define DSIPORTA_LANE0Y 0x00ce +#define DSIPORTA_LANE1X 0x00d0 +#define DSIPORTA_LANE1Y 0x00d2 +#define DSIPORTA_LANE2X 0x00d4 +#define DSIPORTA_LANE2Y 0x00d6 +#define DSIPORTA_LANE3X 0x00d8 +#define DSIPORTA_LANE3Y 0x00da +#define DSIPORTA_LANE4X 0x00dc +#define DSIPORTA_LANE4Y 0x00de +#define DSIPORTC_LANE0X 0x00e0 +#define DSIPORTC_LANE0Y 0x00e2 +#define DSIPORTC_LANE1X 0x00e4 +#define DSIPORTC_LANE1Y 0x00e6 +#define DSIPORTC_LANE2X 0x00e8 +#define DSIPORTC_LANE2Y 0x00ea +#define DSIPORTC_LANE3X 0x00ec +#define DSIPORTC_LANE3Y 0x00ee +#define DSIPORTC_LANE4X 0x00f0 +#define DSIPORTC_LANE4Y 0x00f2 +#define DSIPORTC_TE0 0x00f4 +#define TIMER9_PWM_EVT 0x00f6 +#define I2C4_SCL 0x00f8 +#define I2C4_SDA 0x00fa +#define MCSPI2_CLK 0x00fc +#define MCSPI2_SIMO 0x00fe +#define MCSPI2_SOMI 0x0100 +#define MCSPI2_CS0 0x0102 +#define RFBI_DATA15 0x0104 +#define RFBI_DATA14 0x0106 +#define RFBI_DATA13 0x0108 +#define RFBI_DATA12 0x010a +#define RFBI_DATA11 0x010c +#define RFBI_DATA10 0x010e +#define RFBI_DATA9 0x0110 +#define RFBI_DATA8 0x0112 +#define RFBI_DATA7 0x0114 +#define RFBI_DATA6 0x0116 +#define RFBI_DATA5 0x0118 +#define RFBI_DATA4 0x011a +#define RFBI_DATA3 0x011c +#define RFBI_DATA2 0x011e +#define RFBI_DATA1 0x0120 +#define RFBI_DATA0 0x0122 +#define RFBI_WE 0x0124 +#define RFBI_CS0 0x0126 +#define RFBI_A0 0x0128 +#define RFBI_RE 0x012a +#define RFBI_HSYNC0 0x012c +#define RFBI_TE_VSYNC0 0x012e +#define GPIO6_182 0x0130 +#define GPIO6_183 0x0132 +#define GPIO6_184 0x0134 +#define GPIO6_185 0x0136 +#define GPIO6_186 0x0138 +#define GPIO6_187 0x013a +#define HDMI_CEC 0x013c +#define HDMI_HPD 0x013e +#define HDMI_DDC_SCL 0x0140 +#define HDMI_DDC_SDA 0x0142 +#define CSIPORTC_LANE0X 0x0144 +#define CSIPORTC_LANE0Y 0x0146 +#define CSIPORTC_LANE1X 0x0148 +#define CSIPORTC_LANE1Y 0x014a +#define CSIPORTB_LANE0X 0x014c +#define CSIPORTB_LANE0Y 0x014e +#define CSIPORTB_LANE1X 0x0150 +#define CSIPORTB_LANE1Y 0x0152 +#define CSIPORTB_LANE2X 0x0154 +#define CSIPORTB_LANE2Y 0x0156 +#define CSIPORTA_LANE0X 0x0158 +#define CSIPORTA_LANE0Y 0x015a +#define CSIPORTA_LANE1X 0x015c +#define CSIPORTA_LANE1Y 0x015e +#define CSIPORTA_LANE2X 0x0160 +#define CSIPORTA_LANE2Y 0x0162 +#define CSIPORTA_LANE3X 0x0164 +#define CSIPORTA_LANE3Y 0x0166 +#define CSIPORTA_LANE4X 0x0168 +#define CSIPORTA_LANE4Y 0x016a +#define CAM_SHUTTER 0x016c +#define CAM_STROBE 0x016e +#define CAM_GLOBALRESET 0x0170 +#define TIMER11_PWM_EVT 0x0172 +#define TIMER5_PWM_EVT 0x0174 +#define TIMER6_PWM_EVT 0x0176 +#define TIMER8_PWM_EVT 0x0178 +#define I2C3_SCL 0x017a +#define I2C3_SDA 0x017c +#define GPIO8_233 0x017e +#define GPIO8_234 0x0180 +#define ABE_CLKS 0x0182 +#define ABEDMIC_DIN1 0x0184 +#define ABEDMIC_DIN2 0x0186 +#define ABEDMIC_DIN3 0x0188 +#define ABEDMIC_CLK1 0x018a +#define ABEDMIC_CLK2 0x018c +#define ABEDMIC_CLK3 0x018e +#define ABESLIMBUS1_CLOCK 0x0190 +#define ABESLIMBUS1_DATA 0x0192 +#define ABEMCBSP2_DR 0x0194 +#define ABEMCBSP2_DX 0x0196 +#define ABEMCBSP2_FSX 0x0198 +#define ABEMCBSP2_CLKX 0x019a +#define ABEMCPDM_UL_DATA 0x019c +#define ABEMCPDM_DL_DATA 0x019e +#define ABEMCPDM_FRAME 0x01a0 +#define ABEMCPDM_LB_CLK 0x01a2 +#define WLSDIO_CLK 0x01a4 +#define WLSDIO_CMD 0x01a6 +#define WLSDIO_DATA0 0x01a8 +#define WLSDIO_DATA1 0x01aa +#define WLSDIO_DATA2 0x01ac +#define WLSDIO_DATA3 0x01ae +#define UART5_RX 0x01b0 +#define UART5_TX 0x01b2 +#define UART5_CTS 0x01b4 +#define UART5_RTS 0x01b6 +#define I2C2_SCL 0x01b8 +#define I2C2_SDA 0x01ba +#define MCSPI1_CLK 0x01bc +#define MCSPI1_SOMI 0x01be +#define MCSPI1_SIMO 0x01c0 +#define MCSPI1_CS0 0x01c2 +#define MCSPI1_CS1 0x01c4 +#define I2C5_SCL 0x01c6 +#define I2C5_SDA 0x01c8 +#define PERSLIMBUS2_CLOCK 0x01ca +#define PERSLIMBUS2_DATA 0x01cc +#define UART6_TX 0x01ce +#define UART6_RX 0x01d0 +#define UART6_CTS 0x01d2 +#define UART6_RTS 0x01d4 +#define UART3_CTS_RCTX 0x01d6 +#define UART3_RTS_IRSD 0x01d8 +#define UART3_TX_IRTX 0x01da +#define UART3_RX_IRRX 0x01dc +#define USBB3_HSIC_STROBE 0x01de +#define USBB3_HSIC_DATA 0x01e0 +#define SDCARD_CLK 0x01e2 +#define SDCARD_CMD 0x01e4 +#define SDCARD_DATA2 0x01e6 +#define SDCARD_DATA3 0x01e8 +#define SDCARD_DATA0 0x01ea +#define SDCARD_DATA1 0x01ec +#define USBD0_HS_DP 0x01ee +#define USBD0_HS_DM 0x01f0 +#define I2C1_PMIC_SCL 0x01f2 +#define I2C1_PMIC_SDA 0x01f4 +#define USBD0_SS_RX 0x01f6 + +#define LLIA_WAKEREQIN 0x0040 +#define LLIB_WAKEREQIN 0x0042 +#define DRM_EMU0 0x0044 +#define DRM_EMU1 0x0046 +#define JTAG_NTRST 0x0048 +#define JTAG_TCK 0x004a +#define JTAG_RTCK 0x004c +#define JTAG_TMSC 0x004e +#define JTAG_TDI 0x0050 +#define JTAG_TDO 0x0052 +#define SYS_32K 0x0054 +#define FREF_CLK_IOREQ 0x0056 +#define FREF_CLK0_OUT 0x0058 +#define FREF_CLK1_OUT 0x005a +#define FREF_CLK2_OUT 0x005c +#define FREF_CLK2_REQ 0x005e +#define FREF_CLK1_REQ 0x0060 +#define SYS_NRESPWRON 0x0062 +#define SYS_NRESWARM 0x0064 +#define SYS_PWR_REQ 0x0066 +#define SYS_NIRQ1 0x0068 +#define SYS_NIRQ2 0x006a +#define SR_PMIC_SCL 0x006c +#define SR_PMIC_SDA 0x006e +#define SYS_BOOT0 0x0070 +#define SYS_BOOT1 0x0072 +#define SYS_BOOT2 0x0074 +#define SYS_BOOT3 0x0076 +#define SYS_BOOT4 0x0078 +#define SYS_BOOT5 0x007a + +#endif /* _MUX_OMAP5_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap5/omap.h b/roms/u-boot/arch/arm/include/asm/arch-omap5/omap.h new file mode 100644 index 000000000..a9c0421b1 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap5/omap.h @@ -0,0 +1,271 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments, + * + * Authors: + * Aneesh V + * Sricharan R + */ + +#ifndef _OMAP5_H_ +#define _OMAP5_H_ + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +#include + +/* + * L4 Peripherals - L4 Wakeup and L4 Core now + */ +#define OMAP54XX_L4_CORE_BASE 0x4A000000 +#define OMAP54XX_L4_WKUP_BASE 0x4Ae00000 +#define OMAP54XX_L4_PER_BASE 0x48000000 + +/* CONTROL ID CODE */ +#define CONTROL_CORE_ID_CODE 0x4A002204 +#define CONTROL_WKUP_ID_CODE 0x4AE0C204 + +#if defined(CONFIG_DRA7XX) +#define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE +#else +#define CONTROL_ID_CODE CONTROL_CORE_ID_CODE +#endif + +#if defined(CONFIG_DRA7XX) +#define DRA7_USB_OTG_SS1_BASE 0x48890000 +#define DRA7_USB_OTG_SS1_GLUE_BASE 0x48880000 +#define DRA7_USB3_PHY1_PLL_CTRL 0x4A084C00 +#define DRA7_USB3_PHY1_POWER 0x4A002370 +#define DRA7_USB2_PHY1_POWER 0x4A002300 + +#define DRA7_USB_OTG_SS2_BASE 0x488D0000 +#define DRA7_USB_OTG_SS2_GLUE_BASE 0x488C0000 +#define DRA7_USB2_PHY2_POWER 0x4A002E74 +#else +#define OMAP5XX_USB_OTG_SS_BASE 0x4A030000 +#define OMAP5XX_USB_OTG_SS_GLUE_BASE 0x4A020000 +#define OMAP5XX_USB3_PHY_PLL_CTRL 0x4A084C00 +#define OMAP5XX_USB3_PHY_POWER 0x4A002370 +#define OMAP5XX_USB2_PHY_POWER 0x4A002300 +#endif + +/* To be verified */ +#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F +#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F +#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F +#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F +#define DRA762_CONTROL_ID_CODE_ES1_0 0x0BB5002F +#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F +#define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F +#define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F +#define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F +#define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F +#define DRA722_CONTROL_ID_CODE_ES2_1 0x2B9BC02F + +#define DRA762_ABZ_PACKAGE 0x2 +#define DRA762_ACD_PACKAGE 0x3 + +/* UART */ +#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) +#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) +#define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000) +#define UART4_BASE (OMAP54XX_L4_PER_BASE + 0x6e000) + +/* General Purpose Timers */ +#define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000) +#define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000) +#define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000) + +/* Watchdog Timer2 - MPU watchdog */ +#define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) + +/* QSPI */ +#define QSPI_BASE 0x4B300000 + +/* SATA */ +#define DWC_AHSATA_BASE 0x4A140000 + +/* + * Hardware Register Details + */ + +/* Watchdog Timer */ +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* GP Timer */ +#define TCLR_ST (0x1 << 0) +#define TCLR_AR (0x1 << 1) +#define TCLR_PRE (0x1 << 5) + +/* Control Module */ +#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) +#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f +#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 +#define CONTROL_EFUSE_2_OVERRIDE 0x00084000 + +/* LPDDR2 IO regs */ +#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C +#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E +#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C +#define LPDDR2IO_GR10_WD_MASK (3 << 17) +#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00 + +/* CONTROL_EFUSE_2 */ +#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 + +#define SDCARD_BIAS_PWRDNZ (1 << 27) +#define SDCARD_PWRDNZ (1 << 26) +#define SDCARD_BIAS_HIZ_MODE (1 << 25) +#define SDCARD_PBIASLITE_VMODE (1 << 21) + +#ifndef __ASSEMBLY__ + +struct s32ktimer { + unsigned char res[0x10]; + unsigned int s32k_cr; /* 0x10 */ +}; + +#define DEVICE_TYPE_SHIFT 0x6 +#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) + +/* Output impedance control */ +#define ds_120_ohm 0x0 +#define ds_60_ohm 0x1 +#define ds_45_ohm 0x2 +#define ds_30_ohm 0x3 +#define ds_mask 0x3 + +/* Slew rate control */ +#define sc_slow 0x0 +#define sc_medium 0x1 +#define sc_fast 0x2 +#define sc_na 0x3 +#define sc_mask 0x3 + +/* Target capacitance control */ +#define lb_5_12_pf 0x0 +#define lb_12_25_pf 0x1 +#define lb_25_50_pf 0x2 +#define lb_50_80_pf 0x3 +#define lb_mask 0x3 + +#define usb_i_mask 0x7 + +#define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082 +#define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200 +#define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421 +#define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084 +#define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000 + +#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C +#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464 +#define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631 +#define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC +#define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 + +#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C +#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464 +#define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 +#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC +#define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 + +#define EFUSE_1 0x45145100 +#define EFUSE_2 0x45145100 +#define EFUSE_3 0x45145100 +#define EFUSE_4 0x45145100 +#endif /* __ASSEMBLY__ */ + +/* + * In all cases, the TRM defines the RAM Memory Map for the processor + * and indicates the area for the downloaded image. We use all of that + * space for download and once up and running may use other parts of the + * map for our needs. We set a scratch space that is at the end of the + * OMAP5 download area, but within the DRA7xx download area (as it is + * much larger) and do not, at this time, make use of the additional + * space. + */ +#if defined(CONFIG_DRA7XX) +#define NON_SECURE_SRAM_START 0x40300000 +#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ +#define NON_SECURE_SRAM_IMG_END 0x4037C000 +#else +#define NON_SECURE_SRAM_START 0x40300000 +#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ +#define NON_SECURE_SRAM_IMG_END 0x4031E000 +#endif +#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K) + +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_ROM_VECT_BASE 0x4031F000 + +/* CONTROL_SRCOMP_XXX_SIDE */ +#define OVERRIDE_XS_SHIFT 30 +#define OVERRIDE_XS_MASK (1 << 30) +#define SRCODE_READ_XS_SHIFT 12 +#define SRCODE_READ_XS_MASK (0xff << 12) +#define PWRDWN_XS_SHIFT 11 +#define PWRDWN_XS_MASK (1 << 11) +#define DIVIDE_FACTOR_XS_SHIFT 4 +#define DIVIDE_FACTOR_XS_MASK (0x7f << 4) +#define MULTIPLY_FACTOR_XS_SHIFT 1 +#define MULTIPLY_FACTOR_XS_MASK (0x7 << 1) +#define SRCODE_OVERRIDE_SEL_XS_SHIFT 0 +#define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0) + +/* ABB settings */ +#define OMAP_ABB_SETTLING_TIME 50 +#define OMAP_ABB_CLOCK_CYCLES 16 + +/* ABB tranxdone mask */ +#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) +#define OMAP_ABB_MM_TXDONE_MASK (0x1 << 31) +#define OMAP_ABB_IVA_TXDONE_MASK (0x1 << 30) +#define OMAP_ABB_EVE_TXDONE_MASK (0x1 << 29) +#define OMAP_ABB_GPU_TXDONE_MASK (0x1 << 28) + +/* ABB efuse masks */ +#define OMAP5_PROD_ABB_FUSE_VSET_MASK (0x1F << 20) +#define OMAP5_PROD_ABB_FUSE_ENABLE_MASK (0x1 << 25) +#define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20) +#define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25) +#define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) +#define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0) + +#ifndef __ASSEMBLY__ +struct srcomp_params { + s8 divide_factor; + s8 multiply_factor; +}; + +struct ctrl_ioregs { + u32 ctrl_ddrch; + u32 ctrl_lpddr2ch; + u32 ctrl_ddr3ch; + u32 ctrl_ddrio_0; + u32 ctrl_ddrio_1; + u32 ctrl_ddrio_2; + u32 ctrl_emif_sdram_config_ext; + u32 ctrl_emif_sdram_config_ext_final; + u32 ctrl_ddr_ctrl_ext_0; +}; + +void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits); + +#endif /* __ASSEMBLY__ */ + +/* Boot parameters */ +#ifndef __ASSEMBLY__ +struct omap_boot_parameters { + unsigned int boot_message; + unsigned int boot_device_descriptor; + unsigned char boot_device; + unsigned char reset_reason; + unsigned char ch_flags; +}; +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap5/sata.h b/roms/u-boot/arch/arm/include/asm/arch-omap5/sata.h new file mode 100644 index 000000000..96c84fca0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap5/sata.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * SATA Wrapper Register map + * + * (C) Copyright 2013 + * Texas Instruments, + */ + +#ifndef _TI_SATA_H +#define _TI_SATA_H + +/* SATA Wrapper module */ +#define TI_SATA_WRAPPER_BASE (OMAP54XX_L4_CORE_BASE + 0x141100) +/* SATA PHY Module */ +#define TI_SATA_PLLCTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x96800) + +/* SATA Wrapper register offsets */ +#define TI_SATA_SYSCONFIG 0x00 +#define TI_SATA_CDRLOCK 0x04 + +/* Register Set */ +#define TI_SATA_SYSCONFIG_OVERRIDE0 (1 << 16) +#define TI_SATA_SYSCONFIG_STANDBY_MASK (0x3 << 4) +#define TI_SATA_SYSCONFIG_IDLE_MASK (0x3 << 2) + +/* Standby modes */ +#define TI_SATA_STANDBY_FORCE 0x0 +#define TI_SATA_STANDBY_NO (0x1 << 4) +#define TI_SATA_STANDBY_SMART_WAKE (0x3 << 4) +#define TI_SATA_STANDBY_SMART (0x2 << 4) + +/* Idle modes */ +#define TI_SATA_IDLE_FORCE 0x0 +#define TI_SATA_IDLE_NO (0x1 << 2) +#define TI_SATA_IDLE_SMART_WAKE (0x3 << 2) +#define TI_SATA_IDLE_SMART (0x2 << 2) + +#endif /* _TI_SATA_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap5/spl.h b/roms/u-boot/arch/arm/include/asm/arch-omap5/spl.h new file mode 100644 index 000000000..cda3b46f0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap5/spl.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Texas Instruments, + */ +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_ARCH_SPL_H_ + +#define BOOT_DEVICE_NONE 0x00 +#define BOOT_DEVICE_XIP 0x01 +#define BOOT_DEVICE_XIPWAIT 0x02 +#define BOOT_DEVICE_NAND 0x03 +#define BOOT_DEVICE_ONENAND 0x04 +#define BOOT_DEVICE_MMC1 0x05 +#define BOOT_DEVICE_MMC2 0x06 +#define BOOT_DEVICE_MMC2_2 0x07 +#define BOOT_DEVICE_SATA 0x09 +#define BOOT_DEVICE_SPI 0x0A +#define BOOT_DEVICE_QSPI_1 0x0A +#define BOOT_DEVICE_QSPI_4 0x0B +#define BOOT_DEVICE_UART 0x43 +#define BOOT_DEVICE_DFU 0x45 + +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2 +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-omap5/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-omap5/sys_proto.h new file mode 100644 index 000000000..80b0c93b5 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments, + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +#include +#include +#include +#include +#include +#include +#include + +/* + * Structure for Iodelay configuration registers. + * Theoretical max for g_delay is 21560 ps. + * Theoretical max for a_delay is 1/3rd of g_delay max. + * So using u16 for both a/g_delay. + */ +struct iodelay_cfg_entry { + u16 offset; + u16 a_delay; + u16 g_delay; +}; + +struct pad_conf_entry { + u32 offset; + u32 val; +}; + +struct mmc_platform_fixups { + const char *hw_rev; + u32 unsupported_caps; + u32 max_freq; +}; + +struct omap_sysinfo { + char *board_string; +}; +extern const struct omap_sysinfo sysinfo; + +void gpmc_init(void); +void watchdog_init(void); +u32 get_device_type(void); +void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); +void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size); +void set_muxconf_regs(void); +u32 wait_on_value(u32, u32, void *, u32); +void sdelay(unsigned long); +void setup_early_clocks(void); +void prcm_init(void); +void do_board_detect(void); +void vcores_init(void); +void bypass_dpll(u32 const base); +void freq_update_core(void); +u32 get_sys_clk_freq(void); +u32 omap5_ddr_clk(void); +void cancel_out(u32 *num, u32 *den, u32 den_limit); +void sdram_init(void); +u32 omap_sdram_size(void); +u32 cortex_rev(void); +void save_omap_boot_params(void); +void init_omap_revision(void); +void init_package_revision(void); +void do_io_settings(void); +void sri2c_init(void); +int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); +u32 warm_reset(void); +void force_emif_self_refresh(void); +void get_ioregs(const struct ctrl_ioregs **regs); +void srcomp_enable(void); +void setup_warmreset_time(void); +const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr); + +static inline u32 div_round_up(u32 num, u32 den) +{ + return (num + den - 1)/den; +} + +static inline u32 usec_to_32k(u32 usec) +{ + return div_round_up(32768 * usec, 1000000); +} + +#define OMAP5_SERVICE_L2ACTLR_SET 0x104 +#define OMAP5_SERVICE_ACR_SET 0x107 + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-orion5x/spl.h b/roms/u-boot/arch/arm/include/asm/arch-orion5x/spl.h new file mode 100644 index 000000000..dc0a9b909 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-orion5x/spl.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2014 Albert ARIBAUD + */ + +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_ARCH_SPL_H_ + +#define BOOT_DEVICE_NOR 1 diff --git a/roms/u-boot/arch/arm/include/asm/arch-owl/regs_s700.h b/roms/u-boot/arch/arm/include/asm/arch-owl/regs_s700.h new file mode 100644 index 000000000..0f79faec6 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-owl/regs_s700.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Actions Semi S700 Register Definitions + * + */ + +#ifndef _OWL_REGS_S700_H_ +#define _OWL_REGS_S700_H_ + +#define CMU_COREPLL 0x0000 +#define CMU_DEVPLL 0x0004 +#define CMU_DDRPLL 0x0008 +#define CMU_NANDPLL 0x000C +#define CMU_DISPLAYPLL 0x0010 +#define CMU_AUDIOPLL 0x0014 +#define CMU_TVOUTPLL 0x0018 +#define CMU_BUSCLK 0x001C +#define CMU_SENSORCLK 0x0020 +#define CMU_LCDCLK 0x0024 +#define CMU_DSIPLLCLK 0x0028 +#define CMU_CSICLK 0x002C +#define CMU_DECLK 0x0030 +#define CMU_SICLK 0x0034 +#define CMU_BUSCLK1 0x0038 +#define CMU_HDECLK 0x003C +#define CMU_VDECLK 0x0040 +#define CMU_VCECLK 0x0044 +#define CMU_NANDCCLK 0x004C +#define CMU_SD0CLK 0x0050 +#define CMU_SD1CLK 0x0054 +#define CMU_SD2CLK 0x0058 +#define CMU_UART0CLK 0x005C +#define CMU_UART1CLK 0x0060 +#define CMU_UART2CLK 0x0064 +#define CMU_UART3CLK 0x0068 +#define CMU_UART4CLK 0x006C +#define CMU_UART5CLK 0x0070 +#define CMU_UART6CLK 0x0074 +#define CMU_PWM0CLK 0x0078 +#define CMU_PWM1CLK 0x007C +#define CMU_PWM2CLK 0x0080 +#define CMU_PWM3CLK 0x0084 +#define CMU_PWM4CLK 0x0088 +#define CMU_PWM5CLK 0x008C +#define CMU_GPU3DCLK 0x0090 +#define CMU_CORECTL 0x009C +#define CMU_DEVCLKEN0 0x00A0 +#define CMU_DEVCLKEN1 0x00A4 +#define CMU_DEVRST0 0x00A8 +#define CMU_DEVRST1 0x00AC +#define CMU_USBPLL 0x00B0 +#define CMU_ETHERNETPLL 0x00B4 +#define CMU_CVBSPLL 0x00B8 +#define CMU_SSTSCLK 0x00C0 + +#define CMU_DEVCLKEN1_ETH BIT(23) + +#define GPIO_MFP_PWM (0xE01B0000) +#define MFP_CTL0 (GPIO_MFP_PWM + 0x40) +#define MFP_CTL1 (GPIO_MFP_PWM + 0x44) +#define MFP_CTL2 (GPIO_MFP_PWM + 0x48) +#define MFP_CTL3 (GPIO_MFP_PWM + 0x4C) + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-owl/regs_s900.h b/roms/u-boot/arch/arm/include/asm/arch-owl/regs_s900.h new file mode 100644 index 000000000..084bc9b8c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-owl/regs_s900.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Actions Semi S900 Register Definitions + * + * Copyright (C) 2015 Actions Semi Co., Ltd. + * Copyright (C) 2018 Manivannan Sadhasivam + * + */ + +#ifndef _OWL_REGS_S900_H_ +#define _OWL_REGS_S900_H_ + +/* CMU registers */ +#define CMU_COREPLL (0x0000) +#define CMU_DEVPLL (0x0004) +#define CMU_DDRPLL (0x0008) +#define CMU_NANDPLL (0x000C) +#define CMU_DISPLAYPLL (0x0010) +#define CMU_AUDIOPLL (0x0014) +#define CMU_TVOUTPLL (0x0018) +#define CMU_BUSCLK (0x001C) +#define CMU_SENSORCLK (0x0020) +#define CMU_LCDCLK (0x0024) +#define CMU_DSICLK (0x0028) +#define CMU_CSICLK (0x002C) +#define CMU_DECLK (0x0030) +#define CMU_BISPCLK (0x0034) +#define CMU_IMXCLK (0x0038) +#define CMU_HDECLK (0x003C) +#define CMU_VDECLK (0x0040) +#define CMU_VCECLK (0x0044) +#define CMU_NANDCCLK (0x004C) +#define CMU_SD0CLK (0x0050) +#define CMU_SD1CLK (0x0054) +#define CMU_SD2CLK (0x0058) +#define CMU_UART0CLK (0x005C) +#define CMU_UART1CLK (0x0060) +#define CMU_UART2CLK (0x0064) +#define CMU_PWM0CLK (0x0070) +#define CMU_PWM1CLK (0x0074) +#define CMU_PWM2CLK (0x0078) +#define CMU_PWM3CLK (0x007C) +#define CMU_USBPLL (0x0080) +#define CMU_ASSISTPLL (0x0084) +#define CMU_EDPCLK (0x0088) +#define CMU_GPU3DCLK (0x0090) +#define CMU_CORECTL (0x009C) +#define CMU_DEVCLKEN0 (0x00A0) +#define CMU_DEVCLKEN1 (0x00A4) +#define CMU_DEVRST0 (0x00A8) +#define CMU_DEVRST1 (0x00AC) +#define CMU_UART3CLK (0x00B0) +#define CMU_UART4CLK (0x00B4) +#define CMU_UART5CLK (0x00B8) +#define CMU_UART6CLK (0x00BC) +#define CMU_TLSCLK (0x00C0) +#define CMU_SD3CLK (0x00C4) +#define CMU_PWM4CLK (0x00C8) +#define CMU_PWM5CLK (0x00CC) +#define CMU_ANALOGDEBUG (0x00D4) +#define CMU_TVOUTPLLDEBUG0 (0x00EC) +#define CMU_TVOUTPLLDEBUG1 (0x00FC) + +#define CMU_DEVCLKEN1_ETH BIT(22) +#define CLK_ETHERNET CLK_ETH_MAC +#define CMU_ETHERNETPLL CMU_ASSISTPLL + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-px30/boot0.h b/roms/u-boot/arch/arm/include/asm/arch-px30/boot0.h new file mode 100644 index 000000000..2e78b074a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-px30/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-px30/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-px30/gpio.h new file mode 100644 index 000000000..eca79d515 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-px30/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-pxa/bitfield.h b/roms/u-boot/arch/arm/include/asm/arch-pxa/bitfield.h new file mode 100644 index 000000000..104a21c2e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-pxa/bitfield.h @@ -0,0 +1,112 @@ +/* + * FILE bitfield.h + * + * Version 1.1 + * Author Copyright (c) Marc A. Viredaz, 1998 + * DEC Western Research Laboratory, Palo Alto, CA + * Date April 1998 (April 1997) + * System Advanced RISC Machine (ARM) + * Language C or ARM Assembly + * Purpose Definition of macros to operate on bit fields. + */ + + +#ifndef __BITFIELD_H +#define __BITFIELD_H + +#ifndef __ASSEMBLY__ +#define UData(Data) ((unsigned long) (Data)) +#else +#define UData(Data) (Data) +#endif + + +/* + * MACRO: Fld + * + * Purpose + * The macro "Fld" encodes a bit field, given its size and its shift value + * with respect to bit 0. + * + * Note + * A more intuitive way to encode bit fields would have been to use their + * mask. However, extracting size and shift value information from a bit + * field's mask is cumbersome and might break the assembler (255-character + * line-size limit). + * + * Input + * Size Size of the bit field, in number of bits. + * Shft Shift value of the bit field with respect to bit 0. + * + * Output + * Fld Encoded bit field. + */ + +#define Fld(Size, Shft) (((Size) << 16) + (Shft)) + + +/* + * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit + * + * Purpose + * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return + * the size, shift value, mask, aligned mask, and first bit of a + * bit field. + * + * Input + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FSize Size of the bit field, in number of bits. + * FShft Shift value of the bit field with respect to bit 0. + * FMsk Mask for the bit field. + * FAlnMsk Mask for the bit field, aligned on bit 0. + * F1stBit First bit of the bit field. + */ + +#define FSize(Field) ((Field) >> 16) +#define FShft(Field) ((Field) & 0x0000FFFF) +#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) +#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) +#define F1stBit(Field) (UData (1) << FShft (Field)) + + +/* + * MACRO: FInsrt + * + * Purpose + * The macro "FInsrt" inserts a value into a bit field by shifting the + * former appropriately. + * + * Input + * Value Bit-field value. + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FInsrt Bit-field value positioned appropriately. + */ + +#define FInsrt(Value, Field) \ + (UData (Value) << FShft (Field)) + + +/* + * MACRO: FExtr + * + * Purpose + * The macro "FExtr" extracts the value of a bit field by masking and + * shifting it appropriately. + * + * Input + * Data Data containing the bit-field to be extracted. + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FExtr Bit-field value. + */ + +#define FExtr(Data, Field) \ + ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) + + +#endif /* __BITFIELD_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-pxa/config.h b/roms/u-boot/arch/arm/include/asm/arch-pxa/config.h new file mode 100644 index 000000000..75b0e491e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-pxa/config.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Andrew Ruder + */ + +#ifndef _ASM_ARM_PXA_CONFIG_ +#define _ASM_ARM_PXA_CONFIG_ + +#include + +/* + * Generic timer support + */ +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#define CONFIG_SYS_TIMER_RATE 3250000 +#elif defined(CONFIG_CPU_PXA25X) +#define CONFIG_SYS_TIMER_RATE 3686400 +#else +#error "Timer frequency unknown - please config PXA CPU type" +#endif + +#define CONFIG_SYS_TIMER_COUNTER OSCR + +#endif /* _ASM_ARM_PXA_CONFIG_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-pxa/hardware.h b/roms/u-boot/arch/arm/include/asm/arch-pxa/hardware.h new file mode 100644 index 000000000..6d0023d7b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-pxa/hardware.h @@ -0,0 +1,82 @@ +/* + * linux/include/asm-arm/arch-pxa/hardware.h + * + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Note: This file was taken from linux-2.4.19-rmk4-pxa1 + * + * - 2003/01/20 implementation specifics activated + * Robert Schwebel + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include + +/* + * Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected. + * PXA300/310/320 all have distinct register mappings in some cases, that's why + * the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common + * drivers and compatibility glue with old source then. + */ +#ifndef CONFIG_CPU_MONAHANS +#if defined(CONFIG_CPU_PXA300) || \ + defined(CONFIG_CPU_PXA310) || \ + defined(CONFIG_CPU_PXA320) +#define CONFIG_CPU_MONAHANS +#endif +#endif + +/* + * These are statically mapped PCMCIA IO space for designs using it as a + * generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc. + * The actual PCMCIA code is mapping required IO region at run time. + */ +#define PCMCIA_IO_0_BASE 0xf6000000 +#define PCMCIA_IO_1_BASE 0xf7000000 + + +/* + * We requires absolute addresses. + */ +#define PCIO_BASE 0 + +/* + * Workarounds for at least 2 errata so far require this. + * The mapping is set in mach-pxa/generic.c. + */ +#define UNCACHED_PHYS_0 0xff000000 +#define UNCACHED_ADDR UNCACHED_PHYS_0 + +/* + * Intel PXA internal I/O mappings: + * + * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff + * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff + * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff + */ + +#include "pxa-regs.h" + +#ifndef __ASSEMBLY__ + +/* + * GPIO edge detection for IRQs: + * IRQs are generated on Falling-Edge, Rising-Edge, or both. + * This must be called *before* the corresponding IRQ is registered. + * Use this instead of directly setting GRER/GFER. + */ +#define GPIO_FALLING_EDGE 1 +#define GPIO_RISING_EDGE 2 +#define GPIO_BOTH_EDGES 3 + +#endif + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-pxa/pxa-regs.h b/roms/u-boot/arch/arm/include/asm/arch-pxa/pxa-regs.h new file mode 100644 index 000000000..b81b42c07 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-pxa/pxa-regs.h @@ -0,0 +1,2635 @@ +/* + * linux/include/asm-arm/arch-pxa/pxa-regs.h + * + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * - 2003/01/20: Robert Schwebel */ +#define GPLR1 0x40E00004 /* GPIO Pin-Level Register GPIO<63:32> */ +#define GPLR2 0x40E00008 /* GPIO Pin-Level Register GPIO<80:64> */ + +#define GPDR0 0x40E0000C /* GPIO Pin Direction Register GPIO<31:0> */ +#define GPDR1 0x40E00010 /* GPIO Pin Direction Register GPIO<63:32> */ +#define GPDR2 0x40E00014 /* GPIO Pin Direction Register GPIO<80:64> */ + +#define GPSR0 0x40E00018 /* GPIO Pin Output Set Register GPIO<31:0> */ +#define GPSR1 0x40E0001C /* GPIO Pin Output Set Register GPIO<63:32> */ +#define GPSR2 0x40E00020 /* GPIO Pin Output Set Register GPIO<80:64> */ + +#define GPCR0 0x40E00024 /* GPIO Pin Output Clear Register GPIO<31:0> */ +#define GPCR1 0x40E00028 /* GPIO Pin Output Clear Register GPIO <63:32> */ +#define GPCR2 0x40E0002C /* GPIO Pin Output Clear Register GPIO <80:64> */ + +#define GRER0 0x40E00030 /* GPIO Rising-Edge Detect Register GPIO<31:0> */ +#define GRER1 0x40E00034 /* GPIO Rising-Edge Detect Register GPIO<63:32> */ +#define GRER2 0x40E00038 /* GPIO Rising-Edge Detect Register GPIO<80:64> */ + +#define GFER0 0x40E0003C /* GPIO Falling-Edge Detect Register GPIO<31:0> */ +#define GFER1 0x40E00040 /* GPIO Falling-Edge Detect Register GPIO<63:32> */ +#define GFER2 0x40E00044 /* GPIO Falling-Edge Detect Register GPIO<80:64> */ + +#define GEDR0 0x40E00048 /* GPIO Edge Detect Status Register GPIO<31:0> */ +#define GEDR1 0x40E0004C /* GPIO Edge Detect Status Register GPIO<63:32> */ +#define GEDR2 0x40E00050 /* GPIO Edge Detect Status Register GPIO<80:64> */ + +#define GAFR0_L 0x40E00054 /* GPIO Alternate Function Select Register GPIO<15:0> */ +#define GAFR0_U 0x40E00058 /* GPIO Alternate Function Select Register GPIO<31:16> */ +#define GAFR1_L 0x40E0005C /* GPIO Alternate Function Select Register GPIO<47:32> */ +#define GAFR1_U 0x40E00060 /* GPIO Alternate Function Select Register GPIO<63:48> */ +#define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO<79:64> */ +#define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO 80 */ + +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#define GPLR3 0x40E00100 /* GPIO Pin-Level Register GPIO<127:96> */ +#define GPDR3 0x40E0010C /* GPIO Pin Direction Register GPIO<127:96> */ +#define GPSR3 0x40E00118 /* GPIO Pin Output Set Register GPIO<127:96> */ +#define GPCR3 0x40E00124 /* GPIO Pin Output Clear Register GPIO<127:96> */ +#define GRER3 0x40E00130 /* GPIO Rising-Edge Detect Register GPIO<127:96> */ +#define GFER3 0x40E0013C /* GPIO Falling-Edge Detect Register GPIO<127:96> */ +#define GEDR3 0x40E00148 /* GPIO Edge Detect Status Register GPIO<127:96> */ +#define GAFR3_L 0x40E0006C /* GPIO Alternate Function Select Register GPIO<111:96> */ +#define GAFR3_U 0x40E00070 /* GPIO Alternate Function Select Register GPIO<127:112> */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ + +#ifdef CONFIG_CPU_MONAHANS +#define GSDR0 0x40E00400 /* Bit-wise Set of GPDR[31:0] */ +#define GSDR1 0x40E00404 /* Bit-wise Set of GPDR[63:32] */ +#define GSDR2 0x40E00408 /* Bit-wise Set of GPDR[95:64] */ +#define GSDR3 0x40E0040C /* Bit-wise Set of GPDR[127:96] */ + +#define GCDR0 0x40E00420 /* Bit-wise Clear of GPDR[31:0] */ +#define GCDR1 0x40E00424 /* Bit-wise Clear of GPDR[63:32] */ +#define GCDR2 0x40E00428 /* Bit-wise Clear of GPDR[95:64] */ +#define GCDR3 0x40E0042C /* Bit-wise Clear of GPDR[127:96] */ + +#define GSRER0 0x40E00440 /* Set Rising Edge Det. Enable [31:0] */ +#define GSRER1 0x40E00444 /* Set Rising Edge Det. Enable [63:32] */ +#define GSRER2 0x40E00448 /* Set Rising Edge Det. Enable [95:64] */ +#define GSRER3 0x40E0044C /* Set Rising Edge Det. Enable [127:96] */ + +#define GCRER0 0x40E00460 /* Clear Rising Edge Det. Enable [31:0] */ +#define GCRER1 0x40E00464 /* Clear Rising Edge Det. Enable [63:32] */ +#define GCRER2 0x40E00468 /* Clear Rising Edge Det. Enable [95:64] */ +#define GCRER3 0x40E0046C /* Clear Rising Edge Det. Enable[127:96] */ + +#define GSFER0 0x40E00480 /* Set Falling Edge Det. Enable [31:0] */ +#define GSFER1 0x40E00484 /* Set Falling Edge Det. Enable [63:32] */ +#define GSFER2 0x40E00488 /* Set Falling Edge Det. Enable [95:64] */ +#define GSFER3 0x40E0048C /* Set Falling Edge Det. Enable[127:96] */ + +#define GCFER0 0x40E004A0 /* Clr Falling Edge Det. Enable [31:0] */ +#define GCFER1 0x40E004A4 /* Clr Falling Edge Det. Enable [63:32] */ +#define GCFER2 0x40E004A8 /* Clr Falling Edge Det. Enable [95:64] */ +#define GCFER3 0x40E004AC /* Clr Falling Edge Det. Enable[127:96] */ + +#define GSDR(x) (0x40E00400 | ((x) & 0x60) >> 3) +#define GCDR(x) (0x40E00420 | ((x) & 0x60) >> 3) +#endif + +#define _GPLR(x) (0x40E00000 + (((x) & 0x60) >> 3)) +#define _GPDR(x) (0x40E0000C + (((x) & 0x60) >> 3)) +#define _GPSR(x) (0x40E00018 + (((x) & 0x60) >> 3)) +#define _GPCR(x) (0x40E00024 + (((x) & 0x60) >> 3)) +#define _GRER(x) (0x40E00030 + (((x) & 0x60) >> 3)) +#define _GFER(x) (0x40E0003C + (((x) & 0x60) >> 3)) +#define _GEDR(x) (0x40E00048 + (((x) & 0x60) >> 3)) +#define _GAFR(x) (0x40E00054 + (((x) & 0x70) >> 2)) + +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#define GPLR(x) (((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)) +#define GPDR(x) (((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)) +#define GPSR(x) (((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)) +#define GPCR(x) (((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)) +#define GRER(x) (((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)) +#define GFER(x) (((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)) +#define GEDR(x) (((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)) +#define GAFR(x) (((((x) & 0x7f) < 96) ? _GAFR(x) : \ + ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))) +#else +#define GPLR(x) _GPLR(x) +#define GPDR(x) _GPDR(x) +#define GPSR(x) _GPSR(x) +#define GPCR(x) _GPCR(x) +#define GRER(x) _GRER(x) +#define GFER(x) _GFER(x) +#define GEDR(x) _GEDR(x) +#define GAFR(x) _GAFR(x) +#endif + +#define GPIO_bit(x) (1 << ((x) & 0x1f)) + +/******************************************************************************/ +/* + * Multi-function Pin Registers: + */ +/* PXA320 */ +#if defined(CONFIG_CPU_PXA320) +#define DF_IO0 0x40e1024c +#define DF_IO1 0x40e10254 +#define DF_IO2 0x40e1025c +#define DF_IO3 0x40e10264 +#define DF_IO4 0x40e1026c +#define DF_IO5 0x40e10274 +#define DF_IO6 0x40e1027c +#define DF_IO7 0x40e10284 +#define DF_IO8 0x40e10250 +#define DF_IO9 0x40e10258 +#define DF_IO10 0x40e10260 +#define DF_IO11 0x40e10268 +#define DF_IO12 0x40e10270 +#define DF_IO13 0x40e10278 +#define DF_IO14 0x40e10280 +#define DF_IO15 0x40e10288 +#define DF_CLE_nOE 0x40e10204 +#define DF_ALE_nWE1 0x40e10208 +#define DF_ALE_nWE2 0x40e1021c +#define DF_SCLK_E 0x40e10210 +#define DF_nCS0 0x40e10224 +#define DF_nCS1 0x40e10228 +#define nBE0 0x40e10214 +#define nBE1 0x40e10218 +#define nLUA 0x40e10234 +#define nLLA 0x40e10238 +#define DF_ADDR0 0x40e1023c +#define DF_ADDR1 0x40e10240 +#define DF_ADDR2 0x40e10244 +#define DF_ADDR3 0x40e10248 +#define DF_INT_RnB 0x40e10220 +#define DF_nCS0 0x40e10224 +#define DF_nCS1 0x40e10228 +#define DF_nWE 0x40e1022c +#define DF_nRE 0x40e10230 + +#define nXCVREN 0x40e10138 + +#define GPIO0 0x40e10124 +#define GPIO1 0x40e10128 +#define GPIO2 0x40e1012c +#define GPIO3 0x40e10130 +#define GPIO4 0x40e10134 +#define GPIO5 0x40e1028c +#define GPIO6 0x40e10290 +#define GPIO7 0x40e10294 +#define GPIO8 0x40e10298 +#define GPIO9 0x40e1029c +#define GPIO10 0x40e10458 +#define GPIO11 0x40e102a0 +#define GPIO12 0x40e102a4 +#define GPIO13 0x40e102a8 +#define GPIO14 0x40e102ac +#define GPIO15 0x40e102b0 +#define GPIO16 0x40e102b4 +#define GPIO17 0x40e102b8 +#define GPIO18 0x40e102bc +#define GPIO19 0x40e102c0 +#define GPIO20 0x40e102c4 +#define GPIO21 0x40e102c8 +#define GPIO22 0x40e102cc +#define GPIO23 0x40e102d0 +#define GPIO24 0x40e102d4 +#define GPIO25 0x40e102d8 +#define GPIO26 0x40e102dc + +#define GPIO27 0x40e10400 +#define GPIO28 0x40e10404 +#define GPIO29 0x40e10408 +#define GPIO30 0x40e1040c +#define GPIO31 0x40e10410 +#define GPIO32 0x40e10414 +#define GPIO33 0x40e10418 +#define GPIO34 0x40e1041c +#define GPIO35 0x40e10420 +#define GPIO36 0x40e10424 +#define GPIO37 0x40e10428 +#define GPIO38 0x40e1042c +#define GPIO39 0x40e10430 +#define GPIO40 0x40e10434 +#define GPIO41 0x40e10438 +#define GPIO42 0x40e1043c +#define GPIO43 0x40e10440 +#define GPIO44 0x40e10444 +#define GPIO45 0x40e10448 +#define GPIO46 0x40e1044c +#define GPIO47 0x40e10450 +#define GPIO48 0x40e10454 +#define GPIO49 0x40e1045c +#define GPIO50 0x40e10460 +#define GPIO51 0x40e10464 +#define GPIO52 0x40e10468 +#define GPIO53 0x40e1046c +#define GPIO54 0x40e10470 +#define GPIO55 0x40e10474 +#define GPIO56 0x40e10478 +#define GPIO57 0x40e1047c +#define GPIO58 0x40e10480 +#define GPIO59 0x40e10484 +#define GPIO60 0x40e10488 +#define GPIO61 0x40e1048c +#define GPIO62 0x40e10490 + +#define GPIO6_2 0x40e10494 +#define GPIO7_2 0x40e10498 +#define GPIO8_2 0x40e1049c +#define GPIO9_2 0x40e104a0 +#define GPIO10_2 0x40e104a4 +#define GPIO11_2 0x40e104a8 +#define GPIO12_2 0x40e104ac +#define GPIO13_2 0x40e104b0 + +#define GPIO63 0x40e104b4 +#define GPIO64 0x40e104b8 +#define GPIO65 0x40e104bc +#define GPIO66 0x40e104c0 +#define GPIO67 0x40e104c4 +#define GPIO68 0x40e104c8 +#define GPIO69 0x40e104cc +#define GPIO70 0x40e104d0 +#define GPIO71 0x40e104d4 +#define GPIO72 0x40e104d8 +#define GPIO73 0x40e104dc + +#define GPIO14_2 0x40e104e0 +#define GPIO15_2 0x40e104e4 +#define GPIO16_2 0x40e104e8 +#define GPIO17_2 0x40e104ec + +#define GPIO74 0x40e104f0 +#define GPIO75 0x40e104f4 +#define GPIO76 0x40e104f8 +#define GPIO77 0x40e104fc +#define GPIO78 0x40e10500 +#define GPIO79 0x40e10504 +#define GPIO80 0x40e10508 +#define GPIO81 0x40e1050c +#define GPIO82 0x40e10510 +#define GPIO83 0x40e10514 +#define GPIO84 0x40e10518 +#define GPIO85 0x40e1051c +#define GPIO86 0x40e10520 +#define GPIO87 0x40e10524 +#define GPIO88 0x40e10528 +#define GPIO89 0x40e1052c +#define GPIO90 0x40e10530 +#define GPIO91 0x40e10534 +#define GPIO92 0x40e10538 +#define GPIO93 0x40e1053c +#define GPIO94 0x40e10540 +#define GPIO95 0x40e10544 +#define GPIO96 0x40e10548 +#define GPIO97 0x40e1054c +#define GPIO98 0x40e10550 + +#define GPIO99 0x40e10600 +#define GPIO100 0x40e10604 +#define GPIO101 0x40e10608 +#define GPIO102 0x40e1060c +#define GPIO103 0x40e10610 +#define GPIO104 0x40e10614 +#define GPIO105 0x40e10618 +#define GPIO106 0x40e1061c +#define GPIO107 0x40e10620 +#define GPIO108 0x40e10624 +#define GPIO109 0x40e10628 +#define GPIO110 0x40e1062c +#define GPIO111 0x40e10630 +#define GPIO112 0x40e10634 + +#define GPIO113 0x40e10638 +#define GPIO114 0x40e1063c +#define GPIO115 0x40e10640 +#define GPIO116 0x40e10644 +#define GPIO117 0x40e10648 +#define GPIO118 0x40e1064c +#define GPIO119 0x40e10650 +#define GPIO120 0x40e10654 +#define GPIO121 0x40e10658 +#define GPIO122 0x40e1065c +#define GPIO123 0x40e10660 +#define GPIO124 0x40e10664 +#define GPIO125 0x40e10668 +#define GPIO126 0x40e1066c +#define GPIO127 0x40e10670 + +#define GPIO0_2 0x40e10674 +#define GPIO1_2 0x40e10678 +#define GPIO2_2 0x40e1067c +#define GPIO3_2 0x40e10680 +#define GPIO4_2 0x40e10684 +#define GPIO5_2 0x40e10688 + +/* PXA300 and PXA310 */ +#elif defined(CONFIG_CPU_PXA300) || defined(CONFIG_CPU_PXA310) +#define DF_IO0 0x40e10220 +#define DF_IO1 0x40e10228 +#define DF_IO2 0x40e10230 +#define DF_IO3 0x40e10238 +#define DF_IO4 0x40e10258 +#define DF_IO5 0x40e10260 +#define DF_IO7 0x40e10270 +#define DF_IO6 0x40e10268 +#define DF_IO8 0x40e10224 +#define DF_IO9 0x40e1022c +#define DF_IO10 0x40e10234 +#define DF_IO11 0x40e1023c +#define DF_IO12 0x40e1025c +#define DF_IO13 0x40e10264 +#define DF_IO14 0x40e1026c +#define DF_IO15 0x40e10274 +#define DF_CLE_NOE 0x40e10240 +#define DF_ALE_nWE 0x40e1020c +#define DF_SCLK_E 0x40e10250 +#define nCS0 0x40e100c4 +#define nCS1 0x40e100c0 +#define nBE0 0x40e10204 +#define nBE1 0x40e10208 +#define nLUA 0x40e10244 +#define nLLA 0x40e10254 +#define DF_ADDR0 0x40e10210 +#define DF_ADDR1 0x40e10214 +#define DF_ADDR2 0x40e10218 +#define DF_ADDR3 0x40e1021c +#define DF_INT_RnB 0x40e100c8 +#define DF_nCS0 0x40e10248 +#define DF_nCS1 0x40e10278 +#define DF_nWE 0x40e100cc +#define DF_nRE 0x40e10200 + +#define GPIO0 0x40e100b4 +#define GPIO1 0x40e100b8 +#define GPIO2 0x40e100bc +#define GPIO3 0x40e1027c +#define GPIO4 0x40e10280 + +#define GPIO5 0x40e10284 +#define GPIO6 0x40e10288 +#define GPIO7 0x40e1028c +#define GPIO8 0x40e10290 +#define GPIO9 0x40e10294 +#define GPIO10 0x40e10298 +#define GPIO11 0x40e1029c +#define GPIO12 0x40e102a0 +#define GPIO13 0x40e102a4 +#define GPIO14 0x40e102a8 +#define GPIO15 0x40e102ac +#define GPIO16 0x40e102b0 +#define GPIO17 0x40e102b4 +#define GPIO18 0x40e102b8 +#define GPIO19 0x40e102bc +#define GPIO20 0x40e102c0 +#define GPIO21 0x40e102c4 +#define GPIO22 0x40e102c8 +#define GPIO23 0x40e102cc +#define GPIO24 0x40e102d0 +#define GPIO25 0x40e102d4 +#define GPIO26 0x40e102d8 + +#define GPIO27 0x40e10400 +#define GPIO28 0x40e10404 +#define GPIO29 0x40e10408 +#define ULPI_STP 0x40e1040c +#define ULPI_NXT 0x40e10410 +#define ULPI_DIR 0x40e10414 +#define GPIO30 0x40e10418 +#define GPIO31 0x40e1041c +#define GPIO32 0x40e10420 +#define GPIO33 0x40e10424 +#define GPIO34 0x40e10428 +#define GPIO35 0x40e1042c +#define GPIO36 0x40e10430 +#define GPIO37 0x40e10434 +#define GPIO38 0x40e10438 +#define GPIO39 0x40e1043c +#define GPIO40 0x40e10440 +#define GPIO41 0x40e10444 +#define GPIO42 0x40e10448 +#define GPIO43 0x40e1044c +#define GPIO44 0x40e10450 +#define GPIO45 0x40e10454 +#define GPIO46 0x40e10458 +#define GPIO47 0x40e1045c +#define GPIO48 0x40e10460 + +#define GPIO49 0x40e10464 +#define GPIO50 0x40e10468 +#define GPIO51 0x40e1046c +#define GPIO52 0x40e10470 +#define GPIO53 0x40e10474 +#define GPIO54 0x40e10478 +#define GPIO55 0x40e1047c +#define GPIO56 0x40e10480 +#define GPIO57 0x40e10484 +#define GPIO58 0x40e10488 +#define GPIO59 0x40e1048c +#define GPIO60 0x40e10490 +#define GPIO61 0x40e10494 +#define GPIO62 0x40e10498 +#define GPIO63 0x40e1049c +#define GPIO64 0x40e104a0 +#define GPIO65 0x40e104a4 +#define GPIO66 0x40e104a8 +#define GPIO67 0x40e104ac +#define GPIO68 0x40e104b0 +#define GPIO69 0x40e104b4 +#define GPIO70 0x40e104b8 +#define GPIO71 0x40e104bc +#define GPIO72 0x40e104c0 +#define GPIO73 0x40e104c4 +#define GPIO74 0x40e104c8 +#define GPIO75 0x40e104cc +#define GPIO76 0x40e104d0 +#define GPIO77 0x40e104d4 +#define GPIO78 0x40e104d8 +#define GPIO79 0x40e104dc +#define GPIO80 0x40e104e0 +#define GPIO81 0x40e104e4 +#define GPIO82 0x40e104e8 +#define GPIO83 0x40e104ec +#define GPIO84 0x40e104f0 +#define GPIO85 0x40e104f4 +#define GPIO86 0x40e104f8 +#define GPIO87 0x40e104fc +#define GPIO88 0x40e10500 +#define GPIO89 0x40e10504 +#define GPIO90 0x40e10508 +#define GPIO91 0x40e1050c +#define GPIO92 0x40e10510 +#define GPIO93 0x40e10514 +#define GPIO94 0x40e10518 +#define GPIO95 0x40e1051c +#define GPIO96 0x40e10520 +#define GPIO97 0x40e10524 +#define GPIO98 0x40e10528 + +#define GPIO99 0x40e10600 +#define GPIO100 0x40e10604 +#define GPIO101 0x40e10608 +#define GPIO102 0x40e1060c +#define GPIO103 0x40e10610 +#define GPIO104 0x40e10614 +#define GPIO105 0x40e10618 +#define GPIO106 0x40e1061c +#define GPIO107 0x40e10620 +#define GPIO108 0x40e10624 +#define GPIO109 0x40e10628 +#define GPIO110 0x40e1062c +#define GPIO111 0x40e10630 +#define GPIO112 0x40e10634 + +#define GPIO113 0x40e10638 +#define GPIO114 0x40e1063c +#define GPIO115 0x40e10640 +#define GPIO116 0x40e10644 +#define GPIO117 0x40e10648 +#define GPIO118 0x40e1064c +#define GPIO119 0x40e10650 +#define GPIO120 0x40e10654 +#define GPIO121 0x40e10658 +#define GPIO122 0x40e1065c +#define GPIO123 0x40e10660 +#define GPIO124 0x40e10664 +#define GPIO125 0x40e10668 +#define GPIO126 0x40e1066c +#define GPIO127 0x40e10670 + +#define GPIO0_2 0x40e10674 +#define GPIO1_2 0x40e10678 +#define GPIO2_2 0x40e102dc +#define GPIO3_2 0x40e102e0 +#define GPIO4_2 0x40e102e4 +#define GPIO5_2 0x40e102e8 +#define GPIO6_2 0x40e102ec + +#ifndef CONFIG_CPU_PXA300 /* PXA310 only */ +#define GPIO7_2 0x40e1052c +#define GPIO8_2 0x40e10530 +#define GPIO9_2 0x40e10534 +#define GPIO10_2 0x40e10538 +#endif +#endif + +#ifdef CONFIG_CPU_MONAHANS +/* MFPR Bit Definitions, see 4-10, Vol. 1 */ +#define PULL_SEL 0x8000 +#define PULLUP_EN 0x4000 +#define PULLDOWN_EN 0x2000 + +#define DRIVE_FAST_1mA 0x0 +#define DRIVE_FAST_2mA 0x400 +#define DRIVE_FAST_3mA 0x800 +#define DRIVE_FAST_4mA 0xC00 +#define DRIVE_SLOW_6mA 0x1000 +#define DRIVE_FAST_6mA 0x1400 +#define DRIVE_SLOW_10mA 0x1800 +#define DRIVE_FAST_10mA 0x1C00 + +#define SLEEP_SEL 0x200 +#define SLEEP_DATA 0x100 +#define SLEEP_OE_N 0x80 +#define EDGE_CLEAR 0x40 +#define EDGE_FALL_EN 0x20 +#define EDGE_RISE_EN 0x10 + +#define AF_SEL_0 0x0 /* Alternate function 0 (reset state) */ +#define AF_SEL_1 0x1 /* Alternate function 1 */ +#define AF_SEL_2 0x2 /* Alternate function 2 */ +#define AF_SEL_3 0x3 /* Alternate function 3 */ +#define AF_SEL_4 0x4 /* Alternate function 4 */ +#define AF_SEL_5 0x5 /* Alternate function 5 */ +#define AF_SEL_6 0x6 /* Alternate function 6 */ +#define AF_SEL_7 0x7 /* Alternate function 7 */ + +#endif /* CONFIG_CPU_MONAHANS */ + +/* GPIO alternate function assignments */ + +#define GPIO1_RST 1 /* reset */ +#define GPIO6_MMCCLK 6 /* MMC Clock */ +#define GPIO8_48MHz 7 /* 48 MHz clock output */ +#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */ +#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */ +#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */ +#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */ +#define GPIO12_32KHz 12 /* 32 kHz out */ +#define GPIO13_MBGNT 13 /* memory controller grant */ +#define GPIO14_MBREQ 14 /* alternate bus master request */ +#define GPIO15_nCS_1 15 /* chip select 1 */ +#define GPIO16_PWM0 16 /* PWM0 output */ +#define GPIO17_PWM1 17 /* PWM1 output */ +#define GPIO18_RDY 18 /* Ext. Bus Ready */ +#define GPIO19_DREQ1 19 /* External DMA Request */ +#define GPIO20_DREQ0 20 /* External DMA Request */ +#define GPIO23_SCLK 23 /* SSP clock */ +#define GPIO24_SFRM 24 /* SSP Frame */ +#define GPIO25_STXD 25 /* SSP transmit */ +#define GPIO26_SRXD 26 /* SSP receive */ +#define GPIO27_SEXTCLK 27 /* SSP ext_clk */ +#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ +#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ +#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ +#define GPIO31_SYNC 31 /* AC97/I2S sync */ +#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */ +#define GPIO33_nCS_5 33 /* chip select 5 */ +#define GPIO34_FFRXD 34 /* FFUART receive */ +#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */ +#define GPIO35_FFCTS 35 /* FFUART Clear to send */ +#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */ +#define GPIO37_FFDSR 37 /* FFUART data set ready */ +#define GPIO38_FFRI 38 /* FFUART Ring Indicator */ +#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */ +#define GPIO39_FFTXD 39 /* FFUART transmit data */ +#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ +#define GPIO41_FFRTS 41 /* FFUART request to send */ +#define GPIO42_BTRXD 42 /* BTUART receive data */ +#define GPIO43_BTTXD 43 /* BTUART transmit data */ +#define GPIO44_BTCTS 44 /* BTUART clear to send */ +#define GPIO45_BTRTS 45 /* BTUART request to send */ +#define GPIO46_ICPRXD 46 /* ICP receive data */ +#define GPIO46_STRXD 46 /* STD_UART receive data */ +#define GPIO47_ICPTXD 47 /* ICP transmit data */ +#define GPIO47_STTXD 47 /* STD_UART transmit data */ +#define GPIO48_nPOE 48 /* Output Enable for Card Space */ +#define GPIO49_nPWE 49 /* Write Enable for Card Space */ +#define GPIO50_nPIOR 50 /* I/O Read for Card Space */ +#define GPIO51_nPIOW 51 /* I/O Write for Card Space */ +#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */ +#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */ +#define GPIO53_MMCCLK 53 /* MMC Clock */ +#define GPIO54_MMCCLK 54 /* MMC Clock */ +#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */ +#define GPIO55_nPREG 55 /* Card Address bit 26 */ +#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */ +#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */ +#define GPIO58_LDD_0 58 /* LCD data pin 0 */ +#define GPIO59_LDD_1 59 /* LCD data pin 1 */ +#define GPIO60_LDD_2 60 /* LCD data pin 2 */ +#define GPIO61_LDD_3 61 /* LCD data pin 3 */ +#define GPIO62_LDD_4 62 /* LCD data pin 4 */ +#define GPIO63_LDD_5 63 /* LCD data pin 5 */ +#define GPIO64_LDD_6 64 /* LCD data pin 6 */ +#define GPIO65_LDD_7 65 /* LCD data pin 7 */ +#define GPIO66_LDD_8 66 /* LCD data pin 8 */ +#define GPIO66_MBREQ 66 /* alternate bus master req */ +#define GPIO67_LDD_9 67 /* LCD data pin 9 */ +#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */ +#define GPIO68_LDD_10 68 /* LCD data pin 10 */ +#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */ +#define GPIO69_LDD_11 69 /* LCD data pin 11 */ +#define GPIO69_MMCCLK 69 /* MMC_CLK */ +#define GPIO70_LDD_12 70 /* LCD data pin 12 */ +#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */ +#define GPIO71_LDD_13 71 /* LCD data pin 13 */ +#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */ +#define GPIO72_LDD_14 72 /* LCD data pin 14 */ +#define GPIO72_32kHz 72 /* 32 kHz clock */ +#define GPIO73_LDD_15 73 /* LCD data pin 15 */ +#define GPIO73_MBGNT 73 /* Memory controller grant */ +#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */ +#define GPIO75_LCD_LCLK 75 /* LCD line clock */ +#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */ +#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ +#define GPIO78_nCS_2 78 /* chip select 2 */ +#define GPIO79_nCS_3 79 /* chip select 3 */ +#define GPIO80_nCS_4 80 /* chip select 4 */ + +/* GPIO alternate function mode & direction */ + +#define GPIO_IN 0x000 +#define GPIO_OUT 0x080 +#define GPIO_ALT_FN_1_IN 0x100 +#define GPIO_ALT_FN_1_OUT 0x180 +#define GPIO_ALT_FN_2_IN 0x200 +#define GPIO_ALT_FN_2_OUT 0x280 +#define GPIO_ALT_FN_3_IN 0x300 +#define GPIO_ALT_FN_3_OUT 0x380 +#define GPIO_MD_MASK_NR 0x07f +#define GPIO_MD_MASK_DIR 0x080 +#define GPIO_MD_MASK_FN 0x300 + +#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN) +#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT) +#define GPIO8_48MHz_MD ( 8 | GPIO_ALT_FN_1_OUT) +#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT) +#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT) +#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT) +#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT) +#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT) +#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT) +#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN) +#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT) +#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT) +#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT) +#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) +#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) +#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) +#define GPIO23_SCLK_md (23 | GPIO_ALT_FN_2_OUT) +#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) +#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) +#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) +#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) +#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) +#define GPIO28_BITCLK_I2S_MD (28 | GPIO_ALT_FN_2_IN) +#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN) +#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN) +#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT) +#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT) +#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT) +#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT) +#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN) +#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT) +#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN) +#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT) +#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN) +#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN) +#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN) +#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN) +#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT) +#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT) +#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) +#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) +#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) +#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) +#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) +#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) +#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) +#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) +#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) +#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) +#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) +#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) +#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) +#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) +#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) +#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) +#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT) +#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT) +#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT) +#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT) +#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN) +#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN) +#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT) +#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT) +#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT) +#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT) +#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT) +#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT) +#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT) +#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT) +#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT) +#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN) +#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT) +#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT) +#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT) +#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT) +#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT) +#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT) +#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT) +#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT) +#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT) +#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT) +#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT) +#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT) +#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT) +#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT) +#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT) +#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT) +#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT) +#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT) +#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT) +#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) +#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) + +#define GPIO117_SCL (117 | GPIO_ALT_FN_1_OUT) +#define GPIO118_SDA (118 | GPIO_ALT_FN_1_OUT) + +/* + * Power Manager + */ +#ifdef CONFIG_CPU_MONAHANS + +#define ASCR 0x40F40000 /* Application Subsystem Power Status/Control Register */ +#define ARSR 0x40F40004 /* Application Subsystem Reset Status Register */ +#define AD3ER 0x40F40008 /* Application Subsystem D3 state Wakeup Enable Register */ +#define AD3SR 0x40F4000C /* Application Subsystem D3 state Wakeup Status Register */ +#define AD2D0ER 0x40F40010 /* Application Subsystem D2 to D0 state Wakeup Enable Register */ +#define AD2D0SR 0x40F40014 /* Application Subsystem D2 to D0 state Wakeup Status Register */ +#define AD2D1ER 0x40F40018 /* Application Subsystem D2 to D1 state Wakeup Enable Register */ +#define AD2D1SR 0x40F4001C /* Application Subsystem D2 to D1 state Wakeup Status Register */ +#define AD1D0ER 0x40F40020 /* Application Subsystem D1 to D0 state Wakeup Enable Register */ +#define AD1D0SR 0x40F40024 /* Application Subsystem D1 to D0 state Wakeup Status Register */ +#define ASDCNT 0x40F40028 /* Application Subsystem SRAM Drowsy Count Register */ +#define AD3R 0x40F40030 /* Application Subsystem D3 State Configuration Register */ +#define AD2R 0x40F40034 /* Application Subsystem D2 State Configuration Register */ +#define AD1R 0x40F40038 /* Application Subsystem D1 State Configuration Register */ + +#define PMCR 0x40F50000 /* Power Manager Control Register */ +#define PSR 0x40F50004 /* Power Manager S2 Status Register */ +#define PSPR 0x40F50008 /* Power Manager Scratch Pad Register */ +#define PCFR 0x40F5000C /* Power Manager General Configuration Register */ +#define PWER 0x40F50010 /* Power Manager Wake-up Enable Register */ +#define PWSR 0x40F50014 /* Power Manager Wake-up Status Register */ +#define PECR 0x40F50018 /* Power Manager EXT_WAKEUP[1:0] Control Register */ +#define DCDCSR 0x40F50080 /* DC-DC Controller Status Register */ +#define PVCR 0x40F50100 /* Power Manager Voltage Change Control Register */ +#define PCMD(x) (0x40F50110 + x*4) +#define PCMD0 (0x40F50110 + 0 * 4) +#define PCMD1 (0x40F50110 + 1 * 4) +#define PCMD2 (0x40F50110 + 2 * 4) +#define PCMD3 (0x40F50110 + 3 * 4) +#define PCMD4 (0x40F50110 + 4 * 4) +#define PCMD5 (0x40F50110 + 5 * 4) +#define PCMD6 (0x40F50110 + 6 * 4) +#define PCMD7 (0x40F50110 + 7 * 4) +#define PCMD8 (0x40F50110 + 8 * 4) +#define PCMD9 (0x40F50110 + 9 * 4) +#define PCMD10 (0x40F50110 + 10 * 4) +#define PCMD11 (0x40F50110 + 11 * 4) +#define PCMD12 (0x40F50110 + 12 * 4) +#define PCMD13 (0x40F50110 + 13 * 4) +#define PCMD14 (0x40F50110 + 14 * 4) +#define PCMD15 (0x40F50110 + 15 * 4) +#define PCMD16 (0x40F50110 + 16 * 4) +#define PCMD17 (0x40F50110 + 17 * 4) +#define PCMD18 (0x40F50110 + 18 * 4) +#define PCMD19 (0x40F50110 + 19 * 4) +#define PCMD20 (0x40F50110 + 20 * 4) +#define PCMD21 (0x40F50110 + 21 * 4) +#define PCMD22 (0x40F50110 + 22 * 4) +#define PCMD23 (0x40F50110 + 23 * 4) +#define PCMD24 (0x40F50110 + 24 * 4) +#define PCMD25 (0x40F50110 + 25 * 4) +#define PCMD26 (0x40F50110 + 26 * 4) +#define PCMD27 (0x40F50110 + 27 * 4) +#define PCMD28 (0x40F50110 + 28 * 4) +#define PCMD29 (0x40F50110 + 29 * 4) +#define PCMD30 (0x40F50110 + 30 * 4) +#define PCMD31 (0x40F50110 + 31 * 4) + +#define PCMD_MBC (1<<12) +#define PCMD_DCE (1<<11) +#define PCMD_LC (1<<10) +#define PCMD_SQC (3<<8) /* only 00 and 01 are valid */ + +#define PVCR_FVC (0x1 << 28) +#define PVCR_VCSA (0x1<<14) +#define PVCR_CommandDelay (0xf80) +#define PVCR_ReadPointer 0x01f00000 +#define PVCR_SlaveAddress (0x7f) + +#else /* ifdef CONFIG_CPU_MONAHANS */ + +#define PMCR 0x40F00000 /* Power Manager Control Register */ +#define PSSR 0x40F00004 /* Power Manager Sleep Status Register */ +#define PSPR 0x40F00008 /* Power Manager Scratch Pad Register */ +#define PWER 0x40F0000C /* Power Manager Wake-up Enable Register */ +#define PRER 0x40F00010 /* Power Manager GPIO Rising-Edge Detect Enable Register */ +#define PFER 0x40F00014 /* Power Manager GPIO Falling-Edge Detect Enable Register */ +#define PEDR 0x40F00018 /* Power Manager GPIO Edge Detect Status Register */ +#define PCFR 0x40F0001C /* Power Manager General Configuration Register */ +#define PGSR0 0x40F00020 /* Power Manager GPIO Sleep State Register for GP[31-0] */ +#define PGSR1 0x40F00024 /* Power Manager GPIO Sleep State Register for GP[63-32] */ +#define PGSR2 0x40F00028 /* Power Manager GPIO Sleep State Register for GP[84-64] */ +#define PGSR3 0x40F0002C /* Power Manager GPIO Sleep State Register for GP[118-96] */ +#define RCSR 0x40F00030 /* Reset Controller Status Register */ + +#define PSLR 0x40F00034 /* Power Manager Sleep Config Register */ +#define PSTR 0x40F00038 /* Power Manager Standby Config Register */ +#define PSNR 0x40F0003C /* Power Manager Sense Config Register */ +#define PVCR 0x40F00040 /* Power Manager VoltageControl Register */ +#define PKWR 0x40F00050 /* Power Manager KB Wake-up Enable Reg */ +#define PKSR 0x40F00054 /* Power Manager KB Level-Detect Register */ +#define PCMD(x) (0x40F00080 + x*4) +#define PCMD0 (0x40F00080 + 0 * 4) +#define PCMD1 (0x40F00080 + 1 * 4) +#define PCMD2 (0x40F00080 + 2 * 4) +#define PCMD3 (0x40F00080 + 3 * 4) +#define PCMD4 (0x40F00080 + 4 * 4) +#define PCMD5 (0x40F00080 + 5 * 4) +#define PCMD6 (0x40F00080 + 6 * 4) +#define PCMD7 (0x40F00080 + 7 * 4) +#define PCMD8 (0x40F00080 + 8 * 4) +#define PCMD9 (0x40F00080 + 9 * 4) +#define PCMD10 (0x40F00080 + 10 * 4) +#define PCMD11 (0x40F00080 + 11 * 4) +#define PCMD12 (0x40F00080 + 12 * 4) +#define PCMD13 (0x40F00080 + 13 * 4) +#define PCMD14 (0x40F00080 + 14 * 4) +#define PCMD15 (0x40F00080 + 15 * 4) +#define PCMD16 (0x40F00080 + 16 * 4) +#define PCMD17 (0x40F00080 + 17 * 4) +#define PCMD18 (0x40F00080 + 18 * 4) +#define PCMD19 (0x40F00080 + 19 * 4) +#define PCMD20 (0x40F00080 + 20 * 4) +#define PCMD21 (0x40F00080 + 21 * 4) +#define PCMD22 (0x40F00080 + 22 * 4) +#define PCMD23 (0x40F00080 + 23 * 4) +#define PCMD24 (0x40F00080 + 24 * 4) +#define PCMD25 (0x40F00080 + 25 * 4) +#define PCMD26 (0x40F00080 + 26 * 4) +#define PCMD27 (0x40F00080 + 27 * 4) +#define PCMD28 (0x40F00080 + 28 * 4) +#define PCMD29 (0x40F00080 + 29 * 4) +#define PCMD30 (0x40F00080 + 30 * 4) +#define PCMD31 (0x40F00080 + 31 * 4) + +#define PCMD_MBC (1<<12) +#define PCMD_DCE (1<<11) +#define PCMD_LC (1<<10) +/* FIXME: PCMD_SQC need be checked. */ +#define PCMD_SQC (3<<8) /* currently only bit 8 is changerable, */ + /* bit 9 should be 0 all day. */ +#define PVCR_VCSA (0x1<<14) +#define PVCR_CommandDelay (0xf80) +/* define MACRO for Power Manager General Configuration Register (PCFR) */ +#define PCFR_FVC (0x1 << 10) +#define PCFR_PI2C_EN (0x1 << 6) + +#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ +#define PSSR_RDH (1 << 5) /* Read Disable Hold */ +#define PSSR_PH (1 << 4) /* Peripheral Control Hold */ +#define PSSR_VFS (1 << 2) /* VDD Fault Status */ +#define PSSR_BFS (1 << 1) /* Battery Fault Status */ +#define PSSR_SSS (1 << 0) /* Software Sleep Status */ + +#define PCFR_DS (1 << 3) /* Deep Sleep Mode */ +#define PCFR_FS (1 << 2) /* Float Static Chip Selects */ +#define PCFR_FP (1 << 1) /* Float PCMCIA controls */ +#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ + +#define RCSR_GPR (1 << 3) /* GPIO Reset */ +#define RCSR_SMR (1 << 2) /* Sleep Mode */ +#define RCSR_WDR (1 << 1) /* Watchdog Reset */ +#define RCSR_HWR (1 << 0) /* Hardware Reset */ + +#endif /* CONFIG_CPU_MONAHANS */ + +/* + * SSP Serial Port Registers + */ +#define SSCR0 0x41000000 /* SSP Control Register 0 */ +#define SSCR1 0x41000004 /* SSP Control Register 1 */ +#define SSSR 0x41000008 /* SSP Status Register */ +#define SSITR 0x4100000C /* SSP Interrupt Test Register */ +#define SSDR 0x41000010 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */ + +/* + * MultiMediaCard (MMC) controller + */ +#define MMC_STRPCL 0x41100000 /* Control to start and stop MMC clock */ +#define MMC_STAT 0x41100004 /* MMC Status Register (read only) */ +#define MMC_CLKRT 0x41100008 /* MMC clock rate */ +#define MMC_SPI 0x4110000c /* SPI mode control bits */ +#define MMC_CMDAT 0x41100010 /* Command/response/data sequence control */ +#define MMC_RESTO 0x41100014 /* Expected response time out */ +#define MMC_RDTO 0x41100018 /* Expected data read time out */ +#define MMC_BLKLEN 0x4110001c /* Block length of data transaction */ +#define MMC_NOB 0x41100020 /* Number of blocks, for block mode */ +#define MMC_PRTBUF 0x41100024 /* Partial MMC_TXFIFO FIFO written */ +#define MMC_I_MASK 0x41100028 /* Interrupt Mask */ +#define MMC_I_REG 0x4110002c /* Interrupt Register (read only) */ +#define MMC_CMD 0x41100030 /* Index of current command */ +#define MMC_ARGH 0x41100034 /* MSW part of the current command argument */ +#define MMC_ARGL 0x41100038 /* LSW part of the current command argument */ +#define MMC_RES 0x4110003c /* Response FIFO (read only) */ +#define MMC_RXFIFO 0x41100040 /* Receive FIFO (read only) */ +#define MMC_TXFIFO 0x41100044 /* Transmit FIFO (write only) */ + + +/* + * LCD + */ +#define LCCR0 0x44000000 /* LCD Controller Control Register 0 */ +#define LCCR1 0x44000004 /* LCD Controller Control Register 1 */ +#define LCCR2 0x44000008 /* LCD Controller Control Register 2 */ +#define LCCR3 0x4400000C /* LCD Controller Control Register 3 */ +#define DFBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */ +#define DFBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */ +#define LCSR0 0x44000038 /* LCD Controller Status Register */ +#define LCSR1 0x44000034 /* LCD Controller Status Register */ +#define LIIDR 0x4400003C /* LCD Controller Interrupt ID Register */ +#define TMEDRGBR 0x44000040 /* TMED RGB Seed Register */ +#define TMEDCR 0x44000044 /* TMED Control Register */ + +#define FDADR0 0x44000200 /* DMA Channel 0 Frame Descriptor Address Register */ +#define FSADR0 0x44000204 /* DMA Channel 0 Frame Source Address Register */ +#define FIDR0 0x44000208 /* DMA Channel 0 Frame ID Register */ +#define LDCMD0 0x4400020C /* DMA Channel 0 Command Register */ +#define FDADR1 0x44000210 /* DMA Channel 1 Frame Descriptor Address Register */ +#define FSADR1 0x44000214 /* DMA Channel 1 Frame Source Address Register */ +#define FIDR1 0x44000218 /* DMA Channel 1 Frame ID Register */ +#define LDCMD1 0x4400021C /* DMA Channel 1 Command Register */ + +#define LCCR0_ENB (1 << 0) /* LCD Controller enable */ +#define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */ +#define LCCR0_SDS (1 << 2) /* Single Panel = 0, Dual Panel = 1 */ +#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ +#define LCCR0_SFM (1 << 4) /* Start of frame mask */ +#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ +#define LCCR0_EFM (1 << 6) /* End of Frame mask */ +#define LCCR0_PAS (1 << 7) /* Passive = 0, Active = 1 */ +#define LCCR0_BLE (1 << 8) /* Little Endian = 0, Big Endian = 1 */ +#define LCCR0_DPD (1 << 9) /* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */ +#define LCCR0_DIS (1 << 10) /* LCD Disable */ +#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ +#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ +#define LCCR0_PDD_S 12 +#define LCCR0_BM (1 << 20) /* Branch mask */ +#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ +#if defined(CONFIG_CPU_PXA27X) +#define LCCR0_LCDT (1 << 22) /* LCD Panel Type */ +#define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */ +#define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */ +#endif + +#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ +#define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \ + (((Pixel) - 1) << FShft (LCCR1_PPL)) + +#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ +#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ + /* pulse Width [1..64 Tpix] */ \ + (((Tpix) - 1) << FShft (LCCR1_HSW)) + +#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ + /* count - 1 [Tpix] */ +#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ + /* [1..256 Tpix] */ \ + (((Tpix) - 1) << FShft (LCCR1_ELW)) + +#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ + /* Wait count - 1 [Tpix] */ +#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ + /* [1..256 Tpix] */ \ + (((Tpix) - 1) << FShft (LCCR1_BLW)) + + +#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ +#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ + (((Line) - 1) << FShft (LCCR2_LPP)) + +#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ + /* Width - 1 [Tln] (L_FCLK) */ +#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ + /* Width [1..64 Tln] */ \ + (((Tln) - 1) << FShft (LCCR2_VSW)) + +#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ + /* count [Tln] */ +#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ + /* [0..255 Tln] */ \ + ((Tln) << FShft (LCCR2_EFW)) + +#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ + /* Wait count [Tln] */ +#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ + /* [0..255 Tln] */ \ + ((Tln) << FShft (LCCR2_BFW)) + +#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ +#define LCCR3_API_S 16 +#define LCCR3_VSP (1 << 20) /* vertical sync polarity */ +#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ +#define LCCR3_PCP (1 << 22) /* pixel clock polarity */ +#define LCCR3_OEP (1 << 23) /* output enable polarity */ +#define LCCR3_DPC (1 << 27) /* double pixel clock mode */ + +#define LCCR3_PDFOR_0 (0 << 30) +#define LCCR3_PDFOR_1 (1 << 30) +#define LCCR3_PDFOR_2 (2 << 30) +#define LCCR3_PDFOR_3 (3 << 30) + + +#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ +#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \ + (((Div) << FShft (LCCR3_PCD))) + + +#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */ +#define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \ + ((((Bpp&0x7) << FShft (LCCR3_BPP)))|(((Bpp&0x8)<<26))) + +#define LCCR3_ACB Fld (8, 8) /* AC Bias */ +#define LCCR3_Acb(Acb) /* BAC Bias */ \ + (((Acb) << FShft (LCCR3_ACB))) + +#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ + /* pulse active High */ +#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ + +#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ + /* active High */ +#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ + /* active Low */ + +#define LCSR0_LDD (1 << 0) /* LCD Disable Done */ +#define LCSR0_SOF (1 << 1) /* Start of frame */ +#define LCSR0_BER (1 << 2) /* Bus error */ +#define LCSR0_ABC (1 << 3) /* AC Bias count */ +#define LCSR0_IUL (1 << 4) /* input FIFO underrun Lower panel */ +#define LCSR0_IUU (1 << 5) /* input FIFO underrun Upper panel */ +#define LCSR0_OU (1 << 6) /* output FIFO underrun */ +#define LCSR0_QD (1 << 7) /* quick disable */ +#define LCSR0_EOF0 (1 << 8) /* end of frame */ +#define LCSR0_BS (1 << 9) /* branch status */ +#define LCSR0_SINT (1 << 10) /* subsequent interrupt */ + +#define LCSR1_SOF1 (1 << 0) +#define LCSR1_SOF2 (1 << 1) +#define LCSR1_SOF3 (1 << 2) +#define LCSR1_SOF4 (1 << 3) +#define LCSR1_SOF5 (1 << 4) +#define LCSR1_SOF6 (1 << 5) + +#define LCSR1_EOF1 (1 << 8) +#define LCSR1_EOF2 (1 << 9) +#define LCSR1_EOF3 (1 << 10) +#define LCSR1_EOF4 (1 << 11) +#define LCSR1_EOF5 (1 << 12) +#define LCSR1_EOF6 (1 << 13) + +#define LCSR1_BS1 (1 << 16) +#define LCSR1_BS2 (1 << 17) +#define LCSR1_BS3 (1 << 18) +#define LCSR1_BS4 (1 << 19) +#define LCSR1_BS5 (1 << 20) +#define LCSR1_BS6 (1 << 21) + +#define LCSR1_IU2 (1 << 25) +#define LCSR1_IU3 (1 << 26) +#define LCSR1_IU4 (1 << 27) +#define LCSR1_IU5 (1 << 28) +#define LCSR1_IU6 (1 << 29) + +#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ +#if defined(CONFIG_CPU_PXA27X) +#define LDCMD_SOFINT (1 << 22) +#define LDCMD_EOFINT (1 << 21) +#endif + +/* + * Memory controller + */ + +#ifdef CONFIG_CPU_MONAHANS + +/* PXA3xx */ + +/* Static Memory Controller Registers */ +#define MSC0 0x4A000008 /* Static Memory Control Register 0 */ +#define MSC1 0x4A00000C /* Static Memory Control Register 1 */ +#define MECR 0x4A000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ +#define SXCNFG 0x4A00001C /* Synchronous Static Memory Control Register */ +#define MCMEM0 0x4A000028 /* Card interface Common Memory Space Socket 0 Timing */ +#define MCATT0 0x4A000030 /* Card interface Attribute Space Socket 0 Timing Configuration */ +#define MCIO0 0x4A000038 /* Card interface I/O Space Socket 0 Timing Configuration */ +#define MEMCLKCFG 0x4A000068 /* SCLK speed configuration */ +#define CSADRCFG0 0x4A000080 /* Address Configuration for chip select 0 */ +#define CSADRCFG1 0x4A000084 /* Address Configuration for chip select 1 */ +#define CSADRCFG2 0x4A000088 /* Address Configuration for chip select 2 */ +#define CSADRCFG3 0x4A00008C /* Address Configuration for chip select 3 */ +#define CSADRCFG_P 0x4A000090 /* Address Configuration for pcmcia card interface */ +#define CSMSADRCFG 0x4A0000A0 /* Master Address Configuration Register */ +#define CLK_RET_DEL 0x4A0000B0 /* Delay line and mux selects for return data latching for sync. flash */ +#define ADV_RET_DEL 0x4A0000B4 /* Delay line and mux selects for return data latching for sync. flash */ + +/* Dynamic Memory Controller Registers */ +#define MDCNFG 0x48100000 /* SDRAM Configuration Register 0 */ +#define MDREFR 0x48100004 /* SDRAM Refresh Control Register */ +#define FLYCNFG 0x48100020 /* Fly-by DMA DVAL[1:0] polarities */ +#define MDMRS 0x48100040 /* MRS value to be written to SDRAM */ +#define DDR_SCAL 0x48100050 /* Software Delay Line Calibration/Configuration for external DDR memory. */ +#define DDR_HCAL 0x48100060 /* Hardware Delay Line Calibration/Configuration for external DDR memory. */ +#define DDR_WCAL 0x48100068 /* DDR Write Strobe Calibration Register */ +#define DMCIER 0x48100070 /* Dynamic MC Interrupt Enable Register. */ +#define DMCISR 0x48100078 /* Dynamic MC Interrupt Status Register. */ +#define DDR_DLS 0x48100080 /* DDR Delay Line Value Status register for external DDR memory. */ +#define EMPI 0x48100090 /* EMPI Control Register */ +#define RCOMP 0x48100100 +#define PAD_MA 0x48100110 +#define PAD_MDMSB 0x48100114 +#define PAD_MDLSB 0x48100118 +#define PAD_DMEM 0x4810011c +#define PAD_SDCLK 0x48100120 +#define PAD_SDCS 0x48100124 +#define PAD_SMEM 0x48100128 +#define PAD_SCLK 0x4810012C +#define TAI 0x48100F00 /* TAI Tavor Address Isolation Register */ + +/* Some frequently used bits */ +#define MDCNFG_DMAP 0x80000000 /* SDRAM 1GB Memory Map Enable */ +#define MDCNFG_DMCEN 0x40000000 /* Enable Dynamic Memory Controller */ +#define MDCNFG_HWFREQ 0x20000000 /* Hardware Frequency Change Calibration */ +#define MDCNFG_DTYPE 0x400 /* SDRAM Type: 1=DDR SDRAM */ + +#define MDCNFG_DTC_0 0x0 /* Timing Category of SDRAM */ +#define MDCNFG_DTC_1 0x100 +#define MDCNFG_DTC_2 0x200 +#define MDCNFG_DTC_3 0x300 + +#define MDCNFG_DRAC_12 0x0 /* Number of Row Access Bits */ +#define MDCNFG_DRAC_13 0x20 +#define MDCNFG_DRAC_14 0x40 + +#define MDCNFG_DCAC_9 0x0 /* Number of Column Acess Bits */ +#define MDCNFG_DCAC_10 0x08 +#define MDCNFG_DCAC_11 0x10 + +#define MDCNFG_DBW_16 0x4 /* SDRAM Data Bus width 16bit */ +#define MDCNFG_DCSE1 0x2 /* SDRAM CS 1 Enable */ +#define MDCNFG_DCSE0 0x1 /* SDRAM CS 0 Enable */ + + +/* Data Flash Controller Registers */ + +#define NDCR 0x43100000 /* Data Flash Control register */ +#define NDTR0CS0 0x43100004 /* Data Controller Timing Parameter 0 Register for ND_nCS0 */ +/* #define NDTR0CS1 0x43100008 /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */ +#define NDTR1CS0 0x4310000C /* Data Controller Timing Parameter 1 Register for ND_nCS0 */ +/* #define NDTR1CS1 0x43100010 /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */ +#define NDSR 0x43100014 /* Data Controller Status Register */ +#define NDPCR 0x43100018 /* Data Controller Page Count Register */ +#define NDBDR0 0x4310001C /* Data Controller Bad Block Register 0 */ +#define NDBDR1 0x43100020 /* Data Controller Bad Block Register 1 */ +#define NDDB 0x43100040 /* Data Controller Data Buffer */ +#define NDCB0 0x43100048 /* Data Controller Command Buffer0 */ +#define NDCB1 0x4310004C /* Data Controller Command Buffer1 */ +#define NDCB2 0x43100050 /* Data Controller Command Buffer2 */ + +#define NDCR_SPARE_EN (0x1<<31) +#define NDCR_ECC_EN (0x1<<30) +#define NDCR_DMA_EN (0x1<<29) +#define NDCR_ND_RUN (0x1<<28) +#define NDCR_DWIDTH_C (0x1<<27) +#define NDCR_DWIDTH_M (0x1<<26) +#define NDCR_PAGE_SZ (0x3<<24) +#define NDCR_NCSX (0x1<<23) +#define NDCR_ND_STOP (0x1<<22) +/* reserved: + * #define NDCR_ND_MODE (0x3<<21) + * #define NDCR_NAND_MODE 0x0 */ +#define NDCR_CLR_PG_CNT (0x1<<20) +#define NDCR_CLR_ECC (0x1<<19) +#define NDCR_RD_ID_CNT (0x7<<16) +#define NDCR_RA_START (0x1<<15) +#define NDCR_PG_PER_BLK (0x1<<14) +#define NDCR_ND_ARB_EN (0x1<<12) +#define NDCR_RDYM (0x1<<11) +#define NDCR_CS0_PAGEDM (0x1<<10) +#define NDCR_CS1_PAGEDM (0x1<<9) +#define NDCR_CS0_CMDDM (0x1<<8) +#define NDCR_CS1_CMDDM (0x1<<7) +#define NDCR_CS0_BBDM (0x1<<6) +#define NDCR_CS1_BBDM (0x1<<5) +#define NDCR_DBERRM (0x1<<4) +#define NDCR_SBERRM (0x1<<3) +#define NDCR_WRDREQM (0x1<<2) +#define NDCR_RDDREQM (0x1<<1) +#define NDCR_WRCMDREQM (0x1) + +#define NDSR_RDY (0x1<<11) +#define NDSR_CS0_PAGED (0x1<<10) +#define NDSR_CS1_PAGED (0x1<<9) +#define NDSR_CS0_CMDD (0x1<<8) +#define NDSR_CS1_CMDD (0x1<<7) +#define NDSR_CS0_BBD (0x1<<6) +#define NDSR_CS1_BBD (0x1<<5) +#define NDSR_DBERR (0x1<<4) +#define NDSR_SBERR (0x1<<3) +#define NDSR_WRDREQ (0x1<<2) +#define NDSR_RDDREQ (0x1<<1) +#define NDSR_WRCMDREQ (0x1) + +#define NDCB0_AUTO_RS (0x1<<25) +#define NDCB0_CSEL (0x1<<24) +#define NDCB0_CMD_TYPE (0x7<<21) +#define NDCB0_NC (0x1<<20) +#define NDCB0_DBC (0x1<<19) +#define NDCB0_ADDR_CYC (0x7<<16) +#define NDCB0_CMD2 (0xff<<8) +#define NDCB0_CMD1 (0xff) +#define MCMEM(s) MCMEM0 +#define MCATT(s) MCATT0 +#define MCIO(s) MCIO0 +#define MECR_CIT (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */ + +/* Maximum values for NAND Interface Timing Registers in DFC clock + * periods */ +#define DFC_MAX_tCH 7 +#define DFC_MAX_tCS 7 +#define DFC_MAX_tWH 7 +#define DFC_MAX_tWP 7 +#define DFC_MAX_tRH 7 +#define DFC_MAX_tRP 15 +#define DFC_MAX_tR 65535 +#define DFC_MAX_tWHR 15 +#define DFC_MAX_tAR 15 + +#define DFC_CLOCK 104 /* DFC Clock is 104 MHz */ +#define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */ + +#else /* CONFIG_CPU_MONAHANS */ + +/* PXA2xx */ + +#define MEMC_BASE 0x48000000 /* Base of Memory Controller */ +#define MDCNFG_OFFSET 0x0 +#define MDREFR_OFFSET 0x4 +#define MSC0_OFFSET 0x8 +#define MSC1_OFFSET 0xC +#define MSC2_OFFSET 0x10 +#define MECR_OFFSET 0x14 +#define SXLCR_OFFSET 0x18 +#define SXCNFG_OFFSET 0x1C +#define FLYCNFG_OFFSET 0x20 +#define SXMRS_OFFSET 0x24 +#define MCMEM0_OFFSET 0x28 +#define MCMEM1_OFFSET 0x2C +#define MCATT0_OFFSET 0x30 +#define MCATT1_OFFSET 0x34 +#define MCIO0_OFFSET 0x38 +#define MCIO1_OFFSET 0x3C +#define MDMRS_OFFSET 0x40 + +#define MDCNFG 0x48000000 /* SDRAM Configuration Register 0 */ +#define MDCNFG_DE0 0x00000001 +#define MDCNFG_DE1 0x00000002 +#define MDCNFG_DE2 0x00010000 +#define MDCNFG_DE3 0x00020000 +#define MDCNFG_DWID0 0x00000004 + +#define MDREFR 0x48000004 /* SDRAM Refresh Control Register */ +#define MSC0 0x48000008 /* Static Memory Control Register 0 */ +#define MSC1 0x4800000C /* Static Memory Control Register 1 */ +#define MSC2 0x48000010 /* Static Memory Control Register 2 */ +#define MECR 0x48000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ +#define SXLCR 0x48000018 /* LCR value to be written to SDRAM-Timing Synchronous Flash */ +#define SXCNFG 0x4800001C /* Synchronous Static Memory Control Register */ +#define FLYCNFG 0x48000020 +#define SXMRS 0x48000024 /* MRS value to be written to Synchronous Flash or SMROM */ +#define MCMEM0 0x48000028 /* Card interface Common Memory Space Socket 0 Timing */ +#define MCMEM1 0x4800002C /* Card interface Common Memory Space Socket 1 Timing */ +#define MCATT0 0x48000030 /* Card interface Attribute Space Socket 0 Timing Configuration */ +#define MCATT1 0x48000034 /* Card interface Attribute Space Socket 1 Timing Configuration */ +#define MCIO0 0x48000038 /* Card interface I/O Space Socket 0 Timing Configuration */ +#define MCIO1 0x4800003C /* Card interface I/O Space Socket 1 Timing Configuration */ +#define MDMRS 0x48000040 /* MRS value to be written to SDRAM */ +#define BOOT_DEF 0x48000044 /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ + +#define MDREFR_ALTREFA (1 << 31) /* Exiting Alternate Bus Master Mode Refresh Control */ +#define MDREFR_ALTREFB (1 << 30) /* Entering Alternate Bus Master Mode Refresh Control */ +#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ +#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ +#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ +#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ +#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ +#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ +#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ +#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ +#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ +#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ +#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ +#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ +#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ +#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ + +#if defined(CONFIG_CPU_PXA27X) + +#define ARB_CNTRL 0x48000048 /* Arbiter Control Register */ + +#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ +#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ +#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ +#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ +#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ +#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ +#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ +#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ +#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ + +#endif /* CONFIG_CPU_PXA27X */ + +/* LCD registers */ +#define LCCR4 0x44000010 /* LCD Controller Control Register 4 */ +#define LCCR5 0x44000014 /* LCD Controller Control Register 5 */ +#define FBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */ +#define FBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */ +#define FBR2 0x44000028 /* DMA Channel 2 Frame Branch Register */ +#define FBR3 0x4400002C /* DMA Channel 3 Frame Branch Register */ +#define FBR4 0x44000030 /* DMA Channel 4 Frame Branch Register */ +#define FDADR2 0x44000220 /* DMA Channel 2 Frame Descriptor Address Register */ +#define FSADR2 0x44000224 /* DMA Channel 2 Frame Source Address Register */ +#define FIDR2 0x44000228 /* DMA Channel 2 Frame ID Register */ +#define LDCMD2 0x4400022C /* DMA Channel 2 Command Register */ +#define FDADR3 0x44000230 /* DMA Channel 3 Frame Descriptor Address Register */ +#define FSADR3 0x44000234 /* DMA Channel 3 Frame Source Address Register */ +#define FIDR3 0x44000238 /* DMA Channel 3 Frame ID Register */ +#define LDCMD3 0x4400023C /* DMA Channel 3 Command Register */ +#define FDADR4 0x44000240 /* DMA Channel 4 Frame Descriptor Address Register */ +#define FSADR4 0x44000244 /* DMA Channel 4 Frame Source Address Register */ +#define FIDR4 0x44000248 /* DMA Channel 4 Frame ID Register */ +#define LDCMD4 0x4400024C /* DMA Channel 4 Command Register */ +#define FDADR5 0x44000250 /* DMA Channel 5 Frame Descriptor Address Register */ +#define FSADR5 0x44000254 /* DMA Channel 5 Frame Source Address Register */ +#define FIDR5 0x44000258 /* DMA Channel 5 Frame ID Register */ +#define LDCMD5 0x4400025C /* DMA Channel 5 Command Register */ + +#define OVL1C1 0x44000050 /* Overlay 1 Control Register 1 */ +#define OVL1C2 0x44000060 /* Overlay 1 Control Register 2 */ +#define OVL2C1 0x44000070 /* Overlay 2 Control Register 1 */ +#define OVL2C2 0x44000080 /* Overlay 2 Control Register 2 */ +#define CCR 0x44000090 /* Cursor Control Register */ + +#define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */ +#define FBR6 0x44000114 /* DMA Channel 6 Frame Branch Register */ + +#define LCCR0_LDDALT (1<<26) /* LDD Alternate mapping bit when base pixel is RGBT16 */ +#define LCCR0_OUC (1<<25) /* Overlay Underlay Control Bit */ + +#define LCCR5_SOFM1 (1<<0) /* Start Of Frame Mask for Overlay 1 (channel 1) */ +#define LCCR5_SOFM2 (1<<1) /* Start Of Frame Mask for Overlay 2 (channel 2) */ +#define LCCR5_SOFM3 (1<<2) /* Start Of Frame Mask for Overlay 2 (channel 3) */ +#define LCCR5_SOFM4 (1<<3) /* Start Of Frame Mask for Overlay 2 (channel 4) */ +#define LCCR5_SOFM5 (1<<4) /* Start Of Frame Mask for cursor (channel 5) */ +#define LCCR5_SOFM6 (1<<5) /* Start Of Frame Mask for command data (channel 6) */ + +#define LCCR5_EOFM1 (1<<8) /* End Of Frame Mask for Overlay 1 (channel 1) */ +#define LCCR5_EOFM2 (1<<9) /* End Of Frame Mask for Overlay 2 (channel 2) */ +#define LCCR5_EOFM3 (1<<10) /* End Of Frame Mask for Overlay 2 (channel 3) */ +#define LCCR5_EOFM4 (1<<11) /* End Of Frame Mask for Overlay 2 (channel 4) */ +#define LCCR5_EOFM5 (1<<12) /* End Of Frame Mask for cursor (channel 5) */ +#define LCCR5_EOFM6 (1<<13) /* End Of Frame Mask for command data (channel 6) */ + +#define LCCR5_BSM1 (1<<16) /* Branch mask for Overlay 1 (channel 1) */ +#define LCCR5_BSM2 (1<<17) /* Branch mask for Overlay 2 (channel 2) */ +#define LCCR5_BSM3 (1<<18) /* Branch mask for Overlay 2 (channel 3) */ +#define LCCR5_BSM4 (1<<19) /* Branch mask for Overlay 2 (channel 4) */ +#define LCCR5_BSM5 (1<<20) /* Branch mask for cursor (channel 5) */ +#define LCCR5_BSM6 (1<<21) /* Branch mask for data command (channel 6) */ + +#define LCCR5_IUM1 (1<<24) /* Input FIFO Underrun Mask for Overlay 1 */ +#define LCCR5_IUM2 (1<<25) /* Input FIFO Underrun Mask for Overlay 2 */ +#define LCCR5_IUM3 (1<<26) /* Input FIFO Underrun Mask for Overlay 2 */ +#define LCCR5_IUM4 (1<<27) /* Input FIFO Underrun Mask for Overlay 2 */ +#define LCCR5_IUM5 (1<<28) /* Input FIFO Underrun Mask for cursor */ +#define LCCR5_IUM6 (1<<29) /* Input FIFO Underrun Mask for data command */ + +#define OVL1C1_O1EN (1<<31) /* Enable bit for Overlay 1 */ +#define OVL2C1_O2EN (1<<31) /* Enable bit for Overlay 2 */ +#define CCR_CEN (1<<31) /* Enable bit for Cursor */ + +/* Keypad controller */ + +#define KPC 0x41500000 /* Keypad Interface Control register */ +#define KPDK 0x41500008 /* Keypad Interface Direct Key register */ +#define KPREC 0x41500010 /* Keypad Intefcace Rotary Encoder register */ +#define KPMK 0x41500018 /* Keypad Intefcace Matrix Key register */ +#define KPAS 0x41500020 /* Keypad Interface Automatic Scan register */ +#define KPASMKP0 0x41500028 /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */ +#define KPASMKP1 0x41500030 /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */ +#define KPASMKP2 0x41500038 /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */ +#define KPASMKP3 0x41500040 /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */ +#define KPKDI 0x41500048 /* Keypad Interface Key Debounce Interval register */ + +#define KPC_AS (0x1 << 30) /* Automatic Scan bit */ +#define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */ +#define KPC_MI (0x1 << 22) /* Matrix interrupt bit */ +#define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */ +#define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */ +#define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */ +#define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */ +#define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */ +#define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */ +#define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */ +#define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */ +#define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */ +#define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */ +#define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */ +#define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Key Debounce select */ +#define KPC_DI (0x1 << 5) /* Direct key interrupt bit */ +#define KPC_DEE0 (0x1 << 2) /* Rotary Encoder 0 Enable */ +#define KPC_DE (0x1 << 1) /* Direct Keypad Enable */ +#define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */ + +#define KPDK_DKP (0x1 << 31) +#define KPDK_DK7 (0x1 << 7) +#define KPDK_DK6 (0x1 << 6) +#define KPDK_DK5 (0x1 << 5) +#define KPDK_DK4 (0x1 << 4) +#define KPDK_DK3 (0x1 << 3) +#define KPDK_DK2 (0x1 << 2) +#define KPDK_DK1 (0x1 << 1) +#define KPDK_DK0 (0x1 << 0) + +#define KPREC_OF1 (0x1 << 31) +#define kPREC_UF1 (0x1 << 30) +#define KPREC_OF0 (0x1 << 15) +#define KPREC_UF0 (0x1 << 14) + +#define KPMK_MKP (0x1 << 31) +#define KPAS_SO (0x1 << 31) +#define KPASMKPx_SO (0x1 << 31) + +#define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */ +#define PSLR 0x40F00034 +#define PSTR 0x40F00038 /* Power Manager Standby Configuration Reg */ +#define PSNR 0x40F0003C /* Power Manager Sense Configuration Reg */ +#define PVCR 0x40F00040 /* Power Manager Voltage Change Control Reg */ +#define PKWR 0x40F00050 /* Power Manager KB Wake-Up Enable Reg */ +#define PKSR 0x40F00054 /* Power Manager KB Level-Detect Status Reg */ +#define OSMR4 0x40A00080 /* */ +#define OSCR4 0x40A00040 /* OS Timer Counter Register */ +#define OMCR4 0x40A000C0 /* */ + +#endif /* CONFIG_CPU_PXA27X */ + +#endif /* _PXA_REGS_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-pxa/pxa.h b/roms/u-boot/arch/arm/include/asm/arch-pxa/pxa.h new file mode 100644 index 000000000..428a848e1 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-pxa/pxa.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * PXA common functions + * + * Copyright (C) 2011 Marek Vasut + */ + +#ifndef __PXA_H__ +#define __PXA_H__ + +#define PXA255_A0 0x00000106 +#define PXA250_C0 0x00000105 +#define PXA250_B2 0x00000104 +#define PXA250_B1 0x00000103 +#define PXA250_B0 0x00000102 +#define PXA250_A1 0x00000101 +#define PXA250_A0 0x00000100 +#define PXA210_C0 0x00000125 +#define PXA210_B2 0x00000124 +#define PXA210_B1 0x00000123 +#define PXA210_B0 0x00000122 + +int cpu_is_pxa25x(void); +int cpu_is_pxa27x(void); +uint32_t pxa_get_cpu_revision(void); +void pxa2xx_dram_init(void); + +#endif /* __PXA_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-mmc.h b/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-mmc.h new file mode 100644 index 000000000..6d9a736d9 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-mmc.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 Marek Vasut + */ + +#ifndef __REGS_MMC_H__ +#define __REGS_MMC_H__ + +#define MMC0_BASE 0x41100000 +#define MMC1_BASE 0x42000000 + +int pxa_mmc_register(int card_index); + +struct pxa_mmc_regs { + uint32_t strpcl; + uint32_t stat; + uint32_t clkrt; + uint32_t spi; + uint32_t cmdat; + uint32_t resto; + uint32_t rdto; + uint32_t blklen; + uint32_t nob; + uint32_t prtbuf; + uint32_t i_mask; + uint32_t i_reg; + uint32_t cmd; + uint32_t argh; + uint32_t argl; + uint32_t res; + uint32_t rxfifo; + uint32_t txfifo; +}; + +/* MMC_STRPCL */ +#define MMC_STRPCL_STOP_CLK (1 << 0) +#define MMC_STRPCL_START_CLK (1 << 1) + +/* MMC_STAT */ +#define MMC_STAT_END_CMD_RES (1 << 13) +#define MMC_STAT_PRG_DONE (1 << 12) +#define MMC_STAT_DATA_TRAN_DONE (1 << 11) +#define MMC_STAT_CLK_EN (1 << 8) +#define MMC_STAT_RECV_FIFO_FULL (1 << 7) +#define MMC_STAT_XMIT_FIFO_EMPTY (1 << 6) +#define MMC_STAT_RES_CRC_ERROR (1 << 5) +#define MMC_STAT_SPI_READ_ERROR_TOKEN (1 << 4) +#define MMC_STAT_CRC_READ_ERROR (1 << 3) +#define MMC_STAT_CRC_WRITE_ERROR (1 << 2) +#define MMC_STAT_TIME_OUT_RESPONSE (1 << 1) +#define MMC_STAT_READ_TIME_OUT (1 << 0) + +/* MMC_CLKRT */ +#define MMC_CLKRT_20MHZ 0 +#define MMC_CLKRT_10MHZ 1 +#define MMC_CLKRT_5MHZ 2 +#define MMC_CLKRT_2_5MHZ 3 +#define MMC_CLKRT_1_25MHZ 4 +#define MMC_CLKRT_0_625MHZ 5 +#define MMC_CLKRT_0_3125MHZ 6 + +/* MMC_SPI */ +#define MMC_SPI_EN (1 << 0) +#define MMC_SPI_CS_EN (1 << 2) +#define MMC_SPI_CS_ADDRESS (1 << 3) +#define MMC_SPI_CRC_ON (1 << 1) + +/* MMC_CMDAT */ +#define MMC_CMDAT_SD_4DAT (1 << 8) +#define MMC_CMDAT_MMC_DMA_EN (1 << 7) +#define MMC_CMDAT_INIT (1 << 6) +#define MMC_CMDAT_BUSY (1 << 5) +#define MMC_CMDAT_BCR (MMC_CMDAT_BUSY | MMC_CMDAT_INIT) +#define MMC_CMDAT_STREAM (1 << 4) +#define MMC_CMDAT_WRITE (1 << 3) +#define MMC_CMDAT_DATA_EN (1 << 2) +#define MMC_CMDAT_R0 0 +#define MMC_CMDAT_R1 1 +#define MMC_CMDAT_R2 2 +#define MMC_CMDAT_R3 3 + +/* MMC_RESTO */ +#define MMC_RES_TO_MAX_MASK 0x7f + +/* MMC_RDTO */ +#define MMC_READ_TO_MAX_MASK 0xffff + +/* MMC_BLKLEN */ +#define MMC_BLK_LEN_MAX_MASK 0x3ff + +/* MMC_PRTBUF */ +#define MMC_PRTBUF_BUF_PART_FULL (1 << 0) + +/* MMC_I_MASK */ +#define MMC_I_MASK_TXFIFO_WR_REQ (1 << 6) +#define MMC_I_MASK_RXFIFO_RD_REQ (1 << 5) +#define MMC_I_MASK_CLK_IS_OFF (1 << 4) +#define MMC_I_MASK_STOP_CMD (1 << 3) +#define MMC_I_MASK_END_CMD_RES (1 << 2) +#define MMC_I_MASK_PRG_DONE (1 << 1) +#define MMC_I_MASK_DATA_TRAN_DONE (1 << 0) +#define MMC_I_MASK_ALL 0x7f + + +/* MMC_I_REG */ +#define MMC_I_REG_TXFIFO_WR_REQ (1 << 6) +#define MMC_I_REG_RXFIFO_RD_REQ (1 << 5) +#define MMC_I_REG_CLK_IS_OFF (1 << 4) +#define MMC_I_REG_STOP_CMD (1 << 3) +#define MMC_I_REG_END_CMD_RES (1 << 2) +#define MMC_I_REG_PRG_DONE (1 << 1) +#define MMC_I_REG_DATA_TRAN_DONE (1 << 0) + +/* MMC_CMD */ +#define MMC_CMD_INDEX_MAX 0x6f + +#define MMC_R1_IDLE_STATE 0x01 +#define MMC_R1_ERASE_STATE 0x02 +#define MMC_R1_ILLEGAL_CMD 0x04 +#define MMC_R1_COM_CRC_ERR 0x08 +#define MMC_R1_ERASE_SEQ_ERR 0x01 +#define MMC_R1_ADDR_ERR 0x02 +#define MMC_R1_PARAM_ERR 0x04 + +#define MMC_R1B_WP_ERASE_SKIP 0x0002 +#define MMC_R1B_ERR 0x0004 +#define MMC_R1B_CC_ERR 0x0008 +#define MMC_R1B_CARD_ECC_ERR 0x0010 +#define MMC_R1B_WP_VIOLATION 0x0020 +#define MMC_R1B_ERASE_PARAM 0x0040 +#define MMC_R1B_OOR 0x0080 +#define MMC_R1B_IDLE_STATE 0x0100 +#define MMC_R1B_ERASE_RESET 0x0200 +#define MMC_R1B_ILLEGAL_CMD 0x0400 +#define MMC_R1B_COM_CRC_ERR 0x0800 +#define MMC_R1B_ERASE_SEQ_ERR 0x1000 +#define MMC_R1B_ADDR_ERR 0x2000 +#define MMC_R1B_PARAM_ERR 0x4000 + +#endif /* __REGS_MMC_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-uart.h b/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-uart.h new file mode 100644 index 000000000..bdd0a4757 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-uart.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 Marek Vasut + */ + +#ifndef __REGS_UART_H__ +#define __REGS_UART_H__ + +#define FFUART_BASE 0x40100000 +#define BTUART_BASE 0x40200000 +#define STUART_BASE 0x40700000 +#define HWUART_BASE 0x41600000 + +struct pxa_uart_regs { + union { + uint32_t thr; + uint32_t rbr; + uint32_t dll; + }; + union { + uint32_t ier; + uint32_t dlh; + }; + union { + uint32_t fcr; + uint32_t iir; + }; + uint32_t lcr; + uint32_t mcr; + uint32_t lsr; + uint32_t msr; + uint32_t spr; + uint32_t isr; +}; + +#define IER_DMAE (1 << 7) +#define IER_UUE (1 << 6) +#define IER_NRZE (1 << 5) +#define IER_RTIOE (1 << 4) +#define IER_MIE (1 << 3) +#define IER_RLSE (1 << 2) +#define IER_TIE (1 << 1) +#define IER_RAVIE (1 << 0) + +#define IIR_FIFOES1 (1 << 7) +#define IIR_FIFOES0 (1 << 6) +#define IIR_TOD (1 << 3) +#define IIR_IID2 (1 << 2) +#define IIR_IID1 (1 << 1) +#define IIR_IP (1 << 0) + +#define FCR_ITL2 (1 << 7) +#define FCR_ITL1 (1 << 6) +#define FCR_RESETTF (1 << 2) +#define FCR_RESETRF (1 << 1) +#define FCR_TRFIFOE (1 << 0) +#define FCR_ITL_1 0 +#define FCR_ITL_8 (FCR_ITL1) +#define FCR_ITL_16 (FCR_ITL2) +#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) + +#define LCR_DLAB (1 << 7) +#define LCR_SB (1 << 6) +#define LCR_STKYP (1 << 5) +#define LCR_EPS (1 << 4) +#define LCR_PEN (1 << 3) +#define LCR_STB (1 << 2) +#define LCR_WLS1 (1 << 1) +#define LCR_WLS0 (1 << 0) + +#define LSR_FIFOE (1 << 7) +#define LSR_TEMT (1 << 6) +#define LSR_TDRQ (1 << 5) +#define LSR_BI (1 << 4) +#define LSR_FE (1 << 3) +#define LSR_PE (1 << 2) +#define LSR_OE (1 << 1) +#define LSR_DR (1 << 0) + +#define MCR_LOOP (1 << 4) +#define MCR_OUT2 (1 << 3) +#define MCR_OUT1 (1 << 2) +#define MCR_RTS (1 << 1) +#define MCR_DTR (1 << 0) + +#define MSR_DCD (1 << 7) +#define MSR_RI (1 << 6) +#define MSR_DSR (1 << 5) +#define MSR_CTS (1 << 4) +#define MSR_DDCD (1 << 3) +#define MSR_TERI (1 << 2) +#define MSR_DDSR (1 << 1) +#define MSR_DCTS (1 << 0) + +#endif /* __REGS_UART_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-usb.h b/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-usb.h new file mode 100644 index 000000000..e46887c9e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-usb.h @@ -0,0 +1,146 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * PXA25x UDC definitions + * + * Copyright (C) 2012 Łukasz Dałek + */ + +#ifndef __REGS_USB_H__ +#define __REGS_USB_H__ + +struct pxa25x_udc_regs { + /* UDC Control Register */ + uint32_t udccr; /* 0x000 */ + uint32_t reserved1; + + /* UDC Control Function Register */ + uint32_t udccfr; /* 0x008 */ + uint32_t reserved2; + + /* UDC Endpoint Control/Status Registers */ + uint32_t udccs[16]; /* 0x010 - 0x04c */ + + /* UDC Interrupt Control/Status Registers */ + uint32_t uicr0; /* 0x050 */ + uint32_t uicr1; /* 0x054 */ + uint32_t usir0; /* 0x058 */ + uint32_t usir1; /* 0x05c */ + + /* UDC Frame Number/Byte Count Registers */ + uint32_t ufnrh; /* 0x060 */ + uint32_t ufnrl; /* 0x064 */ + uint32_t ubcr2; /* 0x068 */ + uint32_t ubcr4; /* 0x06c */ + uint32_t ubcr7; /* 0x070 */ + uint32_t ubcr9; /* 0x074 */ + uint32_t ubcr12; /* 0x078 */ + uint32_t ubcr14; /* 0x07c */ + + /* UDC Endpoint Data Registers */ + uint32_t uddr0; /* 0x080 */ + uint32_t reserved3[7]; + uint32_t uddr5; /* 0x0a0 */ + uint32_t reserved4[7]; + uint32_t uddr10; /* 0x0c0 */ + uint32_t reserved5[7]; + uint32_t uddr15; /* 0x0e0 */ + uint32_t reserved6[7]; + uint32_t uddr1; /* 0x100 */ + uint32_t reserved7[31]; + uint32_t uddr2; /* 0x180 */ + uint32_t reserved8[31]; + uint32_t uddr3; /* 0x200 */ + uint32_t reserved9[127]; + uint32_t uddr4; /* 0x400 */ + uint32_t reserved10[127]; + uint32_t uddr6; /* 0x600 */ + uint32_t reserved11[31]; + uint32_t uddr7; /* 0x680 */ + uint32_t reserved12[31]; + uint32_t uddr8; /* 0x700 */ + uint32_t reserved13[127]; + uint32_t uddr9; /* 0x900 */ + uint32_t reserved14[127]; + uint32_t uddr11; /* 0xb00 */ + uint32_t reserved15[31]; + uint32_t uddr12; /* 0xb80 */ + uint32_t reserved16[31]; + uint32_t uddr13; /* 0xc00 */ + uint32_t reserved17[127]; + uint32_t uddr14; /* 0xe00 */ + +}; + +#define PXA25X_UDC_BASE 0x40600000 + +#define UDCCR_UDE (1 << 0) +#define UDCCR_UDA (1 << 1) +#define UDCCR_RSM (1 << 2) +#define UDCCR_RESIR (1 << 3) +#define UDCCR_SUSIR (1 << 4) +#define UDCCR_SRM (1 << 5) +#define UDCCR_RSTIR (1 << 6) +#define UDCCR_REM (1 << 7) + +/* Bulk IN endpoint 1/6/11 */ +#define UDCCS_BI_TSP (1 << 7) +#define UDCCS_BI_FST (1 << 5) +#define UDCCS_BI_SST (1 << 4) +#define UDCCS_BI_TUR (1 << 3) +#define UDCCS_BI_FTF (1 << 2) +#define UDCCS_BI_TPC (1 << 1) +#define UDCCS_BI_TFS (1 << 0) + +/* Bulk OUT endpoint 2/7/12 */ +#define UDCCS_BO_RSP (1 << 7) +#define UDCCS_BO_RNE (1 << 6) +#define UDCCS_BO_FST (1 << 5) +#define UDCCS_BO_SST (1 << 4) +#define UDCCS_BO_DME (1 << 3) +#define UDCCS_BO_RPC (1 << 1) +#define UDCCS_BO_RFS (1 << 0) + +/* Isochronous OUT endpoint 4/9/14 */ +#define UDCCS_IO_RSP (1 << 7) +#define UDCCS_IO_RNE (1 << 6) +#define UDCCS_IO_DME (1 << 3) +#define UDCCS_IO_ROF (1 << 2) +#define UDCCS_IO_RPC (1 << 1) +#define UDCCS_IO_RFS (1 << 0) + +/* Control endpoint 0 */ +#define UDCCS0_OPR (1 << 0) +#define UDCCS0_IPR (1 << 1) +#define UDCCS0_FTF (1 << 2) +#define UDCCS0_DRWF (1 << 3) +#define UDCCS0_SST (1 << 4) +#define UDCCS0_FST (1 << 5) +#define UDCCS0_RNE (1 << 6) +#define UDCCS0_SA (1 << 7) + +#define UICR0_IM0 (1 << 0) + +#define USIR0_IR0 (1 << 0) +#define USIR0_IR1 (1 << 1) +#define USIR0_IR2 (1 << 2) +#define USIR0_IR3 (1 << 3) +#define USIR0_IR4 (1 << 4) +#define USIR0_IR5 (1 << 5) +#define USIR0_IR6 (1 << 6) +#define USIR0_IR7 (1 << 7) + +#define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */ +#define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */ +/* + * Intel(R) PXA255 Processor Specification, September 2003 (page 31) + * define new "must be one" bits in UDCCFR (see Table 12-13.) + */ +#define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN | UDCCFR_ACM)) + +#define UFNRH_SIR (1 << 7) /* SOF interrupt request */ +#define UFNRH_SIM (1 << 6) /* SOF interrupt mask */ +#define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */ +#define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */ +#define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */ + +#endif /* __REGS_USB_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk3036/boot0.h b/roms/u-boot/arch/arm/include/asm/arch-rk3036/boot0.h new file mode 100644 index 000000000..2e78b074a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk3036/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk3036/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-rk3036/gpio.h new file mode 100644 index 000000000..eca79d515 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk3036/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk3128/boot0.h b/roms/u-boot/arch/arm/include/asm/arch-rk3128/boot0.h new file mode 100644 index 000000000..2e78b074a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk3128/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk3128/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-rk3128/gpio.h new file mode 100644 index 000000000..eca79d515 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk3128/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk3188/boot0.h b/roms/u-boot/arch/arm/include/asm/arch-rk3188/boot0.h new file mode 100644 index 000000000..2e78b074a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk3188/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk3188/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-rk3188/gpio.h new file mode 100644 index 000000000..eca79d515 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk3188/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk322x/boot0.h b/roms/u-boot/arch/arm/include/asm/arch-rk322x/boot0.h new file mode 100644 index 000000000..2e78b074a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk322x/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk322x/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-rk322x/gpio.h new file mode 100644 index 000000000..eca79d515 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk322x/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk3288/boot0.h b/roms/u-boot/arch/arm/include/asm/arch-rk3288/boot0.h new file mode 100644 index 000000000..2e78b074a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk3288/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk3288/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-rk3288/gpio.h new file mode 100644 index 000000000..eca79d515 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk3288/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk3308/boot0.h b/roms/u-boot/arch/arm/include/asm/arch-rk3308/boot0.h new file mode 100644 index 000000000..2e78b074a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk3308/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk3308/cru_rk3308.h b/roms/u-boot/arch/arm/include/asm/arch-rk3308/cru_rk3308.h new file mode 100644 index 000000000..86c906bb0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk3308/cru_rk3308.h @@ -0,0 +1,288 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd. + */ +#ifndef _ASM_ARCH_CRU_RK3308_H +#define _ASM_ARCH_CRU_RK3308_H + +#define MHz 1000000 +#define OSC_HZ (24 * MHz) + +#define APLL_HZ (816 * MHz) + +#define CORE_ACLK_HZ 408000000 +#define CORE_DBG_HZ 204000000 + +#define BUS_ACLK_HZ 200000000 +#define BUS_HCLK_HZ 100000000 +#define BUS_PCLK_HZ 100000000 + +#define PERI_ACLK_HZ 200000000 +#define PERI_HCLK_HZ 100000000 +#define PERI_PCLK_HZ 100000000 + +#define AUDIO_HCLK_HZ 100000000 +#define AUDIO_PCLK_HZ 100000000 + +#define RK3308_PLL_CON(x) ((x) * 0x4) +#define RK3308_MODE_CON 0xa0 + +/* RK3308 pll id */ +enum rk3308_pll_id { + APLL, + DPLL, + VPLL0, + VPLL1, + PLL_COUNT, +}; + +struct rk3308_clk_info { + unsigned long id; + char *name; +}; + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk3308_clk_priv { + struct rk3308_cru *cru; + ulong armclk_hz; + ulong dpll_hz; + ulong vpll0_hz; + ulong vpll1_hz; +}; + +struct rk3308_cru { + struct rk3308_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + unsigned int con4; + unsigned int reserved0[3]; + } pll[4]; + unsigned int reserved1[8]; + unsigned int mode; + unsigned int misc; + unsigned int reserved2[2]; + unsigned int glb_cnt_th; + unsigned int glb_rst_st; + unsigned int glb_srst_fst; + unsigned int glb_srst_snd; + unsigned int glb_rst_con; + unsigned int pll_lock; + unsigned int reserved3[6]; + unsigned int hwffc_con0; + unsigned int reserved4; + unsigned int hwffc_th; + unsigned int hwffc_intst; + unsigned int apll_con0_s; + unsigned int apll_con1_s; + unsigned int clksel_con0_s; + unsigned int reserved5; + unsigned int clksel_con[74]; + unsigned int reserved6[54]; + unsigned int clkgate_con[15]; + unsigned int reserved7[(0x380 - 0x338) / 4 - 1]; + unsigned int ssgtbl[32]; + unsigned int softrst_con[10]; + unsigned int reserved8[(0x480 - 0x424) / 4 - 1]; + unsigned int sdmmc_con[2]; + unsigned int sdio_con[2]; + unsigned int emmc_con[2]; +}; + +enum { + /* PLLCON0*/ + PLL_BP_SHIFT = 15, + PLL_POSTDIV1_SHIFT = 12, + PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, + PLL_FBDIV_SHIFT = 0, + PLL_FBDIV_MASK = 0xfff, + + /* PLLCON1 */ + PLL_PDSEL_SHIFT = 15, + PLL_PD1_SHIFT = 14, + PLL_PD_SHIFT = 13, + PLL_PD_MASK = 1 << PLL_PD_SHIFT, + PLL_DSMPD_SHIFT = 12, + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, + PLL_LOCK_STATUS_SHIFT = 10, + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, + PLL_POSTDIV2_SHIFT = 6, + PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, + PLL_REFDIV_SHIFT = 0, + PLL_REFDIV_MASK = 0x3f, + + /* PLLCON2 */ + PLL_FOUT4PHASEPD_SHIFT = 27, + PLL_FOUTVCOPD_SHIFT = 26, + PLL_FOUTPOSTDIVPD_SHIFT = 25, + PLL_DACPD_SHIFT = 24, + PLL_FRAC_DIV = 0xffffff, + + /* CRU_MODE */ + PLLMUX_FROM_XIN24M = 0, + PLLMUX_FROM_PLL, + PLLMUX_FROM_RTC32K, + USBPHY480M_MODE_SHIFT = 8, + USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT, + VPLL1_MODE_SHIFT = 6, + VPLL1_MODE_MASK = 3 << VPLL1_MODE_SHIFT, + VPLL0_MODE_SHIFT = 4, + VPLL0_MODE_MASK = 3 << VPLL0_MODE_SHIFT, + DPLL_MODE_SHIFT = 2, + DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, + APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 3 << APLL_MODE_SHIFT, + + /* CRU_CLK_SEL0_CON */ + CORE_ACLK_DIV_SHIFT = 12, + CORE_ACLK_DIV_MASK = 0x7 << CORE_ACLK_DIV_SHIFT, + CORE_DBG_DIV_SHIFT = 8, + CORE_DBG_DIV_MASK = 0xf << CORE_DBG_DIV_SHIFT, + CORE_CLK_PLL_SEL_SHIFT = 6, + CORE_CLK_PLL_SEL_MASK = 0x3 << CORE_CLK_PLL_SEL_SHIFT, + CORE_CLK_PLL_SEL_APLL = 0, + CORE_CLK_PLL_SEL_VPLL0, + CORE_CLK_PLL_SEL_VPLL1, + CORE_DIV_CON_SHIFT = 0, + CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, + + /* CRU_CLK_SEL5_CON */ + BUS_PLL_SEL_SHIFT = 6, + BUS_PLL_SEL_MASK = 0x3 << BUS_PLL_SEL_SHIFT, + BUS_PLL_SEL_DPLL = 0, + BUS_PLL_SEL_VPLL0, + BUS_PLL_SEL_VPLL1, + BUS_ACLK_DIV_SHIFT = 0, + BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, + + /* CRU_CLK_SEL6_CON */ + BUS_PCLK_DIV_SHIFT = 8, + BUS_PCLK_DIV_MASK = 0x1f << BUS_PCLK_DIV_SHIFT, + BUS_HCLK_DIV_SHIFT = 0, + BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT, + + /* CRU_CLK_SEL7_CON */ + CRYPTO_APK_SEL_SHIFT = 14, + CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT, + CRYPTO_PLL_SEL_DPLL = 0, + CRYPTO_PLL_SEL_VPLL0, + CRYPTO_PLL_SEL_VPLL1 = 0, + CRYPTO_APK_DIV_SHIFT = 8, + CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT, + CRYPTO_PLL_SEL_SHIFT = 6, + CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT, + CRYPTO_DIV_SHIFT = 0, + CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT, + + /* CRU_CLK_SEL8_CON */ + DCLK_VOP_SEL_SHIFT = 14, + DCLK_VOP_SEL_MASK = 0x3 << DCLK_VOP_SEL_SHIFT, + DCLK_VOP_SEL_DIVOUT = 0, + DCLK_VOP_SEL_FRACOUT, + DCLK_VOP_SEL_24M, + DCLK_VOP_PLL_SEL_SHIFT = 10, + DCLK_VOP_PLL_SEL_MASK = 0x3 << DCLK_VOP_PLL_SEL_SHIFT, + DCLK_VOP_PLL_SEL_DPLL = 0, + DCLK_VOP_PLL_SEL_VPLL0, + DCLK_VOP_PLL_SEL_VPLL1, + DCLK_VOP_DIV_SHIFT = 0, + DCLK_VOP_DIV_MASK = 0xff, + + /* CRU_CLK_SEL25_CON */ + /* CRU_CLK_SEL26_CON */ + /* CRU_CLK_SEL27_CON */ + /* CRU_CLK_SEL28_CON */ + CLK_I2C_PLL_SEL_SHIFT = 14, + CLK_I2C_PLL_SEL_MASK = 0x3 << CLK_I2C_PLL_SEL_SHIFT, + CLK_I2C_PLL_SEL_DPLL = 0, + CLK_I2C_PLL_SEL_VPLL0, + CLK_I2C_PLL_SEL_24M, + CLK_I2C_DIV_CON_SHIFT = 0, + CLK_I2C_DIV_CON_MASK = 0x7f << CLK_I2C_DIV_CON_SHIFT, + + /* CRU_CLK_SEL29_CON */ + CLK_PWM_PLL_SEL_SHIFT = 14, + CLK_PWM_PLL_SEL_MASK = 0x3 << CLK_PWM_PLL_SEL_SHIFT, + CLK_PWM_PLL_SEL_DPLL = 0, + CLK_PWM_PLL_SEL_VPLL0, + CLK_PWM_PLL_SEL_24M, + CLK_PWM_DIV_CON_SHIFT = 0, + CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT, + + /* CRU_CLK_SEL30_CON */ + /* CRU_CLK_SEL31_CON */ + /* CRU_CLK_SEL32_CON */ + CLK_SPI_PLL_SEL_SHIFT = 14, + CLK_SPI_PLL_SEL_MASK = 0x3 << CLK_SPI_PLL_SEL_SHIFT, + CLK_SPI_PLL_SEL_DPLL = 0, + CLK_SPI_PLL_SEL_VPLL0, + CLK_SPI_PLL_SEL_24M, + CLK_SPI_DIV_CON_SHIFT = 0, + CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT, + + /* CRU_CLK_SEL34_CON */ + CLK_SARADC_DIV_CON_SHIFT = 0, + CLK_SARADC_DIV_CON_MASK = 0x7ff << CLK_SARADC_DIV_CON_SHIFT, + + /* CRU_CLK_SEL36_CON */ + PERI_PLL_SEL_SHIFT = 6, + PERI_PLL_SEL_MASK = 0x3 << PERI_PLL_SEL_SHIFT, + PERI_PLL_DPLL = 0, + PERI_PLL_VPLL0, + PERI_PLL_VPLL1, + PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, + + /* CRU_CLK_SEL37_CON */ + PERI_PCLK_DIV_SHIFT = 8, + PERI_PCLK_DIV_MASK = 0x1f << PERI_PCLK_DIV_SHIFT, + PERI_HCLK_DIV_SHIFT = 0, + PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT, + + /* CRU_CLKSEL41_CON */ + EMMC_CLK_SEL_SHIFT = 15, + EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, + EMMC_CLK_SEL_EMMC = 0, + EMMC_CLK_SEL_EMMC_DIV50, + EMMC_PLL_SHIFT = 8, + EMMC_PLL_MASK = 0x3 << EMMC_PLL_SHIFT, + EMMC_SEL_DPLL = 0, + EMMC_SEL_VPLL0, + EMMC_SEL_VPLL1, + EMMC_SEL_24M, + EMMC_DIV_SHIFT = 0, + EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, + + /* CRU_CLKSEL43_CON */ + MAC_CLK_SPEED_SEL_SHIFT = 15, + MAC_CLK_SPEED_SEL_MASK = 1 << MAC_CLK_SPEED_SEL_SHIFT, + MAC_CLK_SPEED_SEL_10M = 0, + MAC_CLK_SPEED_SEL_100M, + MAC_CLK_SOURCE_SEL_SHIFT = 14, + MAC_CLK_SOURCE_SEL_MASK = 1 << MAC_CLK_SOURCE_SEL_SHIFT, + MAC_CLK_SOURCE_SEL_INTERNAL = 0, + MAC_CLK_SOURCE_SEL_EXTERNAL, + MAC_PLL_SHIFT = 6, + MAC_PLL_MASK = 0x3 << MAC_PLL_SHIFT, + MAC_SEL_DPLL = 0, + MAC_SEL_VPLL0, + MAC_SEL_VPLL1, + MAC_DIV_SHIFT = 0, + MAC_DIV_MASK = 0x1f << MAC_DIV_SHIFT, + + /* CRU_CLK_SEL45_CON */ + AUDIO_PCLK_DIV_SHIFT = 8, + AUDIO_PCLK_DIV_MASK = 0x1f << AUDIO_PCLK_DIV_SHIFT, + AUDIO_PLL_SEL_SHIFT = 6, + AUDIO_PLL_SEL_MASK = 0x3 << AUDIO_PLL_SEL_SHIFT, + AUDIO_PLL_VPLL0 = 0, + AUDIO_PLL_VPLL1, + AUDIO_PLL_24M, + AUDIO_HCLK_DIV_SHIFT = 0, + AUDIO_HCLK_DIV_MASK = 0x1f << AUDIO_HCLK_DIV_SHIFT, +}; + +check_member(rk3308_cru, emmc_con[1], 0x494); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk3308/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-rk3308/gpio.h new file mode 100644 index 000000000..eca79d515 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk3308/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk3308/grf_rk3308.h b/roms/u-boot/arch/arm/include/asm/arch-rk3308/grf_rk3308.h new file mode 100644 index 000000000..a995bb950 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk3308/grf_rk3308.h @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + *Copyright 2019 Rockchip Electronics Co., Ltd. + */ +#ifndef _ASM_ARCH_GRF_rk3308_H +#define _ASM_ARCH_GRF_rk3308_H + +struct rk3308_grf { + unsigned int gpio0a_iomux; + unsigned int reserved0; + unsigned int gpio0b_iomux; + unsigned int reserved1; + unsigned int gpio0c_iomux; + unsigned int reserved2[3]; + unsigned int gpio1a_iomux; + unsigned int reserved3; + unsigned int gpio1bl_iomux; + unsigned int gpio1bh_iomux; + unsigned int gpio1cl_iomux; + unsigned int gpio1ch_iomux; + unsigned int gpio1d_iomux; + unsigned int reserved4; + unsigned int gpio2a_iomux; + unsigned int reserved5; + unsigned int gpio2b_iomux; + unsigned int reserved6; + unsigned int gpio2c_iomux; + unsigned int reserved7[3]; + unsigned int gpio3a_iomux; + unsigned int reserved8; + unsigned int gpio3b_iomux; + unsigned int reserved9[5]; + unsigned int gpio4a_iomux; + unsigned int reserved33; + unsigned int gpio4b_iomux; + unsigned int reserved10; + unsigned int gpio4c_iomux; + unsigned int reserved11; + unsigned int gpio4d_iomux; + unsigned int reserved34; + unsigned int gpio0a_p; + unsigned int gpio0b_p; + unsigned int gpio0c_p; + unsigned int reserved12; + unsigned int gpio1a_p; + unsigned int gpio1b_p; + unsigned int gpio1c_p; + unsigned int gpio1d_p; + unsigned int gpio2a_p; + unsigned int gpio2b_p; + unsigned int gpio2c_p; + unsigned int reserved13; + unsigned int gpio3a_p; + unsigned int gpio3b_p; + unsigned int reserved14[2]; + unsigned int gpio4a_p; + unsigned int gpio4b_p; + unsigned int gpio4c_p; + unsigned int gpio4d_p; + unsigned int reserved15[(0x100 - 0xec) / 4 - 1]; + unsigned int gpio0a_e; + unsigned int gpio0b_e; + unsigned int gpio0c_e; + unsigned int reserved16; + unsigned int gpio1a_e; + unsigned int gpio1b_e; + unsigned int gpio1c_e; + unsigned int gpio1d_e; + unsigned int gpio2a_e; + unsigned int gpio2b_e; + unsigned int gpio2c_e; + unsigned int reserved17; + unsigned int gpio3a_e; + unsigned int gpio3b_e; + unsigned int reserved18[2]; + unsigned int gpio4a_e; + unsigned int gpio4b_e; + unsigned int gpio4c_e; + unsigned int gpio4d_e; + unsigned int gpio0a_sr; + unsigned int gpio0b_sr; + unsigned int gpio0c_sr; + unsigned int reserved19; + unsigned int gpio1a_sr; + unsigned int gpio1b_sr; + unsigned int gpio1c_sr; + unsigned int gpio1d_sr; + unsigned int gpio2a_sr; + unsigned int gpio2b_sr; + unsigned int gpio2c_sr; + unsigned int reserved20; + unsigned int gpio3a_sr; + unsigned int gpio3b_sr; + unsigned int reserved21[2]; + unsigned int gpio4a_sr; + unsigned int gpio4b_sr; + unsigned int gpio4c_sr; + unsigned int gpio4d_sr; + unsigned int gpio0a_smt; + unsigned int gpio0b_smt; + unsigned int gpio0c_smt; + unsigned int reserved22; + unsigned int gpio1a_smt; + unsigned int gpio1b_smt; + unsigned int gpio1c_smt; + unsigned int gpio1d_smt; + unsigned int gpio2a_smt; + unsigned int gpio2b_smt; + unsigned int gpio2c_smt; + unsigned int reserved23; + unsigned int gpio3a_smt; + unsigned int gpio3b_smt; + unsigned int reserved35[2]; + unsigned int gpio4a_smt; + unsigned int gpio4b_smt; + unsigned int gpio4c_smt; + unsigned int gpio4d_smt; + unsigned int reserved24[(0x300 - 0x1EC) / 4 - 1]; + unsigned int soc_con0; + unsigned int soc_con1; + unsigned int soc_con2; + unsigned int soc_con3; + unsigned int soc_con4; + unsigned int soc_con5; + unsigned int soc_con6; + unsigned int soc_con7; + unsigned int soc_con8; + unsigned int soc_con9; + unsigned int soc_con10; + unsigned int reserved25[(0x380 - 0x328) / 4 - 1]; + unsigned int soc_status0; + unsigned int reserved26[(0x400 - 0x380) / 4 - 1]; + unsigned int cpu_con0; + unsigned int cpu_con1; + unsigned int cpu_con2; + unsigned int reserved27[(0x420 - 0x408) / 4 - 1]; + unsigned int cpu_status0; + unsigned int cpu_status1; + unsigned int reserved28[(0x440 - 0x424) / 4 - 1]; + unsigned int pvtm_con0; + unsigned int pvtm_con1; + unsigned int pvtm_status0; + unsigned int pvtm_status1; + unsigned int reserved29[(0x460 - 0x44C) / 4 - 1]; + unsigned int tsadc_tbl; + unsigned int tsadc_tbh; + unsigned int reserved30[(0x480 - 0x464) / 4 - 1]; + unsigned int host0_con0; + unsigned int host0_con1; + unsigned int otg_con0; + unsigned int host0_status0; + unsigned int reserved31[(0x4a0 - 0x48C) / 4 - 1]; + unsigned int mac_con0; + unsigned int upctrl_con0; + unsigned int upctrl_status0; + unsigned int reserved32[(0x500 - 0x4A8) / 4 - 1]; + unsigned int os_reg0; + unsigned int os_reg1; + unsigned int os_reg2; + unsigned int os_reg3; + unsigned int os_reg4; + unsigned int os_reg5; + unsigned int os_reg6; + unsigned int os_reg7; + unsigned int os_reg8; + unsigned int os_reg9; + unsigned int os_reg10; + unsigned int os_reg11; + unsigned int reserved38[(0x600 - 0x52c) / 4 - 1]; + unsigned int soc_con12; + unsigned int reserved39; + unsigned int soc_con13; + unsigned int soc_con14; + unsigned int soc_con15; + unsigned int reserved40[(0x800 - 0x610) / 4 - 1]; + unsigned int chip_id; +}; +check_member(rk3308_grf, gpio0a_p, 0xa0); + +struct rk3308_sgrf { + unsigned int soc_con0; + unsigned int soc_con1; + unsigned int con_tzma_r0size; + unsigned int con_secure0; + unsigned int reserved0; + unsigned int clk_timer_en; + unsigned int clkgat_con; + unsigned int fastboot_addr; + unsigned int fastboot_en; + unsigned int reserved1[(0x30 - 0x24) / 4]; + unsigned int srst_con; +}; +check_member(rk3308_sgrf, fastboot_en, 0x20); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk3328/boot0.h b/roms/u-boot/arch/arm/include/asm/arch-rk3328/boot0.h new file mode 100644 index 000000000..2e78b074a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk3328/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk3328/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-rk3328/gpio.h new file mode 100644 index 000000000..eca79d515 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk3328/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk3368/boot0.h b/roms/u-boot/arch/arm/include/asm/arch-rk3368/boot0.h new file mode 100644 index 000000000..2e78b074a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk3368/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk3368/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-rk3368/gpio.h new file mode 100644 index 000000000..eca79d515 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk3368/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk3399/boot0.h b/roms/u-boot/arch/arm/include/asm/arch-rk3399/boot0.h new file mode 100644 index 000000000..2e78b074a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk3399/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rk3399/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-rk3399/gpio.h new file mode 100644 index 000000000..eca79d515 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rk3399/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/boot0.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/boot0.h new file mode 100644 index 000000000..0c375e543 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/boot0.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 Theobroma Systems Design und Consulting GmbH + */ + +/* + * Execution starts on the instruction following this 4-byte header + * (containing the magic 'RK30', 'RK31', 'RK32' or 'RK33'). This + * magic constant will be written into the final image by the rkimage + * tool, but we need to reserve space for it here. + * + * To make life easier for everyone, we build the SPL binary with + * space for this 4-byte header already included in the binary. + */ +#ifdef CONFIG_SPL_BUILD + /* + * We need to add 4 bytes of space for the 'RK33' at the + * beginning of the executable. However, as we want to keep + * this generic and make it applicable to builds that are like + * the RK3368 (TPL needs this, SPL doesn't) or the RK3399 (no + * TPL, but extra space needed in the SPL), we simply insert + * a branch-to-next-instruction-word with the expectation that + * the first one may be overwritten, if this is the first stage + * contained in the final image created with mkimage)... + */ + b 1f /* if overwritten, entry-address is at the next word */ +1: +#endif +#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM) + adr r3, entry_counter + ldr r0, [r3] + cmp r0, #1 /* check if entry_counter == 1 */ + beq reset /* regular bootup */ + add r0, #1 + str r0, [r3] /* increment the entry_counter in memory */ + mov r0, #0 /* return 0 to the BROM to signal 'OK' */ + bx lr /* return control to the BROM */ +entry_counter: + .word 0 +#endif + +#if (defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARM64)) + /* U-Boot proper of armv7 do not need this */ + b reset +#endif + +#if !defined(CONFIG_ARM64) + /* + * For armv7, the addr '_start' will used as vector start address + * and write to VBAR register, which needs to aligned to 0x20. + */ + .align(5), 0x0 +_start: + ARM_VECTORS +#endif + +#if !defined(CONFIG_TPL_BUILD) && defined(CONFIG_SPL_BUILD) && \ + (CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0) + .space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */ +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/boot_mode.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/boot_mode.h new file mode 100644 index 000000000..6b2a610cf --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/boot_mode.h @@ -0,0 +1,25 @@ +#ifndef __REBOOT_MODE_H +#define __REBOOT_MODE_H + +/* high 24 bits is tag, low 8 bits is type */ +#define REBOOT_FLAG 0x5242C300 +/* normal boot */ +#define BOOT_NORMAL (REBOOT_FLAG + 0) +/* enter loader rockusb mode */ +#define BOOT_LOADER (REBOOT_FLAG + 1) +/* enter recovery */ +#define BOOT_RECOVERY (REBOOT_FLAG + 3) +/* enter fastboot mode */ +#define BOOT_FASTBOOT (REBOOT_FLAG + 9) +/* enter charging mode */ +#define BOOT_CHARGING (REBOOT_FLAG + 11) +/* enter usb mass storage mode */ +#define BOOT_UMS (REBOOT_FLAG + 12) +/* enter bootrom download mode */ +#define BOOT_BROM_DOWNLOAD 0xEF08A53C + +#ifndef __ASSEMBLY__ +int setup_boot_mode(void); +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/bootrom.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/bootrom.h new file mode 100644 index 000000000..0da78f30b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/bootrom.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2017 Heiko Stuebner + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + */ + +#ifndef _ASM_ARCH_BOOTROM_H +#define _ASM_ARCH_BOOTROM_H + +/* + * Saved Stack pointer address. + * Access might be needed in some special cases. + */ +extern u32 SAVE_SP_ADDR; + +/** + * back_to_bootrom() - return to bootrom (for TPL/SPL), passing a + * result code + * + * Transfer control back to the Rockchip BROM, restoring necessary + * register context and passing a command/result code to the BROM + * to instruct its next actions (e.g. continue boot sequence, enter + * download mode, ...). + * + * This function does not return. + * + * @brom_cmd: indicates how the bootrom should continue the boot + * sequence (e.g. load the next stage) + */ +enum rockchip_bootrom_cmd { + /* + * These can not start at 0, as 0 has a special meaning + * for setjmp(). + */ + + BROM_BOOT_NEXTSTAGE = 1, /* continue boot-sequence */ + BROM_BOOT_ENTER_DNL, /* have BROM enter download-mode */ +}; + +void back_to_bootrom(enum rockchip_bootrom_cmd brom_cmd); + +/** + * Boot-device identifiers as used by the BROM + */ +enum { + BROM_BOOTSOURCE_NAND = 1, + BROM_BOOTSOURCE_EMMC = 2, + BROM_BOOTSOURCE_SPINOR = 3, + BROM_BOOTSOURCE_SPINAND = 4, + BROM_BOOTSOURCE_SD = 5, + BROM_BOOTSOURCE_USB = 10, + BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB +}; + +extern const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1]; + +/** + * Locations of the boot-device identifier in SRAM + */ +#define BROM_BOOTSOURCE_ID_ADDR (CONFIG_IRAM_BASE + 0x10) + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/clock.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/clock.h new file mode 100644 index 000000000..5108180ea --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/clock.h @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2015 Google, Inc + */ + +#ifndef _ASM_ARCH_CLOCK_H +#define _ASM_ARCH_CLOCK_H + +struct udevice; + +/* define pll mode */ +#define RKCLK_PLL_MODE_SLOW 0 +#define RKCLK_PLL_MODE_NORMAL 1 +#define RKCLK_PLL_MODE_DEEP 2 + +enum { + ROCKCHIP_SYSCON_NOC, + ROCKCHIP_SYSCON_GRF, + ROCKCHIP_SYSCON_SGRF, + ROCKCHIP_SYSCON_PMU, + ROCKCHIP_SYSCON_PMUGRF, + ROCKCHIP_SYSCON_PMUSGRF, + ROCKCHIP_SYSCON_CIC, + ROCKCHIP_SYSCON_MSCH, +}; + +/* Standard Rockchip clock numbers */ +enum rk_clk_id { + CLK_OSC, + CLK_ARM, + CLK_DDR, + CLK_CODEC, + CLK_GENERAL, + CLK_NEW, + + CLK_COUNT, +}; + +#define PLL(_type, _id, _con, _mode, _mshift, \ + _lshift, _pflags, _rtable) \ + { \ + .id = _id, \ + .type = _type, \ + .con_offset = _con, \ + .mode_offset = _mode, \ + .mode_shift = _mshift, \ + .lock_shift = _lshift, \ + .pll_flags = _pflags, \ + .rate_table = _rtable, \ + } + +#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ + _postdiv2, _dsmpd, _frac) \ +{ \ + .rate = _rate##U, \ + .fbdiv = _fbdiv, \ + .postdiv1 = _postdiv1, \ + .refdiv = _refdiv, \ + .postdiv2 = _postdiv2, \ + .dsmpd = _dsmpd, \ + .frac = _frac, \ +} + +struct rockchip_pll_rate_table { + unsigned long rate; + unsigned int nr; + unsigned int nf; + unsigned int no; + unsigned int nb; + /* for RK3036/RK3399 */ + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int refdiv; + unsigned int postdiv2; + unsigned int dsmpd; + unsigned int frac; +}; + +enum rockchip_pll_type { + pll_rk3036, + pll_rk3066, + pll_rk3328, + pll_rk3366, + pll_rk3399, +}; + +struct rockchip_pll_clock { + unsigned int id; + unsigned int con_offset; + unsigned int mode_offset; + unsigned int mode_shift; + unsigned int lock_shift; + enum rockchip_pll_type type; + unsigned int pll_flags; + struct rockchip_pll_rate_table *rate_table; + unsigned int mode_mask; +}; + +struct rockchip_cpu_rate_table { + unsigned long rate; + unsigned int aclk_div; + unsigned int pclk_div; +}; + +int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, + void __iomem *base, ulong clk_id, + ulong drate); +ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, + void __iomem *base, ulong clk_id); +const struct rockchip_cpu_rate_table * +rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table, + ulong rate); + +static inline int rk_pll_id(enum rk_clk_id clk_id) +{ + return clk_id - 1; +} + +struct sysreset_reg { + unsigned int glb_srst_fst_value; + unsigned int glb_srst_snd_value; +}; + +/** + * clk_get_divisor() - Calculate the required clock divisior + * + * Given an input rate and a required output_rate, calculate the Rockchip + * divisor needed to achieve this. + * + * @input_rate: Input clock rate in Hz + * @output_rate: Output clock rate in Hz + * @return divisor register value to use + */ +static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) +{ + uint clk_div; + + clk_div = input_rate / output_rate; + clk_div = (clk_div + 1) & 0xfffe; + + return clk_div; +} + +/** + * rockchip_get_cru() - get a pointer to the clock/reset unit registers + * + * @return pointer to registers, or -ve error on error + */ +void *rockchip_get_cru(void); + +/** + * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers + * + * @return pointer to registers, or -ve error on error + */ +void *rockchip_get_pmucru(void); + +struct rockchip_cru; +struct rk3288_grf; + +void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf); + +int rockchip_get_clk(struct udevice **devp); + +/* + * rockchip_reset_bind() - Bind soft reset device as child of clock device + * + * @pdev: clock udevice + * @reg_offset: the first offset in cru for softreset registers + * @reg_number: the reg numbers of softreset registers + * @return 0 success, or error value + */ +int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/cpu_rk3288.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cpu_rk3288.h new file mode 100644 index 000000000..7445e64b8 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cpu_rk3288.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Rockchip Electronics Co., Ltd. + */ + +#ifndef __ASM_ARCH_CPU_RK3288_H +#define __ASM_ARCH_CPU_RK3288_H + +#include + +#define ROCKCHIP_CPU_MASK 0xffff0000 +#define ROCKCHIP_CPU_RK3288 0x32880000 + +#define ROCKCHIP_SOC_MASK (ROCKCHIP_CPU_MASK | 0xff) +#define ROCKCHIP_SOC_RK3288 (ROCKCHIP_CPU_RK3288 | 0x00) +#define ROCKCHIP_SOC_RK3288W (ROCKCHIP_CPU_RK3288 | 0x01) + +#define RK3288_HDMI_PHYS 0xff980000 +#define HDMI_CONFIG0_ID 0x4 +#define RK3288W_HDMI_REVID 0x1a + +static inline int rockchip_soc_id(void) +{ + u8 reg; + +#if defined(CONFIG_ROCKCHIP_RK3288) + reg = readb(RK3288_HDMI_PHYS + HDMI_CONFIG0_ID); + if (reg == RK3288W_HDMI_REVID) + return ROCKCHIP_SOC_RK3288W; + else + return ROCKCHIP_SOC_RK3288; +#else + return 0; +#endif +} + +#define ROCKCHIP_SOC(id, ID) \ +static inline bool soc_is_##id(void) \ +{ \ + int soc_id = rockchip_soc_id(); \ + if (soc_id) \ + return ((soc_id & ROCKCHIP_SOC_MASK) == ROCKCHIP_SOC_ ##ID); \ + return false; \ +} + +ROCKCHIP_SOC(rk3288, RK3288) +ROCKCHIP_SOC(rk3288w, RK3288W) + +#endif /* __ASM_ARCH_CPU_RK3288_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru.h new file mode 100644 index 000000000..13ea4aba8 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * (C) Copyright 2019 Amarula Solutions. + * Author: Jagan Teki + */ + +#ifndef _ROCKCHIP_CLOCK_H +#define _ROCKCHIP_CLOCK_H + +#ifndef __ASSEMBLY__ +#include +#endif + +#if defined(CONFIG_ROCKCHIP_RK3288) +# include +#elif defined(CONFIG_ROCKCHIP_RK3399) +# include +#endif + +/* CRU_GLB_RST_ST */ +enum { + GLB_POR_RST, + FST_GLB_RST_ST = BIT(0), + SND_GLB_RST_ST = BIT(1), + FST_GLB_TSADC_RST_ST = BIT(2), + SND_GLB_TSADC_RST_ST = BIT(3), + FST_GLB_WDT_RST_ST = BIT(4), + SND_GLB_WDT_RST_ST = BIT(5), +}; + +#define MHz 1000000 + +char *get_reset_cause(void); + +#endif /* _ROCKCHIP_CLOCK_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_px30.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_px30.h new file mode 100644 index 000000000..732ca3704 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_px30.h @@ -0,0 +1,449 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + */ +#ifndef _ASM_ARCH_CRU_PX30_H +#define _ASM_ARCH_CRU_PX30_H + +#define MHz 1000000 +#define KHz 1000 +#define OSC_HZ (24 * MHz) + +#define APLL_HZ (600 * MHz) +#define GPLL_HZ (1200 * MHz) +#define NPLL_HZ (1188 * MHz) +#define ACLK_BUS_HZ (200 * MHz) +#define HCLK_BUS_HZ (150 * MHz) +#define PCLK_BUS_HZ (100 * MHz) +#define ACLK_PERI_HZ (200 * MHz) +#define HCLK_PERI_HZ (150 * MHz) +#define PCLK_PMU_HZ (100 * MHz) + +/* PX30 pll id */ +enum px30_pll_id { + APLL, + DPLL, + CPLL, + NPLL, + GPLL, + PLL_COUNT, +}; + +struct px30_clk_priv { + struct px30_cru *cru; + ulong gpll_hz; +}; + +struct px30_pmuclk_priv { + struct px30_pmucru *pmucru; + ulong gpll_hz; +}; + +struct px30_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + unsigned int con4; + unsigned int reserved0[3]; +}; + +struct px30_cru { + struct px30_pll pll[4]; + unsigned int reserved1[8]; + unsigned int mode; + unsigned int misc; + unsigned int reserved2[2]; + unsigned int glb_cnt_th; + unsigned int glb_rst_st; + unsigned int glb_srst_fst; + unsigned int glb_srst_snd; + unsigned int glb_rst_con; + unsigned int reserved3[7]; + unsigned int hwffc_con0; + unsigned int reserved4; + unsigned int hwffc_th; + unsigned int hwffc_intst; + unsigned int apll_con0_s; + unsigned int apll_con1_s; + unsigned int clksel_con0_s; + unsigned int reserved5; + unsigned int clksel_con[60]; + unsigned int reserved6[4]; + unsigned int clkgate_con[18]; + unsigned int reserved7[(0x280 - 0x244) / 4 - 1]; + unsigned int ssgtbl[32]; + unsigned int softrst_con[12]; + unsigned int reserved8[(0x380 - 0x32c) / 4 - 1]; + unsigned int sdmmc_con[2]; + unsigned int sdio_con[2]; + unsigned int emmc_con[2]; + unsigned int reserved9[(0x400 - 0x394) / 4 - 1]; + unsigned int autocs_con[8]; +}; + +check_member(px30_cru, autocs_con[7], 0x41c); + +struct px30_pmucru { + struct px30_pll pll; + unsigned int pmu_mode; + unsigned int reserved1[7]; + unsigned int pmu_clksel_con[6]; + unsigned int reserved2[10]; + unsigned int pmu_clkgate_con[2]; + unsigned int reserved3[14]; + unsigned int pmu_autocs_con[2]; +}; + +check_member(px30_pmucru, pmu_autocs_con[1], 0xc4); + +struct pll_rate_table { + unsigned long rate; + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int refdiv; + unsigned int postdiv2; + unsigned int dsmpd; + unsigned int frac; +}; + +struct cpu_rate_table { + unsigned long rate; + unsigned int aclk_div; + unsigned int pclk_div; +}; + +enum { + /* PLLCON0*/ + PLL_BP_SHIFT = 15, + PLL_POSTDIV1_SHIFT = 12, + PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, + PLL_FBDIV_SHIFT = 0, + PLL_FBDIV_MASK = 0xfff, + + /* PLLCON1 */ + PLL_PDSEL_SHIFT = 15, + PLL_PD1_SHIFT = 14, + PLL_PD_SHIFT = 13, + PLL_PD_MASK = 1 << PLL_PD_SHIFT, + PLL_DSMPD_SHIFT = 12, + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, + PLL_LOCK_STATUS_SHIFT = 10, + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, + PLL_POSTDIV2_SHIFT = 6, + PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, + PLL_REFDIV_SHIFT = 0, + PLL_REFDIV_MASK = 0x3f, + + /* PLLCON2 */ + PLL_FOUT4PHASEPD_SHIFT = 27, + PLL_FOUTVCOPD_SHIFT = 26, + PLL_FOUTPOSTDIVPD_SHIFT = 25, + PLL_DACPD_SHIFT = 24, + PLL_FRAC_DIV = 0xffffff, + + /* CRU_MODE */ + PLLMUX_FROM_XIN24M = 0, + PLLMUX_FROM_PLL, + PLLMUX_FROM_RTC32K, + USBPHY480M_MODE_SHIFT = 8, + USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT, + NPLL_MODE_SHIFT = 6, + NPLL_MODE_MASK = 3 << NPLL_MODE_SHIFT, + DPLL_MODE_SHIFT = 4, + DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, + CPLL_MODE_SHIFT = 2, + CPLL_MODE_MASK = 3 << CPLL_MODE_SHIFT, + APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 3 << APLL_MODE_SHIFT, + + /* CRU_CLK_SEL0_CON */ + CORE_ACLK_DIV_SHIFT = 12, + CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT, + CORE_DBG_DIV_SHIFT = 8, + CORE_DBG_DIV_MASK = 0x03 << CORE_DBG_DIV_SHIFT, + CORE_CLK_PLL_SEL_SHIFT = 7, + CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, + CORE_CLK_PLL_SEL_APLL = 0, + CORE_CLK_PLL_SEL_GPLL, + CORE_DIV_CON_SHIFT = 0, + CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, + + /* CRU_CLK_SEL3_CON */ + ACLK_VO_PLL_SHIFT = 6, + ACLK_VO_PLL_MASK = 0x3 << ACLK_VO_PLL_SHIFT, + ACLK_VO_SEL_GPLL = 0, + ACLK_VO_SEL_CPLL, + ACLK_VO_SEL_NPLL, + ACLK_VO_DIV_SHIFT = 0, + ACLK_VO_DIV_MASK = 0x1f << ACLK_VO_DIV_SHIFT, + + /* CRU_CLK_SEL5_CON */ + DCLK_VOPB_SEL_SHIFT = 14, + DCLK_VOPB_SEL_MASK = 0x3 << DCLK_VOPB_SEL_SHIFT, + DCLK_VOPB_SEL_DIVOUT = 0, + DCLK_VOPB_SEL_FRACOUT, + DCLK_VOPB_SEL_24M, + DCLK_VOPB_PLL_SEL_SHIFT = 11, + DCLK_VOPB_PLL_SEL_MASK = 0x1 << DCLK_VOPB_PLL_SEL_SHIFT, + DCLK_VOPB_PLL_SEL_CPLL = 0, + DCLK_VOPB_PLL_SEL_NPLL, + DCLK_VOPB_DIV_SHIFT = 0, + DCLK_VOPB_DIV_MASK = 0xff, + + /* CRU_CLK_SEL8_CON */ + DCLK_VOPL_SEL_SHIFT = 14, + DCLK_VOPL_SEL_MASK = 0x3 << DCLK_VOPL_SEL_SHIFT, + DCLK_VOPL_SEL_DIVOUT = 0, + DCLK_VOPL_SEL_FRACOUT, + DCLK_VOPL_SEL_24M, + DCLK_VOPL_PLL_SEL_SHIFT = 11, + DCLK_VOPL_PLL_SEL_MASK = 0x1 << DCLK_VOPL_PLL_SEL_SHIFT, + DCLK_VOPL_PLL_SEL_NPLL = 0, + DCLK_VOPL_PLL_SEL_CPLL, + DCLK_VOPL_DIV_SHIFT = 0, + DCLK_VOPL_DIV_MASK = 0xff, + + /* CRU_CLK_SEL14_CON */ + PERI_PLL_SEL_SHIFT = 15, + PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, + PERI_PLL_GPLL = 0, + PERI_PLL_CPLL, + PERI_HCLK_DIV_SHIFT = 8, + PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT, + PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, + + /* CRU_CLKSEL15_CON */ + NANDC_CLK_SEL_SHIFT = 15, + NANDC_CLK_SEL_MASK = 0x1 << NANDC_CLK_SEL_SHIFT, + NANDC_CLK_SEL_NANDC = 0, + NANDC_CLK_SEL_NANDC_DIV50, + NANDC_DIV50_SHIFT = 8, + NANDC_DIV50_MASK = 0x1f << NANDC_DIV50_SHIFT, + NANDC_PLL_SHIFT = 6, + NANDC_PLL_MASK = 0x3 << NANDC_PLL_SHIFT, + NANDC_SEL_GPLL = 0, + NANDC_SEL_CPLL, + NANDC_SEL_NPLL, + NANDC_DIV_SHIFT = 0, + NANDC_DIV_MASK = 0x1f << NANDC_DIV_SHIFT, + + /* CRU_CLKSEL20_CON */ + EMMC_PLL_SHIFT = 14, + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, + EMMC_SEL_GPLL = 0, + EMMC_SEL_CPLL, + EMMC_SEL_NPLL, + EMMC_SEL_24M, + EMMC_DIV_SHIFT = 0, + EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, + + /* CRU_CLKSEL21_CON */ + EMMC_CLK_SEL_SHIFT = 15, + EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, + EMMC_CLK_SEL_EMMC = 0, + EMMC_CLK_SEL_EMMC_DIV50, + EMMC_DIV50_SHIFT = 0, + EMMC_DIV50_MASK = 0xff << EMMC_DIV_SHIFT, + + /* CRU_CLKSEL22_CON */ + GMAC_PLL_SEL_SHIFT = 14, + GMAC_PLL_SEL_MASK = 3 << GMAC_PLL_SEL_SHIFT, + GMAC_PLL_SEL_GPLL = 0, + GMAC_PLL_SEL_CPLL, + GMAC_PLL_SEL_NPLL, + CLK_GMAC_DIV_SHIFT = 8, + CLK_GMAC_DIV_MASK = 0x1f << CLK_GMAC_DIV_SHIFT, + SFC_PLL_SEL_SHIFT = 7, + SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, + SFC_DIV_CON_SHIFT = 0, + SFC_DIV_CON_MASK = 0x7f, + + /* CRU_CLK_SEL23_CON */ + BUS_PLL_SEL_SHIFT = 15, + BUS_PLL_SEL_MASK = 1 << BUS_PLL_SEL_SHIFT, + BUS_PLL_SEL_GPLL = 0, + BUS_PLL_SEL_CPLL, + BUS_ACLK_DIV_SHIFT = 8, + BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, + RMII_CLK_SEL_SHIFT = 7, + RMII_CLK_SEL_MASK = 1 << RMII_CLK_SEL_SHIFT, + RMII_CLK_SEL_10M = 0, + RMII_CLK_SEL_100M, + RMII_EXTCLK_SEL_SHIFT = 6, + RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, + RMII_EXTCLK_SEL_INT = 0, + RMII_EXTCLK_SEL_EXT, + PCLK_GMAC_DIV_SHIFT = 0, + PCLK_GMAC_DIV_MASK = 0x0f << PCLK_GMAC_DIV_SHIFT, + + /* CRU_CLK_SEL24_CON */ + BUS_PCLK_DIV_SHIFT = 8, + BUS_PCLK_DIV_MASK = 3 << BUS_PCLK_DIV_SHIFT, + BUS_HCLK_DIV_SHIFT = 0, + BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT, + + /* CRU_CLK_SEL25_CON */ + CRYPTO_APK_SEL_SHIFT = 14, + CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT, + CRYPTO_PLL_SEL_GPLL = 0, + CRYPTO_PLL_SEL_CPLL, + CRYPTO_PLL_SEL_NPLL = 0, + CRYPTO_APK_DIV_SHIFT = 8, + CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT, + CRYPTO_PLL_SEL_SHIFT = 6, + CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT, + CRYPTO_DIV_SHIFT = 0, + CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT, + + /* CRU_CLK_SEL30_CON */ + CLK_I2S1_DIV_CON_MASK = 0x7f, + CLK_I2S1_PLL_SEL_MASK = 0X1 << 8, + CLK_I2S1_PLL_SEL_GPLL = 0X0 << 8, + CLK_I2S1_PLL_SEL_NPLL = 0X1 << 8, + CLK_I2S1_SEL_MASK = 0x3 << 10, + CLK_I2S1_SEL_I2S1 = 0x0 << 10, + CLK_I2S1_SEL_FRAC = 0x1 << 10, + CLK_I2S1_SEL_MCLK_IN = 0x2 << 10, + CLK_I2S1_SEL_OSC = 0x3 << 10, + CLK_I2S1_OUT_SEL_MASK = 0x1 << 15, + CLK_I2S1_OUT_SEL_I2S1 = 0x0 << 15, + CLK_I2S1_OUT_SEL_OSC = 0x1 << 15, + + /* CRU_CLK_SEL31_CON */ + CLK_I2S1_FRAC_NUMERATOR_SHIFT = 16, + CLK_I2S1_FRAC_NUMERATOR_MASK = 0xffff << 16, + CLK_I2S1_FRAC_DENOMINATOR_SHIFT = 0, + CLK_I2S1_FRAC_DENOMINATOR_MASK = 0xffff, + + /* CRU_CLK_SEL34_CON */ + UART1_PLL_SEL_SHIFT = 14, + UART1_PLL_SEL_MASK = 3 << UART1_PLL_SEL_SHIFT, + UART1_PLL_SEL_GPLL = 0, + UART1_PLL_SEL_24M, + UART1_PLL_SEL_480M, + UART1_PLL_SEL_NPLL, + UART1_DIV_CON_SHIFT = 0, + UART1_DIV_CON_MASK = 0x1f << UART1_DIV_CON_SHIFT, + + /* CRU_CLK_SEL35_CON */ + UART1_CLK_SEL_SHIFT = 14, + UART1_CLK_SEL_MASK = 3 << UART1_PLL_SEL_SHIFT, + UART1_CLK_SEL_UART1 = 0, + UART1_CLK_SEL_UART1_NP5, + UART1_CLK_SEL_UART1_FRAC, + UART1_DIVNP5_SHIFT = 0, + UART1_DIVNP5_MASK = 0x1f << UART1_DIVNP5_SHIFT, + + /* CRU_CLK_SEL37_CON */ + UART2_PLL_SEL_SHIFT = 14, + UART2_PLL_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT, + UART2_PLL_SEL_GPLL = 0, + UART2_PLL_SEL_24M, + UART2_PLL_SEL_480M, + UART2_PLL_SEL_NPLL, + UART2_DIV_CON_SHIFT = 0, + UART2_DIV_CON_MASK = 0x1f << UART2_DIV_CON_SHIFT, + + /* CRU_CLK_SEL38_CON */ + UART2_CLK_SEL_SHIFT = 14, + UART2_CLK_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT, + UART2_CLK_SEL_UART2 = 0, + UART2_CLK_SEL_UART2_NP5, + UART2_CLK_SEL_UART2_FRAC, + UART2_DIVNP5_SHIFT = 0, + UART2_DIVNP5_MASK = 0x1f << UART2_DIVNP5_SHIFT, + + /* CRU_CLK_SEL40_CON */ + UART3_PLL_SEL_SHIFT = 14, + UART3_PLL_SEL_MASK = 3 << UART3_PLL_SEL_SHIFT, + UART3_PLL_SEL_GPLL = 0, + UART3_PLL_SEL_24M, + UART3_PLL_SEL_480M, + UART3_PLL_SEL_NPLL, + UART3_DIV_CON_SHIFT = 0, + UART3_DIV_CON_MASK = 0x1f << UART3_DIV_CON_SHIFT, + + /* CRU_CLK_SEL41_CON */ + UART3_CLK_SEL_SHIFT = 14, + UART3_CLK_SEL_MASK = 3 << UART3_PLL_SEL_SHIFT, + UART3_CLK_SEL_UART3 = 0, + UART3_CLK_SEL_UART3_NP5, + UART3_CLK_SEL_UART3_FRAC, + UART3_DIVNP5_SHIFT = 0, + UART3_DIVNP5_MASK = 0x1f << UART3_DIVNP5_SHIFT, + + /* CRU_CLK_SEL46_CON */ + UART5_PLL_SEL_SHIFT = 14, + UART5_PLL_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT, + UART5_PLL_SEL_GPLL = 0, + UART5_PLL_SEL_24M, + UART5_PLL_SEL_480M, + UART5_PLL_SEL_NPLL, + UART5_DIV_CON_SHIFT = 0, + UART5_DIV_CON_MASK = 0x1f << UART5_DIV_CON_SHIFT, + + /* CRU_CLK_SEL47_CON */ + UART5_CLK_SEL_SHIFT = 14, + UART5_CLK_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT, + UART5_CLK_SEL_UART5 = 0, + UART5_CLK_SEL_UART5_NP5, + UART5_CLK_SEL_UART5_FRAC, + UART5_DIVNP5_SHIFT = 0, + UART5_DIVNP5_MASK = 0x1f << UART5_DIVNP5_SHIFT, + + /* CRU_CLK_SEL49_CON */ + CLK_I2C_PLL_SEL_GPLL = 0, + CLK_I2C_PLL_SEL_24M, + CLK_I2C_DIV_CON_MASK = 0x7f, + CLK_I2C_PLL_SEL_MASK = 1, + CLK_I2C1_PLL_SEL_SHIFT = 15, + CLK_I2C1_DIV_CON_SHIFT = 8, + CLK_I2C0_PLL_SEL_SHIFT = 7, + CLK_I2C0_DIV_CON_SHIFT = 0, + + /* CRU_CLK_SEL50_CON */ + CLK_I2C3_PLL_SEL_SHIFT = 15, + CLK_I2C3_DIV_CON_SHIFT = 8, + CLK_I2C2_PLL_SEL_SHIFT = 7, + CLK_I2C2_DIV_CON_SHIFT = 0, + + /* CRU_CLK_SEL52_CON */ + CLK_PWM_PLL_SEL_GPLL = 0, + CLK_PWM_PLL_SEL_24M, + CLK_PWM_DIV_CON_MASK = 0x7f, + CLK_PWM_PLL_SEL_MASK = 1, + CLK_PWM1_PLL_SEL_SHIFT = 15, + CLK_PWM1_DIV_CON_SHIFT = 8, + CLK_PWM0_PLL_SEL_SHIFT = 7, + CLK_PWM0_DIV_CON_SHIFT = 0, + + /* CRU_CLK_SEL53_CON */ + CLK_SPI_PLL_SEL_GPLL = 0, + CLK_SPI_PLL_SEL_24M, + CLK_SPI_DIV_CON_MASK = 0x7f, + CLK_SPI_PLL_SEL_MASK = 1, + CLK_SPI1_PLL_SEL_SHIFT = 15, + CLK_SPI1_DIV_CON_SHIFT = 8, + CLK_SPI0_PLL_SEL_SHIFT = 7, + CLK_SPI0_DIV_CON_SHIFT = 0, + + /* CRU_CLK_SEL55_CON */ + CLK_SARADC_DIV_CON_SHIFT = 0, + CLK_SARADC_DIV_CON_MASK = 0x7ff, + + /* CRU_CLK_GATE10_CON */ + CLK_I2S1_OUT_MCLK_PAD_MASK = 0x1 << 9, + CLK_I2S1_OUT_MCLK_PAD_ENABLE = 0x1 << 9, + CLK_I2S1_OUT_MCLK_PAD_DISABLE = 0x0 << 9, + + /* CRU_PMU_MODE */ + GPLL_MODE_SHIFT = 0, + GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, + + /* CRU_PMU_CLK_SEL0_CON */ + CLK_PMU_PCLK_DIV_SHIFT = 0, + CLK_PMU_PCLK_DIV_MASK = 0x1f << CLK_PMU_PCLK_DIV_SHIFT, +}; +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3036.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3036.h new file mode 100644 index 000000000..5db0407ba --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3036.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + */ +#ifndef _ASM_ARCH_CRU_RK3036_H +#define _ASM_ARCH_CRU_RK3036_H + +#define OSC_HZ (24 * 1000 * 1000) + +#define APLL_HZ (600 * 1000000) +#define GPLL_HZ (594 * 1000000) + +#define CORE_PERI_HZ 150000000 +#define CORE_ACLK_HZ 300000000 + +#define BUS_ACLK_HZ 148500000 +#define BUS_HCLK_HZ 148500000 +#define BUS_PCLK_HZ 74250000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk3036_clk_priv { + struct rk3036_cru *cru; + ulong rate; +}; + +struct rk3036_cru { + struct rk3036_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + } pll[4]; + unsigned int cru_mode_con; + unsigned int cru_clksel_con[35]; + unsigned int cru_clkgate_con[11]; + unsigned int reserved; + unsigned int cru_glb_srst_fst_value; + unsigned int cru_glb_srst_snd_value; + unsigned int reserved1[2]; + unsigned int cru_softrst_con[9]; + unsigned int cru_misc_con; + unsigned int reserved2[2]; + unsigned int cru_glb_cnt_th; + unsigned int cru_sdmmc_con[2]; + unsigned int cru_sdio_con[2]; + unsigned int cru_emmc_con[2]; + unsigned int reserved3; + unsigned int cru_rst_st; + unsigned int reserved4[0x23]; + unsigned int cru_pll_mask_con; +}; +check_member(rk3036_cru, cru_pll_mask_con, 0x01f0); + +struct pll_div { + u32 refdiv; + u32 fbdiv; + u32 postdiv1; + u32 postdiv2; + u32 frac; +}; + +enum { + /* PLLCON0*/ + PLL_POSTDIV1_SHIFT = 12, + PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, + PLL_FBDIV_SHIFT = 0, + PLL_FBDIV_MASK = 0xfff, + + /* PLLCON1 */ + PLL_RST_SHIFT = 14, + PLL_DSMPD_SHIFT = 12, + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, + PLL_LOCK_STATUS_SHIFT = 10, + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, + PLL_POSTDIV2_SHIFT = 6, + PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, + PLL_REFDIV_SHIFT = 0, + PLL_REFDIV_MASK = 0x3f, + + /* CRU_MODE */ + GPLL_MODE_SHIFT = 12, + GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, + GPLL_MODE_SLOW = 0, + GPLL_MODE_NORM, + GPLL_MODE_DEEP, + DPLL_MODE_SHIFT = 4, + DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, + DPLL_MODE_SLOW = 0, + DPLL_MODE_NORM, + APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, + APLL_MODE_SLOW = 0, + APLL_MODE_NORM, + + /* CRU_CLK_SEL0_CON */ + BUS_ACLK_PLL_SEL_SHIFT = 14, + BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, + BUS_ACLK_PLL_SEL_APLL = 0, + BUS_ACLK_PLL_SEL_DPLL, + BUS_ACLK_PLL_SEL_GPLL, + BUS_ACLK_DIV_SHIFT = 8, + BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, + CORE_CLK_PLL_SEL_SHIFT = 7, + CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, + CORE_CLK_PLL_SEL_APLL = 0, + CORE_CLK_PLL_SEL_GPLL, + CORE_DIV_CON_SHIFT = 0, + CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, + + /* CRU_CLK_SEL1_CON */ + BUS_PCLK_DIV_SHIFT = 12, + BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, + BUS_HCLK_DIV_SHIFT = 8, + BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, + CORE_ACLK_DIV_SHIFT = 4, + CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, + CORE_PERI_DIV_SHIFT = 0, + CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, + + /* CRU_CLKSEL10_CON */ + PERI_PLL_SEL_SHIFT = 14, + PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, + PERI_PLL_APLL = 0, + PERI_PLL_DPLL, + PERI_PLL_GPLL, + PERI_PCLK_DIV_SHIFT = 12, + PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, + PERI_HCLK_DIV_SHIFT = 8, + PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, + PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, + + /* CRU_CLKSEL11_CON */ + SDIO_DIV_SHIFT = 8, + SDIO_DIV_MASK = 0x7f << SDIO_DIV_SHIFT, + MMC0_DIV_SHIFT = 0, + MMC0_DIV_MASK = 0x7f << MMC0_DIV_SHIFT, + + /* CRU_CLKSEL12_CON */ + EMMC_PLL_SHIFT = 12, + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, + EMMC_SEL_APLL = 0, + EMMC_SEL_DPLL, + EMMC_SEL_GPLL, + EMMC_SEL_24M, + SDIO_PLL_SHIFT = 10, + SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, + SDIO_SEL_APLL = 0, + SDIO_SEL_DPLL, + SDIO_SEL_GPLL, + SDIO_SEL_24M, + MMC0_PLL_SHIFT = 8, + MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, + MMC0_SEL_APLL = 0, + MMC0_SEL_DPLL, + MMC0_SEL_GPLL, + MMC0_SEL_24M, + EMMC_DIV_SHIFT = 0, + EMMC_DIV_MASK = 0x7f << EMMC_DIV_SHIFT, + + /* CRU_SOFTRST5_CON */ + DDRCTRL_PSRST_SHIFT = 11, + DDRCTRL_SRST_SHIFT = 10, + DDRPHY_PSRST_SHIFT = 9, + DDRPHY_SRST_SHIFT = 8, +}; +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3128.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3128.h new file mode 100644 index 000000000..cca812d29 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3128.h @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2017 Rockchip Electronics Co., Ltd + */ + +#ifndef _ASM_ARCH_CRU_RK3128_H +#define _ASM_ARCH_CRU_RK3128_H + +#ifndef __ASSEMBLY__ +#include +#endif + +#define MHz 1000000 +#define OSC_HZ (24 * MHz) + +#define APLL_HZ (600 * MHz) +#define GPLL_HZ (594 * MHz) + +#define CORE_PERI_HZ 150000000 +#define CORE_ACLK_HZ 300000000 + +#define BUS_ACLK_HZ 148500000 +#define BUS_HCLK_HZ 148500000 +#define BUS_PCLK_HZ 74250000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk3128_clk_priv { + struct rk3128_cru *cru; +}; + +struct rk3128_cru { + struct rk3128_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + } pll[4]; + unsigned int cru_mode_con; + unsigned int cru_clksel_con[35]; + unsigned int cru_clkgate_con[11]; + unsigned int reserved; + unsigned int cru_glb_srst_fst_value; + unsigned int cru_glb_srst_snd_value; + unsigned int reserved1[2]; + unsigned int cru_softrst_con[9]; + unsigned int cru_misc_con; + unsigned int reserved2[2]; + unsigned int cru_glb_cnt_th; + unsigned int reserved3[3]; + unsigned int cru_glb_rst_st; + unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1]; + unsigned int cru_sdmmc_con[2]; + unsigned int cru_sdio_con[2]; + unsigned int reserved5[2]; + unsigned int cru_emmc_con[2]; + unsigned int reserved6[4]; + unsigned int cru_pll_prg_en; +}; +check_member(rk3128_cru, cru_pll_prg_en, 0x01f0); + +struct pll_div { + u32 refdiv; + u32 fbdiv; + u32 postdiv1; + u32 postdiv2; + u32 frac; +}; + +enum { + /* PLLCON0*/ + PLL_POSTDIV1_SHIFT = 12, + PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, + PLL_FBDIV_SHIFT = 0, + PLL_FBDIV_MASK = 0xfff, + + /* PLLCON1 */ + PLL_RST_SHIFT = 14, + PLL_PD_SHIFT = 13, + PLL_PD_MASK = 1 << PLL_PD_SHIFT, + PLL_DSMPD_SHIFT = 12, + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, + PLL_LOCK_STATUS_SHIFT = 10, + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, + PLL_POSTDIV2_SHIFT = 6, + PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, + PLL_REFDIV_SHIFT = 0, + PLL_REFDIV_MASK = 0x3f, + + /* CRU_MODE */ + GPLL_MODE_SHIFT = 12, + GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, + GPLL_MODE_SLOW = 0, + GPLL_MODE_NORM, + GPLL_MODE_DEEP, + CPLL_MODE_SHIFT = 8, + CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT, + CPLL_MODE_SLOW = 0, + CPLL_MODE_NORM, + DPLL_MODE_SHIFT = 4, + DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, + DPLL_MODE_SLOW = 0, + DPLL_MODE_NORM, + APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, + APLL_MODE_SLOW = 0, + APLL_MODE_NORM, + + /* CRU_CLK_SEL0_CON */ + BUS_ACLK_PLL_SEL_SHIFT = 14, + BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, + BUS_ACLK_PLL_SEL_CPLL = 0, + BUS_ACLK_PLL_SEL_GPLL, + BUS_ACLK_PLL_SEL_GPLL_DIV2, + BUS_ACLK_PLL_SEL_GPLL_DIV3, + BUS_ACLK_DIV_SHIFT = 8, + BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, + CORE_CLK_PLL_SEL_SHIFT = 7, + CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, + CORE_CLK_PLL_SEL_APLL = 0, + CORE_CLK_PLL_SEL_GPLL_DIV2, + CORE_DIV_CON_SHIFT = 0, + CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, + + /* CRU_CLK_SEL1_CON */ + BUS_PCLK_DIV_SHIFT = 12, + BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, + BUS_HCLK_DIV_SHIFT = 8, + BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, + CORE_ACLK_DIV_SHIFT = 4, + CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, + CORE_PERI_DIV_SHIFT = 0, + CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, + + /* CRU_CLK_SEL2_CON */ + NANDC_PLL_SEL_SHIFT = 14, + NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT, + NANDC_PLL_SEL_CPLL = 0, + NANDC_PLL_SEL_GPLL, + NANDC_CLK_DIV_SHIFT = 8, + NANDC_CLK_DIV_MASK = 0x1f << NANDC_CLK_DIV_SHIFT, + PVTM_CLK_DIV_SHIFT = 0, + PVTM_CLK_DIV_MASK = 0x3f << PVTM_CLK_DIV_SHIFT, + + /* CRU_CLKSEL10_CON */ + PERI_PLL_SEL_SHIFT = 14, + PERI_PLL_SEL_MASK = 1 << PERI_PLL_SEL_SHIFT, + PERI_PLL_APLL = 0, + PERI_PLL_DPLL, + PERI_PLL_GPLL, + PERI_PCLK_DIV_SHIFT = 12, + PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, + PERI_HCLK_DIV_SHIFT = 8, + PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, + PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, + + /* CRU_CLKSEL11_CON */ + MMC0_PLL_SHIFT = 6, + MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, + MMC0_SEL_APLL = 0, + MMC0_SEL_GPLL, + MMC0_SEL_GPLL_DIV2, + MMC0_SEL_24M, + MMC0_DIV_SHIFT = 0, + MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, + + /* CRU_CLKSEL12_CON */ + EMMC_PLL_SHIFT = 14, + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, + EMMC_SEL_APLL = 0, + EMMC_SEL_GPLL, + EMMC_SEL_GPLL_DIV2, + EMMC_SEL_24M, + EMMC_DIV_SHIFT = 8, + EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT, + + /* CLKSEL_CON24 */ + SARADC_DIV_CON_SHIFT = 8, + SARADC_DIV_CON_MASK = GENMASK(15, 8), + SARADC_DIV_CON_WIDTH = 8, + + /* CRU_CLKSEL27_CON*/ + DCLK_VOP_SEL_SHIFT = 0, + DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, + DCLK_VOP_PLL_SEL_CPLL = 0, + DCLK_VOP_DIV_CON_SHIFT = 8, + DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT, + + /* CRU_CLKSEL31_CON */ + VIO0_PLL_SHIFT = 5, + VIO0_PLL_MASK = 7 << VIO0_PLL_SHIFT, + VI00_SEL_CPLL = 0, + VIO0_SEL_GPLL, + VIO0_DIV_SHIFT = 0, + VIO0_DIV_MASK = 0x1f << VIO0_DIV_SHIFT, + VIO1_PLL_SHIFT = 13, + VIO1_PLL_MASK = 7 << VIO1_PLL_SHIFT, + VI01_SEL_CPLL = 0, + VIO1_SEL_GPLL, + VIO1_DIV_SHIFT = 8, + VIO1_DIV_MASK = 0x1f << VIO1_DIV_SHIFT, + + /* CRU_SOFTRST5_CON */ + DDRCTRL_PSRST_SHIFT = 11, + DDRCTRL_SRST_SHIFT = 10, + DDRPHY_PSRST_SHIFT = 9, + DDRPHY_SRST_SHIFT = 8, +}; +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3188.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3188.h new file mode 100644 index 000000000..eec4815bb --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3188.h @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Heiko Stuebner + */ +#ifndef _ASM_ARCH_CRU_RK3188_H +#define _ASM_ARCH_CRU_RK3188_H + +#define OSC_HZ (24 * 1000 * 1000) + +#define APLL_HZ (1608 * 1000000) +#define APLL_SAFE_HZ (600 * 1000000) +#define GPLL_HZ (594 * 1000000) +#define CPLL_HZ (384 * 1000000) + +/* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */ +#define CPU_ACLK_HZ 297000000 +#define CPU_HCLK_HZ 148500000 +#define CPU_PCLK_HZ 74250000 +#define CPU_H2P_HZ 74250000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk3188_clk_priv { + struct rk3188_grf *grf; + struct rk3188_cru *cru; + ulong rate; + bool has_bwadj; +}; + +struct rk3188_cru { + struct rk3188_pll { + u32 con0; + u32 con1; + u32 con2; + u32 con3; + } pll[4]; + u32 cru_mode_con; + u32 cru_clksel_con[35]; + u32 cru_clkgate_con[10]; + u32 reserved1[2]; + u32 cru_glb_srst_fst_value; + u32 cru_glb_srst_snd_value; + u32 reserved2[2]; + u32 cru_softrst_con[9]; + u32 cru_misc_con; + u32 reserved3[2]; + u32 cru_glb_cnt_th; +}; +check_member(rk3188_cru, cru_glb_cnt_th, 0x0140); + +/* CRU_CLKSEL0_CON */ +enum { + /* a9_core_div: core = core_src / (a9_core_div + 1) */ + A9_CORE_DIV_SHIFT = 9, + A9_CORE_DIV_MASK = 0x1f, + CORE_PLL_SHIFT = 8, + CORE_PLL_MASK = 1, + CORE_PLL_SELECT_APLL = 0, + CORE_PLL_SELECT_GPLL, + + /* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */ + CORE_PERI_DIV_SHIFT = 6, + CORE_PERI_DIV_MASK = 3, + + /* aclk_cpu pll selection */ + CPU_ACLK_PLL_SHIFT = 5, + CPU_ACLK_PLL_MASK = 1, + CPU_ACLK_PLL_SELECT_APLL = 0, + CPU_ACLK_PLL_SELECT_GPLL, + + /* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */ + A9_CPU_DIV_SHIFT = 0, + A9_CPU_DIV_MASK = 0x1f, +}; + +/* CRU_CLKSEL1_CON */ +enum { + /* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */ + AHB2APB_DIV_SHIFT = 14, + AHB2APB_DIV_MASK = 3, + + /* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */ + CPU_PCLK_DIV_SHIFT = 12, + CPU_PCLK_DIV_MASK = 3, + + /* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */ + CPU_HCLK_DIV_SHIFT = 8, + CPU_HCLK_DIV_MASK = 3, + + /* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */ + CORE_ACLK_DIV_SHIFT = 3, + CORE_ACLK_DIV_MASK = 7, +}; + +/* CRU_CLKSEL10_CON */ +enum { + PERI_SEL_PLL_MASK = 1, + PERI_SEL_PLL_SHIFT = 15, + PERI_SEL_CPLL = 0, + PERI_SEL_GPLL, + + /* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */ + PERI_PCLK_DIV_SHIFT = 12, + PERI_PCLK_DIV_MASK = 3, + + /* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */ + PERI_HCLK_DIV_SHIFT = 8, + PERI_HCLK_DIV_MASK = 3, + + /* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */ + PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f, +}; +/* CRU_CLKSEL11_CON */ +enum { + HSICPHY_DIV_SHIFT = 8, + HSICPHY_DIV_MASK = 0x3f, + + MMC0_DIV_SHIFT = 0, + MMC0_DIV_MASK = 0x3f, +}; + +/* CRU_CLKSEL12_CON */ +enum { + UART_PLL_SHIFT = 15, + UART_PLL_MASK = 1, + UART_PLL_SELECT_GENERAL = 0, + UART_PLL_SELECT_CODEC, + + EMMC_DIV_SHIFT = 8, + EMMC_DIV_MASK = 0x3f, + + SDIO_DIV_SHIFT = 0, + SDIO_DIV_MASK = 0x3f, +}; + +/* CRU_CLKSEL25_CON */ +enum { + SPI1_DIV_SHIFT = 8, + SPI1_DIV_MASK = 0x7f, + + SPI0_DIV_SHIFT = 0, + SPI0_DIV_MASK = 0x7f, +}; + +/* CRU_MODE_CON */ +enum { + GPLL_MODE_SHIFT = 12, + GPLL_MODE_MASK = 3, + GPLL_MODE_SLOW = 0, + GPLL_MODE_NORMAL, + GPLL_MODE_DEEP, + + CPLL_MODE_SHIFT = 8, + CPLL_MODE_MASK = 3, + CPLL_MODE_SLOW = 0, + CPLL_MODE_NORMAL, + CPLL_MODE_DEEP, + + DPLL_MODE_SHIFT = 4, + DPLL_MODE_MASK = 3, + DPLL_MODE_SLOW = 0, + DPLL_MODE_NORMAL, + DPLL_MODE_DEEP, + + APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 3, + APLL_MODE_SLOW = 0, + APLL_MODE_NORMAL, + APLL_MODE_DEEP, +}; + +/* CRU_APLL_CON0 */ +enum { + CLKR_SHIFT = 8, + CLKR_MASK = 0x3f, + + CLKOD_SHIFT = 0, + CLKOD_MASK = 0x3f, +}; + +/* CRU_APLL_CON1 */ +enum { + CLKF_SHIFT = 0, + CLKF_MASK = 0x1fff, +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk322x.h new file mode 100644 index 000000000..ee12fa831 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk322x.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + */ +#ifndef _ASM_ARCH_CRU_RK322X_H +#define _ASM_ARCH_CRU_RK322X_H + +#define MHz 1000000 +#define OSC_HZ (24 * MHz) + +#define APLL_HZ (600 * MHz) +#define GPLL_HZ (594 * MHz) + +#define CORE_PERI_HZ 150000000 +#define CORE_ACLK_HZ 300000000 + +#define BUS_ACLK_HZ 148500000 +#define BUS_HCLK_HZ 148500000 +#define BUS_PCLK_HZ 74250000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk322x_clk_priv { + struct rk322x_cru *cru; + ulong rate; +}; + +struct rk322x_cru { + struct rk322x_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + } pll[4]; + unsigned int reserved0[4]; + unsigned int cru_mode_con; + unsigned int cru_clksel_con[35]; + unsigned int cru_clkgate_con[16]; + unsigned int cru_softrst_con[9]; + unsigned int cru_misc_con; + unsigned int reserved1[2]; + unsigned int cru_glb_cnt_th; + unsigned int reserved2[3]; + unsigned int cru_glb_rst_st; + unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1]; + unsigned int cru_sdmmc_con[2]; + unsigned int cru_sdio_con[2]; + unsigned int reserved4[2]; + unsigned int cru_emmc_con[2]; + unsigned int reserved5[4]; + unsigned int cru_glb_srst_fst_value; + unsigned int cru_glb_srst_snd_value; + unsigned int cru_pll_mask_con; +}; +check_member(rk322x_cru, cru_pll_mask_con, 0x01f8); + +struct pll_div { + u32 refdiv; + u32 fbdiv; + u32 postdiv1; + u32 postdiv2; + u32 frac; +}; + +enum { + /* PLLCON0*/ + PLL_BP_SHIFT = 15, + PLL_POSTDIV1_SHIFT = 12, + PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, + PLL_FBDIV_SHIFT = 0, + PLL_FBDIV_MASK = 0xfff, + + /* PLLCON1 */ + PLL_RST_SHIFT = 14, + PLL_PD_SHIFT = 13, + PLL_PD_MASK = 1 << PLL_PD_SHIFT, + PLL_DSMPD_SHIFT = 12, + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, + PLL_LOCK_STATUS_SHIFT = 10, + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, + PLL_POSTDIV2_SHIFT = 6, + PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, + PLL_REFDIV_SHIFT = 0, + PLL_REFDIV_MASK = 0x3f, + + /* CRU_MODE */ + GPLL_MODE_SHIFT = 12, + GPLL_MODE_MASK = 1 << GPLL_MODE_SHIFT, + GPLL_MODE_SLOW = 0, + GPLL_MODE_NORM, + CPLL_MODE_SHIFT = 8, + CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT, + CPLL_MODE_SLOW = 0, + CPLL_MODE_NORM, + DPLL_MODE_SHIFT = 4, + DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, + DPLL_MODE_SLOW = 0, + DPLL_MODE_NORM, + APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, + APLL_MODE_SLOW = 0, + APLL_MODE_NORM, + + /* CRU_CLK_SEL0_CON */ + BUS_ACLK_PLL_SEL_SHIFT = 13, + BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, + BUS_ACLK_PLL_SEL_APLL = 0, + BUS_ACLK_PLL_SEL_GPLL, + BUS_ACLK_PLL_SEL_HDMIPLL, + BUS_ACLK_DIV_SHIFT = 8, + BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, + CORE_CLK_PLL_SEL_SHIFT = 6, + CORE_CLK_PLL_SEL_MASK = 3 << CORE_CLK_PLL_SEL_SHIFT, + CORE_CLK_PLL_SEL_APLL = 0, + CORE_CLK_PLL_SEL_GPLL, + CORE_CLK_PLL_SEL_DPLL, + CORE_DIV_CON_SHIFT = 0, + CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, + + /* CRU_CLK_SEL1_CON */ + BUS_PCLK_DIV_SHIFT = 12, + BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, + BUS_HCLK_DIV_SHIFT = 8, + BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, + CORE_ACLK_DIV_SHIFT = 4, + CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, + CORE_PERI_DIV_SHIFT = 0, + CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, + + /* CRU_CLKSEL5_CON */ + GMAC_OUT_PLL_SHIFT = 15, + GMAC_OUT_PLL_MASK = 1 << GMAC_OUT_PLL_SHIFT, + GMAC_OUT_DIV_SHIFT = 8, + GMAC_OUT_DIV_MASK = 0x1f << GMAC_OUT_DIV_SHIFT, + MAC_PLL_SEL_SHIFT = 7, + MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, + RMII_EXTCLK_SLE_SHIFT = 5, + RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SLE_SHIFT, + RMII_EXTCLK_SEL_INT = 0, + RMII_EXTCLK_SEL_EXT, + CLK_MAC_DIV_SHIFT = 0, + CLK_MAC_DIV_MASK = 0x1f << CLK_MAC_DIV_SHIFT, + + /* CRU_CLKSEL10_CON */ + PERI_PCLK_DIV_SHIFT = 12, + PERI_PCLK_DIV_MASK = 7 << PERI_PCLK_DIV_SHIFT, + PERI_PLL_SEL_SHIFT = 10, + PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, + PERI_PLL_CPLL = 0, + PERI_PLL_GPLL, + PERI_PLL_HDMIPLL, + PERI_HCLK_DIV_SHIFT = 8, + PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, + PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, + + /* CRU_CLKSEL11_CON */ + EMMC_PLL_SHIFT = 12, + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, + EMMC_SEL_CPLL = 0, + EMMC_SEL_GPLL, + EMMC_SEL_24M, + SDIO_PLL_SHIFT = 10, + SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, + SDIO_SEL_CPLL = 0, + SDIO_SEL_GPLL, + SDIO_SEL_24M, + MMC0_PLL_SHIFT = 8, + MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, + MMC0_SEL_CPLL = 0, + MMC0_SEL_GPLL, + MMC0_SEL_24M, + MMC0_DIV_SHIFT = 0, + MMC0_DIV_MASK = 0xff << MMC0_DIV_SHIFT, + + /* CRU_CLKSEL12_CON */ + EMMC_DIV_SHIFT = 8, + EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, + SDIO_DIV_SHIFT = 0, + SDIO_DIV_MASK = 0xff << SDIO_DIV_SHIFT, + + /* CRU_CLKSEL26_CON */ + DDR_CLK_PLL_SEL_SHIFT = 8, + DDR_CLK_PLL_SEL_MASK = 3 << DDR_CLK_PLL_SEL_SHIFT, + DDR_CLK_SEL_DPLL = 0, + DDR_CLK_SEL_GPLL, + DDR_CLK_SEL_APLL, + DDR_DIV_SEL_SHIFT = 0, + DDR_DIV_SEL_MASK = 3 << DDR_DIV_SEL_SHIFT, + + /* CRU_CLKSEL27_CON */ + VOP_DCLK_DIV_SHIFT = 8, + VOP_DCLK_DIV_MASK = 0xff << VOP_DCLK_DIV_SHIFT, + VOP_PLL_SEL_SHIFT = 1, + VOP_PLL_SEL_MASK = 1 << VOP_PLL_SEL_SHIFT, + + /* CRU_CLKSEL29_CON */ + GMAC_CLK_SRC_SHIFT = 12, + GMAC_CLK_SRC_MASK = 1 << GMAC_CLK_SRC_SHIFT, + + /* CRU_SOFTRST5_CON */ + DDRCTRL_PSRST_SHIFT = 11, + DDRCTRL_SRST_SHIFT = 10, + DDRPHY_PSRST_SHIFT = 9, + DDRPHY_SRST_SHIFT = 8, +}; +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3288.h new file mode 100644 index 000000000..412b73e55 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Google, Inc + * + * (C) Copyright 2008-2014 Rockchip Electronics + * Peter, Software Engineering, . + */ +#ifndef _ASM_ARCH_CRU_RK3288_H +#define _ASM_ARCH_CRU_RK3288_H + +#define OSC_HZ (24 * 1000 * 1000) + +#define APLL_HZ (1800 * 1000000) +#define GPLL_HZ (594 * 1000000) +#define CPLL_HZ (384 * 1000000) +#define NPLL_HZ (384 * 1000000) + +/* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */ +#define PD_BUS_ACLK_HZ 297000000 +#define PD_BUS_HCLK_HZ 148500000 +#define PD_BUS_PCLK_HZ 74250000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk3288_clk_priv { + struct rk3288_grf *grf; + struct rockchip_cru *cru; + ulong rate; +}; + +struct rockchip_cru { + struct rk3288_pll { + u32 con0; + u32 con1; + u32 con2; + u32 con3; + } pll[5]; + u32 cru_mode_con; + u32 reserved0[3]; + u32 cru_clksel_con[43]; + u32 reserved1[21]; + u32 cru_clkgate_con[19]; + u32 reserved2; + u32 cru_glb_srst_fst_value; + u32 cru_glb_srst_snd_value; + u32 cru_softrst_con[12]; + u32 cru_misc_con; + u32 cru_glb_cnt_th; + u32 cru_glb_rst_con; + u32 reserved3; + u32 glb_rst_st; + u32 reserved4; + u32 cru_sdmmc_con[2]; + u32 cru_sdio0_con[2]; + u32 cru_sdio1_con[2]; + u32 cru_emmc_con[2]; +}; +check_member(rockchip_cru, cru_emmc_con[1], 0x021c); + +/* CRU_CLKSEL11_CON */ +enum { + HSICPHY_DIV_SHIFT = 8, + HSICPHY_DIV_MASK = 0x3f << HSICPHY_DIV_SHIFT, + + MMC0_PLL_SHIFT = 6, + MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, + MMC0_PLL_SELECT_CODEC = 0, + MMC0_PLL_SELECT_GENERAL, + MMC0_PLL_SELECT_24MHZ, + + MMC0_DIV_SHIFT = 0, + MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, +}; + +/* CRU_CLKSEL8_CON */ +enum { + I2S0_FRAC_DENOM_SHIFT = 0, + I2S0_FRAC_DENOM_MASK = 0xffff << I2S0_FRAC_DENOM_SHIFT, + I2S0_FRAC_NUMER_SHIFT = 16, + I2S0_FRAC_NUMER_MASK = 0xffffu << I2S0_FRAC_NUMER_SHIFT, +}; + +/* CRU_CLKSEL12_CON */ +enum { + EMMC_PLL_SHIFT = 0xe, + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, + EMMC_PLL_SELECT_CODEC = 0, + EMMC_PLL_SELECT_GENERAL, + EMMC_PLL_SELECT_24MHZ, + + EMMC_DIV_SHIFT = 8, + EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT, + + SDIO0_PLL_SHIFT = 6, + SDIO0_PLL_MASK = 3 << SDIO0_PLL_SHIFT, + SDIO0_PLL_SELECT_CODEC = 0, + SDIO0_PLL_SELECT_GENERAL, + SDIO0_PLL_SELECT_24MHZ, + + SDIO0_DIV_SHIFT = 0, + SDIO0_DIV_MASK = 0x3f << SDIO0_DIV_SHIFT, +}; + +/* CRU_CLKSEL21_CON */ +enum { + MAC_DIV_CON_SHIFT = 0xf, + MAC_DIV_CON_MASK = 0x1f << MAC_DIV_CON_SHIFT, + + RMII_EXTCLK_SHIFT = 4, + RMII_EXTCLK_MASK = 1 << RMII_EXTCLK_SHIFT, + RMII_EXTCLK_SELECT_INT_DIV_CLK = 0, + RMII_EXTCLK_SELECT_EXT_CLK = 1, + + EMAC_PLL_SHIFT = 0, + EMAC_PLL_MASK = 0x3 << EMAC_PLL_SHIFT, + EMAC_PLL_SELECT_NEW = 0x0, + EMAC_PLL_SELECT_CODEC = 0x1, + EMAC_PLL_SELECT_GENERAL = 0x2, +}; + +/* CRU_CLKSEL25_CON */ +enum { + SPI1_PLL_SHIFT = 0xf, + SPI1_PLL_MASK = 1 << SPI1_PLL_SHIFT, + SPI1_PLL_SELECT_CODEC = 0, + SPI1_PLL_SELECT_GENERAL, + + SPI1_DIV_SHIFT = 8, + SPI1_DIV_MASK = 0x7f << SPI1_DIV_SHIFT, + + SPI0_PLL_SHIFT = 7, + SPI0_PLL_MASK = 1 << SPI0_PLL_SHIFT, + SPI0_PLL_SELECT_CODEC = 0, + SPI0_PLL_SELECT_GENERAL, + + SPI0_DIV_SHIFT = 0, + SPI0_DIV_MASK = 0x7f << SPI0_DIV_SHIFT, +}; + +/* CRU_CLKSEL37_CON */ +enum { + PCLK_CORE_DBG_DIV_SHIFT = 9, + PCLK_CORE_DBG_DIV_MASK = 0x1f << PCLK_CORE_DBG_DIV_SHIFT, + + ATCLK_CORE_DIV_CON_SHIFT = 4, + ATCLK_CORE_DIV_CON_MASK = 0x1f << ATCLK_CORE_DIV_CON_SHIFT, + + CLK_L2RAM_DIV_SHIFT = 0, + CLK_L2RAM_DIV_MASK = 7 << CLK_L2RAM_DIV_SHIFT, +}; + +/* CRU_CLKSEL39_CON */ +enum { + ACLK_HEVC_PLL_SHIFT = 0xe, + ACLK_HEVC_PLL_MASK = 3 << ACLK_HEVC_PLL_SHIFT, + ACLK_HEVC_PLL_SELECT_CODEC = 0, + ACLK_HEVC_PLL_SELECT_GENERAL, + ACLK_HEVC_PLL_SELECT_NEW, + + ACLK_HEVC_DIV_SHIFT = 8, + ACLK_HEVC_DIV_MASK = 0x1f << ACLK_HEVC_DIV_SHIFT, + + SPI2_PLL_SHIFT = 7, + SPI2_PLL_MASK = 1 << SPI2_PLL_SHIFT, + SPI2_PLL_SELECT_CODEC = 0, + SPI2_PLL_SELECT_GENERAL, + + SPI2_DIV_SHIFT = 0, + SPI2_DIV_MASK = 0x7f << SPI2_DIV_SHIFT, +}; + +/* CRU_MODE_CON */ +enum { + CRU_MODE_MASK = 3, + + NPLL_MODE_SHIFT = 0xe, + NPLL_MODE_MASK = CRU_MODE_MASK << NPLL_MODE_SHIFT, + NPLL_MODE_SLOW = 0, + NPLL_MODE_NORMAL, + NPLL_MODE_DEEP, + + GPLL_MODE_SHIFT = 0xc, + GPLL_MODE_MASK = CRU_MODE_MASK << GPLL_MODE_SHIFT, + GPLL_MODE_SLOW = 0, + GPLL_MODE_NORMAL, + GPLL_MODE_DEEP, + + CPLL_MODE_SHIFT = 8, + CPLL_MODE_MASK = CRU_MODE_MASK << CPLL_MODE_SHIFT, + CPLL_MODE_SLOW = 0, + CPLL_MODE_NORMAL, + CPLL_MODE_DEEP, + + DPLL_MODE_SHIFT = 4, + DPLL_MODE_MASK = CRU_MODE_MASK << DPLL_MODE_SHIFT, + DPLL_MODE_SLOW = 0, + DPLL_MODE_NORMAL, + DPLL_MODE_DEEP, + + APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = CRU_MODE_MASK << APLL_MODE_SHIFT, + APLL_MODE_SLOW = 0, + APLL_MODE_NORMAL, + APLL_MODE_DEEP, +}; + +/* CRU_APLL_CON0 */ +enum { + CLKR_SHIFT = 8, + CLKR_MASK = 0x3f << CLKR_SHIFT, + + CLKOD_SHIFT = 0, + CLKOD_MASK = 0xf << CLKOD_SHIFT, +}; + +/* CRU_APLL_CON1 */ +enum { + LOCK_SHIFT = 0x1f, + LOCK_MASK = 1 << LOCK_SHIFT, + LOCK_UNLOCK = 0, + LOCK_LOCK, + + CLKF_SHIFT = 0, + CLKF_MASK = 0x1fff << CLKF_SHIFT, +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3328.h new file mode 100644 index 000000000..226744d67 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3328.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_CRU_RK3328_H_ +#define __ASM_ARCH_CRU_RK3328_H_ + +struct rk3328_clk_priv { + struct rk3328_cru *cru; + ulong rate; +}; + +struct rk3328_cru { + u32 apll_con[5]; + u32 reserved1[3]; + u32 dpll_con[5]; + u32 reserved2[3]; + u32 cpll_con[5]; + u32 reserved3[3]; + u32 gpll_con[5]; + u32 reserved4[3]; + u32 mode_con; + u32 misc; + u32 reserved5[2]; + u32 glb_cnt_th; + u32 glb_rst_st; + u32 glb_srst_snd_value; + u32 glb_srst_fst_value; + u32 npll_con[5]; + u32 reserved6[(0x100 - 0xb4) / 4]; + u32 clksel_con[53]; + u32 reserved7[(0x200 - 0x1d4) / 4]; + u32 clkgate_con[29]; + u32 reserved8[3]; + u32 ssgtbl[32]; + u32 softrst_con[12]; + u32 reserved9[(0x380 - 0x330) / 4]; + u32 sdmmc_con[2]; + u32 sdio_con[2]; + u32 emmc_con[2]; + u32 sdmmc_ext_con[2]; +}; +check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c); +#define MHz 1000000 +#define KHz 1000 +#define OSC_HZ (24 * MHz) +#define APLL_HZ (600 * MHz) +#define GPLL_HZ (576 * MHz) +#define CPLL_HZ (594 * MHz) + +#define CLK_CORE_HZ (600 * MHz) +#define ACLKM_CORE_HZ (300 * MHz) +#define PCLK_DBG_HZ (300 * MHz) + +#define PERIHP_ACLK_HZ (144000 * KHz) +#define PERIHP_HCLK_HZ (72000 * KHz) +#define PERIHP_PCLK_HZ (72000 * KHz) + +#define PWM_CLOCK_HZ (74 * MHz) + +enum apll_frequencies { + APLL_816_MHZ, + APLL_600_MHZ, +}; + +void rk3328_configure_cpu(struct rk3328_cru *cru, + enum apll_frequencies apll_freq); + +#endif /* __ASM_ARCH_CRU_RK3328_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3368.h new file mode 100644 index 000000000..316c67c62 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3368.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * Author: Andy Yan + */ +#ifndef _ASM_ARCH_CRU_RK3368_H +#define _ASM_ARCH_CRU_RK3368_H + +#ifndef __ASSEMBLY__ +#include +#endif + +/* RK3368 clock numbers */ +enum rk3368_pll_id { + APLLB, + APLLL, + DPLL, + CPLL, + GPLL, + NPLL, + PLL_COUNT, +}; + +struct rk3368_cru { + struct rk3368_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + } pll[6]; + unsigned int reserved[0x28]; + unsigned int clksel_con[56]; + unsigned int reserved1[8]; + unsigned int clkgate_con[25]; + unsigned int reserved2[7]; + unsigned int glb_srst_fst_val; + unsigned int glb_srst_snd_val; + unsigned int reserved3[0x1e]; + unsigned int softrst_con[15]; + unsigned int reserved4[0x11]; + unsigned int misc_con; + unsigned int glb_cnt_th; + unsigned int glb_rst_con; + unsigned int glb_rst_st; + unsigned int reserved5[0x1c]; + unsigned int sdmmc_con[2]; + unsigned int sdio0_con[2]; + unsigned int sdio1_con[2]; + unsigned int emmc_con[2]; +}; +check_member(rk3368_cru, emmc_con[1], 0x41c); + +struct rk3368_clk_priv { + struct rk3368_cru *cru; +}; + +enum { + /* PLL CON0 */ + PLL_NR_SHIFT = 8, + PLL_NR_MASK = GENMASK(13, 8), + PLL_OD_SHIFT = 0, + PLL_OD_MASK = GENMASK(3, 0), + + /* PLL CON1 */ + PLL_LOCK_STA = BIT(31), + PLL_NF_SHIFT = 0, + PLL_NF_MASK = GENMASK(12, 0), + + /* PLL CON2 */ + PLL_BWADJ_SHIFT = 0, + PLL_BWADJ_MASK = GENMASK(11, 0), + + /* PLL CON3 */ + PLL_MODE_SHIFT = 8, + PLL_MODE_MASK = GENMASK(9, 8), + PLL_MODE_SLOW = 0, + PLL_MODE_NORMAL = 1, + PLL_MODE_DEEP_SLOW = 3, + PLL_RESET_SHIFT = 5, + PLL_RESET = 1, + PLL_RESET_MASK = GENMASK(5, 5), + + /* CLKSEL12_CON */ + MCU_STCLK_DIV_SHIFT = 8, + MCU_STCLK_DIV_MASK = GENMASK(10, 8), + MCU_PLL_SEL_SHIFT = 7, + MCU_PLL_SEL_MASK = BIT(7), + MCU_PLL_SEL_CPLL = 0, + MCU_PLL_SEL_GPLL = 1, + MCU_CLK_DIV_SHIFT = 0, + MCU_CLK_DIV_MASK = GENMASK(4, 0), + + /* CLKSEL_CON25 */ + CLK_SARADC_DIV_CON_SHIFT = 8, + CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), + CLK_SARADC_DIV_CON_WIDTH = 8, + + /* CLKSEL43_CON */ + GMAC_DIV_CON_SHIFT = 0x0, + GMAC_DIV_CON_MASK = GENMASK(4, 0), + GMAC_PLL_SHIFT = 6, + GMAC_PLL_MASK = GENMASK(7, 6), + GMAC_PLL_SELECT_NEW = (0x0 << GMAC_PLL_SHIFT), + GMAC_PLL_SELECT_CODEC = (0x1 << GMAC_PLL_SHIFT), + GMAC_PLL_SELECT_GENERAL = (0x2 << GMAC_PLL_SHIFT), + GMAC_MUX_SEL_EXTCLK = BIT(8), + + /* CLKSEL51_CON */ + MMC_PLL_SEL_SHIFT = 8, + MMC_PLL_SEL_MASK = GENMASK(9, 8), + MMC_PLL_SEL_CPLL = (0 << MMC_PLL_SEL_SHIFT), + MMC_PLL_SEL_GPLL = (1 << MMC_PLL_SEL_SHIFT), + MMC_PLL_SEL_USBPHY_480M = (2 << MMC_PLL_SEL_SHIFT), + MMC_PLL_SEL_24M = (3 << MMC_PLL_SEL_SHIFT), + MMC_CLK_DIV_SHIFT = 0, + MMC_CLK_DIV_MASK = GENMASK(6, 0), + + /* SOFTRST1_CON */ + MCU_PO_SRST_MASK = BIT(13), + MCU_SYS_SRST_MASK = BIT(12), + DMA1_SRST_REQ = BIT(2), + + /* SOFTRST4_CON */ + DMA2_SRST_REQ = BIT(0), + + /* GLB_RST_CON */ + PMU_GLB_SRST_CTRL_SHIFT = 2, + PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2), + PMU_RST_BY_FST_GLB_SRST = 0, + PMU_RST_BY_SND_GLB_SRST = 1, + PMU_RST_DISABLE = 2, + WDT_GLB_SRST_CTRL_SHIFT = 1, + WDT_GLB_SRST_CTRL_MASK = BIT(1), + WDT_TRIGGER_SND_GLB_SRST = 0, + WDT_TRIGGER_FST_GLB_SRST = 1, + TSADC_GLB_SRST_CTRL_SHIFT = 0, + TSADC_GLB_SRST_CTRL_MASK = BIT(0), + TSADC_TRIGGER_SND_GLB_SRST = 0, + TSADC_TRIGGER_FST_GLB_SRST = 1, + +}; +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3399.h new file mode 100644 index 000000000..d941a129f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3399.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_CRU_RK3399_H_ +#define __ASM_ARCH_CRU_RK3399_H_ + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk3399_clk_priv { + struct rockchip_cru *cru; +}; + +struct rk3399_pmuclk_priv { + struct rk3399_pmucru *pmucru; +}; + +struct rk3399_pmucru { + u32 ppll_con[6]; + u32 reserved[0x1a]; + u32 pmucru_clksel[6]; + u32 pmucru_clkfrac_con[2]; + u32 reserved2[0x18]; + u32 pmucru_clkgate_con[3]; + u32 reserved3; + u32 pmucru_softrst_con[2]; + u32 reserved4[2]; + u32 pmucru_rstnhold_con[2]; + u32 reserved5[2]; + u32 pmucru_gatedis_con[2]; +}; +check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134); + +struct rockchip_cru { + u32 apll_l_con[6]; + u32 reserved[2]; + u32 apll_b_con[6]; + u32 reserved1[2]; + u32 dpll_con[6]; + u32 reserved2[2]; + u32 cpll_con[6]; + u32 reserved3[2]; + u32 gpll_con[6]; + u32 reserved4[2]; + u32 npll_con[6]; + u32 reserved5[2]; + u32 vpll_con[6]; + u32 reserved6[0x0a]; + u32 clksel_con[108]; + u32 reserved7[0x14]; + u32 clkgate_con[35]; + u32 reserved8[0x1d]; + u32 softrst_con[21]; + u32 reserved9[0x2b]; + u32 glb_srst_fst_value; + u32 glb_srst_snd_value; + u32 glb_cnt_th; + u32 misc_con; + u32 glb_rst_con; + u32 glb_rst_st; + u32 reserved10[0x1a]; + u32 sdmmc_con[2]; + u32 sdio0_con[2]; + u32 sdio1_con[2]; +}; +check_member(rockchip_cru, sdio1_con[1], 0x594); +#define KHz 1000 +#define OSC_HZ (24*MHz) +#define LPLL_HZ (600*MHz) +#define BPLL_HZ (600*MHz) +#define GPLL_HZ (594*MHz) +#define CPLL_HZ (384*MHz) +#define PPLL_HZ (676*MHz) + +#define PMU_PCLK_HZ (48*MHz) + +#define ACLKM_CORE_L_HZ (300*MHz) +#define ATCLK_CORE_L_HZ (300*MHz) +#define PCLK_DBG_L_HZ (100*MHz) + +#define ACLKM_CORE_B_HZ (300*MHz) +#define ATCLK_CORE_B_HZ (300*MHz) +#define PCLK_DBG_B_HZ (100*MHz) + +#define PERIHP_ACLK_HZ (148500*KHz) +#define PERIHP_HCLK_HZ (148500*KHz) +#define PERIHP_PCLK_HZ (37125*KHz) + +#define PERILP0_ACLK_HZ (99000*KHz) +#define PERILP0_HCLK_HZ (99000*KHz) +#define PERILP0_PCLK_HZ (49500*KHz) + +#define PERILP1_HCLK_HZ (99000*KHz) +#define PERILP1_PCLK_HZ (49500*KHz) + +#define PWM_CLOCK_HZ PMU_PCLK_HZ + +enum apll_l_frequencies { + APLL_L_1600_MHZ, + APLL_L_600_MHZ, +}; + +enum apll_b_frequencies { + APLL_B_600_MHZ, +}; + +void rk3399_configure_cpu_l(struct rockchip_cru *cru, + enum apll_l_frequencies apll_l_freq); +void rk3399_configure_cpu_b(struct rockchip_cru *cru, + enum apll_b_frequencies apll_b_freq); + +#endif /* __ASM_ARCH_CRU_RK3399_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rv1108.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rv1108.h new file mode 100644 index 000000000..0ba5ff6a0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/cru_rv1108.h @@ -0,0 +1,260 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Author: Andy Yan + */ +#ifndef _ASM_ARCH_CRU_RV1108_H +#define _ASM_ARCH_CRU_RV1108_H + +#ifndef __ASSEMBLY__ +#include +#endif + +#define OSC_HZ (24 * 1000 * 1000) + +#define APLL_HZ (600 * 1000000) +#define GPLL_HZ (1188 * 1000000) +#define ACLK_PERI_HZ (148500000) +#define HCLK_PERI_HZ (148500000) +#define PCLK_PERI_HZ (74250000) +#define ACLK_BUS_HZ (148500000) + +struct rv1108_clk_priv { + struct rv1108_cru *cru; + ulong rate; +}; + +struct rv1108_cru { + struct rv1108_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + unsigned int con4; + unsigned int con5; + unsigned int reserved[2]; + } pll[3]; + unsigned int clksel_con[46]; + unsigned int reserved1[2]; + unsigned int clkgate_con[20]; + unsigned int reserved2[4]; + unsigned int softrst_con[13]; + unsigned int reserved3[3]; + unsigned int glb_srst_fst_val; + unsigned int glb_srst_snd_val; + unsigned int glb_cnt_th; + unsigned int misc_con; + unsigned int glb_rst_con; + unsigned int glb_rst_st; + unsigned int sdmmc_con[2]; + unsigned int sdio_con[2]; + unsigned int emmc_con[2]; +}; +check_member(rv1108_cru, emmc_con[1], 0x01ec); + +struct pll_div { + u32 refdiv; + u32 fbdiv; + u32 postdiv1; + u32 postdiv2; + u32 frac; +}; + +enum { + /* PLL CON0 */ + FBDIV_MASK = 0xfff, + FBDIV_SHIFT = 0, + + /* PLL CON1 */ + POSTDIV2_SHIFT = 12, + POSTDIV2_MASK = 7 << POSTDIV2_SHIFT, + POSTDIV1_SHIFT = 8, + POSTDIV1_MASK = 7 << POSTDIV1_SHIFT, + REFDIV_MASK = 0x3f, + REFDIV_SHIFT = 0, + + /* PLL CON2 */ + LOCK_STA_SHIFT = 31, + LOCK_STA_MASK = 1 << LOCK_STA_SHIFT, + FRACDIV_MASK = 0xffffff, + FRACDIV_SHIFT = 0, + + /* PLL CON3 */ + WORK_MODE_SHIFT = 8, + WORK_MODE_MASK = 1 << WORK_MODE_SHIFT, + WORK_MODE_SLOW = 0, + WORK_MODE_NORMAL = 1, + DSMPD_SHIFT = 3, + DSMPD_MASK = 1 << DSMPD_SHIFT, + INTEGER_MODE = 1, + GLOBAL_POWER_DOWN_SHIFT = 0, + GLOBAL_POWER_DOWN_MASK = 1 << GLOBAL_POWER_DOWN_SHIFT, + GLOBAL_POWER_DOWN = 1, + GLOBAL_POWER_UP = 0, + + /* CLKSEL0_CON */ + CORE_PLL_SEL_SHIFT = 8, + CORE_PLL_SEL_MASK = 3 << CORE_PLL_SEL_SHIFT, + CORE_PLL_SEL_APLL = 0, + CORE_PLL_SEL_GPLL = 1, + CORE_PLL_SEL_DPLL = 2, + CORE_CLK_DIV_SHIFT = 0, + CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, + + /* CLKSEL_CON1 */ + PCLK_DBG_DIV_CON_SHIFT = 4, + PCLK_DBG_DIV_CON_MASK = 0xf << PCLK_DBG_DIV_CON_SHIFT, + ACLK_CORE_DIV_CON_SHIFT = 0, + ACLK_CORE_DIV_CON_MASK = 7 << ACLK_CORE_DIV_CON_SHIFT, + + /* CLKSEL_CON2 */ + ACLK_BUS_PLL_SEL_SHIFT = 8, + ACLK_BUS_PLL_SEL_MASK = 3 << ACLK_BUS_PLL_SEL_SHIFT, + ACLK_BUS_PLL_SEL_GPLL = 0, + ACLK_BUS_PLL_SEL_APLL = 1, + ACLK_BUS_PLL_SEL_DPLL = 2, + ACLK_BUS_DIV_CON_SHIFT = 0, + ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT, + ACLK_BUS_DIV_CON_WIDTH = 5, + + /* CLKSEL_CON3 */ + PCLK_BUS_DIV_CON_SHIFT = 8, + PCLK_BUS_DIV_CON_MASK = 0x1f << PCLK_BUS_DIV_CON_SHIFT, + HCLK_BUS_DIV_CON_SHIFT = 0, + HCLK_BUS_DIV_CON_MASK = 0x1f, + + /* CLKSEL_CON4 */ + CLK_DDR_PLL_SEL_SHIFT = 8, + CLK_DDR_PLL_SEL_MASK = 0x3 << CLK_DDR_PLL_SEL_SHIFT, + CLK_DDR_DIV_CON_SHIFT = 0, + CLK_DDR_DIV_CON_MASK = 0x3 << CLK_DDR_DIV_CON_SHIFT, + + /* CLKSEL_CON19 */ + CLK_I2C1_PLL_SEL_SHIFT = 15, + CLK_I2C1_PLL_SEL_MASK = 1 << CLK_I2C1_PLL_SEL_SHIFT, + CLK_I2C1_PLL_SEL_DPLL = 0, + CLK_I2C1_PLL_SEL_GPLL = 1, + CLK_I2C1_DIV_CON_SHIFT = 8, + CLK_I2C1_DIV_CON_MASK = 0x7f << CLK_I2C1_DIV_CON_SHIFT, + CLK_I2C0_PLL_SEL_SHIFT = 7, + CLK_I2C0_PLL_SEL_MASK = 1 << CLK_I2C0_PLL_SEL_SHIFT, + CLK_I2C0_DIV_CON_SHIFT = 0, + CLK_I2C0_DIV_CON_MASK = 0x7f, + I2C_DIV_CON_WIDTH = 7, + + /* CLKSEL_CON20 */ + CLK_I2C3_PLL_SEL_SHIFT = 15, + CLK_I2C3_PLL_SEL_MASK = 1 << CLK_I2C3_PLL_SEL_SHIFT, + CLK_I2C3_PLL_SEL_DPLL = 0, + CLK_I2C3_PLL_SEL_GPLL = 1, + CLK_I2C3_DIV_CON_SHIFT = 8, + CLK_I2C3_DIV_CON_MASK = 0x7f << CLK_I2C3_DIV_CON_SHIFT, + CLK_I2C2_PLL_SEL_SHIFT = 7, + CLK_I2C2_PLL_SEL_MASK = 1 << CLK_I2C2_PLL_SEL_SHIFT, + CLK_I2C2_DIV_CON_SHIFT = 0, + CLK_I2C2_DIV_CON_MASK = 0x7f, + + /* CLKSEL_CON22 */ + CLK_SARADC_DIV_CON_SHIFT= 0, + CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0), + CLK_SARADC_DIV_CON_WIDTH= 10, + + /* CLKSEL_CON23 */ + ACLK_PERI_PLL_SEL_SHIFT = 15, + ACLK_PERI_PLL_SEL_MASK = 1 << ACLK_PERI_PLL_SEL_SHIFT, + ACLK_PERI_PLL_SEL_GPLL = 0, + ACLK_PERI_PLL_SEL_DPLL = 1, + PCLK_PERI_DIV_CON_SHIFT = 10, + PCLK_PERI_DIV_CON_MASK = 0x1f << PCLK_PERI_DIV_CON_SHIFT, + HCLK_PERI_DIV_CON_SHIFT = 5, + HCLK_PERI_DIV_CON_MASK = 0x1f << HCLK_PERI_DIV_CON_SHIFT, + ACLK_PERI_DIV_CON_SHIFT = 0, + ACLK_PERI_DIV_CON_MASK = 0x1f, + PERI_DIV_CON_WIDTH = 5, + + /* CLKSEL24_CON */ + MAC_PLL_SEL_SHIFT = 12, + MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, + MAC_PLL_SEL_APLL = 0, + MAC_PLL_SEL_GPLL = 1, + RMII_EXTCLK_SEL_SHIFT = 8, + RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, + MAC_CLK_DIV_MASK = 0x1f, + MAC_CLK_DIV_SHIFT = 0, + + /* CLKSEL25_CON */ + EMMC_PLL_SEL_SHIFT = 12, + EMMC_PLL_SEL_MASK = 3 << EMMC_PLL_SEL_SHIFT, + EMMC_PLL_SEL_DPLL = 0, + EMMC_PLL_SEL_GPLL, + EMMC_PLL_SEL_OSC, + + /* CLKSEL26_CON */ + EMMC_CLK_DIV_SHIFT = 8, + EMMC_CLK_DIV_MASK = 0xff << EMMC_CLK_DIV_SHIFT, + + /* CLKSEL27_CON */ + SFC_PLL_SEL_SHIFT = 7, + SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, + SFC_PLL_SEL_DPLL = 0, + SFC_PLL_SEL_GPLL = 1, + SFC_CLK_DIV_SHIFT = 0, + SFC_CLK_DIV_MASK = 0x3f << SFC_CLK_DIV_SHIFT, + + /* CLKSEL28_CON */ + ACLK_VIO1_PLL_SEL_SHIFT = 14, + ACLK_VIO1_PLL_SEL_MASK = 3 << ACLK_VIO1_PLL_SEL_SHIFT, + VIO_PLL_SEL_DPLL = 0, + VIO_PLL_SEL_GPLL = 1, + ACLK_VIO1_CLK_DIV_SHIFT = 8, + ACLK_VIO1_CLK_DIV_MASK = 0x1f << ACLK_VIO1_CLK_DIV_SHIFT, + CLK_VIO_DIV_CON_WIDTH = 5, + ACLK_VIO0_PLL_SEL_SHIFT = 6, + ACLK_VIO0_PLL_SEL_MASK = 3 << ACLK_VIO0_PLL_SEL_SHIFT, + ACLK_VIO0_CLK_DIV_SHIFT = 0, + ACLK_VIO0_CLK_DIV_MASK = 0x1f << ACLK_VIO0_CLK_DIV_SHIFT, + + /* CLKSEL29_CON */ + PCLK_VIO_CLK_DIV_SHIFT = 8, + PCLK_VIO_CLK_DIV_MASK = 0x1f << PCLK_VIO_CLK_DIV_SHIFT, + HCLK_VIO_CLK_DIV_SHIFT = 0, + HCLK_VIO_CLK_DIV_MASK = 0x1f << HCLK_VIO_CLK_DIV_SHIFT, + + /* CLKSEL32_CON */ + DCLK_VOP_SEL_SHIFT = 7, + DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, + DCLK_VOP_SEL_HDMI = 0, + DCLK_VOP_SEL_PLL = 1, + DCLK_VOP_PLL_SEL_SHIFT = 6, + DCLK_VOP_PLL_SEL_MASK = 1 << DCLK_VOP_PLL_SEL_SHIFT, + DCLK_VOP_PLL_SEL_GPLL = 0, + DCLK_VOP_PLL_SEL_DPLL = 1, + DCLK_VOP_CLK_DIV_SHIFT = 0, + DCLK_VOP_CLK_DIV_MASK = 0x3f << DCLK_VOP_CLK_DIV_SHIFT, + DCLK_VOP_DIV_CON_WIDTH = 6, + + /* SOFTRST1_CON*/ + DDRPHY_SRSTN_CLKDIV_REQ_SHIFT = 0, + DDRPHY_SRSTN_CLKDIV_REQ = 1, + DDRPHY_SRSTN_CLKDIV_DIS = 0, + DDRPHY_SRSTN_CLKDIV_REQ_MASK = 1 << DDRPHY_SRSTN_CLKDIV_REQ_SHIFT, + DDRPHY_SRSTN_REQ_SHIFT = 1, + DDRPHY_SRSTN_REQ = 1, + DDRPHY_SRSTN_DIS = 0, + DDRPHY_SRSTN_REQ_MASK = 1 << DDRPHY_SRSTN_REQ_SHIFT, + DDRPHY_PSRSTN_REQ_SHIFT = 2, + DDRPHY_PSRSTN_REQ = 1, + DDRPHY_PSRSTN_DIS = 0, + DDRPHY_PSRSTN_REQ_MASK = 1 << DDRPHY_PSRSTN_REQ_SHIFT, + + /* SOFTRST2_CON*/ + DDRUPCTL_PSRSTN_REQ_SHIFT = 0, + DDRUPCTL_PSRSTN_REQ = 1, + DDRUPCTL_PSRSTN_DIS = 0, + DDRUPCTL_PSRSTN_REQ_MASK = 1 << DDRUPCTL_PSRSTN_REQ_SHIFT, + DDRUPCTL_NSRSTN_REQ_SHIFT = 1, + DDRUPCTL_NSRSTN_REQ = 1, + DDRUPCTL_NSRSTN_DIS = 0, + DDRUPCTL_NSRSTN_REQ_MASK = 1 << DDRUPCTL_NSRSTN_REQ_SHIFT, +}; +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h new file mode 100644 index 000000000..db83d0e7d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2015 Google, Inc + */ + +#ifndef _ASM_ARCH_DDR_RK3188_H +#define _ASM_ARCH_DDR_RK3188_H + +#include + +/* + * RK3188 Memory scheduler register map. + */ +struct rk3188_msch { + u32 coreid; + u32 revisionid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 readlatency; +}; +check_member(rk3188_msch, readlatency, 0x0014); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h new file mode 100644 index 000000000..979d5470e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h @@ -0,0 +1,443 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2015 Google, Inc + */ + +#ifndef _ASM_ARCH_DDR_RK3288_H +#define _ASM_ARCH_DDR_RK3288_H + +struct rk3288_ddr_pctl { + u32 scfg; + u32 sctl; + u32 stat; + u32 intrstat; + u32 reserved0[12]; + u32 mcmd; + u32 powctl; + u32 powstat; + u32 cmdtstat; + u32 tstaten; + u32 reserved1[3]; + u32 mrrcfg0; + u32 mrrstat0; + u32 mrrstat1; + u32 reserved2[4]; + u32 mcfg1; + u32 mcfg; + u32 ppcfg; + u32 mstat; + u32 lpddr2zqcfg; + u32 reserved3; + u32 dtupdes; + u32 dtuna; + u32 dtune; + u32 dtuprd0; + u32 dtuprd1; + u32 dtuprd2; + u32 dtuprd3; + u32 dtuawdt; + u32 reserved4[3]; + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tdpd; + u32 reserved5[14]; + u32 ecccfg; + u32 ecctst; + u32 eccclr; + u32 ecclog; + u32 reserved6[28]; + u32 dtuwactl; + u32 dturactl; + u32 dtucfg; + u32 dtuectl; + u32 dtuwd0; + u32 dtuwd1; + u32 dtuwd2; + u32 dtuwd3; + u32 dtuwdm; + u32 dturd0; + u32 dturd1; + u32 dturd2; + u32 dturd3; + u32 dtulfsrwd; + u32 dtulfsrrd; + u32 dtueaf; + u32 dfitctrldelay; + u32 dfiodtcfg; + u32 dfiodtcfg1; + u32 dfiodtrankmap; + u32 dfitphywrdata; + u32 dfitphywrlat; + u32 reserved7[2]; + u32 dfitrddataen; + u32 dfitphyrdlat; + u32 reserved8[2]; + u32 dfitphyupdtype0; + u32 dfitphyupdtype1; + u32 dfitphyupdtype2; + u32 dfitphyupdtype3; + u32 dfitctrlupdmin; + u32 dfitctrlupdmax; + u32 dfitctrlupddly; + u32 reserved9; + u32 dfiupdcfg; + u32 dfitrefmski; + u32 dfitctrlupdi; + u32 reserved10[4]; + u32 dfitrcfg0; + u32 dfitrstat0; + u32 dfitrwrlvlen; + u32 dfitrrdlvlen; + u32 dfitrrdlvlgateen; + u32 dfiststat0; + u32 dfistcfg0; + u32 dfistcfg1; + u32 reserved11; + u32 dfitdramclken; + u32 dfitdramclkdis; + u32 dfistcfg2; + u32 dfistparclr; + u32 dfistparlog; + u32 reserved12[3]; + u32 dfilpcfg0; + u32 reserved13[3]; + u32 dfitrwrlvlresp0; + u32 dfitrwrlvlresp1; + u32 dfitrwrlvlresp2; + u32 dfitrrdlvlresp0; + u32 dfitrrdlvlresp1; + u32 dfitrrdlvlresp2; + u32 dfitrwrlvldelay0; + u32 dfitrwrlvldelay1; + u32 dfitrwrlvldelay2; + u32 dfitrrdlvldelay0; + u32 dfitrrdlvldelay1; + u32 dfitrrdlvldelay2; + u32 dfitrrdlvlgatedelay0; + u32 dfitrrdlvlgatedelay1; + u32 dfitrrdlvlgatedelay2; + u32 dfitrcmd; + u32 reserved14[46]; + u32 ipvr; + u32 iptr; +}; +check_member(rk3288_ddr_pctl, iptr, 0x03fc); + +struct rk3288_ddr_publ_datx { + u32 dxgcr; + u32 dxgsr[2]; + u32 dxdllcr; + u32 dxdqtr; + u32 dxdqstr; + u32 reserved[10]; +}; + +struct rk3288_ddr_publ { + u32 ridr; + u32 pir; + u32 pgcr; + u32 pgsr; + u32 dllgcr; + u32 acdllcr; + u32 ptr[3]; + u32 aciocr; + u32 dxccr; + u32 dsgcr; + u32 dcr; + u32 dtpr[3]; + u32 mr[4]; + u32 odtcr; + u32 dtar; + u32 dtdr[2]; + u32 reserved1[24]; + u32 dcuar; + u32 dcudr; + u32 dcurr; + u32 dculr; + u32 dcugcr; + u32 dcutpr; + u32 dcusr[2]; + u32 reserved2[8]; + u32 bist[17]; + u32 reserved3[15]; + u32 zq0cr[2]; + u32 zq0sr[2]; + u32 zq1cr[2]; + u32 zq1sr[2]; + u32 zq2cr[2]; + u32 zq2sr[2]; + u32 zq3cr[2]; + u32 zq3sr[2]; + struct rk3288_ddr_publ_datx datx8[4]; +}; +check_member(rk3288_ddr_publ, datx8[3].dxdqstr, 0x0294); + +struct rk3288_msch { + u32 coreid; + u32 revisionid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 readlatency; + u32 reserved1[8]; + u32 activate; + u32 devtodev; +}; +check_member(rk3288_msch, devtodev, 0x003c); + +/* PCT_DFISTCFG0 */ +#define DFI_INIT_START (1 << 0) + +/* PCT_DFISTCFG1 */ +#define DFI_DRAM_CLK_SR_EN (1 << 0) +#define DFI_DRAM_CLK_DPD_EN (1 << 1) + +/* PCT_DFISTCFG2 */ +#define DFI_PARITY_INTR_EN (1 << 0) +#define DFI_PARITY_EN (1 << 1) + +/* PCT_DFILPCFG0 */ +#define TLP_RESP_TIME_SHIFT 16 +#define LP_SR_EN (1 << 8) +#define LP_PD_EN (1 << 0) + +/* PCT_DFITCTRLDELAY */ +#define TCTRL_DELAY_TIME_SHIFT 0 + +/* PCT_DFITPHYWRDATA */ +#define TPHY_WRDATA_TIME_SHIFT 0 + +/* PCT_DFITPHYRDLAT */ +#define TPHY_RDLAT_TIME_SHIFT 0 + +/* PCT_DFITDRAMCLKDIS */ +#define TDRAM_CLK_DIS_TIME_SHIFT 0 + +/* PCT_DFITDRAMCLKEN */ +#define TDRAM_CLK_EN_TIME_SHIFT 0 + +/* PCTL_DFIODTCFG */ +#define RANK0_ODT_WRITE_SEL (1 << 3) +#define RANK1_ODT_WRITE_SEL (1 << 11) + +/* PCTL_DFIODTCFG1 */ +#define ODT_LEN_BL8_W_SHIFT 16 + +/* PUBL_ACDLLCR */ +#define ACDLLCR_DLLDIS (1 << 31) +#define ACDLLCR_DLLSRST (1 << 30) + +/* PUBL_DXDLLCR */ +#define DXDLLCR_DLLDIS (1 << 31) +#define DXDLLCR_DLLSRST (1 << 30) + +/* PUBL_DLLGCR */ +#define DLLGCR_SBIAS (1 << 30) + +/* PUBL_DXGCR */ +#define DQSRTT (1 << 9) +#define DQRTT (1 << 10) + +/* PIR */ +#define PIR_INIT (1 << 0) +#define PIR_DLLSRST (1 << 1) +#define PIR_DLLLOCK (1 << 2) +#define PIR_ZCAL (1 << 3) +#define PIR_ITMSRST (1 << 4) +#define PIR_DRAMRST (1 << 5) +#define PIR_DRAMINIT (1 << 6) +#define PIR_QSTRN (1 << 7) +#define PIR_RVTRN (1 << 8) +#define PIR_ICPC (1 << 16) +#define PIR_DLLBYP (1 << 17) +#define PIR_CTLDINIT (1 << 18) +#define PIR_CLRSR (1 << 28) +#define PIR_LOCKBYP (1 << 29) +#define PIR_ZCALBYP (1 << 30) +#define PIR_INITBYP (1u << 31) + +/* PGCR */ +#define PGCR_DFTLMT_SHIFT 3 +#define PGCR_DFTCMP_SHIFT 2 +#define PGCR_DQSCFG_SHIFT 1 +#define PGCR_ITMDMD_SHIFT 0 + +/* PGSR */ +#define PGSR_IDONE (1 << 0) +#define PGSR_DLDONE (1 << 1) +#define PGSR_ZCDONE (1 << 2) +#define PGSR_DIDONE (1 << 3) +#define PGSR_DTDONE (1 << 4) +#define PGSR_DTERR (1 << 5) +#define PGSR_DTIERR (1 << 6) +#define PGSR_DFTERR (1 << 7) +#define PGSR_RVERR (1 << 8) +#define PGSR_RVEIRR (1 << 9) + +/* PTR0 */ +#define PRT_ITMSRST_SHIFT 18 +#define PRT_DLLLOCK_SHIFT 6 +#define PRT_DLLSRST_SHIFT 0 + +/* PTR1 */ +#define PRT_DINIT0_SHIFT 0 +#define PRT_DINIT1_SHIFT 19 + +/* PTR2 */ +#define PRT_DINIT2_SHIFT 0 +#define PRT_DINIT3_SHIFT 17 + +/* DCR */ +#define DDRMD_LPDDR 0 +#define DDRMD_DDR 1 +#define DDRMD_DDR2 2 +#define DDRMD_DDR3 3 +#define DDRMD_LPDDR2_LPDDR3 4 +#define DDRMD_MASK 7 +#define DDRMD_SHIFT 0 +#define PDQ_MASK 7 +#define PDQ_SHIFT 4 + +/* DXCCR */ +#define DQSNRES_MASK 0xf +#define DQSNRES_SHIFT 8 +#define DQSRES_MASK 0xf +#define DQSRES_SHIFT 4 + +/* DTPR */ +#define TDQSCKMAX_SHIFT 27 +#define TDQSCKMAX_MASK 7 +#define TDQSCK_SHIFT 24 +#define TDQSCK_MASK 7 + +/* DSGCR */ +#define DQSGX_SHIFT 5 +#define DQSGX_MASK 7 +#define DQSGE_SHIFT 8 +#define DQSGE_MASK 7 + +/* SCTL */ +#define INIT_STATE 0 +#define CFG_STATE 1 +#define GO_STATE 2 +#define SLEEP_STATE 3 +#define WAKEUP_STATE 4 + +/* STAT */ +#define LP_TRIG_SHIFT 4 +#define LP_TRIG_MASK 7 +#define PCTL_STAT_MSK 7 +#define INIT_MEM 0 +#define CONFIG 1 +#define CONFIG_REQ 2 +#define ACCESS 3 +#define ACCESS_REQ 4 +#define LOW_POWER 5 +#define LOW_POWER_ENTRY_REQ 6 +#define LOW_POWER_EXIT_REQ 7 + +/* ZQCR*/ +#define PD_OUTPUT_SHIFT 0 +#define PU_OUTPUT_SHIFT 5 +#define PD_ONDIE_SHIFT 10 +#define PU_ONDIE_SHIFT 15 +#define ZDEN_SHIFT 28 + +/* DDLGCR */ +#define SBIAS_BYPASS (1 << 23) + +/* MCFG */ +#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24 +#define PD_IDLE_SHIFT 8 +#define MDDR_EN (2 << 22) +#define LPDDR2_EN (3 << 22) +#define DDR2_EN (0 << 5) +#define DDR3_EN (1 << 5) +#define LPDDR2_S2 (0 << 6) +#define LPDDR2_S4 (1 << 6) +#define MDDR_LPDDR2_BL_2 (0 << 20) +#define MDDR_LPDDR2_BL_4 (1 << 20) +#define MDDR_LPDDR2_BL_8 (2 << 20) +#define MDDR_LPDDR2_BL_16 (3 << 20) +#define DDR2_DDR3_BL_4 0 +#define DDR2_DDR3_BL_8 1 +#define TFAW_SHIFT 18 +#define PD_EXIT_SLOW (0 << 17) +#define PD_EXIT_FAST (1 << 17) +#define PD_TYPE_SHIFT 16 +#define BURSTLENGTH_SHIFT 20 + +/* POWCTL */ +#define POWER_UP_START (1 << 0) + +/* POWSTAT */ +#define POWER_UP_DONE (1 << 0) + +/* MCMD */ +enum { + DESELECT_CMD = 0, + PREA_CMD, + REF_CMD, + MRS_CMD, + ZQCS_CMD, + ZQCL_CMD, + RSTL_CMD, + MRR_CMD = 8, + DPDE_CMD, +}; + +#define LPDDR2_MA_SHIFT 4 +#define LPDDR2_MA_MASK 0xff +#define LPDDR2_OP_SHIFT 12 +#define LPDDR2_OP_MASK 0xff + +#define START_CMD (1u << 31) + +/* + * DDRCONF + * [5:4] row(13+n) + * [1:0] col(9+n), assume bw=2 + */ +#define DDRCONF_ROW_SHIFT 4 +#define DDRCONF_COL_SHIFT 0 + +/* DEVTODEV */ +#define BUSWRTORD_SHIFT 4 +#define BUSRDTOWR_SHIFT 2 +#define BUSRDTORD_SHIFT 0 + +/* mr1 for ddr3 */ +#define DDR3_DLL_DISABLE 1 + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h new file mode 100644 index 000000000..40cdcf4a4 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h @@ -0,0 +1,190 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + */ + +#ifndef __ASM_ARCH_DDR_RK3368_H__ +#define __ASM_ARCH_DDR_RK3368_H__ + +#ifndef __ASSEMBLY__ +#include +#endif + +/* + * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only + * in a few details. Most notably, it has an additional field to track + * tREFI in controller cycles (i.e. trefi_mem_ddr3). + */ +struct rk3368_ddr_pctl { + u32 scfg; + u32 sctl; + u32 stat; + u32 intrstat; + u32 reserved0[12]; + u32 mcmd; + u32 powctl; + u32 powstat; + u32 cmdtstat; + u32 cmdtstaten; + u32 reserved1[3]; + u32 mrrcfg0; + u32 mrrstat0; + u32 mrrstat1; + u32 reserved2[4]; + u32 mcfg1; + u32 mcfg; + u32 ppcfg; + u32 mstat; + u32 lpddr2zqcfg; + u32 reserved3; + u32 dtupdes; + u32 dtuna; + u32 dtune; + u32 dtuprd0; + u32 dtuprd1; + u32 dtuprd2; + u32 dtuprd3; + u32 dtuawdt; + u32 reserved4[3]; + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tdpd; + u32 trefi_mem_ddr3; + u32 reserved5[45]; + u32 dtuwactl; + u32 dturactl; + u32 dtucfg; + u32 dtuectl; + u32 dtuwd0; + u32 dtuwd1; + u32 dtuwd2; + u32 dtuwd3; + u32 dtuwdm; + u32 dturd0; + u32 dturd1; + u32 dturd2; + u32 dturd3; + u32 dtulfsrwd; + u32 dtulfsrrd; + u32 dtueaf; + u32 dfitctrldelay; + u32 dfiodtcfg; + u32 dfiodtcfg1; + u32 dfiodtrankmap; + u32 dfitphywrdata; + u32 dfitphywrlat; + u32 reserved7[2]; + u32 dfitrddataen; + u32 dfitphyrdlat; + u32 reserved8[2]; + u32 dfitphyupdtype0; + u32 dfitphyupdtype1; + u32 dfitphyupdtype2; + u32 dfitphyupdtype3; + u32 dfitctrlupdmin; + u32 dfitctrlupdmax; + u32 dfitctrlupddly; + u32 reserved9; + u32 dfiupdcfg; + u32 dfitrefmski; + u32 dfitctrlupdi; + u32 reserved10[4]; + u32 dfitrcfg0; + u32 dfitrstat0; + u32 dfitrwrlvlen; + u32 dfitrrdlvlen; + u32 dfitrrdlvlgateen; + u32 dfiststat0; + u32 dfistcfg0; + u32 dfistcfg1; + u32 reserved11; + u32 dfitdramclken; + u32 dfitdramclkdis; + u32 dfistcfg2; + u32 dfistparclr; + u32 dfistparlog; + u32 reserved12[3]; + u32 dfilpcfg0; + u32 reserved13[3]; + u32 dfitrwrlvlresp0; + u32 dfitrwrlvlresp1; + u32 dfitrwrlvlresp2; + u32 dfitrrdlvlresp0; + u32 dfitrrdlvlresp1; + u32 dfitrrdlvlresp2; + u32 dfitrwrlvldelay0; + u32 dfitrwrlvldelay1; + u32 dfitrwrlvldelay2; + u32 dfitrrdlvldelay0; + u32 dfitrrdlvldelay1; + u32 dfitrrdlvldelay2; + u32 dfitrrdlvlgatedelay0; + u32 dfitrrdlvlgatedelay1; + u32 dfitrrdlvlgatedelay2; + u32 dfitrcmd; + u32 reserved14[46]; + u32 ipvr; + u32 iptr; +}; +check_member(rk3368_ddr_pctl, iptr, 0x03fc); + +struct rk3368_ddrphy { + u32 reg[0x100]; +}; +check_member(rk3368_ddrphy, reg[0xff], 0x03fc); + +struct rk3368_msch { + u32 coreid; + u32 revisionid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 readlatency; + u32 reserved1[8]; + u32 activate; + u32 devtodev; +}; +check_member(rk3368_msch, devtodev, 0x003c); + +/* GRF_SOC_CON0 */ +enum { + NOC_RSP_ERR_STALL = BIT(9), + MOBILE_DDR_SEL = BIT(4), + DDR0_16BIT_EN = BIT(3), + MSCH0_MAINDDR3_DDR3 = BIT(2), + MSCH0_MAINPARTIALPOP = BIT(1), + UPCTL_C_ACTIVE = BIT(0), +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/edp_rk3288.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/edp_rk3288.h new file mode 100644 index 000000000..9559813e5 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/edp_rk3288.h @@ -0,0 +1,638 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2015 Google, Inc + * Copyright 2014 Rockchip Inc. + */ + +#ifndef _ASM_ARCH_EDP_H +#define _ASM_ARCH_EDP_H + +struct rk3288_edp { + u8 res0[0x10]; + u32 dp_tx_version; + u8 res1[0x4]; + u32 func_en_1; + u32 func_en_2; + u32 video_ctl_1; + u32 video_ctl_2; + u32 video_ctl_3; + u32 video_ctl_4; + u8 res2[0xc]; + u32 video_ctl_8; + u8 res3[0x4]; + u32 video_ctl_10; + u32 total_line_l; + u32 total_line_h; + u32 active_line_l; + u32 active_line_h; + u32 v_f_porch; + u32 vsync; + u32 v_b_porch; + u32 total_pixel_l; + u32 total_pixel_h; + u32 active_pixel_l; + u32 active_pixel_h; + u32 h_f_porch_l; + u32 h_f_porch_h; + u32 hsync_l; + u32 hysnc_h; + u32 h_b_porch_l; + u32 h_b_porch_h; + u32 vid_status; + u32 total_line_sta_l; + u32 total_line_sta_h; + u32 active_line_sta_l; + u32 active_line_sta_h; + u32 v_f_porch_sta; + u32 vsync_sta; + u32 v_b_porch_sta; + u32 total_pixel_sta_l; + u32 total_pixel_sta_h; + u32 active_pixel_sta_l; + u32 active_pixel_sta_h; + u32 h_f_porch_sta_l; + u32 h_f_porch_sta_h; + u32 hsync_sta_l; + u32 hsync_sta_h; + u32 h_b_porch_sta_l; + u32 h_b_porch__sta_h; + u8 res4[0x28]; + u32 pll_reg_1; + u8 res5[4]; + u32 ssc_reg; + u8 res6[0xc]; + u32 tx_common; + u32 tx_common2; + u8 res7[0x4]; + u32 dp_aux; + u32 dp_bias; + u32 dp_test; + u32 dp_pd; + u32 dp_reserv1; + u32 dp_reserv2; + u8 res8[0x224]; + u32 lane_map; + u8 res9[0x14]; + u32 analog_ctl_2; + u8 res10[0x48]; + u32 int_state; + u32 common_int_sta_1; + u32 common_int_sta_2; + u32 common_int_sta_3; + u32 common_int_sta_4; + u32 spdif_biphase_int_sta; + u8 res11[0x4]; + u32 dp_int_sta; + u32 common_int_mask_1; + u32 common_int_mask_2; + u32 common_int_mask_3; + u32 common_int_mask_4; + u8 res12[0x08]; + u32 int_sta_mask; + u32 int_ctl; + u8 res13[0x200]; + u32 sys_ctl_1; + u32 sys_ctl_2; + u32 sys_ctl_3; + u32 sys_ctl_4; + u32 dp_vid_ctl; + u8 res14[0x4]; + u32 dp_aud_ctl; + u8 res15[0x24]; + u32 pkt_send_ctl; + u8 res16[0x4]; + u32 dp_hdcp_ctl; + u8 res17[0x34]; + u32 link_bw_set; + u32 lane_count_set; + u32 dp_training_ptn_set; + u32 ln_link_trn_ctl[4]; + u8 res18[0x4]; + u32 dp_hw_link_training; + u8 res19[0x1c]; + u32 dp_debug_ctl; + u32 hpd_deglitch_l; + u32 hpd_deglitch_h; + u8 res20[0x14]; + u32 dp_link_debug_ctl; + u8 res21[0x1c]; + u32 m_vid_0; + u32 m_vid_1; + u32 m_vid_2; + u32 n_vid_0; + u32 n_vid_1; + u32 n_vid_2; + u32 m_vid_mon; + u8 res22[0x14]; + u32 dp_video_fifo_thrd; + u8 res23[0x8]; + u32 dp_audio_margin; + u8 res24[0x20]; + u32 dp_m_cal_ctl; + u32 m_vid_gen_filter_th; + u8 res25[0x10]; + u32 m_aud_gen_filter_th; + u8 res26[0x4]; + u32 aux_ch_sta; + u32 aux_err_num; + u32 aux_ch_defer_dtl; + u32 aux_rx_comm; + u32 buf_data_ctl; + u32 aux_ch_ctl_1; + u32 aux_addr_7_0; + u32 aux_addr_15_8; + u32 aux_addr_19_16; + u32 aux_ch_ctl_2; + u8 res27[0x18]; + u32 buf_data[16]; + u32 soc_general_ctl; + u8 res29[0x1e0]; + u32 pll_reg_2; + u32 pll_reg_3; + u32 pll_reg_4; + u8 res30[0x10]; + u32 pll_reg_5; +}; +check_member(rk3288_edp, pll_reg_5, 0xa00); + +/* func_en_1 */ +#define VID_CAP_FUNC_EN_N (0x1 << 6) +#define VID_FIFO_FUNC_EN_N (0x1 << 5) +#define AUD_FIFO_FUNC_EN_N (0x1 << 4) +#define AUD_FUNC_EN_N (0x1 << 3) +#define HDCP_FUNC_EN_N (0x1 << 2) +#define SW_FUNC_EN_N (0x1 << 0) + +/* func_en_2 */ +#define SSC_FUNC_EN_N (0x1 << 7) +#define AUX_FUNC_EN_N (0x1 << 2) +#define SERDES_FIFO_FUNC_EN_N (0x1 << 1) +#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) + +/* video_ctl_1 */ +#define VIDEO_EN (0x1 << 7) +#define VIDEO_MUTE (0x1 << 6) + +/* video_ctl_2 */ +#define IN_D_RANGE_MASK (0x1 << 7) +#define IN_D_RANGE_SHIFT (7) +#define IN_D_RANGE_CEA (0x1 << 7) +#define IN_D_RANGE_VESA (0x0 << 7) +#define IN_BPC_MASK (0x7 << 4) +#define IN_BPC_SHIFT (4) +#define IN_BPC_12_BITS (0x3 << 4) +#define IN_BPC_10_BITS (0x2 << 4) +#define IN_BPC_8_BITS (0x1 << 4) +#define IN_BPC_6_BITS (0x0 << 4) +#define IN_COLOR_F_MASK (0x3 << 0) +#define IN_COLOR_F_SHIFT (0) +#define IN_COLOR_F_YCBCR444 (0x2 << 0) +#define IN_COLOR_F_YCBCR422 (0x1 << 0) +#define IN_COLOR_F_RGB (0x0 << 0) + +/* video_ctl_3 */ +#define IN_YC_COEFFI_MASK (0x1 << 7) +#define IN_YC_COEFFI_SHIFT (7) +#define IN_YC_COEFFI_ITU709 (0x1 << 7) +#define IN_YC_COEFFI_ITU601 (0x0 << 7) +#define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) +#define VID_CHK_UPDATE_TYPE_SHIFT (4) +#define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) +#define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) + +/* video_ctl_4 */ +#define BIST_EN (0x1 << 3) +#define BIST_WH_64 (0x1 << 2) +#define BIST_WH_32 (0x0 << 2) +#define BIST_TYPE_COLR_BAR (0x0 << 0) +#define BIST_TYPE_GRAY_BAR (0x1 << 0) +#define BIST_TYPE_MOBILE_BAR (0x2 << 0) + +/* video_ctl_8 */ +#define VID_HRES_TH(x) (((x) & 0xf) << 4) +#define VID_VRES_TH(x) (((x) & 0xf) << 0) + +/* video_ctl_10 */ +#define F_SEL (0x1 << 4) +#define INTERACE_SCAN_CFG (0x1 << 2) +#define INTERACD_SCAN_CFG_OFFSET 2 +#define VSYNC_POLARITY_CFG (0x1 << 1) +#define VSYNC_POLARITY_CFG_OFFSET 1 +#define HSYNC_POLARITY_CFG (0x1 << 0) +#define HSYNC_POLARITY_CFG_OFFSET 0 + +/* dp_pd */ +#define PD_INC_BG (0x1 << 7) +#define PD_EXP_BG (0x1 << 6) +#define PD_AUX (0x1 << 5) +#define PD_PLL (0x1 << 4) +#define PD_CH3 (0x1 << 3) +#define PD_CH2 (0x1 << 2) +#define PD_CH1 (0x1 << 1) +#define PD_CH0 (0x1 << 0) + +/* pll_reg_1 */ +#define REF_CLK_24M (0x1 << 0) +#define REF_CLK_27M (0x0 << 0) +#define REF_CLK_MASK (0x1 << 0) + +/* line_map */ +#define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) +#define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) +#define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) +#define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) +#define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) +#define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) +#define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) +#define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) +#define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) +#define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) +#define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) +#define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) +#define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) +#define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) +#define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) +#define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) + +/* analog_ctl_2 */ +#define SEL_24M (0x1 << 3) + +/* common_int_sta_1 */ +#define VSYNC_DET (0x1 << 7) +#define PLL_LOCK_CHG (0x1 << 6) +#define SPDIF_ERR (0x1 << 5) +#define SPDIF_UNSTBL (0x1 << 4) +#define VID_FORMAT_CHG (0x1 << 3) +#define AUD_CLK_CHG (0x1 << 2) +#define VID_CLK_CHG (0x1 << 1) +#define SW_INT (0x1 << 0) + +/* common_int_sta_2 */ +#define ENC_EN_CHG (0x1 << 6) +#define HW_BKSV_RDY (0x1 << 3) +#define HW_SHA_DONE (0x1 << 2) +#define HW_AUTH_STATE_CHG (0x1 << 1) +#define HW_AUTH_DONE (0x1 << 0) + +/* common_int_sta_3 */ +#define AFIFO_UNDER (0x1 << 7) +#define AFIFO_OVER (0x1 << 6) +#define R0_CHK_FLAG (0x1 << 5) + +/* common_int_sta_4 */ +#define PSR_ACTIVE (0x1 << 7) +#define PSR_INACTIVE (0x1 << 6) +#define SPDIF_BI_PHASE_ERR (0x1 << 5) +#define HOTPLUG_CHG (0x1 << 2) +#define HPD_LOST (0x1 << 1) +#define PLUG (0x1 << 0) + +/* dp_int_sta */ +#define INT_HPD (0x1 << 6) +#define HW_LT_DONE (0x1 << 5) +#define SINK_LOST (0x1 << 3) +#define LINK_LOST (0x1 << 2) +#define RPLY_RECEIV (0x1 << 1) +#define AUX_ERR (0x1 << 0) + +/* int_ctl */ +#define SOFT_INT_CTRL (0x1 << 2) +#define INT_POL1 (0x1 << 1) +#define INT_POL0 (0x1 << 0) +#define INT_POL (INT_POL0 | INT_POL1) + +/* sys_ctl_1 */ +#define DET_STA (0x1 << 2) +#define FORCE_DET (0x1 << 1) +#define DET_CTRL (0x1 << 0) + +/* sys_ctl_2 */ +#define CHA_CRI(x) (((x) & 0xf) << 4) +#define CHA_STA (0x1 << 2) +#define FORCE_CHA (0x1 << 1) +#define CHA_CTRL (0x1 << 0) + +/* sys_ctl_3 */ +#define HPD_STATUS (0x1 << 6) +#define F_HPD (0x1 << 5) +#define HPD_CTRL (0x1 << 4) +#define HDCP_RDY (0x1 << 3) +#define STRM_VALID (0x1 << 2) +#define F_VALID (0x1 << 1) +#define VALID_CTRL (0x1 << 0) + +/* sys_ctl_4 */ +#define FIX_M_AUD (0x1 << 4) +#define ENHANCED (0x1 << 3) +#define FIX_M_VID (0x1 << 2) +#define M_VID_UPDATE_CTRL (0x3 << 0) + +/* pll_reg_2 */ +#define LDO_OUTPUT_V_SEL_145 (2 << 6) +#define KVCO_DEFALUT (1 << 4) +#define CHG_PUMP_CUR_SEL_5US (1 << 2) +#define V2L_CUR_SEL_1MA (1 << 0) + +/* pll_reg_3 */ +#define LOCK_DET_CNT_SEL_256 (2 << 5) +#define LOOP_FILTER_RESET (0 << 4) +#define PALL_SSC_RESET (0 << 3) +#define LOCK_DET_BYPASS (0 << 2) +#define PLL_LOCK_DET_MODE (0 << 1) +#define PLL_LOCK_DET_FORCE (0 << 0) + +/* pll_reg_5 */ +#define REGULATOR_V_SEL_950MV (2 << 4) +#define STANDBY_CUR_SEL (0 << 3) +#define CHG_PUMP_INOUT_CTRL_1200MV (1 << 1) +#define CHG_PUMP_INPUT_CTRL_OP (0 << 0) + +/* ssc_reg */ +#define SSC_OFFSET (0 << 6) +#define SSC_MODE (1 << 4) +#define SSC_DEPTH (9 << 0) + +/* tx_common */ +#define TX_SWING_PRE_EMP_MODE (1 << 7) +#define PRE_DRIVER_PW_CTRL1 (0 << 5) +#define LP_MODE_CLK_REGULATOR (0 << 4) +#define RESISTOR_MSB_CTRL (0 << 3) +#define RESISTOR_CTRL (7 << 0) + +/* dp_aux */ +#define DP_AUX_COMMON_MODE (0 << 4) +#define DP_AUX_EN (0 << 3) +#define AUX_TERM_50OHM (3 << 0) + +/* dp_bias */ +#define DP_BG_OUT_SEL (4 << 4) +#define DP_DB_CUR_CTRL (0 << 3) +#define DP_BG_SEL (1 << 2) +#define DP_RESISTOR_TUNE_BG (2 << 0) + +/* dp_reserv2 */ +#define CH1_CH3_SWING_EMP_CTRL (5 << 4) +#define CH0_CH2_SWING_EMP_CTRL (5 << 0) + +/* dp_training_ptn_set */ +#define SCRAMBLING_DISABLE (0x1 << 5) +#define SCRAMBLING_ENABLE (0x0 << 5) +#define LINK_QUAL_PATTERN_SET_MASK (0x7 << 2) +#define LINK_QUAL_PATTERN_SET_HBR2 (0x5 << 2) +#define LINK_QUAL_PATTERN_SET_80BIT (0x4 << 2) +#define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) +#define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) +#define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) +#define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) +#define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) +#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) +#define SW_TRAINING_PATTERN_SET_DISABLE (0x0 << 0) + +/* dp_hw_link_training_ctl */ +#define HW_LT_ERR_CODE_MASK 0x70 +#define HW_LT_ERR_CODE_SHIFT 4 +#define HW_LT_EN (0x1 << 0) + +/* dp_debug_ctl */ +#define PLL_LOCK (0x1 << 4) +#define F_PLL_LOCK (0x1 << 3) +#define PLL_LOCK_CTRL (0x1 << 2) +#define POLL_EN (0x1 << 1) +#define PN_INV (0x1 << 0) + +/* aux_ch_sta */ +#define AUX_BUSY (0x1 << 4) +#define AUX_STATUS_MASK (0xf << 0) + +/* aux_ch_defer_ctl */ +#define DEFER_CTRL_EN (0x1 << 7) +#define DEFER_COUNT(x) (((x) & 0x7f) << 0) + +/* aux_rx_comm */ +#define AUX_RX_COMM_I2C_DEFER (0x2 << 2) +#define AUX_RX_COMM_AUX_DEFER (0x2 << 0) + +/* buffer_data_ctl */ +#define BUF_CLR (0x1 << 7) +#define BUF_HAVE_DATA (0x1 << 4) +#define BUF_DATA_COUNT(x) (((x) & 0xf) << 0) + +/* aux_ch_ctl_1 */ +#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) +#define AUX_TX_COMM_MASK (0xf << 0) +#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) +#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) +#define AUX_TX_COMM_MOT (0x1 << 2) +#define AUX_TX_COMM_WRITE (0x0 << 0) +#define AUX_TX_COMM_READ (0x1 << 0) + +/* aux_ch_ctl_2 */ +#define PD_AUX_IDLE (0x1 << 3) +#define ADDR_ONLY (0x1 << 1) +#define AUX_EN (0x1 << 0) + +/* tx_sw_reset */ +#define RST_DP_TX (0x1 << 0) + +/* analog_ctl_1 */ +#define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) + +/* analog_ctl_3 */ +#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) +#define VCO_BIT_600_MICRO (0x5 << 0) + +/* pll_filter_ctl_1 */ +#define PD_RING_OSC (0x1 << 6) +#define AUX_TERMINAL_CTRL_37_5_OHM (0x0 << 4) +#define AUX_TERMINAL_CTRL_45_OHM (0x1 << 4) +#define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) +#define AUX_TERMINAL_CTRL_65_OHM (0x3 << 4) +#define TX_CUR1_2X (0x1 << 2) +#define TX_CUR_16_MA (0x3 << 0) + +/* Definition for DPCD Register */ +#define DPCD_DPCD_REV (0x0000) +#define DPCD_MAX_LINK_RATE (0x0001) +#define DPCD_MAX_LANE_COUNT (0x0002) +#define DP_MAX_LANE_COUNT_MASK 0x1f +#define DP_TPS3_SUPPORTED (1 << 6) +#define DP_ENHANCED_FRAME_CAP (1 << 7) + +#define DPCD_LINK_BW_SET (0x0100) +#define DPCD_LANE_COUNT_SET (0x0101) + +#define DPCD_TRAINING_PATTERN_SET (0x0102) +#define DP_TRAINING_PATTERN_DISABLE 0 +#define DP_TRAINING_PATTERN_1 1 +#define DP_TRAINING_PATTERN_2 2 +#define DP_TRAINING_PATTERN_3 3 +#define DP_TRAINING_PATTERN_MASK 0x3 + +#define DPCD_TRAINING_LANE0_SET (0x0103) +#define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 +#define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 +#define DP_TRAIN_MAX_SWING_REACHED (1 << 2) +#define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) +#define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) +#define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) +#define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) + +#define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) +#define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) +#define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) +#define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) +#define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) + +#define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 +#define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) + +#define DPCD_LANE0_1_STATUS (0x0202) +#define DPCD_LANE2_3_STATUS (0x0203) +#define DP_LANE_CR_DONE (1 << 0) +#define DP_LANE_CHANNEL_EQ_DONE (1 << 1) +#define DP_LANE_SYMBOL_LOCKED (1 << 2) +#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE |\ + DP_LANE_CHANNEL_EQ_DONE |\ + DP_LANE_SYMBOL_LOCKED) + +#define DPCD_LANE_ALIGN_STATUS_UPDATED (0x0204) +#define DP_INTERLANE_ALIGN_DONE (1 << 0) +#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) +#define DP_LINK_STATUS_UPDATED (1 << 7) + +#define DPCD_ADJUST_REQUEST_LANE0_1 (0x0206) +#define DPCD_ADJUST_REQUEST_LANE2_3 (0x0207) +#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 +#define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 +#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c +#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 +#define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 +#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 +#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 +#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 + +#define DPCD_TEST_REQUEST (0x0218) +#define DPCD_TEST_RESPONSE (0x0260) +#define DPCD_TEST_EDID_CHECKSUM (0x0261) +#define DPCD_LINK_POWER_STATE (0x0600) +#define DP_SET_POWER_D0 0x1 +#define DP_SET_POWER_D3 0x2 +#define DP_SET_POWER_MASK 0x3 + +#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) +#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) +#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) + +#define STREAM_ON_TIMEOUT 100 +#define PLL_LOCK_TIMEOUT 10 +#define DP_INIT_TRIES 10 + +#define EDID_ADDR 0x50 +#define EDID_LENGTH 0x80 +#define EDID_HEADER 0x00 +#define EDID_EXTENSION_FLAG 0x7e + + +enum dpcd_request { + DPCD_READ, + DPCD_WRITE, +}; + +enum dp_irq_type { + DP_IRQ_TYPE_HP_CABLE_IN, + DP_IRQ_TYPE_HP_CABLE_OUT, + DP_IRQ_TYPE_HP_CHANGE, + DP_IRQ_TYPE_UNKNOWN, +}; + +enum color_coefficient { + COLOR_YCBCR601, + COLOR_YCBCR709 +}; + +enum dynamic_range { + VESA, + CEA +}; + +enum clock_recovery_m_value_type { + CALCULATED_M, + REGISTER_M +}; + +enum video_timing_recognition_type { + VIDEO_TIMING_FROM_CAPTURE, + VIDEO_TIMING_FROM_REGISTER +}; + +enum pattern_set { + PRBS7, + D10_2, + TRAINING_PTN1, + TRAINING_PTN2, + DP_NONE +}; + +enum color_space { + CS_RGB, + CS_YCBCR422, + CS_YCBCR444 +}; + +enum color_depth { + COLOR_6, + COLOR_8, + COLOR_10, + COLOR_12 +}; + +enum link_rate_type { + LINK_RATE_1_62GBPS = 0x06, + LINK_RATE_2_70GBPS = 0x0a +}; + +enum link_lane_count_type { + LANE_CNT1 = 1, + LANE_CNT2 = 2, + LANE_CNT4 = 4 +}; + +enum link_training_state { + LT_START, + LT_CLK_RECOVERY, + LT_EQ_TRAINING, + FINISHED, + FAILED +}; + +enum voltage_swing_level { + VOLTAGE_LEVEL_0, + VOLTAGE_LEVEL_1, + VOLTAGE_LEVEL_2, + VOLTAGE_LEVEL_3, +}; + +enum pre_emphasis_level { + PRE_EMPHASIS_LEVEL_0, + PRE_EMPHASIS_LEVEL_1, + PRE_EMPHASIS_LEVEL_2, + PRE_EMPHASIS_LEVEL_3, +}; + +enum analog_power_block { + AUX_BLOCK, + CH0_BLOCK, + CH1_BLOCK, + CH2_BLOCK, + CH3_BLOCK, + ANALOG_TOTAL, + POWER_ALL +}; + +struct link_train { + unsigned char revision; + u8 link_rate; + u8 lane_count; +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/f_rockusb.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/f_rockusb.h new file mode 100644 index 000000000..977232102 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/f_rockusb.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 + * + * Eddie Cai + */ + +#ifndef _F_ROCKUSB_H_ +#define _F_ROCKUSB_H_ +#include + +#define ROCKUSB_VERSION "0.1" + +#define ROCKUSB_INTERFACE_CLASS 0xff +#define ROCKUSB_INTERFACE_SUB_CLASS 0x06 +#define ROCKUSB_INTERFACE_PROTOCOL 0x05 + +#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0 0x0200 +#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1 0x0040 +#define TX_ENDPOINT_MAXIMUM_PACKET_SIZE 0x0040 + +#define EP_BUFFER_SIZE 4096 +/* + * EP_BUFFER_SIZE must always be an integral multiple of maxpacket size + * (64 or 512 or 1024), else we break on certain controllers like DWC3 + * that expect bulk OUT requests to be divisible by maxpacket size. + */ + +#define RKUSB_BUF_SIZE EP_BUFFER_SIZE * 2 +#define RKBLOCK_BUF_SIZE 4096 + +#define RKUSB_STATUS_IDLE 0 +#define RKUSB_STATUS_CMD 1 +#define RKUSB_STATUS_RXDATA 2 +#define RKUSB_STATUS_TXDATA 3 +#define RKUSB_STATUS_CSW 4 +#define RKUSB_STATUS_RXDATA_PREPARE 5 +#define RKUSB_STATUS_TXDATA_PREPARE 6 + +enum rkusb_command { +K_FW_TEST_UNIT_READY = 0x00, +K_FW_READ_FLASH_ID = 0x01, +K_FW_SET_DEVICE_ID = 0x02, +K_FW_TEST_BAD_BLOCK = 0x03, +K_FW_READ_10 = 0x04, +K_FW_WRITE_10 = 0x05, +K_FW_ERASE_10 = 0x06, +K_FW_WRITE_SPARE = 0x07, +K_FW_READ_SPARE = 0x08, + +K_FW_ERASE_10_FORCE = 0x0b, +K_FW_GET_VERSION = 0x0c, + +K_FW_LBA_READ_10 = 0x14, +K_FW_LBA_WRITE_10 = 0x15, +K_FW_ERASE_SYS_DISK = 0x16, +K_FW_SDRAM_READ_10 = 0x17, +K_FW_SDRAM_WRITE_10 = 0x18, +K_FW_SDRAM_EXECUTE = 0x19, +K_FW_READ_FLASH_INFO = 0x1A, +K_FW_GET_CHIP_VER = 0x1B, +K_FW_LOW_FORMAT = 0x1C, +K_FW_SET_RESET_FLAG = 0x1E, +K_FW_SPI_READ_10 = 0x21, +K_FW_SPI_WRITE_10 = 0x22, +K_FW_LBA_ERASE_10 = 0x25, + +K_FW_SESSION = 0X30, +K_FW_RESET = 0xff, +}; + +#define CBW_DIRECTION_OUT 0x00 +#define CBW_DIRECTION_IN 0x80 + +struct cmd_dispatch_info { + enum rkusb_command cmd; + /* call back function to handle rockusb command */ + void (*cb)(struct usb_ep *ep, struct usb_request *req); +}; + +/* Bulk-only data structures */ + +/* Command Block Wrapper */ +struct fsg_bulk_cb_wrap { + __le32 signature; /* Contains 'USBC' */ + u32 tag; /* Unique per command id */ + __le32 data_transfer_length; /* Size of the data */ + u8 flags; /* Direction in bit 7 */ + u8 lun; /* lun (normally 0) */ + u8 length; /* Of the CDB, <= MAX_COMMAND_SIZE */ + u8 CDB[16]; /* Command Data Block */ +}; + +#define USB_BULK_CB_WRAP_LEN 31 +#define USB_BULK_CB_SIG 0x43425355 /* Spells out USBC */ +#define USB_BULK_IN_FLAG 0x80 + +/* Command status Wrapper */ +struct bulk_cs_wrap { + __le32 signature; /* Should = 'USBS' */ + u32 tag; /* Same as original command */ + __le32 residue; /* Amount not transferred */ + u8 status; /* See below */ +}; + +#define USB_BULK_CS_WRAP_LEN 13 +#define USB_BULK_CS_SIG 0x53425355 /* Spells out 'USBS' */ +#define USB_STATUS_PASS 0 +#define USB_STATUS_FAIL 1 +#define USB_STATUS_PHASE_ERROR 2 + +#define CSW_GOOD 0x00 +#define CSW_FAIL 0x01 + +struct f_rockusb { + struct usb_function usb_function; + struct usb_ep *in_ep, *out_ep; + struct usb_request *in_req, *out_req; + char *dev_type; + unsigned int dev_index; + unsigned int tag; + unsigned int lba; + unsigned int dl_size; + unsigned int dl_bytes; + unsigned int ul_size; + unsigned int ul_bytes; + struct blk_desc *desc; + int reboot_flag; + void *buf; + void *buf_head; +}; + +/* init rockusb device, tell rockusb which device you want to read/write*/ +void rockusb_dev_init(char *dev_type, int dev_index); +#endif /* _F_ROCKUSB_H_ */ + diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/gpio.h new file mode 100644 index 000000000..1aaec5fae --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/gpio.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Google, Inc + */ + +#ifndef _ASM_ARCH_GPIO_H +#define _ASM_ARCH_GPIO_H + +struct rockchip_gpio_regs { + u32 swport_dr; + u32 swport_ddr; + u32 reserved0[(0x30 - 0x08) / 4]; + u32 inten; + u32 intmask; + u32 inttype_level; + u32 int_polarity; + u32 int_status; + u32 int_rawstatus; + u32 debounce; + u32 porta_eoi; + u32 ext_port; + u32 reserved1[(0x60 - 0x54) / 4]; + u32 ls_sync; +}; +check_member(rockchip_gpio_regs, ls_sync, 0x60); + +enum gpio_pu_pd { + GPIO_PULL_NORMAL = 0, + GPIO_PULL_UP, + GPIO_PULL_DOWN, + GPIO_PULL_REPEAT, +}; + +/* These defines are only used by spl_gpio.h */ +enum { + /* Banks have 8 GPIOs, so 3 bits, and there are 4 banks, so 2 bits */ + GPIO_BANK_SHIFT = 3, + GPIO_BANK_MASK = 3 << GPIO_BANK_SHIFT, + + GPIO_OFFSET_MASK = 0x1f, +}; + +#define GPIO(bank, offset) ((bank) << GPIO_BANK_SHIFT | (offset)) + +enum gpio_bank_t { + BANK_A = 0, + BANK_B, + BANK_C, + BANK_D, +}; + +enum gpio_dir_t { + GPIO_INPUT = 0, + GPIO_OUTPUT, +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_px30.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_px30.h new file mode 100644 index 000000000..d51e29b19 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_px30.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + */ +#ifndef _ASM_ARCH_GRF_px30_H +#define _ASM_ARCH_GRF_px30_H + +struct px30_grf { + unsigned int gpio1al_iomux; + unsigned int gpio1ah_iomux; + unsigned int gpio1bl_iomux; + unsigned int gpio1bh_iomux; + unsigned int gpio1cl_iomux; + unsigned int gpio1ch_iomux; + unsigned int gpio1dl_iomux; + unsigned int gpio1dh_iomux; + + unsigned int gpio2al_iomux; + unsigned int gpio2ah_iomux; + unsigned int gpio2bl_iomux; + unsigned int gpio2bh_iomux; + unsigned int gpio2cl_iomux; + unsigned int gpio2ch_iomux; + unsigned int gpio2dl_iomux; + unsigned int gpio2dh_iomux; + + unsigned int gpio3al_iomux; + unsigned int gpio3ah_iomux; + unsigned int gpio3bl_iomux; + unsigned int gpio3bh_iomux; + unsigned int gpio3cl_iomux; + unsigned int gpio3ch_iomux; + unsigned int gpio3dl_iomux; + unsigned int gpio3dh_iomux; + + unsigned int gpio1a_p; + unsigned int gpio1b_p; + unsigned int gpio1c_p; + unsigned int gpio1d_p; + unsigned int gpio2a_p; + unsigned int gpio2b_p; + unsigned int gpio2c_p; + unsigned int gpio2d_p; + unsigned int gpio3a_p; + unsigned int gpio3b_p; + unsigned int gpio3c_p; + unsigned int gpio3d_p; + unsigned int gpio1a_sr; + unsigned int gpio1b_sr; + unsigned int gpio1c_sr; + unsigned int gpio1d_sr; + unsigned int gpio2a_sr; + unsigned int gpio2b_sr; + unsigned int gpio2c_sr; + unsigned int gpio2d_sr; + unsigned int gpio3a_sr; + unsigned int gpio3b_sr; + unsigned int gpio3c_sr; + unsigned int gpio3d_sr; + unsigned int gpio1a_smt; + unsigned int gpio1b_smt; + unsigned int gpio1c_smt; + unsigned int gpio1d_smt; + unsigned int gpio2a_smt; + unsigned int gpio2b_smt; + unsigned int gpio2c_smt; + unsigned int gpio2d_smt; + unsigned int gpio3a_smt; + unsigned int gpio3b_smt; + unsigned int gpio3c_smt; + unsigned int gpio3d_smt; + unsigned int gpio1a_e; + unsigned int gpio1b_e; + unsigned int gpio1c_e; + unsigned int gpio1d_e; + unsigned int gpio2a_e; + unsigned int gpio2b_e; + unsigned int gpio2c_e; + unsigned int gpio2d_e; + unsigned int gpio3a_e; + unsigned int gpio3b_e; + unsigned int gpio3c_e; + unsigned int gpio3d_e; + + unsigned int reserved0[(0x180 - 0x11C) / 4 - 1]; + unsigned int io_vsel; + unsigned int iofunc_con0; + unsigned int reserved1[(0x400 - 0x184) / 4 - 1]; + unsigned int soc_con[6]; + unsigned int reserved2[(0x480 - 0x414) / 4 - 1]; + unsigned int soc_status0; + unsigned int reserved3[(0x500 - 0x480) / 4 - 1]; + unsigned int cpu_con[3]; + unsigned int reserved4[5]; + unsigned int cpu_status[2]; + unsigned int reserved5[2]; + unsigned int soc_noc_con[2]; + unsigned int reserved6[6]; + unsigned int ddr_bankhash[4]; + unsigned int reserved7[(0x700 - 0x55c) / 4 - 1]; + unsigned int host0_con[2]; + unsigned int reserved8[(0x880 - 0x704) / 4 - 1]; + unsigned int otg_con3; + unsigned int reserved9[3]; + unsigned int host0_status4; + unsigned int reserved10[(0x904 - 0x890) / 4 - 1]; + unsigned int mac_con1; +}; + +check_member(px30_grf, mac_con1, 0x904); + +struct px30_pmugrf { + unsigned int gpio0al_iomux; + unsigned int gpio0bl_iomux; + unsigned int gpio0cl_iomux; + unsigned int gpio0dl_iomux; + unsigned int gpio0a_p; + unsigned int gpio0b_p; + unsigned int gpio0c_p; + unsigned int gpio0d_p; + unsigned int gpio0a_e; + unsigned int gpio0b_e; + unsigned int gpio0c_e; + unsigned int gpio0d_e; + unsigned int gpio0l_sr; + unsigned int gpio0h_sr; + unsigned int gpio0l_smt; + unsigned int gpio0h_smt; + unsigned int reserved1[(0x100 - 0x3c) / 4 - 1]; + unsigned int soc_con[4]; + unsigned int reserved2[(0x180 - 0x10c) / 4 - 1]; + unsigned int pvtm_con[2]; + unsigned int reserved3[2]; + unsigned int pvtm_status[2]; + unsigned int reserved4[(0x200 - 0x194) / 4 - 1]; + unsigned int os_reg[12]; + unsigned int reset_function_status; +}; + +check_member(px30_pmugrf, reset_function_status, 0x230); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3036.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3036.h new file mode 100644 index 000000000..08348d822 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3036.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + */ +#ifndef _ASM_ARCH_GRF_RK3036_H +#define _ASM_ARCH_GRF_RK3036_H + +struct rk3036_grf { + unsigned int reserved[0x2a]; + unsigned int gpio0a_iomux; + unsigned int gpio0b_iomux; + unsigned int gpio0c_iomux; + unsigned int gpio0d_iomux; + + unsigned int gpio1a_iomux; + unsigned int gpio1b_iomux; + unsigned int gpio1c_iomux; + unsigned int gpio1d_iomux; + + unsigned int gpio2a_iomux; + unsigned int gpio2b_iomux; + unsigned int gpio2c_iomux; + unsigned int gpio2d_iomux; + + unsigned int reserved2[0x0a]; + unsigned int gpiods; + unsigned int reserved3[0x05]; + unsigned int gpio0l_pull; + unsigned int gpio0h_pull; + unsigned int gpio1l_pull; + unsigned int gpio1h_pull; + unsigned int gpio2l_pull; + unsigned int gpio2h_pull; + unsigned int reserved4[4]; + unsigned int soc_con0; + unsigned int soc_con1; + unsigned int soc_con2; + unsigned int soc_status0; + unsigned int reserved5; + unsigned int soc_con3; + unsigned int reserved6; + unsigned int dmac_con0; + unsigned int dmac_con1; + unsigned int dmac_con2; + unsigned int reserved7[5]; + unsigned int uoc0_con5; + unsigned int reserved8[4]; + unsigned int uoc1_con4; + unsigned int uoc1_con5; + unsigned int reserved9; + unsigned int ddrc_stat; + unsigned int uoc_con6; + unsigned int soc_status1; + unsigned int cpu_con0; + unsigned int cpu_con1; + unsigned int cpu_con2; + unsigned int cpu_con3; + unsigned int reserved10; + unsigned int reserved11; + unsigned int cpu_status0; + unsigned int cpu_status1; + unsigned int os_reg[8]; + unsigned int reserved12[6]; + unsigned int dll_con[4]; + unsigned int dll_status[4]; + unsigned int dfi_wrnum; + unsigned int dfi_rdnum; + unsigned int dfi_actnum; + unsigned int dfi_timerval; + unsigned int nfi_fifo[4]; + unsigned int reserved13[0x10]; + unsigned int usbphy0_con[8]; + unsigned int usbphy1_con[8]; + unsigned int reserved14[0x10]; + unsigned int chip_tag; + unsigned int sdmmc_det_cnt; +}; +check_member(rk3036_grf, sdmmc_det_cnt, 0x304); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3128.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3128.h new file mode 100644 index 000000000..fe07d69b4 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3128.h @@ -0,0 +1,548 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ +#ifndef _ASM_ARCH_GRF_RK3128_H +#define _ASM_ARCH_GRF_RK3128_H + +struct rk3128_grf { + unsigned int reserved[0x2a]; + unsigned int gpio0a_iomux; + unsigned int gpio0b_iomux; + unsigned int gpio0c_iomux; + unsigned int gpio0d_iomux; + unsigned int gpio1a_iomux; + unsigned int gpio1b_iomux; + unsigned int gpio1c_iomux; + unsigned int gpio1d_iomux; + unsigned int gpio2a_iomux; + unsigned int gpio2b_iomux; + unsigned int gpio2c_iomux; + unsigned int gpio2d_iomux; + unsigned int gpio3a_iomux; + unsigned int gpio3b_iomux; + unsigned int gpio3c_iomux; + unsigned int gpio3d_iomux; + unsigned int gpio2c_iomux2; + unsigned int grf_cif_iomux; + unsigned int grf_cif_iomux1; + unsigned int reserved1[(0x118 - 0xf0) / 4 - 1]; + unsigned int gpio0l_pull; + unsigned int gpio0h_pull; + unsigned int gpio1l_pull; + unsigned int gpio1h_pull; + unsigned int gpio2l_pull; + unsigned int gpio2h_pull; + unsigned int gpio3l_pull; + unsigned int gpio3h_pull; + unsigned int reserved2; + unsigned int soc_con0; + unsigned int soc_con1; + unsigned int soc_con2; + unsigned int soc_status0; + unsigned int reserved3[6]; + unsigned int mac_con0; + unsigned int mac_con1; + unsigned int reserved4[4]; + unsigned int uoc0_con0; + unsigned int reserved5; + unsigned int uoc1_con1; + unsigned int uoc1_con2; + unsigned int uoc1_con3; + unsigned int uoc1_con4; + unsigned int uoc1_con5; + unsigned int reserved6; + unsigned int ddrc_stat; + unsigned int reserved9; + unsigned int soc_status1; + unsigned int cpu_con0; + unsigned int cpu_con1; + unsigned int cpu_con2; + unsigned int cpu_con3; + unsigned int reserved10; + unsigned int reserved11; + unsigned int cpu_status0; + unsigned int cpu_status1; + unsigned int os_reg[8]; + unsigned int reserved12[(0x280 - 0x1e4) / 4 - 1]; + unsigned int usbphy0_con[8]; + unsigned int usbphy1_con[8]; + unsigned int uoc_status0; + unsigned int reserved13[(0x300 - 0x2c0) / 4 - 1]; + unsigned int chip_tag; + unsigned int sdmmc_det_cnt; +}; +check_member(rk3128_grf, sdmmc_det_cnt, 0x304); + +struct rk3128_pmu { + unsigned int wakeup_cfg; + unsigned int pwrdn_con; + unsigned int pwrdn_st; + unsigned int idle_req; + unsigned int idle_st; + unsigned int pwrmode_con; + unsigned int pwr_state; + unsigned int osc_cnt; + unsigned int core_pwrdwn_cnt; + unsigned int core_pwrup_cnt; + unsigned int sft_con; + unsigned int ddr_sref_st; + unsigned int int_con; + unsigned int int_st; + unsigned int sys_reg[4]; +}; +check_member(rk3128_pmu, int_st, 0x34); + +/* GRF_GPIO0A_IOMUX */ +enum { + GPIO0A7_SHIFT = 14, + GPIO0A7_MASK = 3 << GPIO0A7_SHIFT, + GPIO0A7_GPIO = 0, + GPIO0A7_I2C3_SDA, + + GPIO0A6_SHIFT = 12, + GPIO0A6_MASK = 3 << GPIO0A6_SHIFT, + GPIO0A6_GPIO = 0, + GPIO0A6_I2C3_SCL, + + GPIO0A3_SHIFT = 6, + GPIO0A3_MASK = 3 << GPIO0A3_SHIFT, + GPIO0A3_GPIO = 0, + GPIO0A3_I2C1_SDA, + + GPIO0A2_SHIFT = 4, + GPIO0A2_MASK = 1 << GPIO0A2_SHIFT, + GPIO0A2_GPIO = 0, + GPIO0A2_I2C1_SCL, + + GPIO0A1_SHIFT = 2, + GPIO0A1_MASK = 1 << GPIO0A1_SHIFT, + GPIO0A1_GPIO = 0, + GPIO0A1_I2C0_SDA, + + GPIO0A0_SHIFT = 0, + GPIO0A0_MASK = 1 << GPIO0A0_SHIFT, + GPIO0A0_GPIO = 0, + GPIO0A0_I2C0_SCL, +}; + +/* GRF_GPIO0B_IOMUX */ +enum { + GPIO0B6_SHIFT = 12, + GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, + GPIO0B6_GPIO = 0, + GPIO0B6_I2S_SDI, + GPIO0B6_SPI_CSN0, + + GPIO0B5_SHIFT = 10, + GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, + GPIO0B5_GPIO = 0, + GPIO0B5_I2S_SDO, + GPIO0B5_SPI_RXD, + + GPIO0B4_SHIFT = 8, + GPIO0B4_MASK = 1 << GPIO0B4_SHIFT, + GPIO0B4_GPIO = 0, + GPIO0B4_I2S_LRCKTX, + + GPIO0B3_SHIFT = 6, + GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, + GPIO0B3_GPIO = 0, + GPIO0B3_I2S_LRCKRX, + GPIO0B3_SPI_TXD, + + GPIO0B1_SHIFT = 2, + GPIO0B1_MASK = 3, + GPIO0B1_GPIO = 0, + GPIO0B1_I2S_SCLK, + GPIO0B1_SPI_CLK, + + GPIO0B0_SHIFT = 0, + GPIO0B0_MASK = 3, + GPIO0B0_GPIO = 0, + GPIO0B0_I2S1_MCLK, +}; + +/* GRF_GPIO0D_IOMUX */ +enum { + GPIO0D4_SHIFT = 8, + GPIO0D4_MASK = 1 << GPIO0D4_SHIFT, + GPIO0D4_GPIO = 0, + GPIO0D4_PWM2, + + GPIO0D3_SHIFT = 6, + GPIO0D3_MASK = 1 << GPIO0D3_SHIFT, + GPIO0D3_GPIO = 0, + GPIO0D3_PWM1, + + GPIO0D2_SHIFT = 4, + GPIO0D2_MASK = 1 << GPIO0D2_SHIFT, + GPIO0D2_GPIO = 0, + GPIO0D2_PWM0, + + GPIO0D1_SHIFT = 2, + GPIO0D1_MASK = 1 << GPIO0D1_SHIFT, + GPIO0D1_GPIO = 0, + GPIO0D1_UART2_CTSN, + + GPIO0D0_SHIFT = 0, + GPIO0D0_MASK = 3 << GPIO0D0_SHIFT, + GPIO0D0_GPIO = 0, + GPIO0D0_UART2_RTSN, + GPIO0D0_PMIC_SLEEP, +}; + +/* GRF_GPIO1A_IOMUX */ +enum { + GPIO1A5_SHIFT = 10, + GPIO1A5_MASK = 3 << GPIO1A5_SHIFT, + GPIO1A5_GPIO = 0, + GPIO1A5_I2S_SDI, + GPIO1A5_SDMMC_DATA3, + + GPIO1A4_SHIFT = 8, + GPIO1A4_MASK = 3 << GPIO1A4_SHIFT, + GPIO1A4_GPIO = 0, + GPIO1A4_I2S_SD0, + GPIO1A4_SDMMC_DATA2, + + GPIO1A3_SHIFT = 6, + GPIO1A3_MASK = 1 << GPIO1A3_SHIFT, + GPIO1A3_GPIO = 0, + GPIO1A3_I2S_LRCKTX, + + GPIO1A2_SHIFT = 4, + GPIO1A2_MASK = 3 << GPIO1A2_SHIFT, + GPIO1A2_GPIO = 0, + GPIO1A2_I2S_LRCKRX, + GPIO1A2_SDMMC_DATA1, + + GPIO1A1_SHIFT = 2, + GPIO1A1_MASK = 3 << GPIO1A1_SHIFT, + GPIO1A1_GPIO = 0, + GPIO1A1_I2S_SCLK, + GPIO1A1_SDMMC_DATA0, + GPIO1A1_PMIC_SLEEP, + + GPIO1A0_SHIFT = 0, + GPIO1A0_MASK = 3, + GPIO1A0_GPIO = 0, + GPIO1A0_I2S_MCLK, + GPIO1A0_SDMMC_CLKOUT, + GPIO1A0_XIN32K, + +}; + +/* GRF_GPIO1B_IOMUX */ +enum { + GPIO1B7_SHIFT = 14, + GPIO1B7_MASK = 1 << GPIO1B7_SHIFT, + GPIO1B7_GPIO = 0, + GPIO1B7_MMC0_CMD, + + GPIO1B6_SHIFT = 12, + GPIO1B6_MASK = 1 << GPIO1B6_SHIFT, + GPIO1B6_GPIO = 0, + GPIO1B6_MMC_PWREN, + + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, + GPIO1B2_GPIO = 0, + GPIO1B2_SPI_RXD, + GPIO1B2_UART1_SIN, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, + GPIO1B1_GPIO = 0, + GPIO1B1_SPI_TXD, + GPIO1B1_UART1_SOUT, + + GPIO1B0_SHIFT = 0, + GPIO1B0_MASK = 3 << GPIO1B0_SHIFT, + GPIO1B0_GPIO = 0, + GPIO1B0_SPI_CLK, + GPIO1B0_UART1_CTSN +}; + +/* GRF_GPIO1C_IOMUX */ +enum { + GPIO1C6_SHIFT = 12, + GPIO1C6_MASK = 3 << GPIO1C6_SHIFT, + GPIO1C6_GPIO = 0, + GPIO1C6_NAND_CS2, + GPIO1C6_EMMC_CMD, + + GPIO1C5_SHIFT = 10, + GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, + GPIO1C5_GPIO = 0, + GPIO1C5_MMC0_D3, + GPIO1C5_JTAG_TMS, + + GPIO1C4_SHIFT = 8, + GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, + GPIO1C4_GPIO = 0, + GPIO1C4_MMC0_D2, + GPIO1C4_JTAG_TCK, + + GPIO1C3_SHIFT = 6, + GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, + GPIO1C3_GPIO = 0, + GPIO1C3_MMC0_D1, + GPIO1C3_UART2_RX, + + GPIO1C2_SHIFT = 4, + GPIO1C2_MASK = 3 << GPIO1C2_SHIFT, + GPIO1C2_GPIO = 0, + GPIO1C2_MMC0_D0, + GPIO1C2_UART2_TX, + + GPIO1C1_SHIFT = 2, + GPIO1C1_MASK = 1 << GPIO1C1_SHIFT, + GPIO1C1_GPIO = 0, + GPIO1C1_MMC0_DETN, + + GPIO1C0_SHIFT = 0, + GPIO1C0_MASK = 1 << GPIO1C0_SHIFT, + GPIO1C0_GPIO = 0, + GPIO1C0_MMC0_CLKOUT, +}; + +/* GRF_GPIO1D_IOMUX */ +enum { + GPIO1D7_SHIFT = 14, + GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, + GPIO1D7_GPIO = 0, + GPIO1D7_NAND_D7, + GPIO1D7_EMMC_D7, + GPIO1D7_SPI_CSN1, + + GPIO1D6_SHIFT = 12, + GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, + GPIO1D6_GPIO = 0, + GPIO1D6_NAND_D6, + GPIO1D6_EMMC_D6, + GPIO1D6_SPI_CSN0, + + GPIO1D5_SHIFT = 10, + GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, + GPIO1D5_GPIO = 0, + GPIO1D5_NAND_D5, + GPIO1D5_EMMC_D5, + GPIO1D5_SPI_TXD1, + + GPIO1D4_SHIFT = 8, + GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, + GPIO1D4_GPIO = 0, + GPIO1D4_NAND_D4, + GPIO1D4_EMMC_D4, + GPIO1D4_SPI_RXD1, + + GPIO1D3_SHIFT = 6, + GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, + GPIO1D3_GPIO = 0, + GPIO1D3_NAND_D3, + GPIO1D3_EMMC_D3, + GPIO1D3_SFC_SIO3, + + GPIO1D2_SHIFT = 4, + GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, + GPIO1D2_GPIO = 0, + GPIO1D2_NAND_D2, + GPIO1D2_EMMC_D2, + GPIO1D2_SFC_SIO2, + + GPIO1D1_SHIFT = 2, + GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, + GPIO1D1_GPIO = 0, + GPIO1D1_NAND_D1, + GPIO1D1_EMMC_D1, + GPIO1D1_SFC_SIO1, + + GPIO1D0_SHIFT = 0, + GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, + GPIO1D0_GPIO = 0, + GPIO1D0_NAND_D0, + GPIO1D0_EMMC_D0, + GPIO1D0_SFC_SIO0, +}; + +/* GRF_GPIO2A_IOMUX */ +enum { + GPIO2A7_SHIFT = 14, + GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, + GPIO2A7_GPIO = 0, + GPIO2A7_NAND_DQS, + GPIO2A7_EMMC_CLKOUT, + + GPIO2A6_SHIFT = 12, + GPIO2A6_MASK = 1 << GPIO2A6_SHIFT, + GPIO2A6_GPIO = 0, + GPIO2A6_NAND_CS0, + + GPIO2A5_SHIFT = 10, + GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, + GPIO2A5_GPIO = 0, + GPIO2A5_NAND_WP, + GPIO2A5_EMMC_PWREN, + + GPIO2A4_SHIFT = 8, + GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, + GPIO2A4_GPIO = 0, + GPIO2A4_NAND_RDY, + GPIO2A4_EMMC_CMD, + GPIO2A3_SFC_CLK, + + GPIO2A3_SHIFT = 6, + GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, + GPIO2A3_GPIO = 0, + GPIO2A3_NAND_RDN, + GPIO2A4_SFC_CSN1, + + GPIO2A2_SHIFT = 4, + GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, + GPIO2A2_GPIO = 0, + GPIO2A2_NAND_WRN, + GPIO2A4_SFC_CSN0, + + GPIO2A1_SHIFT = 2, + GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, + GPIO2A1_GPIO = 0, + GPIO2A1_NAND_CLE, + GPIO2A1_EMMC_CLKOUT, + + GPIO2A0_SHIFT = 0, + GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, + GPIO2A0_GPIO = 0, + GPIO2A0_NAND_ALE, + GPIO2A0_SPI_CLK, +}; + +/* GRF_GPIO2B_IOMUX */ +enum { + GPIO2B7_SHIFT = 14, + GPIO2B7_MASK = 3 << GPIO2B7_SHIFT, + GPIO2B7_GPIO = 0, + GPIO2B7_LCDC0_D13, + GPIO2B7_EBC_SDCE5, + GPIO2B7_GMAC_RXER, + + GPIO2B6_SHIFT = 12, + GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, + GPIO2B6_GPIO = 0, + GPIO2B6_LCDC0_D12, + GPIO2B6_EBC_SDCE4, + GPIO2B6_GMAC_CLK, + + GPIO2B5_SHIFT = 10, + GPIO2B5_MASK = 3 << GPIO2B5_SHIFT, + GPIO2B5_GPIO = 0, + GPIO2B5_LCDC0_D11, + GPIO2B5_EBC_SDCE3, + GPIO2B5_GMAC_TXEN, + + GPIO2B4_SHIFT = 8, + GPIO2B4_MASK = 3 << GPIO2B4_SHIFT, + GPIO2B4_GPIO = 0, + GPIO2B4_LCDC0_D10, + GPIO2B4_EBC_SDCE2, + GPIO2B4_GMAC_MDIO, + + GPIO2B3_SHIFT = 6, + GPIO2B3_MASK = 3 << GPIO2B3_SHIFT, + GPIO2B3_GPIO = 0, + GPIO2B3_LCDC0_DEN, + GPIO2B3_EBC_GDCLK, + GPIO2B3_GMAC_RXCLK, + + GPIO2B2_SHIFT = 4, + GPIO2B2_MASK = 3 << GPIO2B2_SHIFT, + GPIO2B2_GPIO = 0, + GPIO2B2_LCDC0_VSYNC, + GPIO2B2_EBC_SDOE, + GPIO2B2_GMAC_CRS, + + GPIO2B1_SHIFT = 2, + GPIO2B1_MASK = 3 << GPIO2B1_SHIFT, + GPIO2B1_GPIO = 0, + GPIO2B1_LCDC0_HSYNC, + GPIO2B1_EBC_SDLE, + GPIO2B1_GMAC_TXCLK, + + GPIO2B0_SHIFT = 0, + GPIO2B0_MASK = 3 << GPIO2B0_SHIFT, + GPIO2B0_GPIO = 0, + GPIO2B0_LCDC0_DCLK, + GPIO2B0_EBC_SDCLK, + GPIO2B0_GMAC_RXDV, +}; + +/* GRF_GPIO2C_IOMUX */ +enum { + GPIO2C3_SHIFT = 6, + GPIO2C3_MASK = 3 << GPIO2C3_SHIFT, + GPIO2C3_GPIO = 0, + GPIO2C3_LCDC0_D17, + GPIO2C3_EBC_GDPWR0, + GPIO2C3_GMAC_TXD0, + + GPIO2C2_SHIFT = 4, + GPIO2C2_MASK = 3 << GPIO2C2_SHIFT, + GPIO2C2_GPIO = 0, + GPIO2C2_LCDC0_D16, + GPIO2C2_EBC_GDSP, + GPIO2C2_GMAC_TXD1, + + GPIO2C1_SHIFT = 2, + GPIO2C1_MASK = 3 << GPIO2C1_SHIFT, + GPIO2C1_GPIO = 0, + GPIO2C1_LCDC0_D15, + GPIO2C1_EBC_GDOE, + GPIO2C1_GMAC_RXD0, + + GPIO2C0_SHIFT = 0, + GPIO2C0_MASK = 3 << GPIO2C0_SHIFT, + GPIO2C0_GPIO = 0, + GPIO2C0_LCDC0_D14, + GPIO2C0_EBC_VCOM, + GPIO2C0_GMAC_RXD1, +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2D6_SHIFT = 12, + GPIO2D6_MASK = 3 << GPIO2D6_SHIFT, + GPIO2D6_GPIO = 0, + GPIO2D6_LCDC0_D22, + GPIO2D6_GMAC_COL = 4, + + GPIO2D1_SHIFT = 2, + GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, + GPIO2D1_GPIO = 0, + GPIO2D1_GMAC_MDC = 3, +}; + +/* GRF_GPIO2C_IOMUX2 */ +enum { + GPIO2C7_SHIFT = 12, + GPIO2C7_MASK = 7 << GPIO2C7_SHIFT, + GPIO2C7_GPIO = 0, + GPIO2C7_GMAC_TXD3 = 4, + + GPIO2C6_SHIFT = 12, + GPIO2C6_MASK = 7 << GPIO2C6_SHIFT, + GPIO2C6_GPIO = 0, + GPIO2C6_GMAC_TXD2 = 4, + + GPIO2C5_SHIFT = 4, + GPIO2C5_MASK = 7 << GPIO2C5_SHIFT, + GPIO2C5_GPIO = 0, + GPIO2C5_I2C2_SCL = 3, + GPIO2C5_GMAC_RXD2, + + GPIO2C4_SHIFT = 0, + GPIO2C4_MASK = 7 << GPIO2C4_SHIFT, + GPIO2C4_GPIO = 0, + GPIO2C4_I2C2_SDA = 3, + GPIO2C4_GMAC_RXD2, +}; +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3188.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3188.h new file mode 100644 index 000000000..d05197670 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3188.h @@ -0,0 +1,250 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2016 Heiko Stuebner + */ + +#ifndef _ASM_ARCH_GRF_RK3188_H +#define _ASM_ARCH_GRF_RK3188_H + +struct rk3188_grf_gpio_lh { + u32 l; + u32 h; +}; + +struct rk3188_grf { + struct rk3188_grf_gpio_lh gpio_dir[4]; + struct rk3188_grf_gpio_lh gpio_do[4]; + struct rk3188_grf_gpio_lh gpio_en[4]; + + u32 reserved[2]; + u32 gpio0c_iomux; + u32 gpio0d_iomux; + + u32 gpio1a_iomux; + u32 gpio1b_iomux; + u32 gpio1c_iomux; + u32 gpio1d_iomux; + + u32 gpio2a_iomux; + u32 gpio2b_iomux; + u32 gpio2c_iomux; + u32 gpio2d_iomux; + + u32 gpio3a_iomux; + u32 gpio3b_iomux; + u32 gpio3c_iomux; + u32 gpio3d_iomux; + + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_status0; + + u32 busdmac_con[3]; + u32 peridmac_con[4]; + + u32 cpu_con[6]; + u32 reserved0[2]; + + u32 ddrc_con0; + u32 ddrc_stat; + + u32 io_con[5]; + u32 soc_status1; + + u32 uoc0_con[4]; + u32 uoc1_con[4]; + u32 uoc2_con[2]; + u32 reserved1; + u32 uoc3_con[2]; + u32 hsic_stat; + u32 os_reg[8]; + + u32 gpio0_p[3]; + u32 gpio1_p[3][4]; + + u32 flash_data_p; + u32 flash_cmd_p; +}; +check_member(rk3188_grf, flash_cmd_p, 0x01a4); + +/* GRF_SOC_CON0 */ +enum { + HSADC_CLK_DIR_SHIFT = 15, + HSADC_CLK_DIR_MASK = 1, + + HSADC_SEL_SHIFT = 14, + HSADC_SEL_MASK = 1, + + NOC_REMAP_SHIFT = 12, + NOC_REMAP_MASK = 1, + + EMMC_FLASH_SEL_SHIFT = 11, + EMMC_FLASH_SEL_MASK = 1, + + TZPC_REVISION_SHIFT = 7, + TZPC_REVISION_MASK = 0xf, + + L2CACHE_ACC_SHIFT = 5, + L2CACHE_ACC_MASK = 3, + + L2RD_WAIT_SHIFT = 3, + L2RD_WAIT_MASK = 3, + + IMEMRD_WAIT_SHIFT = 1, + IMEMRD_WAIT_MASK = 3, +}; + +/* GRF_SOC_CON1 */ +enum { + RKI2C4_SEL_SHIFT = 15, + RKI2C4_SEL_MASK = 1, + + RKI2C3_SEL_SHIFT = 14, + RKI2C3_SEL_MASK = 1, + + RKI2C2_SEL_SHIFT = 13, + RKI2C2_SEL_MASK = 1, + + RKI2C1_SEL_SHIFT = 12, + RKI2C1_SEL_MASK = 1, + + RKI2C0_SEL_SHIFT = 11, + RKI2C0_SEL_MASK = 1, + + VCODEC_SEL_SHIFT = 10, + VCODEC_SEL_MASK = 1, + + PERI_EMEM_PAUSE_SHIFT = 9, + PERI_EMEM_PAUSE_MASK = 1, + + PERI_USB_PAUSE_SHIFT = 8, + PERI_USB_PAUSE_MASK = 1, + + SMC_MUX_MODE_0_SHIFT = 6, + SMC_MUX_MODE_0_MASK = 1, + + SMC_SRAM_MW_0_SHIFT = 4, + SMC_SRAM_MW_0_MASK = 3, + + SMC_REMAP_0_SHIFT = 3, + SMC_REMAP_0_MASK = 1, + + SMC_A_GT_M0_SYNC_SHIFT = 2, + SMC_A_GT_M0_SYNC_MASK = 1, + + EMAC_SPEED_SHIFT = 1, + EMAC_SPEEC_MASK = 1, + + EMAC_MODE_SHIFT = 0, + EMAC_MODE_MASK = 1, +}; + +/* GRF_SOC_CON2 */ +enum { + SDIO_CLK_OUT_SR_SHIFT = 15, + SDIO_CLK_OUT_SR_MASK = 1, + + MEM_EMA_L2C_SHIFT = 11, + MEM_EMA_L2C_MASK = 7, + + MEM_EMA_A9_SHIFT = 8, + MEM_EMA_A9_MASK = 7, + + MSCH4_MAINDDR3_SHIFT = 7, + MSCH4_MAINDDR3_MASK = 1, + MSCH4_MAINDDR3_DDR3 = 1, + + EMAC_NEWRCV_EN_SHIFT = 6, + EMAC_NEWRCV_EN_MASK = 1, + + SW_ADDR15_EN_SHIFT = 5, + SW_ADDR15_EN_MASK = 1, + + SW_ADDR16_EN_SHIFT = 4, + SW_ADDR16_EN_MASK = 1, + + SW_ADDR17_EN_SHIFT = 3, + SW_ADDR17_EN_MASK = 1, + + BANK2_TO_RANK_EN_SHIFT = 2, + BANK2_TO_RANK_EN_MASK = 1, + + RANK_TO_ROW15_EN_SHIFT = 1, + RANK_TO_ROW15_EN_MASK = 1, + + UPCTL_C_ACTIVE_IN_SHIFT = 0, + UPCTL_C_ACTIVE_IN_MASK = 1, + UPCTL_C_ACTIVE_IN_MAY = 0, + UPCTL_C_ACTIVE_IN_WILL, +}; + +/* GRF_DDRC_CON0 */ +enum { + DDR_16BIT_EN_SHIFT = 15, + DDR_16BIT_EN_MASK = 1, + + DTO_LB_SHIFT = 11, + DTO_LB_MASK = 3, + + DTO_TE_SHIFT = 9, + DTO_TE_MASK = 3, + + DTO_PDR_SHIFT = 7, + DTO_PDR_MASK = 3, + + DTO_PDD_SHIFT = 5, + DTO_PDD_MASK = 3, + + DTO_IOM_SHIFT = 3, + DTO_IOM_MASK = 3, + + DTO_OE_SHIFT = 1, + DTO_OE_MASK = 3, + + ATO_AE_SHIFT = 0, + ATO_AE_MASK = 1, +}; + +/* GRF_UOC_CON0 */ +enum { + SIDDQ_SHIFT = 13, + SIDDQ_MASK = 1 << SIDDQ_SHIFT, + + BYPASSSEL_SHIFT = 9, + BYPASSSEL_MASK = 1 << BYPASSSEL_SHIFT, + + BYPASSDMEN_SHIFT = 8, + BYPASSDMEN_MASK = 1 << BYPASSDMEN_SHIFT, + + UOC_DISABLE_SHIFT = 4, + UOC_DISABLE_MASK = 1 << UOC_DISABLE_SHIFT, + + COMMON_ON_N_SHIFT = 0, + COMMON_ON_N_MASK = 1 << COMMON_ON_N_SHIFT, +}; + +/* GRF_UOC_CON2 */ +enum { + SOFT_CON_SEL_SHIFT = 2, + SOFT_CON_SEL_MASK = 1 << SOFT_CON_SEL_SHIFT, +}; + +/* GRF_UOC0_CON3 */ +enum { + TERMSEL_FULLSPEED_SHIFT = 5, + TERMSEL_FULLSPEED_MASK = 1 << TERMSEL_FULLSPEED_SHIFT, + + XCVRSELECT_SHIFT = 3, + XCVRSELECT_FSTRANSC = 1, + XCVRSELECT_MASK = 3 << XCVRSELECT_SHIFT, + + OPMODE_SHIFT = 1, + OPMODE_NODRIVING = 1, + OPMODE_MASK = 3 << OPMODE_SHIFT, + + SUSPENDN_SHIFT = 0, + SUSPENDN_MASK = 1 << SUSPENDN_SHIFT, +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk322x.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk322x.h new file mode 100644 index 000000000..5f4d9d822 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk322x.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + */ +#ifndef _ASM_ARCH_GRF_RK322X_H +#define _ASM_ARCH_GRF_RK322X_H + +struct rk322x_grf { + unsigned int gpio0a_iomux; + unsigned int gpio0b_iomux; + unsigned int gpio0c_iomux; + unsigned int gpio0d_iomux; + + unsigned int gpio1a_iomux; + unsigned int gpio1b_iomux; + unsigned int gpio1c_iomux; + unsigned int gpio1d_iomux; + + unsigned int gpio2a_iomux; + unsigned int gpio2b_iomux; + unsigned int gpio2c_iomux; + unsigned int gpio2d_iomux; + + unsigned int gpio3a_iomux; + unsigned int gpio3b_iomux; + unsigned int gpio3c_iomux; + unsigned int gpio3d_iomux; + + unsigned int reserved1[4]; + unsigned int con_iomux; + unsigned int reserved2[(0x100 - 0x50) / 4 - 1]; + unsigned int gpio0_p[4]; + unsigned int gpio1_p[4]; + unsigned int gpio2_p[4]; + unsigned int gpio3_p[4]; + unsigned int reserved3[(0x200 - 0x13c) / 4 - 1]; + unsigned int gpio0_e[4]; + unsigned int gpio1_e[4]; + unsigned int gpio2_e[4]; + unsigned int gpio3_e[4]; + unsigned int reserved4[(0x400 - 0x23c) / 4 - 1]; + unsigned int soc_con[7]; + unsigned int reserved5[(0x480 - 0x418) / 4 - 1]; + unsigned int soc_status[3]; + unsigned int chip_id; + unsigned int reserved6[(0x500 - 0x48c) / 4 - 1]; + unsigned int cpu_con[4]; + unsigned int reserved7[4]; + unsigned int cpu_status[2]; + unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1]; + unsigned int os_reg[8]; + unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1]; + unsigned int ddrc_stat; + unsigned int reserved10[(0x680 - 0x604) / 4 - 1]; + unsigned int sig_detect_con[2]; + unsigned int reserved11[(0x690 - 0x684) / 4 - 1]; + unsigned int sig_detect_status[2]; + unsigned int reserved12[(0x6a0 - 0x694) / 4 - 1]; + unsigned int sig_detect_clr[2]; + unsigned int reserved13[(0x6b0 - 0x6a4) / 4 - 1]; + unsigned int emmc_det; + unsigned int reserved14[(0x700 - 0x6b0) / 4 - 1]; + unsigned int host0_con[3]; + unsigned int reserved15; + unsigned int host1_con[3]; + unsigned int reserved16; + unsigned int host2_con[3]; + unsigned int reserved17[(0x760 - 0x728) / 4 - 1]; + unsigned int usbphy0_con[27]; + unsigned int reserved18[(0x800 - 0x7c8) / 4 - 1]; + unsigned int usbphy1_con[27]; + unsigned int reserved19[(0x880 - 0x868) / 4 - 1]; + unsigned int otg_con0; + unsigned int uoc_status0; + unsigned int reserved20[(0x900 - 0x884) / 4 - 1]; + unsigned int mac_con[2]; + unsigned int reserved21[(0xb00 - 0x904) / 4 - 1]; + unsigned int macphy_con[4]; + unsigned int macphy_status; +}; +check_member(rk322x_grf, ddrc_stat, 0x604); + +struct rk322x_sgrf { + unsigned int soc_con[11]; + unsigned int busdmac_con[4]; +}; + +/* GRF_MACPHY_CON0 */ +enum { + MACPHY_CFG_ENABLE_SHIFT = 0, + MACPHY_CFG_ENABLE_MASK = 1 << MACPHY_CFG_ENABLE_SHIFT, +}; +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3288.h new file mode 100644 index 000000000..894d3a40b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3288.h @@ -0,0 +1,1155 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2015 Google, Inc + * Copyright 2014 Rockchip Inc. + */ + +#ifndef _ASM_ARCH_GRF_RK3288_H +#define _ASM_ARCH_GRF_RK3288_H + +struct rk3288_grf_gpio_lh { + u32 l; + u32 h; +}; + +struct rk3288_grf { + u32 reserved[3]; + u32 gpio1d_iomux; + u32 gpio2a_iomux; + u32 gpio2b_iomux; + + u32 gpio2c_iomux; + u32 reserved2; + u32 gpio3a_iomux; + u32 gpio3b_iomux; + + u32 gpio3c_iomux; + u32 gpio3dl_iomux; + u32 gpio3dh_iomux; + u32 gpio4al_iomux; + + u32 gpio4ah_iomux; + u32 gpio4bl_iomux; + u32 reserved3; + u32 gpio4c_iomux; + + u32 gpio4d_iomux; + u32 reserved4; + u32 gpio5b_iomux; + u32 gpio5c_iomux; + + u32 reserved5; + u32 gpio6a_iomux; + u32 gpio6b_iomux; + u32 gpio6c_iomux; + u32 reserved6; + u32 gpio7a_iomux; + u32 gpio7b_iomux; + u32 gpio7cl_iomux; + u32 gpio7ch_iomux; + u32 reserved7; + u32 gpio8a_iomux; + u32 gpio8b_iomux; + u32 reserved8[30]; + struct rk3288_grf_gpio_lh gpio_sr[8]; + u32 gpio1_p[8][4]; + u32 gpio1_e[8][4]; + u32 gpio_smt; + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5; + u32 soc_con6; + u32 soc_con7; + u32 soc_con8; + u32 soc_con9; + u32 soc_con10; + u32 soc_con11; + u32 soc_con12; + u32 soc_con13; + u32 soc_con14; + u32 soc_status[22]; + u32 reserved9[2]; + u32 peridmac_con[4]; + u32 ddrc0_con0; + u32 ddrc1_con0; + u32 cpu_con[5]; + u32 reserved10[3]; + u32 cpu_status0; + u32 reserved11; + u32 uoc0_con[5]; + u32 uoc1_con[5]; + u32 uoc2_con[4]; + u32 uoc3_con[2]; + u32 uoc4_con[2]; + u32 pvtm_con[3]; + u32 pvtm_status[3]; + u32 io_vsel; + u32 saradc_testbit; + u32 tsadc_testbit_l; + u32 tsadc_testbit_h; + u32 os_reg[4]; + u32 reserved12; + u32 soc_con15; + u32 soc_con16; +}; + +struct rk3288_sgrf { + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5; + u32 reserved1[(0x20-0x18)/4]; + u32 busdmac_con[2]; + u32 reserved2[(0x40-0x28)/4]; + u32 cpu_con[3]; + u32 reserved3[(0x50-0x4c)/4]; + u32 soc_con6; + u32 soc_con7; + u32 soc_con8; + u32 soc_con9; + u32 soc_con10; + u32 soc_con11; + u32 soc_con12; + u32 soc_con13; + u32 soc_con14; + u32 soc_con15; + u32 soc_con16; + u32 soc_con17; + u32 soc_con18; + u32 soc_con19; + u32 soc_con20; + u32 soc_con21; + u32 reserved4[(0x100-0x90)/4]; + u32 soc_status[2]; + u32 reserved5[(0x120-0x108)/4]; + u32 fast_boot_addr; +}; + +/* GRF_GPIO1D_IOMUX */ +enum { + GPIO1D3_SHIFT = 6, + GPIO1D3_MASK = 1, + GPIO1D3_GPIO = 0, + GPIO1D3_LCDC0_DCLK, + + GPIO1D2_SHIFT = 4, + GPIO1D2_MASK = 1, + GPIO1D2_GPIO = 0, + GPIO1D2_LCDC0_DEN, + + GPIO1D1_SHIFT = 2, + GPIO1D1_MASK = 1, + GPIO1D1_GPIO = 0, + GPIO1D1_LCDC0_VSYNC, + + GPIO1D0_SHIFT = 0, + GPIO1D0_MASK = 1, + GPIO1D0_GPIO = 0, + GPIO1D0_LCDC0_HSYNC, +}; + +/* GRF_GPIO2C_IOMUX */ +enum { + GPIO2C1_SHIFT = 2, + GPIO2C1_MASK = 1, + GPIO2C1_GPIO = 0, + GPIO2C1_I2C3CAM_SDA, + + GPIO2C0_SHIFT = 0, + GPIO2C0_MASK = 1, + GPIO2C0_GPIO = 0, + GPIO2C0_I2C3CAM_SCL, +}; + +/* GRF_GPIO3A_IOMUX */ +enum { + GPIO3A7_SHIFT = 14, + GPIO3A7_MASK = 3, + GPIO3A7_GPIO = 0, + GPIO3A7_FLASH0_DATA7, + GPIO3A7_EMMC_DATA7, + + GPIO3A6_SHIFT = 12, + GPIO3A6_MASK = 3, + GPIO3A6_GPIO = 0, + GPIO3A6_FLASH0_DATA6, + GPIO3A6_EMMC_DATA6, + + GPIO3A5_SHIFT = 10, + GPIO3A5_MASK = 3, + GPIO3A5_GPIO = 0, + GPIO3A5_FLASH0_DATA5, + GPIO3A5_EMMC_DATA5, + + GPIO3A4_SHIFT = 8, + GPIO3A4_MASK = 3, + GPIO3A4_GPIO = 0, + GPIO3A4_FLASH0_DATA4, + GPIO3A4_EMMC_DATA4, + + GPIO3A3_SHIFT = 6, + GPIO3A3_MASK = 3, + GPIO3A3_GPIO = 0, + GPIO3A3_FLASH0_DATA3, + GPIO3A3_EMMC_DATA3, + + GPIO3A2_SHIFT = 4, + GPIO3A2_MASK = 3, + GPIO3A2_GPIO = 0, + GPIO3A2_FLASH0_DATA2, + GPIO3A2_EMMC_DATA2, + + GPIO3A1_SHIFT = 2, + GPIO3A1_MASK = 3, + GPIO3A1_GPIO = 0, + GPIO3A1_FLASH0_DATA1, + GPIO3A1_EMMC_DATA1, + + GPIO3A0_SHIFT = 0, + GPIO3A0_MASK = 3, + GPIO3A0_GPIO = 0, + GPIO3A0_FLASH0_DATA0, + GPIO3A0_EMMC_DATA0, +}; + +/* GRF_GPIO3B_IOMUX */ +enum { + GPIO3B7_SHIFT = 14, + GPIO3B7_MASK = 1, + GPIO3B7_GPIO = 0, + GPIO3B7_FLASH0_CSN1, + + GPIO3B6_SHIFT = 12, + GPIO3B6_MASK = 1, + GPIO3B6_GPIO = 0, + GPIO3B6_FLASH0_CSN0, + + GPIO3B5_SHIFT = 10, + GPIO3B5_MASK = 1, + GPIO3B5_GPIO = 0, + GPIO3B5_FLASH0_WRN, + + GPIO3B4_SHIFT = 8, + GPIO3B4_MASK = 1, + GPIO3B4_GPIO = 0, + GPIO3B4_FLASH0_CLE, + + GPIO3B3_SHIFT = 6, + GPIO3B3_MASK = 1, + GPIO3B3_GPIO = 0, + GPIO3B3_FLASH0_ALE, + + GPIO3B2_SHIFT = 4, + GPIO3B2_MASK = 1, + GPIO3B2_GPIO = 0, + GPIO3B2_FLASH0_RDN, + + GPIO3B1_SHIFT = 2, + GPIO3B1_MASK = 3, + GPIO3B1_GPIO = 0, + GPIO3B1_FLASH0_WP, + GPIO3B1_EMMC_PWREN, + + GPIO3B0_SHIFT = 0, + GPIO3B0_MASK = 1, + GPIO3B0_GPIO = 0, + GPIO3B0_FLASH0_RDY, +}; + +/* GRF_GPIO3C_IOMUX */ +enum { + GPIO3C2_SHIFT = 4, + GPIO3C2_MASK = 3, + GPIO3C2_GPIO = 0, + GPIO3C2_FLASH0_DQS, + GPIO3C2_EMMC_CLKOUT, + + GPIO3C1_SHIFT = 2, + GPIO3C1_MASK = 3, + GPIO3C1_GPIO = 0, + GPIO3C1_FLASH0_CSN3, + GPIO3C1_EMMC_RSTNOUT, + + GPIO3C0_SHIFT = 0, + GPIO3C0_MASK = 3, + GPIO3C0_GPIO = 0, + GPIO3C0_FLASH0_CSN2, + GPIO3C0_EMMC_CMD, +}; + +/* GRF_GPIO3DL_IOMUX */ +enum { + GPIO3D3_SHIFT = 12, + GPIO3D3_MASK = 7, + GPIO3D3_GPIO = 0, + GPIO3D3_FLASH1_DATA3, + GPIO3D3_HOST_DOUT3, + GPIO3D3_MAC_RXD3, + GPIO3D3_SDIO1_DATA3, + + GPIO3D2_SHIFT = 8, + GPIO3D2_MASK = 7, + GPIO3D2_GPIO = 0, + GPIO3D2_FLASH1_DATA2, + GPIO3D2_HOST_DOUT2, + GPIO3D2_MAC_RXD2, + GPIO3D2_SDIO1_DATA2, + + GPIO3D1_SHIFT = 4, + GPIO3D1_MASK = 7, + GPIO3D1_GPIO = 0, + GPIO3DL1_FLASH1_DATA1, + GPIO3D1_HOST_DOUT1, + GPIO3D1_MAC_TXD3, + GPIO3D1_SDIO1_DATA1, + + GPIO3D0_SHIFT = 0, + GPIO3D0_MASK = 7, + GPIO3D0_GPIO = 0, + GPIO3D0_FLASH1_DATA0, + GPIO3D0_HOST_DOUT0, + GPIO3D0_MAC_TXD2, + GPIO3D0_SDIO1_DATA0, +}; + +/* GRF_GPIO3HL_IOMUX */ +enum { + GPIO3D7_SHIFT = 12, + GPIO3D7_MASK = 7, + GPIO3D7_GPIO = 0, + GPIO3D7_FLASH1_DATA7, + GPIO3D7_HOST_DOUT7, + GPIO3D7_MAC_RXD1, + GPIO3D7_SDIO1_INTN, + + GPIO3D6_SHIFT = 8, + GPIO3D6_MASK = 7, + GPIO3D6_GPIO = 0, + GPIO3D6_FLASH1_DATA6, + GPIO3D6_HOST_DOUT6, + GPIO3D6_MAC_RXD0, + GPIO3D6_SDIO1_BKPWR, + + GPIO3D5_SHIFT = 4, + GPIO3D5_MASK = 7, + GPIO3D5_GPIO = 0, + GPIO3D5_FLASH1_DATA5, + GPIO3D5_HOST_DOUT5, + GPIO3D5_MAC_TXD1, + GPIO3D5_SDIO1_WRPRT, + + GPIO3D4_SHIFT = 0, + GPIO3D4_MASK = 7, + GPIO3D4_GPIO = 0, + GPIO3D4_FLASH1_DATA4, + GPIO3D4_HOST_DOUT4, + GPIO3D4_MAC_TXD0, + GPIO3D4_SDIO1_DETECTN, +}; + +/* GRF_GPIO4AL_IOMUX */ +enum { + GPIO4A3_SHIFT = 12, + GPIO4A3_MASK = 7, + GPIO4A3_GPIO = 0, + GPIO4A3_FLASH1_ALE, + GPIO4A3_HOST_DOUT9, + GPIO4A3_MAC_CLK, + GPIO4A3_FLASH0_CSN6, + + GPIO4A2_SHIFT = 8, + GPIO4A2_MASK = 7, + GPIO4A2_GPIO = 0, + GPIO4A2_FLASH1_RDN, + GPIO4A2_HOST_DOUT8, + GPIO4A2_MAC_RXER, + GPIO4A2_FLASH0_CSN5, + + GPIO4A1_SHIFT = 4, + GPIO4A1_MASK = 7, + GPIO4A1_GPIO = 0, + GPIO4A1_FLASH1_WP, + GPIO4A1_HOST_CKOUTN, + GPIO4A1_MAC_TXDV, + GPIO4A1_FLASH0_CSN4, + + GPIO4A0_SHIFT = 0, + GPIO4A0_MASK = 3, + GPIO4A0_GPIO = 0, + GPIO4A0_FLASH1_RDY, + GPIO4A0_HOST_CKOUTP, + GPIO4A0_MAC_MDC, +}; + +/* GRF_GPIO4AH_IOMUX */ +enum { + GPIO4A7_SHIFT = 12, + GPIO4A7_MASK = 7, + GPIO4A7_GPIO = 0, + GPIO4A7_FLASH1_CSN1, + GPIO4A7_HOST_DOUT13, + GPIO4A7_MAC_CSR, + GPIO4A7_SDIO1_CLKOUT, + + GPIO4A6_SHIFT = 8, + GPIO4A6_MASK = 7, + GPIO4A6_GPIO = 0, + GPIO4A6_FLASH1_CSN0, + GPIO4A6_HOST_DOUT12, + GPIO4A6_MAC_RXCLK, + GPIO4A6_SDIO1_CMD, + + GPIO4A5_SHIFT = 4, + GPIO4A5_MASK = 3, + GPIO4A5_GPIO = 0, + GPIO4A5_FLASH1_WRN, + GPIO4A5_HOST_DOUT11, + GPIO4A5_MAC_MDIO, + + GPIO4A4_SHIFT = 0, + GPIO4A4_MASK = 7, + GPIO4A4_GPIO = 0, + GPIO4A4_FLASH1_CLE, + GPIO4A4_HOST_DOUT10, + GPIO4A4_MAC_TXEN, + GPIO4A4_FLASH0_CSN7, +}; + +/* GRF_GPIO4BL_IOMUX */ +enum { + GPIO4B1_SHIFT = 4, + GPIO4B1_MASK = 7, + GPIO4B1_GPIO = 0, + GPIO4B1_FLASH1_CSN2, + GPIO4B1_HOST_DOUT15, + GPIO4B1_MAC_TXCLK, + GPIO4B1_SDIO1_PWREN, + + GPIO4B0_SHIFT = 0, + GPIO4B0_MASK = 7, + GPIO4B0_GPIO = 0, + GPIO4B0_FLASH1_DQS, + GPIO4B0_HOST_DOUT14, + GPIO4B0_MAC_COL, + GPIO4B0_FLASH1_CSN3, +}; + +/* GRF_GPIO4C_IOMUX */ +enum { + GPIO4C7_SHIFT = 14, + GPIO4C7_MASK = 1, + GPIO4C7_GPIO = 0, + GPIO4C7_SDIO0_DATA3, + + GPIO4C6_SHIFT = 12, + GPIO4C6_MASK = 1, + GPIO4C6_GPIO = 0, + GPIO4C6_SDIO0_DATA2, + + GPIO4C5_SHIFT = 10, + GPIO4C5_MASK = 1, + GPIO4C5_GPIO = 0, + GPIO4C5_SDIO0_DATA1, + + GPIO4C4_SHIFT = 8, + GPIO4C4_MASK = 1, + GPIO4C4_GPIO = 0, + GPIO4C4_SDIO0_DATA0, + + GPIO4C3_SHIFT = 6, + GPIO4C3_MASK = 1, + GPIO4C3_GPIO = 0, + GPIO4C3_UART0BT_RTSN, + + GPIO4C2_SHIFT = 4, + GPIO4C2_MASK = 1, + GPIO4C2_GPIO = 0, + GPIO4C2_UART0BT_CTSN, + + GPIO4C1_SHIFT = 2, + GPIO4C1_MASK = 1, + GPIO4C1_GPIO = 0, + GPIO4C1_UART0BT_SOUT, + + GPIO4C0_SHIFT = 0, + GPIO4C0_MASK = 1, + GPIO4C0_GPIO = 0, + GPIO4C0_UART0BT_SIN, +}; + +/* GRF_GPIO5B_IOMUX */ +enum { + GPIO5B7_SHIFT = 14, + GPIO5B7_MASK = 3, + GPIO5B7_GPIO = 0, + GPIO5B7_SPI0_RXD, + GPIO5B7_TS0_DATA7, + GPIO5B7_UART4EXP_SIN, + + GPIO5B6_SHIFT = 12, + GPIO5B6_MASK = 3, + GPIO5B6_GPIO = 0, + GPIO5B6_SPI0_TXD, + GPIO5B6_TS0_DATA6, + GPIO5B6_UART4EXP_SOUT, + + GPIO5B5_SHIFT = 10, + GPIO5B5_MASK = 3, + GPIO5B5_GPIO = 0, + GPIO5B5_SPI0_CSN0, + GPIO5B5_TS0_DATA5, + GPIO5B5_UART4EXP_RTSN, + + GPIO5B4_SHIFT = 8, + GPIO5B4_MASK = 3, + GPIO5B4_GPIO = 0, + GPIO5B4_SPI0_CLK, + GPIO5B4_TS0_DATA4, + GPIO5B4_UART4EXP_CTSN, + + GPIO5B3_SHIFT = 6, + GPIO5B3_MASK = 3, + GPIO5B3_GPIO = 0, + GPIO5B3_UART1BB_RTSN, + GPIO5B3_TS0_DATA3, + + GPIO5B2_SHIFT = 4, + GPIO5B2_MASK = 3, + GPIO5B2_GPIO = 0, + GPIO5B2_UART1BB_CTSN, + GPIO5B2_TS0_DATA2, + + GPIO5B1_SHIFT = 2, + GPIO5B1_MASK = 3, + GPIO5B1_GPIO = 0, + GPIO5B1_UART1BB_SOUT, + GPIO5B1_TS0_DATA1, + + GPIO5B0_SHIFT = 0, + GPIO5B0_MASK = 3, + GPIO5B0_GPIO = 0, + GPIO5B0_UART1BB_SIN, + GPIO5B0_TS0_DATA0, +}; + +/* GRF_GPIO5C_IOMUX */ +enum { + GPIO5C3_SHIFT = 6, + GPIO5C3_MASK = 1, + GPIO5C3_GPIO = 0, + GPIO5C3_TS0_ERR, + + GPIO5C2_SHIFT = 4, + GPIO5C2_MASK = 1, + GPIO5C2_GPIO = 0, + GPIO5C2_TS0_CLK, + + GPIO5C1_SHIFT = 2, + GPIO5C1_MASK = 1, + GPIO5C1_GPIO = 0, + GPIO5C1_TS0_VALID, + + GPIO5C0_SHIFT = 0, + GPIO5C0_MASK = 3, + GPIO5C0_GPIO = 0, + GPIO5C0_SPI0_CSN1, + GPIO5C0_TS0_SYNC, +}; + +/* GRF_GPIO6A_IOMUX */ +enum { + GPIO6A7_SHIFT = 0xe, + GPIO6A7_MASK = 1, + GPIO6A7_GPIO = 0, + GPIO6A7_I2S_SDO3, + + GPIO6A6_SHIFT = 0xc, + GPIO6A6_MASK = 1, + GPIO6A6_GPIO = 0, + GPIO6A6_I2S_SDO2, + + GPIO6A5_SHIFT = 0xa, + GPIO6A5_MASK = 1, + GPIO6A5_GPIO = 0, + GPIO6A5_I2S_SDO1, + + GPIO6A4_SHIFT = 8, + GPIO6A4_MASK = 1, + GPIO6A4_GPIO = 0, + GPIO6A4_I2S_SDO0, + + GPIO6A3_SHIFT = 6, + GPIO6A3_MASK = 1, + GPIO6A3_GPIO = 0, + GPIO6A3_I2S_SDI, + + GPIO6A2_SHIFT = 4, + GPIO6A2_MASK = 1, + GPIO6A2_GPIO = 0, + GPIO6A2_I2S_LRCKTX, + + GPIO6A1_SHIFT = 2, + GPIO6A1_MASK = 1, + GPIO6A1_GPIO = 0, + GPIO6A1_I2S_LRCKRX, + + GPIO6A0_SHIFT = 0, + GPIO6A0_MASK = 1, + GPIO6A0_GPIO = 0, + GPIO6A0_I2S_SCLK, +}; + +/* GRF_GPIO6B_IOMUX */ +enum { + GPIO6B3_SHIFT = 6, + GPIO6B3_MASK = 1, + GPIO6B3_GPIO = 0, + GPIO6B3_SPDIF_TX, + + GPIO6B2_SHIFT = 4, + GPIO6B2_MASK = 1, + GPIO6B2_GPIO = 0, + GPIO6B2_I2C1AUDIO_SCL, + + GPIO6B1_SHIFT = 2, + GPIO6B1_MASK = 1, + GPIO6B1_GPIO = 0, + GPIO6B1_I2C1AUDIO_SDA, + + GPIO6B0_SHIFT = 0, + GPIO6B0_MASK = 1, + GPIO6B0_GPIO = 0, + GPIO6B0_I2S_CLK, +}; + +/* GRF_GPIO6C_IOMUX */ +enum { + GPIO6C6_SHIFT = 12, + GPIO6C6_MASK = 1, + GPIO6C6_GPIO = 0, + GPIO6C6_SDMMC0_DECTN, + + GPIO6C5_SHIFT = 10, + GPIO6C5_MASK = 1, + GPIO6C5_GPIO = 0, + GPIO6C5_SDMMC0_CMD, + + GPIO6C4_SHIFT = 8, + GPIO6C4_MASK = 3, + GPIO6C4_GPIO = 0, + GPIO6C4_SDMMC0_CLKOUT, + GPIO6C4_JTAG_TDO, + + GPIO6C3_SHIFT = 6, + GPIO6C3_MASK = 3, + GPIO6C3_GPIO = 0, + GPIO6C3_SDMMC0_DATA3, + GPIO6C3_JTAG_TCK, + + GPIO6C2_SHIFT = 4, + GPIO6C2_MASK = 3, + GPIO6C2_GPIO = 0, + GPIO6C2_SDMMC0_DATA2, + GPIO6C2_JTAG_TDI, + + GPIO6C1_SHIFT = 2, + GPIO6C1_MASK = 3, + GPIO6C1_GPIO = 0, + GPIO6C1_SDMMC0_DATA1, + GPIO6C1_JTAG_TRSTN, + + GPIO6C0_SHIFT = 0, + GPIO6C0_MASK = 3, + GPIO6C0_GPIO = 0, + GPIO6C0_SDMMC0_DATA0, + GPIO6C0_JTAG_TMS, +}; + +/* GRF_GPIO7A_IOMUX */ +enum { + GPIO7A7_SHIFT = 14, + GPIO7A7_MASK = 3, + GPIO7A7_GPIO = 0, + GPIO7A7_UART3GPS_SIN, + GPIO7A7_GPS_MAG, + GPIO7A7_HSADCT1_DATA0, + + GPIO7A1_SHIFT = 2, + GPIO7A1_MASK = 1, + GPIO7A1_GPIO = 0, + GPIO7A1_PWM_1, + + GPIO7A0_SHIFT = 0, + GPIO7A0_MASK = 3, + GPIO7A0_GPIO = 0, + GPIO7A0_PWM_0, + GPIO7A0_VOP0_PWM, + GPIO7A0_VOP1_PWM, +}; + +/* GRF_GPIO7B_IOMUX */ +enum { + GPIO7B7_SHIFT = 14, + GPIO7B7_MASK = 3, + GPIO7B7_GPIO = 0, + GPIO7B7_ISP_SHUTTERTRIG, + GPIO7B7_SPI1_TXD, + + GPIO7B6_SHIFT = 12, + GPIO7B6_MASK = 3, + GPIO7B6_GPIO = 0, + GPIO7B6_ISP_PRELIGHTTRIG, + GPIO7B6_SPI1_RXD, + + GPIO7B5_SHIFT = 10, + GPIO7B5_MASK = 3, + GPIO7B5_GPIO = 0, + GPIO7B5_ISP_FLASHTRIGOUT, + GPIO7B5_SPI1_CSN0, + + GPIO7B4_SHIFT = 8, + GPIO7B4_MASK = 3, + GPIO7B4_GPIO = 0, + GPIO7B4_ISP_SHUTTEREN, + GPIO7B4_SPI1_CLK, + + GPIO7B3_SHIFT = 6, + GPIO7B3_MASK = 3, + GPIO7B3_GPIO = 0, + GPIO7B3_USB_DRVVBUS1, + GPIO7B3_EDP_HOTPLUG, + + GPIO7B2_SHIFT = 4, + GPIO7B2_MASK = 3, + GPIO7B2_GPIO = 0, + GPIO7B2_UART3GPS_RTSN, + GPIO7B2_USB_DRVVBUS0, + + GPIO7B1_SHIFT = 2, + GPIO7B1_MASK = 3, + GPIO7B1_GPIO = 0, + GPIO7B1_UART3GPS_CTSN, + GPIO7B1_GPS_RFCLK, + GPIO7B1_GPST1_CLK, + + GPIO7B0_SHIFT = 0, + GPIO7B0_MASK = 3, + GPIO7B0_GPIO = 0, + GPIO7B0_UART3GPS_SOUT, + GPIO7B0_GPS_SIG, + GPIO7B0_HSADCT1_DATA1, +}; + +/* GRF_GPIO7CL_IOMUX */ +enum { + GPIO7C3_SHIFT = 12, + GPIO7C3_MASK = 3, + GPIO7C3_GPIO = 0, + GPIO7C3_I2C5HDMI_SDA, + GPIO7C3_EDPHDMII2C_SDA, + + GPIO7C2_SHIFT = 8, + GPIO7C2_MASK = 1, + GPIO7C2_GPIO = 0, + GPIO7C2_I2C4TP_SCL, + + GPIO7C1_SHIFT = 4, + GPIO7C1_MASK = 1, + GPIO7C1_GPIO = 0, + GPIO7C1_I2C4TP_SDA, + + GPIO7C0_SHIFT = 0, + GPIO7C0_MASK = 3, + GPIO7C0_GPIO = 0, + GPIO7C0_ISP_FLASHTRIGIN, + GPIO7C0_EDPHDMI_CECINOUTT1, +}; + +/* GRF_GPIO7CH_IOMUX */ +enum { + GPIO7C7_SHIFT = 12, + GPIO7C7_MASK = 7, + GPIO7C7_GPIO = 0, + GPIO7C7_UART2DBG_SOUT, + GPIO7C7_UART2DBG_SIROUT, + GPIO7C7_PWM_3, + GPIO7C7_EDPHDMI_CECINOUT, + + GPIO7C6_SHIFT = 8, + GPIO7C6_MASK = 3, + GPIO7C6_GPIO = 0, + GPIO7C6_UART2DBG_SIN, + GPIO7C6_UART2DBG_SIRIN, + GPIO7C6_PWM_2, + + GPIO7C4_SHIFT = 0, + GPIO7C4_MASK = 3, + GPIO7C4_GPIO = 0, + GPIO7C4_I2C5HDMI_SCL, + GPIO7C4_EDPHDMII2C_SCL, +}; + +/* GRF_GPIO8A_IOMUX */ +enum { + GPIO8A7_SHIFT = 14, + GPIO8A7_MASK = 3, + GPIO8A7_GPIO = 0, + GPIO8A7_SPI2_CSN0, + GPIO8A7_SC_DETECT, + GPIO8A7_RESERVE, + + GPIO8A6_SHIFT = 12, + GPIO8A6_MASK = 3, + GPIO8A6_GPIO = 0, + GPIO8A6_SPI2_CLK, + GPIO8A6_SC_IO, + GPIO8A6_RESERVE, + + GPIO8A5_SHIFT = 10, + GPIO8A5_MASK = 3, + GPIO8A5_GPIO = 0, + GPIO8A5_I2C2SENSOR_SCL, + GPIO8A5_SC_CLK, + + GPIO8A4_SHIFT = 8, + GPIO8A4_MASK = 3, + GPIO8A4_GPIO = 0, + GPIO8A4_I2C2SENSOR_SDA, + GPIO8A4_SC_RST, + + GPIO8A3_SHIFT = 6, + GPIO8A3_MASK = 3, + GPIO8A3_GPIO = 0, + GPIO8A3_SPI2_CSN1, + GPIO8A3_SC_IOT1, + + GPIO8A2_SHIFT = 4, + GPIO8A2_MASK = 1, + GPIO8A2_GPIO = 0, + GPIO8A2_SC_DETECTT1, + + GPIO8A1_SHIFT = 2, + GPIO8A1_MASK = 3, + GPIO8A1_GPIO = 0, + GPIO8A1_PS2_DATA, + GPIO8A1_SC_VCC33V, + + GPIO8A0_SHIFT = 0, + GPIO8A0_MASK = 3, + GPIO8A0_GPIO = 0, + GPIO8A0_PS2_CLK, + GPIO8A0_SC_VCC18V, +}; + +/* GRF_GPIO8B_IOMUX */ +enum { + GPIO8B1_SHIFT = 2, + GPIO8B1_MASK = 3, + GPIO8B1_GPIO = 0, + GPIO8B1_SPI2_TXD, + GPIO8B1_SC_CLK, + + GPIO8B0_SHIFT = 0, + GPIO8B0_MASK = 3, + GPIO8B0_GPIO = 0, + GPIO8B0_SPI2_RXD, + GPIO8B0_SC_RST, +}; + +/* GRF_SOC_CON0 */ +enum { + PAUSE_MMC_PERI_SHIFT = 0xf, + PAUSE_MMC_PERI_MASK = 1, + + PAUSE_EMEM_PERI_SHIFT = 0xe, + PAUSE_EMEM_PERI_MASK = 1, + + PAUSE_USB_PERI_SHIFT = 0xd, + PAUSE_USB_PERI_MASK = 1, + + GRF_FORCE_JTAG_SHIFT = 0xc, + GRF_FORCE_JTAG_MASK = 1, + + GRF_CORE_IDLE_REQ_MODE_SEL1_SHIFT = 0xb, + GRF_CORE_IDLE_REQ_MODE_SEL1_MASK = 1, + + GRF_CORE_IDLE_REQ_MODE_SEL0_SHIFT = 0xa, + GRF_CORE_IDLE_REQ_MODE_SEL0_MASK = 1, + + DDR1_16BIT_EN_SHIFT = 9, + DDR1_16BIT_EN_MASK = 1, + + DDR0_16BIT_EN_SHIFT = 8, + DDR0_16BIT_EN_MASK = 1, + + VCODEC_SHIFT = 7, + VCODEC_MASK = 1, + VCODEC_SELECT_VEPU_ACLK = 0, + VCODEC_SELECT_VDPU_ACLK, + + UPCTL1_C_ACTIVE_IN_SHIFT = 6, + UPCTL1_C_ACTIVE_IN_MASK = 1, + UPCTL1_C_ACTIVE_IN_MAY = 0, + UPCTL1_C_ACTIVE_IN_WILL, + + UPCTL0_C_ACTIVE_IN_SHIFT = 5, + UPCTL0_C_ACTIVE_IN_MASK = 1, + UPCTL0_C_ACTIVE_IN_MAY = 0, + UPCTL0_C_ACTIVE_IN_WILL, + + MSCH1_MAINDDR3_SHIFT = 4, + MSCH1_MAINDDR3_MASK = 1, + MSCH1_MAINDDR3_DDR3 = 1, + + MSCH0_MAINDDR3_SHIFT = 3, + MSCH0_MAINDDR3_MASK = 1, + MSCH0_MAINDDR3_DDR3 = 1, + + MSCH1_MAINPARTIALPOP_SHIFT = 2, + MSCH1_MAINPARTIALPOP_MASK = 1, + + MSCH0_MAINPARTIALPOP_SHIFT = 1, + MSCH0_MAINPARTIALPOP_MASK = 1, +}; + +/* GRF_SOC_CON1 */ +enum { + RK3288_RMII_MODE_SHIFT = 14, + RK3288_RMII_MODE_MASK = (1 << RK3288_RMII_MODE_SHIFT), + RK3288_RMII_MODE = (1 << RK3288_RMII_MODE_SHIFT), + + RK3288_GMAC_CLK_SEL_SHIFT = 12, + RK3288_GMAC_CLK_SEL_MASK = (3 << RK3288_GMAC_CLK_SEL_SHIFT), + RK3288_GMAC_CLK_SEL_125M = (0 << RK3288_GMAC_CLK_SEL_SHIFT), + RK3288_GMAC_CLK_SEL_25M = (3 << RK3288_GMAC_CLK_SEL_SHIFT), + RK3288_GMAC_CLK_SEL_2_5M = (2 << RK3288_GMAC_CLK_SEL_SHIFT), + + RK3288_RMII_CLK_SEL_SHIFT = 11, + RK3288_RMII_CLK_SEL_MASK = (1 << RK3288_RMII_CLK_SEL_SHIFT), + RK3288_RMII_CLK_SEL_2_5M = (0 << RK3288_RMII_CLK_SEL_SHIFT), + RK3288_RMII_CLK_SEL_25M = (1 << RK3288_RMII_CLK_SEL_SHIFT), + + GMAC_SPEED_SHIFT = 0xa, + GMAC_SPEED_MASK = 1, + GMAC_SPEED_10M = 0, + GMAC_SPEED_100M, + + GMAC_FLOWCTRL_SHIFT = 0x9, + GMAC_FLOWCTRL_MASK = 1, + + RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6, + RK3288_GMAC_PHY_INTF_SEL_MASK = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), + RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), + RK3288_GMAC_PHY_INTF_SEL_RMII = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), + + HOST_REMAP_SHIFT = 0x5, + HOST_REMAP_MASK = 1 +}; + +/* GRF_SOC_CON2 */ +enum { + UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd, + UPCTL1_LPDDR3_ODT_EN_MASK = 1, + UPCTL1_LPDDR3_ODT_EN_ODT = 1, + + UPCTL1_BST_DIABLE_SHIFT = 0xc, + UPCTL1_BST_DIABLE_MASK = 1, + UPCTL1_BST_DIABLE_DISABLE = 1, + + LPDDR3_EN1_SHIFT = 0xb, + LPDDR3_EN1_MASK = 1, + LPDDR3_EN1_LPDDR3 = 1, + + UPCTL0_LPDDR3_ODT_EN_SHIFT = 0xa, + UPCTL0_LPDDR3_ODT_EN_MASK = 1, + UPCTL0_LPDDR3_ODT_EN_ODT_ENABLE = 1, + + UPCTL0_BST_DIABLE_SHIFT = 9, + UPCTL0_BST_DIABLE_MASK = 1, + UPCTL0_BST_DIABLE_DISABLE = 1, + + LPDDR3_EN0_SHIFT = 8, + LPDDR3_EN0_MASK = 1, + LPDDR3_EN0_LPDDR3 = 1, + + GRF_POC_FLASH0_CTRL_SHIFT = 7, + GRF_POC_FLASH0_CTRL_MASK = 1, + GRF_POC_FLASH0_CTRL_GPIO3C_3 = 0, + GRF_POC_FLASH0_CTRL_GRF_IO_VSEL, + + SIMCARD_MUX_SHIFT = 6, + SIMCARD_MUX_MASK = 1, + SIMCARD_MUX_USE_A = 1, + SIMCARD_MUX_USE_B = 0, + + GRF_SPDIF_2CH_EN_SHIFT = 1, + GRF_SPDIF_2CH_EN_MASK = 1, + GRF_SPDIF_2CH_EN_8CH = 0, + GRF_SPDIF_2CH_EN_2CH, + + PWM_SHIFT = 0, + PWM_MASK = 1, + PWM_RK = 1, + PWM_PWM = 0, +}; + +/* GRF_SOC_CON3 */ +enum { + RK3288_RXCLK_DLY_ENA_GMAC_SHIFT = 0xf, + RK3288_RXCLK_DLY_ENA_GMAC_MASK = + (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT), + RK3288_RXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3288_RXCLK_DLY_ENA_GMAC_ENABLE = + (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT), + + RK3288_TXCLK_DLY_ENA_GMAC_SHIFT = 0xe, + RK3288_TXCLK_DLY_ENA_GMAC_MASK = + (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT), + RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3288_TXCLK_DLY_ENA_GMAC_ENABLE = + (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT), + + RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, + RK3288_CLK_RX_DL_CFG_GMAC_MASK = + (0x7f << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT), + + RK3288_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, + RK3288_CLK_TX_DL_CFG_GMAC_MASK = + (0x7f << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT), +}; + +/* GRF_SOC_CON6 */ +enum GRF_SOC_CON6 { + RK3288_HDMI_EDP_SEL_SHIFT = 0xf, + RK3288_HDMI_EDP_SEL_MASK = + 1 << RK3288_HDMI_EDP_SEL_SHIFT, + RK3288_HDMI_EDP_SEL_EDP = 0, + RK3288_HDMI_EDP_SEL_HDMI, + + RK3288_DSI0_DPICOLORM_SHIFT = 0x8, + RK3288_DSI0_DPICOLORM_MASK = + 1 << RK3288_DSI0_DPICOLORM_SHIFT, + + RK3288_DSI0_DPISHUTDN_SHIFT = 0x7, + RK3288_DSI0_DPISHUTDN_MASK = + 1 << RK3288_DSI0_DPISHUTDN_SHIFT, + + RK3288_DSI0_LCDC_SEL_SHIFT = 0x6, + RK3288_DSI0_LCDC_SEL_MASK = + 1 << RK3288_DSI0_LCDC_SEL_SHIFT, + RK3288_DSI0_LCDC_SEL_BIG = 0, + RK3288_DSI0_LCDC_SEL_LIT = 1, + + RK3288_EDP_LCDC_SEL_SHIFT = 0x5, + RK3288_EDP_LCDC_SEL_MASK = + 1 << RK3288_EDP_LCDC_SEL_SHIFT, + RK3288_EDP_LCDC_SEL_BIG = 0, + RK3288_EDP_LCDC_SEL_LIT = 1, + + RK3288_HDMI_LCDC_SEL_SHIFT = 0x4, + RK3288_HDMI_LCDC_SEL_MASK = + 1 << RK3288_HDMI_LCDC_SEL_SHIFT, + RK3288_HDMI_LCDC_SEL_BIG = 0, + RK3288_HDMI_LCDC_SEL_LIT = 1, + + RK3288_LVDS_LCDC_SEL_SHIFT = 0x3, + RK3288_LVDS_LCDC_SEL_MASK = + 1 << RK3288_LVDS_LCDC_SEL_SHIFT, + RK3288_LVDS_LCDC_SEL_BIG = 0, + RK3288_LVDS_LCDC_SEL_LIT = 1, +}; + +/* RK3288_SOC_CON8 */ +enum GRF_SOC_CON8 { + RK3288_DPHY_TX0_RXMODE_SHIFT = 4, + RK3288_DPHY_TX0_RXMODE_MASK = + 0xf << RK3288_DPHY_TX0_RXMODE_SHIFT, + RK3288_DPHY_TX0_RXMODE_EN = 0xf, + RK3288_DPHY_TX0_RXMODE_DIS = 0, + + RK3288_DPHY_TX0_TXSTOPMODE_SHIFT = 0x8, + RK3288_DPHY_TX0_TXSTOPMODE_MASK = + 0xf << RK3288_DPHY_TX0_TXSTOPMODE_SHIFT, + RK3288_DPHY_TX0_TXSTOPMODE_EN = 0xf, + RK3288_DPHY_TX0_TXSTOPMODE_DIS = 0, + + RK3288_DPHY_TX0_TURNREQUEST_SHIFT = 0, + RK3288_DPHY_TX0_TURNREQUEST_MASK = + 0xf << RK3288_DPHY_TX0_TURNREQUEST_SHIFT, + RK3288_DPHY_TX0_TURNREQUEST_EN = 0xf, + RK3288_DPHY_TX0_TURNREQUEST_DIS = 0, +}; + +/* GRF_IO_VSEL */ +enum { + GPIO1830_V18SEL_SHIFT = 9, + GPIO1830_V18SEL_MASK = 1, + GPIO1830_V18SEL_3_3V = 0, + GPIO1830_V18SEL_1_8V, + + GPIO30_V18SEL_SHIFT = 8, + GPIO30_V18SEL_MASK = 1, + GPIO30_V18SEL_3_3V = 0, + GPIO30_V18SEL_1_8V, + + SDCARD_V18SEL_SHIFT = 7, + SDCARD_V18SEL_MASK = 1, + SDCARD_V18SEL_3_3V = 0, + SDCARD_V18SEL_1_8V, + + AUDIO_V18SEL_SHIFT = 6, + AUDIO_V18SEL_MASK = 1, + AUDIO_V18SEL_3_3V = 0, + AUDIO_V18SEL_1_8V, + + BB_V18SEL_SHIFT = 5, + BB_V18SEL_MASK = 1, + BB_V18SEL_3_3V = 0, + BB_V18SEL_1_8V, + + WIFI_V18SEL_SHIFT = 4, + WIFI_V18SEL_MASK = 1, + WIFI_V18SEL_3_3V = 0, + WIFI_V18SEL_1_8V, + + FLASH1_V18SEL_SHIFT = 3, + FLASH1_V18SEL_MASK = 1, + FLASH1_V18SEL_3_3V = 0, + FLASH1_V18SEL_1_8V, + + FLASH0_V18SEL_SHIFT = 2, + FLASH0_V18SEL_MASK = 1, + FLASH0_V18SEL_3_3V = 0, + FLASH0_V18SEL_1_8V, + + DVP_V18SEL_SHIFT = 1, + DVP_V18SEL_MASK = 1, + DVP_V18SEL_3_3V = 0, + DVP_V18SEL_1_8V, + + LCDC_V18SEL_SHIFT = 0, + LCDC_V18SEL_MASK = 1, + LCDC_V18SEL_3_3V = 0, + LCDC_V18SEL_1_8V, +}; + +/* GPIO Bias settings */ +enum GPIO_BIAS { + GPIO_BIAS_2MA = 0, + GPIO_BIAS_4MA, + GPIO_BIAS_8MA, + GPIO_BIAS_12MA, +}; + +#define GPIO_BIAS_MASK 0x3 +#define GPIO_BIAS_SHIFT(x) ((x) * 2) + +#define GPIO_PULL_MASK 0x3 +#define GPIO_PULL_SHIFT(x) ((x) * 2) + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3328.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3328.h new file mode 100644 index 000000000..d8a46800f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3328.h @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __SOC_ROCKCHIP_RK3328_GRF_H__ +#define __SOC_ROCKCHIP_RK3328_GRF_H__ + +struct rk3328_grf_regs { + u32 gpio0a_iomux; + u32 gpio0b_iomux; + u32 gpio0c_iomux; + u32 gpio0d_iomux; + u32 gpio1a_iomux; + u32 gpio1b_iomux; + u32 gpio1c_iomux; + u32 gpio1d_iomux; + u32 gpio2a_iomux; + u32 gpio2bl_iomux; + u32 gpio2bh_iomux; + u32 gpio2cl_iomux; + u32 gpio2ch_iomux; + u32 gpio2d_iomux; + u32 gpio3al_iomux; + u32 gpio3ah_iomux; + u32 gpio3bl_iomux; + u32 gpio3bh_iomux; + u32 gpio3c_iomux; + u32 gpio3d_iomux; + u32 com_iomux; + u32 reserved1[(0x100 - 0x54) / 4]; + + u32 gpio0a_p; + u32 gpio0b_p; + u32 gpio0c_p; + u32 gpio0d_p; + u32 gpio1a_p; + u32 gpio1b_p; + u32 gpio1c_p; + u32 gpio1d_p; + u32 gpio2a_p; + u32 gpio2b_p; + u32 gpio2c_p; + u32 gpio2d_p; + u32 gpio3a_p; + u32 gpio3b_p; + u32 gpio3c_p; + u32 gpio3d_p; + u32 reserved2[(0x200 - 0x140) / 4]; + u32 gpio0a_e; + u32 gpio0b_e; + u32 gpio0c_e; + u32 gpio0d_e; + u32 gpio1a_e; + u32 gpio1b_e; + u32 gpio1c_e; + u32 gpio1d_e; + u32 gpio2a_e; + u32 gpio2b_e; + u32 gpio2c_e; + u32 gpio2d_e; + u32 gpio3a_e; + u32 gpio3b_e; + u32 gpio3c_e; + u32 gpio3d_e; + u32 reserved3[(0x300 - 0x240) / 4]; + u32 gpio0l_sr; + u32 gpio0h_sr; + u32 gpio1l_sr; + u32 gpio1h_sr; + u32 gpio2l_sr; + u32 gpio2h_sr; + u32 gpio3l_sr; + u32 gpio3h_sr; + u32 reserved4[(0x380 - 0x320) / 4]; + u32 gpio0l_smt; + u32 gpio0h_smt; + u32 gpio1l_smt; + u32 gpio1h_smt; + u32 gpio2l_smt; + u32 gpio2h_smt; + u32 gpio3l_smt; + u32 gpio3h_smt; + u32 reserved5[(0x400 - 0x3a0) / 4]; + u32 soc_con[11]; + u32 reserved6[(0x480 - 0x42c) / 4]; + u32 soc_status[5]; + u32 reserved7[(0x4c0 - 0x494) / 4]; + u32 otg3_con[2]; + u32 reserved8[(0x500 - 0x4c8) / 4]; + u32 cpu_con[2]; + u32 reserved9[(0x520 - 0x508) / 4]; + u32 cpu_status[2]; + u32 reserved10[(0x5c8 - 0x528) / 4]; + u32 os_reg[8]; + u32 reserved11[(0x680 - 0x5e8) / 4]; + u32 sig_detect_con; + u32 reserved12[3]; + u32 sig_detect_status; + u32 reserved13[3]; + u32 sig_detect_status_clr; + u32 reserved14[3]; + + u32 sdmmc_det_counter; + u32 reserved15[(0x700 - 0x6b4) / 4]; + u32 host0_con[3]; + u32 reserved16[(0x880 - 0x70c) / 4]; + u32 otg_con0; + u32 reserved17[3]; + u32 host0_status; + u32 reserved18[(0x900 - 0x894) / 4]; + u32 mac_con[3]; + u32 reserved19[(0xb00 - 0x90c) / 4]; + u32 macphy_con[4]; + u32 macphy_status; +}; +check_member(rk3328_grf_regs, macphy_status, 0xb10); + +struct rk3328_sgrf_regs { + u32 soc_con[6]; + u32 reserved0[(0x100 - 0x18) / 4]; + u32 dmac_con[6]; + u32 reserved1[(0x180 - 0x118) / 4]; + u32 fast_boot_addr; + u32 reserved2[(0x200 - 0x184) / 4]; + u32 chip_fuse_con; + u32 reserved3[(0x280 - 0x204) / 4]; + u32 hdcp_key_reg[8]; + u32 hdcp_key_access_mask; +}; +check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0); + +#endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3368.h new file mode 100644 index 000000000..0079d2007 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3368.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + */ +#ifndef _ASM_ARCH_GRF_RK3368_H +#define _ASM_ARCH_GRF_RK3368_H + +#ifndef __ASSEMBLY__ +#include +#endif + +struct rk3368_grf { + u32 gpio1a_iomux; + u32 gpio1b_iomux; + u32 gpio1c_iomux; + u32 gpio1d_iomux; + u32 gpio2a_iomux; + u32 gpio2b_iomux; + u32 gpio2c_iomux; + u32 gpio2d_iomux; + u32 gpio3a_iomux; + u32 gpio3b_iomux; + u32 gpio3c_iomux; + u32 gpio3d_iomux; + u32 reserved[0x34]; + u32 gpio1a_pull; + u32 gpio1b_pull; + u32 gpio1c_pull; + u32 gpio1d_pull; + u32 gpio2a_pull; + u32 gpio2b_pull; + u32 gpio2c_pull; + u32 gpio2d_pull; + u32 gpio3a_pull; + u32 gpio3b_pull; + u32 gpio3c_pull; + u32 gpio3d_pull; + u32 reserved1[0x34]; + u32 gpio1a_drv; + u32 gpio1b_drv; + u32 gpio1c_drv; + u32 gpio1d_drv; + u32 gpio2a_drv; + u32 gpio2b_drv; + u32 gpio2c_drv; + u32 gpio2d_drv; + u32 gpio3a_drv; + u32 gpio3b_drv; + u32 gpio3c_drv; + u32 gpio3d_drv; + u32 reserved2[0x34]; + u32 gpio1l_sr; + u32 gpio1h_sr; + u32 gpio2l_sr; + u32 gpio2h_sr; + u32 gpio3l_sr; + u32 gpio3h_sr; + u32 reserved3[0x1a]; + u32 gpio_smt; + u32 reserved4[0x1f]; + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5; + u32 soc_con6; + u32 soc_con7; + u32 soc_con8; + u32 soc_con9; + u32 soc_con10; + u32 soc_con11; + u32 soc_con12; + u32 soc_con13; + u32 soc_con14; + u32 soc_con15; + u32 soc_con16; + u32 soc_con17; + u32 reserved5[0x6e]; + u32 ddrc0_con0; +}; +check_member(rk3368_grf, soc_con17, 0x444); +check_member(rk3368_grf, ddrc0_con0, 0x600); + +struct rk3368_pmu_grf { + u32 gpio0a_iomux; + u32 gpio0b_iomux; + u32 gpio0c_iomux; + u32 gpio0d_iomux; + u32 gpio0a_pull; + u32 gpio0b_pull; + u32 gpio0c_pull; + u32 gpio0d_pull; + u32 gpio0a_drv; + u32 gpio0b_drv; + u32 gpio0c_drv; + u32 gpio0d_drv; + u32 gpio0l_sr; + u32 gpio0h_sr; + u32 reserved[0x72]; + u32 os_reg[4]; +}; +check_member(rk3368_pmu_grf, gpio0h_sr, 0x34); +check_member(rk3368_pmu_grf, os_reg[0], 0x200); + +/*GRF_SOC_CON11/12/13*/ +enum { + MCU_SRAM_BASE_BIT27_BIT12_SHIFT = 0, + MCU_SRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0), +}; + +/*GRF_SOC_CON12*/ +enum { + MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT = 0, + MCU_EXSRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0), +}; + +/*GRF_SOC_CON13*/ +enum { + MCU_EXPERI_BASE_BIT27_BIT12_SHIFT = 0, + MCU_EXPERI_BASE_BIT27_BIT12_MASK = GENMASK(15, 0), +}; + +/*GRF_SOC_CON14*/ +enum { + MCU_EXPERI_BASE_BIT31_BIT28_SHIFT = 12, + MCU_EXPERI_BASE_BIT31_BIT28_MASK = GENMASK(15, 12), + MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT = 8, + MCU_EXSRAM_BASE_BIT31_BIT28_MASK = GENMASK(11, 8), + MCU_SRAM_BASE_BIT31_BIT28_SHIFT = 4, + MCU_SRAM_BASE_BIT31_BIT28_MASK = GENMASK(7, 4), + MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0, + MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0), +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3399.h new file mode 100644 index 000000000..dd89cd205 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -0,0 +1,672 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __SOC_ROCKCHIP_RK3399_GRF_H__ +#define __SOC_ROCKCHIP_RK3399_GRF_H__ + +struct rk3399_grf_regs { + u32 reserved[0x800]; + u32 usb3_perf_con0; + u32 usb3_perf_con1; + u32 usb3_perf_con2; + u32 usb3_perf_rd_max_latency_num; + u32 usb3_perf_rd_latency_samp_num; + u32 usb3_perf_rd_latency_acc_num; + u32 usb3_perf_rd_axi_total_byte; + u32 usb3_perf_wr_axi_total_byte; + u32 usb3_perf_working_cnt; + u32 reserved1[0x103]; + u32 usb3otg0_con0; + u32 usb3otg0_con1; + u32 reserved2[2]; + u32 usb3otg1_con0; + u32 usb3otg1_con1; + u32 reserved3[2]; + u32 usb3otg0_status_lat0; + u32 usb3otg0_status_lat1; + u32 usb3otg0_status_cb; + u32 reserved4; + u32 usb3otg1_status_lat0; + u32 usb3otg1_status_lat1; + u32 usb3ogt1_status_cb; + u32 reserved5[0x6e5]; + u32 pcie_perf_con0; + u32 pcie_perf_con1; + u32 pcie_perf_con2; + u32 pcie_perf_rd_max_latency_num; + u32 pcie_perf_rd_latency_samp_num; + u32 pcie_perf_rd_laterncy_acc_num; + u32 pcie_perf_rd_axi_total_byte; + u32 pcie_perf_wr_axi_total_byte; + u32 pcie_perf_working_cnt; + u32 reserved6[0x37]; + u32 usb20_host0_con0; + u32 usb20_host0_con1; + u32 reserved7[2]; + u32 usb20_host1_con0; + u32 usb20_host1_con1; + u32 reserved8[2]; + u32 hsic_con0; + u32 hsic_con1; + u32 reserved9[6]; + u32 grf_usbhost0_status; + u32 grf_usbhost1_Status; + u32 grf_hsic_status; + u32 reserved10[0xc9]; + u32 hsicphy_con0; + u32 reserved11[3]; + u32 usbphy0_ctrl[26]; + u32 reserved12[6]; + u32 usbphy1[26]; + u32 reserved13[0x72f]; + u32 soc_con9; + u32 reserved14[0x0a]; + u32 soc_con20; + u32 soc_con21; + u32 soc_con22; + u32 soc_con23; + u32 soc_con24; + u32 soc_con25; + u32 soc_con26; + u32 reserved15[0xf65]; + u32 cpu_con[4]; + u32 reserved16[0x1c]; + u32 cpu_status[6]; + u32 reserved17[0x1a]; + u32 a53_perf_con[4]; + u32 a53_perf_rd_mon_st; + u32 a53_perf_rd_mon_end; + u32 a53_perf_wr_mon_st; + u32 a53_perf_wr_mon_end; + u32 a53_perf_rd_max_latency_num; + u32 a53_perf_rd_latency_samp_num; + u32 a53_perf_rd_laterncy_acc_num; + u32 a53_perf_rd_axi_total_byte; + u32 a53_perf_wr_axi_total_byte; + u32 a53_perf_working_cnt; + u32 a53_perf_int_status; + u32 reserved18[0x31]; + u32 a72_perf_con[4]; + u32 a72_perf_rd_mon_st; + u32 a72_perf_rd_mon_end; + u32 a72_perf_wr_mon_st; + u32 a72_perf_wr_mon_end; + u32 a72_perf_rd_max_latency_num; + u32 a72_perf_rd_latency_samp_num; + u32 a72_perf_rd_laterncy_acc_num; + u32 a72_perf_rd_axi_total_byte; + u32 a72_perf_wr_axi_total_byte; + u32 a72_perf_working_cnt; + u32 a72_perf_int_status; + u32 reserved19[0x7f6]; + u32 soc_con5; + u32 soc_con6; + u32 reserved20[0x779]; + u32 gpio2a_iomux; + union { + u32 iomux_spi2; + u32 gpio2b_iomux; + }; + union { + u32 gpio2c_iomux; + u32 iomux_spi5; + }; + u32 gpio2d_iomux; + union { + u32 gpio3a_iomux; + u32 iomux_spi0; + }; + u32 gpio3b_iomux; + u32 gpio3c_iomux; + union { + u32 iomux_i2s0; + u32 gpio3d_iomux; + }; + union { + u32 iomux_i2sclk; + u32 gpio4a_iomux; + }; + union { + u32 iomux_sdmmc; + u32 iomux_uart2a; + u32 gpio4b_iomux; + }; + union { + u32 iomux_pwm_0; + u32 iomux_pwm_1; + u32 iomux_uart2b; + u32 iomux_uart2c; + u32 iomux_edp_hotplug; + u32 gpio4c_iomux; + }; + u32 gpio4d_iomux; + u32 reserved21[4]; + u32 gpio2_p[4]; + u32 gpio3_p[4]; + u32 gpio4_p[4]; + u32 reserved22[4]; + u32 gpio2_sr[3][4]; + u32 reserved23[4]; + u32 gpio2_smt[3][4]; + u32 reserved24[(0xe100 - 0xe0ec)/4 - 1]; + u32 gpio2_e[4]; + u32 gpio3_e[7]; + u32 gpio4_e[5]; + u32 reserved24a[(0xe200 - 0xe13c)/4 - 1]; + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5_pcie; + u32 reserved25; + u32 soc_con7; + u32 soc_con8; + u32 soc_con9_pcie; + u32 reserved26[0x1e]; + u32 soc_status[6]; + u32 reserved27[0x32]; + u32 ddrc0_con0; + u32 ddrc0_con1; + u32 ddrc1_con0; + u32 ddrc1_con1; + u32 reserved28[0xac]; + u32 io_vsel; + u32 saradc_testbit; + u32 tsadc_testbit_l; + u32 tsadc_testbit_h; + u32 reserved29[0x6c]; + u32 chip_id_addr; + u32 reserved30[0x1f]; + u32 fast_boot_addr; + u32 reserved31[0x1df]; + u32 emmccore_con[12]; + u32 reserved32[4]; + u32 emmccore_status[4]; + u32 reserved33[0x1cc]; + u32 emmcphy_con[7]; + u32 reserved34; + u32 emmcphy_status; +}; +check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0); + +struct rk3399_pmugrf_regs { + union { + u32 iomux_pwm_3a; + u32 gpio0a_iomux; + }; + u32 gpio0b_iomux; + u32 reserved0[2]; + union { + u32 spi1_rxd; + u32 tsadc_int; + u32 gpio1a_iomux; + }; + union { + u32 spi1_csclktx; + u32 iomux_pwm_3b; + u32 iomux_i2c0_sda; + u32 gpio1b_iomux; + }; + union { + u32 iomux_pwm_2; + u32 iomux_i2c0_scl; + u32 gpio1c_iomux; + }; + u32 gpio1d_iomux; + u32 reserved1[8]; + u32 gpio0_p[2]; + u32 reserved2[2]; + u32 gpio1_p[4]; + u32 reserved3[8]; + u32 gpio0a_e; + u32 reserved4; + u32 gpio0b_e; + u32 reserved5[5]; + u32 gpio1a_e; + u32 reserved6; + u32 gpio1b_e; + u32 reserved7; + u32 gpio1c_e; + u32 reserved8; + u32 gpio1d_e; + u32 reserved9[0x11]; + u32 gpio0l_sr; + u32 reserved10; + u32 gpio1l_sr; + u32 gpio1h_sr; + u32 reserved11[4]; + u32 gpio0a_smt; + u32 gpio0b_smt; + u32 reserved12[2]; + u32 gpio1a_smt; + u32 gpio1b_smt; + u32 gpio1c_smt; + u32 gpio1d_smt; + u32 reserved13[8]; + u32 gpio0l_he; + u32 reserved14; + u32 gpio1l_he; + u32 gpio1h_he; + u32 reserved15[4]; + u32 soc_con0; + u32 reserved16[9]; + u32 soc_con10; + u32 soc_con11; + u32 reserved17[0x24]; + u32 pmupvtm_con0; + u32 pmupvtm_con1; + u32 pmupvtm_status0; + u32 pmupvtm_status1; + u32 grf_osc_e; + u32 reserved18[0x2b]; + u32 os_reg0; + u32 os_reg1; + u32 os_reg2; + u32 os_reg3; +}; +check_member(rk3399_pmugrf_regs, os_reg3, 0x30c); + +struct rk3399_pmusgrf_regs { + u32 ddr_rgn_con[35]; + u32 reserved[0x1fe5]; + u32 soc_con8; + u32 soc_con9; + u32 soc_con10; + u32 soc_con11; + u32 soc_con12; + u32 soc_con13; + u32 soc_con14; + u32 soc_con15; + u32 reserved1[3]; + u32 soc_con19; + u32 soc_con20; + u32 soc_con21; + u32 soc_con22; + u32 reserved2[0x29]; + u32 perilp_con[9]; + u32 reserved4[7]; + u32 perilp_status; + u32 reserved5[0xfaf]; + u32 soc_con0; + u32 soc_con1; + u32 reserved6[0x3e]; + u32 pmu_con[9]; + u32 reserved7[0x17]; + u32 fast_boot_addr; + u32 reserved8[0x1f]; + u32 efuse_prg_mask; + u32 efuse_read_mask; + u32 reserved9[0x0e]; + u32 pmu_slv_con0; + u32 pmu_slv_con1; + u32 reserved10[0x771]; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5; + u32 soc_con6; + u32 soc_con7; + u32 reserved11[8]; + u32 soc_con16; + u32 soc_con17; + u32 soc_con18; + u32 reserved12[0xdd]; + u32 slv_secure_con0; + u32 slv_secure_con1; + u32 reserved13; + u32 slv_secure_con2; + u32 slv_secure_con3; + u32 slv_secure_con4; +}; +check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4); + +enum { + /* GRF_GPIO2A_IOMUX */ + GRF_GPIO2A0_SEL_SHIFT = 0, + GRF_GPIO2A0_SEL_MASK = 3 << GRF_GPIO2A0_SEL_SHIFT, + GRF_I2C2_SDA = 2, + GRF_GPIO2A1_SEL_SHIFT = 2, + GRF_GPIO2A1_SEL_MASK = 3 << GRF_GPIO2A1_SEL_SHIFT, + GRF_I2C2_SCL = 2, + GRF_GPIO2A7_SEL_SHIFT = 14, + GRF_GPIO2A7_SEL_MASK = 3 << GRF_GPIO2A7_SEL_SHIFT, + GRF_I2C7_SDA = 2, + + /* GRF_GPIO2B_IOMUX */ + GRF_GPIO2B0_SEL_SHIFT = 0, + GRF_GPIO2B0_SEL_MASK = 3 << GRF_GPIO2B0_SEL_SHIFT, + GRF_I2C7_SCL = 2, + GRF_GPIO2B1_SEL_SHIFT = 2, + GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT, + GRF_SPI2TPM_RXD = 1, + GRF_I2C6_SDA = 2, + GRF_GPIO2B2_SEL_SHIFT = 4, + GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT, + GRF_SPI2TPM_TXD = 1, + GRF_I2C6_SCL = 2, + GRF_GPIO2B3_SEL_SHIFT = 6, + GRF_GPIO2B3_SEL_MASK = 3 << GRF_GPIO2B3_SEL_SHIFT, + GRF_SPI2TPM_CLK = 1, + GRF_GPIO2B4_SEL_SHIFT = 8, + GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT, + GRF_SPI2TPM_CSN0 = 1, + + /* GRF_GPIO2C_IOMUX */ + GRF_GPIO2C0_SEL_SHIFT = 0, + GRF_GPIO2C0_SEL_MASK = 3 << GRF_GPIO2C0_SEL_SHIFT, + GRF_UART0BT_SIN = 1, + GRF_GPIO2C1_SEL_SHIFT = 2, + GRF_GPIO2C1_SEL_MASK = 3 << GRF_GPIO2C1_SEL_SHIFT, + GRF_UART0BT_SOUT = 1, + GRF_GPIO2C4_SEL_SHIFT = 8, + GRF_GPIO2C4_SEL_MASK = 3 << GRF_GPIO2C4_SEL_SHIFT, + GRF_SPI5EXPPLUS_RXD = 2, + GRF_GPIO2C5_SEL_SHIFT = 10, + GRF_GPIO2C5_SEL_MASK = 3 << GRF_GPIO2C5_SEL_SHIFT, + GRF_SPI5EXPPLUS_TXD = 2, + GRF_GPIO2C6_SEL_SHIFT = 12, + GRF_GPIO2C6_SEL_MASK = 3 << GRF_GPIO2C6_SEL_SHIFT, + GRF_SPI5EXPPLUS_CLK = 2, + GRF_GPIO2C7_SEL_SHIFT = 14, + GRF_GPIO2C7_SEL_MASK = 3 << GRF_GPIO2C7_SEL_SHIFT, + GRF_SPI5EXPPLUS_CSN0 = 2, + + /* GRF_GPIO3A_IOMUX */ + GRF_GPIO3A0_SEL_SHIFT = 0, + GRF_GPIO3A0_SEL_MASK = 3 << GRF_GPIO3A0_SEL_SHIFT, + GRF_MAC_TXD2 = 1, + GRF_GPIO3A1_SEL_SHIFT = 2, + GRF_GPIO3A1_SEL_MASK = 3 << GRF_GPIO3A1_SEL_SHIFT, + GRF_MAC_TXD3 = 1, + GRF_GPIO3A2_SEL_SHIFT = 4, + GRF_GPIO3A2_SEL_MASK = 3 << GRF_GPIO3A2_SEL_SHIFT, + GRF_MAC_RXD2 = 1, + GRF_GPIO3A3_SEL_SHIFT = 6, + GRF_GPIO3A3_SEL_MASK = 3 << GRF_GPIO3A3_SEL_SHIFT, + GRF_MAC_RXD3 = 1, + GRF_GPIO3A4_SEL_SHIFT = 8, + GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT, + GRF_MAC_TXD0 = 1, + GRF_SPI0NORCODEC_RXD = 2, + GRF_GPIO3A5_SEL_SHIFT = 10, + GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT, + GRF_MAC_TXD1 = 1, + GRF_SPI0NORCODEC_TXD = 2, + GRF_GPIO3A6_SEL_SHIFT = 12, + GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT, + GRF_MAC_RXD0 = 1, + GRF_SPI0NORCODEC_CLK = 2, + GRF_GPIO3A7_SEL_SHIFT = 14, + GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT, + GRF_MAC_RXD1 = 1, + GRF_SPI0NORCODEC_CSN0 = 2, + + /* GRF_GPIO3B_IOMUX */ + GRF_GPIO3B0_SEL_SHIFT = 0, + GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT, + GRF_MAC_MDC = 1, + GRF_SPI0NORCODEC_CSN1 = 2, + GRF_GPIO3B1_SEL_SHIFT = 2, + GRF_GPIO3B1_SEL_MASK = 3 << GRF_GPIO3B1_SEL_SHIFT, + GRF_MAC_RXDV = 1, + GRF_GPIO3B3_SEL_SHIFT = 6, + GRF_GPIO3B3_SEL_MASK = 3 << GRF_GPIO3B3_SEL_SHIFT, + GRF_MAC_CLK = 1, + GRF_GPIO3B4_SEL_SHIFT = 8, + GRF_GPIO3B4_SEL_MASK = 3 << GRF_GPIO3B4_SEL_SHIFT, + GRF_MAC_TXEN = 1, + GRF_GPIO3B5_SEL_SHIFT = 10, + GRF_GPIO3B5_SEL_MASK = 3 << GRF_GPIO3B5_SEL_SHIFT, + GRF_MAC_MDIO = 1, + GRF_GPIO3B6_SEL_SHIFT = 12, + GRF_GPIO3B6_SEL_MASK = 3 << GRF_GPIO3B6_SEL_SHIFT, + GRF_MAC_RXCLK = 1, + GRF_UART3_SIN = 2, + GRF_GPIO3B7_SEL_SHIFT = 14, + GRF_GPIO3B7_SEL_MASK = 3 << GRF_GPIO3B7_SEL_SHIFT, + GRF_UART3_SOUT = 2, + + /* GRF_GPIO3C_IOMUX */ + GRF_GPIO3C1_SEL_SHIFT = 2, + GRF_GPIO3C1_SEL_MASK = 3 << GRF_GPIO3C1_SEL_SHIFT, + GRF_MAC_TXCLK = 1, + + /* GRF_GPIO4A_IOMUX */ + GRF_GPIO4A1_SEL_SHIFT = 2, + GRF_GPIO4A1_SEL_MASK = 3 << GRF_GPIO4A1_SEL_SHIFT, + GRF_I2C1_SDA = 1, + GRF_GPIO4A2_SEL_SHIFT = 4, + GRF_GPIO4A2_SEL_MASK = 3 << GRF_GPIO4A2_SEL_SHIFT, + GRF_I2C1_SCL = 1, + + /* GRF_GPIO4B_IOMUX */ + GRF_GPIO4B0_SEL_SHIFT = 0, + GRF_GPIO4B0_SEL_MASK = 3 << GRF_GPIO4B0_SEL_SHIFT, + GRF_SDMMC_DATA0 = 1, + GRF_UART2DBGA_SIN = 2, + GRF_GPIO4B1_SEL_SHIFT = 2, + GRF_GPIO4B1_SEL_MASK = 3 << GRF_GPIO4B1_SEL_SHIFT, + GRF_SDMMC_DATA1 = 1, + GRF_UART2DBGA_SOUT = 2, + GRF_GPIO4B2_SEL_SHIFT = 4, + GRF_GPIO4B2_SEL_MASK = 3 << GRF_GPIO4B2_SEL_SHIFT, + GRF_SDMMC_DATA2 = 1, + GRF_GPIO4B3_SEL_SHIFT = 6, + GRF_GPIO4B3_SEL_MASK = 3 << GRF_GPIO4B3_SEL_SHIFT, + GRF_SDMMC_DATA3 = 1, + GRF_GPIO4B4_SEL_SHIFT = 8, + GRF_GPIO4B4_SEL_MASK = 3 << GRF_GPIO4B4_SEL_SHIFT, + GRF_SDMMC_CLKOUT = 1, + GRF_GPIO4B5_SEL_SHIFT = 10, + GRF_GPIO4B5_SEL_MASK = 3 << GRF_GPIO4B5_SEL_SHIFT, + GRF_SDMMC_CMD = 1, + + /* GRF_GPIO4C_IOMUX */ + GRF_GPIO4C0_SEL_SHIFT = 0, + GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT, + GRF_UART2DGBB_SIN = 2, + GRF_HDMII2C_SCL = 3, + GRF_GPIO4C1_SEL_SHIFT = 2, + GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT, + GRF_UART2DGBB_SOUT = 2, + GRF_HDMII2C_SDA = 3, + GRF_GPIO4C2_SEL_SHIFT = 4, + GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT, + GRF_PWM_0 = 1, + GRF_GPIO4C3_SEL_SHIFT = 6, + GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT, + GRF_UART2DGBC_SIN = 1, + GRF_GPIO4C4_SEL_SHIFT = 8, + GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT, + GRF_UART2DBGC_SOUT = 1, + GRF_GPIO4C6_SEL_SHIFT = 12, + GRF_GPIO4C6_SEL_MASK = 3 << GRF_GPIO4C6_SEL_SHIFT, + GRF_PWM_1 = 1, + + /* GRF_GPIO3A_E01 */ + GRF_GPIO3A0_E_SHIFT = 0, + GRF_GPIO3A0_E_MASK = 7 << GRF_GPIO3A0_E_SHIFT, + GRF_GPIO3A1_E_SHIFT = 3, + GRF_GPIO3A1_E_MASK = 7 << GRF_GPIO3A1_E_SHIFT, + GRF_GPIO3A2_E_SHIFT = 6, + GRF_GPIO3A2_E_MASK = 7 << GRF_GPIO3A2_E_SHIFT, + GRF_GPIO3A3_E_SHIFT = 9, + GRF_GPIO3A3_E_MASK = 7 << GRF_GPIO3A3_E_SHIFT, + GRF_GPIO3A4_E_SHIFT = 12, + GRF_GPIO3A4_E_MASK = 7 << GRF_GPIO3A4_E_SHIFT, + GRF_GPIO3A5_E0_SHIFT = 15, + GRF_GPIO3A5_E0_MASK = 1 << GRF_GPIO3A5_E0_SHIFT, + + /* GRF_GPIO3A_E2 */ + GRF_GPIO3A5_E12_SHIFT = 0, + GRF_GPIO3A5_E12_MASK = 3 << GRF_GPIO3A5_E12_SHIFT, + GRF_GPIO3A6_E_SHIFT = 2, + GRF_GPIO3A6_E_MASK = 7 << GRF_GPIO3A6_E_SHIFT, + GRF_GPIO3A7_E_SHIFT = 5, + GRF_GPIO3A7_E_MASK = 7 << GRF_GPIO3A7_E_SHIFT, + + /* GRF_GPIO3B_E01 */ + GRF_GPIO3B0_E_SHIFT = 0, + GRF_GPIO3B0_E_MASK = 7 << GRF_GPIO3B0_E_SHIFT, + GRF_GPIO3B1_E_SHIFT = 3, + GRF_GPIO3B1_E_MASK = 7 << GRF_GPIO3B1_E_SHIFT, + GRF_GPIO3B2_E_SHIFT = 6, + GRF_GPIO3B2_E_MASK = 7 << GRF_GPIO3B2_E_SHIFT, + GRF_GPIO3B3_E_SHIFT = 9, + GRF_GPIO3B3_E_MASK = 7 << GRF_GPIO3B3_E_SHIFT, + GRF_GPIO3B4_E_SHIFT = 12, + GRF_GPIO3B4_E_MASK = 7 << GRF_GPIO3B4_E_SHIFT, + GRF_GPIO3B5_E0_SHIFT = 15, + GRF_GPIO3B5_E0_MASK = 1 << GRF_GPIO3B5_E0_SHIFT, + + /* GRF_GPIO3A_E2 */ + GRF_GPIO3B5_E12_SHIFT = 0, + GRF_GPIO3B5_E12_MASK = 3 << GRF_GPIO3B5_E12_SHIFT, + GRF_GPIO3B6_E_SHIFT = 2, + GRF_GPIO3B6_E_MASK = 7 << GRF_GPIO3B6_E_SHIFT, + GRF_GPIO3B7_E_SHIFT = 5, + GRF_GPIO3B7_E_MASK = 7 << GRF_GPIO3B7_E_SHIFT, + + /* GRF_GPIO3C_E01 */ + GRF_GPIO3C0_E_SHIFT = 0, + GRF_GPIO3C0_E_MASK = 7 << GRF_GPIO3C0_E_SHIFT, + GRF_GPIO3C1_E_SHIFT = 3, + GRF_GPIO3C1_E_MASK = 7 << GRF_GPIO3C1_E_SHIFT, + GRF_GPIO3C2_E_SHIFT = 6, + GRF_GPIO3C2_E_MASK = 7 << GRF_GPIO3C2_E_SHIFT, + GRF_GPIO3C3_E_SHIFT = 9, + GRF_GPIO3C3_E_MASK = 7 << GRF_GPIO3C3_E_SHIFT, + GRF_GPIO3C4_E_SHIFT = 12, + GRF_GPIO3C4_E_MASK = 7 << GRF_GPIO3C4_E_SHIFT, + GRF_GPIO3C5_E0_SHIFT = 15, + GRF_GPIO3C5_E0_MASK = 1 << GRF_GPIO3C5_E0_SHIFT, + + /* GRF_GPIO3C_E2 */ + GRF_GPIO3C5_E12_SHIFT = 0, + GRF_GPIO3C5_E12_MASK = 3 << GRF_GPIO3C5_E12_SHIFT, + GRF_GPIO3C6_E_SHIFT = 2, + GRF_GPIO3C6_E_MASK = 7 << GRF_GPIO3C6_E_SHIFT, + GRF_GPIO3C7_E_SHIFT = 5, + GRF_GPIO3C7_E_MASK = 7 << GRF_GPIO3C7_E_SHIFT, + + /* GRF_SOC_CON7 */ + GRF_UART_DBG_SEL_SHIFT = 10, + GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT, + GRF_UART_DBG_SEL_C = 2, + + /* GRF_SOC_CON20 */ + GRF_DSI0_VOP_SEL_SHIFT = 0, + GRF_DSI0_VOP_SEL_MASK = 1 << GRF_DSI0_VOP_SEL_SHIFT, + GRF_DSI0_VOP_SEL_B = 0, + GRF_DSI0_VOP_SEL_L = 1, + GRF_RK3399_HDMI_VOP_SEL_MASK = 1 << 6, + GRF_RK3399_HDMI_VOP_SEL_B = 0 << 6, + GRF_RK3399_HDMI_VOP_SEL_L = 1 << 6, + + /* GRF_SOC_CON22 */ + GRF_DPHY_TX0_RXMODE_SHIFT = 0, + GRF_DPHY_TX0_RXMODE_MASK = 0xf << GRF_DPHY_TX0_RXMODE_SHIFT, + GRF_DPHY_TX0_RXMODE_EN = 0xb, + GRF_DPHY_TX0_RXMODE_DIS = 0, + + GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4, + GRF_DPHY_TX0_TXSTOPMODE_MASK = 0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT, + GRF_DPHY_TX0_TXSTOPMODE_EN = 0xc, + GRF_DPHY_TX0_TXSTOPMODE_DIS = 0, + + GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12, + GRF_DPHY_TX0_TURNREQUEST_MASK = + 0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT, + GRF_DPHY_TX0_TURNREQUEST_EN = 0x1, + GRF_DPHY_TX0_TURNREQUEST_DIS = 0, + + /* PMUGRF_GPIO0A_IOMUX */ + PMUGRF_GPIO0A6_SEL_SHIFT = 12, + PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT, + PMUGRF_PWM_3A = 1, + + /* PMUGRF_GPIO1A_IOMUX */ + PMUGRF_GPIO1A7_SEL_SHIFT = 14, + PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT, + PMUGRF_SPI1EC_RXD = 2, + + /* PMUGRF_GPIO1B_IOMUX */ + PMUGRF_GPIO1B0_SEL_SHIFT = 0, + PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT, + PMUGRF_SPI1EC_TXD = 2, + PMUGRF_GPIO1B1_SEL_SHIFT = 2, + PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT, + PMUGRF_SPI1EC_CLK = 2, + PMUGRF_GPIO1B2_SEL_SHIFT = 4, + PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT, + PMUGRF_SPI1EC_CSN0 = 2, + PMUGRF_GPIO1B3_SEL_SHIFT = 6, + PMUGRF_GPIO1B3_SEL_MASK = 3 << PMUGRF_GPIO1B3_SEL_SHIFT, + PMUGRF_I2C4_SDA = 1, + PMUGRF_GPIO1B4_SEL_SHIFT = 8, + PMUGRF_GPIO1B4_SEL_MASK = 3 << PMUGRF_GPIO1B4_SEL_SHIFT, + PMUGRF_I2C4_SCL = 1, + PMUGRF_GPIO1B6_SEL_SHIFT = 12, + PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT, + PMUGRF_PWM_3B = 1, + PMUGRF_GPIO1B7_SEL_SHIFT = 14, + PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT, + PMUGRF_I2C0PMU_SDA = 2, + + /* PMUGRF_GPIO1C_IOMUX */ + PMUGRF_GPIO1C0_SEL_SHIFT = 0, + PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT, + PMUGRF_I2C0PMU_SCL = 2, + PMUGRF_GPIO1C3_SEL_SHIFT = 6, + PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT, + PMUGRF_PWM_2 = 1, + PMUGRF_GPIO1C4_SEL_SHIFT = 8, + PMUGRF_GPIO1C4_SEL_MASK = 3 << PMUGRF_GPIO1C4_SEL_SHIFT, + PMUGRF_I2C8PMU_SDA = 1, + PMUGRF_GPIO1C5_SEL_SHIFT = 10, + PMUGRF_GPIO1C5_SEL_MASK = 3 << PMUGRF_GPIO1C5_SEL_SHIFT, + PMUGRF_I2C8PMU_SCL = 1, +}; + +/* GRF_SOC_CON5 */ +enum { + RK3399_GMAC_PHY_INTF_SEL_SHIFT = 9, + RK3399_GMAC_PHY_INTF_SEL_MASK = (7 << RK3399_GMAC_PHY_INTF_SEL_SHIFT), + RK3399_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3399_GMAC_PHY_INTF_SEL_SHIFT), + RK3399_GMAC_PHY_INTF_SEL_RMII = (4 << RK3399_GMAC_PHY_INTF_SEL_SHIFT), + + RK3399_GMAC_CLK_SEL_SHIFT = 4, + RK3399_GMAC_CLK_SEL_MASK = (3 << RK3399_GMAC_CLK_SEL_SHIFT), + RK3399_GMAC_CLK_SEL_125M = (0 << RK3399_GMAC_CLK_SEL_SHIFT), + RK3399_GMAC_CLK_SEL_25M = (3 << RK3399_GMAC_CLK_SEL_SHIFT), + RK3399_GMAC_CLK_SEL_2_5M = (2 << RK3399_GMAC_CLK_SEL_SHIFT), +}; + +/* GRF_SOC_CON6 */ +enum { + RK3399_RXCLK_DLY_ENA_GMAC_SHIFT = 15, + RK3399_RXCLK_DLY_ENA_GMAC_MASK = + (1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT), + RK3399_RXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3399_RXCLK_DLY_ENA_GMAC_ENABLE = + (1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT), + + RK3399_TXCLK_DLY_ENA_GMAC_SHIFT = 7, + RK3399_TXCLK_DLY_ENA_GMAC_MASK = + (1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT), + RK3399_TXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3399_TXCLK_DLY_ENA_GMAC_ENABLE = + (1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT), + + RK3399_CLK_RX_DL_CFG_GMAC_SHIFT = 8, + RK3399_CLK_RX_DL_CFG_GMAC_MASK = + (0x7f << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT), + + RK3399_CLK_TX_DL_CFG_GMAC_SHIFT = 0, + RK3399_CLK_TX_DL_CFG_GMAC_MASK = + (0x7f << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT), +}; + +#endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rv1108.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rv1108.h new file mode 100644 index 000000000..92bbe34af --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/grf_rv1108.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ +#ifndef _ASM_ARCH_GRF_RV1108_H +#define _ASM_ARCH_GRF_RV1108_H + +struct rv1108_grf { + u32 reserved[4]; + u32 gpio1a_iomux; + u32 gpio1b_iomux; + u32 gpio1c_iomux; + u32 gpio1d_iomux; + u32 gpio2a_iomux; + u32 gpio2b_iomux; + u32 gpio2c_iomux; + u32 gpio2d_iomux; + u32 gpio3a_iomux; + u32 gpio3b_iomux; + u32 gpio3c_iomux; + u32 gpio3d_iomux; + u32 reserved1[52]; + u32 gpio1a_pull; + u32 gpio1b_pull; + u32 gpio1c_pull; + u32 gpio1d_pull; + u32 gpio2a_pull; + u32 gpio2b_pull; + u32 gpio2c_pull; + u32 gpio2d_pull; + u32 gpio3a_pull; + u32 gpio3b_pull; + u32 gpio3c_pull; + u32 gpio3d_pull; + u32 reserved2[52]; + u32 gpio1a_drv; + u32 gpio1b_drv; + u32 gpio1c_drv; + u32 gpio1d_drv; + u32 gpio2a_drv; + u32 gpio2b_drv; + u32 gpio2c_drv; + u32 gpio2d_drv; + u32 gpio3a_drv; + u32 gpio3b_drv; + u32 gpio3c_drv; + u32 gpio3d_drv; + u32 reserved3[50]; + u32 gpio1l_sr; + u32 gpio1h_sr; + u32 gpio2l_sr; + u32 gpio2h_sr; + u32 gpio3l_sr; + u32 gpio3h_sr; + u32 reserved4[26]; + u32 gpio1l_smt; + u32 gpio1h_smt; + u32 gpio2l_smt; + u32 gpio2h_smt; + u32 gpio3l_smt; + u32 gpio3h_smt; + u32 reserved5[24]; + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5; + u32 soc_con6; + u32 soc_con7; + u32 soc_con8; + u32 soc_con9; + u32 soc_con10; + u32 soc_con11; + u32 reserved6[20]; + u32 soc_status0; + u32 soc_status1; + u32 reserved7[30]; + u32 cpu_con0; + u32 cpu_con1; + u32 reserved8[30]; + u32 os_reg0; + u32 os_reg1; + u32 os_reg2; + u32 os_reg3; + u32 reserved9[29]; + u32 ddr_status; + u32 reserved10[30]; + u32 sig_det_con; + u32 reserved11[3]; + u32 sig_det_status; + u32 reserved12[3]; + u32 sig_det_clr; + u32 reserved13[23]; + u32 host_con0; + u32 host_con1; + u32 reserved14[2]; + u32 dma_con0; + u32 dma_con1; + u32 reserved15[59]; + u32 uoc_status; + u32 reserved16[2]; + u32 host_status; + u32 reserved17[59]; + u32 gmac_con0; + u32 reserved18[191]; + u32 chip_id; +}; + +check_member(rv1108_grf, chip_id, 0x0c00); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/hardware.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/hardware.h new file mode 100644 index 000000000..62e8bed8f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/hardware.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Google, Inc + */ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +#define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | (set)) +#define RK_SETBITS(set) RK_CLRSETBITS(0, set) +#define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) + +#define rk_clrsetreg(addr, clr, set) \ + writel(((clr) | (set)) << 16 | (set), addr) +#define rk_clrreg(addr, clr) writel((clr) << 16, addr) +#define rk_setreg(addr, set) writel((set) << 16 | (set), addr) + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/i2c.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/i2c.h new file mode 100644 index 000000000..b0e1936f6 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/i2c.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 SAMSUNG Electronics + * Jaehoon Chung + */ + +#ifndef __ASM_ARCH_I2C_H +#define __ASM_ARCH_I2C_H + +struct i2c_regs { + u32 con; + u32 clkdiv; + u32 mrxaddr; + u32 mrxraddr; + u32 mtxcnt; + u32 mrxcnt; + u32 ien; + u32 ipd; + u32 fcnt; + u32 reserved0[0x37]; + u32 txdata[8]; + u32 reserved1[0x38]; + u32 rxdata[8]; +}; + +/* Control register */ +#define I2C_CON_EN (1 << 0) +#define I2C_CON_MOD(mod) ((mod) << 1) +#define I2C_MODE_TX 0x00 +#define I2C_MODE_TRX 0x01 +#define I2C_MODE_RX 0x02 +#define I2C_MODE_RRX 0x03 +#define I2C_CON_MASK (3 << 1) + +#define I2C_CON_START (1 << 3) +#define I2C_CON_STOP (1 << 4) +#define I2C_CON_LASTACK (1 << 5) +#define I2C_CON_ACTACK (1 << 6) + +/* Clock dividor register */ +#define I2C_CLKDIV_VAL(divl, divh) \ + (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000)) + +/* the slave address accessed for master rx mode */ +#define I2C_MRXADDR_SET(vld, addr) (((vld) << 24) | (addr)) + +/* the slave register address accessed for master rx mode */ +#define I2C_MRXRADDR_SET(vld, raddr) (((vld) << 24) | (raddr)) + +/* interrupt enable register */ +#define I2C_BTFIEN (1 << 0) +#define I2C_BRFIEN (1 << 1) +#define I2C_MBTFIEN (1 << 2) +#define I2C_MBRFIEN (1 << 3) +#define I2C_STARTIEN (1 << 4) +#define I2C_STOPIEN (1 << 5) +#define I2C_NAKRCVIEN (1 << 6) + +/* interrupt pending register */ +#define I2C_BTFIPD (1 << 0) +#define I2C_BRFIPD (1 << 1) +#define I2C_MBTFIPD (1 << 2) +#define I2C_MBRFIPD (1 << 3) +#define I2C_STARTIPD (1 << 4) +#define I2C_STOPIPD (1 << 5) +#define I2C_NAKRCVIPD (1 << 6) +#define I2C_IPD_ALL_CLEAN 0x7f + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h new file mode 100644 index 000000000..fb25504b1 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Rockchip Inc. + */ + +#ifndef _ASM_ARCH_LVDS_RK3288_H +#define _ASM_ARCH_LVDS_RK3288_H + +#ifndef __ASSEMBLY__ +#include +#endif + +#define RK3288_LVDS_CH0_REG0 0x00 +#define RK3288_LVDS_CH0_REG0_LVDS_EN BIT(7) +#define RK3288_LVDS_CH0_REG0_TTL_EN BIT(6) +#define RK3288_LVDS_CH0_REG0_LANECK_EN BIT(5) +#define RK3288_LVDS_CH0_REG0_LANE4_EN BIT(4) +#define RK3288_LVDS_CH0_REG0_LANE3_EN BIT(3) +#define RK3288_LVDS_CH0_REG0_LANE2_EN BIT(2) +#define RK3288_LVDS_CH0_REG0_LANE1_EN BIT(1) +#define RK3288_LVDS_CH0_REG0_LANE0_EN BIT(0) + +#define RK3288_LVDS_CH0_REG1 0x04 +#define RK3288_LVDS_CH0_REG1_LANECK_BIAS BIT(5) +#define RK3288_LVDS_CH0_REG1_LANE4_BIAS BIT(4) +#define RK3288_LVDS_CH0_REG1_LANE3_BIAS BIT(3) +#define RK3288_LVDS_CH0_REG1_LANE2_BIAS BIT(2) +#define RK3288_LVDS_CH0_REG1_LANE1_BIAS BIT(1) +#define RK3288_LVDS_CH0_REG1_LANE0_BIAS BIT(0) + +#define RK3288_LVDS_CH0_REG2 0x08 +#define RK3288_LVDS_CH0_REG2_RESERVE_ON BIT(7) +#define RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE BIT(6) +#define RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE BIT(5) +#define RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE BIT(4) +#define RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE BIT(3) +#define RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE BIT(2) +#define RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE BIT(1) +#define RK3288_LVDS_CH0_REG2_PLL_FBDIV8 BIT(0) + +#define RK3288_LVDS_CH0_REG3 0x0c +#define RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK 0xff + +#define RK3288_LVDS_CH0_REG4 0x10 +#define RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE BIT(5) +#define RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE BIT(4) +#define RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE BIT(3) +#define RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE BIT(2) +#define RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE BIT(1) +#define RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE BIT(0) + +#define RK3288_LVDS_CH0_REG5 0x14 +#define RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA BIT(5) +#define RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA BIT(4) +#define RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA BIT(3) +#define RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA BIT(2) +#define RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA BIT(1) +#define RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA BIT(0) + +#define RK3288_LVDS_CFG_REGC 0x30 +#define RK3288_LVDS_CFG_REGC_PLL_ENABLE 0x00 +#define RK3288_LVDS_CFG_REGC_PLL_DISABLE 0xff + +#define RK3288_LVDS_CH0_REGD 0x34 +#define RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK 0x1f + +#define RK3288_LVDS_CH0_REG20 0x80 +#define RK3288_LVDS_CH0_REG20_MSB 0x45 +#define RK3288_LVDS_CH0_REG20_LSB 0x44 + +#define RK3288_LVDS_CFG_REG21 0x84 +#define RK3288_LVDS_CFG_REG21_TX_ENABLE 0x92 +#define RK3288_LVDS_CFG_REG21_TX_DISABLE 0x00 + +/* fbdiv value is split over 2 registers, with bit8 in reg2 */ +#define RK3288_LVDS_PLL_FBDIV_REG2(_fbd) \ + (_fbd & BIT(8) ? RK3288_LVDS_CH0_REG2_PLL_FBDIV8 : 0) +#define RK3288_LVDS_PLL_FBDIV_REG3(_fbd) \ + (_fbd & RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK) +#define RK3288_LVDS_PLL_PREDIV_REGD(_pd) \ + (_pd & RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK) + +#define RK3288_LVDS_SOC_CON6_SEL_VOP_LIT BIT(3) + +#define LVDS_FMT_MASK (7 << 16) +#define LVDS_MSB (1 << 3) +#define LVDS_DUAL (1 << 4) +#define LVDS_FMT_1 (1 << 5) +#define LVDS_TTL_EN (1 << 6) +#define LVDS_START_PHASE_RST_1 (1 << 7) +#define LVDS_DCLK_INV (1 << 8) +#define LVDS_CH0_EN (1 << 11) +#define LVDS_CH1_EN (1 << 12) +#define LVDS_PWRDN (1 << 15) + +#define LVDS_24BIT (0 << 1) +#define LVDS_18BIT (1 << 1) + + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/misc.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/misc.h new file mode 100644 index 000000000..b6b03c934 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/misc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * RK3399: Architecture common definitions + * + * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/ + * Rohan Garg + */ + +int rockchip_cpuid_from_efuse(const u32 cpuid_offset, + const u32 cpuid_length, + u8 *cpuid); +int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length); +int rockchip_setup_macaddr(void); diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/periph.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/periph.h new file mode 100644 index 000000000..2191b7d43 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/periph.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2015 Google, Inc + */ + +#ifndef _ASM_ARCH_PERIPH_H +#define _ASM_ARCH_PERIPH_H + +/* + * The peripherals supported by the hardware. This is used to specify clocks + * and pinctrl settings. Some SoCs will not support all of these, but it + * provides a common reference for common drivers to use. + */ +enum periph_id { + PERIPH_ID_PWM0, + PERIPH_ID_PWM1, + PERIPH_ID_PWM2, + PERIPH_ID_PWM3, + PERIPH_ID_PWM4, + PERIPH_ID_I2C0, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, + PERIPH_ID_I2C8, + PERIPH_ID_SPI0, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SPI3, + PERIPH_ID_SPI4, + PERIPH_ID_SPI5, + PERIPH_ID_UART0, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + PERIPH_ID_UART3, + PERIPH_ID_UART4, + PERIPH_ID_LCDC0, + PERIPH_ID_LCDC1, + PERIPH_ID_SDMMC0, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC2, + PERIPH_ID_HDMI, + PERIPH_ID_GMAC, + PERIPH_ID_SFC, + PERIPH_ID_I2S, + + PERIPH_ID_COUNT, + + /* Some aliases */ + PERIPH_ID_EMMC = PERIPH_ID_SDMMC0, + PERIPH_ID_SDCARD = PERIPH_ID_SDMMC1, + PERIPH_ID_UART_BT = PERIPH_ID_UART0, + PERIPH_ID_UART_BB = PERIPH_ID_UART1, + PERIPH_ID_UART_DBG = PERIPH_ID_UART2, + PERIPH_ID_UART_GPS = PERIPH_ID_UART3, + PERIPH_ID_UART_EXP = PERIPH_ID_UART4, +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/pmu_rk3188.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/pmu_rk3188.h new file mode 100644 index 000000000..f7b9a0674 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/pmu_rk3188.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2016 Heiko Stuebner + */ + +#ifndef _ASM_ARCH_PMU_RK3188_H +#define _ASM_ARCH_PMU_RK3188_H + +struct rk3188_pmu { + u32 wakeup_cfg[2]; + u32 pwrdn_con; + u32 pwrdn_st; + + u32 int_con; + u32 int_st; + u32 misc_con; + + u32 osc_cnt; + u32 pll_cnt; + u32 pmu_cnt; + u32 ddrio_pwron_cnt; + u32 wakeup_rst_clr_cnt; + u32 scu_pwrdwn_cnt; + u32 scu_pwrup_cnt; + u32 misc_con1; + u32 gpio0_con; + + u32 sys_reg[4]; + u32 reserved0[4]; + u32 stop_int_dly; + u32 gpio0_p[2]; +}; +check_member(rk3188_pmu, gpio0_p[1], 0x0068); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/pmu_rk3288.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/pmu_rk3288.h new file mode 100644 index 000000000..8553d2eee --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/pmu_rk3288.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2015 Google, Inc + * + * Copyright 2014 Rockchip Inc. + */ + +#ifndef _ASM_ARCH_PMU_RK3288_H +#define _ASM_ARCH_PMU_RK3288_H + +struct rk3288_pmu { + u32 wakeup_cfg[2]; + u32 pwrdn_con; + u32 pwrdn_st; + + u32 idle_req; + u32 idle_st; + u32 pwrmode_con; + u32 pwr_state; + + u32 osc_cnt; + u32 pll_cnt; + u32 stabl_cnt; + u32 ddr0io_pwron_cnt; + + u32 ddr1io_pwron_cnt; + u32 core_pwrdn_cnt; + u32 core_pwrup_cnt; + u32 gpu_pwrdn_cnt; + + u32 gpu_pwrup_cnt; + u32 wakeup_rst_clr_cnt; + u32 sft_con; + u32 ddr_sref_st; + + u32 int_con; + u32 int_st; + u32 boot_addr_sel; + u32 grf_con; + + u32 gpio_sr; + u32 gpio0pull[3]; + + u32 gpio0drv[3]; + u32 gpio_op; + + u32 gpio0_sel18; /* 0x80 */ + u32 gpio0_iomux[4]; /* a, b, c, d */ + u32 sys_reg[4]; +}; +check_member(rk3288_pmu, sys_reg[3], 0x00a0); + +enum { + PMU_GPIO0_A = 0, + PMU_GPIO0_B, + PMU_GPIO0_C, + PMU_GPIO0_D, +}; + +/* PMU_GPIO0_B_IOMUX */ +enum { + GPIO0_B7_SHIFT = 14, + GPIO0_B7_MASK = 1, + GPIO0_B7_GPIOB7 = 0, + GPIO0_B7_I2C0PMU_SDA, + + GPIO0_B5_SHIFT = 10, + GPIO0_B5_MASK = 1, + GPIO0_B5_GPIOB5 = 0, + GPIO0_B5_CLK_27M, + + GPIO0_B2_SHIFT = 4, + GPIO0_B2_MASK = 1, + GPIO0_B2_GPIOB2 = 0, + GPIO0_B2_TSADC_INT, +}; + +/* PMU_GPIO0_C_IOMUX */ +enum { + GPIO0_C1_SHIFT = 2, + GPIO0_C1_MASK = 3, + GPIO0_C1_GPIOC1 = 0, + GPIO0_C1_TEST_CLKOUT, + GPIO0_C1_CLKT1_27M, + + GPIO0_C0_SHIFT = 0, + GPIO0_C0_MASK = 1, + GPIO0_C0_GPIOC0 = 0, + GPIO0_C0_I2C0PMU_SCL, +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h new file mode 100644 index 000000000..f1096dccc --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd. + * + */ + +#ifndef __SOC_ROCKCHIP_RK3399_PMU_H__ +#define __SOC_ROCKCHIP_RK3399_PMU_H__ + +struct rk3399_pmu_regs { + u32 pmu_wakeup_cfg[5]; + u32 pmu_pwrdn_con; + u32 pmu_pwrdn_st; + u32 pmu_pll_con; + u32 pmu_pwrmode_con; + u32 pmu_sft_con; + u32 pmu_int_con; + u32 pmu_int_st; + u32 pmu_gpio0_pos_int_con; + u32 pmu_gpio0_net_int_con; + u32 pmu_gpio1_pos_int_con; + u32 pmu_gpio1_net_int_con; + u32 pmu_gpio0_pos_int_st; + u32 pmu_gpio0_net_int_st; + u32 pmu_gpio1_pos_int_st; + u32 pmu_gpio1_net_int_st; + u32 pmu_pwrdn_inten; + u32 pmu_pwrdn_status; + u32 pmu_wakeup_status; + u32 pmu_bus_clr; + u32 pmu_bus_idle_req; + u32 pmu_bus_idle_st; + u32 pmu_bus_idle_ack; + u32 pmu_cci500_con; + u32 pmu_adb400_con; + u32 pmu_adb400_st; + u32 pmu_power_st; + u32 pmu_core_pwr_st; + u32 pmu_osc_cnt; + u32 pmu_plllock_cnt; + u32 pmu_pllrst_cnt; + u32 pmu_stable_cnt; + u32 pmu_ddrio_pwron_cnt; + u32 pmu_wakeup_rst_clr_cnt; + u32 pmu_ddr_sref_st; + u32 pmu_scu_l_pwrdn_cnt; + u32 pmu_scu_l_pwrup_cnt; + u32 pmu_scu_b_pwrdn_cnt; + u32 pmu_scu_b_pwrup_cnt; + u32 pmu_gpu_pwrdn_cnt; + u32 pmu_gpu_pwrup_cnt; + u32 pmu_center_pwrdn_cnt; + u32 pmu_center_pwrup_cnt; + u32 pmu_timeout_cnt; + u32 pmu_cpu0apm_con; + u32 pmu_cpu1apm_con; + u32 pmu_cpu2apm_con; + u32 pmu_cpu3apm_con; + u32 pmu_cpu0bpm_con; + u32 pmu_cpu1bpm_con; + u32 pmu_noc_auto_ena; + u32 pmu_pwrdn_con1; + u32 reserved0[0x4]; + u32 pmu_sys_reg_reg0; + u32 pmu_sys_reg_reg1; + u32 pmu_sys_reg_reg2; + u32 pmu_sys_reg_reg3; +}; + +check_member(rk3399_pmu_regs, pmu_sys_reg_reg3, 0xfc); + +#endif /* __SOC_ROCKCHIP_RK3399_PMU_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/pwm.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/pwm.h new file mode 100644 index 000000000..e8594055c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/pwm.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Google, Inc + * (C) Copyright 2008-2014 Rockchip Electronics + */ + +#ifndef _ASM_ARCH_PWM_H +#define _ASM_ARCH_PWM_H + +struct rockchip_pwm_regs { + unsigned long duty; + unsigned long period; + unsigned long cntr; + unsigned long ctrl; +}; + +#define PWM_CTRL_TIMER_EN (1 << 0) +#define PWM_CTRL_OUTPUT_EN (1 << 3) + +#define RK_PWM_DISABLE (0 << 0) +#define RK_PWM_ENABLE (1 << 0) + +#define PWM_ONE_SHOT (0 << 1) +#define PWM_CONTINUOUS (1 << 1) +#define RK_PWM_CAPTURE (1 << 2) + +#define PWM_DUTY_POSTIVE (1 << 3) +#define PWM_DUTY_NEGATIVE (0 << 3) +#define PWM_DUTY_MASK (1 << 3) + +#define PWM_INACTIVE_POSTIVE (1 << 4) +#define PWM_INACTIVE_NEGATIVE (0 << 4) +#define PWM_INACTIVE_MASK (1 << 4) + +#define PWM_OUTPUT_LEFT (0 << 5) +#define PWM_OUTPUT_CENTER (1 << 5) + +#define PWM_LOCK (1 << 6) +#define PWM_UNLOCK (0 << 6) + +#define PWM_LP_ENABLE (1 << 8) +#define PWM_LP_DISABLE (0 << 8) + +#define PWM_SEL_SCALE_CLK (1 << 9) +#define PWM_SEL_SRC_CLK (0 << 9) + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/qos_rk3288.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/qos_rk3288.h new file mode 100644 index 000000000..c24b090b0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/qos_rk3288.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Rockchip Inc. + */ +#ifndef _ASM_ARCH_QOS_RK3288_H +#define _ASM_ARCH_QOS_RK3288_H + +#define PRIORITY_HIGH_SHIFT 2 +#define PRIORITY_LOW_SHIFT 0 + +#define CPU_AXI_QOS_PRIORITY 0x08 + +#define VIO0_VOP_QOS 0xffad0400 +#define VIO1_VOP_QOS 0xffad0000 +#define VIO1_ISP_R_QOS 0xffad0900 +#define VIO1_ISP_W0_QOS 0xffad0100 +#define VIO1_ISP_W1_QOS 0xffad0180 + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h new file mode 100644 index 000000000..c13957a62 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h @@ -0,0 +1,194 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd + * author: Eric Gao + */ + +#ifndef ROCKCHIP_MIPI_DSI_H +#define ROCKCHIP_MIPI_DSI_H + +/* + * All these mipi controller register declaration provide reg address offset, + * bits width, bit offset for a specified register bits. With these message, we + * can set or clear every bits individually for a 32bit widthregister. We use + * DSI_HOST_BITS macro definition to combinat these message using the following + * format: val(32bit) = addr(16bit) | width(8bit) | offest(8bit) + * For example: + * #define SHUTDOWNZ DSI_HOST_BITS(0x004, 1, 0) + * means SHUTDOWNZ is a signal reg bit with bit offset qual 0,and it's reg addr + * offset is 0x004.The conbinat result = (0x004 << 16) | (1 << 8) | 0 + */ +#define ADDR_SHIFT 16 +#define BITS_SHIFT 8 +#define OFFSET_SHIFT 0 +#define DSI_HOST_BITS(addr, bits, bit_offset) \ +((addr << ADDR_SHIFT) | (bits << BITS_SHIFT) | (bit_offset << OFFSET_SHIFT)) + +/* DWC_DSI_VERSION_0x3133302A */ +#define VERSION DSI_HOST_BITS(0x000, 32, 0) +#define SHUTDOWNZ DSI_HOST_BITS(0x004, 1, 0) +#define TO_CLK_DIVISION DSI_HOST_BITS(0x008, 8, 8) +#define TX_ESC_CLK_DIVISION DSI_HOST_BITS(0x008, 8, 0) +#define DPI_VCID DSI_HOST_BITS(0x00c, 2, 0) +#define EN18_LOOSELY DSI_HOST_BITS(0x010, 1, 8) +#define DPI_COLOR_CODING DSI_HOST_BITS(0x010, 4, 0) +#define COLORM_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 4) +#define SHUTD_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 3) +#define HSYNC_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 2) +#define VSYNC_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 1) +#define DATAEN_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 0) +#define OUTVACT_LPCMD_TIME DSI_HOST_BITS(0x018, 8, 16) +#define INVACT_LPCMD_TIME DSI_HOST_BITS(0x018, 8, 0) +#define CRC_RX_EN DSI_HOST_BITS(0x02c, 1, 4) +#define ECC_RX_EN DSI_HOST_BITS(0x02c, 1, 3) +#define BTA_EN DSI_HOST_BITS(0x02c, 1, 2) +#define EOTP_RX_EN DSI_HOST_BITS(0x02c, 1, 1) +#define EOTP_TX_EN DSI_HOST_BITS(0x02c, 1, 0) +#define GEN_VID_RX DSI_HOST_BITS(0x030, 2, 0) +#define CMD_VIDEO_MODE DSI_HOST_BITS(0x034, 1, 0) +#define VPG_ORIENTATION DSI_HOST_BITS(0x038, 1, 24) +#define VPG_MODE DSI_HOST_BITS(0x038, 1, 20) +#define VPG_EN DSI_HOST_BITS(0x038, 1, 16) +#define LP_CMD_EN DSI_HOST_BITS(0x038, 1, 15) +#define FRAME_BTA_ACK_EN DSI_HOST_BITS(0x038, 1, 14) +#define LP_HFP_EN DSI_HOST_BITS(0x038, 1, 13) +#define LP_HBP_EN DSI_HOST_BITS(0x038, 1, 12) +#define LP_VACT_EN DSI_HOST_BITS(0x038, 1, 11) +#define LP_VFP_EN DSI_HOST_BITS(0x038, 1, 10) +#define LP_VBP_EN DSI_HOST_BITS(0x038, 1, 9) +#define LP_VSA_EN DSI_HOST_BITS(0x038, 1, 8) +#define VID_MODE_TYPE DSI_HOST_BITS(0x038, 2, 0) +#define VID_PKT_SIZE DSI_HOST_BITS(0x03c, 14, 0) +#define NUM_CHUNKS DSI_HOST_BITS(0x040, 13, 0) +#define NULL_PKT_SIZE DSI_HOST_BITS(0x044, 13, 0) +#define VID_HSA_TIME DSI_HOST_BITS(0x048, 12, 0) +#define VID_HBP_TIME DSI_HOST_BITS(0x04c, 12, 0) +#define VID_HLINE_TIME DSI_HOST_BITS(0x050, 15, 0) +#define VID_VSA_LINES DSI_HOST_BITS(0x054, 10, 0) +#define VID_VBP_LINES DSI_HOST_BITS(0x058, 10, 0) +#define VID_VFP_LINES DSI_HOST_BITS(0x05c, 10, 0) +#define VID_ACTIVE_LINES DSI_HOST_BITS(0x060, 14, 0) +#define EDPI_CMD_SIZE DSI_HOST_BITS(0x064, 16, 0) +#define MAX_RD_PKT_SIZE DSI_HOST_BITS(0x068, 1, 24) +#define DCS_LW_TX DSI_HOST_BITS(0x068, 1, 19) +#define DCS_SR_0P_TX DSI_HOST_BITS(0x068, 1, 18) +#define DCS_SW_1P_TX DSI_HOST_BITS(0x068, 1, 17) +#define DCS_SW_0P_TX DSI_HOST_BITS(0x068, 1, 16) +#define GEN_LW_TX DSI_HOST_BITS(0x068, 1, 14) +#define GEN_SR_2P_TX DSI_HOST_BITS(0x068, 1, 13) +#define GEN_SR_1P_TX DSI_HOST_BITS(0x068, 1, 12) +#define GEN_SR_0P_TX DSI_HOST_BITS(0x068, 1, 11) +#define GEN_SW_2P_TX DSI_HOST_BITS(0x068, 1, 10) +#define GEN_SW_1P_TX DSI_HOST_BITS(0x068, 1, 9) +#define GEN_SW_0P_TX DSI_HOST_BITS(0x068, 1, 8) +#define ACK_RQST_EN DSI_HOST_BITS(0x068, 1, 1) +#define TEAR_FX_EN DSI_HOST_BITS(0x068, 1, 0) +#define GEN_WC_MSBYTE DSI_HOST_BITS(0x06c, 14, 16) +#define GEN_WC_LSBYTE DSI_HOST_BITS(0x06c, 8, 8) +#define GEN_VC DSI_HOST_BITS(0x06c, 2, 6) +#define GEN_DT DSI_HOST_BITS(0x06c, 6, 0) +#define GEN_PLD_DATA DSI_HOST_BITS(0x070, 32, 0) +#define GEN_RD_CMD_BUSY DSI_HOST_BITS(0x074, 1, 6) +#define GEN_PLD_R_FULL DSI_HOST_BITS(0x074, 1, 5) +#define GEN_PLD_R_EMPTY DSI_HOST_BITS(0x074, 1, 4) +#define GEN_PLD_W_FULL DSI_HOST_BITS(0x074, 1, 3) +#define GEN_PLD_W_EMPTY DSI_HOST_BITS(0x074, 1, 2) +#define GEN_CMD_FULL DSI_HOST_BITS(0x074, 1, 1) +#define GEN_CMD_EMPTY DSI_HOST_BITS(0x074, 1, 0) +#define HSTX_TO_CNT DSI_HOST_BITS(0x078, 16, 16) +#define LPRX_TO_CNT DSI_HOST_BITS(0x078, 16, 0) +#define HS_RD_TO_CNT DSI_HOST_BITS(0x07c, 16, 0) +#define LP_RD_TO_CNT DSI_HOST_BITS(0x080, 16, 0) +#define PRESP_TO_MODE DSI_HOST_BITS(0x084, 1, 24) +#define HS_WR_TO_CNT DSI_HOST_BITS(0x084, 16, 0) +#define LP_WR_TO_CNT DSI_HOST_BITS(0x088, 16, 0) +#define BTA_TO_CNT DSI_HOST_BITS(0x08c, 16, 0) +#define AUTO_CLKLANE_CTRL DSI_HOST_BITS(0x094, 1, 1) +#define PHY_TXREQUESTCLKHS DSI_HOST_BITS(0x094, 1, 0) +#define PHY_HS2LP_TIME_CLK_LANE DSI_HOST_BITS(0x098, 10, 16) +#define PHY_HS2HS_TIME_CLK_LANE DSI_HOST_BITS(0x098, 10, 0) +#define PHY_HS2LP_TIME DSI_HOST_BITS(0x09c, 8, 24) +#define PHY_LP2HS_TIME DSI_HOST_BITS(0x09c, 8, 16) +#define MAX_RD_TIME DSI_HOST_BITS(0x09c, 15, 0) +#define PHY_FORCEPLL DSI_HOST_BITS(0x0a0, 1, 3) +#define PHY_ENABLECLK DSI_HOST_BITS(0x0a0, 1, 2) +#define PHY_RSTZ DSI_HOST_BITS(0x0a0, 1, 1) +#define PHY_SHUTDOWNZ DSI_HOST_BITS(0x0a0, 1, 0) +#define PHY_STOP_WAIT_TIME DSI_HOST_BITS(0x0a4, 8, 8) +#define N_LANES DSI_HOST_BITS(0x0a4, 2, 0) +#define PHY_TXEXITULPSLAN DSI_HOST_BITS(0x0a8, 1, 3) +#define PHY_TXREQULPSLAN DSI_HOST_BITS(0x0a8, 1, 2) +#define PHY_TXEXITULPSCLK DSI_HOST_BITS(0x0a8, 1, 1) +#define PHY_TXREQULPSCLK DSI_HOST_BITS(0x0a8, 1, 0) +#define PHY_TX_TRIGGERS DSI_HOST_BITS(0x0ac, 4, 0) +#define PHYSTOPSTATECLKLANE DSI_HOST_BITS(0x0b0, 1, 2) +#define PHYLOCK DSI_HOST_BITS(0x0b0, 1, 0) +#define PHY_TESTCLK DSI_HOST_BITS(0x0b4, 1, 1) +#define PHY_TESTCLR DSI_HOST_BITS(0x0b4, 1, 0) +#define PHY_TESTEN DSI_HOST_BITS(0x0b8, 1, 16) +#define PHY_TESTDOUT DSI_HOST_BITS(0x0b8, 8, 8) +#define PHY_TESTDIN DSI_HOST_BITS(0x0b8, 8, 0) +#define PHY_TEST_CTRL1 DSI_HOST_BITS(0x0b8, 17, 0) +#define PHY_TEST_CTRL0 DSI_HOST_BITS(0x0b4, 2, 0) +#define INT_ST0 DSI_HOST_BITS(0x0bc, 21, 0) +#define INT_ST1 DSI_HOST_BITS(0x0c0, 18, 0) +#define INT_MKS0 DSI_HOST_BITS(0x0c4, 21, 0) +#define INT_MKS1 DSI_HOST_BITS(0x0c8, 18, 0) +#define INT_FORCE0 DSI_HOST_BITS(0x0d8, 21, 0) +#define INT_FORCE1 DSI_HOST_BITS(0x0dc, 18, 0) + +#define CODE_HS_RX_CLOCK 0x34 +#define CODE_HS_RX_LANE0 0x44 +#define CODE_HS_RX_LANE1 0x54 +#define CODE_HS_RX_LANE2 0x84 +#define CODE_HS_RX_LANE3 0x94 + +#define CODE_PLL_VCORANGE_VCOCAP 0x10 +#define CODE_PLL_CPCTRL 0x11 +#define CODE_PLL_LPF_CP 0x12 +#define CODE_PLL_INPUT_DIV_RAT 0x17 +#define CODE_PLL_LOOP_DIV_RAT 0x18 +#define CODE_PLL_INPUT_LOOP_DIV_RAT 0x19 +#define CODE_BANDGAP_BIAS_CTRL 0x20 +#define CODE_TERMINATION_CTRL 0x21 +#define CODE_AFE_BIAS_BANDGAP_ANOLOG 0x22 + +#define CODE_HSTXDATALANEREQUSETSTATETIME 0x70 +#define CODE_HSTXDATALANEPREPARESTATETIME 0x71 +#define CODE_HSTXDATALANEHSZEROSTATETIME 0x72 + +/* Transmission mode between vop and MIPI controller */ +enum vid_mode_type_t { + NON_BURST_SYNC_PLUSE = 0, + NON_BURST_SYNC_EVENT, + BURST_MODE, +}; + +enum cmd_video_mode { + VIDEO_MODE = 0, + CMD_MODE, +}; + +/* Indicate MIPI DSI color mode */ +enum dpi_color_coding { + DPI_16BIT_CFG_1 = 0, + DPI_16BIT_CFG_2, + DPI_16BIT_CFG_3, + DPI_18BIT_CFG_1, + DPI_18BIT_CFG_2, + DPI_24BIT, + DPI_20BIT_YCBCR_422_LP, + DPI_24BIT_YCBCR_422, + DPI_16BIT_YCBCR_422, + DPI_30BIT, + DPI_36BIT, + DPI_12BIT_YCBCR_420, +}; + +/* Indicate which VOP the MIPI DSI use, bit or little one */ +enum vop_id { + VOP_B = 0, + VOP_L, +}; + +#endif /* end of ROCKCHIP_MIPI_DSI_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram.h new file mode 100644 index 000000000..cf2a7b7d1 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. + */ + +#ifndef _ASM_ARCH_SDRAM_H +#define _ASM_ARCH_SDRAM_H + +enum { + DDR4 = 0, + DDR3 = 0x3, + LPDDR2 = 0x5, + LPDDR3 = 0x6, + LPDDR4 = 0x7, + UNUSED = 0xFF +}; + +/* + * sys_reg2 bitfield struct + * [31] row_3_4_ch1 + * [30] row_3_4_ch0 + * [29:28] chinfo + * [27] rank_ch1 + * [26:25] col_ch1 + * [24] bk_ch1 + * [23:22] low bits of cs0_row_ch1 + * [21:20] low bits of cs1_row_ch1 + * [19:18] bw_ch1 + * [17:16] dbw_ch1; + * [15:13] ddrtype + * [12] channelnum + * [11] rank_ch0 + * [10:9] col_ch0, + * [8] bk_ch0 + * [7:6] low bits of cs0_row_ch0 + * [5:4] low bits of cs1_row_ch0 + * [3:2] bw_ch0 + * [1:0] dbw_ch0 + */ +#define SYS_REG_DDRTYPE_SHIFT 13 +#define SYS_REG_DDRTYPE_MASK 7 +#define SYS_REG_NUM_CH_SHIFT 12 +#define SYS_REG_NUM_CH_MASK 1 +#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) +#define SYS_REG_ROW_3_4_MASK 1 +#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) +#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) +#define SYS_REG_RANK_MASK 1 +#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) +#define SYS_REG_COL_MASK 3 +#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) +#define SYS_REG_BK_MASK 1 +#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) +#define SYS_REG_CS0_ROW_MASK 3 +#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) +#define SYS_REG_CS1_ROW_MASK 3 +#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) +#define SYS_REG_BW_MASK 3 +#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) +#define SYS_REG_DBW_MASK 3 + +/* + * sys_reg3 bitfield struct + * [7] high bit of cs0_row_ch1 + * [6] high bit of cs1_row_ch1 + * [5] high bit of cs0_row_ch0 + * [4] high bit of cs1_row_ch0 + * [3:2] cs1_col_ch1 + * [1:0] cs1_col_ch0 + */ +#define SYS_REG_VERSION_SHIFT 28 +#define SYS_REG_VERSION_MASK 0xf +#define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) +#define SYS_REG_EXTEND_CS0_ROW_MASK 1 +#define SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) (4 + (ch) * 2) +#define SYS_REG_EXTEND_CS1_ROW_MASK 1 +#define SYS_REG_CS1_COL_SHIFT(ch) (0 + (ch) * 2) +#define SYS_REG_CS1_COL_MASK 3 + +/* Get sdram size decode from reg */ +size_t rockchip_sdram_size(phys_addr_t reg); + +/* Called by U-Boot board_init_r for Rockchip SoCs */ +int dram_init(void); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_common.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_common.h new file mode 100644 index 000000000..5efa6e944 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Rockchip Electronics Co., Ltd + */ + +#ifndef _ASM_ARCH_SDRAM_COMMON_H +#define _ASM_ARCH_SDRAM_COMMON_H + +#ifndef MHZ +#define MHZ (1000 * 1000) +#endif + +#define PATTERN (0x5aa5f00f) + +#define MIN(a, b) (((a) > (b)) ? (b) : (a)) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) + +struct sdram_cap_info { + unsigned int rank; + /* dram column number, 0 means this channel is invalid */ + unsigned int col; + /* dram bank number, 3:8bank, 2:4bank */ + unsigned int bk; + /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ + unsigned int bw; + /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ + unsigned int dbw; + /* + * row_3_4 = 1: 6Gb or 12Gb die + * row_3_4 = 0: normal die, power of 2 + */ + unsigned int row_3_4; + unsigned int cs0_row; + unsigned int cs1_row; + unsigned int cs0_high16bit_row; + unsigned int cs1_high16bit_row; + unsigned int ddrconfig; +}; + +struct sdram_base_params { + unsigned int ddr_freq; + unsigned int dramtype; + unsigned int num_channels; + unsigned int stride; + unsigned int odt; +}; + +#define DDR_SYS_REG_VERSION (0x2) +/* + * sys_reg2 bitfield struct + * [31] row_3_4_ch1 + * [30] row_3_4_ch0 + * [29:28] chinfo + * [27] rank_ch1 + * [26:25] col_ch1 + * [24] bk_ch1 + * [23:22] cs0_row_ch1 + * [21:20] cs1_row_ch1 + * [19:18] bw_ch1 + * [17:16] dbw_ch1; + * [15:13] ddrtype + * [12] channelnum + * [11] rank_ch0 + * [10:9] col_ch0 + * [8] bk_ch0 + * [7:6] cs0_row_ch0 + * [5:4] cs1_row_ch0 + * [3:2] bw_ch0 + * [1:0] dbw_ch0 + */ +#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) +#define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) +#define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) +#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) +#define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7) +#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) +#define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1)) +#define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + ((ch) * 16))) +#define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + 16 * (ch))) & 0x1)) +#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16))) +#define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + 16 * (ch))) & 0x3)) +#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \ + (8 + ((ch) * 16))) +#define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + 16 * (ch))) & 0x1)) +#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + ((ch) * 16))) +#define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + 16 * (ch))) & 0x3)) +#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16))) +#define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + 16 * (ch))) & 0x3)) +/* sys reg 3 */ +#define SYS_REG_ENC_VERSION(n) ((n) << 28) +#define SYS_REG_DEC_VERSION(n) (((n) >> 28) & 0xf) +#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \ + (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \ + (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ + (5 + 2 * (ch)); \ + } while (0) + +#define SYS_REG_DEC_CS0_ROW(os_reg2, os_reg3, ch) \ + ((((((os_reg2) >> (6 + 16 * (ch)) & 0x3) | \ + ((((os_reg3) >> (5 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12) + +#define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \ + (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \ + (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \ + (os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \ + (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ + (4 + 2 * (ch)); \ + } while (0) + +#define SYS_REG_DEC_CS1_ROW(os_reg2, os_reg3, ch) \ + ((((((os_reg2) >> (4 + 16 * (ch)) & 0x3) | \ + ((((os_reg3) >> (4 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12) + +#define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << (0 + 2 * (ch))) +#define SYS_REG_DEC_CS1_COL(n, ch) (9 + (((n) >> (0 + 2 * (ch))) & 0x3)) + +void sdram_print_dram_type(unsigned char dramtype); +void sdram_print_ddr_info(struct sdram_cap_info *cap_info, + struct sdram_base_params *base); +void sdram_print_stride(unsigned int stride); + +void sdram_org_config(struct sdram_cap_info *cap_info, + struct sdram_base_params *base, + u32 *p_os_reg2, u32 *p_os_reg3, u32 channel); + +int sdram_detect_bw(struct sdram_cap_info *cap_info); +int sdram_detect_cs(struct sdram_cap_info *cap_info); +int sdram_detect_col(struct sdram_cap_info *cap_info, + u32 coltmp); +int sdram_detect_bank(struct sdram_cap_info *cap_info, + u32 coltmp, u32 bktmp); +int sdram_detect_bg(struct sdram_cap_info *cap_info, + u32 coltmp); +int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type); +int sdram_detect_row(struct sdram_cap_info *cap_info, + u32 coltmp, u32 bktmp, u32 rowtmp); +int sdram_detect_row_3_4(struct sdram_cap_info *cap_info, + u32 coltmp, u32 bktmp); +int sdram_detect_high_row(struct sdram_cap_info *cap_info); +int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type); +u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type); +void sdram_copy_to_reg(u32 *dest, const u32 *src, u32 n); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_msch.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_msch.h new file mode 100644 index 000000000..cfb3d9cc8 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_msch.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef _ASM_ARCH_SDRAM_MSCH_H +#define _ASM_ARCH_SDRAM_MSCH_H + +union noc_ddrtiminga0 { + u32 d32; + struct { + unsigned acttoact : 6; + unsigned reserved0 : 2; + unsigned rdtomiss : 6; + unsigned reserved1 : 2; + unsigned wrtomiss : 6; + unsigned reserved2 : 2; + unsigned readlatency : 8; + } b; +}; + +union noc_ddrtimingb0 { + u32 d32; + struct { + unsigned rdtowr : 5; + unsigned reserved0 : 3; + unsigned wrtord : 5; + unsigned reserved1 : 3; + unsigned rrd : 4; + unsigned reserved2 : 4; + unsigned faw : 6; + unsigned reserved3 : 2; + } b; +}; + +union noc_ddrtimingc0 { + u32 d32; + struct { + unsigned burstpenalty : 4; + unsigned reserved0 : 4; + unsigned wrtomwr : 6; + unsigned reserved1 : 18; + } b; +}; + +union noc_devtodev0 { + u32 d32; + struct { + unsigned busrdtord : 3; + unsigned reserved0 : 1; + unsigned busrdtowr : 3; + unsigned reserved1 : 1; + unsigned buswrtord : 3; + unsigned reserved2 : 1; + unsigned buswrtowr : 3; + unsigned reserved3 : 17; + } b; +}; + +union noc_ddrmode { + u32 d32; + struct { + unsigned autoprecharge : 1; + unsigned bypassfiltering : 1; + unsigned fawbank : 1; + unsigned burstsize : 2; + unsigned mwrsize : 2; + unsigned reserved2 : 1; + unsigned forceorder : 8; + unsigned forceorderstate : 8; + unsigned reserved3 : 8; + } b; +}; + +union noc_ddr4timing { + u32 d32; + struct { + unsigned ccdl : 3; + unsigned wrtordl : 5; + unsigned rrdl : 4; + unsigned reserved1 : 20; + } b; +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h new file mode 100644 index 000000000..3a3657789 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Rockchip Electronics Co., Ltd + */ + +#ifndef _ASM_ARCH_SDRAM_PCTL_PX30_H +#define _ASM_ARCH_SDRAM_PCTL_PX30_H +#include + +#ifndef __ASSEMBLY__ +#include +#endif + +struct ddr_pctl_regs { + u32 pctl[30][2]; +}; + +/* ddr pctl registers define */ +#define DDR_PCTL2_MSTR 0x0 +#define DDR_PCTL2_STAT 0x4 +#define DDR_PCTL2_MSTR1 0x8 +#define DDR_PCTL2_MRCTRL0 0x10 +#define DDR_PCTL2_MRCTRL1 0x14 +#define DDR_PCTL2_MRSTAT 0x18 +#define DDR_PCTL2_MRCTRL2 0x1c +#define DDR_PCTL2_DERATEEN 0x20 +#define DDR_PCTL2_DERATEINT 0x24 +#define DDR_PCTL2_PWRCTL 0x30 +#define DDR_PCTL2_PWRTMG 0x34 +#define DDR_PCTL2_HWLPCTL 0x38 +#define DDR_PCTL2_RFSHCTL0 0x50 +#define DDR_PCTL2_RFSHCTL1 0x54 +#define DDR_PCTL2_RFSHCTL2 0x58 +#define DDR_PCTL2_RFSHCTL4 0x5c +#define DDR_PCTL2_RFSHCTL3 0x60 +#define DDR_PCTL2_RFSHTMG 0x64 +#define DDR_PCTL2_RFSHTMG1 0x68 +#define DDR_PCTL2_RFSHCTL5 0x6c +#define DDR_PCTL2_INIT0 0xd0 +#define DDR_PCTL2_INIT1 0xd4 +#define DDR_PCTL2_INIT2 0xd8 +#define DDR_PCTL2_INIT3 0xdc +#define DDR_PCTL2_INIT4 0xe0 +#define DDR_PCTL2_INIT5 0xe4 +#define DDR_PCTL2_INIT6 0xe8 +#define DDR_PCTL2_INIT7 0xec +#define DDR_PCTL2_DIMMCTL 0xf0 +#define DDR_PCTL2_RANKCTL 0xf4 +#define DDR_PCTL2_CHCTL 0xfc +#define DDR_PCTL2_DRAMTMG0 0x100 +#define DDR_PCTL2_DRAMTMG1 0x104 +#define DDR_PCTL2_DRAMTMG2 0x108 +#define DDR_PCTL2_DRAMTMG3 0x10c +#define DDR_PCTL2_DRAMTMG4 0x110 +#define DDR_PCTL2_DRAMTMG5 0x114 +#define DDR_PCTL2_DRAMTMG6 0x118 +#define DDR_PCTL2_DRAMTMG7 0x11c +#define DDR_PCTL2_DRAMTMG8 0x120 +#define DDR_PCTL2_DRAMTMG9 0x124 +#define DDR_PCTL2_DRAMTMG10 0x128 +#define DDR_PCTL2_DRAMTMG11 0x12c +#define DDR_PCTL2_DRAMTMG12 0x130 +#define DDR_PCTL2_DRAMTMG13 0x134 +#define DDR_PCTL2_DRAMTMG14 0x138 +#define DDR_PCTL2_DRAMTMG15 0x13c +#define DDR_PCTL2_DRAMTMG16 0x140 +#define DDR_PCTL2_ZQCTL0 0x180 +#define DDR_PCTL2_ZQCTL1 0x184 +#define DDR_PCTL2_ZQCTL2 0x188 +#define DDR_PCTL2_ZQSTAT 0x18c +#define DDR_PCTL2_DFITMG0 0x190 +#define DDR_PCTL2_DFITMG1 0x194 +#define DDR_PCTL2_DFILPCFG0 0x198 +#define DDR_PCTL2_DFILPCFG1 0x19c +#define DDR_PCTL2_DFIUPD0 0x1a0 +#define DDR_PCTL2_DFIUPD1 0x1a4 +#define DDR_PCTL2_DFIUPD2 0x1a8 +#define DDR_PCTL2_DFIMISC 0x1b0 +#define DDR_PCTL2_DFITMG2 0x1b4 +#define DDR_PCTL2_DFITMG3 0x1b8 +#define DDR_PCTL2_DFISTAT 0x1bc +#define DDR_PCTL2_DBICTL 0x1c0 +#define DDR_PCTL2_ADDRMAP0 0x200 +#define DDR_PCTL2_ADDRMAP1 0x204 +#define DDR_PCTL2_ADDRMAP2 0x208 +#define DDR_PCTL2_ADDRMAP3 0x20c +#define DDR_PCTL2_ADDRMAP4 0x210 +#define DDR_PCTL2_ADDRMAP5 0x214 +#define DDR_PCTL2_ADDRMAP6 0x218 +#define DDR_PCTL2_ADDRMAP7 0x21c +#define DDR_PCTL2_ADDRMAP8 0x220 +#define DDR_PCTL2_ADDRMAP9 0x224 +#define DDR_PCTL2_ADDRMAP10 0x228 +#define DDR_PCTL2_ADDRMAP11 0x22c +#define DDR_PCTL2_ODTCFG 0x240 +#define DDR_PCTL2_ODTMAP 0x244 +#define DDR_PCTL2_SCHED 0x250 +#define DDR_PCTL2_SCHED1 0x254 +#define DDR_PCTL2_PERFHPR1 0x25c +#define DDR_PCTL2_PERFLPR1 0x264 +#define DDR_PCTL2_PERFWR1 0x26c +#define DDR_PCTL2_DQMAP0 0x280 +#define DDR_PCTL2_DQMAP1 0x284 +#define DDR_PCTL2_DQMAP2 0x288 +#define DDR_PCTL2_DQMAP3 0x28c +#define DDR_PCTL2_DQMAP4 0x290 +#define DDR_PCTL2_DQMAP5 0x294 +#define DDR_PCTL2_DBG0 0x300 +#define DDR_PCTL2_DBG1 0x304 +#define DDR_PCTL2_DBGCAM 0x308 +#define DDR_PCTL2_DBGCMD 0x30c +#define DDR_PCTL2_DBGSTAT 0x310 +#define DDR_PCTL2_SWCTL 0x320 +#define DDR_PCTL2_SWSTAT 0x324 +#define DDR_PCTL2_POISONCFG 0x36c +#define DDR_PCTL2_POISONSTAT 0x370 +#define DDR_PCTL2_ADVECCINDEX 0x374 +#define DDR_PCTL2_ADVECCSTAT 0x378 +#define DDR_PCTL2_PSTAT 0x3fc +#define DDR_PCTL2_PCCFG 0x400 +#define DDR_PCTL2_PCFGR_n 0x404 +#define DDR_PCTL2_PCFGW_n 0x408 +#define DDR_PCTL2_PCTRL_n 0x490 + +/* PCTL2_MRSTAT */ +#define MR_WR_BUSY BIT(0) + +void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num); +int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg, + u32 dramtype); +int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate, + u32 dramtype); + +u32 pctl_dis_zqcs_aref(void __iomem *pctl_base); +void pctl_rest_zqcs_aref(void __iomem *pctl_base, u32 dis_auto_zq); + +u32 pctl_remodify_sdram_params(struct ddr_pctl_regs *pctl_regs, + struct sdram_cap_info *cap_info, + u32 dram_type); +int pctl_cfg(void __iomem *pctl_base, struct ddr_pctl_regs *pctl_regs, + u32 sr_idle, u32 pd_idle); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_phy_px30.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_phy_px30.h new file mode 100644 index 000000000..a033a1853 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_phy_px30.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Rockchip Electronics Co., Ltd + */ + +#ifndef _ASM_ARCH_SDRAM_PHY_PX30_H +#define _ASM_ARCH_SDRAM_PHY_PX30_H +#include +#include + +#ifndef __ASSEMBLY__ +#include +#endif + +struct ddr_phy_regs { + u32 phy[5][2]; +}; + +#define PHY_REG(base, n) ((base) + 4 * (n)) + +/* PHY_REG0 */ +#define DIGITAL_DERESET BIT(3) +#define ANALOG_DERESET BIT(2) +#define DIGITAL_RESET (0 << 3) +#define ANALOG_RESET (0 << 2) + +/* PHY_REG1 */ +#define PHY_DDR2 (0) +#define PHY_LPDDR2 (1) +#define PHY_DDR3 (2) +#define PHY_LPDDR3 (3) +#define PHY_DDR4 (4) +#define PHY_BL_4 (0 << 2) +#define PHY_BL_8 BIT(2) + +/* PHY_REG2 */ +#define PHY_DTT_EN BIT(0) +#define PHY_DTT_DISB (0 << 0) +#define PHY_WRITE_LEVELING_EN BIT(2) +#define PHY_WRITE_LEVELING_DISB (0 << 2) +#define PHY_SELECT_CS0 (2) +#define PHY_SELECT_CS1 (1) +#define PHY_SELECT_CS0_1 (0) +#define PHY_WRITE_LEVELING_SELECTCS(n) ((n) << 6) +#define PHY_DATA_TRAINING_SELECTCS(n) ((n) << 4) + +struct ddr_phy_skew { + u32 a0_a1_skew[15]; + u32 cs0_dm0_skew[11]; + u32 cs0_dm1_skew[11]; + u32 cs0_dm2_skew[11]; + u32 cs0_dm3_skew[11]; + u32 cs1_dm0_skew[11]; + u32 cs1_dm1_skew[11]; + u32 cs1_dm2_skew[11]; + u32 cs1_dm3_skew[11]; +}; + +void phy_soft_reset(void __iomem *phy_base); +void phy_dram_set_bw(void __iomem *phy_base, u32 bw); +void phy_cfg(void __iomem *phy_base, + struct ddr_phy_regs *phy_regs, struct ddr_phy_skew *skew, + struct sdram_base_params *base, u32 bw); +int phy_data_training(void __iomem *phy_base, u32 cs, u32 dramtype); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_phy_ron_rtt_px30.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_phy_ron_rtt_px30.h new file mode 100644 index 000000000..9c1523204 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_phy_ron_rtt_px30.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Rockchip Electronics Co., Ltd + */ + +#ifndef _ASM_ARCH_SDRAM_PHY_RON_RTT_PX30_H +#define _ASM_ARCH_SDRAM_PHY_RON_RTT_PX30_H + +#define PHY_DDR3_RON_RTT_DISABLE (0) +#define PHY_DDR3_RON_RTT_451ohm (1) +#define PHY_DDR3_RON_RTT_225ohm (2) +#define PHY_DDR3_RON_RTT_150ohm (3) +#define PHY_DDR3_RON_RTT_112ohm (4) +#define PHY_DDR3_RON_RTT_90ohm (5) +#define PHY_DDR3_RON_RTT_75ohm (6) +#define PHY_DDR3_RON_RTT_64ohm (7) +#define PHY_DDR3_RON_RTT_56ohm (16) +#define PHY_DDR3_RON_RTT_50ohm (17) +#define PHY_DDR3_RON_RTT_45ohm (18) +#define PHY_DDR3_RON_RTT_41ohm (19) +#define PHY_DDR3_RON_RTT_37ohm (20) +#define PHY_DDR3_RON_RTT_34ohm (21) +#define PHY_DDR3_RON_RTT_33ohm (22) +#define PHY_DDR3_RON_RTT_30ohm (23) +#define PHY_DDR3_RON_RTT_28ohm (24) +#define PHY_DDR3_RON_RTT_26ohm (25) +#define PHY_DDR3_RON_RTT_25ohm (26) +#define PHY_DDR3_RON_RTT_23ohm (27) +#define PHY_DDR3_RON_RTT_22ohm (28) +#define PHY_DDR3_RON_RTT_21ohm (29) +#define PHY_DDR3_RON_RTT_20ohm (30) +#define PHY_DDR3_RON_RTT_19ohm (31) + +#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0) +#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1) +#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2) +#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3) +#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4) +#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5) +#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6) +#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7) +#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16) +#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17) +#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18) +#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19) +#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20) +#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21) +#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22) +#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23) +#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24) +#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25) +#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26) +#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27) +#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28) +#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29) +#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30) +#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31) + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_px30.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_px30.h new file mode 100644 index 000000000..2ab8e97ae --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_px30.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Rockchip Electronics Co., Ltd + */ + +#ifndef _ASM_ARCH_SDRAM_PX30_H +#define _ASM_ARCH_SDRAM_PX30_H +#include +#include +#include +#include +#include + +#define SR_IDLE 93 +#define PD_IDLE 13 + +/* PMUGRF */ +#define PMUGRF_OS_REG0 (0x200) +#define PMUGRF_OS_REG(n) (PMUGRF_OS_REG0 + (n) * 4) + +/* DDR GRF */ +#define DDR_GRF_CON(n) (0 + (n) * 4) +#define DDR_GRF_STATUS_BASE (0X100) +#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) +#define DDR_GRF_LP_CON (0x20) + +#define SPLIT_MODE_32_L16_VALID (0) +#define SPLIT_MODE_32_H16_VALID (1) +#define SPLIT_MODE_16_L8_VALID (2) +#define SPLIT_MODE_16_H8_VALID (3) + +#define DDR_GRF_SPLIT_CON (0x8) +#define SPLIT_MODE_MASK (0x3) +#define SPLIT_MODE_OFFSET (9) +#define SPLIT_BYPASS_MASK (1) +#define SPLIT_BYPASS_OFFSET (8) +#define SPLIT_SIZE_MASK (0xff) +#define SPLIT_SIZE_OFFSET (0) + +/* CRU define */ +/* CRU_PLL_CON0 */ +#define PB(n) ((0x1 << (15 + 16)) | ((n) << 15)) +#define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12)) +#define FBDIV(n) ((0xFFF << 16) | (n)) + +/* CRU_PLL_CON1 */ +#define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15)) +#define RST(n) ((0x1 << (14 + 16)) | ((n) << 14)) +#define PD(n) ((0x1 << (13 + 16)) | ((n) << 13)) +#define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12)) +#define LOCK(n) (((n) >> 10) & 0x1) +#define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6)) +#define REFDIV(n) ((0x3F << 16) | (n)) + +/* CRU_MODE */ +#define CLOCK_FROM_XIN_OSC (0) +#define CLOCK_FROM_PLL (1) +#define CLOCK_FROM_RTC_32K (2) +#define DPLL_MODE(n) ((0x3 << (4 + 16)) | ((n) << 4)) + +/* CRU_SOFTRESET_CON1 */ +#define upctl2_psrstn_req(n) (((0x1 << 6) << 16) | ((n) << 6)) +#define upctl2_asrstn_req(n) (((0x1 << 5) << 16) | ((n) << 5)) +#define upctl2_srstn_req(n) (((0x1 << 4) << 16) | ((n) << 4)) + +/* CRU_SOFTRESET_CON2 */ +#define ddrphy_psrstn_req(n) (((0x1 << 2) << 16) | ((n) << 2)) +#define ddrphy_srstn_req(n) (((0x1 << 0) << 16) | ((n) << 0)) + +/* CRU register */ +#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) +#define CRU_MODE (0xa0) +#define CRU_GLB_CNT_TH (0xb0) +#define CRU_CLKSEL_CON_BASE 0x100 +#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON_BASE + ((i) * 4)) +#define CRU_CLKGATE_CON_BASE 0x200 +#define CRU_CLKGATE_CON(i) (CRU_CLKGATE_CON_BASE + ((i) * 4)) +#define CRU_CLKSFTRST_CON_BASE 0x300 +#define CRU_CLKSFTRST_CON(i) (CRU_CLKSFTRST_CON_BASE + ((i) * 4)) + +struct px30_ddr_grf_regs { + u32 ddr_grf_con[4]; + u32 reserved1[(0x20 - 0x10) / 4]; + u32 ddr_grf_lp_con; + u32 reserved2[(0x100 - 0x24) / 4]; + u32 ddr_grf_status[11]; +}; + +struct msch_regs { + u32 coreid; + u32 revisionid; + u32 deviceconf; + u32 devicesize; + u32 ddrtiminga0; + u32 ddrtimingb0; + u32 ddrtimingc0; + u32 devtodev0; + u32 reserved1[(0x110 - 0x20) / 4]; + u32 ddrmode; + u32 ddr4timing; + u32 reserved2[(0x1000 - 0x118) / 4]; + u32 agingx0; + u32 reserved3[(0x1040 - 0x1004) / 4]; + u32 aging0; + u32 aging1; + u32 aging2; + u32 aging3; +}; + +struct sdram_msch_timings { + union noc_ddrtiminga0 ddrtiminga0; + union noc_ddrtimingb0 ddrtimingb0; + union noc_ddrtimingc0 ddrtimingc0; + union noc_devtodev0 devtodev0; + union noc_ddrmode ddrmode; + union noc_ddr4timing ddr4timing; + u32 agingx0; +}; + +struct px30_sdram_channel { + struct sdram_cap_info cap_info; + struct sdram_msch_timings noc_timings; +}; + +struct px30_sdram_params { + struct px30_sdram_channel ch; + struct sdram_base_params base; + struct ddr_pctl_regs pctl_regs; + struct ddr_phy_regs phy_regs; + struct ddr_phy_skew *skew; +}; + +int sdram_init(void); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h new file mode 100644 index 000000000..46298165f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h @@ -0,0 +1,338 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + */ +#ifndef _ASM_ARCH_SDRAM_RK3036_H +#define _ASM_ARCH_SDRAM_RK3036_H + +struct rk3036_ddr_pctl { + u32 scfg; + u32 sctl; + u32 stat; + u32 intrstat; + u32 reserved0[12]; + u32 mcmd; + u32 powctl; + u32 powstat; + u32 cmdtstat; + u32 cmdtstaten; + u32 reserved1[3]; + u32 mrrcfg0; + u32 mrrstat0; + u32 mrrstat1; + u32 reserved2[4]; + u32 mcfg1; + u32 mcfg; + u32 ppcfg; + u32 mstat; + u32 lpddr2zqcfg; + u32 reserved3; + u32 dtupdes; + u32 dtuna; + u32 dtune; + u32 dtuprd0; + u32 dtuprd1; + u32 dtuprd2; + u32 dtuprd3; + u32 dtuawdt; + u32 reserved4[3]; + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 reserved5[47]; + u32 dtuwactl; + u32 dturactl; + u32 dtucfg; + u32 dtuectl; + u32 dtuwd0; + u32 dtuwd1; + u32 dtuwd2; + u32 dtuwd3; + u32 dtuwdm; + u32 dturd0; + u32 dturd1; + u32 dturd2; + u32 dturd3; + u32 dtulfsrwd; + u32 dtulfsrrd; + u32 dtueaf; + u32 dfitctrldelay; + u32 dfiodtcfg; + u32 dfiodtcfg1; + u32 dfiodtrankmap; + u32 dfitphywrdata; + u32 dfitphywrlat; + u32 reserved7[2]; + u32 dfitrddataen; + u32 dfitphyrdlat; + u32 reserved8[2]; + u32 dfitphyupdtype0; + u32 dfitphyupdtype1; + u32 dfitphyupdtype2; + u32 dfitphyupdtype3; + u32 dfitctrlupdmin; + u32 dfitctrlupdmax; + u32 dfitctrlupddly; + u32 reserved9; + u32 dfiupdcfg; + u32 dfitrefmski; + u32 dfitctrlupdi; + u32 reserved10[4]; + u32 dfitrcfg0; + u32 dfitrstat0; + u32 dfitrwrlvlen; + u32 dfitrrdlvlen; + u32 dfitrrdlvlgateen; + u32 dfiststat0; + u32 dfistcfg0; + u32 dfistcfg1; + u32 reserved11; + u32 dfitdramclken; + u32 dfitdramclkdis; + u32 dfistcfg2; + u32 dfistparclr; + u32 dfistparlog; + u32 reserved12[3]; + u32 dfilpcfg0; + u32 reserved13[3]; + u32 dfitrwrlvlresp0; + u32 dfitrwrlvlresp1; + u32 dfitrwrlvlresp2; + u32 dfitrrdlvlresp0; + u32 dfitrrdlvlresp1; + u32 dfitrrdlvlresp2; + u32 dfitrwrlvldelay0; + u32 dfitrwrlvldelay1; + u32 dfitrwrlvldelay2; + u32 dfitrrdlvldelay0; + u32 dfitrrdlvldelay1; + u32 dfitrrdlvldelay2; + u32 dfitrrdlvlgatedelay0; + u32 dfitrrdlvlgatedelay1; + u32 dfitrrdlvlgatedelay2; + u32 dfitrcmd; + u32 reserved14[46]; + u32 ipvr; + u32 iptr; +}; +check_member(rk3036_ddr_pctl, iptr, 0x03fc); + +struct rk3036_ddr_phy { + u32 ddrphy_reg1; + u32 ddrphy_reg3; + u32 ddrphy_reg2; + u32 reserve[11]; + u32 ddrphy_reg4a; + u32 ddrphy_reg4b; + u32 reserve1[5]; + u32 ddrphy_reg16; + u32 reserve2; + u32 ddrphy_reg18; + u32 ddrphy_reg19; + u32 reserve3; + u32 ddrphy_reg21; + u32 reserve4; + u32 ddrphy_reg22; + u32 reserve5[3]; + u32 ddrphy_reg25; + u32 ddrphy_reg26; + u32 ddrphy_reg27; + u32 ddrphy_reg28; + u32 reserve6[17]; + u32 ddrphy_reg6; + u32 ddrphy_reg7; + u32 reserve7; + u32 ddrphy_reg8; + u32 ddrphy_reg0e4; + u32 reserve8[11]; + u32 ddrphy_reg9; + u32 ddrphy_reg10; + u32 reserve9; + u32 ddrphy_reg11; + u32 ddrphy_reg124; + u32 reserve10[38]; + u32 ddrphy_reg29; + u32 reserve11[40]; + u32 ddrphy_reg264; + u32 reserve12[18]; + u32 ddrphy_reg2a; + u32 reserve13[4]; + u32 ddrphy_reg30; + u32 ddrphy_reg31; + u32 ddrphy_reg32; + u32 ddrphy_reg33; + u32 ddrphy_reg34; + u32 ddrphy_reg35; + u32 ddrphy_reg36; + u32 ddrphy_reg37; + u32 ddrphy_reg38; + u32 ddrphy_reg39; + u32 ddrphy_reg40; + u32 ddrphy_reg41; + u32 ddrphy_reg42; + u32 ddrphy_reg43; + u32 ddrphy_reg44; + u32 ddrphy_reg45; + u32 ddrphy_reg46; + u32 ddrphy_reg47; + u32 ddrphy_reg48; + u32 ddrphy_reg49; + u32 ddrphy_reg50; + u32 ddrphy_reg51; + u32 ddrphy_reg52; + u32 ddrphy_reg53; + u32 reserve14; + u32 ddrphy_reg54; + u32 ddrphy_reg55; + u32 ddrphy_reg56; + u32 ddrphy_reg57; + u32 ddrphy_reg58; + u32 ddrphy_reg59; + u32 ddrphy_reg5a; + u32 ddrphy_reg5b; + u32 ddrphy_reg5c; + u32 ddrphy_reg5d; + u32 ddrphy_reg5e; + u32 reserve15[28]; + u32 ddrphy_reg5f; + u32 reserve16[6]; + u32 ddrphy_reg60; + u32 ddrphy_reg61; + u32 ddrphy_reg62; +}; +check_member(rk3036_ddr_phy, ddrphy_reg62, 0x03e8); + +struct rk3036_pctl_timing { + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tdpd; +}; + +struct rk3036_phy_timing { + u32 mr[4]; + u32 bl; + u32 cl_al; +}; + +typedef union { + u32 noc_timing; + struct { + u32 acttoact:6; + u32 rdtomiss:6; + u32 wrtomiss:6; + u32 burstlen:3; + u32 rdtowr:5; + u32 wrtord:5; + u32 bwratio:1; + }; +} rk3036_noc_timing; + +struct rk3036_ddr_timing { + u32 freq; + struct rk3036_pctl_timing pctl_timing; + struct rk3036_phy_timing phy_timing; + rk3036_noc_timing noc_timing; +}; + +struct rk3036_service_sys { + u32 id_coreid; + u32 id_revisionid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 readlatency; +}; + +struct rk3036_ddr_config { + /* + * 000: lpddr + * 001: ddr + * 010: ddr2 + * 011: ddr3 + * 100: lpddr2-s2 + * 101: lpddr2-s4 + * 110: lpddr3 + */ + u32 ddr_type; + u32 rank; + u32 cs0_row; + u32 cs1_row; + + /* 2: 4bank, 3: 8bank */ + u32 bank; + u32 col; + + /* bw(0: 8bit, 1: 16bit, 2: 32bit) */ + u32 bw; +}; + +/* rk3036 sdram initial */ +void sdram_init(void); + +/* get ddr die config, implement in specific board */ +void get_ddr_config(struct rk3036_ddr_config *config); + +/* get ddr size on board */ +size_t sdram_size(void); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h new file mode 100644 index 000000000..6f6c5c995 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h @@ -0,0 +1,575 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ +#ifndef _ASM_ARCH_SDRAM_RK322X_H +#define _ASM_ARCH_SDRAM_RK322X_H + +#ifndef __ASSEMBLY__ +#include +#endif + +struct rk322x_sdram_channel { + /* + * bit width in address, eg: + * 8 banks using 3 bit to address, + * 2 cs using 1 bit to address. + */ + u8 rank; + u8 col; + u8 bk; + u8 bw; + u8 dbw; + u8 row_3_4; + u8 cs0_row; + u8 cs1_row; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + /* + * For of-platdata, which would otherwise convert this into two + * byte-swapped integers. With a size of 9 bytes, this struct will + * appear in of-platdata as a byte array. + * + * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff) + */ + u8 dummy; +#endif +}; + +struct rk322x_ddr_pctl { + u32 scfg; + u32 sctl; + u32 stat; + u32 intrstat; + u32 reserved0[(0x40 - 0x10) / 4]; + u32 mcmd; + u32 powctl; + u32 powstat; + u32 cmdtstat; + u32 cmdtstaten; + u32 reserved1[(0x60 - 0x54) / 4]; + u32 mrrcfg0; + u32 mrrstat0; + u32 mrrstat1; + u32 reserved2[(0x7c - 0x6c) / 4]; + + u32 mcfg1; + u32 mcfg; + u32 ppcfg; + u32 mstat; + u32 lpddr2zqcfg; + u32 reserved3; + + u32 dtupdes; + u32 dtuna; + u32 dtune; + u32 dtuprd0; + u32 dtuprd1; + u32 dtuprd2; + u32 dtuprd3; + u32 dtuawdt; + u32 reserved4[(0xc0 - 0xb4) / 4]; + + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tdpd; + u32 tref_mem_ddr3; + u32 reserved5[(0x180 - 0x14c) / 4]; + u32 ecccfg; + u32 ecctst; + u32 eccclr; + u32 ecclog; + u32 reserved6[(0x200 - 0x190) / 4]; + u32 dtuwactl; + u32 dturactl; + u32 dtucfg; + u32 dtuectl; + u32 dtuwd0; + u32 dtuwd1; + u32 dtuwd2; + u32 dtuwd3; + u32 dtuwdm; + u32 dturd0; + u32 dturd1; + u32 dturd2; + u32 dturd3; + u32 dtulfsrwd; + u32 dtulfsrrd; + u32 dtueaf; + /* dfi control registers */ + u32 dfitctrldelay; + u32 dfiodtcfg; + u32 dfiodtcfg1; + u32 dfiodtrankmap; + /* dfi write data registers */ + u32 dfitphywrdata; + u32 dfitphywrlat; + u32 reserved7[(0x260 - 0x258) / 4]; + u32 dfitrddataen; + u32 dfitphyrdlat; + u32 reserved8[(0x270 - 0x268) / 4]; + u32 dfitphyupdtype0; + u32 dfitphyupdtype1; + u32 dfitphyupdtype2; + u32 dfitphyupdtype3; + u32 dfitctrlupdmin; + u32 dfitctrlupdmax; + u32 dfitctrlupddly; + u32 reserved9; + u32 dfiupdcfg; + u32 dfitrefmski; + u32 dfitctrlupdi; + u32 reserved10[(0x2ac - 0x29c) / 4]; + u32 dfitrcfg0; + u32 dfitrstat0; + u32 dfitrwrlvlen; + u32 dfitrrdlvlen; + u32 dfitrrdlvlgateen; + u32 dfiststat0; + u32 dfistcfg0; + u32 dfistcfg1; + u32 reserved11; + u32 dfitdramclken; + u32 dfitdramclkdis; + u32 dfistcfg2; + u32 dfistparclr; + u32 dfistparlog; + u32 reserved12[(0x2f0 - 0x2e4) / 4]; + + u32 dfilpcfg0; + u32 reserved13[(0x300 - 0x2f4) / 4]; + u32 dfitrwrlvlresp0; + u32 dfitrwrlvlresp1; + u32 dfitrwrlvlresp2; + u32 dfitrrdlvlresp0; + u32 dfitrrdlvlresp1; + u32 dfitrrdlvlresp2; + u32 dfitrwrlvldelay0; + u32 dfitrwrlvldelay1; + u32 dfitrwrlvldelay2; + u32 dfitrrdlvldelay0; + u32 dfitrrdlvldelay1; + u32 dfitrrdlvldelay2; + u32 dfitrrdlvlgatedelay0; + u32 dfitrrdlvlgatedelay1; + u32 dfitrrdlvlgatedelay2; + u32 dfitrcmd; + u32 reserved14[(0x3f8 - 0x340) / 4]; + u32 ipvr; + u32 iptr; +}; +check_member(rk322x_ddr_pctl, iptr, 0x03fc); + +struct rk322x_ddr_phy { + u32 ddrphy_reg[0x100]; +}; + +struct rk322x_pctl_timing { + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tdpd; + u32 trefi_mem_ddr3; +}; + +struct rk322x_phy_timing { + u32 mr[4]; + u32 mr11; + u32 bl; + u32 cl_al; +}; + +struct rk322x_msch_timings { + u32 ddrtiming; + u32 ddrmode; + u32 readlatency; + u32 activate; + u32 devtodev; +}; + +struct rk322x_service_sys { + u32 id_coreid; + u32 id_revisionid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 readlatency; + u32 activate; + u32 devtodev; +}; + +struct rk322x_base_params { + struct rk322x_msch_timings noc_timing; + u32 ddrconfig; + u32 ddr_freq; + u32 dramtype; + /* + * unused for rk322x + */ + u32 stride; + u32 odt; +}; + +/* PCT_DFISTCFG0 */ +#define DFI_INIT_START BIT(0) +#define DFI_DATA_BYTE_DISABLE_EN BIT(2) + +/* PCT_DFISTCFG1 */ +#define DFI_DRAM_CLK_SR_EN BIT(0) +#define DFI_DRAM_CLK_DPD_EN BIT(1) + +/* PCT_DFISTCFG2 */ +#define DFI_PARITY_INTR_EN BIT(0) +#define DFI_PARITY_EN BIT(1) + +/* PCT_DFILPCFG0 */ +#define TLP_RESP_TIME_SHIFT 16 +#define LP_SR_EN BIT(8) +#define LP_PD_EN BIT(0) + +/* PCT_DFITCTRLDELAY */ +#define TCTRL_DELAY_TIME_SHIFT 0 + +/* PCT_DFITPHYWRDATA */ +#define TPHY_WRDATA_TIME_SHIFT 0 + +/* PCT_DFITPHYRDLAT */ +#define TPHY_RDLAT_TIME_SHIFT 0 + +/* PCT_DFITDRAMCLKDIS */ +#define TDRAM_CLK_DIS_TIME_SHIFT 0 + +/* PCT_DFITDRAMCLKEN */ +#define TDRAM_CLK_EN_TIME_SHIFT 0 + +/* PCTL_DFIODTCFG */ +#define RANK0_ODT_WRITE_SEL BIT(3) +#define RANK1_ODT_WRITE_SEL BIT(11) + +/* PCTL_DFIODTCFG1 */ +#define ODT_LEN_BL8_W_SHIFT 16 + +/* PUBL_ACDLLCR */ +#define ACDLLCR_DLLDIS BIT(31) +#define ACDLLCR_DLLSRST BIT(30) + +/* PUBL_DXDLLCR */ +#define DXDLLCR_DLLDIS BIT(31) +#define DXDLLCR_DLLSRST BIT(30) + +/* PUBL_DLLGCR */ +#define DLLGCR_SBIAS BIT(30) + +/* PUBL_DXGCR */ +#define DQSRTT BIT(9) +#define DQRTT BIT(10) + +/* PIR */ +#define PIR_INIT BIT(0) +#define PIR_DLLSRST BIT(1) +#define PIR_DLLLOCK BIT(2) +#define PIR_ZCAL BIT(3) +#define PIR_ITMSRST BIT(4) +#define PIR_DRAMRST BIT(5) +#define PIR_DRAMINIT BIT(6) +#define PIR_QSTRN BIT(7) +#define PIR_RVTRN BIT(8) +#define PIR_ICPC BIT(16) +#define PIR_DLLBYP BIT(17) +#define PIR_CTLDINIT BIT(18) +#define PIR_CLRSR BIT(28) +#define PIR_LOCKBYP BIT(29) +#define PIR_ZCALBYP BIT(30) +#define PIR_INITBYP BIT(31) + +/* PGCR */ +#define PGCR_DFTLMT_SHIFT 3 +#define PGCR_DFTCMP_SHIFT 2 +#define PGCR_DQSCFG_SHIFT 1 +#define PGCR_ITMDMD_SHIFT 0 + +/* PGSR */ +#define PGSR_IDONE BIT(0) +#define PGSR_DLDONE BIT(1) +#define PGSR_ZCDONE BIT(2) +#define PGSR_DIDONE BIT(3) +#define PGSR_DTDONE BIT(4) +#define PGSR_DTERR BIT(5) +#define PGSR_DTIERR BIT(6) +#define PGSR_DFTERR BIT(7) +#define PGSR_RVERR BIT(8) +#define PGSR_RVEIRR BIT(9) + +/* PTR0 */ +#define PRT_ITMSRST_SHIFT 18 +#define PRT_DLLLOCK_SHIFT 6 +#define PRT_DLLSRST_SHIFT 0 + +/* PTR1 */ +#define PRT_DINIT0_SHIFT 0 +#define PRT_DINIT1_SHIFT 19 + +/* PTR2 */ +#define PRT_DINIT2_SHIFT 0 +#define PRT_DINIT3_SHIFT 17 + +/* DCR */ +#define DDRMD_LPDDR 0 +#define DDRMD_DDR 1 +#define DDRMD_DDR2 2 +#define DDRMD_DDR3 3 +#define DDRMD_LPDDR2_LPDDR3 4 +#define DDRMD_MASK 7 +#define DDRMD_SHIFT 0 +#define PDQ_MASK 7 +#define PDQ_SHIFT 4 + +/* DXCCR */ +#define DQSNRES_MASK 0xf +#define DQSNRES_SHIFT 8 +#define DQSRES_MASK 0xf +#define DQSRES_SHIFT 4 + +/* DTPR */ +#define TDQSCKMAX_SHIFT 27 +#define TDQSCKMAX_MASK 7 +#define TDQSCK_SHIFT 24 +#define TDQSCK_MASK 7 + +/* DSGCR */ +#define DQSGX_SHIFT 5 +#define DQSGX_MASK 7 +#define DQSGE_SHIFT 8 +#define DQSGE_MASK 7 + +/* SCTL */ +#define INIT_STATE 0 +#define CFG_STATE 1 +#define GO_STATE 2 +#define SLEEP_STATE 3 +#define WAKEUP_STATE 4 + +/* STAT */ +#define LP_TRIG_SHIFT 4 +#define LP_TRIG_MASK 7 +#define PCTL_STAT_MASK 7 +#define INIT_MEM 0 +#define CONFIG 1 +#define CONFIG_REQ 2 +#define ACCESS 3 +#define ACCESS_REQ 4 +#define LOW_POWER 5 +#define LOW_POWER_ENTRY_REQ 6 +#define LOW_POWER_EXIT_REQ 7 + +/* ZQCR*/ +#define PD_OUTPUT_SHIFT 0 +#define PU_OUTPUT_SHIFT 5 +#define PD_ONDIE_SHIFT 10 +#define PU_ONDIE_SHIFT 15 +#define ZDEN_SHIFT 28 + +/* DDLGCR */ +#define SBIAS_BYPASS BIT(23) + +/* MCFG */ +#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24 +#define PD_IDLE_SHIFT 8 +#define MDDR_EN (2 << 22) +#define LPDDR2_EN (3 << 22) +#define LPDDR3_EN (1 << 22) +#define DDR2_EN (0 << 5) +#define DDR3_EN (1 << 5) +#define LPDDR2_S2 (0 << 6) +#define LPDDR2_S4 (1 << 6) +#define MDDR_LPDDR2_BL_2 (0 << 20) +#define MDDR_LPDDR2_BL_4 (1 << 20) +#define MDDR_LPDDR2_BL_8 (2 << 20) +#define MDDR_LPDDR2_BL_16 (3 << 20) +#define DDR2_DDR3_BL_4 0 +#define DDR2_DDR3_BL_8 1 +#define TFAW_SHIFT 18 +#define PD_EXIT_SLOW (0 << 17) +#define PD_EXIT_FAST (1 << 17) +#define PD_TYPE_SHIFT 16 +#define BURSTLENGTH_SHIFT 20 + +/* POWCTL */ +#define POWER_UP_START BIT(0) + +/* POWSTAT */ +#define POWER_UP_DONE BIT(0) + +/* MCMD */ +enum { + DESELECT_CMD = 0, + PREA_CMD, + REF_CMD, + MRS_CMD, + ZQCS_CMD, + ZQCL_CMD, + RSTL_CMD, + MRR_CMD = 8, + DPDE_CMD, +}; + +#define BANK_ADDR_MASK 7 +#define BANK_ADDR_SHIFT 17 +#define CMD_ADDR_MASK 0x1fff +#define CMD_ADDR_SHIFT 4 + +#define LPDDR23_MA_SHIFT 4 +#define LPDDR23_MA_MASK 0xff +#define LPDDR23_OP_SHIFT 12 +#define LPDDR23_OP_MASK 0xff + +#define START_CMD (1u << 31) + +/* DDRPHY REG */ +enum { + /* DDRPHY_REG0 */ + SOFT_RESET_MASK = 3, + SOFT_DERESET_ANALOG = 1 << 2, + SOFT_DERESET_DIGITAL = 1 << 3, + SOFT_RESET_SHIFT = 2, + + /* DDRPHY REG1 */ + PHY_DDR3 = 0, + PHY_DDR2 = 1, + PHY_LPDDR3 = 2, + PHY_LPDDR2 = 3, + + PHT_BL_8 = 1 << 2, + PHY_BL_4 = 0 << 2, + + /* DDRPHY_REG2 */ + MEMORY_SELECT_DDR3 = 0 << 0, + MEMORY_SELECT_LPDDR3 = 2 << 0, + MEMORY_SELECT_LPDDR2 = 3 << 0, + DQS_SQU_CAL_SEL_CS0_CS1 = 0 << 4, + DQS_SQU_CAL_SEL_CS1 = 1 << 4, + DQS_SQU_CAL_SEL_CS0 = 2 << 4, + DQS_SQU_CAL_NORMAL_MODE = 0 << 1, + DQS_SQU_CAL_BYPASS_MODE = 1 << 1, + DQS_SQU_CAL_START = 1 << 0, + DQS_SQU_NO_CAL = 0 << 0, +}; + +/* CK pull up/down driver strength control */ +enum { + PHY_RON_RTT_DISABLE = 0, + PHY_RON_RTT_451OHM = 1, + PHY_RON_RTT_225OHM, + PHY_RON_RTT_150OHM, + PHY_RON_RTT_112OHM, + PHY_RON_RTT_90OHM, + PHY_RON_RTT_75OHM, + PHY_RON_RTT_64OHM = 7, + + PHY_RON_RTT_56OHM = 16, + PHY_RON_RTT_50OHM, + PHY_RON_RTT_45OHM, + PHY_RON_RTT_41OHM, + PHY_RON_RTT_37OHM, + PHY_RON_RTT_34OHM, + PHY_RON_RTT_33OHM, + PHY_RON_RTT_30OHM = 23, + + PHY_RON_RTT_28OHM = 24, + PHY_RON_RTT_26OHM, + PHY_RON_RTT_25OHM, + PHY_RON_RTT_23OHM, + PHY_RON_RTT_22OHM, + PHY_RON_RTT_21OHM, + PHY_RON_RTT_20OHM, + PHY_RON_RTT_19OHM = 31, +}; + +/* DQS squelch DLL delay */ +enum { + DQS_DLL_NO_DELAY = 0, + DQS_DLL_22P5_DELAY, + DQS_DLL_45_DELAY, + DQS_DLL_67P5_DELAY, + DQS_DLL_90_DELAY, + DQS_DLL_112P5_DELAY, + DQS_DLL_135_DELAY, + DQS_DLL_157P5_DELAY, +}; + +/* GRF_SOC_CON0 */ +#define GRF_DDR_16BIT_EN (((0x1 << 0) << 16) | (0x1 << 0)) +#define GRF_DDR_32BIT_EN (((0x1 << 0) << 16) | (0x0 << 0)) +#define GRF_MSCH_NOC_16BIT_EN (((0x1 << 7) << 16) | (0x1 << 7)) +#define GRF_MSCH_NOC_32BIT_EN (((0x1 << 7) << 16) | (0x0 << 7)) + +#define GRF_DDRPHY_BUFFEREN_CORE_EN (((0x1 << 8) << 16) | (0x0 << 8)) +#define GRF_DDRPHY_BUFFEREN_CORE_DIS (((0x1 << 8) << 16) | (0x1 << 8)) + +#define GRF_DDR3_EN (((0x1 << 6) << 16) | (0x1 << 6)) +#define GRF_LPDDR2_3_EN (((0x1 << 6) << 16) | (0x0 << 6)) + +#define PHY_DRV_ODT_SET(n) (((n) << 4) | (n)) +#define DDR3_DLL_RESET (1 << 8) + +#endif /* _ASM_ARCH_SDRAM_RK322X_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3288.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3288.h new file mode 100644 index 000000000..9220763fa --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3288.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2015 Google, Inc + * + * Copyright 2014 Rockchip Inc. + */ + +#ifndef _ASM_ARCH_RK3288_SDRAM_H__ +#define _ASM_ARCH_RK3288_SDRAM_H__ + +struct rk3288_sdram_channel { + /* + * bit width in address, eg: + * 8 banks using 3 bit to address, + * 2 cs using 1 bit to address. + */ + u8 rank; + u8 col; + u8 bk; + u8 bw; + u8 dbw; + u8 row_3_4; + u8 cs0_row; + u8 cs1_row; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + /* + * For of-platdata, which would otherwise convert this into two + * byte-swapped integers. With a size of 9 bytes, this struct will + * appear in of-platdata as a byte array. + * + * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff) + */ + u8 dummy; +#endif +}; + +struct rk3288_sdram_pctl_timing { + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tdpd; +}; +check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0); + +struct rk3288_sdram_phy_timing { + u32 dtpr0; + u32 dtpr1; + u32 dtpr2; + u32 mr[4]; +}; + +struct rk3288_base_params { + u32 noc_timing; + u32 noc_activate; + u32 ddrconfig; + u32 ddr_freq; + u32 dramtype; + /* + * DDR Stride is address mapping for DRAM space + * Stride Ch 0 range Ch1 range Total + * 0x00 0-256MB 256MB-512MB 512MB + * 0x05 0-1GB 0-1GB 1GB + * 0x09 0-2GB 0-2GB 2GB + * 0x0d 0-4GB 0-4GB 4GB + * 0x17 N/A 0-4GB 4GB + * 0x1a 0-4GB 4GB-8GB 8GB + */ + u32 stride; + u32 odt; +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h new file mode 100644 index 000000000..10923505d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h @@ -0,0 +1,265 @@ +/* + * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_SDRAM_RK3328_H +#define _ASM_ARCH_SDRAM_RK3328_H +#include +#include +#include +#include + +#define SR_IDLE 93 +#define PD_IDLE 13 +#define SDRAM_ADDR 0x00000000 + +/* noc registers define */ +#define DDRCONF 0x8 +#define DDRTIMING 0xc +#define DDRMODE 0x10 +#define READLATENCY 0x14 +#define AGING0 0x18 +#define AGING1 0x1c +#define AGING2 0x20 +#define AGING3 0x24 +#define AGING4 0x28 +#define AGING5 0x2c +#define ACTIVATE 0x38 +#define DEVTODEV 0x3c +#define DDR4TIMING 0x40 + +/* DDR GRF */ +#define DDR_GRF_CON(n) (0 + (n) * 4) +#define DDR_GRF_STATUS_BASE (0X100) +#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) + +/* CRU_SOFTRESET_CON5 */ +#define ddrphy_psrstn_req(n) (((0x1 << 15) << 16) | ((n) << 15)) +#define ddrphy_srstn_req(n) (((0x1 << 14) << 16) | ((n) << 14)) +#define ddrctrl_psrstn_req(n) (((0x1 << 13) << 16) | ((n) << 13)) +#define ddrctrl_srstn_req(n) (((0x1 << 12) << 16) | ((n) << 12)) +#define ddrmsch_srstn_req(n) (((0x1 << 11) << 16) | ((n) << 11)) +#define msch_srstn_req(n) (((0x1 << 9) << 16) | ((n) << 9)) +#define dfimon_srstn_req(n) (((0x1 << 8) << 16) | ((n) << 8)) +#define grf_ddr_srstn_req(n) (((0x1 << 7) << 16) | ((n) << 7)) +/* CRU_SOFTRESET_CON9 */ +#define ddrctrl_asrstn_req(n) (((0x1 << 9) << 16) | ((n) << 9)) + +/* CRU register */ +#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) +#define CRU_MODE (0x80) +#define CRU_GLB_CNT_TH (0x90) +#define CRU_CLKSEL_CON_BASE 0x100 +#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON_BASE + ((i) * 4)) +#define CRU_CLKGATE_CON_BASE 0x200 +#define CRU_CLKGATE_CON(i) (CRU_CLKGATE_CON_BASE + ((i) * 4)) +#define CRU_CLKSFTRST_CON_BASE 0x300 +#define CRU_CLKSFTRST_CON(i) (CRU_CLKSFTRST_CON_BASE + ((i) * 4)) + +/* CRU_PLL_CON0 */ +#define PB(n) ((0x1 << (15 + 16)) | ((n) << 15)) +#define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12)) +#define FBDIV(n) ((0xFFF << 16) | (n)) + +/* CRU_PLL_CON1 */ +#define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15)) +#define RST(n) ((0x1 << (14 + 16)) | ((n) << 14)) +#define PD(n) ((0x1 << (13 + 16)) | ((n) << 13)) +#define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12)) +#define LOCK(n) (((n) >> 10) & 0x1) +#define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6)) +#define REFDIV(n) ((0x3F << 16) | (n)) + +u16 ddr_cfg_2_rbc[] = { + /* + * [5:4] row(13+n) + * [3] cs(0:0 cs, 1:2 cs) + * [2] bank(0:0bank,1:8bank) + * [1:0] col(11+n) + */ + /* row, cs, bank, col */ + ((3 << 4) | (0 << 3) | (1 << 2) | 0), + ((3 << 4) | (0 << 3) | (1 << 2) | 1), + ((2 << 4) | (0 << 3) | (1 << 2) | 2), + ((3 << 4) | (0 << 3) | (1 << 2) | 2), + ((2 << 4) | (0 << 3) | (1 << 2) | 3), + ((3 << 4) | (1 << 3) | (1 << 2) | 0), + ((3 << 4) | (1 << 3) | (1 << 2) | 1), + ((2 << 4) | (1 << 3) | (1 << 2) | 2), + ((3 << 4) | (0 << 3) | (0 << 2) | 1), + ((2 << 4) | (0 << 3) | (1 << 2) | 1), +}; + +u16 ddr4_cfg_2_rbc[] = { + /*************************** + * [6] cs 0:0cs 1:2 cs + * [5:3] row(13+n) + * [2] cs(0:0 cs, 1:2 cs) + * [1] bw 0: 16bit 1:32bit + * [0] diebw 0:8bit 1:16bit + ***************************/ + /* cs, row, cs, bw, diebw */ + ((0 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 0), + ((1 << 6) | (2 << 3) | (0 << 2) | (1 << 1) | 0), + ((0 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 0), + ((1 << 6) | (3 << 3) | (0 << 2) | (0 << 1) | 0), + ((0 << 6) | (4 << 3) | (0 << 2) | (1 << 1) | 1), + ((1 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 1), + ((1 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 1), + ((0 << 6) | (2 << 3) | (1 << 2) | (1 << 1) | 0), + ((0 << 6) | (3 << 3) | (1 << 2) | (0 << 1) | 0), + ((0 << 6) | (3 << 3) | (1 << 2) | (1 << 1) | 1), + ((0 << 6) | (4 << 3) | (1 << 2) | (0 << 1) | 1), +}; + +u32 addrmap[21][9] = { + /* map0 map1 map2 map3 map4 map5 map6 map7 map8 */ + {22, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606, + 0x06060606, 0x00000f0f, 0x3f3f}, + {23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f0f, 0x3f3f}, + {23, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, + 0x0f080808, 0x00000f0f, 0x3f3f}, + {24, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, + 0x08080808, 0x00000f0f, 0x3f3f}, + {24, 0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909, + 0x0f090909, 0x00000f0f, 0x3f3f}, + {6, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f0f, 0x3f3f}, + {7, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x08080808, + 0x08080808, 0x00000f0f, 0x3f3f}, + {8, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x09090909, + 0x0f090909, 0x00000f0f, 0x3f3f}, + {22, 0x001f0808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606, + 0x06060606, 0x00000f0f, 0x3f3f}, + {23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, + 0x0f070707, 0x00000f0f, 0x3f3f}, + + {24, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, + 0x08080808, 0x00000f0f, 0x0801}, + {23, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, + 0x0f080808, 0x00000f0f, 0x0801}, + {24, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f07, 0x0700}, + {23, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f0f, 0x0700}, + {24, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f07, 0x3f01}, + {23, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f0f, 0x3f01}, + {24, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606, + 0x06060606, 0x00000f06, 0x3f00}, + {8, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x09090909, + 0x0f090909, 0x00000f0f, 0x0801}, + {7, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x08080808, + 0x08080808, 0x00000f0f, 0x0700}, + {7, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, + 0x08080808, 0x00000f0f, 0x3f01}, + + {6, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f07, 0x3f00} +}; + +struct rk3328_ddr_grf_regs { + u32 ddr_grf_con[4]; + u32 reserved[(0x100 - 0x10) / 4]; + u32 ddr_grf_status[11]; +}; + +union noc_ddrtiming { + u32 d32; + struct { + unsigned acttoact:6; + unsigned rdtomiss:6; + unsigned wrtomiss:6; + unsigned burstlen:3; + unsigned rdtowr:5; + unsigned wrtord:5; + unsigned bwratio:1; + } b; +}; + +union noc_activate { + u32 d32; + struct { + unsigned rrd:4; + unsigned faw:6; + unsigned fawbank:1; + unsigned reserved1:21; + } b; +}; + +union noc_devtodev { + u32 d32; + struct { + unsigned busrdtord:2; + unsigned busrdtowr:2; + unsigned buswrtord:2; + unsigned reserved2:26; + } b; +}; + +union noc_ddr4timing { + u32 d32; + struct { + unsigned ccdl:3; + unsigned wrtordl:5; + unsigned rrdl:4; + unsigned reserved2:20; + } b; +}; + +union noc_ddrmode { + u32 d32; + struct { + unsigned autoprecharge:1; + unsigned bwratioextended:1; + unsigned reserved3:30; + } b; +}; + +struct msch_regs { + u32 coreid; + u32 revisionid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 readlatency; + u32 aging0; + u32 aging1; + u32 aging2; + u32 aging3; + u32 aging4; + u32 aging5; + u32 reserved[2]; + u32 activate; + u32 devtodev; + u32 ddr4_timing; +}; + +struct sdram_msch_timings { + union noc_ddrtiming ddrtiming; + union noc_ddrmode ddrmode; + u32 readlatency; + union noc_activate activate; + union noc_devtodev devtodev; + union noc_ddr4timing ddr4timing; + u32 agingx0; +}; + +struct rk3328_sdram_channel { + struct sdram_cap_info cap_info; + struct sdram_msch_timings noc_timings; +}; + +struct rk3328_sdram_params { + struct rk3328_sdram_channel ch; + struct sdram_base_params base; + struct ddr_pctl_regs pctl_regs; + struct ddr_phy_regs phy_regs; + struct ddr_phy_skew skew; +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h new file mode 100644 index 000000000..c76372ee8 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd + */ + +#ifndef _ASM_ARCH_SDRAM_RK3399_H +#define _ASM_ARCH_SDRAM_RK3399_H +#include +#include +#ifndef __ASSEMBLY__ +#include +#endif + +struct rk3399_ddr_pctl_regs { + u32 denali_ctl[332]; +}; + +struct rk3399_ddr_publ_regs { + u32 denali_phy[959]; +}; + +struct rk3399_ddr_pi_regs { + u32 denali_pi[200]; +}; + +struct rk3399_ddr_cic_regs { + u32 cic_ctrl0; + u32 cic_ctrl1; + u32 cic_idle_th; + u32 cic_cg_wait_th; + u32 cic_status0; + u32 cic_status1; + u32 cic_ctrl2; + u32 cic_ctrl3; + u32 cic_ctrl4; +}; + +/* DENALI_CTL_00 */ +#define START 1 + +/* DENALI_CTL_68 */ +#define PWRUP_SREFRESH_EXIT BIT(16) + +/* DENALI_CTL_274 */ +#define MEM_RST_VALID 1 + +struct msch_regs { + u32 coreid; + u32 revisionid; + u32 ddrconf; + u32 ddrsize; + union noc_ddrtiminga0 ddrtiminga0; + union noc_ddrtimingb0 ddrtimingb0; + union noc_ddrtimingc0 ddrtimingc0; + union noc_devtodev0 devtodev0; + u32 reserved0[(0x110 - 0x20) / 4]; + union noc_ddrmode ddrmode; + u32 reserved1[(0x1000 - 0x114) / 4]; + u32 agingx0; +}; + +struct sdram_msch_timings { + union noc_ddrtiminga0 ddrtiminga0; + union noc_ddrtimingb0 ddrtimingb0; + union noc_ddrtimingc0 ddrtimingc0; + union noc_devtodev0 devtodev0; + union noc_ddrmode ddrmode; + u32 agingx0; +}; + +struct rk3399_sdram_channel { + struct sdram_cap_info cap_info; + struct sdram_msch_timings noc_timings; +}; + +struct rk3399_sdram_params { + struct rk3399_sdram_channel ch[2]; + struct sdram_base_params base; + struct rk3399_ddr_pctl_regs pctl_regs; + struct rk3399_ddr_pi_regs pi_regs; + struct rk3399_ddr_publ_regs phy_regs; +}; + +#define PI_CA_TRAINING BIT(0) +#define PI_WRITE_LEVELING BIT(1) +#define PI_READ_GATE_TRAINING BIT(2) +#define PI_READ_LEVELING BIT(3) +#define PI_WDQ_LEVELING BIT(4) +#define PI_FULL_TRAINING 0xff + +enum { + STRIDE_128B = 0, + STRIDE_256B = 1, + STRIDE_512B = 2, + STRIDE_4KB = 3, + UN_STRIDE = 4, + PART_STRIDE = 5, +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sys_proto.h new file mode 100644 index 000000000..de5a8f11a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/sys_proto.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co.,Ltd + */ + +#ifndef _ASM_ARCH_SYS_PROTO_H +#define _ASM_ARCH_SYS_PROTO_H + +#endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/timer.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/timer.h new file mode 100644 index 000000000..77b542204 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/timer.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_TIMER_H +#define __ASM_ARCH_TIMER_H + +struct rk_timer { + u32 timer_load_count0; + u32 timer_load_count1; + u32 timer_curr_value0; + u32 timer_curr_value1; + u32 timer_ctrl_reg; + u32 timer_int_status; +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/uart.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/uart.h new file mode 100644 index 000000000..feede5e55 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/uart.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_UART_H +#define __ASM_ARCH_UART_H +struct rk_uart { + unsigned int rbr; /* Receive buffer register. */ + unsigned int ier; /* Interrupt enable register. */ + unsigned int fcr; /* FIFO control register. */ + unsigned int lcr; /* Line control register. */ + unsigned int mcr; /* Modem control register. */ + unsigned int lsr; /* Line status register. */ + unsigned int msr; /* Modem status register. */ + unsigned int scr; + unsigned int reserved1[(0x30 - 0x20) / 4]; + unsigned int srbr[(0x70 - 0x30) / 4]; + unsigned int far; + unsigned int tfr; + unsigned int rfw; + unsigned int usr; + unsigned int tfl; + unsigned int rfl; + unsigned int srr; + unsigned int srts; + unsigned int sbcr; + unsigned int sdmam; + unsigned int sfe; + unsigned int srt; + unsigned int stet; + unsigned int htx; + unsigned int dmasa; + unsigned int reserver2[(0xf4 - 0xac) / 4]; + unsigned int cpr; + unsigned int ucv; + unsigned int ctr; +}; + +void rk_uart_init(void *base); +void print_hex(unsigned int n); +void print(char *s); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rockchip/vop_rk3288.h b/roms/u-boot/arch/arm/include/asm/arch-rockchip/vop_rk3288.h new file mode 100644 index 000000000..49a714143 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rockchip/vop_rk3288.h @@ -0,0 +1,359 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2015 Google, Inc + * Copyright 2014 Rockchip Inc. + */ + +#ifndef _ASM_ARCH_VOP_RK3288_H +#define _ASM_ARCH_VOP_RK3288_H + +struct rk3288_vop { + u32 reg_cfg_done; + u32 version_info; + u32 sys_ctrl; + u32 sys_ctrl1; + u32 dsp_ctrl0; + u32 dsp_ctrl1; + u32 dsp_bg; + u32 mcu_ctrl; + u32 intr_ctrl0; + u32 intr_ctrl1; + u32 intr_reserved0; + u32 intr_reserved1; + + u32 win0_ctrl0; + u32 win0_ctrl1; + u32 win0_color_key; + u32 win0_vir; + u32 win0_yrgb_mst; + u32 win0_cbr_mst; + u32 win0_act_info; + u32 win0_dsp_info; + u32 win0_dsp_st; + u32 win0_scl_factor_yrgb; + u32 win0_scl_factor_cbr; + u32 win0_scl_offset; + u32 win0_src_alpha_ctrl; + u32 win0_dst_alpha_ctrl; + u32 win0_fading_ctrl; + u32 win0_reserved0; + + u32 win1_ctrl0; + u32 win1_ctrl1; + u32 win1_color_key; + u32 win1_vir; + u32 win1_yrgb_mst; + u32 win1_cbr_mst; + u32 win1_act_info; + u32 win1_dsp_info; + u32 win1_dsp_st; + u32 win1_scl_factor_yrgb; + u32 win1_scl_factor_cbr; + u32 win1_scl_offset; + u32 win1_src_alpha_ctrl; + u32 win1_dst_alpha_ctrl; + u32 win1_fading_ctrl; + u32 win1_reservd0; + u32 reserved2[48]; + u32 post_dsp_hact_info; + u32 post_dsp_vact_info; + u32 post_scl_factor_yrgb; + u32 post_reserved; + u32 post_scl_ctrl; + u32 post_dsp_vact_info_f1; + u32 dsp_htotal_hs_end; + u32 dsp_hact_st_end; + u32 dsp_vtotal_vs_end; + u32 dsp_vact_st_end; + u32 dsp_vs_st_end_f1; + u32 dsp_vact_st_end_f1; +}; +check_member(rk3288_vop, dsp_vact_st_end_f1, 0x19c); + +enum rockchip_fb_data_format_t { + ARGB8888 = 0, + RGB888 = 1, + RGB565 = 2, +}; + +enum { + LB_YUV_3840X5 = 0x0, + LB_YUV_2560X8 = 0x1, + LB_RGB_3840X2 = 0x2, + LB_RGB_2560X4 = 0x3, + LB_RGB_1920X5 = 0x4, + LB_RGB_1280X8 = 0x5 +}; + +enum vop_modes { + VOP_MODE_EDP = 0, + VOP_MODE_MIPI, + VOP_MODE_HDMI, + VOP_MODE_LVDS, + VOP_MODE_DP, +}; + +/* VOP_VERSION_INFO */ +#define M_FPGA_VERSION (0xffff << 16) +#define M_RTL_VERSION (0xffff) + +/* VOP_SYS_CTRL */ +#define M_AUTO_GATING_EN (1 << 23) +#define M_STANDBY_EN (1 << 22) +#define M_DMA_STOP (1 << 21) +#define M_MMU_EN (1 << 20) +#define M_DAM_BURST_LENGTH (0x3 << 18) +#define M_MIPI_OUT_EN (1 << 15) +#define M_EDP_OUT_EN (1 << 14) +#define M_HDMI_OUT_EN (1 << 13) +#define M_RGB_OUT_EN (1 << 12) +#define M_ALL_OUT_EN \ + (M_MIPI_OUT_EN | M_EDP_OUT_EN | M_HDMI_OUT_EN | M_RGB_OUT_EN) +#define M_EDPI_WMS_FS (1 << 10) +#define M_EDPI_WMS_MODE (1 << 9) +#define M_EDPI_HALT_EN (1 << 8) +#define M_DOUB_CH_OVERLAP_NUM (0xf << 4) +#define M_DOUB_CHANNEL_EN (1 << 3) +#define M_DIRECT_PATH_LAYER_SEL (0x3 << 1) +#define M_DIRECT_PATH_EN (1) + +#define V_AUTO_GATING_EN(x) (((x) & 1) << 23) +#define V_STANDBY_EN(x) (((x) & 1) << 22) +#define V_DMA_STOP(x) (((x) & 1) << 21) +#define V_MMU_EN(x) (((x) & 1) << 20) +#define V_DMA_BURST_LENGTH(x) (((x) & 3) << 18) +#define V_MIPI_OUT_EN(x) (((x) & 1) << 15) +#define V_EDP_OUT_EN(x) (((x) & 1) << 14) +#define V_HDMI_OUT_EN(x) (((x) & 1) << 13) +#define V_RGB_OUT_EN(x) (((x) & 1) << 12) +#define V_EDPI_WMS_FS(x) (((x) & 1) << 10) +#define V_EDPI_WMS_MODE(x) (((x) & 1) << 9) +#define V_EDPI_HALT_EN(x) (((x)&1)<<8) +#define V_DOUB_CH_OVERLAP_NUM(x) (((x) & 0xf) << 4) +#define V_DOUB_CHANNEL_EN(x) (((x) & 1) << 3) +#define V_DIRECT_PATH_LAYER_SEL(x) (((x) & 3) << 1) +#define V_DIRECT_PATH_EN(x) ((x) & 1) + +/* VOP_SYS_CTRL1 */ +#define M_AXI_OUTSTANDING_MAX_NUM (0x1f << 13) +#define M_AXI_MAX_OUTSTANDING_EN (1 << 12) +#define M_NOC_WIN_QOS (3 << 10) +#define M_NOC_QOS_EN (1 << 9) +#define M_NOC_HURRY_THRESHOLD (0x3f << 3) +#define M_NOC_HURRY_VALUE (0x3 << 1) +#define M_NOC_HURRY_EN (1) + +#define V_AXI_OUTSTANDING_MAX_NUM(x) (((x) & 0x1f) << 13) +#define V_AXI_MAX_OUTSTANDING_EN(x) (((x) & 1) << 12) +#define V_NOC_WIN_QOS(x) (((x) & 3) << 10) +#define V_NOC_QOS_EN(x) (((x) & 1) << 9) +#define V_NOC_HURRY_THRESHOLD(x) (((x) & 0x3f) << 3) +#define V_NOC_HURRY_VALUE(x) (((x) & 3) << 1) +#define V_NOC_HURRY_EN(x) ((x) & 1) + +/* VOP_DSP_CTRL0 */ +#define M_DSP_Y_MIR_EN (1 << 23) +#define M_DSP_X_MIR_EN (1 << 22) +#define M_DSP_YUV_CLIP (1 << 21) +#define M_DSP_CCIR656_AVG (1 << 20) +#define M_DSP_BLACK_EN (1 << 19) +#define M_DSP_BLANK_EN (1 << 18) +#define M_DSP_OUT_ZERO (1 << 17) +#define M_DSP_DUMMY_SWAP (1 << 16) +#define M_DSP_DELTA_SWAP (1 << 15) +#define M_DSP_RG_SWAP (1 << 14) +#define M_DSP_RB_SWAP (1 << 13) +#define M_DSP_BG_SWAP (1 << 12) +#define M_DSP_FIELD_POL (1 << 11) +#define M_DSP_INTERLACE (1 << 10) +#define M_DSP_DDR_PHASE (1 << 9) +#define M_DSP_DCLK_DDR (1 << 8) +#define M_DSP_DCLK_POL (1 << 7) +#define M_DSP_DEN_POL (1 << 6) +#define M_DSP_VSYNC_POL (1 << 5) +#define M_DSP_HSYNC_POL (1 << 4) +#define M_DSP_OUT_MODE (0xf) + +#define V_DSP_Y_MIR_EN(x) (((x) & 1) << 23) +#define V_DSP_X_MIR_EN(x) (((x) & 1) << 22) +#define V_DSP_YUV_CLIP(x) (((x) & 1) << 21) +#define V_DSP_CCIR656_AVG(x) (((x) & 1) << 20) +#define V_DSP_BLACK_EN(x) (((x) & 1) << 19) +#define V_DSP_BLANK_EN(x) (((x) & 1) << 18) +#define V_DSP_OUT_ZERO(x) (((x) & 1) << 17) +#define V_DSP_DUMMY_SWAP(x) (((x) & 1) << 16) +#define V_DSP_DELTA_SWAP(x) (((x) & 1) << 15) +#define V_DSP_RG_SWAP(x) (((x) & 1) << 14) +#define V_DSP_RB_SWAP(x) (((x) & 1) << 13) +#define V_DSP_BG_SWAP(x) (((x) & 1) << 12) +#define V_DSP_FIELD_POL(x) (((x) & 1) << 11) +#define V_DSP_INTERLACE(x) (((x) & 1) << 10) +#define V_DSP_DDR_PHASE(x) (((x) & 1) << 9) +#define V_DSP_DCLK_DDR(x) (((x) & 1) << 8) +#define V_DSP_DCLK_POL(x) (((x) & 1) << 7) +#define V_DSP_DEN_POL(x) (((x) & 1) << 6) +#define V_DSP_VSYNC_POL(x) (((x) & 1) << 5) +#define V_DSP_HSYNC_POL(x) (((x) & 1) << 4) +#define V_DSP_PIN_POL(x) (((x) & 0xf) << 4) +#define V_DSP_OUT_MODE(x) ((x) & 0xf) + +/* VOP_DSP_CTRL1 */ +#define V_RK3399_DSP_MIPI_POL(x) ((x) << 28) +#define V_RK3399_DSP_EDP_POL(x) ((x) << 24) +#define V_RK3399_DSP_HDMI_POL(x) ((x) << 20) +#define V_RK3399_DSP_LVDS_POL(x) ((x) << 16) + +#define M_RK3399_DSP_MIPI_POL (V_RK3399_DSP_MIPI_POL(0xf)) +#define M_RK3399_DSP_EDP_POL (V_RK3399_DSP_EDP_POL(0xf)) +#define M_RK3399_DSP_HDMI_POL (V_RK3399_DSP_HDMI_POL(0xf)) +#define M_RK3399_DSP_LVDS_POL (V_RK3399_DSP_LVDS_POL(0xf)) + +#define M_DSP_LAYER3_SEL (3 << 14) +#define M_DSP_LAYER2_SEL (3 << 12) +#define M_DSP_LAYER1_SEL (3 << 10) +#define M_DSP_LAYER0_SEL (3 << 8) +#define M_DITHER_UP_EN (1 << 6) +#define M_DITHER_DOWN_SEL (1 << 4) +#define M_DITHER_DOWN_MODE (1 << 3) +#define M_DITHER_DOWN_EN (1 << 2) +#define M_PRE_DITHER_DOWN_EN (1 << 1) +#define M_DSP_LUT_EN (1) + +#define V_DSP_LAYER3_SEL(x) (((x) & 3) << 14) +#define V_DSP_LAYER2_SEL(x) (((x) & 3) << 12) +#define V_DSP_LAYER1_SEL(x) (((x) & 3) << 10) +#define V_DSP_LAYER0_SEL(x) (((x) & 3) << 8) +#define V_DITHER_UP_EN(x) (((x) & 1) << 6) +#define V_DITHER_DOWN_SEL(x) (((x) & 1) << 4) +#define V_DITHER_DOWN_MODE(x) (((x) & 1) << 3) +#define V_DITHER_DOWN_EN(x) (((x) & 1) << 2) +#define V_PRE_DITHER_DOWN_EN(x) (((x) & 1) << 1) +#define V_DSP_LUT_EN(x) ((x)&1) + +/* VOP_DSP_BG */ +#define M_DSP_BG_RED (0x3f << 20) +#define M_DSP_BG_GREEN (0x3f << 10) +#define M_DSP_BG_BLUE (0x3f << 0) + +#define V_DSP_BG_RED(x) (((x) & 0x3f) << 20) +#define V_DSP_BG_GREEN(x) (((x) & 0x3f) << 10) +#define V_DSP_BG_BLUE(x) (((x) & 0x3f) << 0) + +/* VOP_WIN0_CTRL0 */ +#define M_WIN0_YUV_CLIP (1 << 20) +#define M_WIN0_CBR_DEFLICK (1 << 19) +#define M_WIN0_YRGB_DEFLICK (1 << 18) +#define M_WIN0_PPAS_ZERO_EN (1 << 16) +#define M_WIN0_UV_SWAP (1 << 15) +#define M_WIN0_MID_SWAP (1 << 14) +#define M_WIN0_ALPHA_SWAP (1 << 13) +#define M_WIN0_RB_SWAP (1 << 12) +#define M_WIN0_CSC_MODE (3 << 10) +#define M_WIN0_NO_OUTSTANDING (1 << 9) +#define M_WIN0_INTERLACE_READ (1 << 8) +#define M_WIN0_LB_MODE (7 << 5) +#define M_WIN0_FMT_10 (1 << 4) +#define M_WIN0_DATA_FMT (7 << 1) +#define M_WIN0_EN (1 << 0) + +#define V_WIN0_YUV_CLIP(x) (((x) & 1) << 20) +#define V_WIN0_CBR_DEFLICK(x) (((x) & 1) << 19) +#define V_WIN0_YRGB_DEFLICK(x) (((x) & 1) << 18) +#define V_WIN0_PPAS_ZERO_EN(x) (((x) & 1) << 16) +#define V_WIN0_UV_SWAP(x) (((x) & 1) << 15) +#define V_WIN0_MID_SWAP(x) (((x) & 1) << 14) +#define V_WIN0_ALPHA_SWAP(x) (((x) & 1) << 13) +#define V_WIN0_RB_SWAP(x) (((x) & 1) << 12) +#define V_WIN0_CSC_MODE(x) (((x) & 3) << 10) +#define V_WIN0_NO_OUTSTANDING(x) (((x) & 1) << 9) +#define V_WIN0_INTERLACE_READ(x) (((x) & 1) << 8) +#define V_WIN0_LB_MODE(x) (((x) & 7) << 5) +#define V_WIN0_FMT_10(x) (((x) & 1) << 4) +#define V_WIN0_DATA_FMT(x) (((x) & 7) << 1) +#define V_WIN0_EN(x) ((x) & 1) + +/* VOP_WIN0_CTRL1 */ +#define M_WIN0_CBR_VSD_MODE (1 << 31) +#define M_WIN0_CBR_VSU_MODE (1 << 30) +#define M_WIN0_CBR_HSD_MODE (3 << 28) +#define M_WIN0_CBR_VER_SCL_MODE (3 << 26) +#define M_WIN0_CBR_HOR_SCL_MODE (3 << 24) +#define M_WIN0_YRGB_VSD_MODE (1 << 23) +#define M_WIN0_YRGB_VSU_MODE (1 << 22) +#define M_WIN0_YRGB_HSD_MODE (3 << 20) +#define M_WIN0_YRGB_VER_SCL_MODE (3 << 18) +#define M_WIN0_YRGB_HOR_SCL_MODE (3 << 16) +#define M_WIN0_LINE_LOAD_MODE (1 << 15) +#define M_WIN0_CBR_AXI_GATHER_NUM (7 << 12) +#define M_WIN0_YRGB_AXI_GATHER_NUM (0xf << 8) +#define M_WIN0_VSD_CBR_GT2 (1 << 7) +#define M_WIN0_VSD_CBR_GT4 (1 << 6) +#define M_WIN0_VSD_YRGB_GT2 (1 << 5) +#define M_WIN0_VSD_YRGB_GT4 (1 << 4) +#define M_WIN0_BIC_COE_SEL (3 << 2) +#define M_WIN0_CBR_AXI_GATHER_EN (1 << 1) +#define M_WIN0_YRGB_AXI_GATHER_EN (1) + +#define V_WIN0_CBR_VSD_MODE(x) (((x) & 1) << 31) +#define V_WIN0_CBR_VSU_MODE(x) (((x) & 1) << 30) +#define V_WIN0_CBR_HSD_MODE(x) (((x) & 3) << 28) +#define V_WIN0_CBR_VER_SCL_MODE(x) (((x) & 3) << 26) +#define V_WIN0_CBR_HOR_SCL_MODE(x) (((x) & 3) << 24) +#define V_WIN0_YRGB_VSD_MODE(x) (((x) & 1) << 23) +#define V_WIN0_YRGB_VSU_MODE(x) (((x) & 1) << 22) +#define V_WIN0_YRGB_HSD_MODE(x) (((x) & 3) << 20) +#define V_WIN0_YRGB_VER_SCL_MODE(x) (((x) & 3) << 18) +#define V_WIN0_YRGB_HOR_SCL_MODE(x) (((x) & 3) << 16) +#define V_WIN0_LINE_LOAD_MODE(x) (((x) & 1) << 15) +#define V_WIN0_CBR_AXI_GATHER_NUM(x) (((x) & 7) << 12) +#define V_WIN0_YRGB_AXI_GATHER_NUM(x) (((x) & 0xf) << 8) +#define V_WIN0_VSD_CBR_GT2(x) (((x) & 1) << 7) +#define V_WIN0_VSD_CBR_GT4(x) (((x) & 1) << 6) +#define V_WIN0_VSD_YRGB_GT2(x) (((x) & 1) << 5) +#define V_WIN0_VSD_YRGB_GT4(x) (((x) & 1) << 4) +#define V_WIN0_BIC_COE_SEL(x) (((x) & 3) << 2) +#define V_WIN0_CBR_AXI_GATHER_EN(x) (((x) & 1) << 1) +#define V_WIN0_YRGB_AXI_GATHER_EN(x) ((x) & 1) + +/*VOP_WIN0_COLOR_KEY*/ +#define M_WIN0_KEY_EN (1 << 31) +#define M_WIN0_KEY_COLOR (0x3fffffff) + +#define V_WIN0_KEY_EN(x) (((x) & 1) << 31) +#define V_WIN0_KEY_COLOR(x) ((x) & 0x3fffffff) + +/* VOP_WIN0_VIR */ +#define V_ARGB888_VIRWIDTH(x) (((x) & 0x3fff) << 0) +#define V_RGB888_VIRWIDTH(x) (((((x * 3) >> 2)+((x) % 3)) & 0x3fff) << 0) +#define V_RGB565_VIRWIDTH(x) (((x / 2) & 0x3fff) << 0) +#define YUV_VIRWIDTH(x) (((x / 4) & 0x3fff) << 0) + +/* VOP_WIN0_ACT_INFO */ +#define V_ACT_HEIGHT(x) (((x) & 0x1fff) << 16) +#define V_ACT_WIDTH(x) ((x) & 0x1fff) + +/* VOP_WIN0_DSP_INFO */ +#define V_DSP_HEIGHT(x) (((x) & 0xfff) << 16) +#define V_DSP_WIDTH(x) ((x) & 0xfff) + +/* VOP_WIN0_DSP_ST */ +#define V_DSP_YST(x) (((x) & 0x1fff) << 16) +#define V_DSP_XST(x) ((x) & 0x1fff) + +/* VOP_WIN0_SCL_OFFSET */ +#define V_WIN0_VS_OFFSET_CBR(x) (((x) & 0xff) << 24) +#define V_WIN0_VS_OFFSET_YRGB(x) (((x) & 0xff) << 16) +#define V_WIN0_HS_OFFSET_CBR(x) (((x) & 0xff) << 8) +#define V_WIN0_HS_OFFSET_YRGB(x) ((x) & 0xff) + +#define V_HSYNC(x) (((x)&0x1fff)<<0) /* hsync pulse width */ +#define V_HORPRD(x) (((x)&0x1fff)<<16) /* horizontal period */ +#define V_VSYNC(x) (((x)&0x1fff)<<0) +#define V_VERPRD(x) (((x)&0x1fff)<<16) + +#define V_HEAP(x) (((x)&0x1fff)<<0)/* horizontal active end */ +#define V_HASP(x) (((x)&0x1fff)<<16)/* horizontal active start */ +#define V_VAEP(x) (((x)&0x1fff)<<0) +#define V_VASP(x) (((x)&0x1fff)<<16) + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rv1108/boot0.h b/roms/u-boot/arch/arm/include/asm/arch-rv1108/boot0.h new file mode 100644 index 000000000..2e78b074a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rv1108/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-rv1108/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-rv1108/gpio.h new file mode 100644 index 000000000..eca79d515 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-rv1108/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-sa1100/bitfield.h b/roms/u-boot/arch/arm/include/asm/arch-sa1100/bitfield.h new file mode 100644 index 000000000..104a21c2e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sa1100/bitfield.h @@ -0,0 +1,112 @@ +/* + * FILE bitfield.h + * + * Version 1.1 + * Author Copyright (c) Marc A. Viredaz, 1998 + * DEC Western Research Laboratory, Palo Alto, CA + * Date April 1998 (April 1997) + * System Advanced RISC Machine (ARM) + * Language C or ARM Assembly + * Purpose Definition of macros to operate on bit fields. + */ + + +#ifndef __BITFIELD_H +#define __BITFIELD_H + +#ifndef __ASSEMBLY__ +#define UData(Data) ((unsigned long) (Data)) +#else +#define UData(Data) (Data) +#endif + + +/* + * MACRO: Fld + * + * Purpose + * The macro "Fld" encodes a bit field, given its size and its shift value + * with respect to bit 0. + * + * Note + * A more intuitive way to encode bit fields would have been to use their + * mask. However, extracting size and shift value information from a bit + * field's mask is cumbersome and might break the assembler (255-character + * line-size limit). + * + * Input + * Size Size of the bit field, in number of bits. + * Shft Shift value of the bit field with respect to bit 0. + * + * Output + * Fld Encoded bit field. + */ + +#define Fld(Size, Shft) (((Size) << 16) + (Shft)) + + +/* + * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit + * + * Purpose + * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return + * the size, shift value, mask, aligned mask, and first bit of a + * bit field. + * + * Input + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FSize Size of the bit field, in number of bits. + * FShft Shift value of the bit field with respect to bit 0. + * FMsk Mask for the bit field. + * FAlnMsk Mask for the bit field, aligned on bit 0. + * F1stBit First bit of the bit field. + */ + +#define FSize(Field) ((Field) >> 16) +#define FShft(Field) ((Field) & 0x0000FFFF) +#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) +#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) +#define F1stBit(Field) (UData (1) << FShft (Field)) + + +/* + * MACRO: FInsrt + * + * Purpose + * The macro "FInsrt" inserts a value into a bit field by shifting the + * former appropriately. + * + * Input + * Value Bit-field value. + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FInsrt Bit-field value positioned appropriately. + */ + +#define FInsrt(Value, Field) \ + (UData (Value) << FShft (Field)) + + +/* + * MACRO: FExtr + * + * Purpose + * The macro "FExtr" extracts the value of a bit field by masking and + * shifting it appropriately. + * + * Input + * Data Data containing the bit-field to be extracted. + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FExtr Bit-field value. + */ + +#define FExtr(Data, Field) \ + ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) + + +#endif /* __BITFIELD_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-spear/clk.h b/roms/u-boot/arch/arm/include/asm/arch-spear/clk.h new file mode 100644 index 000000000..b193f764b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-spear/clk.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2010, STMicroelectronics - All Rights Reserved + * Author(s): Vipin Kumar, for STMicroelectronics. + */ + +static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) +{ + return 83000000; +} diff --git a/roms/u-boot/arch/arm/include/asm/arch-spear/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-spear/gpio.h new file mode 100644 index 000000000..4c8c40b1c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-spear/gpio.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 Stefan Roese + */ + + +#ifndef __ASM_ARCH_SPEAR_GPIO_H +#define __ASM_ARCH_SPEAR_GPIO_H + +enum gpio_direction { + GPIO_DIRECTION_IN, + GPIO_DIRECTION_OUT, +}; + +struct gpio_regs { + u32 gpiodata[0x100]; /* 0x000 ... 0x3fc */ + u32 gpiodir; /* 0x400 */ +}; + +#define SPEAR_GPIO_COUNT 8 +#define DATA_REG_ADDR(gpio) (1 << (gpio + 2)) + +#endif /* __ASM_ARCH_SPEAR_GPIO_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-spear/hardware.h b/roms/u-boot/arch/arm/include/asm/arch-spear/hardware.h new file mode 100644 index 000000000..c05bd44c4 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-spear/hardware.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2009, STMicroelectronics - All Rights Reserved + * Author(s): Vipin Kumar, for STMicroelectronics. + */ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +#define CONFIG_SYS_USBD_BASE 0xE1100000 +#define CONFIG_SYS_PLUG_BASE 0xE1200000 +#define CONFIG_SYS_FIFO_BASE 0xE1000800 +#define CONFIG_SYS_UHC0_EHCI_BASE 0xE1800000 +#define CONFIG_SYS_UHC1_EHCI_BASE 0xE2000000 +#define CONFIG_SYS_SMI_BASE 0xFC000000 +#define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000 +#define CONFIG_SPEAR_TIMERBASE 0xFC800000 +#define CONFIG_SPEAR_MISCBASE 0xFCA80000 +#define CONFIG_SPEAR_ETHBASE 0xE0800000 +#define CONFIG_SPEAR_MPMCBASE 0xFC600000 +#define CONFIG_SSP1_BASE 0xD0100000 +#define CONFIG_SSP2_BASE 0xD0180000 +#define CONFIG_SSP3_BASE 0xD8180000 +#define CONFIG_GPIO_BASE 0xD8100000 + +#define CONFIG_SYS_NAND_CLE (1 << 16) +#define CONFIG_SYS_NAND_ALE (1 << 17) + +#if defined(CONFIG_SPEAR600) +#define CONFIG_SYS_FSMC_BASE 0xD1800000 +#define CONFIG_FSMC_NAND_BASE 0xD2000000 + +#define CONFIG_SPEAR_BOOTSTRAPCFG 0xFCA80000 +#define CONFIG_SPEAR_BOOTSTRAPSHFT 16 +#define CONFIG_SPEAR_BOOTSTRAPMASK 0xB +#define CONFIG_SPEAR_ONLYSNORBOOT 0xA +#define CONFIG_SPEAR_NORNANDBOOT 0xB +#define CONFIG_SPEAR_NORNAND8BOOT 0x8 +#define CONFIG_SPEAR_NORNAND16BOOT 0x9 +#define CONFIG_SPEAR_USBBOOT 0x8 + +#define CONFIG_SPEAR_MPMCREGS 100 + +#elif defined(CONFIG_SPEAR300) +#define CONFIG_SYS_FSMC_BASE 0x94000000 + +#elif defined(CONFIG_SPEAR310) +#define CONFIG_SYS_FSMC_BASE 0x44000000 + +#undef CONFIG_SYS_NAND_CLE +#undef CONFIG_SYS_NAND_ALE +#define CONFIG_SYS_NAND_CLE (1 << 17) +#define CONFIG_SYS_NAND_ALE (1 << 16) + +#define CONFIG_SPEAR_EMIBASE 0x4F000000 +#define CONFIG_SPEAR_RASBASE 0xB4000000 + +#define CONFIG_SYS_MACB0_BASE 0xB0000000 +#define CONFIG_SYS_MACB1_BASE 0xB0800000 +#define CONFIG_SYS_MACB2_BASE 0xB1000000 +#define CONFIG_SYS_MACB3_BASE 0xB1800000 + +#elif defined(CONFIG_SPEAR320) +#define CONFIG_SYS_FSMC_BASE 0x4C000000 + +#define CONFIG_SPEAR_EMIBASE 0x40000000 +#define CONFIG_SPEAR_RASBASE 0xB3000000 + +#define CONFIG_SYS_MACB0_BASE 0xAA000000 + +#endif +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-spear/spr_defs.h b/roms/u-boot/arch/arm/include/asm/arch-spear/spr_defs.h new file mode 100644 index 000000000..d09e7eb63 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-spear/spr_defs.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + */ + +#ifndef __SPR_DEFS_H__ +#define __SPR_DEFS_H__ + +extern int spear_board_init(ulong); +extern void setfreq(unsigned int, unsigned int); +extern unsigned int setfreq_sz; + +void plat_ddr_init(void); +void spear_late_init(void); + +int snor_boot_selected(void); +int nand_boot_selected(void); +int pnor_boot_selected(void); +int usb_boot_selected(void); +int uart_boot_selected(void); +int tftp_boot_selected(void); +int i2c_boot_selected(void); +int spi_boot_selected(void); +int mmc_boot_selected(void); + +extern u32 mpmc_conf_vals[]; + +struct chip_data { + int cpufreq; + int dramfreq; + int dramtype; + uchar version[32]; +}; + +/* HW mac id in i2c memory definitions */ +#define MAGIC_OFF 0x0 +#define MAGIC_LEN 0x2 +#define MAGIC_BYTE0 0x55 +#define MAGIC_BYTE1 0xAA +#define MAC_OFF 0x2 +#define MAC_LEN 0x6 + +#define PNOR_WIDTH_8 0 +#define PNOR_WIDTH_16 1 +#define PNOR_WIDTH_32 2 +#define PNOR_WIDTH_NUM 3 +#define PNOR_WIDTH_SEARCH 0xff + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-spear/spr_emi.h b/roms/u-boot/arch/arm/include/asm/arch-spear/spr_emi.h new file mode 100644 index 000000000..7b1cf35d3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-spear/spr_emi.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com + */ + +#ifndef __SPEAR_EMI_H__ +#define __SPEAR_EMI_H__ + +#ifdef CONFIG_SPEAR_EMI + +struct emi_bank_regs { + u32 tap; + u32 tsdp; + u32 tdpw; + u32 tdpr; + u32 tdcs; + u32 control; +}; + +struct emi_regs { + struct emi_bank_regs bank_regs[CONFIG_SYS_MAX_FLASH_BANKS]; + u32 tout; + u32 ack; + u32 irq; +}; + +#define EMI_ACKMSK 0x40 + +/* control register definitions */ +#define EMI_CNTL_ENBBYTEW (1 << 2) +#define EMI_CNTL_ENBBYTER (1 << 3) +#define EMI_CNTL_ENBBYTERW (EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW) + +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-spear/spr_gpt.h b/roms/u-boot/arch/arm/include/asm/arch-spear/spr_gpt.h new file mode 100644 index 000000000..dced0a17a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-spear/spr_gpt.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + */ + +#ifndef _SPR_GPT_H +#define _SPR_GPT_H + +struct gpt_regs { + u8 reserved[0x80]; + u32 control; + u32 status; + u32 compare; + u32 count; + u32 capture_re; + u32 capture_fe; +}; + +/* + * TIMER_CONTROL register settings + */ + +#define GPT_PRESCALER_MASK 0x000F +#define GPT_PRESCALER_1 0x0000 +#define GPT_PRESCALER_2 0x0001 +#define GPT_PRESCALER_4 0x0002 +#define GPT_PRESCALER_8 0x0003 +#define GPT_PRESCALER_16 0x0004 +#define GPT_PRESCALER_32 0x0005 +#define GPT_PRESCALER_64 0x0006 +#define GPT_PRESCALER_128 0x0007 +#define GPT_PRESCALER_256 0x0008 + +#define GPT_MODE_SINGLE_SHOT 0x0010 +#define GPT_MODE_AUTO_RELOAD 0x0000 + +#define GPT_ENABLE 0x0020 + +#define GPT_CAPT_MODE_MASK 0x00C0 +#define GPT_CAPT_MODE_NONE 0x0000 +#define GPT_CAPT_MODE_RE 0x0040 +#define GPT_CAPT_MODE_FE 0x0080 +#define GPT_CAPT_MODE_BOTH 0x00C0 + +#define GPT_INT_MATCH 0x0100 +#define GPT_INT_FE 0x0200 +#define GPT_INT_RE 0x0400 + +/* + * TIMER_STATUS register settings + */ + +#define GPT_STS_MATCH 0x0001 +#define GPT_STS_FE 0x0002 +#define GPT_STS_RE 0x0004 + +/* + * TIMER_COMPARE register settings + */ + +#define GPT_FREE_RUNNING 0xFFFF + +/* Timer, HZ specific defines */ +#define CONFIG_SPEAR_HZ 1000 +#define CONFIG_SPEAR_HZ_CLOCK 8300000 + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-spear/spr_misc.h b/roms/u-boot/arch/arm/include/asm/arch-spear/spr_misc.h new file mode 100644 index 000000000..017111935 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-spear/spr_misc.h @@ -0,0 +1,260 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + */ + +#ifndef _SPR_MISC_H +#define _SPR_MISC_H + +struct misc_regs { + u32 auto_cfg_reg; /* 0x0 */ + u32 armdbg_ctr_reg; /* 0x4 */ + u32 pll1_cntl; /* 0x8 */ + u32 pll1_frq; /* 0xc */ + u32 pll1_mod; /* 0x10 */ + u32 pll2_cntl; /* 0x14 */ + u32 pll2_frq; /* 0x18 */ + u32 pll2_mod; /* 0x1C */ + u32 pll_ctr_reg; /* 0x20 */ + u32 amba_clk_cfg; /* 0x24 */ + u32 periph_clk_cfg; /* 0x28 */ + u32 periph1_clken; /* 0x2C */ + u32 soc_core_id; /* 0x30 */ + u32 ras_clken; /* 0x34 */ + u32 periph1_rst; /* 0x38 */ + u32 periph2_rst; /* 0x3C */ + u32 ras_rst; /* 0x40 */ + u32 prsc1_clk_cfg; /* 0x44 */ + u32 prsc2_clk_cfg; /* 0x48 */ + u32 prsc3_clk_cfg; /* 0x4C */ + u32 amem_cfg_ctrl; /* 0x50 */ + u32 expi_clk_cfg; /* 0x54 */ + u32 reserved_1; /* 0x58 */ + u32 clcd_synth_clk; /* 0x5C */ + u32 irda_synth_clk; /* 0x60 */ + u32 uart_synth_clk; /* 0x64 */ + u32 gmac_synth_clk; /* 0x68 */ + u32 ras_synth1_clk; /* 0x6C */ + u32 ras_synth2_clk; /* 0x70 */ + u32 ras_synth3_clk; /* 0x74 */ + u32 ras_synth4_clk; /* 0x78 */ + u32 arb_icm_ml1; /* 0x7C */ + u32 arb_icm_ml2; /* 0x80 */ + u32 arb_icm_ml3; /* 0x84 */ + u32 arb_icm_ml4; /* 0x88 */ + u32 arb_icm_ml5; /* 0x8C */ + u32 arb_icm_ml6; /* 0x90 */ + u32 arb_icm_ml7; /* 0x94 */ + u32 arb_icm_ml8; /* 0x98 */ + u32 arb_icm_ml9; /* 0x9C */ + u32 dma_src_sel; /* 0xA0 */ + u32 uphy_ctr_reg; /* 0xA4 */ + u32 gmac_ctr_reg; /* 0xA8 */ + u32 port_bridge_ctrl; /* 0xAC */ + u32 reserved_2[4]; /* 0xB0--0xBC */ + u32 prc1_ilck_ctrl_reg; /* 0xC0 */ + u32 prc2_ilck_ctrl_reg; /* 0xC4 */ + u32 prc3_ilck_ctrl_reg; /* 0xC8 */ + u32 prc4_ilck_ctrl_reg; /* 0xCC */ + u32 prc1_intr_ctrl_reg; /* 0xD0 */ + u32 prc2_intr_ctrl_reg; /* 0xD4 */ + u32 prc3_intr_ctrl_reg; /* 0xD8 */ + u32 prc4_intr_ctrl_reg; /* 0xDC */ + u32 powerdown_cfg_reg; /* 0xE0 */ + u32 ddr_1v8_compensation; /* 0xE4 */ + u32 ddr_2v5_compensation; /* 0xE8 */ + u32 core_3v3_compensation; /* 0xEC */ + u32 ddr_pad; /* 0xF0 */ + u32 bist1_ctr_reg; /* 0xF4 */ + u32 bist2_ctr_reg; /* 0xF8 */ + u32 bist3_ctr_reg; /* 0xFC */ + u32 bist4_ctr_reg; /* 0x100 */ + u32 bist5_ctr_reg; /* 0x104 */ + u32 bist1_rslt_reg; /* 0x108 */ + u32 bist2_rslt_reg; /* 0x10C */ + u32 bist3_rslt_reg; /* 0x110 */ + u32 bist4_rslt_reg; /* 0x114 */ + u32 bist5_rslt_reg; /* 0x118 */ + u32 syst_error_reg; /* 0x11C */ + u32 reserved_3[0x1FB8]; /* 0x120--0x7FFC */ + u32 ras_gpp1_in; /* 0x8000 */ + u32 ras_gpp2_in; /* 0x8004 */ + u32 ras_gpp1_out; /* 0x8008 */ + u32 ras_gpp2_out; /* 0x800C */ +}; + +/* SYNTH_CLK value*/ +#define SYNTH23 0x00020003 + +/* PLLx_FRQ value */ +#if defined(CONFIG_SPEAR3XX) +#define FREQ_332 0xA600010C +#define FREQ_266 0x8500010C +#elif defined(CONFIG_SPEAR600) +#define FREQ_332 0xA600010F +#define FREQ_266 0x8500010F +#endif + +/* PLL_CTR_REG */ +#define MEM_CLK_SEL_MSK 0x70000000 +#define MEM_CLK_HCLK 0x00000000 +#define MEM_CLK_2HCLK 0x10000000 +#define MEM_CLK_PLL2 0x30000000 + +#define EXPI_CLK_CFG_LOW_COMPR 0x2000 +#define EXPI_CLK_CFG_CLK_EN 0x0400 +#define EXPI_CLK_CFG_RST 0x0200 +#define EXPI_CLK_SYNT_EN 0x0010 +#define EXPI_CLK_CFG_SEL_PLL2 0x0004 +#define EXPI_CLK_CFG_INT_CLK_EN 0x0001 + +#define PLL2_CNTL_6UA 0x1c00 +#define PLL2_CNTL_SAMPLE 0x0008 +#define PLL2_CNTL_ENABLE 0x0004 +#define PLL2_CNTL_RESETN 0x0002 +#define PLL2_CNTL_LOCK 0x0001 + +/* AUTO_CFG_REG value */ +#define MISC_SOCCFGMSK 0x0000003F +#define MISC_SOCCFG30 0x0000000C +#define MISC_SOCCFG31 0x0000000D +#define MISC_NANDDIS 0x00020000 + +/* PERIPH_CLK_CFG value */ +#define MISC_GPT3SYNTH 0x00000400 +#define MISC_GPT4SYNTH 0x00000800 +#define CONFIG_SPEAR_UART48M 0 +#define CONFIG_SPEAR_UARTCLKMSK (0x1 << 4) + +/* PRSC_CLK_CFG value */ +/* + * Fout = Fin / (2^(N+1) * (M + 1)) + */ +#define MISC_PRSC_N_1 0x00001000 +#define MISC_PRSC_M_9 0x00000009 +#define MISC_PRSC_N_4 0x00004000 +#define MISC_PRSC_M_399 0x0000018F +#define MISC_PRSC_N_6 0x00006000 +#define MISC_PRSC_M_2593 0x00000A21 +#define MISC_PRSC_M_124 0x0000007C +#define MISC_PRSC_CFG (MISC_PRSC_N_1 | MISC_PRSC_M_9) + +/* PERIPH1_CLKEN, PERIPH1_RST value */ +#define MISC_USBDENB 0x01000000 +#define MISC_ETHENB 0x00800000 +#define MISC_SMIENB 0x00200000 +#define MISC_GPIO3ENB 0x00040000 +#define MISC_GPT3ENB 0x00010000 +#define MISC_SSP3ENB 0x00004000 +#define MISC_GPIO4ENB 0x00002000 +#define MISC_GPT2ENB 0x00000800 +#define MISC_FSMCENB 0x00000200 +#define MISC_I2CENB 0x00000080 +#define MISC_SSP2ENB 0x00000040 +#define MISC_SSP1ENB 0x00000020 +#define MISC_UART0ENB 0x00000008 + +/* PERIPH_CLK_CFG */ +#define XTALTIMEEN 0x00000001 +#define PLLTIMEEN 0x00000002 +#define CLCDCLK_SYNTH 0x00000000 +#define CLCDCLK_48MHZ 0x00000004 +#define CLCDCLK_EXT 0x00000008 +#define UARTCLK_MASK (0x1 << 4) +#define UARTCLK_48MHZ 0x00000000 +#define UARTCLK_SYNTH 0x00000010 +#define IRDACLK_48MHZ 0x00000000 +#define IRDACLK_SYNTH 0x00000020 +#define IRDACLK_EXT 0x00000040 +#define RTC_DISABLE 0x00000080 +#define GPT1CLK_48MHZ 0x00000000 +#define GPT1CLK_SYNTH 0x00000100 +#define GPT2CLK_48MHZ 0x00000000 +#define GPT2CLK_SYNTH 0x00000200 +#define GPT3CLK_48MHZ 0x00000000 +#define GPT3CLK_SYNTH 0x00000400 +#define GPT4CLK_48MHZ 0x00000000 +#define GPT4CLK_SYNTH 0x00000800 +#define GPT5CLK_48MHZ 0x00000000 +#define GPT5CLK_SYNTH 0x00001000 +#define GPT1_FREEZE 0x00002000 +#define GPT2_FREEZE 0x00004000 +#define GPT3_FREEZE 0x00008000 +#define GPT4_FREEZE 0x00010000 +#define GPT5_FREEZE 0x00020000 + +/* PERIPH1_CLKEN bits */ +#define PERIPH_ARM1_WE 0x00000001 +#define PERIPH_ARM1 0x00000002 +#define PERIPH_ARM2 0x00000004 +#define PERIPH_UART1 0x00000008 +#define PERIPH_UART2 0x00000010 +#define PERIPH_SSP1 0x00000020 +#define PERIPH_SSP2 0x00000040 +#define PERIPH_I2C 0x00000080 +#define PERIPH_JPEG 0x00000100 +#define PERIPH_FSMC 0x00000200 +#define PERIPH_FIRDA 0x00000400 +#define PERIPH_GPT4 0x00000800 +#define PERIPH_GPT5 0x00001000 +#define PERIPH_GPIO4 0x00002000 +#define PERIPH_SSP3 0x00004000 +#define PERIPH_ADC 0x00008000 +#define PERIPH_GPT3 0x00010000 +#define PERIPH_RTC 0x00020000 +#define PERIPH_GPIO3 0x00040000 +#define PERIPH_DMA 0x00080000 +#define PERIPH_ROM 0x00100000 +#define PERIPH_SMI 0x00200000 +#define PERIPH_CLCD 0x00400000 +#define PERIPH_GMAC 0x00800000 +#define PERIPH_USBD 0x01000000 +#define PERIPH_USBH1 0x02000000 +#define PERIPH_USBH2 0x04000000 +#define PERIPH_MPMC 0x08000000 +#define PERIPH_RAMW 0x10000000 +#define PERIPH_MPMC_EN 0x20000000 +#define PERIPH_MPMC_WE 0x40000000 +#define PERIPH_MPMCMSK 0x60000000 + +#define PERIPH_CLK_ALL 0x0FFFFFF8 +#define PERIPH_RST_ALL 0x00000004 + +/* DDR_PAD values */ +#define DDR_PAD_CNF_MSK 0x0000ffff +#define DDR_PAD_SW_CONF 0x00060000 +#define DDR_PAD_SSTL_SEL 0x00000001 +#define DDR_PAD_DRAM_TYPE 0x00008000 + +/* DDR_COMP values */ +#define DDR_COMP_ACCURATE 0x00000010 + +/* SoC revision stuff */ +#define SOC_PRI_SHFT 16 +#define SOC_SEC_SHFT 8 + +/* Revision definitions */ +#define SOC_SPEAR_NA 0 + +/* + * The definitons have started from + * 101 for SPEAr6xx + * 201 for SPEAr3xx + * 301 for SPEAr13xx + */ +#define SOC_SPEAR600_AA 101 +#define SOC_SPEAR600_AB 102 +#define SOC_SPEAR600_BA 103 +#define SOC_SPEAR600_BB 104 +#define SOC_SPEAR600_BC 105 +#define SOC_SPEAR600_BD 106 + +#define SOC_SPEAR300 201 +#define SOC_SPEAR310 202 +#define SOC_SPEAR320 203 + +extern int get_socrev(void); +int fsmc_nand_switch_ecc(uint32_t eccstrength); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-spear/spr_ssp.h b/roms/u-boot/arch/arm/include/asm/arch-spear/spr_ssp.h new file mode 100644 index 000000000..088d34b40 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-spear/spr_ssp.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 Stefan Roese + */ + +#ifndef _SPR_SSP_H +#define _SPR_SSP_H + +struct ssp_regs { + u32 sspcr0; + u32 sspcr1; + u32 sspdr; + u32 sspsr; + u32 sspcpsr; + u32 sspimsc; + u32 sspicr; + u32 sspdmacr; +}; + +#define SSPCR0_FRF_MOT_SPI 0x0000 +#define SSPCR0_DSS_16BITS 0x000f + +#define SSPCR1_SSE 0x0002 + +#define SSPSR_TNF 0x2 +#define SSPSR_TFE 0x1 + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-spear/spr_syscntl.h b/roms/u-boot/arch/arm/include/asm/arch-spear/spr_syscntl.h new file mode 100644 index 000000000..6a83d87d1 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-spear/spr_syscntl.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com + */ + +#ifndef __SYSCTRL_H +#define __SYSCTRL_H + +struct syscntl_regs { + u32 scctrl; + u32 scsysstat; + u32 scimctrl; + u32 scimsysstat; + u32 scxtalctrl; + u32 scpllctrl; + u32 scpllfctrl; + u32 scperctrl0; + u32 scperctrl1; + u32 scperen; + u32 scperdis; + const u32 scperclken; + const u32 scperstat; +}; + +#define MODE_SHIFT 0x00000003 + +#define NORMAL 0x00000004 +#define SLOW 0x00000002 +#define DOZE 0x00000001 +#define SLEEP 0x00000000 + +#define PLL_TIM 0x01FFFFFF + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-stih410/sdhci.h b/roms/u-boot/arch/arm/include/asm/arch-stih410/sdhci.h new file mode 100644 index 000000000..1735c0e39 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stih410/sdhci.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, for STMicroelectronics. + */ + +#ifndef __STI_SDHCI_H__ +#define __STI_SDHCI_H__ + +#ifndef __ASSEMBLY__ +#include +#endif + +#define FLASHSS_MMC_CORE_CONFIG_1 0x400 +#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ BIT(24) +#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN BIT(12) + +#define STI_FLASHSS_MMC_CORE_CONFIG_1 \ + (FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ | \ + FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN) + +#define FLASHSS_MMC_CORE_CONFIG_2 0x404 +#define FLASHSS_MMC_CORECFG_HIGH_SPEED BIT(28) +#define FLASHSS_MMC_CORECFG_8BIT_EMMC BIT(20) +#define MAX_BLK_LENGTH_1024 BIT(16) +#define BASE_CLK_FREQ_200 0xc8 + +#define STI_FLASHSS_MMC_CORE_CONFIG2 \ + (FLASHSS_MMC_CORECFG_HIGH_SPEED | \ + FLASHSS_MMC_CORECFG_8BIT_EMMC | \ + MAX_BLK_LENGTH_1024 | \ + BASE_CLK_FREQ_200 << 0) + +#define STI_FLASHSS_SDCARD_CORE_CONFIG2 \ + (FLASHSS_MMC_CORECFG_HIGH_SPEED | \ + MAX_BLK_LENGTH_1024 | \ + BASE_CLK_FREQ_200) + +#define FLASHSS_MMC_CORE_CONFIG_3 0x408 +#define FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC BIT(28) +#define FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT BIT(20) +#define FLASHSS_MMC_CORECFG_3P3_VOLT BIT(8) +#define FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT BIT(4) +#define FLASHSS_MMC_CORECFG_SDMA BIT(0) + +#define STI_FLASHSS_MMC_CORE_CONFIG3 \ + (FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC | \ + FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \ + FLASHSS_MMC_CORECFG_3P3_VOLT | \ + FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \ + FLASHSS_MMC_CORECFG_SDMA) + +#define STI_FLASHSS_SDCARD_CORE_CONFIG3 \ + (FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \ + FLASHSS_MMC_CORECFG_3P3_VOLT | \ + FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \ + FLASHSS_MMC_CORECFG_SDMA) + +#define FLASHSS_MMC_CORE_CONFIG_4 0x40c +#define FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT BIT(20) +#define FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT BIT(16) +#define FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT BIT(12) + +#define STI_FLASHSS_MMC_CORE_CONFIG4 \ + (FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT | \ + FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT | \ + FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT) + +#define ST_MMC_CCONFIG_REG_5 0x210 +#define SYSCONF_MMC1_ENABLE_BIT 3 + +#endif /* _STI_SDHCI_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-stih410/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-stih410/sys_proto.h new file mode 100644 index 000000000..30e7f398e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stih410/sys_proto.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, for STMicroelectronics. + */ + +#ifndef _ASM_ARCH_SYS_PROTO_H +#define _ASM_ARCH_SYS_PROTO_H + +#endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-stm32/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-stm32/gpio.h new file mode 100644 index 000000000..233ce278a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stm32/gpio.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016, STMicroelectronics - All Rights Reserved + * Author(s): Vikas Manocha, for STMicroelectronics. + */ + +#ifndef _GPIO_H_ +#define _GPIO_H_ + +enum stm32_gpio_mode { + STM32_GPIO_MODE_IN = 0, + STM32_GPIO_MODE_OUT, + STM32_GPIO_MODE_AF, + STM32_GPIO_MODE_AN +}; + +enum stm32_gpio_otype { + STM32_GPIO_OTYPE_PP = 0, + STM32_GPIO_OTYPE_OD +}; + +enum stm32_gpio_speed { + STM32_GPIO_SPEED_2M = 0, + STM32_GPIO_SPEED_25M, + STM32_GPIO_SPEED_50M, + STM32_GPIO_SPEED_100M +}; + +enum stm32_gpio_pupd { + STM32_GPIO_PUPD_NO = 0, + STM32_GPIO_PUPD_UP, + STM32_GPIO_PUPD_DOWN +}; + +enum stm32_gpio_af { + STM32_GPIO_AF0 = 0, + STM32_GPIO_AF1, + STM32_GPIO_AF2, + STM32_GPIO_AF3, + STM32_GPIO_AF4, + STM32_GPIO_AF5, + STM32_GPIO_AF6, + STM32_GPIO_AF7, + STM32_GPIO_AF8, + STM32_GPIO_AF9, + STM32_GPIO_AF10, + STM32_GPIO_AF11, + STM32_GPIO_AF12, + STM32_GPIO_AF13, + STM32_GPIO_AF14, + STM32_GPIO_AF15 +}; + +struct stm32_gpio_dsc { + u8 port; + u8 pin; +}; + +struct stm32_gpio_ctl { + enum stm32_gpio_mode mode; + enum stm32_gpio_otype otype; + enum stm32_gpio_speed speed; + enum stm32_gpio_pupd pupd; + enum stm32_gpio_af af; +}; + +struct stm32_gpio_regs { + u32 moder; /* GPIO port mode */ + u32 otyper; /* GPIO port output type */ + u32 ospeedr; /* GPIO port output speed */ + u32 pupdr; /* GPIO port pull-up/pull-down */ + u32 idr; /* GPIO port input data */ + u32 odr; /* GPIO port output data */ + u32 bsrr; /* GPIO port bit set/reset */ + u32 lckr; /* GPIO port configuration lock */ + u32 afr[2]; /* GPIO alternate function */ +}; + +struct stm32_gpio_priv { + struct stm32_gpio_regs *regs; + unsigned int gpio_range; +}; + +int stm32_offset_to_index(struct udevice *dev, unsigned int offset); + +#endif /* _GPIO_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-stm32/stm32f.h b/roms/u-boot/arch/arm/include/asm/arch-stm32/stm32f.h new file mode 100644 index 000000000..a1ce81eca --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stm32/stm32f.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, for STMicroelectronics. + */ + +#ifndef _ASM_ARCH_STM32F_H +#define _ASM_ARCH_STM32F_H + +#define STM32_PERIPH_BASE 0x40000000UL + +#define STM32_APB2_PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000) +#define STM32_AHB1_PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000) + +#define STM32_SYSCFG_BASE (STM32_APB2_PERIPH_BASE + 0x3800) +#define STM32_FLASH_CNTL_BASE (STM32_AHB1_PERIPH_BASE + 0x3C00) + +void stm32_flash_latency_cfg(int latency); + +#endif /* _ASM_ARCH_STM32F_H */ + diff --git a/roms/u-boot/arch/arm/include/asm/arch-stm32f4/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-stm32f4/gpio.h new file mode 100644 index 000000000..490f686a8 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stm32f4/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 + * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com + * + * (C) Copyright 2015 + * Kamil Lulko, + */ + +#ifndef _STM32_GPIO_H_ +#define _STM32_GPIO_H_ + +#include + +#endif /* _STM32_GPIO_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-stm32f4/stm32.h b/roms/u-boot/arch/arm/include/asm/arch-stm32f4/stm32.h new file mode 100644 index 000000000..2094bd732 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 + * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com + * + * (C) Copyright 2015 + * Kamil Lulko, + */ + +#ifndef _MACH_STM32_H_ +#define _MACH_STM32_H_ + +#include + +/* + * Peripheral memory map + */ +#define STM32_SYSMEM_BASE 0x1FFF0000 + +/* + * Register maps + */ +struct stm32_u_id_regs { + u32 u_id_low; + u32 u_id_mid; + u32 u_id_high; +}; + +/* + * Registers access macros + */ +#define STM32_U_ID_BASE (STM32_SYSMEM_BASE + 0x7A10) +#define STM32_U_ID ((struct stm32_u_id_regs *)STM32_U_ID_BASE) +static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { + [0 ... 3] = 16 * 1024, + [4] = 64 * 1024, + [5 ... 11] = 128 * 1024 +}; + +#endif /* _MACH_STM32_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h b/roms/u-boot/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h new file mode 100644 index 000000000..fe6ca03d2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, for STMicroelectronics. + */ + +#ifndef __STM32_PWR_H_ +#define __STM32_PWR_H_ + +#ifndef __ASSEMBLY__ +#include +#endif + +/* + * Offsets of some PWR registers + */ +#define PWR_CR1_ODEN BIT(16) +#define PWR_CR1_ODSWEN BIT(17) +#define PWR_CSR1_ODRDY BIT(16) +#define PWR_CSR1_ODSWRDY BIT(17) + +struct stm32_pwr_regs { + u32 cr1; /* power control register 1 */ + u32 csr1; /* power control/status register 2 */ +}; + +#endif /* __STM32_PWR_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-stm32f7/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-stm32f7/gpio.h new file mode 100644 index 000000000..21f4e0fd2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stm32f7/gpio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016, STMicroelectronics - All Rights Reserved + * Author(s): Vikas Manocha, for STMicroelectronics. + */ + +#ifndef _STM32_GPIO_H_ +#define _STM32_GPIO_H_ + +#include + +#endif /* _STM32_GPIO_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-stm32f7/stm32.h b/roms/u-boot/arch/arm/include/asm/arch-stm32f7/stm32.h new file mode 100644 index 000000000..3451e74a3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stm32f7/stm32.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016, STMicroelectronics - All Rights Reserved + * Author(s): Vikas Manocha, for STMicroelectronics. + */ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +#include + +static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { + [0 ... 3] = 32 * 1024, + [4] = 128 * 1024, + [5 ... 7] = 256 * 1024 +}; + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h b/roms/u-boot/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h new file mode 100644 index 000000000..5cd6553d0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, for STMicroelectronics. + */ + +#ifndef __STM32_PWR_H_ +#define __STM32_PWR_H_ + +#ifndef __ASSEMBLY__ +#include +#endif + +/* + * Offsets of some PWR registers + */ +#define PWR_CR1_ODEN BIT(16) +#define PWR_CR1_ODSWEN BIT(17) +#define PWR_CSR1_ODRDY BIT(16) +#define PWR_CSR1_ODSWRDY BIT(17) + +struct stm32_pwr_regs { + u32 cr1; /* power control register 1 */ + u32 csr1; /* power control/status register 2 */ + u32 cr2; /* power control register 2 */ + u32 csr2; /* power control/status register 2 */ +}; + +#endif /* __STM32_PWR_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-stm32f7/syscfg.h b/roms/u-boot/arch/arm/include/asm/arch-stm32f7/syscfg.h new file mode 100644 index 000000000..985ae2544 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stm32f7/syscfg.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 + * Michael Kurz, michi.kurz@gmail.com. + */ + +#ifndef _STM32_SYSCFG_H +#define _STM32_SYSCFG_H + +#ifndef __ASSEMBLY__ +#include +#endif + +struct stm32_syscfg_regs { + u32 memrmp; + u32 pmc; + u32 exticr1; + u32 exticr2; + u32 exticr3; + u32 exticr4; + u32 cmpcr; +}; + +/* + * SYSCFG registers base + */ +#define STM32_SYSCFG ((struct stm32_syscfg_regs *)STM32_SYSCFG_BASE) + +/* SYSCFG peripheral mode configuration register */ +#define SYSCFG_PMC_MII_RMII_SEL BIT(23) + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-stm32h7/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-stm32h7/gpio.h new file mode 100644 index 000000000..4f57f175f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stm32h7/gpio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, for STMicroelectronics. + */ + +#ifndef _STM32_GPIO_H_ +#define _STM32_GPIO_H_ + +#include + +#endif /* _STM32_GPIO_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-stm32h7/stm32.h b/roms/u-boot/arch/arm/include/asm/arch-stm32h7/stm32.h new file mode 100644 index 000000000..2b0a67000 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stm32h7/stm32.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, for STMicroelectronics. + */ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +/* + * This empty files is needed to not break compilation + * Some common drivers to STM32F4/F7 and H7 include a stm32.h file + * Some cleanup need to be done to communalize all the following + * stm32.h files: + * + * arch/arm/include/asm/arch-stm32f1/stm32.h + * arch/arm/include/asm/arch-stm32f4/stm32.h + * arch/arm/include/asm/arch-stm32f7/stm32.h + */ +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-stv0991/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-stv0991/gpio.h new file mode 100644 index 000000000..b27f40785 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stv0991/gpio.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014, STMicroelectronics - All Rights Reserved + * Author(s): Vikas Manocha, for STMicroelectronics. + */ + +#ifndef __ASM_ARCH_STV0991_GPIO_H +#define __ASM_ARCH_STV0991_GPIO_H + +enum gpio_direction { + GPIO_DIRECTION_IN, + GPIO_DIRECTION_OUT, +}; + +struct gpio_regs { + u32 data; /* offset 0x0 */ + u32 reserved[0xff]; /* 0x4--0x3fc */ + u32 dir; /* offset 0x400 */ +}; + +#endif /* __ASM_ARCH_STV0991_GPIO_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-stv0991/hardware.h b/roms/u-boot/arch/arm/include/asm/arch-stv0991/hardware.h new file mode 100644 index 000000000..ea8f82063 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stv0991/hardware.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014, STMicroelectronics - All Rights Reserved + * Author(s): Vikas Manocha, for STMicroelectronics. + */ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +/* STV0991 */ +#define SRAM0_BASE_ADDR 0x00000000UL +#define SRAM1_BASE_ADDR 0x00068000UL +#define SRAM2_BASE_ADDR 0x000D0000UL +#define SRAM3_BASE_ADDR 0x00138000UL +#define CFS_SRAM0_BASE_ADDR 0x00198000UL +#define CFS_SRAM1_BASE_ADDR 0x001B8000UL +#define FAST_SRAM_BASE_ADDR 0x001D8000UL +#define FLASH_BASE_ADDR 0x40000000UL +#define PL310_BASE_ADDR 0x70000000UL +#define HSAXIM_BASE_ADDR 0x70100000UL +#define IMGSS_BASE_ADDR 0x70200000UL +#define ADC_BASE_ADDR 0x80000000UL +#define GPIOA_BASE_ADDR 0x80001000UL +#define GPIOB_BASE_ADDR 0x80002000UL +#define GPIOC_BASE_ADDR 0x80003000UL +#define HDM_BASE_ADDR 0x80004000UL +#define THSENS_BASE_ADDR 0x80200000UL +#define GPTIMER2_BASE_ADDR 0x80201000UL +#define GPTIMER1_BASE_ADDR 0x80202000UL +#define QSPI_BASE_ADDR 0x80203000UL +#define CGU_BASE_ADDR 0x80204000UL +#define CREG_BASE_ADDR 0x80205000UL +#define PEC_BASE_ADDR 0x80206000UL +#define WDRU_BASE_ADDR 0x80207000UL +#define BSEC_BASE_ADDR 0x80208000UL +#define DAP_ROM_BASE_ADDR 0x80210000UL +#define SOC_CTI_BASE_ADDR 0x80211000UL +#define TPIU_BASE_ADDR 0x80212000UL +#define TMC_ETF_BASE_ADDR 0x80213000UL +#define R4_ETM_BASE_ADDR 0x80214000UL +#define R4_CTI_BASE_ADDR 0x80215000UL +#define R4_DBG_BASE_ADDR 0x80216000UL +#define GMAC_BASE_ADDR 0x80300000UL +#define RNSS_BASE_ADDR 0x80302000UL +#define CRYP_BASE_ADDR 0x80303000UL +#define HASH_BASE_ADDR 0x80304000UL +#define GPDMA_BASE_ADDR 0x80305000UL +#define ISA_BASE_ADDR 0x8032A000UL +#define HCI_BASE_ADDR 0x80400000UL +#define I2C1_BASE_ADDR 0x80401000UL +#define I2C2_BASE_ADDR 0x80402000UL +#define SAI_BASE_ADDR 0x80403000UL +#define USI_BASE_ADDR 0x80404000UL +#define SPI1_BASE_ADDR 0x80405000UL +#define UART_BASE_ADDR 0x80406000UL +#define SPI2_BASE_ADDR 0x80500000UL +#define CAN_BASE_ADDR 0x80501000UL +#define USART1_BASE_ADDR 0x80502000UL +#define USART2_BASE_ADDR 0x80503000UL +#define USART3_BASE_ADDR 0x80504000UL +#define USART4_BASE_ADDR 0x80505000UL +#define USART5_BASE_ADDR 0x80506000UL +#define USART6_BASE_ADDR 0x80507000UL +#define SDI2_BASE_ADDR 0x80600000UL +#define SDI1_BASE_ADDR 0x80601000UL +#define VICA_BASE_ADDR 0x81000000UL +#define VICB_BASE_ADDR 0x81001000UL +#define STM_CHANNELS_BASE_ADDR 0x81100000UL +#define STM_BASE_ADDR 0x81110000UL +#define SROM_BASE_ADDR 0xFFFF0000UL + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h b/roms/u-boot/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h new file mode 100644 index 000000000..df9dd54e5 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014, STMicroelectronics - All Rights Reserved + * Author(s): Vikas Manocha, for STMicroelectronics. + */ + +#ifndef _STV0991_CGU_H +#define _STV0991_CGU_H + +struct stv0991_cgu_regs { + u32 cpu_freq; /* offset 0x0 */ + u32 icn2_freq; /* offset 0x4 */ + u32 dma_freq; /* offset 0x8 */ + u32 isp_freq; /* offset 0xc */ + u32 h264_freq; /* offset 0x10 */ + u32 osif_freq; /* offset 0x14 */ + u32 ren_freq; /* offset 0x18 */ + u32 tim_freq; /* offset 0x1c */ + u32 sai_freq; /* offset 0x20 */ + u32 eth_freq; /* offset 0x24 */ + u32 i2c_freq; /* offset 0x28 */ + u32 spi_freq; /* offset 0x2c */ + u32 uart_freq; /* offset 0x30 */ + u32 qspi_freq; /* offset 0x34 */ + u32 sdio_freq; /* offset 0x38 */ + u32 usi_freq; /* offset 0x3c */ + u32 can_line_freq; /* offset 0x40 */ + u32 debug_freq; /* offset 0x44 */ + u32 trace_freq; /* offset 0x48 */ + u32 stm_freq; /* offset 0x4c */ + u32 eth_ctrl; /* offset 0x50 */ + u32 reserved[3]; /* offset 0x54 */ + u32 osc_ctrl; /* offset 0x60 */ + u32 pll1_ctrl; /* offset 0x64 */ + u32 pll1_freq; /* offset 0x68 */ + u32 pll1_fract; /* offset 0x6c */ + u32 pll1_spread; /* offset 0x70 */ + u32 pll1_status; /* offset 0x74 */ + u32 pll2_ctrl; /* offset 0x78 */ + u32 pll2_freq; /* offset 0x7c */ + u32 pll2_fract; /* offset 0x80 */ + u32 pll2_spread; /* offset 0x84 */ + u32 pll2_status; /* offset 0x88 */ + u32 cgu_enable_1; /* offset 0x8c */ + u32 cgu_enable_2; /* offset 0x90 */ + u32 cgu_isp_pulse; /* offset 0x94 */ + u32 cgu_h264_pulse; /* offset 0x98 */ + u32 cgu_osif_pulse; /* offset 0x9c */ + u32 cgu_ren_pulse; /* offset 0xa0 */ + +}; + +/* CGU Timer */ +#define CLK_TMR_OSC 0 +#define CLK_TMR_MCLK 1 +#define CLK_TMR_PLL1 2 +#define CLK_TMR_PLL2 3 +#define MDIV_SHIFT_TMR 3 +#define DIV_SHIFT_TMR 6 + +#define TIMER1_CLK_CFG (0 << DIV_SHIFT_TMR \ + | 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK) + +/* Clock Enable/Disable */ + +#define TIMER1_CLK_EN (1 << 15) + +/* CGU Uart config */ +#define CLK_UART_MCLK 0 +#define CLK_UART_PLL1 1 +#define CLK_UART_PLL2 2 + +#define MDIV_SHIFT_UART 3 +#define DIV_SHIFT_UART 6 + +#define UART_CLK_CFG (4 << DIV_SHIFT_UART \ + | 1 << MDIV_SHIFT_UART | CLK_UART_MCLK) + +/* CGU Ethernet clock config */ +#define CLK_ETH_MCLK 0 +#define CLK_ETH_PLL1 1 +#define CLK_ETH_PLL2 2 + +#define MDIV_SHIFT_ETH 3 +#define DIV_SHIFT_ETH 6 +#define DIV_ETH_125 9 +#define DIV_ETH_50 12 +#define DIV_ETH_P2P 15 + +#define ETH_CLK_CFG (4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \ + | 1 << DIV_ETH_125 \ + | 0 << DIV_SHIFT_ETH \ + | 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1) + /* CGU Ethernet control */ + +#define ETH_CLK_TX_EXT_PHY 0 +#define ETH_CLK_TX_125M 1 +#define ETH_CLK_TX_25M 2 +#define ETH_CLK_TX_2M5 3 +#define ETH_CLK_TX_DIS 7 + +#define ETH_CLK_RX_EXT_PHY 0 +#define ETH_CLK_RX_25M 1 +#define ETH_CLK_RX_2M5 2 +#define ETH_CLK_RX_DIS 3 +#define RX_CLK_SHIFT 3 +#define ETH_CLK_MASK ~(0x1F) + +#define ETH_PHY_MODE_GMII 0 +#define ETH_PHY_MODE_RMII 1 +#define ETH_PHY_CLK_DIS 1 + +#define ETH_CLK_CTRL (ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \ + | ETH_CLK_TX_EXT_PHY) +/* CGU qspi clock */ +#define DIV_HCLK1_SHIFT 9 +#define DIV_CRYP_SHIFT 6 +#define MDIV_QSPI_SHIFT 3 + +#define CLK_QSPI_OSC 0 +#define CLK_QSPI_MCLK 1 +#define CLK_QSPI_PLL1 2 +#define CLK_QSPI_PLL2 3 + +#define QSPI_CLK_CTRL (3 << DIV_HCLK1_SHIFT \ + | 1 << DIV_CRYP_SHIFT \ + | 0 << MDIV_QSPI_SHIFT \ + | CLK_QSPI_OSC) + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-stv0991/stv0991_creg.h b/roms/u-boot/arch/arm/include/asm/arch-stv0991/stv0991_creg.h new file mode 100644 index 000000000..4d444a6df --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stv0991/stv0991_creg.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014, STMicroelectronics - All Rights Reserved + * Author(s): Vikas Manocha, for STMicroelectronics. + */ + +#ifndef _STV0991_CREG_H +#define _STV0991_CREG_H + +struct stv0991_creg { + u32 version; /* offset 0x0 */ + u32 hdpctl; /* offset 0x4 */ + u32 hdpval; /* offset 0x8 */ + u32 hdpgposet; /* offset 0xc */ + u32 hdpgpoclr; /* offset 0x10 */ + u32 hdpgpoval; /* offset 0x14 */ + u32 stm_mux; /* offset 0x18 */ + u32 sysctrl_1; /* offset 0x1c */ + u32 sysctrl_2; /* offset 0x20 */ + u32 sysctrl_3; /* offset 0x24 */ + u32 sysctrl_4; /* offset 0x28 */ + u32 reserved_1[0x35]; /* offset 0x2C-0xFC */ + u32 mux1; /* offset 0x100 */ + u32 mux2; /* offset 0x104 */ + u32 mux3; /* offset 0x108 */ + u32 mux4; /* offset 0x10c */ + u32 mux5; /* offset 0x110 */ + u32 mux6; /* offset 0x114 */ + u32 mux7; /* offset 0x118 */ + u32 mux8; /* offset 0x11c */ + u32 mux9; /* offset 0x120 */ + u32 mux10; /* offset 0x124 */ + u32 mux11; /* offset 0x128 */ + u32 mux12; /* offset 0x12c */ + u32 mux13; /* offset 0x130 */ + u32 reserved_2[0x33]; /* offset 0x134-0x1FC */ + u32 cfg_pad1; /* offset 0x200 */ + u32 cfg_pad2; /* offset 0x204 */ + u32 cfg_pad3; /* offset 0x208 */ + u32 cfg_pad4; /* offset 0x20c */ + u32 cfg_pad5; /* offset 0x210 */ + u32 cfg_pad6; /* offset 0x214 */ + u32 cfg_pad7; /* offset 0x218 */ + u32 reserved_3[0x39]; /* offset 0x21C-0x2FC */ + u32 vdd_pad1; /* offset 0x300 */ + u32 vdd_pad2; /* offset 0x304 */ + u32 reserved_4[0x3e]; /* offset 0x308-0x3FC */ + u32 vdd_comp1; /* offset 0x400 */ +}; + +/* CREG MUX 13 register */ +#define FLASH_CS_NC_SHIFT 4 +#define FLASH_CS_NC_MASK ~(7 << FLASH_CS_NC_SHIFT) +#define CFG_FLASH_CS_NC (0 << FLASH_CS_NC_SHIFT) + +#define FLASH_CLK_SHIFT 0 +#define FLASH_CLK_MASK ~(7 << FLASH_CLK_SHIFT) +#define CFG_FLASH_CLK (0 << FLASH_CLK_SHIFT) + +/* CREG MUX 12 register */ +#define GPIOC_30_MUX_SHIFT 24 +#define GPIOC_30_MUX_MASK ~(1 << GPIOC_30_MUX_SHIFT) +#define CFG_GPIOC_30_UART_TX (1 << GPIOC_30_MUX_SHIFT) + +#define GPIOC_31_MUX_SHIFT 28 +#define GPIOC_31_MUX_MASK ~(1 << GPIOC_31_MUX_SHIFT) +#define CFG_GPIOC_31_UART_RX (1 << GPIOC_31_MUX_SHIFT) + +/* CREG MUX 7 register */ +#define GPIOB_16_MUX_SHIFT 0 +#define GPIOB_16_MUX_MASK ~(1 << GPIOB_16_MUX_SHIFT) +#define CFG_GPIOB_16_UART_TX (1 << GPIOB_16_MUX_SHIFT) + +#define GPIOB_17_MUX_SHIFT 4 +#define GPIOB_17_MUX_MASK ~(1 << GPIOB_17_MUX_SHIFT) +#define CFG_GPIOB_17_UART_RX (1 << GPIOB_17_MUX_SHIFT) + +/* CREG CFG_PAD6 register */ + +#define GPIOC_31_MODE_SHIFT 30 +#define GPIOC_31_MODE_MASK ~(1 << GPIOC_31_MODE_SHIFT) +#define CFG_GPIOC_31_MODE_OD (0 << GPIOC_31_MODE_SHIFT) +#define CFG_GPIOC_31_MODE_PP (1 << GPIOC_31_MODE_SHIFT) + +#define GPIOC_30_MODE_SHIFT 28 +#define GPIOC_30_MODE_MASK ~(1 << GPIOC_30_MODE_SHIFT) +#define CFG_GPIOC_30_MODE_LOW (0 << GPIOC_30_MODE_SHIFT) +#define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT) + +/* CREG Ethernet pad config */ + +#define VDD_ETH_PS_1V8 0 +#define VDD_ETH_PS_2V5 2 +#define VDD_ETH_PS_3V3 3 +#define VDD_ETH_PS_MASK 0x3 + +#define VDD_ETH_PS_SHIFT 12 +#define ETH_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_PS_SHIFT) + +#define VDD_ETH_M_PS_SHIFT 28 +#define ETH_M_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_M_PS_SHIFT) + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-stv0991/stv0991_defs.h b/roms/u-boot/arch/arm/include/asm/arch-stv0991/stv0991_defs.h new file mode 100644 index 000000000..97d28b26f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stv0991/stv0991_defs.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014, STMicroelectronics - All Rights Reserved + * Author(s): Vikas Manocha, for STMicroelectronics. + */ + +#ifndef __STV0991_DEFS_H__ +#define __STV0991_DEFS_H__ +#include + +extern int stv0991_pinmux_config(enum periph_id); +extern int clock_setup(enum periph_clock); + +#endif + diff --git a/roms/u-boot/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/roms/u-boot/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h new file mode 100644 index 000000000..cd27472ad --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014, STMicroelectronics - All Rights Reserved + * Author(s): Vikas Manocha, for STMicroelectronics. + */ + +#ifndef _STV0991_GPT_H +#define _STV0991_GPT_H + +#include + +struct gpt_regs { + u32 cr1; + u32 cr2; + u32 reserved_1; + u32 dier; /* dma_int_en */ + u32 sr; /* status reg */ + u32 egr; /* event gen */ + u32 reserved_2[3]; /* offset 0x18--0x20*/ + u32 cnt; + u32 psc; + u32 arr; +}; + +struct gpt_regs *const gpt1_regs_ptr = + (struct gpt_regs *) GPTIMER1_BASE_ADDR; + +/* Timer control1 register */ +#define GPT_CR1_CEN 0x0001 +#define GPT_MODE_AUTO_RELOAD (1 << 7) + +/* Timer prescalar reg */ +#define GPT_PRESCALER_128 0x128 + +/* Auto reload register for free running config */ +#define GPT_FREE_RUNNING 0xFFFF + +/* Timer, HZ specific defines */ +#define CONFIG_STV0991_HZ 1000 +#define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128 + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-stv0991/stv0991_periph.h b/roms/u-boot/arch/arm/include/asm/arch-stv0991/stv0991_periph.h new file mode 100644 index 000000000..7a50be183 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stv0991/stv0991_periph.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014, STMicroelectronics - All Rights Reserved + * Author(s): Vikas Manocha, for STMicroelectronics. + */ + +#ifndef __ASM_ARM_ARCH_PERIPH_H +#define __ASM_ARM_ARCH_PERIPH_H + +/* + * Peripherals required for pinmux configuration. List will + * grow with support for more devices getting added. + * Numbering based on interrupt table. + * + */ +enum periph_id { + UART_GPIOC_30_31 = 0, + UART_GPIOB_16_17, + ETH_GPIOB_10_31_C_0_4, + QSPI_CS_CLK_PAD, + PERIPH_ID_I2C0, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, + PERIPH_ID_SPI0, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SDMMC0, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC2, + PERIPH_ID_SDMMC3, + PERIPH_ID_I2S1, +}; + +enum periph_clock { + UART_CLOCK_CFG = 0, + ETH_CLOCK_CFG, + QSPI_CLOCK_CFG, +}; + +#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h b/roms/u-boot/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h new file mode 100644 index 000000000..8cb8a8a61 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014, STMicroelectronics - All Rights Reserved + * Author(s): Vikas Manocha, for STMicroelectronics. + */ + +#ifndef _STV0991_WD_RST_H +#define _STV0991_WD_RST_H +#include + +struct stv0991_wd_ru { + u32 wdru_config; + u32 wdru_ctrl1; + u32 wdru_ctrl2; + u32 wdru_tim; + u32 wdru_count; + u32 wdru_stat; + u32 wdru_wrlock; +}; + +struct stv0991_wd_ru *const stv0991_wd_ru_ptr = \ + (struct stv0991_wd_ru *)WDRU_BASE_ADDR; + +/* Watchdog control register */ +#define WDRU_RST_SYS 0x1 + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/boot0.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/boot0.h new file mode 100644 index 000000000..e8e8e38f0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/boot0.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the Allwinner A64 (sun50i) CPU + */ + +#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD) +/* reserve space for BOOT0 header information */ + b reset + .space 1532 +#elif defined(CONFIG_ARM_BOOT_HOOK_RMR) +/* + * Switch into AArch64 if needed. + * Refer to arch/arm/mach-sunxi/rmr_switch.S for the original source. + */ + tst x0, x0 // this is "b #0x84" in ARM + b reset + .space 0x7c + + .word 0xe28f0058 // add r0, pc, #88 + .word 0xe59f1054 // ldr r1, [pc, #84] + .word 0xe0800001 // add r0, r0, r1 + .word 0xe580d000 // str sp, [r0] + .word 0xe580e004 // str lr, [r0, #4] + .word 0xe10fe000 // mrs lr, CPSR + .word 0xe580e008 // str lr, [r0, #8] + .word 0xee11ef10 // mrc 15, 0, lr, cr1, cr0, {0} + .word 0xe580e00c // str lr, [r0, #12] + .word 0xee1cef10 // mrc 15, 0, lr, cr12, cr0, {0} + .word 0xe580e010 // str lr, [r0, #16] + + .word 0xe59f1024 // ldr r1, [pc, #36] ; 0x170000a0 + .word 0xe59f0024 // ldr r0, [pc, #36] ; CONFIG_*_TEXT_BASE + .word 0xe5810000 // str r0, [r1] + .word 0xf57ff04f // dsb sy + .word 0xf57ff06f // isb sy + .word 0xee1c0f50 // mrc 15, 0, r0, cr12, cr0, {2} ; RMR + .word 0xe3800003 // orr r0, r0, #3 + .word 0xee0c0f50 // mcr 15, 0, r0, cr12, cr0, {2} ; RMR + .word 0xf57ff06f // isb sy + .word 0xe320f003 // wfi + .word 0xeafffffd // b @wfi +#ifndef CONFIG_SUN50I_GEN_H6 + .word 0x017000a0 // writeable RVBAR mapping address +#else + .word 0x09010040 // writeable RVBAR mapping address +#endif +#ifdef CONFIG_SPL_BUILD + .word CONFIG_SPL_TEXT_BASE +#else + .word CONFIG_SYS_TEXT_BASE +#endif + .word fel_stash - . +#else +/* normal execution */ + b reset +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/ccu.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/ccu.h new file mode 100644 index 000000000..cac5c5faf --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/ccu.h @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Amarula Solutions. + * Author: Jagan Teki + */ + +#ifndef _ASM_ARCH_CCU_H +#define _ASM_ARCH_CCU_H + +#ifndef __ASSEMBLY__ +#include +#endif + +/** + * enum ccu_flags - ccu clock/reset flags + * + * @CCU_CLK_F_IS_VALID: is given clock gate is valid? + * @CCU_RST_F_IS_VALID: is given reset control is valid? + */ +enum ccu_flags { + CCU_CLK_F_IS_VALID = BIT(0), + CCU_RST_F_IS_VALID = BIT(1), +}; + +/** + * struct ccu_clk_gate - ccu clock gate + * @off: gate offset + * @bit: gate bit + * @flags: ccu clock gate flags + */ +struct ccu_clk_gate { + u16 off; + u32 bit; + enum ccu_flags flags; +}; + +#define GATE(_off, _bit) { \ + .off = _off, \ + .bit = _bit, \ + .flags = CCU_CLK_F_IS_VALID, \ +} + +/** + * struct ccu_reset - ccu reset + * @off: reset offset + * @bit: reset bit + * @flags: ccu reset control flags + */ +struct ccu_reset { + u16 off; + u32 bit; + enum ccu_flags flags; +}; + +#define RESET(_off, _bit) { \ + .off = _off, \ + .bit = _bit, \ + .flags = CCU_RST_F_IS_VALID, \ +} + +/** + * struct ccu_desc - clock control unit descriptor + * + * @gates: clock gates + * @resets: reset unit + */ +struct ccu_desc { + const struct ccu_clk_gate *gates; + const struct ccu_reset *resets; +}; + +/** + * struct ccu_priv - sunxi clock control unit + * + * @base: base address + * @desc: ccu descriptor + */ +struct ccu_priv { + void *base; + const struct ccu_desc *desc; +}; + +/** + * sunxi_clk_probe - common sunxi clock probe + * @dev: clock device + */ +int sunxi_clk_probe(struct udevice *dev); + +extern struct clk_ops sunxi_clk_ops; + +/** + * sunxi_reset_bind() - reset binding + * + * @dev: reset device + * @count: reset count + * @return 0 success, or error value + */ +int sunxi_reset_bind(struct udevice *dev, ulong count); + +#endif /* _ASM_ARCH_CCU_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/clock.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/clock.h new file mode 100644 index 000000000..cbbe5c7a1 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/clock.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + */ + +#ifndef _SUNXI_CLOCK_H +#define _SUNXI_CLOCK_H + +#include + +#define CLK_GATE_OPEN 0x1 +#define CLK_GATE_CLOSE 0x0 + +/* clock control module regs definition */ +#if defined(CONFIG_MACH_SUN8I_A83T) +#include +#elif defined(CONFIG_SUN50I_GEN_H6) +#include +#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \ + defined(CONFIG_MACH_SUN50I) +#include +#elif defined(CONFIG_MACH_SUN9I) +#include +#else +#include +#endif + +#ifndef __ASSEMBLY__ +int clock_init(void); +int clock_twi_onoff(int port, int state); +void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz); +void clock_init_safe(void); +void clock_init_sec(void); +void clock_init_uart(void); +#endif + +#endif /* _SUNXI_CLOCK_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/clock_sun4i.h new file mode 100644 index 000000000..2cec91cb2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -0,0 +1,362 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * sun4i, sun5i and sun7i clock register definitions + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + */ + +#ifndef _SUNXI_CLOCK_SUN4I_H +#define _SUNXI_CLOCK_SUN4I_H + +struct sunxi_ccm_reg { + u32 pll1_cfg; /* 0x00 pll1 control */ + u32 pll1_tun; /* 0x04 pll1 tuning */ + u32 pll2_cfg; /* 0x08 pll2 control */ + u32 pll2_tun; /* 0x0c pll2 tuning */ + u32 pll3_cfg; /* 0x10 pll3 control */ + u8 res0[0x4]; + u32 pll4_cfg; /* 0x18 pll4 control */ + u8 res1[0x4]; + u32 pll5_cfg; /* 0x20 pll5 control */ + u32 pll5_tun; /* 0x24 pll5 tuning */ + u32 pll6_cfg; /* 0x28 pll6 control */ + u32 pll6_tun; /* 0x2c pll6 tuning */ + u32 pll7_cfg; /* 0x30 pll7 control */ + u32 pll1_tun2; /* 0x34 pll5 tuning2 */ + u8 res2[0x4]; + u32 pll5_tun2; /* 0x3c pll5 tuning2 */ + u8 res3[0xc]; + u32 pll_lock_dbg; /* 0x4c pll lock time debug */ + u32 osc24m_cfg; /* 0x50 osc24m control */ + u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */ + u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */ + u32 axi_gate; /* 0x5c axi module clock gating */ + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ + u32 apb0_gate; /* 0x68 apb0 module clock gating */ + u32 apb1_gate; /* 0x6c apb1 module clock gating */ + u8 res4[0x10]; + u32 nand0_clk_cfg; /* 0x80 nand sub clock control */ + u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */ + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ + u32 ts_clk_cfg; /* 0x98 transport stream clock control */ + u32 ss_clk_cfg; /* 0x9c */ + u32 spi0_clk_cfg; /* 0xa0 */ + u32 spi1_clk_cfg; /* 0xa4 */ + u32 spi2_clk_cfg; /* 0xa8 */ + u32 pata_clk_cfg; /* 0xac */ + u32 ir0_clk_cfg; /* 0xb0 */ + u32 ir1_clk_cfg; /* 0xb4 */ + u32 iis_clk_cfg; /* 0xb8 */ + u32 ac97_clk_cfg; /* 0xbc */ + u32 spdif_clk_cfg; /* 0xc0 */ + u32 keypad_clk_cfg; /* 0xc4 */ + u32 sata_clk_cfg; /* 0xc8 */ + u32 usb_clk_cfg; /* 0xcc */ + u32 gps_clk_cfg; /* 0xd0 */ + u32 spi3_clk_cfg; /* 0xd4 */ + u8 res5[0x28]; + u32 dram_clk_gate; /* 0x100 */ + u32 be0_clk_cfg; /* 0x104 */ + u32 be1_clk_cfg; /* 0x108 */ + u32 fe0_clk_cfg; /* 0x10c */ + u32 fe1_clk_cfg; /* 0x110 */ + u32 mp_clk_cfg; /* 0x114 */ + u32 lcd0_ch0_clk_cfg; /* 0x118 */ + u32 lcd1_ch0_clk_cfg; /* 0x11c */ + u32 csi_isp_clk_cfg; /* 0x120 */ + u8 res6[0x4]; + u32 tvd_clk_reg; /* 0x128 */ + u32 lcd0_ch1_clk_cfg; /* 0x12c */ + u32 lcd1_ch1_clk_cfg; /* 0x130 */ + u32 csi0_clk_cfg; /* 0x134 */ + u32 csi1_clk_cfg; /* 0x138 */ + u32 ve_clk_cfg; /* 0x13c */ + u32 audio_codec_clk_cfg; /* 0x140 */ + u32 avs_clk_cfg; /* 0x144 */ + u32 ace_clk_cfg; /* 0x148 */ + u32 lvds_clk_cfg; /* 0x14c */ + u32 hdmi_clk_cfg; /* 0x150 */ + u32 mali_clk_cfg; /* 0x154 */ + u8 res7[0x4]; + u32 mbus_clk_cfg; /* 0x15c */ + u8 res8[0x4]; + u32 gmac_clk_cfg; /* 0x164 */ +}; + +/* apb1 bit field */ +#define APB1_CLK_SRC_OSC24M (0x0 << 24) +#define APB1_CLK_SRC_PLL6 (0x1 << 24) +#define APB1_CLK_SRC_LOSC (0x2 << 24) +#define APB1_CLK_SRC_MASK (0x3 << 24) +#define APB1_CLK_RATE_N_1 (0x0 << 16) +#define APB1_CLK_RATE_N_2 (0x1 << 16) +#define APB1_CLK_RATE_N_4 (0x2 << 16) +#define APB1_CLK_RATE_N_8 (0x3 << 16) +#define APB1_CLK_RATE_N_MASK (3 << 16) +#define APB1_CLK_RATE_M(m) (((m)-1) << 0) +#define APB1_CLK_RATE_M_MASK (0x1f << 0) + +/* apb1 gate field */ +#define APB1_GATE_UART_SHIFT (16) +#define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT) +#define APB1_GATE_TWI_SHIFT (0) +#define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT) + +/* clock divide */ +#define AXI_DIV_SHIFT (0) +#define AXI_DIV_1 0 +#define AXI_DIV_2 1 +#define AXI_DIV_3 2 +#define AXI_DIV_4 3 +#define AHB_DIV_SHIFT (4) +#define AHB_DIV_1 0 +#define AHB_DIV_2 1 +#define AHB_DIV_4 2 +#define AHB_DIV_8 3 +#define APB0_DIV_SHIFT (8) +#define APB0_DIV_1 0 +#define APB0_DIV_2 1 +#define APB0_DIV_4 2 +#define APB0_DIV_8 3 +#define CPU_CLK_SRC_SHIFT (16) +#define CPU_CLK_SRC_OSC24M 1 +#define CPU_CLK_SRC_PLL1 2 + +#define CCM_PLL1_CFG_ENABLE_SHIFT 31 +#define CCM_PLL1_CFG_VCO_RST_SHIFT 30 +#define CCM_PLL1_CFG_VCO_BIAS_SHIFT 26 +#define CCM_PLL1_CFG_PLL4_EXCH_SHIFT 25 +#define CCM_PLL1_CFG_BIAS_CUR_SHIFT 20 +#define CCM_PLL1_CFG_DIVP_SHIFT 16 +#define CCM_PLL1_CFG_LCK_TMR_SHIFT 13 +#define CCM_PLL1_CFG_FACTOR_N_SHIFT 8 +#define CCM_PLL1_CFG_FACTOR_K_SHIFT 4 +#define CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT 3 +#define CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT 2 +#define CCM_PLL1_CFG_FACTOR_M_SHIFT 0 + +#define PLL1_CFG_DEFAULT 0xa1005000 + +#if defined CONFIG_OLD_SUNXI_KERNEL_COMPAT && defined CONFIG_MACH_SUN5I +/* + * Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz, + * halving the mbus frequency, so set it to 300 MHz ourselves and base the + * mbus divider on that. + */ +#define PLL6_CFG_DEFAULT 0xa1009900 +#else +#define PLL6_CFG_DEFAULT 0xa1009911 +#endif + +/* nand clock */ +#define NAND_CLK_SRC_OSC24 0 +#define NAND_CLK_DIV_N 0 +#define NAND_CLK_DIV_M 0 + +/* gps clock */ +#define GPS_SCLK_GATING_OFF 0 +#define GPS_RESET 0 + +/* ahb clock gate bit offset */ +#define AHB_GATE_OFFSET_GPS 26 +#define AHB_GATE_OFFSET_SATA 25 +#define AHB_GATE_OFFSET_PATA 24 +#define AHB_GATE_OFFSET_SPI3 23 +#define AHB_GATE_OFFSET_SPI2 22 +#define AHB_GATE_OFFSET_SPI1 21 +#define AHB_GATE_OFFSET_SPI0 20 +#define AHB_GATE_OFFSET_TS0 18 +#define AHB_GATE_OFFSET_EMAC 17 +#define AHB_GATE_OFFSET_ACE 16 +#define AHB_GATE_OFFSET_DLL 15 +#define AHB_GATE_OFFSET_SDRAM 14 +#define AHB_GATE_OFFSET_NAND0 13 +#define AHB_GATE_OFFSET_MS 12 +#define AHB_GATE_OFFSET_MMC3 11 +#define AHB_GATE_OFFSET_MMC2 10 +#define AHB_GATE_OFFSET_MMC1 9 +#define AHB_GATE_OFFSET_MMC0 8 +#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) +#define AHB_GATE_OFFSET_BIST 7 +#define AHB_GATE_OFFSET_DMA 6 +#define AHB_GATE_OFFSET_SS 5 +#define AHB_GATE_OFFSET_USB_OHCI1 4 +#define AHB_GATE_OFFSET_USB_EHCI1 3 +#define AHB_GATE_OFFSET_USB_OHCI0 2 +#define AHB_GATE_OFFSET_USB_EHCI0 1 +#define AHB_GATE_OFFSET_USB0 0 + +/* ahb clock gate bit offset (second register) */ +#define AHB_GATE_OFFSET_GMAC 17 +#define AHB_GATE_OFFSET_DE_FE0 14 +#define AHB_GATE_OFFSET_DE_BE0 12 +#define AHB_GATE_OFFSET_HDMI 11 +#define AHB_GATE_OFFSET_LCD1 5 +#define AHB_GATE_OFFSET_LCD0 4 +#define AHB_GATE_OFFSET_TVE1 3 +#define AHB_GATE_OFFSET_TVE0 2 + +#define CCM_AHB_GATE_GPS (0x1 << 26) +#define CCM_AHB_GATE_SDRAM (0x1 << 14) +#define CCM_AHB_GATE_DLL (0x1 << 15) +#define CCM_AHB_GATE_ACE (0x1 << 16) + +#define CCM_PLL3_CTRL_M_SHIFT 0 +#define CCM_PLL3_CTRL_M_MASK (0x7f << CCM_PLL3_CTRL_M_SHIFT) +#define CCM_PLL3_CTRL_M(n) (((n) & 0x7f) << 0) +#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 15) +#define CCM_PLL3_CTRL_EN (0x1 << 31) + +#define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0) +#define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3) +#define CCM_PLL5_CTRL_M_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_M1(n) (((n) & 0x3) << 2) +#define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3) +#define CCM_PLL5_CTRL_M1_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4) +#define CCM_PLL5_CTRL_K_SHIFT 4 +#define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3) +#define CCM_PLL5_CTRL_K_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_LDO (0x1 << 7) +#define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8) +#define CCM_PLL5_CTRL_N_SHIFT 8 +#define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f) +#define CCM_PLL5_CTRL_N_X(n) (n) +#define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16) +#define CCM_PLL5_CTRL_P_SHIFT 16 +#define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3) +#define CCM_PLL5_CTRL_P_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_BW (0x1 << 18) +#define CCM_PLL5_CTRL_VCO_GAIN (0x1 << 19) +#define CCM_PLL5_CTRL_BIAS(n) (((n) & 0x1f) << 20) +#define CCM_PLL5_CTRL_BIAS_MASK CCM_PLL5_CTRL_BIAS(0x1f) +#define CCM_PLL5_CTRL_BIAS_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_VCO_BIAS (0x1 << 25) +#define CCM_PLL5_CTRL_DDR_CLK (0x1 << 29) +#define CCM_PLL5_CTRL_BYPASS (0x1 << 30) +#define CCM_PLL5_CTRL_EN (0x1 << 31) + +#define CCM_PLL6_CTRL_EN 31 +#define CCM_PLL6_CTRL_BYPASS_EN 30 +#define CCM_PLL6_CTRL_SATA_EN_SHIFT 14 +#define CCM_PLL6_CTRL_N_SHIFT 8 +#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) +#define CCM_PLL6_CTRL_K_SHIFT 4 +#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) + +#define CCM_GPS_CTRL_RESET (0x1 << 0) +#define CCM_GPS_CTRL_GATE (0x1 << 1) + +#define CCM_DRAM_CTRL_DCLK_OUT (0x1 << 15) + +#define CCM_MBUS_CTRL_M(n) (((n) & 0xf) << 0) +#define CCM_MBUS_CTRL_M_MASK CCM_MBUS_CTRL_M(0xf) +#define CCM_MBUS_CTRL_M_X(n) ((n) - 1) +#define CCM_MBUS_CTRL_N(n) (((n) & 0xf) << 16) +#define CCM_MBUS_CTRL_N_MASK CCM_MBUS_CTRL_N(0xf) +#define CCM_MBUS_CTRL_N_X(n) (((n) >> 3) ? 3 : (((n) >> 2) ? 2 : (((n) >> 1) ? 1 : 0))) +#define CCM_MBUS_CTRL_CLK_SRC(n) (((n) & 0x3) << 24) +#define CCM_MBUS_CTRL_CLK_SRC_MASK CCM_MBUS_CTRL_CLK_SRC(0x3) +#define CCM_MBUS_CTRL_CLK_SRC_HOSC 0x0 +#define CCM_MBUS_CTRL_CLK_SRC_PLL6 0x1 +#define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2 +#define CCM_MBUS_CTRL_GATE (0x1 << 31) + +#define CCM_NAND_CTRL_M(x) ((x) - 1) +#define CCM_NAND_CTRL_N(x) ((x) << 16) +#define CCM_NAND_CTRL_OSCM24 (0x0 << 24) +#define CCM_NAND_CTRL_PLL6 (0x1 << 24) +#define CCM_NAND_CTRL_PLL5 (0x2 << 24) +#define CCM_NAND_CTRL_ENABLE (0x1 << 31) + +#define CCM_MMC_CTRL_M(x) ((x) - 1) +#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) +#define CCM_MMC_CTRL_N(x) ((x) << 16) +#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) +#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) +#define CCM_MMC_CTRL_PLL6 (0x1 << 24) +#define CCM_MMC_CTRL_PLL5 (0x2 << 24) +#define CCM_MMC_CTRL_ENABLE (0x1 << 31) + +#define CCM_DRAM_GATE_OFFSET_DE_FE1 24 /* Note the order of FE1 and */ +#define CCM_DRAM_GATE_OFFSET_DE_FE0 25 /* FE0 is swapped ! */ +#define CCM_DRAM_GATE_OFFSET_DE_BE0 26 +#define CCM_DRAM_GATE_OFFSET_DE_BE1 27 + +#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24) +#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24) +#define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24) +#define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24) +#define CCM_LCD_CH0_CTRL_MIPI_PLL 0 /* No mipi pll on sun4i/5i/7i */ +#ifdef CONFIG_MACH_SUN5I +#define CCM_LCD_CH0_CTRL_TVE_RST (0x1 << 29) +#else +#define CCM_LCD_CH0_CTRL_TVE_RST 0 /* No separate tve-rst on sun4i/7i */ +#endif +#define CCM_LCD_CH0_CTRL_RST (0x1 << 30) +#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31) + +#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_LCD_CH1_CTRL_HALF_SCLK1 (1 << 11) +#define CCM_LCD_CH1_CTRL_PLL3 (0 << 24) +#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24) +#define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24) +#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24) +/* Enable / disable both ch1 sclk1 and sclk2 at the same time */ +#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31 | 0x1 << 15) + +#define CCM_LVDS_CTRL_RST (1 << 0) + +#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_HDMI_CTRL_PLL_MASK (3 << 24) +#define CCM_HDMI_CTRL_PLL3 (0 << 24) +#define CCM_HDMI_CTRL_PLL7 (1 << 24) +#define CCM_HDMI_CTRL_PLL3_2X (2 << 24) +#define CCM_HDMI_CTRL_PLL7_2X (3 << 24) +/* No separate ddc gate on sun4i, sun5i and sun7i */ +#define CCM_HDMI_CTRL_DDC_GATE 0 +#define CCM_HDMI_CTRL_GATE (0x1 << 31) + +#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 +#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 +#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 +#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) +#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) +#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5) +#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) + +#define CCM_USB_CTRL_PHY0_RST (0x1 << 0) +#define CCM_USB_CTRL_PHY1_RST (0x1 << 1) +#define CCM_USB_CTRL_PHY2_RST (0x1 << 2) +#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 6) +#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 7) +#define CCM_USB_CTRL_PHYGATE (0x1 << 8) +/* These 3 are sun6i only, define them as 0 on sun4i */ +#define CCM_USB_CTRL_PHY0_CLK 0 +#define CCM_USB_CTRL_PHY1_CLK 0 +#define CCM_USB_CTRL_PHY2_CLK 0 + +/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */ +#define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_DE_CTRL_PLL_MASK (3 << 24) +#define CCM_DE_CTRL_PLL3 (0 << 24) +#define CCM_DE_CTRL_PLL7 (1 << 24) +#define CCM_DE_CTRL_PLL5P (2 << 24) +#define CCM_DE_CTRL_RST (1 << 30) +#define CCM_DE_CTRL_GATE (1 << 31) + +#ifndef __ASSEMBLY__ +void clock_set_pll1(unsigned int hz); +void clock_set_pll3(unsigned int hz); +unsigned int clock_get_pll3(void); +unsigned int clock_get_pll5p(void); +unsigned int clock_get_pll6(void); +#endif + +#endif /* _SUNXI_CLOCK_SUN4I_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h new file mode 100644 index 000000000..62abfc4ef --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h @@ -0,0 +1,341 @@ +/* + * Allwinner H6 clock register definitions + * + * (C) Copyright 2017 Icenowy Zheng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CLOCK_SUN50I_H6_H +#define _SUNXI_CLOCK_SUN50I_H6_H + +#ifndef __ASSEMBLY__ +#include +#endif + +struct sunxi_ccm_reg { + u32 pll1_cfg; /* 0x000 pll1 (cpux) control */ + u8 reserved_0x004[12]; + u32 pll5_cfg; /* 0x010 pll5 (ddr) control */ + u8 reserved_0x014[12]; + u32 pll6_cfg; /* 0x020 pll6 (periph0) control */ + u8 reserved_0x020[4]; + u32 pll_periph1_cfg; /* 0x028 pll periph1 control */ + u8 reserved_0x028[4]; + u32 pll7_cfg; /* 0x030 pll7 (gpu) control */ + u8 reserved_0x034[12]; + u32 pll3_cfg; /* 0x040 pll3 (video0) control */ + u8 reserved_0x044[4]; + u32 pll_video1_cfg; /* 0x048 pll video1 control */ + u8 reserved_0x04c[12]; + u32 pll4_cfg; /* 0x058 pll4 (ve) control */ + u8 reserved_0x05c[4]; + u32 pll10_cfg; /* 0x060 pll10 (de) control */ + u8 reserved_0x064[12]; + u32 pll9_cfg; /* 0x070 pll9 (hsic) control */ + u8 reserved_0x074[4]; + u32 pll2_cfg; /* 0x078 pll2 (audio) control */ + u8 reserved_0x07c[148]; + u32 pll5_pat; /* 0x110 pll5 (ddr) pattern */ + u8 reserved_0x114[20]; + u32 pll_periph1_pat0; /* 0x128 pll periph1 pattern0 */ + u32 pll_periph1_pat1; /* 0x12c pll periph1 pattern1 */ + u32 pll7_pat0; /* 0x130 pll7 (gpu) pattern0 */ + u32 pll7_pat1; /* 0x134 pll7 (gpu) pattern1 */ + u8 reserved_0x138[8]; + u32 pll3_pat0; /* 0x140 pll3 (video0) pattern0 */ + u32 pll3_pat1; /* 0x144 pll3 (video0) pattern1 */ + u32 pll_video1_pat0; /* 0x148 pll video1 pattern0 */ + u32 pll_video1_pat1; /* 0x14c pll video1 pattern1 */ + u8 reserved_0x150[8]; + u32 pll4_pat0; /* 0x158 pll4 (ve) pattern0 */ + u32 pll4_pat1; /* 0x15c pll4 (ve) pattern1 */ + u32 pll10_pat0; /* 0x160 pll10 (de) pattern0 */ + u32 pll10_pat1; /* 0x164 pll10 (de) pattern1 */ + u8 reserved_0x168[8]; + u32 pll9_pat0; /* 0x170 pll9 (hsic) pattern0 */ + u32 pll9_pat1; /* 0x174 pll9 (hsic) pattern1 */ + u32 pll2_pat0; /* 0x178 pll2 (audio) pattern0 */ + u32 pll2_pat1; /* 0x17c pll2 (audio) pattern1 */ + u8 reserved_0x180[384]; + u32 pll1_bias; /* 0x300 pll1 (cpux) bias */ + u8 reserved_0x304[12]; + u32 pll5_bias; /* 0x310 pll5 (ddr) bias */ + u8 reserved_0x314[12]; + u32 pll6_bias; /* 0x320 pll6 (periph0) bias */ + u8 reserved_0x324[4]; + u32 pll_periph1_bias; /* 0x328 pll periph1 bias */ + u8 reserved_0x32c[4]; + u32 pll7_bias; /* 0x330 pll7 (gpu) bias */ + u8 reserved_0x334[12]; + u32 pll3_bias; /* 0x340 pll3 (video0) bias */ + u8 reserved_0x344[4]; + u32 pll_video1_bias; /* 0x348 pll video1 bias */ + u8 reserved_0x34c[12]; + u32 pll4_bias; /* 0x358 pll4 (ve) bias */ + u8 reserved_0x35c[4]; + u32 pll10_bias; /* 0x360 pll10 (de) bias */ + u8 reserved_0x364[12]; + u32 pll9_bias; /* 0x370 pll9 (hsic) bias */ + u8 reserved_0x374[4]; + u32 pll2_bias; /* 0x378 pll2 (audio) bias */ + u8 reserved_0x37c[132]; + u32 pll1_tun; /* 0x400 pll1 (cpux) tunning */ + u8 reserved_0x404[252]; + u32 cpu_axi_cfg; /* 0x500 CPUX/AXI clock control*/ + u8 reserved_0x504[12]; + u32 psi_ahb1_ahb2_cfg; /* 0x510 PSI/AHB1/AHB2 clock control */ + u8 reserved_0x514[8]; + u32 ahb3_cfg; /* 0x51c AHB3 clock control */ + u32 apb1_cfg; /* 0x520 APB1 clock control */ + u32 apb2_cfg; /* 0x524 APB2 clock control */ + u8 reserved_0x528[24]; + u32 mbus_cfg; /* 0x540 MBUS clock control */ + u8 reserved_0x544[188]; + u32 de_clk_cfg; /* 0x600 DE clock control */ + u8 reserved_0x604[8]; + u32 de_gate_reset; /* 0x60c DE gate/reset control */ + u8 reserved_0x610[16]; + u32 di_clk_cfg; /* 0x620 DI clock control */ + u8 reserved_0x024[8]; + u32 di_gate_reset; /* 0x62c DI gate/reset control */ + u8 reserved_0x630[64]; + u32 gpu_clk_cfg; /* 0x670 GPU clock control */ + u8 reserved_0x674[8]; + u32 gpu_gate_reset; /* 0x67c GPU gate/reset control */ + u32 ce_clk_cfg; /* 0x680 CE clock control */ + u8 reserved_0x684[8]; + u32 ce_gate_reset; /* 0x68c CE gate/reset control */ + u32 ve_clk_cfg; /* 0x690 VE clock control */ + u8 reserved_0x694[8]; + u32 ve_gate_reset; /* 0x69c VE gate/reset control */ + u8 reserved_0x6a0[16]; + u32 emce_clk_cfg; /* 0x6b0 EMCE clock control */ + u8 reserved_0x6b4[8]; + u32 emce_gate_reset; /* 0x6bc EMCE gate/reset control */ + u32 vp9_clk_cfg; /* 0x6c0 VP9 clock control */ + u8 reserved_0x6c4[8]; + u32 vp9_gate_reset; /* 0x6cc VP9 gate/reset control */ + u8 reserved_0x6d0[60]; + u32 dma_gate_reset; /* 0x70c DMA gate/reset control */ + u8 reserved_0x710[12]; + u32 msgbox_gate_reset; /* 0x71c Message Box gate/reset control */ + u8 reserved_0x720[12]; + u32 spinlock_gate_reset;/* 0x72c Spinlock gate/reset control */ + u8 reserved_0x730[12]; + u32 hstimer_gate_reset; /* 0x73c HS Timer gate/reset control */ + u32 avs_gate_reset; /* 0x740 AVS gate/reset control */ + u8 reserved_0x744[72]; + u32 dbgsys_gate_reset; /* 0x78c Debugging system gate/reset control */ + u8 reserved_0x790[12]; + u32 psi_gate_reset; /* 0x79c PSI gate/reset control */ + u8 reserved_0x7a0[12]; + u32 pwm_gate_reset; /* 0x7ac PWM gate/reset control */ + u8 reserved_0x7b0[12]; + u32 iommu_gate_reset; /* 0x7bc IOMMU gate/reset control */ + u8 reserved_0x7c0[64]; + u32 dram_clk_cfg; /* 0x800 DRAM clock control */ + u32 mbus_gate; /* 0x804 MBUS gate control */ + u8 reserved_0x808[4]; + u32 dram_gate_reset; /* 0x80c DRAM gate/reset control */ + u32 nand0_clk_cfg; /* 0x810 NAND0 clock control */ + u32 nand1_clk_cfg; /* 0x814 NAND1 clock control */ + u8 reserved_0x818[20]; + u32 nand_gate_reset; /* 0x82c NAND gate/reset control */ + u32 sd0_clk_cfg; /* 0x830 MMC0 clock control */ + u32 sd1_clk_cfg; /* 0x834 MMC1 clock control */ + u32 sd2_clk_cfg; /* 0x838 MMC2 clock control */ + u8 reserved_0x83c[16]; + u32 sd_gate_reset; /* 0x84c MMC gate/reset control */ + u8 reserved_0x850[188]; + u32 uart_gate_reset; /* 0x90c UART gate/reset control */ + u8 reserved_0x910[12]; + u32 twi_gate_reset; /* 0x91c I2C gate/reset control */ + u8 reserved_0x920[28]; + u32 scr_gate_reset; /* 0x93c SCR gate/reset control */ + u32 spi0_clk_cfg; /* 0x940 SPI0 clock control */ + u32 spi1_clk_cfg; /* 0x944 SPI1 clock control */ + u8 reserved_0x948[36]; + u32 spi_gate_reset; /* 0x96c SPI gate/reset control */ + u8 reserved_0x970[12]; + u32 emac_gate_reset; /* 0x97c EMAC gate/reset control */ + u8 reserved_0x980[48]; + u32 ts_clk_cfg; /* 0x9b0 TS clock control */ + u8 reserved_0x9b4[8]; + u32 ts_gate_reset; /* 0x9bc TS gate/reset control */ + u32 irtx_clk_cfg; /* 0x9c0 IR TX clock control */ + u8 reserved_0x9c4[8]; + u32 irtx_gate_reset; /* 0x9cc IR TX gate/reset control */ + u8 reserved_0x9d0[44]; + u32 ths_gate_reset; /* 0x9fc THS gate/reset control */ + u8 reserved_0xa00[12]; + u32 i2s3_clk_cfg; /* 0xa0c I2S3 clock control */ + u32 i2s0_clk_cfg; /* 0xa10 I2S0 clock control */ + u32 i2s1_clk_cfg; /* 0xa14 I2S1 clock control */ + u32 i2s2_clk_cfg; /* 0xa18 I2S2 clock control */ + u32 i2s_gate_reset; /* 0xa1c I2S gate/reset control */ + u32 spdif_clk_cfg; /* 0xa20 SPDIF clock control */ + u8 reserved_0xa24[8]; + u32 spdif_gate_reset; /* 0xa2c SPDIF gate/reset control */ + u8 reserved_0xa30[16]; + u32 dmic_clk_cfg; /* 0xa40 DMIC clock control */ + u8 reserved_0xa44[8]; + u32 dmic_gate_reset; /* 0xa4c DMIC gate/reset control */ + u8 reserved_0xa50[16]; + u32 ahub_clk_cfg; /* 0xa60 Audio HUB clock control */ + u8 reserved_0xa64[8]; + u32 ahub_gate_reset; /* 0xa6c Audio HUB gate/reset control */ + u32 usb0_clk_cfg; /* 0xa70 USB0(OTG) clock control */ + u32 usb1_clk_cfg; /* 0xa74 USB1(XHCI) clock control */ + u8 reserved_0xa78[4]; + u32 usb3_clk_cfg; /* 0xa78 USB3 clock control */ + u8 reserved_0xa80[12]; + u32 usb_gate_reset; /* 0xa8c USB gate/reset control */ + u8 reserved_0xa90[32]; + u32 pcie_ref_clk_cfg; /* 0xab0 PCIE REF clock control */ + u32 pcie_axi_clk_cfg; /* 0xab4 PCIE AXI clock control */ + u32 pcie_aux_clk_cfg; /* 0xab8 PCIE AUX clock control */ + u32 pcie_gate_reset; /* 0xabc PCIE gate/reset control */ + u8 reserved_0xac0[64]; + u32 hdmi_clk_cfg; /* 0xb00 HDMI clock control */ + u32 hdmi_slow_clk_cfg; /* 0xb04 HDMI slow clock control */ + u8 reserved_0xb08[8]; + u32 hdmi_cec_clk_cfg; /* 0xb10 HDMI CEC clock control */ + u8 reserved_0xb14[8]; + u32 hdmi_gate_reset; /* 0xb1c HDMI gate/reset control */ + u8 reserved_0xb20[60]; + u32 tcon_top_gate_reset;/* 0xb5c TCON TOP gate/reset control */ + u32 tcon_lcd0_clk_cfg; /* 0xb60 TCON LCD0 clock control */ + u8 reserved_0xb64[24]; + u32 tcon_lcd_gate_reset;/* 0xb7c TCON LCD gate/reset control */ + u32 tcon_tv0_clk_cfg; /* 0xb80 TCON TV0 clock control */ + u8 reserved_0xb84[24]; + u32 tcon_tv_gate_reset; /* 0xb9c TCON TV gate/reset control */ + u8 reserved_0xba0[96]; + u32 csi_misc_clk_cfg; /* 0xc00 CSI MISC clock control */ + u32 csi_top_clk_cfg; /* 0xc04 CSI TOP clock control */ + u32 csi_mclk_cfg; /* 0xc08 CSI Master clock control */ + u8 reserved_0xc0c[32]; + u32 csi_gate_reset; /* 0xc2c CSI gate/reset control */ + u8 reserved_0xc30[16]; + u32 hdcp_clk_cfg; /* 0xc40 HDCP clock control */ + u8 reserved_0xc44[8]; + u32 hdcp_gate_reset; /* 0xc4c HDCP gate/reset control */ + u8 reserved_0xc50[688]; + u32 ccu_sec_switch; /* 0xf00 CCU security switch */ + u32 pll_lock_dbg_ctrl; /* 0xf04 PLL lock debugging control */ +}; + +/* pll1 bit field */ +#define CCM_PLL1_CTRL_EN BIT(31) +#define CCM_PLL1_LOCK_EN BIT(29) +#define CCM_PLL1_LOCK BIT(28) +#define CCM_PLL1_OUT_EN BIT(27) +#define CCM_PLL1_CLOCK_TIME_2 (2 << 24) +#define CCM_PLL1_CTRL_P(p) ((p) << 16) +#define CCM_PLL1_CTRL_N(n) ((n) << 8) + +/* pll5 bit field */ +#define CCM_PLL5_CTRL_EN BIT(31) +#define CCM_PLL5_LOCK_EN BIT(29) +#define CCM_PLL5_LOCK BIT(28) +#define CCM_PLL5_OUT_EN BIT(27) +#define CCM_PLL5_CTRL_N(n) ((n) << 8) +#define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0) +#define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1) + +/* pll6 bit field */ +#define CCM_PLL6_CTRL_EN BIT(31) +#define CCM_PLL6_LOCK_EN BIT(29) +#define CCM_PLL6_LOCK BIT(28) +#define CCM_PLL6_CTRL_N_SHIFT 8 +#define CCM_PLL6_CTRL_N_MASK (0xff << CCM_PLL6_CTRL_N_SHIFT) +#define CCM_PLL6_CTRL_DIV1_SHIFT 0 +#define CCM_PLL6_CTRL_DIV1_MASK (0x1 << CCM_PLL6_CTRL_DIV1_SHIFT) +#define CCM_PLL6_CTRL_DIV2_SHIFT 1 +#define CCM_PLL6_CTRL_DIV2_MASK (0x1 << CCM_PLL6_CTRL_DIV2_SHIFT) + +/* cpu_axi bit field*/ +#define CCM_CPU_AXI_MUX_MASK (0x3 << 24) +#define CCM_CPU_AXI_MUX_OSC24M (0x0 << 24) +#define CCM_CPU_AXI_MUX_PLL_CPUX (0x3 << 24) +#define CCM_CPU_AXI_APB_MASK 0x300 +#define CCM_CPU_AXI_AXI_MASK 0x3 +#define CCM_CPU_AXI_DEFAULT_FACTORS 0x301 + +#ifdef CONFIG_MACH_SUN50I_H6 +#define CCM_PLL6_DEFAULT 0xa0006300 + +/* psi_ahb1_ahb2 bit field */ +#define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000102 + +/* ahb3 bit field */ +#define CCM_AHB3_DEFAULT 0x03000002 + +/* apb1 bit field */ +#define CCM_APB1_DEFAULT 0x03000102 +#elif CONFIG_MACH_SUN50I_H616 +#define CCM_PLL6_DEFAULT 0xa8003100 + +/* psi_ahb1_ahb2 bit field */ +#define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000002 + +/* ahb3 bit field */ +#define CCM_AHB3_DEFAULT 0x03000002 + +/* apb1 bit field */ +#define CCM_APB1_DEFAULT 0x03000102 +#endif + +/* apb2 bit field */ +#define APB2_CLK_SRC_OSC24M (0x0 << 24) +#define APB2_CLK_SRC_OSC32K (0x1 << 24) +#define APB2_CLK_SRC_PSI (0x2 << 24) +#define APB2_CLK_SRC_PLL6 (0x3 << 24) +#define APB2_CLK_SRC_MASK (0x3 << 24) +#define APB2_CLK_RATE_N_1 (0x0 << 8) +#define APB2_CLK_RATE_N_2 (0x1 << 8) +#define APB2_CLK_RATE_N_4 (0x2 << 8) +#define APB2_CLK_RATE_N_8 (0x3 << 8) +#define APB2_CLK_RATE_N_MASK (3 << 8) +#define APB2_CLK_RATE_M(m) (((m)-1) << 0) +#define APB2_CLK_RATE_M_MASK (3 << 0) + +/* MBUS clock bit field */ +#define MBUS_ENABLE BIT(31) +#define MBUS_RESET BIT(30) +#define MBUS_CLK_SRC_MASK GENMASK(25, 24) +#define MBUS_CLK_SRC_OSCM24 (0 << 24) +#define MBUS_CLK_SRC_PLL6X2 (1 << 24) +#define MBUS_CLK_SRC_PLL5 (2 << 24) +#define MBUS_CLK_SRC_PLL6X4 (3 << 24) +#define MBUS_CLK_M(m) (((m)-1) << 0) + +/* Module gate/reset shift*/ +#define RESET_SHIFT (16) +#define GATE_SHIFT (0) + +/* DRAM clock bit field */ +#define DRAM_MOD_RESET BIT(30) +#define DRAM_CLK_UPDATE BIT(27) +#define DRAM_CLK_SRC_MASK GENMASK(25, 24) +#define DRAM_CLK_SRC_PLL5 (0 << 24) +#define DRAM_CLK_M(m) (((m)-1) << 0) + +/* MMC clock bit field */ +#define CCM_MMC_CTRL_M(x) ((x) - 1) +#define CCM_MMC_CTRL_N(x) ((x) << 8) +#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) +#define CCM_MMC_CTRL_PLL6X2 (0x1 << 24) +#define CCM_MMC_CTRL_PLL_PERIPH2X2 (0x2 << 24) +#define CCM_MMC_CTRL_ENABLE (0x1 << 31) +/* H6 doesn't have these delays */ +#define CCM_MMC_CTRL_OCLK_DLY(a) ((void) (a), 0) +#define CCM_MMC_CTRL_SCLK_DLY(a) ((void) (a), 0) + +#ifndef __ASSEMBLY__ +void clock_set_pll1(unsigned int hz); +unsigned int clock_get_pll6(void); +#endif + +#endif /* _SUNXI_CLOCK_SUN50I_H6_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/clock_sun6i.h new file mode 100644 index 000000000..ee387127f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -0,0 +1,533 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * sun6i clock register definitions + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + */ + +#ifndef _SUNXI_CLOCK_SUN6I_H +#define _SUNXI_CLOCK_SUN6I_H + +struct sunxi_ccm_reg { + u32 pll1_cfg; /* 0x00 pll1 control */ + u32 reserved0; + u32 pll2_cfg; /* 0x08 pll2 control */ + u32 reserved1; + u32 pll3_cfg; /* 0x10 pll3 control */ + u32 reserved2; + u32 pll4_cfg; /* 0x18 pll4 control */ + u32 reserved3; + u32 pll5_cfg; /* 0x20 pll5 control */ + u32 reserved4; + u32 pll6_cfg; /* 0x28 pll6 control */ + u32 reserved5; + u32 pll7_cfg; /* 0x30 pll7 control */ + u32 sata_pll_cfg; /* 0x34 SATA pll control (R40 only) */ + u32 pll8_cfg; /* 0x38 pll8 control */ + u32 reserved7; + u32 mipi_pll_cfg; /* 0x40 MIPI pll control */ + u32 pll9_cfg; /* 0x44 pll9 control */ + u32 pll10_cfg; /* 0x48 pll10 control */ + u32 pll11_cfg; /* 0x4c pll11 (ddr1) control (A33 only) */ + u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */ + u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */ + u32 apb2_div; /* 0x58 APB2 divide ratio */ + u32 axi_gate; /* 0x5c axi module clock gating */ + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ + u32 apb1_gate; /* 0x68 apb1 module clock gating */ + u32 apb2_gate; /* 0x6c apb2 module clock gating */ + u32 bus_gate4; /* 0x70 gate 4 module clock gating */ + u8 res3[0xc]; + u32 nand0_clk_cfg; /* 0x80 nand0 clock control */ + u32 nand1_clk_cfg; /* 0x84 nand1 clock control */ + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ + u32 ts_clk_cfg; /* 0x98 transport stream clock control */ + u32 ss_clk_cfg; /* 0x9c security system clock control */ + u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */ + u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */ + u32 spi2_clk_cfg; /* 0xa8 spi2 clock control */ + u32 spi3_clk_cfg; /* 0xac spi3 clock control */ + u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control*/ + u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */ + u32 reserved10[2]; + u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */ + u32 reserved11; + u32 sata_clk_cfg; /* 0xc8 SATA clock control (R40 only) */ + u32 usb_clk_cfg; /* 0xcc USB clock control */ +#ifdef CONFIG_MACH_SUN8I_R40 + u32 cir0_clk_cfg; /* 0xd0 CIR0 clock control (R40 only) */ +#else + u32 gmac_clk_cfg; /* 0xd0 GMAC clock control (not for R40) */ +#endif + u32 reserved12[7]; + u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */ + u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ + u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register, A33 only */ + u32 mbus_reset; /* 0xfc MBUS reset control, A33 only */ + u32 dram_clk_gate; /* 0x100 DRAM module gating */ +#ifdef CONFIG_SUNXI_DE2 + u32 de_clk_cfg; /* 0x104 DE module clock */ +#else + u32 be0_clk_cfg; /* 0x104 BE0 module clock */ +#endif + u32 be1_clk_cfg; /* 0x108 BE1 module clock */ + u32 fe0_clk_cfg; /* 0x10c FE0 module clock */ + u32 fe1_clk_cfg; /* 0x110 FE1 module clock */ + u32 mp_clk_cfg; /* 0x114 MP module clock */ +#ifdef CONFIG_SUNXI_DE2 + u32 lcd0_clk_cfg; /* 0x118 LCD0 module clock */ + u32 lcd1_clk_cfg; /* 0x11c LCD1 module clock */ +#else + u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */ + u32 lcd1_ch0_clk_cfg; /* 0x11c LCD1 CH0 module clock */ +#endif + u32 tve_clk_cfg; /* 0x120 H3/H5 TVE module clock */ + u32 reserved14[2]; + u32 lcd0_ch1_clk_cfg; /* 0x12c LCD0 CH1 module clock */ + u32 lcd1_ch1_clk_cfg; /* 0x130 LCD1 CH1 module clock */ + u32 csi0_clk_cfg; /* 0x134 CSI0 module clock */ + u32 csi1_clk_cfg; /* 0x138 CSI1 module clock */ + u32 ve_clk_cfg; /* 0x13c VE module clock */ + u32 adda_clk_cfg; /* 0x140 ADDA module clock */ + u32 avs_clk_cfg; /* 0x144 AVS module clock */ + u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/ + u32 reserved15; + u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */ +#ifdef CONFIG_SUNXI_DE2 + u32 hdmi_slow_clk_cfg; /* 0x154 HDMI slow module clock */ +#else + u32 ps_clk_cfg; /* 0x154 PS module clock */ +#endif + u32 mtc_clk_cfg; /* 0x158 MTC module clock */ + u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */ + u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */ +#ifdef CONFIG_MACH_SUN8I_R40 + u32 gmac_clk_cfg; /* 0x164 GMAC clock control (R40 only) */ +#else + u32 reserved16; +#endif + u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */ + u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */ + u32 reserved17[4]; + u32 iep_drc0_clk_cfg; /* 0x180 IEP DRC0 module clock */ + u32 iep_drc1_clk_cfg; /* 0x184 IEP DRC1 module clock */ + u32 iep_deu0_clk_cfg; /* 0x188 IEP DEU0 module clock */ + u32 iep_deu1_clk_cfg; /* 0x18c IEP DEU1 module clock */ + u32 reserved18[4]; + u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */ + u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */ + u32 gpu_hyd_clk_cfg; /* 0x1a0 GPU HYD clock config */ + u32 reserved19[21]; + u32 pll_lock; /* 0x200 PLL Lock Time */ + u32 pll1_lock; /* 0x204 PLL1 Lock Time */ + u32 reserved20[6]; + u32 pll1_bias_cfg; /* 0x220 PLL1 Bias config */ + u32 pll2_bias_cfg; /* 0x224 PLL2 Bias config */ + u32 pll3_bias_cfg; /* 0x228 PLL3 Bias config */ + u32 pll4_bias_cfg; /* 0x22c PLL4 Bias config */ + u32 pll5_bias_cfg; /* 0x230 PLL5 Bias config */ + u32 pll6_bias_cfg; /* 0x234 PLL6 Bias config */ + u32 pll7_bias_cfg; /* 0x238 PLL7 Bias config */ + u32 pll8_bias_cfg; /* 0x23c PLL8 Bias config */ + u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */ + u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */ + u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */ + u32 reserved21[5]; + u32 pll5_tuning_cfg; /* 0x260 PLL5 Tuning config */ + u32 reserved21_5[7]; + u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */ + u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */ + u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */ + u32 pll4_pattern_cfg; /* 0x28c PLL4 Pattern config */ + u32 pll5_pattern_cfg; /* 0x290 PLL5 Pattern config */ + u32 pll6_pattern_cfg; /* 0x294 PLL6 Pattern config */ + u32 pll7_pattern_cfg; /* 0x298 PLL7 Pattern config */ + u32 pll8_pattern_cfg; /* 0x29c PLL8 Pattern config */ + u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */ + u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */ + u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */ + u32 pll11_pattern_cfg0; /* 0x2ac PLL11 Pattern config0, A33 only */ + u32 pll11_pattern_cfg1; /* 0x2b0 PLL11 Pattern config0, A33 only */ + u32 reserved22[3]; + u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */ + u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */ + u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */ + u32 reserved23; + u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */ + u32 reserved24; + u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */ + u32 reserved25[5]; + u32 ccu_sec_switch; /* 0x2f0 CCU Security Switch, H3 only */ + u32 reserved26[11]; + u32 pll_lock_ctrl; /* 0x320 PLL lock control, R40 only */ +}; + +/* apb2 bit field */ +#define APB2_CLK_SRC_LOSC (0x0 << 24) +#define APB2_CLK_SRC_OSC24M (0x1 << 24) +#define APB2_CLK_SRC_PLL6 (0x2 << 24) +#define APB2_CLK_SRC_MASK (0x3 << 24) +#define APB2_CLK_RATE_N_1 (0x0 << 16) +#define APB2_CLK_RATE_N_2 (0x1 << 16) +#define APB2_CLK_RATE_N_4 (0x2 << 16) +#define APB2_CLK_RATE_N_8 (0x3 << 16) +#define APB2_CLK_RATE_N_MASK (3 << 16) +#define APB2_CLK_RATE_M(m) (((m)-1) << 0) +#define APB2_CLK_RATE_M_MASK (0x1f << 0) + +/* apb2 gate field */ +#define APB2_GATE_UART_SHIFT (16) +#define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT) +#define APB2_GATE_TWI_SHIFT (0) +#define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT) + +/* cpu_axi_cfg bits */ +#define AXI_DIV_SHIFT 0 +#define ATB_DIV_SHIFT 8 +#define CPU_CLK_SRC_SHIFT 16 + +#define AXI_DIV_1 0 +#define AXI_DIV_2 1 +#define AXI_DIV_3 2 +#define AXI_DIV_4 3 +#define ATB_DIV_1 0 +#define ATB_DIV_2 1 +#define ATB_DIV_4 2 +#define AHB_DIV_1 0 +#define CPU_CLK_SRC_OSC24M 1 +#define CPU_CLK_SRC_PLL1 2 + +#define CCM_PLL1_CTRL_M(n) ((((n) - 1) & 0x3) << 0) +#define CCM_PLL1_CTRL_K(n) ((((n) - 1) & 0x3) << 4) +#define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) +#define CCM_PLL1_CTRL_P(n) (((n) & 0x3) << 16) +#define CCM_PLL1_CTRL_EN (0x1 << 31) + +#define CCM_PLL3_CTRL_M_SHIFT 0 +#define CCM_PLL3_CTRL_M_MASK (0xf << CCM_PLL3_CTRL_M_SHIFT) +#define CCM_PLL3_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_PLL3_CTRL_N_SHIFT 8 +#define CCM_PLL3_CTRL_N_MASK (0x7f << CCM_PLL3_CTRL_N_SHIFT) +#define CCM_PLL3_CTRL_N(n) ((((n) - 1) & 0x7f) << 8) +#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 24) +#define CCM_PLL3_CTRL_LOCK (0x1 << 28) +#define CCM_PLL3_CTRL_EN (0x1 << 31) + +#define CCM_PLL5_CTRL_M(n) ((((n) - 1) & 0x3) << 0) +#define CCM_PLL5_CTRL_K(n) ((((n) - 1) & 0x3) << 4) +#define CCM_PLL5_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) +#define CCM_PLL5_CTRL_UPD (0x1 << 20) +#define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24) +#define CCM_PLL5_CTRL_EN (0x1 << 31) + +#define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */ + +#define CCM_PLL6_CTRL_N_SHIFT 8 +#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) +#define CCM_PLL6_CTRL_K_SHIFT 4 +#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) +#define CCM_PLL6_CTRL_LOCK (1 << 28) + +#define CCM_SATA_PLL_DEFAULT 0x90005811 /* 100 MHz */ + +#define CCM_MIPI_PLL_CTRL_M_SHIFT 0 +#define CCM_MIPI_PLL_CTRL_M_MASK (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT) +#define CCM_MIPI_PLL_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_MIPI_PLL_CTRL_K_SHIFT 4 +#define CCM_MIPI_PLL_CTRL_K_MASK (0x3 << CCM_MIPI_PLL_CTRL_K_SHIFT) +#define CCM_MIPI_PLL_CTRL_K(n) ((((n) - 1) & 0x3) << 4) +#define CCM_MIPI_PLL_CTRL_N_SHIFT 8 +#define CCM_MIPI_PLL_CTRL_N_MASK (0xf << CCM_MIPI_PLL_CTRL_N_SHIFT) +#define CCM_MIPI_PLL_CTRL_N(n) ((((n) - 1) & 0xf) << 8) +#define CCM_MIPI_PLL_CTRL_LDO_EN (0x3 << 22) +#define CCM_MIPI_PLL_CTRL_EN (0x1 << 31) + +#define CCM_PLL10_CTRL_M_SHIFT 0 +#define CCM_PLL10_CTRL_M_MASK (0xf << CCM_PLL10_CTRL_M_SHIFT) +#define CCM_PLL10_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_PLL10_CTRL_N_SHIFT 8 +#define CCM_PLL10_CTRL_N_MASK (0x7f << CCM_PLL10_CTRL_N_SHIFT) +#define CCM_PLL10_CTRL_N(n) ((((n) - 1) & 0x7f) << 8) +#define CCM_PLL10_CTRL_INTEGER_MODE (0x1 << 24) +#define CCM_PLL10_CTRL_LOCK (0x1 << 28) +#define CCM_PLL10_CTRL_EN (0x1 << 31) + +#define CCM_PLL11_CTRL_N(n) ((((n) - 1) & 0x3f) << 8) +#define CCM_PLL11_CTRL_SIGMA_DELTA_EN (0x1 << 24) +#define CCM_PLL11_CTRL_UPD (0x1 << 30) +#define CCM_PLL11_CTRL_EN (0x1 << 31) + +#define CCM_PLL5_TUN_LOCK_TIME(x) (((x) & 0x7) << 24) +#define CCM_PLL5_TUN_LOCK_TIME_MASK CCM_PLL5_TUN_LOCK_TIME(0x7) +#define CCM_PLL5_TUN_INIT_FREQ(x) (((x) & 0x7f) << 16) +#define CCM_PLL5_TUN_INIT_FREQ_MASK CCM_PLL5_TUN_INIT_FREQ(0x7f) + +#if defined(CONFIG_MACH_SUN50I) +/* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */ +#define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */ +#else +#define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */ +#endif + +#define AXI_GATE_OFFSET_DRAM 0 + +/* ahb_gate0 offsets */ +#ifdef CONFIG_MACH_SUNXI_H3_H5 +/* + * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call + * them 0 - 2 like they were called on older SoCs. + */ +#define AHB_GATE_OFFSET_USB_OHCI3 31 +#define AHB_GATE_OFFSET_USB_OHCI2 30 +#define AHB_GATE_OFFSET_USB_OHCI1 29 +#define AHB_GATE_OFFSET_USB_OHCI0 28 +#define AHB_GATE_OFFSET_USB_EHCI3 27 +#define AHB_GATE_OFFSET_USB_EHCI2 26 +#define AHB_GATE_OFFSET_USB_EHCI1 25 +#define AHB_GATE_OFFSET_USB_EHCI0 24 +#elif defined(CONFIG_MACH_SUN50I) +#define AHB_GATE_OFFSET_USB_OHCI0 28 +#define AHB_GATE_OFFSET_USB_OHCI1 29 +#define AHB_GATE_OFFSET_USB_EHCI0 24 +#define AHB_GATE_OFFSET_USB_EHCI1 25 +#else +#define AHB_GATE_OFFSET_USB_OHCI1 30 +#define AHB_GATE_OFFSET_USB_OHCI0 29 +#define AHB_GATE_OFFSET_USB_EHCI1 27 +#define AHB_GATE_OFFSET_USB_EHCI0 26 +#endif +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNXI_H3_H5) +#define AHB_GATE_OFFSET_USB0 23 +#elif !defined(CONFIG_MACH_SUN8I_R40) +#define AHB_GATE_OFFSET_USB0 24 +#else +#define AHB_GATE_OFFSET_USB0 25 +#define AHB_GATE_OFFSET_SATA 24 +#endif +#define AHB_GATE_OFFSET_MCTL 14 +#define AHB_GATE_OFFSET_GMAC 17 +#define AHB_GATE_OFFSET_NAND0 13 +#define AHB_GATE_OFFSET_NAND1 12 +#define AHB_GATE_OFFSET_MMC3 11 +#define AHB_GATE_OFFSET_MMC2 10 +#define AHB_GATE_OFFSET_MMC1 9 +#define AHB_GATE_OFFSET_MMC0 8 +#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) +#define AHB_GATE_OFFSET_DMA 6 +#define AHB_GATE_OFFSET_SS 5 + +/* ahb_gate1 offsets */ +#define AHB_GATE_OFFSET_DRC0 25 +#define AHB_GATE_OFFSET_DE_FE0 14 +#define AHB_GATE_OFFSET_DE_BE0 12 +#define AHB_GATE_OFFSET_DE 12 +#define AHB_GATE_OFFSET_HDMI 11 +#define AHB_GATE_OFFSET_TVE 9 +#ifndef CONFIG_SUNXI_DE2 +#define AHB_GATE_OFFSET_LCD1 5 +#define AHB_GATE_OFFSET_LCD0 4 +#else +#define AHB_GATE_OFFSET_LCD1 4 +#define AHB_GATE_OFFSET_LCD0 3 +#endif + +#define CCM_NAND_CTRL_M(x) ((x) - 1) +#define CCM_NAND_CTRL_N(x) ((x) << 16) +#define CCM_NAND_CTRL_PLL6 (0x1 << 24) +#define CCM_NAND_CTRL_ENABLE (0x1 << 31) + +#define CCM_MMC_CTRL_M(x) ((x) - 1) +#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) +#define CCM_MMC_CTRL_N(x) ((x) << 16) +#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) +#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) +#define CCM_MMC_CTRL_PLL6 (0x1 << 24) +#define CCM_MMC_CTRL_ENABLE (0x1 << 31) + +#define CCM_SATA_CTRL_ENABLE (0x1 << 31) +#define CCM_SATA_CTRL_USE_EXTCLK (0x1 << 24) + +#define CCM_USB_CTRL_PHY0_RST (0x1 << 0) +#define CCM_USB_CTRL_PHY1_RST (0x1 << 1) +#define CCM_USB_CTRL_PHY2_RST (0x1 << 2) +#define CCM_USB_CTRL_PHY3_RST (0x1 << 3) +/* There is no global phy clk gate on sun6i, define as 0 */ +#define CCM_USB_CTRL_PHYGATE 0 +#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8) +#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) +#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) +#define CCM_USB_CTRL_PHY3_CLK (0x1 << 11) +#ifdef CONFIG_MACH_SUNXI_H3_H5 +#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) +#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) +#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18) +#define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19) +#else +#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) +#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) +#endif + +#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 +#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 +#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 +#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) +#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) +#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5) +#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) + +#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */ + +#define CCM_DRAMCLK_CFG_DIV(x) ((x - 1) << 0) +#define CCM_DRAMCLK_CFG_DIV_MASK (0xf << 0) +#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8) +#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8) +#define CCM_DRAMCLK_CFG_SRC_PLL5 (0x0 << 20) +#define CCM_DRAMCLK_CFG_SRC_PLL6x2 (0x1 << 20) +#define CCM_DRAMCLK_CFG_SRC_PLL11 (0x1 << 20) /* A64 only */ +#define CCM_DRAMCLK_CFG_SRC_MASK (0x3 << 20) +#define CCM_DRAMCLK_CFG_UPD (0x1 << 16) +#define CCM_DRAMCLK_CFG_RST (0x1 << 31) + +#define CCM_DRAMPLL_CFG_SRC_PLL5 (0x0 << 16) /* Select PLL5 (DDR0) */ +#define CCM_DRAMPLL_CFG_SRC_PLL11 (0x1 << 16) /* Select PLL11 (DDR1) */ +#define CCM_DRAMPLL_CFG_SRC_MASK (0x1 << 16) + +#define CCM_MBUS_RESET_RESET (0x1 << 31) + +#define CCM_DRAM_GATE_OFFSET_DE_FE0 24 +#define CCM_DRAM_GATE_OFFSET_DE_FE1 25 +#define CCM_DRAM_GATE_OFFSET_DE_BE0 26 +#define CCM_DRAM_GATE_OFFSET_DE_BE1 27 + +#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24) +#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24) +#define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24) +#define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24) +#define CCM_LCD_CH0_CTRL_MIPI_PLL (4 << 24) +/* No reset bit in ch0_clk_cfg (reset is controlled through ahb_reset1) */ +#define CCM_LCD_CH0_CTRL_RST 0 +#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31) + +#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_LCD_CH1_CTRL_HALF_SCLK1 0 /* no seperate sclk1 & 2 on sun6i */ +#define CCM_LCD_CH1_CTRL_PLL3 (0 << 24) +#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24) +#define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24) +#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24) +#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31) + +#define CCM_LCD0_CTRL_GATE (0x1 << 31) +#define CCM_LCD0_CTRL_M(n) ((((n) - 1) & 0xf) << 0) + +#define CCM_LCD1_CTRL_GATE (0x1 << 31) +#define CCM_LCD1_CTRL_M(n) ((((n) - 1) & 0xf) << 0) + +#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_HDMI_CTRL_PLL_MASK (3 << 24) +#define CCM_HDMI_CTRL_PLL3 (0 << 24) +#define CCM_HDMI_CTRL_PLL7 (1 << 24) +#define CCM_HDMI_CTRL_PLL3_2X (2 << 24) +#define CCM_HDMI_CTRL_PLL7_2X (3 << 24) +#define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30) +#define CCM_HDMI_CTRL_GATE (0x1 << 31) + +#define CCM_HDMI_SLOW_CTRL_DDC_GATE (1 << 31) + +#define CCM_TVE_CTRL_GATE (0x1 << 31) +#define CCM_TVE_CTRL_M(n) ((((n) - 1) & 0xf) << 0) + +#if defined(CONFIG_MACH_SUN50I) +#define MBUS_CLK_DEFAULT 0x81000002 /* PLL6x2 / 3 */ +#elif defined(CONFIG_MACH_SUN8I) +#define MBUS_CLK_DEFAULT 0x81000003 /* PLL6 / 4 */ +#else +#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */ +#endif +#define MBUS_CLK_GATE (0x1 << 31) + +#define CCM_PLL5_PATTERN 0xd1303333 +#define CCM_PLL11_PATTERN 0xf5860000 + +/* ahb_reset0 offsets */ +#ifdef CONFIG_MACH_SUN8I_R40 +#define AHB_RESET_OFFSET_SATA 24 +#endif +#define AHB_RESET_OFFSET_GMAC 17 +#define AHB_RESET_OFFSET_MCTL 14 +#define AHB_RESET_OFFSET_MMC3 11 +#define AHB_RESET_OFFSET_MMC2 10 +#define AHB_RESET_OFFSET_MMC1 9 +#define AHB_RESET_OFFSET_MMC0 8 +#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n)) +#define AHB_RESET_OFFSET_SS 5 + +/* ahb_reset1 offsets */ +#define AHB_RESET_OFFSET_SAT 26 +#define AHB_RESET_OFFSET_DRC0 25 +#define AHB_RESET_OFFSET_DE_FE0 14 +#define AHB_RESET_OFFSET_DE_BE0 12 +#define AHB_RESET_OFFSET_DE 12 +#define AHB_RESET_OFFSET_HDMI 11 +#define AHB_RESET_OFFSET_HDMI2 10 +#define AHB_RESET_OFFSET_TVE 9 +#ifndef CONFIG_SUNXI_DE2 +#define AHB_RESET_OFFSET_LCD1 5 +#define AHB_RESET_OFFSET_LCD0 4 +#else +#define AHB_RESET_OFFSET_LCD1 4 +#define AHB_RESET_OFFSET_LCD0 3 +#endif + +/* ahb_reset2 offsets */ +#define AHB_RESET_OFFSET_EPHY 2 +#define AHB_RESET_OFFSET_LVDS 0 + +/* apb2 reset */ +#define APB2_RESET_UART_SHIFT (16) +#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT) +#define APB2_RESET_TWI_SHIFT (0) +#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT) + +/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */ +#define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_DE_CTRL_PLL_MASK (0xf << 24) +#define CCM_DE_CTRL_PLL3 (0 << 24) +#define CCM_DE_CTRL_PLL7 (1 << 24) +#define CCM_DE_CTRL_PLL6_2X (2 << 24) +#define CCM_DE_CTRL_PLL8 (3 << 24) +#define CCM_DE_CTRL_PLL9 (4 << 24) +#define CCM_DE_CTRL_PLL10 (5 << 24) +#define CCM_DE_CTRL_GATE (1 << 31) + +/* CCM bits common to all Display Engine 2.0 clock ctrl regs */ +#define CCM_DE2_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_DE2_CTRL_PLL_MASK (3 << 24) +#define CCM_DE2_CTRL_PLL6_2X (0 << 24) +#define CCM_DE2_CTRL_PLL10 (1 << 24) +#define CCM_DE2_CTRL_GATE (0x1 << 31) + +/* CCU security switch, H3 only */ +#define CCM_SEC_SWITCH_MBUS_NONSEC (1 << 2) +#define CCM_SEC_SWITCH_BUS_NONSEC (1 << 1) +#define CCM_SEC_SWITCH_PLL_NONSEC (1 << 0) + +#ifndef __ASSEMBLY__ +void clock_set_pll1(unsigned int hz); +void clock_set_pll3(unsigned int hz); +void clock_set_pll3_factors(int m, int n); +void clock_set_pll5(unsigned int clk, bool sigma_delta_enable); +void clock_set_pll10(unsigned int hz); +void clock_set_pll11(unsigned int clk, bool sigma_delta_enable); +void clock_set_mipi_pll(unsigned int hz); +unsigned int clock_get_pll3(void); +unsigned int clock_get_pll6(void); +unsigned int clock_get_mipi_pll(void); +#endif + +#endif /* _SUNXI_CLOCK_SUN6I_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h new file mode 100644 index 000000000..14df3cc8f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h @@ -0,0 +1,305 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * sun8i a83t clock register definitions + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * (C) Copyright 2015 Vishnu Patekar + * from sun6i.h + */ + +#ifndef _SUNXI_CLOCK_SUN8I_A83T_H +#define _SUNXI_CLOCK_SUN8I_A83T_H + +struct sunxi_ccm_reg { + u32 pll1_c0_cfg; /* 0x00 c1cpu# pll control */ + u32 pll1_c1_cfg; /* 0x04 c1cpu# pll control */ + u32 pll2_cfg; /* 0x08 pll2 audio control */ + u32 reserved1; + u32 pll3_cfg; /* 0x10 pll3 video0 control */ + u32 reserved2; + u32 pll4_cfg; /* 0x18 pll4 ve control */ + u32 reserved3; + u32 pll5_cfg; /* 0x20 pll5 ddr control */ + u32 reserved4; + u32 pll6_cfg; /* 0x28 pll6 peripheral control */ + u32 reserved5[3]; /* 0x2c */ + u32 pll7_cfg; /* 0x38 pll7 gpu control */ + u32 reserved6[2]; /* 0x3c */ + u32 pll8_cfg; /* 0x44 pll8 hsic control */ + u32 pll9_cfg; /* 0x48 pll9 de control */ + u32 pll10_cfg; /* 0x4c pll10 video1 control */ + u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */ + u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */ + u32 apb2_div; /* 0x58 APB2 divide ratio */ + u32 ahb2_div; /* 0x5c AHB2 divide ratio */ + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ + u32 apb1_gate; /* 0x68 apb1 module clock gating 3 */ + u32 apb2_gate; /* 0x6c apb2 module clock gating 4 */ + u32 reserved7[2]; /* 0x70 */ + u32 cci400_cfg; /* 0x78 cci400 clock configuration A83T only */ + u32 reserved8; /* 0x7c */ + u32 nand0_clk_cfg; /* 0x80 nand clock control */ + u32 reserved9; /* 0x84 */ + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ + u32 reserved10; /* 0x98 */ + u32 ss_clk_cfg; /* 0x9c security system clock control */ + u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */ + u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */ + u32 reserved11[2]; /* 0xa8 */ + u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control */ + u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */ + u32 i2s2_clk_cfg; /* 0xb8 I2S2 clock control */ + u32 tdm_clk_cfg; /* 0xbc TDM clock control */ + u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */ + u32 reserved12[2]; /* 0xc4 */ + u32 usb_clk_cfg; /* 0xcc USB clock control */ + u32 reserved13[9]; /* 0xd0 */ + u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ + u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register */ + u32 mbus_reset; /* 0xfc MBUS reset control */ + u32 dram_clk_gate; /* 0x100 DRAM module gating */ + u32 reserved14[5]; /* 0x104 BE0 */ + u32 lcd0_clk_cfg; /* 0x118 LCD0 module clock */ + u32 lcd1_clk_cfg; /* 0x11c LCD1 module clock */ + u32 reserved15[4]; /* 0x120 */ + u32 mipi_csi_clk_cfg; /* 0x130 MIPI CSI module clock */ + u32 csi_clk_cfg; /* 0x134 CSI module clock */ + u32 reserved16; /* 0x138 */ + u32 ve_clk_cfg; /* 0x13c VE module clock */ + u32 reserved17; /* 0x140 */ + u32 avs_clk_cfg; /* 0x144 AVS module clock */ + u32 reserved18[2]; /* 0x148 */ + u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */ + u32 hdmi_slow_clk_cfg; /* 0x154 HDMI slow module clock */ + u32 reserved19; /* 0x158 */ + u32 mbus_clk_cfg; /* 0x15c MBUS module clock */ + u32 reserved20[2]; /* 0x160 */ + u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */ + u32 reserved21[13]; /* 0x16c */ + u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */ + u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */ + u32 gpu_hyd_clk_cfg; /* 0x1a8 GPU HYD clock config */ + u32 reserved22[21]; /* 0x1ac */ + u32 pll_stable0; /* 0x200 PLL stable time 0 */ + u32 pll_stable1; /* 0x204 PLL stable time 1 */ + u32 reserved23; /* 0x208 */ + u32 pll_stable_status; /* 0x20c PLL stable status register */ + u32 reserved24[4]; /* 0x210 */ + u32 pll1_c0_bias_cfg; /* 0x220 PLL1 c0cpu# Bias config */ + u32 pll2_bias_cfg; /* 0x224 PLL2 audio Bias config */ + u32 pll3_bias_cfg; /* 0x228 PLL3 video Bias config */ + u32 pll4_bias_cfg; /* 0x22c PLL4 ve Bias config */ + u32 pll5_bias_cfg; /* 0x230 PLL5 ddr Bias config */ + u32 pll6_bias_cfg; /* 0x234 PLL6 periph Bias config */ + u32 pll1_c1_bias_cfg; /* 0x238 PLL1 c1cpu# Bias config */ + u32 pll8_bias_cfg; /* 0x23c PLL7 Bias config */ + u32 reserved25; /* 0x240 */ + u32 pll9_bias_cfg; /* 0x244 PLL9 hsic Bias config */ + u32 de_bias_cfg; /* 0x248 display engine Bias config */ + u32 video1_bias_cfg; /* 0x24c pll video1 bias register */ + u32 c0_tuning_cfg; /* 0x250 pll c0cpu# tuning register */ + u32 c1_tuning_cfg; /* 0x254 pll c1cpu# tuning register */ + u32 reserved26[11]; /* 0x258 */ + u32 pll2_pattern_cfg0; /* 0x284 PLL2 Pattern register 0 */ + u32 pll3_pattern_cfg0; /* 0x288 PLL3 Pattern register 0 */ + u32 reserved27; /* 0x28c */ + u32 pll5_pattern_cfg0; /* 0x290 PLL5 Pattern register 0*/ + u32 reserved28[4]; /* 0x294 */ + u32 pll2_pattern_cfg1; /* 0x2a4 PLL2 Pattern register 1 */ + u32 pll3_pattern_cfg1; /* 0x2a8 PLL3 Pattern register 1 */ + u32 reserved29; /* 0x2ac */ + u32 pll5_pattern_cfg1; /* 0x2b0 PLL5 Pattern register 1 */ + u32 reserved30[3]; /* 0x2b4 */ + u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */ + u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */ + u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */ + u32 reserved31; + u32 ahb_reset3_cfg; /* 0x2d0 AHB1 Reset 3 config */ + u32 reserved32; /* 0x2d4 */ + u32 apb2_reset_cfg; /* 0x2d8 BUS Reset 4 config */ +}; + +/* apb2 bit field */ +#define APB2_CLK_SRC_LOSC (0x0 << 24) +#define APB2_CLK_SRC_OSC24M (0x1 << 24) +#define APB2_CLK_SRC_PLL6 (0x2 << 24) +#define APB2_CLK_SRC_MASK (0x3 << 24) +#define APB2_CLK_RATE_N_1 (0x0 << 16) +#define APB2_CLK_RATE_N_2 (0x1 << 16) +#define APB2_CLK_RATE_N_4 (0x2 << 16) +#define APB2_CLK_RATE_N_8 (0x3 << 16) +#define APB2_CLK_RATE_N_MASK (3 << 16) +#define APB2_CLK_RATE_M(m) (((m)-1) << 0) +#define APB2_CLK_RATE_M_MASK (0x1f << 0) + +/* apb2 gate field */ +#define APB2_GATE_UART_SHIFT (16) +#define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT) +#define APB2_GATE_TWI_SHIFT (0) +#define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT) + +/* cpu_axi_cfg bits */ +#define AXI0_DIV_SHIFT 0 +#define AXI1_DIV_SHIFT 16 +#define C0_CPUX_CLK_SRC_SHIFT 12 +#define C1_CPUX_CLK_SRC_SHIFT 28 + +#define AXI_DIV_1 0 +#define AXI_DIV_2 1 +#define AXI_DIV_3 2 +#define AXI_DIV_4 3 +#define CPU_CLK_SRC_OSC24M 0 +#define CPU_CLK_SRC_PLL1 1 + +#define CCM_PLL1_CTRL_N(n) (((n) & 0xff) << 8) +#define CCM_PLL1_CTRL_P(n) (((n) & 0x1) << 16) +#define CCM_PLL1_CTRL_EN (0x1 << 31) +#define CMM_PLL1_CLOCK_TIME_2 (0x2 << 24) + +#define PLL8_CFG_DEFAULT 0x42800 +#define CCM_CCI400_CLK_SEL_HSIC (0x2<<24) + +#define CCM_PLL5_DIV1_SHIFT 16 +#define CCM_PLL5_DIV2_SHIFT 18 +#define CCM_PLL5_CTRL_N(n) (((n) - 1) << 8) +#define CCM_PLL5_CTRL_UPD (0x1 << 30) +#define CCM_PLL5_CTRL_EN (0x1 << 31) + +#define PLL6_CFG_DEFAULT 0x80001900 /* 600 MHz */ +#define CCM_PLL6_CTRL_N_SHIFT 8 +#define CCM_PLL6_CTRL_N_MASK (0xff << CCM_PLL6_CTRL_N_SHIFT) +#define CCM_PLL6_CTRL_DIV1_SHIFT 16 +#define CCM_PLL6_CTRL_DIV1_MASK (0x1 << CCM_PLL6_CTRL_DIV1_SHIFT) +#define CCM_PLL6_CTRL_DIV2_SHIFT 18 +#define CCM_PLL6_CTRL_DIV2_MASK (0x1 << CCM_PLL6_CTRL_DIV2_SHIFT) + +#define AHB1_ABP1_DIV_DEFAULT 0x00002190 +#define AHB1_CLK_SRC_MASK (0x3<<12) +#define AHB1_CLK_SRC_INTOSC (0x0<<12) +#define AHB1_CLK_SRC_OSC24M (0x1<<12) +#define AHB1_CLK_SRC_PLL6 (0x2<<12) + +#define AXI_GATE_OFFSET_DRAM 0 + +/* ahb_gate0 offsets */ +#define AHB_GATE_OFFSET_USB_OHCI1 30 +#define AHB_GATE_OFFSET_USB_OHCI0 29 +#define AHB_GATE_OFFSET_USB_EHCI1 27 +#define AHB_GATE_OFFSET_USB_EHCI0 26 +#define AHB_GATE_OFFSET_USB0 24 +#define AHB_GATE_OFFSET_SPI1 21 +#define AHB_GATE_OFFSET_SPI0 20 +#define AHB_GATE_OFFSET_HSTIMER 19 +#define AHB_GATE_OFFSET_EMAC 17 +#define AHB_GATE_OFFSET_MCTL 14 +#define AHB_GATE_OFFSET_GMAC 17 +#define AHB_GATE_OFFSET_NAND0 13 +#define AHB_GATE_OFFSET_MMC0 8 +#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) +#define AHB_GATE_OFFSET_DMA 6 +#define AHB_GATE_OFFSET_SS 5 + +/* ahb_gate1 offsets */ +#define AHB_GATE_OFFSET_DRC0 25 +#define AHB_GATE_OFFSET_DE_FE0 14 +#define AHB_GATE_OFFSET_DE_BE0 12 +#define AHB_GATE_OFFSET_HDMI 11 +#define AHB_GATE_OFFSET_LCD1 5 +#define AHB_GATE_OFFSET_LCD0 4 + +#define CCM_MMC_CTRL_M(x) ((x) - 1) +#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) +#define CCM_MMC_CTRL_N(x) ((x) << 16) +#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) +#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) +#define CCM_MMC_CTRL_PLL6 (0x1 << 24) +#define CCM_MMC_CTRL_MODE_SEL_NEW (0x1 << 30) +#define CCM_MMC_CTRL_ENABLE (0x1 << 31) + +#define CCM_USB_CTRL_PHY0_RST (0x1 << 0) +#define CCM_USB_CTRL_PHY1_RST (0x1 << 1) +#define CCM_USB_CTRL_HSIC_RST (0x1 << 2) +/* There is no global phy clk gate on sun6i, define as 0 */ +#define CCM_USB_CTRL_PHYGATE 0 +#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8) +#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) +#define CCM_USB_CTRL_HSIC_CLK (0x1 << 10) +#define CCM_USB_CTRL_12M_CLK (0x1 << 11) +#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) + +#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 +#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 +#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 +#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) +#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) +#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5) +#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) + +#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */ + +#define CCM_DRAMCLK_CFG_DIV(x) ((x - 1) << 0) +#define CCM_DRAMCLK_CFG_DIV_MASK (0xf << 0) +#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8) +#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8) +#define CCM_DRAMCLK_CFG_UPD (0x1 << 16) +#define CCM_DRAMCLK_CFG_RST (0x1 << 31) + +#define CCM_DRAMPLL_CFG_SRC_PLL5 (0x0 << 16) /* Select PLL5 (DDR0) */ +#define CCM_DRAMPLL_CFG_SRC_PLL11 (0x1 << 16) /* Select PLL11 (DDR1) */ +#define CCM_DRAMPLL_CFG_SRC_MASK (0x1 << 16) + +#define CCM_MBUS_RESET_RESET (0x1 << 31) + +#define CCM_DRAM_GATE_OFFSET_DE_FE0 24 +#define CCM_DRAM_GATE_OFFSET_DE_FE1 25 +#define CCM_DRAM_GATE_OFFSET_DE_BE0 26 +#define CCM_DRAM_GATE_OFFSET_DE_BE1 27 + + +#define MBUS_CLK_DEFAULT 0x81000002 /* PLL6 / 2 */ + +#define MBUS_CLK_GATE (0x1 << 31) + +/* ahb_reset0 offsets */ +#define AHB_RESET_OFFSET_GMAC 17 +#define AHB_RESET_OFFSET_MCTL 14 +#define AHB_RESET_OFFSET_MMC3 11 +#define AHB_RESET_OFFSET_MMC2 10 +#define AHB_RESET_OFFSET_MMC1 9 +#define AHB_RESET_OFFSET_MMC0 8 +#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n)) +#define AHB_RESET_OFFSET_SS 5 + +/* ahb_reset1 offsets */ +#define AHB_RESET_OFFSET_SAT 26 +#define AHB_RESET_OFFSET_DRC0 25 +#define AHB_RESET_OFFSET_DE_FE0 14 +#define AHB_RESET_OFFSET_DE_BE0 12 +#define AHB_RESET_OFFSET_HDMI 11 +#define AHB_RESET_OFFSET_LCD1 5 +#define AHB_RESET_OFFSET_LCD0 4 + +/* ahb_reset2 offsets */ +#define AHB_RESET_OFFSET_LVDS 0 + +/* apb2 reset */ +#define APB2_RESET_UART_SHIFT (16) +#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT) +#define APB2_RESET_TWI_SHIFT (0) +#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT) + + +#ifndef __ASSEMBLY__ +void clock_set_pll1(unsigned int hz); +void clock_set_pll5(unsigned int clk); +unsigned int clock_get_pll6(void); +#endif + +#endif /* _SUNXI_CLOCK_SUN8I_A83T_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/clock_sun9i.h new file mode 100644 index 000000000..fe6b8ba27 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/clock_sun9i.h @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * sun9i clock register definitions + * + * (C) Copyright 2015 Hans de Goede + */ + +#ifndef _SUNXI_CLOCK_SUN9I_H +#define _SUNXI_CLOCK_SUN9I_H + +#ifndef __ASSEMBLY__ +#include +#endif + +struct sunxi_ccm_reg { + u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */ + u32 pll2_c1_cfg; /* 0x04 c1cpu# pll configuration */ + u32 pll3_audio_cfg; /* 0x08 audio pll configuration */ + u32 pll4_periph0_cfg; /* 0x0c peripheral0 pll configuration */ + u32 pll5_ve_cfg; /* 0x10 videoengine pll configuration */ + u32 pll6_ddr_cfg; /* 0x14 ddr pll configuration */ + u32 pll7_video0_cfg; /* 0x18 video0 pll configuration */ + u32 pll8_video1_cfg; /* 0x1c video1 pll configuration */ + u32 pll9_gpu_cfg; /* 0x20 gpu pll configuration */ + u32 pll10_de_cfg; /* 0x24 displayengine pll configuration */ + u32 pll11_isp_cfg; /* 0x28 isp pll6 ontrol */ + u32 pll12_periph1_cfg; /* 0x2c peripheral1 pll configuration */ + u8 reserved1[0x20]; /* 0x30 */ + u32 cpu_clk_source; /* 0x50 cpu clk source configuration */ + u32 c0_cfg; /* 0x54 cpu cluster 0 clock configuration */ + u32 c1_cfg; /* 0x58 cpu cluster 1 clock configuration */ + u32 gtbus_cfg; /* 0x5c gtbus clock configuration */ + u32 ahb0_cfg; /* 0x60 ahb0 clock configuration */ + u32 ahb1_cfg; /* 0x64 ahb1 clock configuration */ + u32 ahb2_cfg; /* 0x68 ahb2 clock configuration */ + u8 reserved2[0x04]; /* 0x6c */ + u32 apb0_cfg; /* 0x70 apb0 clock configuration */ + u32 apb1_cfg; /* 0x74 apb1 clock configuration */ + u32 cci400_cfg; /* 0x78 cci400 clock configuration */ + u8 reserved3[0x04]; /* 0x7c */ + u32 ats_cfg; /* 0x80 ats clock configuration */ + u32 trace_cfg; /* 0x84 trace clock configuration */ + u8 reserved4[0x14]; /* 0x88 */ + u32 pll_stable_status; /* 0x9c */ + u8 reserved5[0xe0]; /* 0xa0 */ + u32 clk_output_a; /* 0x180 clk_output_a */ + u32 clk_output_b; /* 0x184 clk_output_a */ + u8 reserved6[0x278]; /* 0x188 */ + + u32 nand0_clk_cfg; /* 0x400 nand0 clock configuration0 */ + u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */ + u8 reserved7[0x08]; /* 0x408 */ + u32 sd0_clk_cfg; /* 0x410 sd0 clock configuration */ + u32 sd1_clk_cfg; /* 0x414 sd1 clock configuration */ + u32 sd2_clk_cfg; /* 0x418 sd2 clock configuration */ + u32 sd3_clk_cfg; /* 0x41c sd3 clock configuration */ + u8 reserved8[0x08]; /* 0x420 */ + u32 ts_clk_cfg; /* 0x428 transport stream clock cfg */ + u32 ss_clk_cfg; /* 0x42c security system clock cfg */ + u32 spi0_clk_cfg; /* 0x430 spi0 clock configuration */ + u32 spi1_clk_cfg; /* 0x434 spi1 clock configuration */ + u32 spi2_clk_cfg; /* 0x438 spi2 clock configuration */ + u32 spi3_clk_cfg; /* 0x43c spi3 clock configuration */ + u8 reserved9[0x44]; /* 0x440 */ + u32 dram_clk_cfg; /* 0x484 DRAM (controller) clock config */ + u8 reserved10[0x8]; /* 0x488 */ + u32 de_clk_cfg; /* 0x490 display engine clock configuration */ + u8 reserved11[0x04]; /* 0x494 */ + u32 mp_clk_cfg; /* 0x498 mp clock configuration */ + u32 lcd0_clk_cfg; /* 0x49c LCD0 module clock */ + u32 lcd1_clk_cfg; /* 0x4a0 LCD1 module clock */ + u8 reserved12[0x1c]; /* 0x4a4 */ + u32 csi_isp_clk_cfg; /* 0x4c0 CSI ISP module clock */ + u32 csi0_clk_cfg; /* 0x4c4 CSI0 module clock */ + u32 csi1_clk_cfg; /* 0x4c8 CSI1 module clock */ + u32 fd_clk_cfg; /* 0x4cc FD module clock */ + u32 ve_clk_cfg; /* 0x4d0 VE module clock */ + u32 avs_clk_cfg; /* 0x4d4 AVS module clock */ + u8 reserved13[0x18]; /* 0x4d8 */ + u32 gpu_core_clk_cfg; /* 0x4f0 GPU core clock config */ + u32 gpu_mem_clk_cfg; /* 0x4f4 GPU memory clock config */ + u32 gpu_axi_clk_cfg; /* 0x4f8 GPU AXI clock config */ + u8 reserved14[0x10]; /* 0x4fc */ + u32 gp_adc_clk_cfg; /* 0x50c General Purpose ADC clk config */ + u8 reserved15[0x70]; /* 0x510 */ + + u32 ahb_gate0; /* 0x580 AHB0 Gating Register */ + u32 ahb_gate1; /* 0x584 AHB1 Gating Register */ + u32 ahb_gate2; /* 0x588 AHB2 Gating Register */ + u8 reserved16[0x04]; /* 0x58c */ + u32 apb0_gate; /* 0x590 APB0 Clock Gating Register */ + u32 apb1_gate; /* 0x594 APB1 Clock Gating Register */ + u8 reserved17[0x08]; /* 0x598 */ + u32 ahb_reset0_cfg; /* 0x5a0 AHB0 Software Reset Register */ + u32 ahb_reset1_cfg; /* 0x5a4 AHB1 Software Reset Register */ + u32 ahb_reset2_cfg; /* 0x5a8 AHB2 Software Reset Register */ + u8 reserved18[0x04]; /* 0x5ac */ + u32 apb0_reset_cfg; /* 0x5b0 Bus Software Reset Register 3 */ + u32 apb1_reset_cfg; /* 0x5b4 Bus Software Reset Register 4 */ +}; + +#define CCM_PLL4_CTRL_N_SHIFT 8 +#define CCM_PLL4_CTRL_N_MASK (0xff << CCM_PLL4_CTRL_N_SHIFT) +#define CCM_PLL4_CTRL_P_SHIFT 16 +#define CCM_PLL4_CTRL_P_MASK (0x1 << CCM_PLL4_CTRL_P_SHIFT) +#define CCM_PLL4_CTRL_M_SHIFT 18 +#define CCM_PLL4_CTRL_M_MASK (0x1 << CCM_PLL4_CTRL_M_SHIFT) + +/* pllx_cfg bits */ +#define CCM_PLL1_CTRL_N(n) (((n) & 0xff) << 8) +#define CCM_PLL1_CTRL_P(n) (((n) & 0x1) << 16) +#define CCM_PLL1_CTRL_EN (1 << 31) +#define CCM_PLL1_CLOCK_TIME_2 (2 << 24) + +#define CCM_PLL2_CTRL_N(n) (((n) & 0xff) << 8) +#define CCM_PLL2_CTRL_P(n) (((n) & 0x1) << 16) +#define CCM_PLL2_CTRL_EN (1 << 31) +#define CCM_PLL2_CLOCK_TIME_2 (2 << 24) + +#define CCM_PLL4_CTRL_N(n) (((n) & 0xff) << 8) +#define CCM_PLL4_CTRL_EN (1 << 31) + +#define CCM_PLL6_CTRL_N(n) (((n) & 0xff) << 8) +#define CCM_PLL6_CTRL_P(p) (((p) & 0x1) << 16) +#define CCM_PLL6_CTRL_EN (1 << 31) +#define CCM_PLL6_CFG_UPDATE (1 << 30) + +#define CCM_PLL12_CTRL_N(n) (((n) & 0xff) << 8) +#define CCM_PLL12_CTRL_EN (1 << 31) + +#define PLL_C0CPUX_STATUS (1 << 0) +#define PLL_C1CPUX_STATUS (1 << 1) +#define PLL_DDR_STATUS (1 << 5) +#define PLL_PERIPH1_STATUS (1 << 11) + +/* cpu_clk_source bits */ +#define C0_CPUX_CLK_SRC_SHIFT 0 +#define C1_CPUX_CLK_SRC_SHIFT 8 +#define C0_CPUX_CLK_SRC_MASK (1 << C0_CPUX_CLK_SRC_SHIFT) +#define C1_CPUX_CLK_SRC_MASK (1 << C1_CPUX_CLK_SRC_SHIFT) +#define C0_CPUX_CLK_SRC_OSC24M (0 << C0_CPUX_CLK_SRC_SHIFT) +#define C0_CPUX_CLK_SRC_PLL1 (1 << C0_CPUX_CLK_SRC_SHIFT) +#define C1_CPUX_CLK_SRC_OSC24M (0 << C1_CPUX_CLK_SRC_SHIFT) +#define C1_CPUX_CLK_SRC_PLL2 (1 << C1_CPUX_CLK_SRC_SHIFT) + +/* c0_cfg */ +#define C0_CFG_AXI0_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0) +#define C0_CFG_APB0_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 8) + +/* ahbx_cfg */ +#define AHBx_SRC_CLK_SELECT_SHIFT 24 +#define AHBx_SRC_MASK (0x3 << AHBx_SRC_CLK_SELECT_SHIFT) +#define AHB0_SRC_GTBUS_CLK (0x0 << AHBx_SRC_CLK_SELECT_SHIFT) +#define AHB1_SRC_GTBUS_CLK (0x0 << AHBx_SRC_CLK_SELECT_SHIFT) +#define AHB2_SRC_OSC24M (0x0 << AHBx_SRC_CLK_SELECT_SHIFT) +#define AHBx_SRC_PLL_PERIPH0 (0x1 << AHBx_SRC_CLK_SELECT_SHIFT) +#define AHBx_SRC_PLL_PERIPH1 (0x2 << AHBx_SRC_CLK_SELECT_SHIFT) +#define AHBx_CLK_DIV_RATIO(n) (((ffs(n) - 1) & 0x3) << 0) + +/* apb0_cfg */ +#define APB0_SRC_CLK_SELECT_SHIFT 24 +#define APB0_SRC_MASK (0x1 << APB0_SRC_CLK_SELECT_SHIFT) +#define APB0_SRC_OSC24M (0x0 << APB0_SRC_CLK_SELECT_SHIFT) +#define APB0_SRC_PLL_PERIPH0 (0x1 << APB0_SRC_CLK_SELECT_SHIFT) +#define APB0_CLK_DIV_RATIO(n) (((ffs(n) - 1) & 0x3) << 0) + +/* gtbus_clk_cfg */ +#define GTBUS_SRC_CLK_SELECT_SHIFT 24 +#define GTBUS_SRC_MASK (0x3 << GTBUS_SRC_CLK_SELECT_SHIFT) +#define GTBUS_SRC_OSC24M (0x0 << GTBUS_SRC_CLK_SELECT_SHIFT) +#define GTBUS_SRC_PLL_PERIPH0 (0x1 << GTBUS_SRC_CLK_SELECT_SHIFT) +#define GTBUS_SRC_PLL_PERIPH1 (0x2 << GTBUS_SRC_CLK_SELECT_SHIFT) +#define GTBUS_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0) + +/* cci400_clk_cfg */ +#define CCI400_SRC_CLK_SELECT_SHIFT 24 +#define CCI400_SRC_MASK (0x3 << CCI400_SRC_CLK_SELECT_SHIFT) +#define CCI400_SRC_OSC24M (0x0 << CCI400_SRC_CLK_SELECT_SHIFT) +#define CCI400_SRC_PLL_PERIPH0 (0x1 << CCI400_SRC_CLK_SELECT_SHIFT) +#define CCI400_SRC_PLL_PERIPH1 (0x2 << CCI400_SRC_CLK_SELECT_SHIFT) +#define CCI400_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0) + +/* sd#_clk_cfg fields */ +#define CCM_MMC_CTRL_M(x) ((x) - 1) +#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) +#define CCM_MMC_CTRL_N(x) ((x) << 16) +#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) +#define CCM_MMC_CTRL_OSCM24 (0 << 24) +#define CCM_MMC_CTRL_PLL_PERIPH0 (1 << 24) +#define CCM_MMC_CTRL_ENABLE (1 << 31) + +/* ahb_gate0 fields */ +#define AHB_GATE_OFFSET_MCTL 14 + +/* On sun9i all sdc-s share their ahb gate, so ignore (x) */ +#define AHB_GATE_OFFSET_NAND0 13 +#define AHB_GATE_OFFSET_MMC(x) 8 + +/* ahb gate1 field */ +#define AHB_GATE_OFFSET_DMA 24 + +/* apb1_gate fields */ +#define APB1_GATE_UART_SHIFT 16 +#define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT) +#define APB1_GATE_TWI_SHIFT 0 +#define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT) + +/* ahb_reset0_cfg fields */ +#define AHB_RESET_OFFSET_MCTL 14 + +/* On sun9i all sdc-s share their ahb reset, so ignore (x) */ +#define AHB_RESET_OFFSET_MMC(x) 8 + +/* apb1_reset_cfg fields */ +#define APB1_RESET_UART_SHIFT 16 +#define APB1_RESET_UART_MASK (0xff << APB1_RESET_UART_SHIFT) +#define APB1_RESET_TWI_SHIFT 0 +#define APB1_RESET_TWI_MASK (0xf << APB1_RESET_TWI_SHIFT) + + +#ifndef __ASSEMBLY__ +void clock_set_pll1(unsigned int clk); +void clock_set_pll2(unsigned int clk); +void clock_set_pll4(unsigned int clk); +void clock_set_pll6(unsigned int clk); +void clock_set_pll12(unsigned int clk); +unsigned int clock_get_pll4_periph0(void); +#endif + +#endif /* _SUNXI_CLOCK_SUN9I_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/cpu.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/cpu.h new file mode 100644 index 000000000..b08f20237 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/cpu.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Hans de Goede + */ + +#ifndef _SUNXI_CPU_H +#define _SUNXI_CPU_H + +#if defined(CONFIG_MACH_SUN9I) +#include +#elif defined(CONFIG_SUN50I_GEN_H6) +#include +#else +#include +#endif + +#define SOCID_A64 0x1689 +#define SOCID_H3 0x1680 +#define SOCID_V3S 0x1681 +#define SOCID_H5 0x1718 +#define SOCID_R40 0x1701 + +#endif /* _SUNXI_CPU_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h new file mode 100644 index 000000000..02ce73954 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -0,0 +1,220 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + */ + +#ifndef _SUNXI_CPU_SUN4I_H +#define _SUNXI_CPU_SUN4I_H + +#define SUNXI_SRAM_A1_BASE 0x00000000 +#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ + +#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */ +#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */ +#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ +#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ +#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */ + +#define SUNXI_DE2_BASE 0x01000000 + +#ifdef CONFIG_MACH_SUN8I_A83T +#define SUNXI_CPUCFG_BASE 0x01700000 +#endif + +#define SUNXI_SRAMC_BASE 0x01c00000 +#define SUNXI_DRAMC_BASE 0x01c01000 +#define SUNXI_DMA_BASE 0x01c02000 +#define SUNXI_NFC_BASE 0x01c03000 +#define SUNXI_TS_BASE 0x01c04000 +#define SUNXI_SPI0_BASE 0x01c05000 +#define SUNXI_SPI1_BASE 0x01c06000 +#define SUNXI_MS_BASE 0x01c07000 +#define SUNXI_TVD_BASE 0x01c08000 +#define SUNXI_CSI0_BASE 0x01c09000 +#ifndef CONFIG_MACH_SUNXI_H3_H5 +#define SUNXI_TVE0_BASE 0x01c0a000 +#endif +#define SUNXI_EMAC_BASE 0x01c0b000 +#define SUNXI_LCD0_BASE 0x01c0C000 +#define SUNXI_LCD1_BASE 0x01c0d000 +#define SUNXI_VE_BASE 0x01c0e000 +#define SUNXI_MMC0_BASE 0x01c0f000 +#define SUNXI_MMC1_BASE 0x01c10000 +#define SUNXI_MMC2_BASE 0x01c11000 +#define SUNXI_MMC3_BASE 0x01c12000 +#ifdef CONFIG_SUNXI_GEN_SUN4I +#define SUNXI_USB0_BASE 0x01c13000 +#define SUNXI_USB1_BASE 0x01c14000 +#endif +#define SUNXI_SS_BASE 0x01c15000 +#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) +#define SUNXI_HDMI_BASE 0x01c16000 +#endif +#define SUNXI_SPI2_BASE 0x01c17000 +#define SUNXI_SATA_BASE 0x01c18000 +#ifdef CONFIG_SUNXI_GEN_SUN4I +#define SUNXI_PATA_BASE 0x01c19000 +#define SUNXI_ACE_BASE 0x01c1a000 +#define SUNXI_TVE1_BASE 0x01c1b000 +#define SUNXI_USB2_BASE 0x01c1c000 +#endif +#ifdef CONFIG_SUNXI_GEN_SUN6I +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) +#define SUNXI_USBPHY_BASE 0x01c19000 +#define SUNXI_USB0_BASE SUNXI_USBPHY_BASE +#define SUNXI_USB1_BASE 0x01c1a000 +#define SUNXI_USB2_BASE 0x01c1b000 +#define SUNXI_USB3_BASE 0x01c1c000 +#define SUNXI_USB4_BASE 0x01c1d000 +#else +#define SUNXI_USB0_BASE 0x01c19000 +#define SUNXI_USB1_BASE 0x01c1a000 +#define SUNXI_USB2_BASE 0x01c1b000 +#endif +#endif +#define SUNXI_CSI1_BASE 0x01c1d000 +#define SUNXI_TZASC_BASE 0x01c1e000 +#define SUNXI_SPI3_BASE 0x01c1f000 + +#define SUNXI_CCM_BASE 0x01c20000 +#define SUNXI_INTC_BASE 0x01c20400 +#define SUNXI_PIO_BASE 0x01c20800 +#define SUNXI_TIMER_BASE 0x01c20c00 +#ifndef CONFIG_SUNXI_GEN_SUN6I +#define SUNXI_PWM_BASE 0x01c20e00 +#endif +#define SUNXI_SPDIF_BASE 0x01c21000 +#ifdef CONFIG_SUNXI_GEN_SUN6I +#define SUNXI_PWM_BASE 0x01c21400 +#else +#define SUNXI_AC97_BASE 0x01c21400 +#endif +#define SUNXI_IR0_BASE 0x01c21800 +#define SUNXI_IR1_BASE 0x01c21c00 + +#define SUNXI_IIS_BASE 0x01c22400 +#define SUNXI_LRADC_BASE 0x01c22800 +#define SUNXI_AD_DA_BASE 0x01c22c00 +#define SUNXI_KEYPAD_BASE 0x01c23000 +#define SUNXI_TZPC_BASE 0x01c23400 + +#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUNXI_H3_H5) || \ +defined(CONFIG_MACH_SUN50I) +/* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */ +#define SUNXI_SIDC_BASE 0x01c14000 +#define SUNXI_SID_BASE 0x01c14200 +#else +#define SUNXI_SID_BASE 0x01c23800 +#endif + +#define SUNXI_SJTAG_BASE 0x01c23c00 + +#define SUNXI_TP_BASE 0x01c25000 +#define SUNXI_PMU_BASE 0x01c25400 + +#if defined CONFIG_MACH_SUN7I || defined CONFIG_MACH_SUN8I_R40 +#define SUNXI_CPUCFG_BASE 0x01c25c00 +#endif + +#define SUNXI_UART0_BASE 0x01c28000 +#define SUNXI_UART1_BASE 0x01c28400 +#define SUNXI_UART2_BASE 0x01c28800 +#define SUNXI_UART3_BASE 0x01c28c00 +#define SUNXI_UART4_BASE 0x01c29000 +#define SUNXI_UART5_BASE 0x01c29400 +#define SUNXI_UART6_BASE 0x01c29800 +#define SUNXI_UART7_BASE 0x01c29c00 +#define SUNXI_PS2_0_BASE 0x01c2a000 +#define SUNXI_PS2_1_BASE 0x01c2a400 + +#define SUNXI_TWI0_BASE 0x01c2ac00 +#define SUNXI_TWI1_BASE 0x01c2b000 +#define SUNXI_TWI2_BASE 0x01c2b400 +#ifdef CONFIG_MACH_SUN6I +#define SUNXI_TWI3_BASE 0x01c0b800 +#endif +#ifdef CONFIG_MACH_SUN7I +#define SUNXI_TWI3_BASE 0x01c2b800 +#define SUNXI_TWI4_BASE 0x01c2c000 +#endif + +#define SUNXI_CAN_BASE 0x01c2bc00 + +#define SUNXI_SCR_BASE 0x01c2c400 + +#ifndef CONFIG_MACH_SUN6I +#define SUNXI_GPS_BASE 0x01c30000 +#define SUNXI_MALI400_BASE 0x01c40000 +#define SUNXI_GMAC_BASE 0x01c50000 +#else +#define SUNXI_GMAC_BASE 0x01c30000 +#endif + +#define SUNXI_DRAM_COM_BASE 0x01c62000 +#define SUNXI_DRAM_CTL0_BASE 0x01c63000 +#define SUNXI_DRAM_CTL1_BASE 0x01c64000 +#define SUNXI_DRAM_PHY0_BASE 0x01c65000 +#define SUNXI_DRAM_PHY1_BASE 0x01c66000 + +#define SUNXI_GIC400_BASE 0x01c80000 + +/* module sram */ +#define SUNXI_SRAM_C_BASE 0x01d00000 + +#ifndef CONFIG_MACH_SUN8I_H3 +#define SUNXI_DE_FE0_BASE 0x01e00000 +#else +#define SUNXI_TVE0_BASE 0x01e00000 +#endif +#define SUNXI_DE_FE1_BASE 0x01e20000 +#define SUNXI_DE_BE0_BASE 0x01e60000 +#ifndef CONFIG_MACH_SUN50I_H5 +#define SUNXI_DE_BE1_BASE 0x01e40000 +#else +#define SUNXI_TVE0_BASE 0x01e40000 +#endif +#define SUNXI_MP_BASE 0x01e80000 +#define SUNXI_AVG_BASE 0x01ea0000 + +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) +#define SUNXI_HDMI_BASE 0x01ee0000 +#endif + +#define SUNXI_RTC_BASE 0x01f00000 +#define SUNXI_PRCM_BASE 0x01f01400 + +#if defined CONFIG_SUNXI_GEN_SUN6I && \ + !defined CONFIG_MACH_SUN8I_A83T && \ + !defined CONFIG_MACH_SUN8I_R40 +#define SUNXI_CPUCFG_BASE 0x01f01c00 +#endif + +#define SUNXI_R_TWI_BASE 0x01f02400 +#define SUNXI_R_UART_BASE 0x01f02800 +#define SUNXI_R_PIO_BASE 0x01f02c00 +#define SUN6I_P2WI_BASE 0x01f03400 +#define SUNXI_RSB_BASE 0x01f03400 + +/* CoreSight Debug Module */ +#define SUNXI_CSDM_BASE 0x3f500000 + +#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */ + +#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */ + +#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) + +/* SS bonding ids used for cpu identification */ +#define SUNXI_SS_BOND_ID_A31 4 +#define SUNXI_SS_BOND_ID_A31S 5 + +#ifndef __ASSEMBLY__ +void sunxi_board_init(void); +void sunxi_reset(void); +int sunxi_get_ss_bonding_id(void); +int sunxi_get_sid(unsigned int *sid); +#endif /* __ASSEMBLY__ */ + +#endif /* _SUNXI_CPU_SUN4I_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h new file mode 100644 index 000000000..d9cf8ae04 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h @@ -0,0 +1,81 @@ +/* + * (C) Copyright 2017 Icenowy Zheng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CPU_SUN50I_H6_H +#define _SUNXI_CPU_SUN50I_H6_H + +#define SUNXI_SRAM_A1_BASE CONFIG_SUNXI_SRAM_ADDRESS +#define SUNXI_SRAM_C_BASE 0x00028000 +#define SUNXI_SRAM_A2_BASE 0x00100000 + +#define SUNXI_DE3_BASE 0x01000000 +#define SUNXI_SS_BASE 0x01904000 +#define SUNXI_EMCE_BASE 0x01905000 + +#define SUNXI_SRAMC_BASE 0x03000000 +#define SUNXI_CCM_BASE 0x03001000 +#define SUNXI_DMA_BASE 0x03002000 +/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */ +#define SUNXI_SIDC_BASE 0x03006000 +#define SUNXI_SID_BASE 0x03006200 +#define SUNXI_TIMER_BASE 0x03009000 +#define SUNXI_PIO_BASE 0x0300B000 +#define SUNXI_PSI_BASE 0x0300C000 + +#define SUNXI_GIC400_BASE 0x03020000 +#define SUNXI_IOMMU_BASE 0x030F0000 + +#ifdef CONFIG_MACH_SUN50I_H6 +#define SUNXI_DRAM_COM_BASE 0x04002000 +#define SUNXI_DRAM_CTL0_BASE 0x04003000 +#define SUNXI_DRAM_PHY0_BASE 0x04005000 +#endif +#define SUNXI_NFC_BASE 0x04011000 +#define SUNXI_MMC0_BASE 0x04020000 +#define SUNXI_MMC1_BASE 0x04021000 +#define SUNXI_MMC2_BASE 0x04022000 +#ifdef CONFIG_MACH_SUN50I_H616 +#define SUNXI_DRAM_COM_BASE 0x047FA000 +#define SUNXI_DRAM_CTL0_BASE 0x047FB000 +#define SUNXI_DRAM_PHY0_BASE 0x04800000 +#endif + +#define SUNXI_UART0_BASE 0x05000000 +#define SUNXI_UART1_BASE 0x05000400 +#define SUNXI_UART2_BASE 0x05000800 +#define SUNXI_UART3_BASE 0x05000C00 +#define SUNXI_TWI0_BASE 0x05002000 +#define SUNXI_TWI1_BASE 0x05002400 +#define SUNXI_TWI2_BASE 0x05002800 +#define SUNXI_TWI3_BASE 0x05002C00 +#define SUNXI_SPI0_BASE 0x05010000 +#define SUNXI_SPI1_BASE 0x05011000 +#define SUNXI_GMAC_BASE 0x05020000 +#define SUNXI_USB0_BASE 0x05100000 +#define SUNXI_XHCI_BASE 0x05200000 +#define SUNXI_USB3_BASE 0x05311000 +#define SUNXI_PCIE_BASE 0x05400000 + +#define SUNXI_HDMI_BASE 0x06000000 +#define SUNXI_TCON_TOP_BASE 0x06510000 +#define SUNXI_TCON_LCD0_BASE 0x06511000 +#define SUNXI_TCON_TV0_BASE 0x06515000 + +#define SUNXI_RTC_BASE 0x07000000 +#define SUNXI_R_CPUCFG_BASE 0x07000400 +#define SUNXI_PRCM_BASE 0x07010000 +#define SUNXI_R_WDOG_BASE 0x07020400 +#define SUNXI_R_PIO_BASE 0x07022000 +#define SUNXI_R_UART_BASE 0x07080000 +#define SUNXI_R_TWI_BASE 0x07081400 + +#ifndef __ASSEMBLY__ +void sunxi_board_init(void); +void sunxi_reset(void); +int sunxi_get_sid(unsigned int *sid); +#endif + +#endif /* _SUNXI_CPU_SUN9I_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h new file mode 100644 index 000000000..9c2d11b59 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Hans de Goede + * (C) Copyright 2007-2013 + * Allwinner Technology Co., Ltd. + * Jerry Wang + */ + +#ifndef _SUNXI_CPU_SUN9I_H +#define _SUNXI_CPU_SUN9I_H + +#define REGS_AHB0_BASE 0x01C00000 +#define REGS_AHB1_BASE 0x00800000 +#define REGS_AHB2_BASE 0x03000000 +#define REGS_APB0_BASE 0x06000000 +#define REGS_APB1_BASE 0x07000000 +#define REGS_RCPUS_BASE 0x08000000 + +#define SUNXI_SRAM_D_BASE 0x08100000 + +/* AHB0 Module */ +#define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000) +#define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000) + +#define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000) +/* SID address space starts at 0x01ce000, but e-fuse is at offset 0x200 */ +#define SUNXI_SID_BASE (REGS_AHB0_BASE + 0xe200) + +#define SUNXI_MMC0_BASE (REGS_AHB0_BASE + 0x0f000) +#define SUNXI_MMC1_BASE (REGS_AHB0_BASE + 0x10000) +#define SUNXI_MMC2_BASE (REGS_AHB0_BASE + 0x11000) +#define SUNXI_MMC3_BASE (REGS_AHB0_BASE + 0x12000) +#define SUNXI_MMC_COMMON_BASE (REGS_AHB0_BASE + 0x13000) + +#define SUNXI_SPI0_BASE (REGS_AHB0_BASE + 0x1A000) +#define SUNXI_SPI1_BASE (REGS_AHB0_BASE + 0x1B000) +#define SUNXI_SPI2_BASE (REGS_AHB0_BASE + 0x1C000) +#define SUNXI_SPI3_BASE (REGS_AHB0_BASE + 0x1D000) + +#define SUNXI_GIC400_BASE (REGS_AHB0_BASE + 0x40000) +#define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000) +#define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000) + +#define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000) +#define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000) +#define SUNXI_DRAM_CTL1_BASE (REGS_AHB0_BASE + 0x64000) +#define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000) +#define SUNXI_DRAM_PHY1_BASE (REGS_AHB0_BASE + 0x66000) + +/* AHB1 Module */ +#define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000) +#define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000) +#define SUNXI_USBEHCI0_BASE (REGS_AHB1_BASE + 0x200000) +#define SUNXI_USBEHCI1_BASE (REGS_AHB1_BASE + 0x201000) +#define SUNXI_USBEHCI2_BASE (REGS_AHB1_BASE + 0x202000) + +/* AHB2 Module */ +#define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000) +#define SUNXI_DISP_SYS_BASE (REGS_AHB2_BASE + 0x010000) +#define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000) +#define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000) +#define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000) + +#define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000) +#define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000) +#define SUNXI_DE_BE2_BASE (REGS_AHB2_BASE + 0x280000) + +#define SUNXI_DE_DEU0_BASE (REGS_AHB2_BASE + 0x300000) +#define SUNXI_DE_DEU1_BASE (REGS_AHB2_BASE + 0x340000) +#define SUNXI_DE_DRC0_BASE (REGS_AHB2_BASE + 0x400000) +#define SUNXI_DE_DRC1_BASE (REGS_AHB2_BASE + 0x440000) + +#define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000) +#define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000) +#define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000) +#define SUNXI_MIPI_DSI0_BASE (REGS_AHB2_BASE + 0xC40000) +/* Also seen as SUNXI_MIPI_DSI0_DPHY_BASE 0x01ca1000 */ +#define SUNXI_MIPI_DSI0_DPHY_BASE (REGS_AHB2_BASE + 0xC40100) +#define SUNXI_HDMI_BASE (REGS_AHB2_BASE + 0xD00000) + +/* APB0 Module */ +#define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000) +#define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400) +#define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800) +#define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00) +#define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400) +#define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800) + +/* APB1 Module */ +#define SUNXI_UART0_BASE (REGS_APB1_BASE + 0x0000) +#define SUNXI_UART1_BASE (REGS_APB1_BASE + 0x0400) +#define SUNXI_UART2_BASE (REGS_APB1_BASE + 0x0800) +#define SUNXI_UART3_BASE (REGS_APB1_BASE + 0x0C00) +#define SUNXI_UART4_BASE (REGS_APB1_BASE + 0x1000) +#define SUNXI_UART5_BASE (REGS_APB1_BASE + 0x1400) +#define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800) +#define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00) +#define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000) +#define SUNXI_TWI3_BASE (REGS_APB1_BASE + 0x3400) +#define SUNXI_TWI4_BASE (REGS_APB1_BASE + 0x3800) + +/* RCPUS Module */ +#define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400) +#define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800) +#define SUNXI_R_PIO_BASE (REGS_RCPUS_BASE + 0x2c00) +#define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400) + +/* Misc. */ +#define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */ +#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) + +#ifndef __ASSEMBLY__ +void sunxi_board_init(void); +void sunxi_reset(void); +int sunxi_get_sid(unsigned int *sid); +#endif + +#endif /* _SUNXI_CPU_SUN9I_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/cpucfg.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/cpucfg.h new file mode 100644 index 000000000..4aaebe0a9 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/cpucfg.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Sunxi A31 CPUCFG register definition. + * + * (C) Copyright 2014 Hans de Goede +#include + +#ifndef __ASSEMBLY__ + +struct __packed sunxi_cpucfg_cpu { + u32 rst; /* base + 0x0 */ + u32 ctrl; /* base + 0x4 */ + u32 status; /* base + 0x8 */ + u8 res[0x34]; /* base + 0xc */ +}; + +struct __packed sunxi_cpucfg_reg { + u8 res0[0x40]; /* 0x000 */ + struct sunxi_cpucfg_cpu cpu[4]; /* 0x040 */ + u8 res1[0x44]; /* 0x140 */ + u32 gen_ctrl; /* 0x184 */ + u32 l2_status; /* 0x188 */ + u8 res2[0x4]; /* 0x18c */ + u32 event_in; /* 0x190 */ + u8 res3[0xc]; /* 0x194 */ + u32 super_standy_flag; /* 0x1a0 */ + u32 priv0; /* 0x1a4 */ + u32 priv1; /* 0x1a8 */ + u8 res4[0x4]; /* 0x1ac */ + u32 cpu1_pwr_clamp; /* 0x1b0 sun7i only */ + u32 cpu1_pwroff; /* 0x1b4 sun7i only */ + u8 res5[0x2c]; /* 0x1b8 */ + u32 dbg_ctrl1; /* 0x1e4 */ + u8 res6[0x18]; /* 0x1e8 */ + u32 idle_cnt0_low; /* 0x200 */ + u32 idle_cnt0_high; /* 0x204 */ + u32 idle_cnt0_ctrl; /* 0x208 */ + u8 res8[0x4]; /* 0x20c */ + u32 idle_cnt1_low; /* 0x210 */ + u32 idle_cnt1_high; /* 0x214 */ + u32 idle_cnt1_ctrl; /* 0x218 */ + u8 res9[0x4]; /* 0x21c */ + u32 idle_cnt2_low; /* 0x220 */ + u32 idle_cnt2_high; /* 0x224 */ + u32 idle_cnt2_ctrl; /* 0x228 */ + u8 res10[0x4]; /* 0x22c */ + u32 idle_cnt3_low; /* 0x230 */ + u32 idle_cnt3_high; /* 0x234 */ + u32 idle_cnt3_ctrl; /* 0x238 */ + u8 res11[0x4]; /* 0x23c */ + u32 idle_cnt4_low; /* 0x240 */ + u32 idle_cnt4_high; /* 0x244 */ + u32 idle_cnt4_ctrl; /* 0x248 */ + u8 res12[0x34]; /* 0x24c */ + u32 cnt64_ctrl; /* 0x280 */ + u32 cnt64_low; /* 0x284 */ + u32 cnt64_high; /* 0x288 */ +}; + +#endif /* __ASSEMBLY__ */ +#endif /* _SUNXI_CPUCFG_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/display.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/display.h new file mode 100644 index 000000000..525f9cb83 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/display.h @@ -0,0 +1,352 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Sunxi platform display controller register and constant defines + * + * (C) Copyright 2014 Hans de Goede + */ + +#ifndef _SUNXI_DISPLAY_H +#define _SUNXI_DISPLAY_H + +struct sunxi_de_fe_reg { + u32 enable; /* 0x000 */ + u32 frame_ctrl; /* 0x004 */ + u32 bypass; /* 0x008 */ + u32 algorithm_sel; /* 0x00c */ + u32 line_int_ctrl; /* 0x010 */ + u8 res0[0x0c]; /* 0x014 */ + u32 ch0_addr; /* 0x020 */ + u32 ch1_addr; /* 0x024 */ + u32 ch2_addr; /* 0x028 */ + u32 field_sequence; /* 0x02c */ + u32 ch0_offset; /* 0x030 */ + u32 ch1_offset; /* 0x034 */ + u32 ch2_offset; /* 0x038 */ + u8 res1[0x04]; /* 0x03c */ + u32 ch0_stride; /* 0x040 */ + u32 ch1_stride; /* 0x044 */ + u32 ch2_stride; /* 0x048 */ + u32 input_fmt; /* 0x04c */ + u32 ch3_addr; /* 0x050 */ + u32 ch4_addr; /* 0x054 */ + u32 ch5_addr; /* 0x058 */ + u32 output_fmt; /* 0x05c */ + u32 int_enable; /* 0x060 */ + u32 int_status; /* 0x064 */ + u32 status; /* 0x068 */ + u8 res2[0x04]; /* 0x06c */ + u32 csc_coef00; /* 0x070 */ + u32 csc_coef01; /* 0x074 */ + u32 csc_coef02; /* 0x078 */ + u32 csc_coef03; /* 0x07c */ + u32 csc_coef10; /* 0x080 */ + u32 csc_coef11; /* 0x084 */ + u32 csc_coef12; /* 0x088 */ + u32 csc_coef13; /* 0x08c */ + u32 csc_coef20; /* 0x090 */ + u32 csc_coef21; /* 0x094 */ + u32 csc_coef22; /* 0x098 */ + u32 csc_coef23; /* 0x09c */ + u32 deinterlace_ctrl; /* 0x0a0 */ + u32 deinterlace_diag; /* 0x0a4 */ + u32 deinterlace_tempdiff; /* 0x0a8 */ + u32 deinterlace_sawtooth; /* 0x0ac */ + u32 deinterlace_spatcomp; /* 0x0b0 */ + u32 deinterlace_burstlen; /* 0x0b4 */ + u32 deinterlace_preluma; /* 0x0b8 */ + u32 deinterlace_tile_addr; /* 0x0bc */ + u32 deinterlace_tile_stride; /* 0x0c0 */ + u8 res3[0x0c]; /* 0x0c4 */ + u32 wb_stride_enable; /* 0x0d0 */ + u32 ch3_stride; /* 0x0d4 */ + u32 ch4_stride; /* 0x0d8 */ + u32 ch5_stride; /* 0x0dc */ + u32 fe_3d_ctrl; /* 0x0e0 */ + u32 fe_3d_ch0_addr; /* 0x0e4 */ + u32 fe_3d_ch1_addr; /* 0x0e8 */ + u32 fe_3d_ch2_addr; /* 0x0ec */ + u32 fe_3d_ch0_offset; /* 0x0f0 */ + u32 fe_3d_ch1_offset; /* 0x0f4 */ + u32 fe_3d_ch2_offset; /* 0x0f8 */ + u8 res4[0x04]; /* 0x0fc */ + u32 ch0_insize; /* 0x100 */ + u32 ch0_outsize; /* 0x104 */ + u32 ch0_horzfact; /* 0x108 */ + u32 ch0_vertfact; /* 0x10c */ + u32 ch0_horzphase; /* 0x110 */ + u32 ch0_vertphase0; /* 0x114 */ + u32 ch0_vertphase1; /* 0x118 */ + u8 res5[0x04]; /* 0x11c */ + u32 ch0_horztapoffset0; /* 0x120 */ + u32 ch0_horztapoffset1; /* 0x124 */ + u32 ch0_verttapoffset; /* 0x128 */ + u8 res6[0xd4]; /* 0x12c */ + u32 ch1_insize; /* 0x200 */ + u32 ch1_outsize; /* 0x204 */ + u32 ch1_horzfact; /* 0x208 */ + u32 ch1_vertfact; /* 0x20c */ + u32 ch1_horzphase; /* 0x210 */ + u32 ch1_vertphase0; /* 0x214 */ + u32 ch1_vertphase1; /* 0x218 */ + u8 res7[0x04]; /* 0x21c */ + u32 ch1_horztapoffset0; /* 0x220 */ + u32 ch1_horztapoffset1; /* 0x224 */ + u32 ch1_verttapoffset; /* 0x228 */ + u8 res8[0x1d4]; /* 0x22c */ + u32 ch0_horzcoef0[32]; /* 0x400 */ + u32 ch0_horzcoef1[32]; /* 0x480 */ + u32 ch0_vertcoef[32]; /* 0x500 */ + u8 res9[0x80]; /* 0x580 */ + u32 ch1_horzcoef0[32]; /* 0x600 */ + u32 ch1_horzcoef1[32]; /* 0x680 */ + u32 ch1_vertcoef[32]; /* 0x700 */ + u8 res10[0x280]; /* 0x780 */ + u32 vpp_enable; /* 0xa00 */ + u32 vpp_dcti; /* 0xa04 */ + u32 vpp_lp1; /* 0xa08 */ + u32 vpp_lp2; /* 0xa0c */ + u32 vpp_wle; /* 0xa10 */ + u32 vpp_ble; /* 0xa14 */ +}; + +struct sunxi_de_be_reg { + u8 res0[0x800]; /* 0x000 */ + u32 mode; /* 0x800 */ + u32 backcolor; /* 0x804 */ + u32 disp_size; /* 0x808 */ + u8 res1[0x4]; /* 0x80c */ + u32 layer0_size; /* 0x810 */ + u32 layer1_size; /* 0x814 */ + u32 layer2_size; /* 0x818 */ + u32 layer3_size; /* 0x81c */ + u32 layer0_pos; /* 0x820 */ + u32 layer1_pos; /* 0x824 */ + u32 layer2_pos; /* 0x828 */ + u32 layer3_pos; /* 0x82c */ + u8 res2[0x10]; /* 0x830 */ + u32 layer0_stride; /* 0x840 */ + u32 layer1_stride; /* 0x844 */ + u32 layer2_stride; /* 0x848 */ + u32 layer3_stride; /* 0x84c */ + u32 layer0_addr_low32b; /* 0x850 */ + u32 layer1_addr_low32b; /* 0x854 */ + u32 layer2_addr_low32b; /* 0x858 */ + u32 layer3_addr_low32b; /* 0x85c */ + u32 layer0_addr_high4b; /* 0x860 */ + u32 layer1_addr_high4b; /* 0x864 */ + u32 layer2_addr_high4b; /* 0x868 */ + u32 layer3_addr_high4b; /* 0x86c */ + u32 reg_ctrl; /* 0x870 */ + u8 res3[0xc]; /* 0x874 */ + u32 color_key_max; /* 0x880 */ + u32 color_key_min; /* 0x884 */ + u32 color_key_config; /* 0x888 */ + u8 res4[0x4]; /* 0x88c */ + u32 layer0_attr0_ctrl; /* 0x890 */ + u32 layer1_attr0_ctrl; /* 0x894 */ + u32 layer2_attr0_ctrl; /* 0x898 */ + u32 layer3_attr0_ctrl; /* 0x89c */ + u32 layer0_attr1_ctrl; /* 0x8a0 */ + u32 layer1_attr1_ctrl; /* 0x8a4 */ + u32 layer2_attr1_ctrl; /* 0x8a8 */ + u32 layer3_attr1_ctrl; /* 0x8ac */ + u8 res5[0x110]; /* 0x8b0 */ + u32 output_color_ctrl; /* 0x9c0 */ + u8 res6[0xc]; /* 0x9c4 */ + u32 output_color_coef[12]; /* 0x9d0 */ +}; + +struct sunxi_hdmi_reg { + u32 version_id; /* 0x000 */ + u32 ctrl; /* 0x004 */ + u32 irq; /* 0x008 */ + u32 hpd; /* 0x00c */ + u32 video_ctrl; /* 0x010 */ + u32 video_size; /* 0x014 */ + u32 video_bp; /* 0x018 */ + u32 video_fp; /* 0x01c */ + u32 video_spw; /* 0x020 */ + u32 video_polarity; /* 0x024 */ + u8 res0[0x58]; /* 0x028 */ + u8 avi_info_frame[0x14]; /* 0x080 */ + u8 res1[0x4c]; /* 0x094 */ + u32 qcp_packet0; /* 0x0e0 */ + u32 qcp_packet1; /* 0x0e4 */ + u8 res2[0x118]; /* 0x0e8 */ + u32 pad_ctrl0; /* 0x200 */ + u32 pad_ctrl1; /* 0x204 */ + u32 pll_ctrl; /* 0x208 */ + u32 pll_dbg0; /* 0x20c */ + u32 pll_dbg1; /* 0x210 */ + u32 hpd_cec; /* 0x214 */ + u8 res3[0x28]; /* 0x218 */ + u8 vendor_info_frame[0x14]; /* 0x240 */ + u8 res4[0x9c]; /* 0x254 */ + u32 pkt_ctrl0; /* 0x2f0 */ + u32 pkt_ctrl1; /* 0x2f4 */ + u8 res5[0x8]; /* 0x2f8 */ + u32 unknown; /* 0x300 */ + u8 res6[0xc]; /* 0x304 */ + u32 audio_sample_count; /* 0x310 */ + u8 res7[0xec]; /* 0x314 */ + u32 audio_tx_fifo; /* 0x400 */ + u8 res8[0xfc]; /* 0x404 */ +#ifndef CONFIG_MACH_SUN6I + u32 ddc_ctrl; /* 0x500 */ + u32 ddc_addr; /* 0x504 */ + u32 ddc_int_mask; /* 0x508 */ + u32 ddc_int_status; /* 0x50c */ + u32 ddc_fifo_ctrl; /* 0x510 */ + u32 ddc_fifo_status; /* 0x514 */ + u32 ddc_fifo_data; /* 0x518 */ + u32 ddc_byte_count; /* 0x51c */ + u32 ddc_cmnd; /* 0x520 */ + u32 ddc_exreg; /* 0x524 */ + u32 ddc_clock; /* 0x528 */ + u8 res9[0x14]; /* 0x52c */ + u32 ddc_line_ctrl; /* 0x540 */ +#else + u32 ddc_ctrl; /* 0x500 */ + u32 ddc_exreg; /* 0x504 */ + u32 ddc_cmnd; /* 0x508 */ + u32 ddc_addr; /* 0x50c */ + u32 ddc_int_mask; /* 0x510 */ + u32 ddc_int_status; /* 0x514 */ + u32 ddc_fifo_ctrl; /* 0x518 */ + u32 ddc_fifo_status; /* 0x51c */ + u32 ddc_clock; /* 0x520 */ + u32 ddc_timeout; /* 0x524 */ + u8 res9[0x18]; /* 0x528 */ + u32 ddc_dbg; /* 0x540 */ + u8 res10[0x3c]; /* 0x544 */ + u32 ddc_fifo_data; /* 0x580 */ +#endif +}; + +/* + * DE-FE register constants. + */ +#define SUNXI_DE_FE_WIDTH(x) (((x) - 1) << 0) +#define SUNXI_DE_FE_HEIGHT(y) (((y) - 1) << 16) +#define SUNXI_DE_FE_FACTOR_INT(n) ((n) << 16) +#define SUNXI_DE_FE_ENABLE_EN (1 << 0) +#define SUNXI_DE_FE_FRAME_CTRL_REG_RDY (1 << 0) +#define SUNXI_DE_FE_FRAME_CTRL_COEF_RDY (1 << 1) +#define SUNXI_DE_FE_FRAME_CTRL_FRM_START (1 << 16) +#define SUNXI_DE_FE_BYPASS_CSC_BYPASS (1 << 1) +#define SUNXI_DE_FE_INPUT_FMT_ARGB8888 0x00000151 +#define SUNXI_DE_FE_OUTPUT_FMT_ARGB8888 0x00000002 + +/* + * DE-BE register constants. + */ +#define SUNXI_DE_BE_WIDTH(x) (((x) - 1) << 0) +#define SUNXI_DE_BE_HEIGHT(y) (((y) - 1) << 16) +#define SUNXI_DE_BE_MODE_ENABLE (1 << 0) +#define SUNXI_DE_BE_MODE_START (1 << 1) +#define SUNXI_DE_BE_MODE_DEFLICKER_ENABLE (1 << 4) +#define SUNXI_DE_BE_MODE_LAYER0_ENABLE (1 << 8) +#define SUNXI_DE_BE_MODE_INTERLACE_ENABLE (1 << 28) +#define SUNXI_DE_BE_LAYER_STRIDE(x) ((x) << 5) +#define SUNXI_DE_BE_REG_CTRL_LOAD_REGS (1 << 0) +#define SUNXI_DE_BE_LAYER_ATTR0_SRC_FE0 0x00000002 +#define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888 (0x09 << 8) +#define SUNXI_DE_BE_OUTPUT_COLOR_CTRL_ENABLE 1 + +/* + * HDMI register constants. + */ +#define SUNXI_HDMI_X(x) (((x) - 1) << 0) +#define SUNXI_HDMI_Y(y) (((y) - 1) << 16) +#define SUNXI_HDMI_CTRL_ENABLE (1 << 31) +#define SUNXI_HDMI_IRQ_STATUS_FIFO_UF (1 << 0) +#define SUNXI_HDMI_IRQ_STATUS_FIFO_OF (1 << 1) +#define SUNXI_HDMI_IRQ_STATUS_BITS 0x73 +#define SUNXI_HDMI_HPD_DETECT (1 << 0) +#define SUNXI_HDMI_VIDEO_CTRL_ENABLE (1 << 31) +#define SUNXI_HDMI_VIDEO_CTRL_HDMI (1 << 30) +#define SUNXI_HDMI_VIDEO_POL_HOR (1 << 0) +#define SUNXI_HDMI_VIDEO_POL_VER (1 << 1) +#define SUNXI_HDMI_VIDEO_POL_TX_CLK (0x3e0 << 16) +#define SUNXI_HDMI_QCP_PACKET0 3 +#define SUNXI_HDMI_QCP_PACKET1 0 + +#ifdef CONFIG_MACH_SUN6I +#define SUNXI_HDMI_PAD_CTRL0_HDP 0x7e80000f +#define SUNXI_HDMI_PAD_CTRL0_RUN 0x7e8000ff +#else +#define SUNXI_HDMI_PAD_CTRL0_HDP 0xfe800000 +#define SUNXI_HDMI_PAD_CTRL0_RUN 0xfe800000 +#endif + +#ifdef CONFIG_MACH_SUN4I +#define SUNXI_HDMI_PAD_CTRL1 0x00d8c820 +#elif defined CONFIG_MACH_SUN6I +#define SUNXI_HDMI_PAD_CTRL1 0x01ded030 +#else +#define SUNXI_HDMI_PAD_CTRL1 0x00d8c830 +#endif +#define SUNXI_HDMI_PAD_CTRL1_HALVE (1 << 6) + +#ifdef CONFIG_MACH_SUN6I +#define SUNXI_HDMI_PLL_CTRL 0xba48a308 +#define SUNXI_HDMI_PLL_CTRL_DIV(n) (((n) - 1) << 4) +#else +#define SUNXI_HDMI_PLL_CTRL 0xfa4ef708 +#define SUNXI_HDMI_PLL_CTRL_DIV(n) ((n) << 4) +#endif +#define SUNXI_HDMI_PLL_CTRL_DIV_MASK (0xf << 4) + +#define SUNXI_HDMI_PLL_DBG0_PLL3 (0 << 21) +#define SUNXI_HDMI_PLL_DBG0_PLL7 (1 << 21) + +#define SUNXI_HDMI_PKT_CTRL0 0x00000f21 +#define SUNXI_HDMI_PKT_CTRL1 0x0000000f +#define SUNXI_HDMI_UNKNOWN_INPUT_SYNC 0x08000000 + +#ifdef CONFIG_MACH_SUN6I +#define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 0) +#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE (1 << 4) +#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE (1 << 6) +#define SUNXI_HMDI_DDC_CTRL_START (1 << 27) +#define SUNXI_HMDI_DDC_CTRL_RESET (1 << 31) +#else +#define SUNXI_HMDI_DDC_CTRL_RESET (1 << 0) +/* sun4i / sun5i / sun7i do not have a separate line_ctrl reg */ +#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE 0 +#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE 0 +#define SUNXI_HMDI_DDC_CTRL_START (1 << 30) +#define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 31) +#endif + +#ifdef CONFIG_MACH_SUN6I +#define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0xa0 << 0) +#else +#define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0x50 << 0) +#endif +#define SUNXI_HMDI_DDC_ADDR_OFFSET(n) (((n) & 0xff) << 8) +#define SUNXI_HMDI_DDC_ADDR_EDDC_ADDR (0x60 << 16) +#define SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(n) ((n) << 24) + +#ifdef CONFIG_MACH_SUN6I +#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 15) +#else +#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 31) +#endif + +#define SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ 6 +#define SUNXI_HDMI_DDC_CMND_IMPLICIT_EDDC_READ 7 + +#ifdef CONFIG_MACH_SUN6I +#define SUNXI_HDMI_DDC_CLOCK 0x61 +#else +/* N = 5,M=1 Fscl= Ftmds/2/10/2^N/(M+1) */ +#define SUNXI_HDMI_DDC_CLOCK 0x0d +#endif + +#define SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE (1 << 8) +#define SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE (1 << 9) + +int sunxi_simplefb_setup(void *blob); + +#endif /* _SUNXI_DISPLAY_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/display2.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/display2.h new file mode 100644 index 000000000..7202d2756 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/display2.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Sunxi platform display controller register and constant defines + * + * (C) Copyright 2017 Jernej Skrabec + * + * Based on out of tree Linux DRM driver defines: + * Copyright (C) 2016 Jean-Francois Moine + * Copyright (c) 2016 Allwinnertech Co., Ltd. + */ + +#ifndef _SUNXI_DISPLAY2_H +#define _SUNXI_DISPLAY2_H + +/* internal clock settings */ +struct de_clk { + u32 gate_cfg; + u32 bus_cfg; + u32 rst_cfg; + u32 div_cfg; + u32 sel_cfg; +}; + +/* global control */ +struct de_glb { + u32 ctl; + u32 status; + u32 dbuff; + u32 size; +}; + +/* alpha blending */ +struct de_bld { + u32 fcolor_ctl; + struct { + u32 fcolor; + u32 insize; + u32 offset; + u32 dum; + } attr[4]; + u32 dum0[15]; + u32 route; + u32 premultiply; + u32 bkcolor; + u32 output_size; + u32 bld_mode[4]; + u32 dum1[4]; + u32 ck_ctl; + u32 ck_cfg; + u32 dum2[2]; + u32 ck_max[4]; + u32 dum3[4]; + u32 ck_min[4]; + u32 dum4[3]; + u32 out_ctl; +}; + +/* VI channel */ +struct de_vi { + struct { + u32 attr; + u32 size; + u32 coord; + u32 pitch[3]; + u32 top_laddr[3]; + u32 bot_laddr[3]; + } cfg[4]; + u32 fcolor[4]; + u32 top_haddr[3]; + u32 bot_haddr[3]; + u32 ovl_size[2]; + u32 hori[2]; + u32 vert[2]; +}; + +struct de_ui { + struct { + u32 attr; + u32 size; + u32 coord; + u32 pitch; + u32 top_laddr; + u32 bot_laddr; + u32 fcolor; + u32 dum; + } cfg[4]; + u32 top_haddr; + u32 bot_haddr; + u32 ovl_size; +}; + +struct de_csc { + u32 csc_ctl; + u8 res[0xc]; + u32 coef11; + u32 coef12; + u32 coef13; + u32 coef14; + u32 coef21; + u32 coef22; + u32 coef23; + u32 coef24; + u32 coef31; + u32 coef32; + u32 coef33; + u32 coef34; +}; + +/* + * DE register constants. + */ +#define SUNXI_DE2_MUX0_BASE (SUNXI_DE2_BASE + 0x100000) +#define SUNXI_DE2_MUX1_BASE (SUNXI_DE2_BASE + 0x200000) + +#define SUNXI_DE2_MUX_GLB_REGS 0x00000 +#define SUNXI_DE2_MUX_BLD_REGS 0x01000 +#define SUNXI_DE2_MUX_CHAN_REGS 0x02000 +#define SUNXI_DE2_MUX_CHAN_SZ 0x1000 +#define SUNXI_DE2_MUX_VSU_REGS 0x20000 +#define SUNXI_DE2_MUX_GSU1_REGS 0x30000 +#define SUNXI_DE2_MUX_GSU2_REGS 0x40000 +#define SUNXI_DE2_MUX_GSU3_REGS 0x50000 +#define SUNXI_DE2_MUX_FCE_REGS 0xa0000 +#define SUNXI_DE2_MUX_BWS_REGS 0xa2000 +#define SUNXI_DE2_MUX_LTI_REGS 0xa4000 +#define SUNXI_DE2_MUX_PEAK_REGS 0xa6000 +#define SUNXI_DE2_MUX_ASE_REGS 0xa8000 +#define SUNXI_DE2_MUX_FCC_REGS 0xaa000 +#define SUNXI_DE2_MUX_DCSC_REGS 0xb0000 + +#define SUNXI_DE2_FORMAT_XRGB_8888 4 +#define SUNXI_DE2_FORMAT_RGB_565 10 + +#define SUNXI_DE2_MUX_GLB_CTL_EN (1 << 0) +#define SUNXI_DE2_UI_CFG_ATTR_EN (1 << 0) +#define SUNXI_DE2_UI_CFG_ATTR_FMT(f) ((f & 0xf) << 8) + +#define SUNXI_DE2_WH(w, h) (((h - 1) << 16) | (w - 1)) + +#endif /* _SUNXI_DISPLAY2_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/dma.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dma.h new file mode 100644 index 000000000..bd4c84f00 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dma.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Roy Spliet + */ + +#ifndef _SUNXI_DMA_H +#define _SUNXI_DMA_H + +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) +#include +#else +#error "DMA definition not available for this architecture" +#endif + +#endif /* _SUNXI_DMA_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/dma_sun4i.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dma_sun4i.h new file mode 100644 index 000000000..309dc4f7c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dma_sun4i.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Roy Spliet + */ + +#ifndef _SUNXI_DMA_SUN4I_H +#define _SUNXI_DMA_SUN4I_H + +struct sunxi_dma_cfg +{ + u32 ctl; /* 0x00 Control */ + u32 src_addr; /* 0x04 Source address */ + u32 dst_addr; /* 0x08 Destination address */ + u32 bc; /* 0x0C Byte counter */ + u32 res0[2]; + u32 ddma_para; /* 0x18 extra parameter (dedicated DMA only) */ + u32 res1; +}; + +struct sunxi_dma +{ + u32 irq_en; /* 0x000 IRQ enable */ + u32 irq_pend; /* 0x004 IRQ pending */ + u32 auto_gate; /* 0x008 auto gating */ + u32 res0[61]; + struct sunxi_dma_cfg ndma[8]; /* 0x100 Normal DMA */ + u32 res1[64]; + struct sunxi_dma_cfg ddma[8]; /* 0x300 Dedicated DMA */ +}; + +enum ddma_drq_type { + DDMA_DST_DRQ_SRAM = 0, + DDMA_SRC_DRQ_SRAM = 0, + DDMA_DST_DRQ_SDRAM = 1, + DDMA_SRC_DRQ_SDRAM = 1, + DDMA_DST_DRQ_PATA = 2, + DDMA_SRC_DRQ_PATA = 2, + DDMA_DST_DRQ_NAND = 3, + DDMA_SRC_DRQ_NAND = 3, + DDMA_DST_DRQ_USB0 = 4, + DDMA_SRC_DRQ_USB0 = 4, + DDMA_DST_DRQ_ETHERNET_MAC_TX = 6, + DDMA_SRC_DRQ_ETHERNET_MAC_RX = 7, + DDMA_DST_DRQ_SPI1_TX = 8, + DDMA_SRC_DRQ_SPI1_RX = 9, + DDMA_DST_DRQ_SECURITY_SYS_TX = 10, + DDMA_SRC_DRQ_SECURITY_SYS_RX = 11, + DDMA_DST_DRQ_TCON0 = 14, + DDMA_DST_DRQ_TCON1 = 15, + DDMA_DST_DRQ_MSC = 23, + DDMA_SRC_DRQ_MSC = 23, + DDMA_DST_DRQ_SPI0_TX = 26, + DDMA_SRC_DRQ_SPI0_RX = 27, + DDMA_DST_DRQ_SPI2_TX = 28, + DDMA_SRC_DRQ_SPI2_RX = 29, + DDMA_DST_DRQ_SPI3_TX = 30, + DDMA_SRC_DRQ_SPI3_RX = 31, +}; + +#define SUNXI_DMA_CTL_SRC_DRQ(a) ((a) & 0x1f) +#define SUNXI_DMA_CTL_MODE_IO (1 << 5) +#define SUNXI_DMA_CTL_SRC_DATA_WIDTH_32 (2 << 9) +#define SUNXI_DMA_CTL_DST_DRQ(a) (((a) & 0x1f) << 16) +#define SUNXI_DMA_CTL_DST_DATA_WIDTH_32 (2 << 25) +#define SUNXI_DMA_CTL_TRIGGER (1 << 31) + +#endif /* _SUNXI_DMA_SUN4I_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram.h new file mode 100644 index 000000000..c3b3e1f51 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Berg Xing + * Tom Cubie + * + * Sunxi platform dram register definition. + */ + +#ifndef _SUNXI_DRAM_H +#define _SUNXI_DRAM_H + +#include +#include + +/* dram regs definition */ +#if defined(CONFIG_MACH_SUN6I) +#include +#elif defined(CONFIG_MACH_SUN8I_A23) +#include +#elif defined(CONFIG_MACH_SUN8I_A33) +#include +#elif defined(CONFIG_MACH_SUN8I_A83T) +#include +#elif defined(CONFIG_SUNXI_DRAM_DW) +#include +#elif defined(CONFIG_MACH_SUN9I) +#include +#elif defined(CONFIG_MACH_SUN50I_H6) +#include +#elif defined(CONFIG_MACH_SUN50I_H616) +#include +#else +#include +#endif + +unsigned long sunxi_dram_init(void); +void mctl_await_completion(u32 *reg, u32 mask, u32 val); +bool mctl_mem_matches(u32 offset); + +#endif /* _SUNXI_DRAM_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun4i.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun4i.h new file mode 100644 index 000000000..69c6600e9 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun4i.h @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Berg Xing + * Tom Cubie + * + * Sunxi platform dram register definition. + */ + +#ifndef _SUNXI_DRAM_SUN4I_H +#define _SUNXI_DRAM_SUN4I_H + +struct sunxi_dram_reg { + u32 ccr; /* 0x00 controller configuration register */ + u32 dcr; /* 0x04 dram configuration register */ + u32 iocr; /* 0x08 i/o configuration register */ + u32 csr; /* 0x0c controller status register */ + u32 drr; /* 0x10 dram refresh register */ + u32 tpr0; /* 0x14 dram timing parameters register 0 */ + u32 tpr1; /* 0x18 dram timing parameters register 1 */ + u32 tpr2; /* 0x1c dram timing parameters register 2 */ + u32 gdllcr; /* 0x20 global dll control register */ + u8 res0[0x28]; + u32 rslr0; /* 0x4c rank system latency register */ + u32 rslr1; /* 0x50 rank system latency register */ + u8 res1[0x8]; + u32 rdgr0; /* 0x5c rank dqs gating register */ + u32 rdgr1; /* 0x60 rank dqs gating register */ + u8 res2[0x34]; + u32 odtcr; /* 0x98 odt configuration register */ + u32 dtr0; /* 0x9c data training register 0 */ + u32 dtr1; /* 0xa0 data training register 1 */ + u32 dtar; /* 0xa4 data training address register */ + u32 zqcr0; /* 0xa8 zq control register 0 */ + u32 zqcr1; /* 0xac zq control register 1 */ + u32 zqsr; /* 0xb0 zq status register */ + u32 idcr; /* 0xb4 initializaton delay configure reg */ + u8 res3[0x138]; + u32 mr; /* 0x1f0 mode register */ + u32 emr; /* 0x1f4 extended mode register */ + u32 emr2; /* 0x1f8 extended mode register */ + u32 emr3; /* 0x1fc extended mode register */ + u32 dllctr; /* 0x200 dll control register */ + u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */ + /* 0x208 dll control register 1(byte 1) */ + /* 0x20c dll control register 2(byte 2) */ + /* 0x210 dll control register 3(byte 3) */ + /* 0x214 dll control register 4(byte 4) */ + u32 dqtr0; /* 0x218 dq timing register */ + u32 dqtr1; /* 0x21c dq timing register */ + u32 dqtr2; /* 0x220 dq timing register */ + u32 dqtr3; /* 0x224 dq timing register */ + u32 dqstr; /* 0x228 dqs timing register */ + u32 dqsbtr; /* 0x22c dqsb timing register */ + u32 mcr; /* 0x230 mode configure register */ + u8 res[0x8]; + u32 ppwrsctl; /* 0x23c pad power save control */ + u32 apr; /* 0x240 arbiter period register */ + u32 pldtr; /* 0x244 priority level data threshold reg */ + u8 res5[0x8]; + u32 hpcr[32]; /* 0x250 host port configure register */ + u8 res6[0x10]; + u32 csel; /* 0x2e0 controller select register */ +}; + +struct dram_para { + u32 clock; + u32 mbus_clock; + u32 type; + u32 rank_num; + u32 density; + u32 io_width; + u32 bus_width; + u32 cas; + u32 zq; + u32 odt_en; + u32 size; /* For compat with dram.c files from u-boot-sunxi, unused */ + u32 tpr0; + u32 tpr1; + u32 tpr2; + u32 tpr3; + u32 tpr4; + u32 tpr5; + u32 emr1; + u32 emr2; + u32 emr3; + u32 dqs_gating_delay; + u32 active_windowing; +}; + +#define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5) +#define DRAM_CCR_DQS_GATE (0x1 << 14) +#define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17) +#define DRAM_CCR_ITM_OFF (0x1 << 28) +#define DRAM_CCR_DATA_TRAINING (0x1 << 30) +#define DRAM_CCR_INIT (0x1 << 31) + +#define DRAM_MEMORY_TYPE_DDR1 1 +#define DRAM_MEMORY_TYPE_DDR2 2 +#define DRAM_MEMORY_TYPE_DDR3 3 +#define DRAM_MEMORY_TYPE_LPDDR2 4 +#define DRAM_MEMORY_TYPE_LPDDR 5 +#define DRAM_DCR_TYPE (0x1 << 0) +#define DRAM_DCR_TYPE_DDR2 0x0 +#define DRAM_DCR_TYPE_DDR3 0x1 +#define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1) +#define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3) +#define DRAM_DCR_IO_WIDTH_8BIT 0x0 +#define DRAM_DCR_IO_WIDTH_16BIT 0x1 +#define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3) +#define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7) +#define DRAM_DCR_CHIP_DENSITY_256M 0x0 +#define DRAM_DCR_CHIP_DENSITY_512M 0x1 +#define DRAM_DCR_CHIP_DENSITY_1024M 0x2 +#define DRAM_DCR_CHIP_DENSITY_2048M 0x3 +#define DRAM_DCR_CHIP_DENSITY_4096M 0x4 +#define DRAM_DCR_CHIP_DENSITY_8192M 0x5 +#define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6) +#define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7) +#define DRAM_DCR_BUS_WIDTH_32BIT 0x3 +#define DRAM_DCR_BUS_WIDTH_16BIT 0x1 +#define DRAM_DCR_BUS_WIDTH_8BIT 0x0 +#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10) +#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3) +#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12) +#define DRAM_DCR_MODE(n) (((n) & 0x3) << 13) +#define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3) +#define DRAM_DCR_MODE_SEQ 0x0 +#define DRAM_DCR_MODE_INTERLEAVE 0x1 + +#define DRAM_CSR_DTERR (0x1 << 20) +#define DRAM_CSR_DTIERR (0x1 << 21) +#define DRAM_CSR_FAILED (DRAM_CSR_DTERR | DRAM_CSR_DTIERR) + +#define DRAM_DRR_TRFC(n) ((n) & 0xff) +#define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8) +#define DRAM_DRR_BURST(n) ((((n) - 1) & 0xf) << 24) + +#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0) +#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3) +#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2) +#define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3) +#define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4) +#define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3) +#define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6) +#define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3) +#define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8) +#define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7) +#define DRAM_MCR_MODE_ADDR_IN (0x1 << 11) +#define DRAM_MCR_RESET (0x1 << 12) +#define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13) +#define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3) +#define DRAM_MCR_DCLK_OUT (0x1 << 16) + +#define DRAM_DLLCR_NRESET (0x1 << 30) +#define DRAM_DLLCR_DISABLE (0x1 << 31) + +#define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20) +#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff) +#define DRAM_ZQCR0_ZCAL (1 << 31) /* Starts ZQ calibration when set to 1 */ +#define DRAM_ZQCR0_ZDEN (1 << 28) /* Uses ZDATA instead of doing calibration */ + +#define DRAM_ZQSR_ZDONE (1 << 31) /* ZQ calibration completion flag */ + +#define DRAM_IOCR_ODT_EN ((3 << 30) | (3 << 0)) + +#define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0) +#define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7) +#define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4) +#define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7) +#define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9) +#define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7) +#define DRAM_MR_POWER_DOWN (0x1 << 12) + +#define DRAM_CSEL_MAGIC 0x16237495 + +unsigned long dramc_init(struct dram_para *para); + +#endif /* _SUNXI_DRAM_SUN4I_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h new file mode 100644 index 000000000..be02655cd --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h @@ -0,0 +1,336 @@ +/* + * H6 dram controller register and constant defines + * + * (C) Copyright 2017 Icenowy Zheng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_DRAM_SUN50I_H6_H +#define _SUNXI_DRAM_SUN50I_H6_H + +#include +#ifndef __ASSEMBLY__ +#include +#endif + +enum sunxi_dram_type { + SUNXI_DRAM_TYPE_DDR3 = 3, + SUNXI_DRAM_TYPE_DDR4, + SUNXI_DRAM_TYPE_LPDDR2 = 6, + SUNXI_DRAM_TYPE_LPDDR3, +}; + +static inline bool sunxi_dram_is_lpddr(int type) +{ + return type >= SUNXI_DRAM_TYPE_LPDDR2; +} + +/* + * The following information is mainly retrieved by disassembly and some FPGA + * test code of sun50iw3 platform. + */ +struct sunxi_mctl_com_reg { + u32 cr; /* 0x000 control register */ + u8 reserved_0x004[4]; /* 0x004 */ + u32 unk_0x008; /* 0x008 */ + u32 tmr; /* 0x00c timer register */ + u8 reserved_0x010[4]; /* 0x010 */ + u32 unk_0x014; /* 0x014 */ + u8 reserved_0x018[8]; /* 0x018 */ + u32 maer0; /* 0x020 master enable register 0 */ + u32 maer1; /* 0x024 master enable register 1 */ + u32 maer2; /* 0x028 master enable register 2 */ + u8 reserved_0x02c[468]; /* 0x02c */ + u32 bwcr; /* 0x200 bandwidth control register */ + u8 reserved_0x204[12]; /* 0x204 */ + /* + * The last master configured by BSP libdram is at 0x49x, so the + * size of this struct array is set to 41 (0x29) now. + */ + struct { + u32 cfg0; /* 0x0 */ + u32 cfg1; /* 0x4 */ + u8 reserved_0x8[8]; /* 0x8 */ + } master[41]; /* 0x210 + index * 0x10 */ +}; +check_member(sunxi_mctl_com_reg, master[40].reserved_0x8, 0x498); + +/* + * The following register information are retrieved from some similar DRAM + * controllers, including the DRAM controllers in Allwinner A23/A80 SoCs, + * Rockchip RK3328 SoC, NXP i.MX7 SoCs and Xilinx Zynq UltraScale+ SoCs. + * + * The DRAM controller in Allwinner A23/A80 SoCs and NXP i.MX7 SoCs seems + * to be older than the one in Allwinner H6, as the DRAMTMG9 register + * is missing in these SoCs. (From the product specifications of these + * SoCs they're not capable of DDR4) + * + * Information sources: + * - dram_sun9i.h and dram_sun8i_a23.h in the same directory. + * - sdram_rk3328.h from the RK3328 TPL DRAM patchset + * - i.MX 7Solo Applications Processor Reference Manual (IMX7SRM) + * - Zynq UltraScale+ MPSoC Register Reference (UG1087) + */ +struct sunxi_mctl_ctl_reg { + u32 mstr; /* 0x000 */ + u32 statr; /* 0x004 unused */ + u32 mstr1; /* 0x008 unused */ + u32 unk_0x00c; /* 0x00c */ + u32 mrctrl0; /* 0x010 unused */ + u32 mrctrl1; /* 0x014 unused */ + u32 mrstatr; /* 0x018 unused */ + u32 mrctrl2; /* 0x01c unused */ + u32 derateen; /* 0x020 unused */ + u32 derateint; /* 0x024 unused */ + u8 reserved_0x028[8]; /* 0x028 */ + u32 pwrctl; /* 0x030 unused */ + u32 pwrtmg; /* 0x034 unused */ + u32 hwlpctl; /* 0x038 unused */ + u8 reserved_0x03c[20]; /* 0x03c */ + u32 rfshctl0; /* 0x050 unused */ + u32 rfshctl1; /* 0x054 unused */ + u8 reserved_0x058[8]; /* 0x05c */ + u32 rfshctl3; /* 0x060 */ + u32 rfshtmg; /* 0x064 */ + u8 reserved_0x068[104]; /* 0x068 reserved for ECC&CRC (from ZynqMP) */ + u32 init[8]; /* 0x0d0 */ + u32 dimmctl; /* 0x0f0 unused */ + u32 rankctl; /* 0x0f4 */ + u8 reserved_0x0f8[8]; /* 0x0f8 */ + u32 dramtmg[17]; /* 0x100 */ + u8 reserved_0x144[60]; /* 0x144 */ + u32 zqctl[3]; /* 0x180 */ + u32 zqstat; /* 0x18c unused */ + u32 dfitmg0; /* 0x190 */ + u32 dfitmg1; /* 0x194 */ + u32 dfilpcfg[2]; /* 0x198 unused */ + u32 dfiupd[3]; /* 0x1a0 */ + u32 reserved_0x1ac; /* 0x1ac */ + u32 dfimisc; /* 0x1b0 */ + u32 dfitmg2; /* 0x1b4 unused, may not exist */ + u8 reserved_0x1b8[8]; /* 0x1b8 */ + u32 dbictl; /* 0x1c0 */ + u8 reserved_0x1c4[60]; /* 0x1c4 */ + u32 addrmap[12]; /* 0x200 */ + u8 reserved_0x230[16]; /* 0x230 */ + u32 odtcfg; /* 0x240 */ + u32 odtmap; /* 0x244 */ + u8 reserved_0x248[8]; /* 0x248 */ + u32 sched[2]; /* 0x250 */ + u8 reserved_0x258[180]; /* 0x258 */ + u32 dbgcmd; /* 0x30c unused */ + u32 dbgstat; /* 0x310 unused */ + u8 reserved_0x314[12]; /* 0x314 */ + u32 swctl; /* 0x320 */ + u32 swstat; /* 0x324 */ +}; +check_member(sunxi_mctl_ctl_reg, swstat, 0x324); + +#define MSTR_DEVICETYPE_DDR3 BIT(0) +#define MSTR_DEVICETYPE_LPDDR2 BIT(2) +#define MSTR_DEVICETYPE_LPDDR3 BIT(3) +#define MSTR_DEVICETYPE_DDR4 BIT(4) +#define MSTR_DEVICETYPE_MASK GENMASK(5, 0) +#define MSTR_2TMODE BIT(10) +#define MSTR_BUSWIDTH_FULL (0 << 12) +#define MSTR_BUSWIDTH_HALF (1 << 12) +#define MSTR_ACTIVE_RANKS(x) (((x == 2) ? 3 : 1) << 24) +#define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16) + +/* + * The following register information is based on Zynq UltraScale+ + * MPSoC Register Reference, as it's the currently only known + * DDR PHY similar to the one used in H6; however although the + * map is similar, the bit fields definitions are different. + * + * Other DesignWare DDR PHY's have similar register names, but the + * offset and definitions are both different. + */ +struct sunxi_mctl_phy_reg { + u32 ver; /* 0x000 guess based on similar PHYs */ + u32 pir; /* 0x004 */ + u8 reserved_0x008[8]; /* 0x008 */ + /* + * The ZynqMP manual didn't document PGCR1, however this register + * exists on H6 and referenced by libdram. + */ + u32 pgcr[8]; /* 0x010 */ + /* + * By comparing the hardware and the ZynqMP manual, the PGSR seems + * to start at 0x34 on H6. + */ + u8 reserved_0x030[4]; /* 0x030 */ + u32 pgsr[3]; /* 0x034 */ + u32 ptr[7]; /* 0x040 */ + /* + * According to ZynqMP reference there's PLLCR0~6 in this area, + * but they're tagged "Type B PLL Only" and H6 seems to have + * no them. + * 0x080 is not present in ZynqMP reference but it seems to be + * present on H6. + */ + u8 reserved_0x05c[36]; /* 0x05c */ + u32 unk_0x080; /* 0x080 */ + u8 reserved_0x084[4]; /* 0x084 */ + u32 dxccr; /* 0x088 */ + u8 reserved_0x08c[4]; /* 0x08c */ + u32 dsgcr; /* 0x090 */ + u8 reserved_0x094[4]; /* 0x094 */ + u32 odtcr; /* 0x098 */ + u8 reserved_0x09c[4]; /* 0x09c */ + u32 aacr; /* 0x0a0 */ + u8 reserved_0x0a4[32]; /* 0x0a4 */ + u32 gpr1; /* 0x0c4 */ + u8 reserved_0x0c8[56]; /* 0x0c8 */ + u32 dcr; /* 0x100 */ + u8 reserved_0x104[12]; /* 0x104 */ + u32 dtpr[7]; /* 0x110 */ + u8 reserved_0x12c[20]; /* 0x12c */ + u32 rdimmgcr[3]; /* 0x140 */ + u8 reserved_0x14c[4]; /* 0x14c */ + u32 rdimmcr[5]; /* 0x150 */ + u8 reserved_0x164[4]; /* 0x164 */ + u32 schcr[2]; /* 0x168 */ + u8 reserved_0x170[16]; /* 0x170 */ + /* + * The ZynqMP manual documents MR0~7, 11~14 and 22. + */ + u32 mr[23]; /* 0x180 */ + u8 reserved_0x1dc[36]; /* 0x1dc */ + u32 dtcr[2]; /* 0x200 */ + u32 dtar[3]; /* 0x208 */ + u8 reserved_0x214[4]; /* 0x214 */ + u32 dtdr[2]; /* 0x218 */ + u8 reserved_0x220[16]; /* 0x220 */ + u32 dtedr0; /* 0x230 */ + u32 dtedr1; /* 0x234 */ + u32 dtedr2; /* 0x238 */ + u32 vtdr; /* 0x23c */ + u32 catr[2]; /* 0x240 */ + u8 reserved_0x248[8]; + u32 dqsdr[3]; /* 0x250 */ + u32 dtedr3; /* 0x25c */ + u8 reserved_0x260[160]; /* 0x260 */ + u32 dcuar; /* 0x300 */ + u32 dcudr; /* 0x304 */ + u32 dcurr; /* 0x308 */ + u32 dculr; /* 0x30c */ + u32 dcugcr; /* 0x310 */ + u32 dcutpr; /* 0x314 */ + u32 dcusr[2]; /* 0x318 */ + u8 reserved_0x320[444]; /* 0x320 */ + u32 rankidr; /* 0x4dc */ + u32 riocr[6]; /* 0x4e0 */ + u8 reserved_0x4f8[8]; /* 0x4f8 */ + u32 aciocr[6]; /* 0x500 */ + u8 reserved_0x518[8]; /* 0x518 */ + u32 iovcr[2]; /* 0x520 */ + u32 vtcr[2]; /* 0x528 */ + u8 reserved_0x530[16]; /* 0x530 */ + u32 acbdlr[17]; /* 0x540 */ + u32 aclcdlr; /* 0x584 */ + u8 reserved_0x588[24]; /* 0x588 */ + u32 acmdlr[2]; /* 0x5a0 */ + u8 reserved_0x5a8[216]; /* 0x5a8 */ + struct { + u32 zqcr; /* 0x00 only the first one valid */ + u32 zqpr[2]; /* 0x04 */ + u32 zqdr[2]; /* 0x0c */ + u32 zqor[2]; /* 0x14 */ + u32 zqsr; /* 0x1c */ + } zq[2]; /* 0x680, 0x6a0 */ + u8 reserved_0x6c0[64]; /* 0x6c0 */ + struct { + u32 gcr[7]; /* 0x00 */ + u8 reserved_0x1c[36]; /* 0x1c */ + u32 bdlr0; /* 0x40 */ + u32 bdlr1; /* 0x44 */ + u32 bdlr2; /* 0x48 */ + u8 reserved_0x4c[4]; /* 0x4c */ + u32 bdlr3; /* 0x50 */ + u32 bdlr4; /* 0x54 */ + u32 bdlr5; /* 0x58 */ + u8 reserved_0x5c[4]; /* 0x5c */ + u32 bdlr6; /* 0x60 */ + u8 reserved_0x64[28]; /* 0x64 */ + u32 lcdlr[6]; /* 0x80 */ + u8 reserved_0x98[8]; /* 0x98 */ + u32 mdlr[2]; /* 0xa0 */ + u8 reserved_0xa8[24]; /* 0xa8 */ + u32 gtr0; /* 0xc0 */ + u8 reserved_0xc4[12]; /* 0xc4 */ + /* + * DXnRSR0 is not documented in ZynqMP manual but + * it's used in libdram. + */ + u32 rsr[4]; /* 0xd0 */ + u32 gsr[4]; /* 0xe0 */ + u8 reserved_0xf0[16]; /* 0xf0 */ + } dx[4]; /* 0x700, 0x800, 0x900, 0xa00 */ +}; +check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0); + +#define PIR_INIT BIT(0) +#define PIR_ZCAL BIT(1) +#define PIR_CA BIT(2) +#define PIR_PLLINIT BIT(4) +#define PIR_DCAL BIT(5) +#define PIR_PHYRST BIT(6) +#define PIR_DRAMRST BIT(7) +#define PIR_DRAMINIT BIT(8) +#define PIR_WL BIT(9) +#define PIR_QSGATE BIT(10) +#define PIR_WLADJ BIT(11) +#define PIR_RDDSKW BIT(12) +#define PIR_WRDSKW BIT(13) +#define PIR_RDEYE BIT(14) +#define PIR_WREYE BIT(15) +#define PIR_VREF BIT(17) +#define PIR_CTLDINIT BIT(18) +#define PIR_DQS2DQ BIT(20) +#define PIR_DCALPSE BIT(29) +#define PIR_ZCALBYP BIT(30) + +#define DCR_LPDDR3 (1 << 0) +#define DCR_DDR3 (3 << 0) +#define DCR_DDR4 (4 << 0) +#define DCR_DDR8BANK BIT(3) +#define DCR_DDR2T BIT(28) + +/* + * The delay parameters allow to allegedly specify delay times of some + * unknown unit for each individual bit trace in each of the four data bytes + * the 32-bit wide access consists of. Also three control signals can be + * adjusted individually. + */ +#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) +/* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable and DQSN */ +#define WR_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 4) +/* + * The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable, DQSN, + * Termination and Power down + */ +#define RD_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 6) +struct dram_para { + u32 clk; + enum sunxi_dram_type type; + u8 cols; + u8 rows; + u8 ranks; + u8 bus_full_width; + const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE]; + const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; +}; + + +static inline int ns_to_t(int nanoseconds) +{ + const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; + + return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); +} + +void mctl_set_timing_params(struct dram_para *para); + +#endif /* _SUNXI_DRAM_SUN50I_H6_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h new file mode 100644 index 000000000..134679d55 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h @@ -0,0 +1,159 @@ +/* + * H616 dram controller register and constant defines + * + * (C) Copyright 2020 Jernej Skrabec + * + * Based on H6 one, which is: + * (C) Copyright 2017 Icenowy Zheng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_DRAM_SUN50I_H616_H +#define _SUNXI_DRAM_SUN50I_H616_H + +#include +#ifndef __ASSEMBLY__ +#include +#endif + +enum sunxi_dram_type { + SUNXI_DRAM_TYPE_DDR3 = 3, + SUNXI_DRAM_TYPE_DDR4, + SUNXI_DRAM_TYPE_LPDDR3 = 7, + SUNXI_DRAM_TYPE_LPDDR4 +}; + +/* MBUS part is largely the same as in H6, except for one special register */ +struct sunxi_mctl_com_reg { + u32 cr; /* 0x000 control register */ + u8 reserved_0x004[4]; /* 0x004 */ + u32 unk_0x008; /* 0x008 */ + u32 tmr; /* 0x00c timer register */ + u8 reserved_0x010[4]; /* 0x010 */ + u32 unk_0x014; /* 0x014 */ + u8 reserved_0x018[8]; /* 0x018 */ + u32 maer0; /* 0x020 master enable register 0 */ + u32 maer1; /* 0x024 master enable register 1 */ + u32 maer2; /* 0x028 master enable register 2 */ + u8 reserved_0x02c[468]; /* 0x02c */ + u32 bwcr; /* 0x200 bandwidth control register */ + u8 reserved_0x204[12]; /* 0x204 */ + /* + * The last master configured by BSP libdram is at 0x49x, so the + * size of this struct array is set to 41 (0x29) now. + */ + struct { + u32 cfg0; /* 0x0 */ + u32 cfg1; /* 0x4 */ + u8 reserved_0x8[8]; /* 0x8 */ + } master[41]; /* 0x210 + index * 0x10 */ + u8 reserved_0x4a0[96]; /* 0x4a0 */ + u32 unk_0x500; /* 0x500 */ +}; +check_member(sunxi_mctl_com_reg, unk_0x500, 0x500); + +/* + * Controller registers seems to be the same or at least very similar + * to those in H6. + */ +struct sunxi_mctl_ctl_reg { + u32 mstr; /* 0x000 */ + u32 statr; /* 0x004 unused */ + u32 mstr1; /* 0x008 unused */ + u32 clken; /* 0x00c */ + u32 mrctrl0; /* 0x010 unused */ + u32 mrctrl1; /* 0x014 unused */ + u32 mrstatr; /* 0x018 unused */ + u32 mrctrl2; /* 0x01c unused */ + u32 derateen; /* 0x020 unused */ + u32 derateint; /* 0x024 unused */ + u8 reserved_0x028[8]; /* 0x028 */ + u32 pwrctl; /* 0x030 unused */ + u32 pwrtmg; /* 0x034 unused */ + u32 hwlpctl; /* 0x038 unused */ + u8 reserved_0x03c[20]; /* 0x03c */ + u32 rfshctl0; /* 0x050 unused */ + u32 rfshctl1; /* 0x054 unused */ + u8 reserved_0x058[8]; /* 0x05c */ + u32 rfshctl3; /* 0x060 */ + u32 rfshtmg; /* 0x064 */ + u8 reserved_0x068[104]; /* 0x068 */ + u32 init[8]; /* 0x0d0 */ + u32 dimmctl; /* 0x0f0 unused */ + u32 rankctl; /* 0x0f4 */ + u8 reserved_0x0f8[8]; /* 0x0f8 */ + u32 dramtmg[17]; /* 0x100 */ + u8 reserved_0x144[60]; /* 0x144 */ + u32 zqctl[3]; /* 0x180 */ + u32 zqstat; /* 0x18c unused */ + u32 dfitmg0; /* 0x190 */ + u32 dfitmg1; /* 0x194 */ + u32 dfilpcfg[2]; /* 0x198 unused */ + u32 dfiupd[3]; /* 0x1a0 */ + u32 reserved_0x1ac; /* 0x1ac */ + u32 dfimisc; /* 0x1b0 */ + u32 dfitmg2; /* 0x1b4 unused */ + u32 dfitmg3; /* 0x1b8 unused */ + u32 dfistat; /* 0x1bc */ + u32 dbictl; /* 0x1c0 */ + u8 reserved_0x1c4[60]; /* 0x1c4 */ + u32 addrmap[12]; /* 0x200 */ + u8 reserved_0x230[16]; /* 0x230 */ + u32 odtcfg; /* 0x240 */ + u32 odtmap; /* 0x244 */ + u8 reserved_0x248[8]; /* 0x248 */ + u32 sched[2]; /* 0x250 */ + u8 reserved_0x258[180]; /* 0x258 */ + u32 dbgcmd; /* 0x30c unused */ + u32 dbgstat; /* 0x310 unused */ + u8 reserved_0x314[12]; /* 0x314 */ + u32 swctl; /* 0x320 */ + u32 swstat; /* 0x324 */ + u8 reserved_0x328[7768];/* 0x328 */ + u32 unk_0x2180; /* 0x2180 */ + u8 reserved_0x2184[188];/* 0x2184 */ + u32 unk_0x2240; /* 0x2240 */ + u8 reserved_0x2244[3900];/* 0x2244 */ + u32 unk_0x3180; /* 0x3180 */ + u8 reserved_0x3184[188];/* 0x3184 */ + u32 unk_0x3240; /* 0x3240 */ + u8 reserved_0x3244[3900];/* 0x3244 */ + u32 unk_0x4180; /* 0x4180 */ + u8 reserved_0x4184[188];/* 0x4184 */ + u32 unk_0x4240; /* 0x4240 */ +}; +check_member(sunxi_mctl_ctl_reg, swstat, 0x324); +check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240); + +#define MSTR_DEVICETYPE_DDR3 BIT(0) +#define MSTR_DEVICETYPE_LPDDR2 BIT(2) +#define MSTR_DEVICETYPE_LPDDR3 BIT(3) +#define MSTR_DEVICETYPE_DDR4 BIT(4) +#define MSTR_DEVICETYPE_MASK GENMASK(5, 0) +#define MSTR_2TMODE BIT(10) +#define MSTR_BUSWIDTH_FULL (0 << 12) +#define MSTR_BUSWIDTH_HALF (1 << 12) +#define MSTR_ACTIVE_RANKS(x) (((x == 2) ? 3 : 1) << 24) +#define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16) + +struct dram_para { + u32 clk; + enum sunxi_dram_type type; + u8 cols; + u8 rows; + u8 ranks; + u8 bus_full_width; +}; + + +static inline int ns_to_t(int nanoseconds) +{ + const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; + + return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); +} + +void mctl_set_timing_params(struct dram_para *para); + +#endif /* _SUNXI_DRAM_SUN50I_H616_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun6i.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun6i.h new file mode 100644 index 000000000..b66d58cd7 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun6i.h @@ -0,0 +1,362 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Sun6i platform dram controller register and constant defines + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Berg Xing + * Tom Cubie + * + * (C) Copyright 2014 Hans de Goede + */ + +#ifndef _SUNXI_DRAM_SUN6I_H +#define _SUNXI_DRAM_SUN6I_H + +#ifndef __ASSEMBLY__ +#include +#endif + +struct sunxi_mctl_com_reg { + u32 cr; /* 0x00 */ + u32 ccr; /* 0x04 controller configuration register */ + u32 dbgcr; /* 0x08 */ + u32 dbgcr1; /* 0x0c */ + u32 rmcr[8]; /* 0x10 */ + u32 mmcr[16]; /* 0x30 */ + u32 mbagcr[6]; /* 0x70 */ + u32 maer; /* 0x88 */ + u8 res0[0x14]; /* 0x8c */ + u32 mdfscr; /* 0x100 */ + u32 mdfsmer; /* 0x104 */ + u32 mdfsmrmr; /* 0x108 */ + u32 mdfstr0; /* 0x10c */ + u32 mdfstr1; /* 0x110 */ + u32 mdfstr2; /* 0x114 */ + u32 mdfstr3; /* 0x118 */ + u32 mdfsgcr; /* 0x11c */ + u8 res1[0x1c]; /* 0x120 */ + u32 mdfsivr; /* 0x13c */ + u8 res2[0x0c]; /* 0x140 */ + u32 mdfstcr; /* 0x14c */ +}; + +struct sunxi_mctl_ctl_reg { + u8 res0[0x04]; /* 0x00 */ + u32 sctl; /* 0x04 */ + u32 sstat; /* 0x08 */ + u8 res1[0x34]; /* 0x0c */ + u32 mcmd; /* 0x40 */ + u8 res2[0x08]; /* 0x44 */ + u32 cmdstat; /* 0x4c */ + u32 cmdstaten; /* 0x50 */ + u8 res3[0x0c]; /* 0x54 */ + u32 mrrcfg0; /* 0x60 */ + u32 mrrstat0; /* 0x64 */ + u32 mrrstat1; /* 0x68 */ + u8 res4[0x10]; /* 0x6c */ + u32 mcfg1; /* 0x7c */ + u32 mcfg; /* 0x80 */ + u32 ppcfg; /* 0x84 */ + u32 mstat; /* 0x88 */ + u32 lp2zqcfg; /* 0x8c */ + u8 res5[0x04]; /* 0x90 */ + u32 dtustat; /* 0x94 */ + u32 dtuna; /* 0x98 */ + u32 dtune; /* 0x9c */ + u32 dtuprd0; /* 0xa0 */ + u32 dtuprd1; /* 0xa4 */ + u32 dtuprd2; /* 0xa8 */ + u32 dtuprd3; /* 0xac */ + u32 dtuawdt; /* 0xb0 */ + u8 res6[0x0c]; /* 0xb4 */ + u32 togcnt1u; /* 0xc0 */ + u8 res7[0x08]; /* 0xc4 */ + u32 togcnt100n; /* 0xcc */ + u32 trefi; /* 0xd0 */ + u32 tmrd; /* 0xd4 */ + u32 trfc; /* 0xd8 */ + u32 trp; /* 0xdc */ + u32 trtw; /* 0xe0 */ + u32 tal; /* 0xe4 */ + u32 tcl; /* 0xe8 */ + u32 tcwl; /* 0xec */ + u32 tras; /* 0xf0 */ + u32 trc; /* 0xf4 */ + u32 trcd; /* 0xf8 */ + u32 trrd; /* 0xfc */ + u32 trtp; /* 0x100 */ + u32 twr; /* 0x104 */ + u32 twtr; /* 0x108 */ + u32 texsr; /* 0x10c */ + u32 txp; /* 0x110 */ + u32 txpdll; /* 0x114 */ + u32 tzqcs; /* 0x118 */ + u32 tzqcsi; /* 0x11c */ + u32 tdqs; /* 0x120 */ + u32 tcksre; /* 0x124 */ + u32 tcksrx; /* 0x128 */ + u32 tcke; /* 0x12c */ + u32 tmod; /* 0x130 */ + u32 trstl; /* 0x134 */ + u32 tzqcl; /* 0x138 */ + u32 tmrr; /* 0x13c */ + u32 tckesr; /* 0x140 */ + u32 tdpd; /* 0x144 */ + u8 res8[0xb8]; /* 0x148 */ + u32 dtuwactl; /* 0x200 */ + u32 dturactl; /* 0x204 */ + u32 dtucfg; /* 0x208 */ + u32 dtuectl; /* 0x20c */ + u32 dtuwd0; /* 0x210 */ + u32 dtuwd1; /* 0x214 */ + u32 dtuwd2; /* 0x218 */ + u32 dtuwd3; /* 0x21c */ + u32 dtuwdm; /* 0x220 */ + u32 dturd0; /* 0x224 */ + u32 dturd1; /* 0x228 */ + u32 dturd2; /* 0x22c */ + u32 dturd3; /* 0x230 */ + u32 dtulfsrwd; /* 0x234 */ + u32 dtulfsrrd; /* 0x238 */ + u32 dtueaf; /* 0x23c */ + u32 dfitctldly; /* 0x240 */ + u32 dfiodtcfg; /* 0x244 */ + u32 dfiodtcfg1; /* 0x248 */ + u32 dfiodtrmap; /* 0x24c */ + u32 dfitphywrd; /* 0x250 */ + u32 dfitphywrl; /* 0x254 */ + u8 res9[0x08]; /* 0x258 */ + u32 dfitrdden; /* 0x260 */ + u32 dfitphyrdl; /* 0x264 */ + u8 res10[0x08]; /* 0x268 */ + u32 dfitphyupdtype0; /* 0x270 */ + u32 dfitphyupdtype1; /* 0x274 */ + u32 dfitphyupdtype2; /* 0x278 */ + u32 dfitphyupdtype3; /* 0x27c */ + u32 dfitctrlupdmin; /* 0x280 */ + u32 dfitctrlupdmax; /* 0x284 */ + u32 dfitctrlupddly; /* 0x288 */ + u8 res11[4]; /* 0x28c */ + u32 dfiupdcfg; /* 0x290 */ + u32 dfitrefmski; /* 0x294 */ + u32 dfitcrlupdi; /* 0x298 */ + u8 res12[0x10]; /* 0x29c */ + u32 dfitrcfg0; /* 0x2ac */ + u32 dfitrstat0; /* 0x2b0 */ + u32 dfitrwrlvlen; /* 0x2b4 */ + u32 dfitrrdlvlen; /* 0x2b8 */ + u32 dfitrrdlvlgateen; /* 0x2bc */ + u8 res13[0x04]; /* 0x2c0 */ + u32 dfistcfg0; /* 0x2c4 */ + u32 dfistcfg1; /* 0x2c8 */ + u8 res14[0x04]; /* 0x2cc */ + u32 dfitdramclken; /* 0x2d0 */ + u32 dfitdramclkdis; /* 0x2d4 */ + u8 res15[0x18]; /* 0x2d8 */ + u32 dfilpcfg0; /* 0x2f0 */ +}; + +struct sunxi_mctl_phy_reg { + u8 res0[0x04]; /* 0x00 */ + u32 pir; /* 0x04 */ + u32 pgcr; /* 0x08 phy general configuration register */ + u32 pgsr; /* 0x0c */ + u32 dllgcr; /* 0x10 */ + u32 acdllcr; /* 0x14 */ + u32 ptr0; /* 0x18 */ + u32 ptr1; /* 0x1c */ + u32 ptr2; /* 0x20 */ + u32 aciocr; /* 0x24 */ + u32 dxccr; /* 0x28 DATX8 common configuration register */ + u32 dsgcr; /* 0x2c dram system general config register */ + u32 dcr; /* 0x30 */ + u32 dtpr0; /* 0x34 dram timing parameters register 0 */ + u32 dtpr1; /* 0x38 dram timing parameters register 1 */ + u32 dtpr2; /* 0x3c dram timing parameters register 2 */ + u32 mr0; /* 0x40 mode register 0 */ + u32 mr1; /* 0x44 mode register 1 */ + u32 mr2; /* 0x48 mode register 2 */ + u32 mr3; /* 0x4c mode register 3 */ + u32 odtcr; /* 0x50 */ + u32 dtar; /* 0x54 data training address register */ + u32 dtd0; /* 0x58 */ + u32 dtd1; /* 0x5c */ + u8 res1[0x60]; /* 0x60 */ + u32 dcuar; /* 0xc0 */ + u32 dcudr; /* 0xc4 */ + u32 dcurr; /* 0xc8 */ + u32 dculr; /* 0xcc */ + u32 dcugcr; /* 0xd0 */ + u32 dcutpr; /* 0xd4 */ + u32 dcusr0; /* 0xd8 */ + u32 dcusr1; /* 0xdc */ + u8 res2[0x20]; /* 0xe0 */ + u32 bistrr; /* 0x100 */ + u32 bistmskr0; /* 0x104 */ + u32 bistmskr1; /* 0x108 */ + u32 bistwcr; /* 0x10c */ + u32 bistlsr; /* 0x110 */ + u32 bistar0; /* 0x114 */ + u32 bistar1; /* 0x118 */ + u32 bistar2; /* 0x11c */ + u32 bistupdr; /* 0x120 */ + u32 bistgsr; /* 0x124 */ + u32 bistwer; /* 0x128 */ + u32 bistber0; /* 0x12c */ + u32 bistber1; /* 0x130 */ + u32 bistber2; /* 0x134 */ + u32 bistwcsr; /* 0x138 */ + u32 bistfwr0; /* 0x13c */ + u32 bistfwr1; /* 0x140 */ + u8 res3[0x3c]; /* 0x144 */ + u32 zq0cr0; /* 0x180 zq 0 control register 0 */ + u32 zq0cr1; /* 0x184 zq 0 control register 1 */ + u32 zq0sr0; /* 0x188 zq 0 status register 0 */ + u32 zq0sr1; /* 0x18c zq 0 status register 1 */ + u8 res4[0x30]; /* 0x190 */ + u32 dx0gcr; /* 0x1c0 */ + u32 dx0gsr0; /* 0x1c4 */ + u32 dx0gsr1; /* 0x1c8 */ + u32 dx0dllcr; /* 0x1cc */ + u32 dx0dqtr; /* 0x1d0 */ + u32 dx0dqstr; /* 0x1d4 */ + u8 res5[0x28]; /* 0x1d8 */ + u32 dx1gcr; /* 0x200 */ + u32 dx1gsr0; /* 0x204 */ + u32 dx1gsr1; /* 0x208 */ + u32 dx1dllcr; /* 0x20c */ + u32 dx1dqtr; /* 0x210 */ + u32 dx1dqstr; /* 0x214 */ + u8 res6[0x28]; /* 0x218 */ + u32 dx2gcr; /* 0x240 */ + u32 dx2gsr0; /* 0x244 */ + u32 dx2gsr1; /* 0x248 */ + u32 dx2dllcr; /* 0x24c */ + u32 dx2dqtr; /* 0x250 */ + u32 dx2dqstr; /* 0x254 */ + u8 res7[0x28]; /* 0x258 */ + u32 dx3gcr; /* 0x280 */ + u32 dx3gsr0; /* 0x284 */ + u32 dx3gsr1; /* 0x288 */ + u32 dx3dllcr; /* 0x28c */ + u32 dx3dqtr; /* 0x290 */ + u32 dx3dqstr; /* 0x294 */ +}; + +/* + * DRAM common (sunxi_mctl_com_reg) register constants. + */ +#define MCTL_CR_RANK_MASK (3 << 0) +#define MCTL_CR_RANK(x) (((x) - 1) << 0) +#define MCTL_CR_BANK_MASK (3 << 2) +#define MCTL_CR_BANK(x) ((x) << 2) +#define MCTL_CR_ROW_MASK (0xf << 4) +#define MCTL_CR_ROW(x) (((x) - 1) << 4) +#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) +#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) +#define MCTL_CR_BUSW_MASK (3 << 12) +#define MCTL_CR_BUSW16 (1 << 12) +#define MCTL_CR_BUSW32 (3 << 12) +#define MCTL_CR_SEQUENCE (1 << 15) +#define MCTL_CR_DDR3 (3 << 16) +#define MCTL_CR_CHANNEL_MASK (1 << 19) +#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) +#define MCTL_CR_UNKNOWN ((1 << 22) | (1 << 20)) +#define MCTL_CCR_CH0_CLK_EN (1 << 0) +#define MCTL_CCR_CH1_CLK_EN (1 << 1) +#define MCTL_CCR_MASTER_CLK_EN (1 << 2) + +/* + * DRAM control (sunxi_mctl_ctl_reg) register constants. + * Note that we use constant values for a lot of the timings, this is what + * the original boot0 bootloader does. + */ +#define MCTL_SCTL_CONFIG 1 +#define MCTL_SCTL_ACCESS 2 +#define MCTL_MCMD_NOP 0x88000000 +#define MCTL_MCMD_BUSY 0x80000000 +#define MCTL_MCFG_DDR3 0x70061 +#define MCTL_TREFI 78 +#define MCTL_TMRD 4 +#define MCTL_TRFC 115 +#define MCTL_TRP 9 +#define MCTL_TPREA 0 +#define MCTL_TRTW 2 +#define MCTL_TAL 0 +#define MCTL_TCL 9 +#define MCTL_TCWL 8 +#define MCTL_TRAS 18 +#define MCTL_TRC 23 +#define MCTL_TRCD 9 +#define MCTL_TRRD 4 +#define MCTL_TRTP 4 +#define MCTL_TWR 8 +#define MCTL_TWTR 4 +#define MCTL_TEXSR 512 +#define MCTL_TXP 4 +#define MCTL_TXPDLL 14 +#define MCTL_TZQCS 64 +#define MCTL_TZQCSI 0 +#define MCTL_TDQS 1 +#define MCTL_TCKSRE 5 +#define MCTL_TCKSRX 5 +#define MCTL_TCKE 4 +#define MCTL_TMOD 12 +#define MCTL_TRSTL 80 +#define MCTL_TZQCL 512 +#define MCTL_TMRR 2 +#define MCTL_TCKESR 5 +#define MCTL_TDPD 0 +#define MCTL_DFITPHYRDL 15 +#define MCTL_DFIUPDCFG_UPD (1 << 1) +#define MCTL_DFISTCFG0 5 + +/* + * DRAM phy (sunxi_mctl_phy_reg) register values / constants. + */ +#define MCTL_PIR_CLEAR_STATUS (1 << 28) +#define MCTL_PIR_STEP1 0xe9 +#define MCTL_PIR_STEP2 0x81 +#define MCTL_PGCR_RANK (1 << 19) +#define MCTL_PGCR 0x018c0202 +#define MCTL_PGSR_TRAIN_ERR_MASK (3 << 5) +/* constants for both acdllcr as well as dx#dllcr */ +#define MCTL_DLLCR_NRESET (1 << 30) +#define MCTL_DLLCR_DISABLE (1 << 31) +/* ptr constants these are or-ed together to get the final ptr# values */ +#define MCTL_TITMSRST 10 +#define MCTL_TDLLLOCK 2250 +#define MCTL_TDLLSRST 23 +#define MCTL_TDINIT0 217000 +#define MCTL_TDINIT1 160 +#define MCTL_TDINIT2 87000 +#define MCTL_TDINIT3 433 +/* end ptr constants */ +#define MCTL_ACIOCR_DISABLE ((3 << 18) | (1 << 8) | (1 << 3)) +#define MCTL_DXCCR_DISABLE ((1 << 3) | (1 << 2)) +#define MCTL_DXCCR 0x800 +#define MCTL_DSGCR_ENABLE (1 << 28) +#define MCTL_DSGCR 0xf200001b +#define MCTL_DCR_DDR3 0x0b +/* dtpr constants these are or-ed together to get the final dtpr# values */ +#define MCTL_TCCD 0 +#define MCTL_TDQSCKMAX 1 +#define MCTL_TDQSCK 1 +#define MCTL_TRTODT 0 +#define MCTL_TFAW 20 +#define MCTL_TAOND 0 +#define MCTL_TDLLK 512 +/* end dtpr constants */ +#define MCTL_MR0 0x1a50 +#define MCTL_MR1 0x4 +#define MCTL_MR2 ((MCTL_TCWL - 5) << 3) +#define MCTL_MR3 0x0 +#define MCTL_DX_GCR_EN (1 << 0) +#define MCTL_DX_GCR 0x880 +#define MCTL_DX_GSR0_RANK0_TRAIN_DONE (1 << 0) +#define MCTL_DX_GSR0_RANK1_TRAIN_DONE (1 << 1) +#define MCTL_DX_GSR0_RANK0_TRAIN_ERR (1 << 4) +#define MCTL_DX_GSR0_RANK1_TRAIN_ERR (1 << 5) + +#endif /* _SUNXI_DRAM_SUN6I_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h new file mode 100644 index 000000000..ca98597f1 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Sun8i platform dram controller register and constant defines + * + * (C) Copyright 2007-2013 + * Allwinner Technology Co., Ltd. + * CPL + * Jerry Wang + * + * (C) Copyright 2014 Hans de Goede + */ + +#ifndef _SUNXI_DRAM_SUN8I_H +#define _SUNXI_DRAM_SUN8I_H + +struct dram_para { + u32 clock; + u32 type; + u32 zq; + u32 odt_en; + s32 odt_correction; + u32 para1; + u32 para2; + u32 mr0; + u32 mr1; + u32 mr2; + u32 mr3; + u32 tpr0; + u32 tpr1; + u32 tpr2; + u32 tpr3; + u32 tpr4; + u32 tpr5; + u32 tpr6; + u32 tpr7; + u32 tpr8; + u32 tpr9; + u32 tpr10; + u32 tpr11; + u32 tpr12; + u32 tpr13; +}; + +struct sunxi_mctl_com_reg { + u32 cr; /* 0x00 */ + u32 ccr; /* 0x04 controller configuration register */ + u32 dbgcr; /* 0x08 */ + u8 res0[0x4]; /* 0x0c */ + u32 mcr0_0; /* 0x10 */ + u32 mcr1_0; /* 0x14 */ + u32 mcr0_1; /* 0x18 */ + u32 mcr1_1; /* 0x1c */ + u32 mcr0_2; /* 0x20 */ + u32 mcr1_2; /* 0x24 */ + u32 mcr0_3; /* 0x28 */ + u32 mcr1_3; /* 0x2c */ + u32 mcr0_4; /* 0x30 */ + u32 mcr1_4; /* 0x34 */ + u32 mcr0_5; /* 0x38 */ + u32 mcr1_5; /* 0x3c */ + u32 mcr0_6; /* 0x40 */ + u32 mcr1_6; /* 0x44 */ + u32 mcr0_7; /* 0x48 */ + u32 mcr1_7; /* 0x4c */ + u32 mcr0_8; /* 0x50 */ + u32 mcr1_8; /* 0x54 */ + u32 mcr0_9; /* 0x58 */ + u32 mcr1_9; /* 0x5c */ + u32 mcr0_10; /* 0x60 */ + u32 mcr1_10; /* 0x64 */ + u32 mcr0_11; /* 0x68 */ + u32 mcr1_11; /* 0x6c */ + u32 mcr0_12; /* 0x70 */ + u32 mcr1_12; /* 0x74 */ + u32 mcr0_13; /* 0x78 */ + u32 mcr1_13; /* 0x7c */ + u32 mcr0_14; /* 0x80 */ + u32 mcr1_14; /* 0x84 */ + u32 mcr0_15; /* 0x88 */ + u32 mcr1_15; /* 0x8c */ + u32 bwcr; /* 0x90 */ + u32 maer; /* 0x94 */ + u8 res1[0x4]; /* 0x98 */ + u32 mcgcr; /* 0x9c */ + u32 bwctr; /* 0xa0 */ + u8 res2[0x4]; /* 0xa4 */ + u32 swonr; /* 0xa8 */ + u32 swoffr; /* 0xac */ +}; + +struct sunxi_mctl_ctl_reg { + u32 mstr; /* 0x00 */ + u32 statr; /* 0x04 */ + u8 res0[0x08]; /* 0x08 */ + u32 mrctrl0; /* 0x10 */ + u32 mrctrl1; /* 0x14 */ + u32 mrstatr; /* 0x18 */ + u8 res1[0x04]; /* 0x1c */ + u32 derateen; /* 0x20 */ + u32 deratenint; /* 0x24 */ + u8 res2[0x08]; /* 0x28 */ + u32 pwrctl; /* 0x30 */ + u32 pwrtmg; /* 0x34 */ + u8 res3[0x18]; /* 0x38 */ + u32 rfshctl0; /* 0x50 */ + u32 rfshctl1; /* 0x54 */ + u8 res4[0x8]; /* 0x58 */ + u32 rfshctl3; /* 0x60 */ + u32 rfshtmg; /* 0x64 */ + u8 res6[0x68]; /* 0x68 */ + u32 init0; /* 0xd0 */ + u32 init1; /* 0xd4 */ + u32 init2; /* 0xd8 */ + u32 init3; /* 0xdc */ + u32 init4; /* 0xe0 */ + u32 init5; /* 0xe4 */ + u8 res7[0x0c]; /* 0xe8 */ + u32 rankctl; /* 0xf4 */ + u8 res8[0x08]; /* 0xf8 */ + u32 dramtmg0; /* 0x100 */ + u32 dramtmg1; /* 0x104 */ + u32 dramtmg2; /* 0x108 */ + u32 dramtmg3; /* 0x10c */ + u32 dramtmg4; /* 0x110 */ + u32 dramtmg5; /* 0x114 */ + u32 dramtmg6; /* 0x118 */ + u32 dramtmg7; /* 0x11c */ + u32 dramtmg8; /* 0x120 */ + u8 res9[0x5c]; /* 0x124 */ + u32 zqctl0; /* 0x180 */ + u32 zqctl1; /* 0x184 */ + u32 zqctl2; /* 0x188 */ + u32 zqstat; /* 0x18c */ + u32 pitmg0; /* 0x190 */ + u32 pitmg1; /* 0x194 */ + u32 plpcfg0; /* 0x198 */ + u8 res10[0x04]; /* 0x19c */ + u32 upd0; /* 0x1a0 */ + u32 upd1; /* 0x1a4 */ + u32 upd2; /* 0x1a8 */ + u32 upd3; /* 0x1ac */ + u32 pimisc; /* 0x1b0 */ + u8 res11[0x1c]; /* 0x1b4 */ + u32 trainctl0; /* 0x1d0 */ + u32 trainctl1; /* 0x1d4 */ + u32 trainctl2; /* 0x1d8 */ + u32 trainstat; /* 0x1dc */ + u8 res12[0x60]; /* 0x1e0 */ + u32 odtcfg; /* 0x240 */ + u32 odtmap; /* 0x244 */ + u8 res13[0x08]; /* 0x248 */ + u32 sched; /* 0x250 */ + u8 res14[0x04]; /* 0x254 */ + u32 perfshpr0; /* 0x258 */ + u32 perfshpr1; /* 0x25c */ + u32 perflpr0; /* 0x260 */ + u32 perflpr1; /* 0x264 */ + u32 perfwr0; /* 0x268 */ + u32 perfwr1; /* 0x26c */ +}; + +struct sunxi_mctl_phy_reg { + u8 res0[0x04]; /* 0x00 */ + u32 pir; /* 0x04 */ + u32 pgcr0; /* 0x08 phy general configuration register */ + u32 pgcr1; /* 0x0c phy general configuration register */ + u32 pgsr0; /* 0x10 */ + u32 pgsr1; /* 0x14 */ + u32 dllgcr; /* 0x18 */ + u32 ptr0; /* 0x1c */ + u32 ptr1; /* 0x20 */ + u32 ptr2; /* 0x24 */ + u32 ptr3; /* 0x28 */ + u32 ptr4; /* 0x2c */ + u32 acmdlr; /* 0x30 */ + u32 acbdlr; /* 0x34 */ + u32 aciocr; /* 0x38 */ + u32 dxccr; /* 0x3c DATX8 common configuration register */ + u32 dsgcr; /* 0x40 dram system general config register */ + u32 dcr; /* 0x44 */ + u32 dtpr0; /* 0x48 dram timing parameters register 0 */ + u32 dtpr1; /* 0x4c dram timing parameters register 1 */ + u32 dtpr2; /* 0x50 dram timing parameters register 2 */ + u32 mr0; /* 0x54 mode register 0 */ + u32 mr1; /* 0x58 mode register 1 */ + u32 mr2; /* 0x5c mode register 2 */ + u32 mr3; /* 0x60 mode register 3 */ + u32 odtcr; /* 0x64 */ + u32 dtcr; /* 0x68 */ + u32 dtar0; /* 0x6c data training address register 0 */ + u32 dtar1; /* 0x70 data training address register 1 */ + u32 dtar2; /* 0x74 data training address register 2 */ + u32 dtar3; /* 0x78 data training address register 3 */ + u32 dtdr0; /* 0x7c */ + u32 dtdr1; /* 0x80 */ + u32 dtedr0; /* 0x84 */ + u32 dtedr1; /* 0x88 */ + u32 pgcr2; /* 0x8c */ + u8 res1[0x70]; /* 0x90 */ + u32 bistrr; /* 0x100 */ + u32 bistwcr; /* 0x104 */ + u32 bistmskr0; /* 0x108 */ + u32 bistmskr1; /* 0x10c */ + u32 bistmskr2; /* 0x110 */ + u32 bistlsr; /* 0x114 */ + u32 bistar0; /* 0x118 */ + u32 bistar1; /* 0x11c */ + u32 bistar2; /* 0x120 */ + u32 bistupdr; /* 0x124 */ + u32 bistgsr; /* 0x128 */ + u32 bistwer; /* 0x12c */ + u32 bistber0; /* 0x130 */ + u32 bistber1; /* 0x134 */ + u32 bistber2; /* 0x138 */ + u32 bistber3; /* 0x13c */ + u32 bistwcsr; /* 0x140 */ + u32 bistfwr0; /* 0x144 */ + u32 bistfwr1; /* 0x148 */ + u32 bistfwr2; /* 0x14c */ + u8 res2[0x30]; /* 0x150 */ + u32 zqcr0; /* 0x180 zq control register 0 */ + u32 zqcr1; /* 0x184 zq control register 1 */ + u32 zqsr0; /* 0x188 zq status register 0 */ + u32 zqsr1; /* 0x18c zq status register 1 */ + u32 zqcr2; /* 0x190 zq control register 2 */ + u8 res3[0x2c]; /* 0x194 */ + u32 dx0gcr; /* 0x1c0 */ + u32 dx0gsr0; /* 0x1c4 */ + u32 dx0gsr1; /* 0x1c8 */ + u32 dx0bdlr0; /* 0x1cc */ + u32 dx0bdlr1; /* 0x1d0 */ + u32 dx0bdlr2; /* 0x1d4 */ + u32 dx0bdlr3; /* 0x1d8 */ + u32 dx0bdlr4; /* 0x1dc */ + u32 dx0lcdlr0; /* 0x1e0 */ + u32 dx0lcdlr1; /* 0x1e4 */ + u32 dx0lcdlr2; /* 0x1e8 */ + u32 dx0mdlr; /* 0x1ec */ + u32 dx0gtr; /* 0x1f0 */ + u32 dx0gsr2; /* 0x1f4 */ + u8 res4[0x08]; /* 0x1f8 */ + u32 dx1gcr; /* 0x200 */ + u32 dx1gsr0; /* 0x204 */ + u32 dx1gsr1; /* 0x208 */ + u32 dx1bdlr0; /* 0x20c */ + u32 dx1bdlr1; /* 0x210 */ + u32 dx1bdlr2; /* 0x214 */ + u32 dx1bdlr3; /* 0x218 */ + u32 dx1bdlr4; /* 0x21c */ + u32 dx1lcdlr0; /* 0x220 */ + u32 dx1lcdlr1; /* 0x224 */ + u32 dx1lcdlr2; /* 0x228 */ + u32 dx1mdlr; /* 0x22c */ + u32 dx1gtr; /* 0x230 */ + u32 dx1gsr2; /* 0x234 */ +}; + +/* + * DRAM common (sunxi_mctl_com_reg) register constants. + */ +#define MCTL_CR_ROW_MASK (0xf << 4) +#define MCTL_CR_ROW(x) (((x) - 1) << 4) +#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) +#define MCTL_CR_PAGE_SIZE(x) ((x) << 8) + +#endif /* _SUNXI_DRAM_SUN8I_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun8i_a33.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun8i_a33.h new file mode 100644 index 000000000..3f65306cc --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun8i_a33.h @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Sun8i platform dram controller register and constant defines + * + * (C) Copyright 2007-2015 Allwinner Technology Co. + * Jerry Wang + * (C) Copyright 2015 Vishnu Patekar + * (C) Copyright 2014-2015 Hans de Goede + */ + +#ifndef _SUNXI_DRAM_SUN8I_A33_H +#define _SUNXI_DRAM_SUN8I_A33_H + +#ifndef __ASSEMBLY__ +#include +#endif + +struct sunxi_mctl_com_reg { + u32 cr; /* 0x00 */ + u32 ccr; /* 0x04 controller configuration register */ + u32 dbgcr; /* 0x08 */ + u8 res0[0x4]; /* 0x0c */ + u32 mcr0_0; /* 0x10 */ + u32 mcr1_0; /* 0x14 */ + u32 mcr0_1; /* 0x18 */ + u32 mcr1_1; /* 0x1c */ + u32 mcr0_2; /* 0x20 */ + u32 mcr1_2; /* 0x24 */ + u32 mcr0_3; /* 0x28 */ + u32 mcr1_3; /* 0x2c */ + u32 mcr0_4; /* 0x30 */ + u32 mcr1_4; /* 0x34 */ + u32 mcr0_5; /* 0x38 */ + u32 mcr1_5; /* 0x3c */ + u32 mcr0_6; /* 0x40 */ + u32 mcr1_6; /* 0x44 */ + u32 mcr0_7; /* 0x48 */ + u32 mcr1_7; /* 0x4c */ + u32 mcr0_8; /* 0x50 */ + u32 mcr1_8; /* 0x54 */ + u32 mcr0_9; /* 0x58 */ + u32 mcr1_9; /* 0x5c */ + u32 mcr0_10; /* 0x60 */ + u32 mcr1_10; /* 0x64 */ + u32 mcr0_11; /* 0x68 */ + u32 mcr1_11; /* 0x6c */ + u32 mcr0_12; /* 0x70 */ + u32 mcr1_12; /* 0x74 */ + u32 mcr0_13; /* 0x78 */ + u32 mcr1_13; /* 0x7c */ + u32 mcr0_14; /* 0x80 */ + u32 mcr1_14; /* 0x84 */ + u32 mcr0_15; /* 0x88 */ + u32 mcr1_15; /* 0x8c */ + u32 bwcr; /* 0x90 */ + u32 maer; /* 0x94 */ + u32 mapr; /* 0x98 */ + u32 mcgcr; /* 0x9c */ + u32 bwctr; /* 0xa0 */ + u8 res2[0x8]; /* 0xa4 */ + u32 swoffr; /* 0xac */ + u8 res3[0x10]; /* 0xb0 */ + u32 swonr; /* 0xc0 */ + u8 res4[0x3c]; /* 0xc4 */ + u32 mdfscr; /* 0x100 */ + u32 mdfsmer; /* 0x104 */ +}; + +struct sunxi_mctl_ctl_reg { + u32 pir; /* 0x00 */ + u32 pwrctl; /* 0x04 */ + u32 mrctrl0; /* 0x08 */ + u32 clken; /* 0x0c */ + u32 pgsr0; /* 0x10 */ + u32 pgsr1; /* 0x14 */ + u32 statr; /* 0x18 */ + u8 res1[0x14]; /* 0x1c */ + u32 mr0; /* 0x30 */ + u32 mr1; /* 0x34 */ + u32 mr2; /* 0x38 */ + u32 mr3; /* 0x3c */ + u32 pllgcr; /* 0x40 */ + u32 ptr0; /* 0x44 */ + u32 ptr1; /* 0x48 */ + u32 ptr2; /* 0x4c */ + u32 ptr3; /* 0x50 */ + u32 ptr4; /* 0x54 */ + u32 dramtmg0; /* 0x58 dram timing parameters register 0 */ + u32 dramtmg1; /* 0x5c dram timing parameters register 1 */ + u32 dramtmg2; /* 0x60 dram timing parameters register 2 */ + u32 dramtmg3; /* 0x64 dram timing parameters register 3 */ + u32 dramtmg4; /* 0x68 dram timing parameters register 4 */ + u32 dramtmg5; /* 0x6c dram timing parameters register 5 */ + u32 dramtmg6; /* 0x70 dram timing parameters register 6 */ + u32 dramtmg7; /* 0x74 dram timing parameters register 7 */ + u32 dramtmg8; /* 0x78 dram timing parameters register 8 */ + u32 odtcfg; /* 0x7c */ + u32 pitmg0; /* 0x80 */ + u32 pitmg1; /* 0x84 */ + u8 res2[0x4]; /* 0x88 */ + u32 rfshctl0; /* 0x8c */ + u32 rfshtmg; /* 0x90 */ + u32 rfshctl1; /* 0x94 */ + u32 pwrtmg; /* 0x98 */ + u8 res3[0x20]; /* 0x9c */ + u32 dqsgmr; /* 0xbc */ + u32 dtcr; /* 0xc0 */ + u32 dtar0; /* 0xc4 */ + u32 dtar1; /* 0xc8 */ + u32 dtar2; /* 0xcc */ + u32 dtar3; /* 0xd0 */ + u32 dtdr0; /* 0xd4 */ + u32 dtdr1; /* 0xd8 */ + u32 dtmr0; /* 0xdc */ + u32 dtmr1; /* 0xe0 */ + u32 dtbmr; /* 0xe4 */ + u32 catr0; /* 0xe8 */ + u32 catr1; /* 0xec */ + u32 dtedr0; /* 0xf0 */ + u32 dtedr1; /* 0xf4 */ + u8 res4[0x8]; /* 0xf8 */ + u32 pgcr0; /* 0x100 */ + u32 pgcr1; /* 0x104 */ + u32 pgcr2; /* 0x108 */ + u8 res5[0x4]; /* 0x10c */ + u32 iovcr0; /* 0x110 */ + u32 iovcr1; /* 0x114 */ + u32 dqsdr; /* 0x118 */ + u32 dxccr; /* 0x11c */ + u32 odtmap; /* 0x120 */ + u32 zqctl0; /* 0x124 */ + u32 zqctl1; /* 0x128 */ + u8 res6[0x14]; /* 0x12c */ + u32 zqcr0; /* 0x140 zq control register 0 */ + u32 zqcr1; /* 0x144 zq control register 1 */ + u32 zqcr2; /* 0x148 zq control register 2 */ + u32 zqsr0; /* 0x14c zq status register 0 */ + u32 zqsr1; /* 0x150 zq status register 1 */ + u8 res7[0x6c]; /* 0x154 */ + u32 sched; /* 0x1c0 */ + u32 perfhpr0; /* 0x1c4 */ + u32 perfhpr1; /* 0x1c8 */ + u32 perflpr0; /* 0x1cc */ + u32 perflpr1; /* 0x1d0 */ + u32 perfwr0; /* 0x1d4 */ + u32 perfwr1; /* 0x1d8 */ +}; + +#define DXnGTR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x) +#define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x) +#define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x) +#define DXnGSR1(x) (SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x) +#define DXnGSR2(x) (SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x) + +/* + * DRAM common (sunxi_mctl_com_reg) register constants. + */ +#define MCTL_CR_RANK_MASK (3 << 0) +#define MCTL_CR_RANK(x) (((x) - 1) << 0) +#define MCTL_CR_BANK_MASK (3 << 2) +#define MCTL_CR_BANK(x) ((x) << 2) +#define MCTL_CR_ROW_MASK (0xf << 4) +#define MCTL_CR_ROW(x) (((x) - 1) << 4) +#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) +#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) +#define MCTL_CR_BUSW_MASK (7 << 12) +#define MCTL_CR_BUSW8 (0 << 12) +#define MCTL_CR_BUSW16 (1 << 12) +#define MCTL_CR_SEQUENCE (1 << 15) +#define MCTL_CR_DDR3 (3 << 16) +#define MCTL_CR_CHANNEL_MASK (1 << 19) +#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) +#define MCTL_CR_UNKNOWN (0x4 << 20) +#define MCTL_CR_CS1_CONTROL(x) ((x) << 24) + +/* DRAM control (sunxi_mctl_ctl_reg) register constants */ +#define MCTL_MR0 0x1c70 /* CL=11, WR=12 */ +#define MCTL_MR1 0x40 +#define MCTL_MR2 0x18 /* CWL=8 */ +#define MCTL_MR3 0x0 + +#endif /* _SUNXI_DRAM_SUN8I_A33_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h new file mode 100644 index 000000000..2a8799635 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Sun8i platform dram controller register and constant defines + * + * (C) Copyright 2007-2015 Allwinner Technology Co. + * Jerry Wang + * (C) Copyright 2015 Vishnu Patekar + * (C) Copyright 2014-2015 Hans de Goede + */ + +#ifndef _SUNXI_DRAM_SUN8I_A83T_H +#define _SUNXI_DRAM_SUN8I_A83T_H + +#ifndef __ASSEMBLY__ +#include +#endif + +struct sunxi_mctl_com_reg { + u32 cr; /* 0x00 */ + u32 ccr; /* 0x04 controller configuration register */ + u32 dbgcr; /* 0x08 */ + u8 res0[0x4]; /* 0x0c */ + u32 mcr0_0; /* 0x10 */ + u32 mcr1_0; /* 0x14 */ + u32 mcr0_1; /* 0x18 */ + u32 mcr1_1; /* 0x1c */ + u32 mcr0_2; /* 0x20 */ + u32 mcr1_2; /* 0x24 */ + u32 mcr0_3; /* 0x28 */ + u32 mcr1_3; /* 0x2c */ + u32 mcr0_4; /* 0x30 */ + u32 mcr1_4; /* 0x34 */ + u32 mcr0_5; /* 0x38 */ + u32 mcr1_5; /* 0x3c */ + u32 mcr0_6; /* 0x40 */ + u32 mcr1_6; /* 0x44 */ + u32 mcr0_7; /* 0x48 */ + u32 mcr1_7; /* 0x4c */ + u32 mcr0_8; /* 0x50 */ + u32 mcr1_8; /* 0x54 */ + u32 mcr0_9; /* 0x58 */ + u32 mcr1_9; /* 0x5c */ + u32 mcr0_10; /* 0x60 */ + u32 mcr1_10; /* 0x64 */ + u32 mcr0_11; /* 0x68 */ + u32 mcr1_11; /* 0x6c */ + u32 mcr0_12; /* 0x70 */ + u32 mcr1_12; /* 0x74 */ + u32 mcr0_13; /* 0x78 */ + u32 mcr1_13; /* 0x7c */ + u32 mcr0_14; /* 0x80 */ + u32 mcr1_14; /* 0x84 */ + u32 mcr0_15; /* 0x88 */ + u32 mcr1_15; /* 0x8c */ + u32 bwcr; /* 0x90 */ + u32 maer; /* 0x94 */ + u32 mapr; /* 0x98 */ + u32 mcgcr; /* 0x9c */ + u32 bwctr; /* 0xa0 */ + u8 res2[0x8]; /* 0xa4 */ + u32 swoffr; /* 0xac */ + u8 res3[0x10]; /* 0xb0 */ + u32 swonr; /* 0xc0 */ + u8 res4[0x3c]; /* 0xc4 */ + u32 mdfscr; /* 0x100 */ + u32 mdfsmer; /* 0x104 */ +}; + +struct sunxi_mctl_ctl_reg { + u32 pir; /* 0x00 */ + u32 pwrctl; /* 0x04 */ + u32 mrctrl0; /* 0x08 */ + u32 clken; /* 0x0c */ + u32 pgsr0; /* 0x10 */ + u32 pgsr1; /* 0x14 */ + u32 statr; /* 0x18 */ + u8 res1[0x14]; /* 0x1c */ + u32 mr0; /* 0x30 */ + u32 mr1; /* 0x34 */ + u32 mr2; /* 0x38 */ + u32 mr3; /* 0x3c */ + u32 pllgcr; /* 0x40 */ + u32 ptr0; /* 0x44 */ + u32 ptr1; /* 0x48 */ + u32 ptr2; /* 0x4c */ + u32 ptr3; /* 0x50 */ + u32 ptr4; /* 0x54 */ + u32 dramtmg0; /* 0x58 dram timing parameters register 0 */ + u32 dramtmg1; /* 0x5c dram timing parameters register 1 */ + u32 dramtmg2; /* 0x60 dram timing parameters register 2 */ + u32 dramtmg3; /* 0x64 dram timing parameters register 3 */ + u32 dramtmg4; /* 0x68 dram timing parameters register 4 */ + u32 dramtmg5; /* 0x6c dram timing parameters register 5 */ + u32 dramtmg6; /* 0x70 dram timing parameters register 6 */ + u32 dramtmg7; /* 0x74 dram timing parameters register 7 */ + u32 dramtmg8; /* 0x78 dram timing parameters register 8 */ + u32 odtcfg; /* 0x7c */ + u32 pitmg0; /* 0x80 */ + u32 pitmg1; /* 0x84 */ + u8 res2[0x4]; /* 0x88 */ + u32 rfshctl0; /* 0x8c */ + u32 rfshtmg; /* 0x90 */ + u32 rfshctl1; /* 0x94 */ + u32 pwrtmg; /* 0x98 */ + u8 res3[0x20]; /* 0x9c */ + u32 dqsgmr; /* 0xbc */ + u32 dtcr; /* 0xc0 */ + u32 dtar0; /* 0xc4 */ + u32 dtar1; /* 0xc8 */ + u32 dtar2; /* 0xcc */ + u32 dtar3; /* 0xd0 */ + u32 dtdr0; /* 0xd4 */ + u32 dtdr1; /* 0xd8 */ + u32 dtmr0; /* 0xdc */ + u32 dtmr1; /* 0xe0 */ + u32 dtbmr; /* 0xe4 */ + u32 catr0; /* 0xe8 */ + u32 catr1; /* 0xec */ + u32 dtedr0; /* 0xf0 */ + u32 dtedr1; /* 0xf4 */ + u8 res4[0x8]; /* 0xf8 */ + u32 pgcr0; /* 0x100 */ + u32 pgcr1; /* 0x104 */ + u32 pgcr2; /* 0x108 */ + u32 pgcr3; /* 0x10c */ + u32 iovcr0; /* 0x110 */ + u32 iovcr1; /* 0x114 */ + u32 dqsdr; /* 0x118 */ + u32 dxccr; /* 0x11c */ + u32 odtmap; /* 0x120 */ + u32 zqctl0; /* 0x124 */ + u32 zqctl1; /* 0x128 */ + u8 res6[0x14]; /* 0x12c */ + u32 zqncr; /* 0x140 zq control register 0 */ + u32 zqnpr; /* 0x144 zq control register 1 */ + u32 zqndr; /* 0x148 zq control register 2 */ + u32 zqnsr; /* 0x14c zq status register 0 */ + u32 res7; /* 0x150 zq status register 1 */ + u8 res8[0x6c]; /* 0x154 */ + u32 sched; /* 0x1c0 */ + u32 perfhpr0; /* 0x1c4 */ + u32 perfhpr1; /* 0x1c8 */ + u32 perflpr0; /* 0x1cc */ + u32 perflpr1; /* 0x1d0 */ + u32 perfwr0; /* 0x1d4 */ + u32 perfwr1; /* 0x1d8 */ +}; + + +#define ZQnPR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000144 + 0x10 * x) +#define ZQnDR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000148 + 0x10 * x) +#define ZQnSR(x) (SUNXI_DRAM_CTL0_BASE + 0x0000014c + 0x10 * x) + +#define DXnGTR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x) +#define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x) +#define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x) +#define DXnGSR1(x) (SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x) +#define DXnGSR2(x) (SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x) + +#define CAIOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000210 + 0x4 * (x)) +#define DXnMDLR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000300 + 0x80 * x) +#define DXMDLR0 (SUNXI_DRAM_CTL0_BASE + 0x00000300) +#define DXnLCDLR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000304 + 0x80 * x) +#define DXnLCDLR1(x) (SUNXI_DRAM_CTL0_BASE + 0x00000308 + 0x80 * x) +#define DXnLCDLR2(x) (SUNXI_DRAM_CTL0_BASE + 0x0000030c + 0x80 * x) +#define DATX0IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000310 + 0x4 * x) +#define DATX1IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000390 + 0x4 * x) +#define DATX2IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000410 + 0x4 * x) +#define DATX3IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000490 + 0x4 * x) +#define MX_UPD0 (SUNXI_DRAM_CTL0_BASE + 0x00000880) +#define MX_UPD2 (SUNXI_DRAM_CTL0_BASE + 0x00000888) + +#define MCTL_PROTECT (SUNXI_DRAM_COM_BASE + 0x800) +#define MCTL_MASTER_CFG0(x) (SUNXI_DRAM_COM_BASE + 0x10 + 0x8 * x) +#define MCTL_MASTER_CFG1(x) (SUNXI_DRAM_COM_BASE + 0x14 + 0x8 * x) + +/* + * DRAM common (sunxi_mctl_com_reg) register constants. + */ +#define MCTL_CR_RANK_MASK (3 << 0) +#define MCTL_CR_RANK(x) (((x) - 1) << 0) +#define MCTL_CR_BANK_MASK (3 << 2) +#define MCTL_CR_BANK(x) ((x) << 2) +#define MCTL_CR_ROW_MASK (0xf << 4) +#define MCTL_CR_ROW(x) (((x) - 1) << 4) +#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) +#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) +#define MCTL_CR_BUSW_MASK (7 << 12) +#define MCTL_CR_BUSW8 (0 << 12) +#define MCTL_CR_BUSW16 (1 << 12) +#define MCTL_CR_SEQUENCE (1 << 15) +#define MCTL_CR_DRAM_TYPE(x) ((x) << 16) +#define MCTL_CR_CHANNEL_MASK (1 << 19) +#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) +#define MCTL_CR_UNKNOWN (0x4 << 20) +#define MCTL_CR_CS1_CONTROL(x) ((x) << 24) + +/* DRAM control (sunxi_mctl_ctl_reg) register constants */ +#define MCTL_MR0 0x1c70 /* CL=11, WR=12 */ +#define MCTL_MR1 0x40 +#define MCTL_MR2 0x18 /* CWL=8 */ +#define MCTL_MR3 0x0 + +#define MCTL_LPDDR3_MR0 0x0 +#define MCTL_LPDDR3_MR1 0xc3 /* twr=8, bl=8 */ +#define MCTL_LPDDR3_MR2 0xa /* RL=12, CWL=6 */ +#define MCTL_LPDDR3_MR3 0x0 + +#define DRAM_TYPE_DDR3 3 +#define DRAM_TYPE_LPDDR3 7 +#endif /* _SUNXI_DRAM_SUN8I_A83T_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun9i.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun9i.h new file mode 100644 index 000000000..41df5fe5b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sun9i.h @@ -0,0 +1,281 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Sun8i platform dram controller register and constant defines + * + * (C) Copyright 2007-2015 Allwinner Technology Co. + * Jerry Wang + * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH + * Philipp Tomsich + */ + +#ifndef _SUNXI_DRAM_SUN9I_H +#define _SUNXI_DRAM_SUN9I_H + +#ifndef __ASSEMBLY__ +#include +#endif + +struct sunxi_mctl_com_reg { + u32 cr; /* 0x00 */ + u32 ccr; /* 0x04 controller configuration register */ + u32 dbgcr; /* 0x08 */ + u32 dbgcr1; /* 0x0c */ + u32 rmcr; /* 0x10 */ + u8 res1[0x1c]; /* 0x14 */ + u32 mmcr; /* 0x30 */ + u8 res2[0x3c]; /* 0x34 */ + u32 mbagcr; /* 0x70 */ + u32 mbacr; /* 0x74 */ + u8 res3[0x10]; /* 0x78 */ + u32 maer; /* 0x88 */ + u8 res4[0x74]; /* 0x8c */ + u32 mdfscr; /* 0x100 */ + u32 mdfsmer; /* 0x104 */ + u32 mdfsmrmr; /* 0x108 */ + u32 mdfstr[4]; /* 0x10c */ + u32 mdfsgcr; /* 0x11c */ + u8 res5[0x1c]; /* 0x120 */ + u32 mdfsivr; /* 0x13c */ + u8 res6[0xc]; /* 0x140 */ + u32 mdfstcr; /* 0x14c */ +}; + + +struct sunxi_mctl_ctl_reg { + u32 mstr; /* 0x00 master register */ + u32 stat; /* 0x04 operating mode status register */ + u8 res1[0x8]; /* 0x08 */ + u32 mrctrl[2]; /* 0x10 mode register read/write control reg */ + u32 mstat; /* 0x18 mode register read/write status reg */ + u8 res2[0x4]; /* 0x1c */ + u32 derateen; /* 0x20 temperature derate enable register */ + u32 derateint; /* 0x24 temperature derate interval register */ + u8 res3[0x8]; /* 0x28 */ + u32 pwrctl; /* 0x30 low power control register */ + u32 pwrtmg; /* 0x34 low power timing register */ + u8 res4[0x18]; /* 0x38 */ + u32 rfshctl0; /* 0x50 refresh control register 0 */ + u32 rfshctl1; /* 0x54 refresh control register 1 */ + u8 res5[0x8]; /* 0x58 */ + u32 rfshctl3; /* 0x60 refresh control register 3 */ + u32 rfshtmg; /* 0x64 refresh timing register */ + u8 res6[0x68]; /* 0x68 */ + u32 init[6]; /* 0xd0 SDRAM initialisation register */ + u8 res7[0xc]; /* 0xe8 */ + u32 rankctl; /* 0xf4 rank control register */ + u8 res8[0x8]; /* 0xf8 */ + u32 dramtmg[9]; /* 0x100 DRAM timing register */ + u8 res9[0x5c]; /* 0x124 */ + u32 zqctrl[3]; /* 0x180 ZQ control register */ + u32 zqstat; /* 0x18c ZQ status register */ + u32 dfitmg[2]; /* 0x190 DFI timing register */ + u32 dfilpcfg; /* 0x198 DFI low power configuration register */ + u8 res10[0x4]; /* 0x19c */ + u32 dfiupd[4]; /* 0x1a0 DFI update register */ + u32 dfimisc; /* 0x1b0 DFI miscellaneous control register */ + u8 res11[0x1c]; /* 0x1b4 */ + u32 trainctl[3]; /* 0x1d0 */ + u32 trainstat; /* 0x1dc */ + u8 res12[0x20]; /* 0x1e0 */ + u32 addrmap[7]; /* 0x200 address map register */ + u8 res13[0x24]; /* 0x21c */ + u32 odtcfg; /* 0x240 ODT configuration register */ + u32 odtmap; /* 0x244 ODT/rank map register */ + u8 res14[0x8]; /* 0x248 */ + u32 sched; /* 0x250 scheduler control register */ + u8 res15[0x4]; /* 0x254 */ + u32 perfhpr0; /* 0x258 high priority read CAM register 0 */ + u32 perfhpr1; /* 0x25c high priority read CAM register 1 */ + u32 perflpr0; /* 0x260 low priority read CAM register 0 */ + u32 perflpr1; /* 0x264 low priority read CAM register 1 */ + u32 perfwr0; /* 0x268 write CAM register 0 */ + u32 perfwr1; /* 0x26c write CAM register 1 */ +}; + + +struct sunxi_mctl_phy_reg { + u8 res0[0x04]; /* 0x00 revision id ??? */ + u32 pir; /* 0x04 PHY initialisation register */ + u32 pgcr[4]; /* 0x08 PHY general configuration register */ + u32 pgsr[2]; /* 0x18 PHY general status register */ + u32 pllcr; /* 0x20 PLL control register */ + u32 ptr[5]; /* 0x24 PHY timing register */ + u32 acmdlr; /* 0x38 AC master delay line register */ + u32 aclcdlr; /* 0x3c AC local calibrated delay line reg */ + u32 acbdlr[10]; /* 0x40 AC bit delay line register */ + u32 aciocr[6]; /* 0x68 AC IO configuration register */ + u32 dxccr; /* 0x80 DATX8 common configuration register */ + u32 dsgcr; /* 0x84 DRAM system general config register */ + u32 dcr; /* 0x88 DRAM configuration register */ + u32 dtpr[4]; /* 0x8c DRAM timing parameters register */ + u32 mr0; /* 0x9c mode register 0 */ + u32 mr1; /* 0xa0 mode register 1 */ + u32 mr2; /* 0xa4 mode register 2 */ + u32 mr3; /* 0xa8 mode register 3 */ + u32 odtcr; /* 0xac ODT configuration register */ + u32 dtcr; /* 0xb0 data training configuration register */ + u32 dtar[4]; /* 0xb4 data training address register */ + u32 dtdr[2]; /* 0xc4 data training data register */ + u32 dtedr[2]; /* 0xcc data training eye data register */ + u32 rdimmgcr[2]; /* 0xd4 RDIMM general configuration register */ + u32 rdimmcr[2]; /* 0xdc RDIMM control register */ + u32 gpr[2]; /* 0xe4 general purpose register */ + u32 catr[2]; /* 0xec CA training register */ + u32 dqdsr; /* 0xf4 DQS drift register */ + u8 res1[0xc8]; /* 0xf8 */ + u32 bistrr; /* 0x1c0 BIST run register */ + u32 bistwcr; /* 0x1c4 BIST word count register */ + u32 bistmskr[3]; /* 0x1c8 BIST mask register */ + u32 bistlsr; /* 0x1d4 BIST LFSR seed register */ + u32 bistar[3]; /* 0x1d8 BIST address register */ + u32 bistupdr; /* 0x1e4 BIST user pattern data register */ + u32 bistgsr; /* 0x1e8 BIST general status register */ + u32 bistwer; /* 0x1dc BIST word error register */ + u32 bistber[4]; /* 0x1f0 BIST bit error register */ + u32 bistwcsr; /* 0x200 BIST word count status register */ + u32 bistfwr[3]; /* 0x204 BIST fail word register */ + u8 res2[0x28]; /* 0x210 */ + u32 iovcr[2]; /* 0x238 IO VREF control register */ + struct ddrphy_zq { + u32 cr; /* impedance control register */ + u32 pr; /* impedance control data register */ + u32 dr; /* impedance control data register */ + u32 sr; /* impedance control status register */ + } zq[4]; /* 0x240, 0x250, 0x260, 0x270 */ + struct ddrphy_dx { + u32 gcr[4]; /* DATX8 general configuration register */ + u32 gsr[3]; /* DATX8 general status register */ + u32 bdlr[7]; /* DATX8 bit delay line register */ + u32 lcdlr[3]; /* DATX8 local calibrated delay line reg */ + u32 mdlr; /* DATX8 master delay line register */ + u32 gtr; /* DATX8 general timing register */ + u8 res[0x34]; + } dx[4]; /* 0x280, 0x300, 0x380, 0x400 */ +}; + +/* + * DRAM common (sunxi_mctl_com_reg) register constants. + */ +#define MCTL_CR_RANK_MASK (3 << 0) +#define MCTL_CR_RANK(x) (((x) - 1) << 0) +#define MCTL_CR_BANK_MASK (3 << 2) +#define MCTL_CR_BANK(x) ((x) << 2) +#define MCTL_CR_ROW_MASK (0xf << 4) +#define MCTL_CR_ROW(x) (((x) - 1) << 4) +#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) +#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) +#define MCTL_CR_BUSW_MASK (3 << 12) +#define MCTL_CR_BUSW16 (1 << 12) +#define MCTL_CR_BUSW32 (3 << 12) +#define MCTL_CR_DRAMTYPE_MASK (7 << 16) +#define MCTL_CR_DRAMTYPE_DDR2 (2 << 16) +#define MCTL_CR_DRAMTYPE_DDR3 (3 << 16) +#define MCTL_CR_DRAMTYPE_LPDDR2 (6 << 16) + +#define MCTL_CR_CHANNEL_MASK ((1 << 22) | (1 << 20) | (1 << 19)) +#define MCTL_CR_CHANNEL_SINGLE (1 << 22) +#define MCTL_CR_CHANNEL_DUAL ((1 << 22) | (1 << 20) | (1 << 19)) + +#define MCTL_CCR_CH0_CLK_EN (1 << 15) +#define MCTL_CCR_CH1_CLK_EN (1 << 31) + +/* + * post_cke_x1024 [bits 16..25]: Cycles to wait after driving CKE high + * to start the SDRAM initialization sequence (in 1024s of cycles). + */ +#define MCTL_INIT0_POST_CKE_x1024(n) ((n & 0x0fff) << 16) +/* + * pre_cke_x1024 [bits 0..11] Cycles to wait after reset before driving + * CKE high to start the SDRAM initialization (in 1024s of cycles) + */ +#define MCTL_INIT0_PRE_CKE_x1024(n) ((n & 0x0fff) << 0) +#define MCTL_INIT1_DRAM_RSTN_x1024(n) ((n & 0xff) << 16) +#define MCTL_INIT1_FINAL_WAIT_x32(n) ((n & 0x3f) << 8) +#define MCTL_INIT1_PRE_OCD_x32(n) ((n & 0x0f) << 0) +#define MCTL_INIT2_IDLE_AFTER_RESET_x32(n) ((n & 0xff) << 8) +#define MCTL_INIT2_MIN_STABLE_CLOCK_x1(n) ((n & 0x0f) << 0) +#define MCTL_INIT3_MR(n) ((n & 0xffff) << 16) +#define MCTL_INIT3_EMR(n) ((n & 0xffff) << 0) +#define MCTL_INIT4_EMR2(n) ((n & 0xffff) << 16) +#define MCTL_INIT4_EMR3(n) ((n & 0xffff) << 0) +#define MCTL_INIT5_DEV_ZQINIT_x32(n) ((n & 0x00ff) << 16) +#define MCTL_INIT5_MAX_AUTO_INIT_x1024(n) ((n & 0x03ff) << 0); + +#define MCTL_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0) +#define MCTL_DFIUPD0_DIS_AUTO_CTRLUPD (1 << 31) + +#define MCTL_MSTR_DEVICETYPE_DDR3 1 +#define MCTL_MSTR_DEVICETYPE_LPDDR2 4 +#define MCTL_MSTR_DEVICETYPE_LPDDR3 8 +#define MCTL_MSTR_DEVICETYPE(type) \ + ((type == DRAM_TYPE_DDR3) ? MCTL_MSTR_DEVICETYPE_DDR3 : \ + ((type == DRAM_TYPE_LPDDR2) ? MCTL_MSTR_DEVICETYPE_LPDDR2 : \ + MCTL_MSTR_DEVICETYPE_LPDDR3)) +#define MCTL_MSTR_BURSTLENGTH4 (2 << 16) +#define MCTL_MSTR_BURSTLENGTH8 (4 << 16) +#define MCTL_MSTR_BURSTLENGTH16 (8 << 16) +#define MCTL_MSTR_BURSTLENGTH(type) \ + ((type == DRAM_TYPE_DDR3) ? MCTL_MSTR_BURSTLENGTH8 : \ + ((type == DRAM_TYPE_LPDDR2) ? MCTL_MSTR_BURSTLENGTH4 : \ + MCTL_MSTR_BURSTLENGTH8)) +#define MCTL_MSTR_ACTIVERANKS(x) (((x == 2) ? 3 : 1) << 24) +#define MCTL_MSTR_BUSWIDTH8 (2 << 12) +#define MCTL_MSTR_BUSWIDTH16 (1 << 12) +#define MCTL_MSTR_BUSWIDTH32 (0 << 12) +#define MCTL_MSTR_2TMODE (1 << 10) + +#define MCTL_RFSHCTL3_DIS_AUTO_REFRESH (1 << 0) + +#define MCTL_ZQCTRL0_TZQCS(x) (x << 0) +#define MCTL_ZQCTRL0_TZQCL(x) (x << 16) +#define MCTL_ZQCTRL0_ZQCL_DIS (1 << 30) +#define MCTL_ZQCTRL0_ZQCS_DIS (1 << 31) +#define MCTL_ZQCTRL1_TZQRESET(x) (x << 20) +#define MCTL_ZQCTRL1_TZQSI_x1024(x) (x << 0) +#define MCTL_ZQCTRL2_TZRESET_TRIGGER (1 << 0) + +#define MCTL_PHY_DCR_BYTEMASK (1 << 10) +#define MCTL_PHY_DCR_2TMODE (1 << 28) +#define MCTL_PHY_DCR_DDR8BNK (1 << 3) +#define MCTL_PHY_DRAMMODE_DDR3 3 +#define MCTL_PHY_DRAMMODE_LPDDR2 0 +#define MCTL_PHY_DRAMMODE_LPDDR3 1 + +#define MCTL_DTCR_DEFAULT 0x00003007 +#define MCTL_DTCR_RANKEN(n) (((n == 2) ? 3 : 1) << 24) + +#define MCTL_PGCR1_ZCKSEL_MASK (3 << 23) +#define MCTL_PGCR1_IODDRM_MASK (3 << 7) +#define MCTL_PGCR1_IODDRM_DDR3 (1 << 7) +#define MCTL_PGCR1_IODDRM_DDR3L (2 << 7) +#define MCTL_PGCR1_INHVT_EN (1 << 26) + +#define MCTL_PLLGCR_PLL_BYPASS (1 << 31) +#define MCTL_PLLGCR_PLL_POWERDOWN (1 << 29) + +#define MCTL_PIR_PLL_BYPASS (1 << 17) +#define MCTL_PIR_MASK (~(1 << 17)) +#define MCTL_PIR_INIT (1 << 0) + +#define MCTL_PGSR0_ERRORS (0x1ff << 20) + +/* Constants for assembling MR0 */ +#define DDR3_MR0_PPD_FAST_EXIT (1 << 12) +#define DDR3_MR0_WR(n) \ + ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9)) +#define DDR3_MR0_CL(n) \ + ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2)) +#define DDR3_MR0_BL8 (0 << 0) + +#define DDR3_MR1_RTT120OHM ((0 << 9) | (1 << 6) | (0 << 2)) + +#define DDR3_MR2_TWL(n) \ + (((n - 5) & 0x7) << 3) + +#define MCTL_NS2CYCLES_CEIL(ns) ((ns * (CONFIG_DRAM_CLK / 2) + 999) / 1000) + +#define DRAM_TYPE_DDR3 3 +#define DRAM_TYPE_LPDDR2 6 +#define DRAM_TYPE_LPDDR3 7 + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h new file mode 100644 index 000000000..e843c1420 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * sun8i H3 platform dram controller register and constant defines + * + * (C) Copyright 2007-2015 Allwinner Technology Co. + * Jerry Wang + * (C) Copyright 2015 Vishnu Patekar + * (C) Copyright 2014-2015 Hans de Goede + * (C) Copyright 2015 Jens Kuske + */ + +#ifndef _SUNXI_DRAM_SUN8I_H3_H +#define _SUNXI_DRAM_SUN8I_H3_H + +#include + +struct sunxi_mctl_com_reg { + u32 cr; /* 0x00 control register */ + u32 cr_r1; /* 0x04 rank 1 control register (R40 only) */ + u8 res0[0x4]; /* 0x08 */ + u32 tmr; /* 0x0c (unused on H3) */ + u32 mcr[16][2]; /* 0x10 */ + u32 bwcr; /* 0x90 bandwidth control register */ + u32 maer; /* 0x94 master enable register */ + u32 mapr; /* 0x98 master priority register */ + u32 mcgcr; /* 0x9c */ + u32 cpu_bwcr; /* 0xa0 */ + u32 gpu_bwcr; /* 0xa4 */ + u32 ve_bwcr; /* 0xa8 */ + u32 disp_bwcr; /* 0xac */ + u32 other_bwcr; /* 0xb0 */ + u32 total_bwcr; /* 0xb4 */ + u8 res1[0x8]; /* 0xb8 */ + u32 swonr; /* 0xc0 */ + u32 swoffr; /* 0xc4 */ + u8 res2[0x8]; /* 0xc8 */ + u32 cccr; /* 0xd0 */ + u8 res3[0x54]; /* 0xd4 */ + u32 mdfs_bwlr[3]; /* 0x128 (unused on H3) */ + u8 res4[0x6cc]; /* 0x134 */ + u32 protect; /* 0x800 */ +}; + +#define MCTL_CR_BL8 (0x4 << 20) + +#define MCTL_CR_1T (0x1 << 19) +#define MCTL_CR_2T (0x0 << 19) + +#define MCTL_CR_LPDDR3 (0x7 << 16) +#define MCTL_CR_LPDDR2 (0x6 << 16) +#define MCTL_CR_DDR3 (0x3 << 16) +#define MCTL_CR_DDR2 (0x2 << 16) + +#define MCTL_CR_SEQUENTIAL (0x1 << 15) +#define MCTL_CR_INTERLEAVED (0x0 << 15) + +#define MCTL_CR_FULL_WIDTH (0x1 << 12) +#define MCTL_CR_HALF_WIDTH (0x0 << 12) +#define MCTL_CR_BUS_FULL_WIDTH(x) ((x) << 12) + +#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) +#define MCTL_CR_ROW_BITS(x) (((x) - 1) << 4) +#define MCTL_CR_EIGHT_BANKS (0x1 << 2) +#define MCTL_CR_FOUR_BANKS (0x0 << 2) +#define MCTL_CR_DUAL_RANK (0x1 << 0) +#define MCTL_CR_SINGLE_RANK (0x0 << 0) + +/* + * CR_R1 is a register found in the R40's DRAM controller. It sets various + * parameters for rank 1. Bits [11:0] have the same meaning as the bits in + * MCTL_CR, but they apply to rank 1 only. This implies we can have + * different chips for rank 1 than rank 0. + * + * As address line A15 and CS1 chip select for rank 1 are muxed on the same + * pin, if single rank is used, A15 must be muxed in. + */ +#define MCTL_CR_R1_MUX_A15 (0x1 << 21) + +#define PROTECT_MAGIC (0x94be6fa3) + +struct sunxi_mctl_ctl_reg { + u32 pir; /* 0x00 PHY initialization register */ + u32 pwrctl; /* 0x04 */ + u32 mrctrl; /* 0x08 */ + u32 clken; /* 0x0c */ + u32 pgsr[2]; /* 0x10 PHY general status registers */ + u32 statr; /* 0x18 */ + u8 res1[0x10]; /* 0x1c */ + u32 lp3mr11; /* 0x2c */ + u32 mr[4]; /* 0x30 mode registers */ + u32 pllgcr; /* 0x40 */ + u32 ptr[5]; /* 0x44 PHY timing registers */ + u32 dramtmg[9]; /* 0x58 DRAM timing registers */ + u32 odtcfg; /* 0x7c */ + u32 pitmg[2]; /* 0x80 PHY interface timing registers */ + u8 res2[0x4]; /* 0x88 */ + u32 rfshctl0; /* 0x8c */ + u32 rfshtmg; /* 0x90 refresh timing */ + u32 rfshctl1; /* 0x94 */ + u32 pwrtmg; /* 0x98 */ + u8 res3[0x1c]; /* 0x9c */ + u32 vtfcr; /* 0xb8 (unused on H3) */ + u32 dqsgmr; /* 0xbc */ + u32 dtcr; /* 0xc0 */ + u32 dtar[4]; /* 0xc4 */ + u32 dtdr[2]; /* 0xd4 */ + u32 dtmr[2]; /* 0xdc */ + u32 dtbmr; /* 0xe4 */ + u32 catr[2]; /* 0xe8 */ + u32 dtedr[2]; /* 0xf0 */ + u8 res4[0x8]; /* 0xf8 */ + u32 pgcr[4]; /* 0x100 PHY general configuration registers */ + u32 iovcr[2]; /* 0x110 */ + u32 dqsdr; /* 0x118 */ + u32 dxccr; /* 0x11c */ + u32 odtmap; /* 0x120 */ + u32 zqctl[2]; /* 0x124 */ + u8 res6[0x14]; /* 0x12c */ + u32 zqcr; /* 0x140 ZQ control register */ + u32 zqsr; /* 0x144 ZQ status register */ + u32 zqdr[3]; /* 0x148 ZQ data registers */ + u8 res7[0x6c]; /* 0x154 */ + u32 sched; /* 0x1c0 */ + u32 perfhpr[2]; /* 0x1c4 */ + u32 perflpr[2]; /* 0x1cc */ + u32 perfwr[2]; /* 0x1d4 */ + u8 res8[0x24]; /* 0x1dc */ + u32 acmdlr; /* 0x200 AC master delay line register */ + u32 aclcdlr; /* 0x204 AC local calibrated delay line register */ + u32 aciocr; /* 0x208 AC I/O configuration register */ + u8 res9[0x4]; /* 0x20c */ + u32 acbdlr[31]; /* 0x210 AC bit delay line registers */ + u8 res10[0x74]; /* 0x28c */ + struct { /* 0x300 DATX8 modules*/ + u32 mdlr; /* 0x00 master delay line register */ + u32 lcdlr[3]; /* 0x04 local calibrated delay line registers */ + u32 bdlr[11]; /* 0x10 bit delay line registers */ + u32 sdlr; /* 0x3c output enable bit delay registers */ + u32 gtr; /* 0x40 general timing register */ + u32 gcr; /* 0x44 general configuration register */ + u32 gsr[3]; /* 0x48 general status registers */ + u8 res0[0x2c]; /* 0x54 */ + } dx[4]; + u8 res11[0x388]; /* 0x500 */ + u32 upd2; /* 0x888 */ +}; + +#define PTR3_TDINIT1(x) ((x) << 20) +#define PTR3_TDINIT0(x) ((x) << 0) + +#define PTR4_TDINIT3(x) ((x) << 20) +#define PTR4_TDINIT2(x) ((x) << 0) + +#define DRAMTMG0_TWTP(x) ((x) << 24) +#define DRAMTMG0_TFAW(x) ((x) << 16) +#define DRAMTMG0_TRAS_MAX(x) ((x) << 8) +#define DRAMTMG0_TRAS(x) ((x) << 0) + +#define DRAMTMG1_TXP(x) ((x) << 16) +#define DRAMTMG1_TRTP(x) ((x) << 8) +#define DRAMTMG1_TRC(x) ((x) << 0) + +#define DRAMTMG2_TCWL(x) ((x) << 24) +#define DRAMTMG2_TCL(x) ((x) << 16) +#define DRAMTMG2_TRD2WR(x) ((x) << 8) +#define DRAMTMG2_TWR2RD(x) ((x) << 0) + +#define DRAMTMG3_TMRW(x) ((x) << 16) +#define DRAMTMG3_TMRD(x) ((x) << 12) +#define DRAMTMG3_TMOD(x) ((x) << 0) + +#define DRAMTMG4_TRCD(x) ((x) << 24) +#define DRAMTMG4_TCCD(x) ((x) << 16) +#define DRAMTMG4_TRRD(x) ((x) << 8) +#define DRAMTMG4_TRP(x) ((x) << 0) + +#define DRAMTMG5_TCKSRX(x) ((x) << 24) +#define DRAMTMG5_TCKSRE(x) ((x) << 16) +#define DRAMTMG5_TCKESR(x) ((x) << 8) +#define DRAMTMG5_TCKE(x) ((x) << 0) + +#define RFSHTMG_TREFI(x) ((x) << 16) +#define RFSHTMG_TRFC(x) ((x) << 0) + +#define PIR_CLRSR (0x1 << 27) /* clear status registers */ +#define PIR_QSGATE (0x1 << 10) /* Read DQS gate training */ +#define PIR_DRAMINIT (0x1 << 8) /* DRAM initialization */ +#define PIR_DRAMRST (0x1 << 7) /* DRAM reset */ +#define PIR_PHYRST (0x1 << 6) /* PHY reset */ +#define PIR_DCAL (0x1 << 5) /* DDL calibration */ +#define PIR_PLLINIT (0x1 << 4) /* PLL initialization */ +#define PIR_ZCAL (0x1 << 1) /* ZQ calibration */ +#define PIR_INIT (0x1 << 0) /* PHY initialization trigger */ + +#define PGSR_INIT_DONE (0x1 << 0) /* PHY init done */ + +#define ZQCR_PWRDOWN (1U << 31) /* ZQ power down */ + +#define ACBDLR_WRITE_DELAY(x) ((x) << 8) + +#define DXBDLR_DQ(x) (x) /* DQ0-7 BDLR index */ +#define DXBDLR_DM 8 /* DM BDLR index */ +#define DXBDLR_DQS 9 /* DQS BDLR index */ +#define DXBDLR_DQSN 10 /* DQSN BDLR index */ + +#define DXBDLR_WRITE_DELAY(x) ((x) << 8) +#define DXBDLR_READ_DELAY(x) ((x) << 0) + +/* + * The delay parameters below allow to allegedly specify delay times of some + * unknown unit for each individual bit trace in each of the four data bytes + * the 32-bit wide access consists of. Also three control signals can be + * adjusted individually. + */ +#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) +/* The eight data lines (DQn) plus DM, DQS and DQSN */ +#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3) + +struct rank_para { + u16 page_size; + u8 row_bits; + u8 bank_bits; +}; + +struct dram_para { + u8 dual_rank; + u8 bus_full_width; + struct rank_para ranks[2]; + const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; + const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; + const u8 ac_delays[31]; +}; + +static inline int ns_to_t(int nanoseconds) +{ + const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; + + return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); +} + +void mctl_set_timing_params(uint16_t socid, struct dram_para *para); + +#endif /* _SUNXI_DRAM_SUN8I_H3_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/gpio.h new file mode 100644 index 000000000..2969a530a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/gpio.h @@ -0,0 +1,255 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Tom Cubie + */ + +#ifndef _SUNXI_GPIO_H +#define _SUNXI_GPIO_H + +#include +#include + +/* + * sunxi has 9 banks of gpio, they are: + * PA0 - PA17 | PB0 - PB23 | PC0 - PC24 + * PD0 - PD27 | PE0 - PE31 | PF0 - PF5 + * PG0 - PG9 | PH0 - PH27 | PI0 - PI12 + */ + +#define SUNXI_GPIO_A 0 +#define SUNXI_GPIO_B 1 +#define SUNXI_GPIO_C 2 +#define SUNXI_GPIO_D 3 +#define SUNXI_GPIO_E 4 +#define SUNXI_GPIO_F 5 +#define SUNXI_GPIO_G 6 +#define SUNXI_GPIO_H 7 +#define SUNXI_GPIO_I 8 + +/* + * This defines the number of GPIO banks for the _main_ GPIO controller. + * You should fix up the padding in struct sunxi_gpio_reg below if you + * change this. + */ +#define SUNXI_GPIO_BANKS 9 + +/* + * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO) + * at a different register offset. + * + * sun6i has 2 banks: + * PL0 - PL8 | PM0 - PM7 + * + * sun8i has 1 bank: + * PL0 - PL11 + * + * sun9i has 3 banks: + * PL0 - PL9 | PM0 - PM15 | PN0 - PN1 + */ +#define SUNXI_GPIO_L 11 +#define SUNXI_GPIO_M 12 +#define SUNXI_GPIO_N 13 + +struct sunxi_gpio { + u32 cfg[4]; + u32 dat; + u32 drv[2]; + u32 pull[2]; +}; + +/* gpio interrupt control */ +struct sunxi_gpio_int { + u32 cfg[3]; + u32 ctl; + u32 sta; + u32 deb; /* interrupt debounce */ +}; + +struct sunxi_gpio_reg { + struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS]; + u8 res[0xbc]; + struct sunxi_gpio_int gpio_int; +}; + +#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340 +#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348 + +#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \ + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \ + &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L]) + +#define GPIO_BANK(pin) ((pin) >> 5) +#define GPIO_NUM(pin) ((pin) & 0x1f) + +#define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3) +#define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2) + +#define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4) +#define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) + +#define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4) +#define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) + +/* GPIO bank sizes */ +#define SUNXI_GPIO_A_NR 32 +#define SUNXI_GPIO_B_NR 32 +#define SUNXI_GPIO_C_NR 32 +#define SUNXI_GPIO_D_NR 32 +#define SUNXI_GPIO_E_NR 32 +#define SUNXI_GPIO_F_NR 32 +#define SUNXI_GPIO_G_NR 32 +#define SUNXI_GPIO_H_NR 32 +#define SUNXI_GPIO_I_NR 32 +#define SUNXI_GPIO_L_NR 32 +#define SUNXI_GPIO_M_NR 32 + +#define SUNXI_GPIO_NEXT(__gpio) \ + ((__gpio##_START) + (__gpio##_NR) + 0) + +enum sunxi_gpio_number { + SUNXI_GPIO_A_START = 0, + SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A), + SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B), + SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C), + SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D), + SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E), + SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), + SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), + SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), + SUNXI_GPIO_L_START = 352, + SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), + SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M), + SUNXI_GPIO_AXP0_START = 1024, +}; + +/* SUNXI GPIO number definitions */ +#define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr)) +#define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr)) +#define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr)) +#define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr)) +#define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr)) +#define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr)) +#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) +#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) +#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) +#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) +#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr)) +#define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr)) + +#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr)) + +/* GPIO pin function config */ +#define SUNXI_GPIO_INPUT 0 +#define SUNXI_GPIO_OUTPUT 1 +#define SUNXI_GPIO_DISABLE 7 + +#define SUNXI_GPA_EMAC 2 +#define SUN6I_GPA_GMAC 2 +#define SUN7I_GPA_GMAC 5 +#define SUN6I_GPA_SDC2 5 +#define SUN6I_GPA_SDC3 4 +#define SUN8I_H3_GPA_UART0 2 + +#define SUN4I_GPB_PWM 2 +#define SUN4I_GPB_TWI0 2 +#define SUN4I_GPB_TWI1 2 +#define SUN5I_GPB_TWI1 2 +#define SUN4I_GPB_TWI2 2 +#define SUN5I_GPB_TWI2 2 +#define SUN8I_V3S_GPB_TWI0 2 +#define SUN4I_GPB_UART0 2 +#define SUN5I_GPB_UART0 2 +#define SUN8I_GPB_UART2 2 +#define SUN8I_A33_GPB_UART0 3 +#define SUN8I_A83T_GPB_UART0 2 +#define SUN8I_V3S_GPB_UART0 3 +#define SUN50I_GPB_UART0 4 + +#define SUNXI_GPC_NAND 2 +#define SUNXI_GPC_SPI0 3 +#define SUNXI_GPC_SDC2 3 +#define SUN6I_GPC_SDC3 4 +#define SUN50I_GPC_SPI0 4 + +#define SUN8I_GPD_SDC1 3 +#define SUNXI_GPD_LCD0 2 +#define SUNXI_GPD_LVDS0 3 +#define SUNXI_GPD_PWM 2 + +#define SUN5I_GPE_SDC2 3 +#define SUN8I_GPE_TWI2 3 +#define SUN50I_GPE_TWI2 3 + +#define SUNXI_GPF_SDC0 2 +#define SUNXI_GPF_UART0 4 +#define SUN8I_GPF_UART0 3 + +#define SUN4I_GPG_SDC1 4 +#define SUN5I_GPG_SDC1 2 +#define SUN6I_GPG_SDC1 2 +#define SUN8I_GPG_SDC1 2 +#define SUN8I_GPG_UART1 2 +#define SUN6I_GPG_TWI3 2 +#define SUN5I_GPG_UART1 4 + +#define SUN6I_GPH_PWM 2 +#define SUN8I_GPH_PWM 2 +#define SUN4I_GPH_SDC1 5 +#define SUN6I_GPH_TWI0 2 +#define SUN8I_GPH_TWI0 2 +#define SUN50I_GPH_TWI0 2 +#define SUN6I_GPH_TWI1 2 +#define SUN8I_GPH_TWI1 2 +#define SUN50I_GPH_TWI1 2 +#define SUN6I_GPH_TWI2 2 +#define SUN6I_GPH_UART0 2 +#define SUN9I_GPH_UART0 2 +#define SUN50I_H6_GPH_UART0 2 +#define SUN50I_H616_GPH_UART0 2 + +#define SUNXI_GPI_SDC3 2 +#define SUN7I_GPI_TWI3 3 +#define SUN7I_GPI_TWI4 3 + +#define SUN6I_GPL0_R_P2WI_SCK 3 +#define SUN6I_GPL1_R_P2WI_SDA 3 + +#define SUN8I_GPL_R_RSB 2 +#define SUN8I_H3_GPL_R_TWI 2 +#define SUN8I_A23_GPL_R_TWI 3 +#define SUN8I_GPL_R_UART 2 +#define SUN50I_GPL_R_TWI 2 +#define SUN50I_H616_GPL_R_TWI 3 + +#define SUN9I_GPN_R_RSB 3 + +/* GPIO pin pull-up/down config */ +#define SUNXI_GPIO_PULL_DISABLE 0 +#define SUNXI_GPIO_PULL_UP 1 +#define SUNXI_GPIO_PULL_DOWN 2 + +/* Virtual AXP0 GPIOs */ +#define SUNXI_GPIO_AXP0_PREFIX "AXP0-" +#define SUNXI_GPIO_AXP0_VBUS_DETECT 4 +#define SUNXI_GPIO_AXP0_VBUS_ENABLE 5 +#define SUNXI_GPIO_AXP0_GPIO_COUNT 6 + +void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val); +void sunxi_gpio_set_cfgpin(u32 pin, u32 val); +int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); +int sunxi_gpio_get_cfgpin(u32 pin); +int sunxi_gpio_set_drv(u32 pin, u32 val); +int sunxi_gpio_set_pull(u32 pin, u32 val); +int sunxi_name_to_gpio_bank(const char *name); +int sunxi_name_to_gpio(const char *name); +#define name_to_gpio(name) sunxi_name_to_gpio(name) + +#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO +int axp_gpio_init(void); +#else +static inline int axp_gpio_init(void) { return 0; } +#endif + +#endif /* _SUNXI_GPIO_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/gtbus.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/gtbus.h new file mode 100644 index 000000000..a89102ecc --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/gtbus.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * GTBUS initialisation + * + * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH + * Philipp Tomsich + */ + +#ifndef _SUNXI_GTBUS_H +#define _SUNXI_GTBUS_H + +#if defined(CONFIG_MACH_SUN9I) +#include +#endif + +#ifndef __ASSEMBLY__ +void gtbus_init(void); +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h new file mode 100644 index 000000000..f9629923a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * GTBUS initialisation for sun9i + * + * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH + * Philipp Tomsich + */ + +#ifndef _SUNXI_GTBUS_SUN9I_H +#define _SUNXI_GTBUS_SUN9I_H + +#include + +struct sunxi_gtbus_reg { + u32 mst_cfg[36]; /* 0x000 */ + u8 reserved1[0x70]; /* 0x090 */ + u32 bw_wdw_cfg; /* 0x100 */ + u32 mst_read_prio_cfg[2]; /* 0x104 */ + u32 lvl2_mst_cfg; /* 0x10c */ + u32 sw_clk_on; /* 0x110 */ + u32 sw_clk_off; /* 0x114 */ + u32 pmu_mst_en; /* 0x118 */ + u32 pmu_cfg; /* 0x11c */ + u32 pmu_cnt[19]; /* 0x120 */ + u32 reserved2[0x94]; /* 0x16c */ + u32 cci400_config[3]; /* 0x200 */ + u32 cci400_status[2]; /* 0x20c */ +}; + +/* for register GT_MST_CFG_REG(n) */ +#define GT_ENABLE_REQ (1<<31) /* clock on */ +#define GT_DISABLE_REQ (1<<30) /* clock off */ +#define GT_QOS_SHIFT 28 +#define GT_THD1_SHIFT 16 +#define GT_REQN_MAX 0xf /* max no master requests in one cycle */ +#define GT_REQN_SHIFT 12 +#define GT_THD0_SHIFT 0 + +#define GT_QOS_MAX 0x3 +#define GT_THD_MAX 0xfff +#define GT_BW_WDW_MAX 0xffff + +/* mst_read_prio_cfg */ +#define GT_PRIO_LOW 0 +#define GT_PRIO_HIGH 1 + +/* GTBUS port ids */ +#define GT_PORT_CPUM1 0 +#define GT_PORT_CPUM2 1 +#define GT_PORT_SATA 2 +#define GT_PORT_USB3 3 +#define GT_PORT_FE0 4 +#define GT_PORT_BE1 5 +#define GT_PORT_BE2 6 +#define GT_PORT_IEP0 7 +#define GT_PORT_FE1 8 +#define GT_PORT_BE0 9 +#define GT_PORT_FE2 10 +#define GT_PORT_IEP1 11 +#define GT_PORT_VED 12 +#define GT_PORT_VEE 13 +#define GT_PORT_FD 14 +#define GT_PORT_CSI 15 +#define GT_PORT_MP 16 +#define GT_PORT_HSI 17 +#define GT_PORT_SS 18 +#define GT_PORT_TS 19 +#define GT_PORT_DMA 20 +#define GT_PORT_NDFC0 21 +#define GT_PORT_NDFC1 22 +#define GT_PORT_CPUS 23 +#define GT_PORT_TH 24 +#define GT_PORT_GMAC 25 +#define GT_PORT_USB0 26 +#define GT_PORT_MSTG0 27 +#define GT_PORT_MSTG1 28 +#define GT_PORT_MSTG2 29 +#define GT_PORT_MSTG3 30 +#define GT_PORT_USB1 31 +#define GT_PORT_GPU0 32 +#define GT_PORT_GPU1 33 +#define GT_PORT_USB2 34 +#define GT_PORT_CPUM0 35 + +#define GP_MST_CFG_DEFAULT \ + ((GT_QOS_MAX << GT_QOS_SHIFT) | \ + (GT_THD_MAX << GT_THD1_SHIFT) | \ + (GT_REQN_MAX << GT_REQN_SHIFT) | \ + (GT_THD_MAX << GT_THD0_SHIFT)) + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/i2c.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/i2c.h new file mode 100644 index 000000000..1cb2ba6b0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/i2c.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 - Hans de Goede + */ +#ifndef _SUNXI_I2C_H_ +#define _SUNXI_I2C_H_ + +#include + +#ifdef CONFIG_I2C0_ENABLE +#define CONFIG_I2C_MVTWSI_BASE0 SUNXI_TWI0_BASE +#endif +#ifdef CONFIG_I2C1_ENABLE +#define CONFIG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE +#endif +#ifdef CONFIG_I2C2_ENABLE +#define CONFIG_I2C_MVTWSI_BASE2 SUNXI_TWI2_BASE +#endif +#ifdef CONFIG_I2C3_ENABLE +#define CONFIG_I2C_MVTWSI_BASE3 SUNXI_TWI3_BASE +#endif +#ifdef CONFIG_I2C4_ENABLE +#define CONFIG_I2C_MVTWSI_BASE4 SUNXI_TWI4_BASE +#endif +#ifdef CONFIG_R_I2C_ENABLE +#define CONFIG_I2C_MVTWSI_BASE5 SUNXI_R_TWI_BASE +#endif + +/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ +#define CONFIG_SYS_TCLK 24000000 + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/lcdc.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/lcdc.h new file mode 100644 index 000000000..90216bcfd --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/lcdc.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Sunxi platform timing controller register and constant defines + * + * (C) Copyright 2014 Hans de Goede + * (C) Copyright 2017 Jernej Skrabec + */ + +#ifndef _LCDC_H +#define _LCDC_H + +#include + +struct sunxi_lcdc_reg { + u32 ctrl; /* 0x00 */ + u32 int0; /* 0x04 */ + u32 int1; /* 0x08 */ + u8 res0[0x04]; /* 0x0c */ + u32 tcon0_frm_ctrl; /* 0x10 */ + u32 tcon0_frm_seed[6]; /* 0x14 */ + u32 tcon0_frm_table[4]; /* 0x2c */ + u8 res1[4]; /* 0x3c */ + u32 tcon0_ctrl; /* 0x40 */ + u32 tcon0_dclk; /* 0x44 */ + u32 tcon0_timing_active; /* 0x48 */ + u32 tcon0_timing_h; /* 0x4c */ + u32 tcon0_timing_v; /* 0x50 */ + u32 tcon0_timing_sync; /* 0x54 */ + u32 tcon0_hv_intf; /* 0x58 */ + u8 res2[0x04]; /* 0x5c */ + u32 tcon0_cpu_intf; /* 0x60 */ + u32 tcon0_cpu_wr_dat; /* 0x64 */ + u32 tcon0_cpu_rd_dat0; /* 0x68 */ + u32 tcon0_cpu_rd_dat1; /* 0x6c */ + u32 tcon0_ttl_timing0; /* 0x70 */ + u32 tcon0_ttl_timing1; /* 0x74 */ + u32 tcon0_ttl_timing2; /* 0x78 */ + u32 tcon0_ttl_timing3; /* 0x7c */ + u32 tcon0_ttl_timing4; /* 0x80 */ + u32 tcon0_lvds_intf; /* 0x84 */ + u32 tcon0_io_polarity; /* 0x88 */ + u32 tcon0_io_tristate; /* 0x8c */ + u32 tcon1_ctrl; /* 0x90 */ + u32 tcon1_timing_source; /* 0x94 */ + u32 tcon1_timing_scale; /* 0x98 */ + u32 tcon1_timing_out; /* 0x9c */ + u32 tcon1_timing_h; /* 0xa0 */ + u32 tcon1_timing_v; /* 0xa4 */ + u32 tcon1_timing_sync; /* 0xa8 */ + u8 res3[0x44]; /* 0xac */ + u32 tcon1_io_polarity; /* 0xf0 */ + u32 tcon1_io_tristate; /* 0xf4 */ + u8 res4[0x108]; /* 0xf8 */ + u32 mux_ctrl; /* 0x200 */ + u8 res5[0x1c]; /* 0x204 */ + u32 lvds_ana0; /* 0x220 */ + u32 lvds_ana1; /* 0x224 */ +}; + +/* + * LCDC register constants. + */ +#define SUNXI_LCDC_X(x) (((x) - 1) << 16) +#define SUNXI_LCDC_Y(y) (((y) - 1) << 0) +#define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24) +#define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25) +#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0) +#define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0) +#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0) +#define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31) +#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 ((1 << 31) | (0 << 4)) +#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 ((1 << 31) | (5 << 4)) +#define SUNXI_LCDC_TCON0_FRM_SEED 0x11111111 +#define SUNXI_LCDC_TCON0_FRM_TAB0 0x01010000 +#define SUNXI_LCDC_TCON0_FRM_TAB1 0x15151111 +#define SUNXI_LCDC_TCON0_FRM_TAB2 0x57575555 +#define SUNXI_LCDC_TCON0_FRM_TAB3 0x7f7f7777 +#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) +#define SUNXI_LCDC_TCON0_CTRL_ENABLE (1 << 31) +#define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0) +#define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28) +#define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0) +#define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16) +#define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0) +#define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16) +#ifdef CONFIG_SUNXI_GEN_SUN6I +#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 (1 << 20) +#else +#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 0 /* NA */ +#endif +#define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26) +#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31) +#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28) +#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) +#define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE (1 << 20) +#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31) +#define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0) +#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) +#define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0) +#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) ((n) << 16) +#define SUNXI_LCDC_MUX_CTRL_SRC0_MASK (0xf << 0) +#define SUNXI_LCDC_MUX_CTRL_SRC0(x) ((x) << 0) +#define SUNXI_LCDC_MUX_CTRL_SRC1_MASK (0xf << 4) +#define SUNXI_LCDC_MUX_CTRL_SRC1(x) ((x) << 4) +#ifdef CONFIG_SUNXI_GEN_SUN6I +#define SUNXI_LCDC_LVDS_ANA0 0x40040320 +#define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31) +#define SUNXI_LCDC_LVDS_ANA0_DRVC (1 << 24) +#define SUNXI_LCDC_LVDS_ANA0_DRVD(x) ((x) << 20) +#else +#define SUNXI_LCDC_LVDS_ANA0 0x3f310000 +#define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22) +#endif +#define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10) +#define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00) + +void lcdc_init(struct sunxi_lcdc_reg * const lcdc); +void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth); +void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc, + const struct display_timing *mode, + int clk_div, bool for_ext_vga_dac, + int depth, int dclk_phase); +void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc, + const struct display_timing *mode, + bool ext_hvsync, bool is_composite); +void lcdc_pll_set(struct sunxi_ccm_reg * const ccm, int tcon, + int dotclock, int *clk_div, int *clk_double, + bool is_composite); + +#endif /* _LCDC_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/mmc.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/mmc.h new file mode 100644 index 000000000..340e25b04 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/mmc.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Aaron + * + * MMC register definition for allwinner sunxi platform. + */ + +#ifndef _SUNXI_MMC_H +#define _SUNXI_MMC_H + +#include + +struct sunxi_mmc { + u32 gctrl; /* 0x00 global control */ + u32 clkcr; /* 0x04 clock control */ + u32 timeout; /* 0x08 time out */ + u32 width; /* 0x0c bus width */ + u32 blksz; /* 0x10 block size */ + u32 bytecnt; /* 0x14 byte count */ + u32 cmd; /* 0x18 command */ + u32 arg; /* 0x1c argument */ + u32 resp0; /* 0x20 response 0 */ + u32 resp1; /* 0x24 response 1 */ + u32 resp2; /* 0x28 response 2 */ + u32 resp3; /* 0x2c response 3 */ + u32 imask; /* 0x30 interrupt mask */ + u32 mint; /* 0x34 masked interrupt status */ + u32 rint; /* 0x38 raw interrupt status */ + u32 status; /* 0x3c status */ + u32 ftrglevel; /* 0x40 FIFO threshold watermark*/ + u32 funcsel; /* 0x44 function select */ + u32 cbcr; /* 0x48 CIU byte count */ + u32 bbcr; /* 0x4c BIU byte count */ + u32 dbgc; /* 0x50 debug enable */ + u32 res0; /* 0x54 reserved */ + u32 a12a; /* 0x58 Auto command 12 argument */ + u32 ntsr; /* 0x5c New timing set register */ + u32 res1[8]; + u32 dmac; /* 0x80 internal DMA control */ + u32 dlba; /* 0x84 internal DMA descr list base address */ + u32 idst; /* 0x88 internal DMA status */ + u32 idie; /* 0x8c internal DMA interrupt enable */ + u32 chda; /* 0x90 */ + u32 cbda; /* 0x94 */ + u32 res2[26]; +#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) + u32 res3[17]; + u32 samp_dl; + u32 res4[46]; +#endif + u32 fifo; /* 0x100 / 0x200 FIFO access address */ +}; + +#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17) +#define SUNXI_MMC_CLK_ENABLE (0x1 << 16) +#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff) + +#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0) +#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1) +#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2) +#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\ + SUNXI_MMC_GCTRL_FIFO_RESET|\ + SUNXI_MMC_GCTRL_DMA_RESET) +#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5) +#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31) + +#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6) +#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7) +#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8) +#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9) +#define SUNXI_MMC_CMD_WRITE (0x1 << 10) +#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12) +#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13) +#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15) +#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21) +#define SUNXI_MMC_CMD_START (0x1 << 31) + +#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1) +#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2) +#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3) +#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4) +#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5) +#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6) +#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7) +#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8) +#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9) +#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10) +#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11) +#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12) +#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13) +#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14) +#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15) +#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16) +#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30) +#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31) +#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \ + (SUNXI_MMC_RINT_RESP_ERROR | \ + SUNXI_MMC_RINT_RESP_CRC_ERROR | \ + SUNXI_MMC_RINT_DATA_CRC_ERROR | \ + SUNXI_MMC_RINT_RESP_TIMEOUT | \ + SUNXI_MMC_RINT_DATA_TIMEOUT | \ + SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \ + SUNXI_MMC_RINT_FIFO_RUN_ERROR | \ + SUNXI_MMC_RINT_HARD_WARE_LOCKED | \ + SUNXI_MMC_RINT_START_BIT_ERROR | \ + SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */ +#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \ + (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \ + SUNXI_MMC_RINT_DATA_OVER | \ + SUNXI_MMC_RINT_COMMAND_DONE | \ + SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE) + +#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0) +#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1) +#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2) +#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3) +#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8) +#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9) +#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10) + +#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31) + +#define SUNXI_MMC_IDMAC_RESET (0x1 << 0) +#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1) +#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7) + +#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0) +#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1) + +#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16) +#define SUNXI_MMC_COMMON_RESET (1 << 18) + +#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7) + +struct mmc *sunxi_mmc_init(int sdc_no); +#endif /* _SUNXI_MMC_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/p2wi.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/p2wi.h new file mode 100644 index 000000000..5f2a898b3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/p2wi.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Sunxi platform Push-Push i2c register definition. + * + * (c) Copyright 2013 Oliver Schinagl + * http://linux-sunxi.org + * + * (c)Copyright 2006-2013 + * Allwinner Technology Co., Ltd. + * Berg Xing + * Tom Cubie + */ + +#ifndef _SUNXI_P2WI_H +#define _SUNXI_P2WI_H + +#include + +#define P2WI_CTRL_RESET (0x1 << 0) +#define P2WI_CTRL_IRQ_EN (0x1 << 1) +#define P2WI_CTRL_TRANS_ABORT (0x1 << 6) +#define P2WI_CTRL_TRANS_START (0x1 << 7) + +#define __P2WI_CC_CLK(n) (((n) & 0xff) << 0) +#define P2WI_CC_CLK_MASK __P2WI_CC_CLK_DIV(0xff) +#define __P2WI_CC_CLK_DIV(n) (((n) >> 1) - 1) +#define P2WI_CC_CLK_DIV(n) \ + __P2WI_CC_CLK(__P2WI_CC_CLK_DIV(n)) +#define P2WI_CC_SDA_OUT_DELAY(n) (((n) & 0x7) << 8) +#define P2WI_CC_SDA_OUT_DELAY_MASK P2WI_CC_SDA_OUT_DELAY(0x7) + +#define P2WI_IRQ_TRANS_DONE (0x1 << 0) +#define P2WI_IRQ_TRANS_ERR (0x1 << 1) +#define P2WI_IRQ_LOAD_BUSY (0x1 << 2) + +#define P2WI_STAT_TRANS_DONE (0x1 << 0) +#define P2WI_STAT_TRANS_ERR (0x1 << 1) +#define P2WI_STAT_LOAD_BUSY (0x1 << 2) +#define __P2WI_STAT_TRANS_ERR(n) (((n) & 0xff) << 8) +#define P2WI_STAT_TRANS_ERR_MASK __P2WI_STAT_TRANS_ERR_ID(0xff) +#define __P2WI_STAT_TRANS_ERR_BYTE_1 0x01 +#define __P2WI_STAT_TRANS_ERR_BYTE_2 0x02 +#define __P2WI_STAT_TRANS_ERR_BYTE_3 0x04 +#define __P2WI_STAT_TRANS_ERR_BYTE_4 0x08 +#define __P2WI_STAT_TRANS_ERR_BYTE_5 0x10 +#define __P2WI_STAT_TRANS_ERR_BYTE_6 0x20 +#define __P2WI_STAT_TRANS_ERR_BYTE_7 0x40 +#define __P2WI_STAT_TRANS_ERR_BYTE_8 0x80 +#define P2WI_STAT_TRANS_ERR_BYTE_1 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_1) +#define P2WI_STAT_TRANS_ERR_BYTE_2 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_2) +#define P2WI_STAT_TRANS_ERR_BYTE_3 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_3) +#define P2WI_STAT_TRANS_ERR_BYTE_4 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_4) +#define P2WI_STAT_TRANS_ERR_BYTE_5 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_5) +#define P2WI_STAT_TRANS_ERR_BYTE_6 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_6) +#define P2WI_STAT_TRANS_ERR_BYTE_7 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_7) +#define P2WI_STAT_TRANS_ERR_BYTE_8 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_8) + +#define P2WI_DATADDR_BYTE_1(n) (((n) & 0xff) << 0) +#define P2WI_DATADDR_BYTE_1_MASK P2WI_DATADDR_BYTE_1(0xff) +#define P2WI_DATADDR_BYTE_2(n) (((n) & 0xff) << 8) +#define P2WI_DATADDR_BYTE_2_MASK P2WI_DATADDR_BYTE_2(0xff) +#define P2WI_DATADDR_BYTE_3(n) (((n) & 0xff) << 16) +#define P2WI_DATADDR_BYTE_3_MASK P2WI_DATADDR_BYTE_3(0xff) +#define P2WI_DATADDR_BYTE_4(n) (((n) & 0xff) << 24) +#define P2WI_DATADDR_BYTE_4_MASK P2WI_DATADDR_BYTE_4(0xff) +#define P2WI_DATADDR_BYTE_5(n) (((n) & 0xff) << 0) +#define P2WI_DATADDR_BYTE_5_MASK P2WI_DATADDR_BYTE_5(0xff) +#define P2WI_DATADDR_BYTE_6(n) (((n) & 0xff) << 8) +#define P2WI_DATADDR_BYTE_6_MASK P2WI_DATADDR_BYTE_6(0xff) +#define P2WI_DATADDR_BYTE_7(n) (((n) & 0xff) << 16) +#define P2WI_DATADDR_BYTE_7_MASK P2WI_DATADDR_BYTE_7(0xff) +#define P2WI_DATADDR_BYTE_8(n) (((n) & 0xff) << 24) +#define P2WI_DATADDR_BYTE_8_MASK P2WI_DATADDR_BYTE_8(0xff) + +#define __P2WI_DATA_NUM_BYTES(n) (((n) & 0x7) << 0) +#define P2WI_DATA_NUM_BYTES_MASK __P2WI_DATA_NUM_BYTES(0x7) +#define P2WI_DATA_NUM_BYTES(n) __P2WI_DATA_NUM_BYTES((n) - 1) +#define P2WI_DATA_NUM_BYTES_READ (0x1 << 4) + +#define P2WI_DATA_BYTE_1(n) (((n) & 0xff) << 0) +#define P2WI_DATA_BYTE_1_MASK P2WI_DATA_BYTE_1(0xff) +#define P2WI_DATA_BYTE_2(n) (((n) & 0xff) << 8) +#define P2WI_DATA_BYTE_2_MASK P2WI_DATA_BYTE_2(0xff) +#define P2WI_DATA_BYTE_3(n) (((n) & 0xff) << 16) +#define P2WI_DATA_BYTE_3_MASK P2WI_DATA_BYTE_3(0xff) +#define P2WI_DATA_BYTE_4(n) (((n) & 0xff) << 24) +#define P2WI_DATA_BYTE_4_MASK P2WI_DATA_BYTE_4(0xff) +#define P2WI_DATA_BYTE_5(n) (((n) & 0xff) << 0) +#define P2WI_DATA_BYTE_5_MASK P2WI_DATA_BYTE_5(0xff) +#define P2WI_DATA_BYTE_6(n) (((n) & 0xff) << 8) +#define P2WI_DATA_BYTE_6_MASK P2WI_DATA_BYTE_6(0xff) +#define P2WI_DATA_BYTE_7(n) (((n) & 0xff) << 16) +#define P2WI_DATA_BYTE_7_MASK P2WI_DATA_BYTE_7(0xff) +#define P2WI_DATA_BYTE_8(n) (((n) & 0xff) << 24) +#define P2WI_DATA_BYTE_8_MASK P2WI_DATA_BYTE_8(0xff) + +#define P2WI_LINECTRL_SDA_CTRL_EN (0x1 << 0) +#define P2WI_LINECTRL_SDA_OUT_HIGH (0x1 << 1) +#define P2WI_LINECTRL_SCL_CTRL_EN (0x1 << 2) +#define P2WI_LINECTRL_SCL_OUT_HIGH (0x1 << 3) +#define P2WI_LINECTRL_SDA_STATE_HIGH (0x1 << 4) +#define P2WI_LINECTRL_SCL_STATE_HIGH (0x1 << 5) + +#define P2WI_PM_DEV_ADDR(n) (((n) & 0xff) << 0) +#define P2WI_PM_DEV_ADDR_MASK P2WI_PM_DEV_ADDR(0xff) +#define P2WI_PM_CTRL_ADDR(n) (((n) & 0xff) << 8) +#define P2WI_PM_CTRL_ADDR_MASK P2WI_PM_CTRL_ADDR(0xff) +#define P2WI_PM_INIT_DATA(n) (((n) & 0xff) << 16) +#define P2WI_PM_INIT_DATA_MASK P2WI_PM_INIT_DATA(0xff) +#define P2WI_PM_INIT_SEND (0x1 << 31) + +struct sunxi_p2wi_reg { + u32 ctrl; /* 0x00 control */ + u32 cc; /* 0x04 clock control */ + u32 irq; /* 0x08 interrupt */ + u32 status; /* 0x0c status */ + u32 dataddr0; /* 0x10 data address 0 */ + u32 dataddr1; /* 0x14 data address 1 */ + u32 numbytes; /* 0x18 num bytes */ + u32 data0; /* 0x1c data buffer 0 */ + u32 data1; /* 0x20 data buffer 1 */ + u32 linectrl; /* 0x24 line control */ + u32 pm; /* 0x28 power management */ +}; + +void p2wi_init(void); +int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data); +int p2wi_read(const u8 addr, u8 *data); +int p2wi_write(const u8 addr, u8 data); + +#endif /* _SUNXI_P2WI_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/pmic_bus.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/pmic_bus.h new file mode 100644 index 000000000..3ccfe138f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/pmic_bus.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Hans de Goede + * + * Sunxi PMIC bus access helpers header + */ + +#ifndef _SUNXI_PMIC_BUS_H +#define _SUNXI_PMIS_BUS_H + +int pmic_bus_init(void); +int pmic_bus_read(u8 reg, u8 *data); +int pmic_bus_write(u8 reg, u8 data); +int pmic_bus_setbits(u8 reg, u8 bits); +int pmic_bus_clrbits(u8 reg, u8 bits); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/prcm.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/prcm.h new file mode 100644 index 000000000..5106076f5 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/prcm.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2020 Jernej Skrabec + * + * Sunxi platform prcm register definition. + */ + +#ifndef _SUNXI_PRCM_H +#define _SUNXI_PRCM_H + +/* prcm regs definition */ +#if defined(CONFIG_SUN50I_GEN_H6) +#include +#else +#include +#endif + +#endif /* _SUNXI_PRCM_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h new file mode 100644 index 000000000..5f636e838 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Sunxi H6 Power Management Unit register definition. + * + * (C) Copyright 2020 Jernej Skrabec + */ + +#ifndef _SUN50I_PRCM_H +#define _SUN50I_PRCM_H + +#ifndef __ASSEMBLY__ +#include + +struct sunxi_prcm_reg { + u32 cpus_cfg; /* 0x000 */ + u8 res0[0x8]; /* 0x004 */ + u32 apbs1_cfg; /* 0x00c */ + u32 apbs2_cfg; /* 0x010 */ + u8 res1[0x108]; /* 0x014 */ + u32 tmr_gate_reset; /* 0x11c */ + u8 res2[0xc]; /* 0x120 */ + u32 twd_gate_reset; /* 0x12c */ + u8 res3[0xc]; /* 0x130 */ + u32 pwm_gate_reset; /* 0x13c */ + u8 res4[0x4c]; /* 0x140 */ + u32 uart_gate_reset; /* 0x18c */ + u8 res5[0xc]; /* 0x190 */ + u32 twi_gate_reset; /* 0x19c */ + u8 res6[0x1c]; /* 0x1a0 */ + u32 rsb_gate_reset; /* 0x1bc */ + u32 cir_cfg; /* 0x1c0 */ + u8 res7[0x8]; /* 0x1c4 */ + u32 cir_gate_reset; /* 0x1cc */ + u8 res8[0x10]; /* 0x1d0 */ + u32 w1_cfg; /* 0x1e0 */ + u8 res9[0x8]; /* 0x1e4 */ + u32 w1_gate_reset; /* 0x1ec */ + u8 res10[0x1c]; /* 0x1f0 */ + u32 rtc_gate_reset; /* 0x20c */ +}; +check_member(sunxi_prcm_reg, rtc_gate_reset, 0x20c); + +#define PRCM_TWI_GATE (1 << 0) +#define PRCM_TWI_RESET (1 << 16) + +#endif /* __ASSEMBLY__ */ +#endif /* _PRCM_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/prcm_sun6i.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/prcm_sun6i.h new file mode 100644 index 000000000..ab664e80b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/prcm_sun6i.h @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Sunxi A31 Power Management Unit register definition. + * + * (C) Copyright 2013 Oliver Schinagl + * http://linux-sunxi.org + * Allwinner Technology Co., Ltd. + * Berg Xing + * Tom Cubie + */ + +#ifndef _SUN6I_PRCM_H +#define _SUN6I_PRCM_H + +#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4) +#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3) +#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1) +#define PRCM_CPUS_CFG_PRE_DIV(n) \ + __PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n)) +#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8) +#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f) +#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1) +#define PRCM_CPUS_CFG_POST_DIV(n) \ + __PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n)) +#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16) +#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3) +#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0 +#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1 +#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2 +#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3 +#define PRCM_CPUS_CFG_CLK_SRC_LOSC \ + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC) +#define PRCM_CPUS_CFG_CLK_SRC_HOSC \ + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC) +#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \ + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6) +#define PRCM_CPUS_CFG_CLK_SRC_PDIV \ + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV) + +#define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0) +#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3) +#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1) +#define PRCM_APB0_RATIO_DIV(n) \ + __PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n)) + +#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0) +#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1) + +#define PRCM_APB0_GATE_PIO (0x1 << 0) +#define PRCM_APB0_GATE_IR (0x1 << 1) +#define PRCM_APB0_GATE_TIMER01 (0x1 << 2) +#define PRCM_APB0_GATE_P2WI (0x1 << 3) /* sun6i */ +#define PRCM_APB0_GATE_RSB (0x1 << 3) /* sun8i */ +#define PRCM_APB0_GATE_UART (0x1 << 4) +#define PRCM_APB0_GATE_1WIRE (0x1 << 5) +#define PRCM_APB0_GATE_I2C (0x1 << 6) + +#define PRCM_APB0_RESET_PIO (0x1 << 0) +#define PRCM_APB0_RESET_IR (0x1 << 1) +#define PRCM_APB0_RESET_TIMER01 (0x1 << 2) +#define PRCM_APB0_RESET_P2WI (0x1 << 3) +#define PRCM_APB0_RESET_UART (0x1 << 4) +#define PRCM_APB0_RESET_1WIRE (0x1 << 5) +#define PRCM_APB0_RESET_I2C (0x1 << 6) + +#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0) +#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1) +#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4) +#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \ + __PRCM_PLL_CTRL_USB_CLK_SRC(0x3) +#define __PRCM_PLL_CTRL_USB_CLK_0 0x0 +#define __PRCM_PLL_CTRL_USB_CLK_1 0x1 +#define __PRCM_PLL_CTRL_USB_CLK_2 0x2 +#define __PRCM_PLL_CTRL_USB_CLK_3 0x3 +#define PRCM_PLL_CTRL_USB_CLK_0 \ + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0) +#define PRCM_PLL_CTRL_USB_CLK_1 \ + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1) +#define PRCM_PLL_CTRL_USB_CLK_2 \ + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2) +#define PRCM_PLL_CTRL_USB_CLK_3 \ + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_3) +#define __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) (((n) & 0x3) << 12) +#define PRCM_PLL_CTRL_INT_PLL_IN_SEL_MASK \ + __PRCM_PLL_CTRL_INT_PLL_IN_SEL(0x3) +#define PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) \ + __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) +#define __PRCM_PLL_CTRL_HOSC_CLK_SEL(n) (((n) & 0x3) << 20) +#define PRCM_PLL_CTRL_HOSC_CLK_SEL_MASK \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(0x3) +#define __PRCM_PLL_CTRL_HOSC_CLK_0 0x0 +#define __PRCM_PLL_CTRL_HOSC_CLK_1 0x1 +#define __PRCM_PLL_CTRL_HOSC_CLK_2 0x2 +#define __PRCM_PLL_CTRL_HOSC_CLK_3 0x3 +#define PRCM_PLL_CTRL_HOSC_CLK_0 \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_0) +#define PRCM_PLL_CTRL_HOSC_CLK_1 \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_1) +#define PRCM_PLL_CTRL_HOSC_CLK_2 \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_2) +#define PRCM_PLL_CTRL_HOSC_CLK_3 \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_3) +#define PRCM_PLL_CTRL_PLL_TST_SRC_EXT (0x1 << 24) +#define PRCM_PLL_CTRL_LDO_DIGITAL_EN (0x1 << 0) +#define PRCM_PLL_CTRL_LDO_ANALOG_EN (0x1 << 1) +#define PRCM_PLL_CTRL_EXT_OSC_EN (0x1 << 2) +#define PRCM_PLL_CTRL_CLK_TST_EN (0x1 << 3) +#define PRCM_PLL_CTRL_IN_PWR_HIGH (0x1 << 15) /* 3.3 for hi 2.5 for lo */ +#define __PRCM_PLL_CTRL_VDD_LDO_OUT(n) (((n) & 0x7) << 16) +#define PRCM_PLL_CTRL_LDO_OUT_MASK \ + __PRCM_PLL_CTRL_LDO_OUT(0x7) +/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */ +#define PRCM_PLL_CTRL_LDO_OUT_L(n) \ + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7) +#define PRCM_PLL_CTRL_LDO_OUT_H(n) \ + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7) +#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \ + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000) +#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \ + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160) +#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24) +#define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24) + +#define PRCM_CLK_1WIRE_GATE (0x1 << 31) + +#define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0) +#define PRCM_CLK_MOD0_M_MASK __PRCM_CLK_MOD0_M(0xf) +#define __PRCM_CLK_MOD0_M_X(n) (n - 1) +#define PRCM_CLK_MOD0_M(n) __PRCM_CLK_MOD0_M(__PRCM_CLK_MOD0_M_X(n)) +#define PRCM_CLK_MOD0_OUT_PHASE(n) (((n) & 0x7) << 8) +#define PRCM_CLK_MOD0_OUT_PHASE_MASK(n) PRCM_CLK_MOD0_OUT_PHASE(0x7) +#define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16) +#define PRCM_CLK_MOD0_N_MASK __PRCM_CLK_MOD_N(0x3) +#define __PRCM_CLK_MOD0_N_X(n) (((n) >> 1) - 1) +#define PRCM_CLK_MOD0_N(n) __PRCM_CLK_MOD0_N(__PRCM_CLK_MOD0_N_X(n)) +#define PRCM_CLK_MOD0_SMPL_PHASE(n) (((n) & 0x7) << 20) +#define PRCM_CLK_MOD0_SMPL_PHASE_MASK PRCM_CLK_MOD0_SMPL_PHASE(0x7) +#define PRCM_CLK_MOD0_SRC_SEL(n) (((n) & 0x7) << 24) +#define PRCM_CLK_MOD0_SRC_SEL_MASK PRCM_CLK_MOD0_SRC_SEL(0x7) +#define PRCM_CLK_MOD0_GATE_EN (0x1 << 31) + +#define PRCM_APB0_RESET_PIO (0x1 << 0) +#define PRCM_APB0_RESET_IR (0x1 << 1) +#define PRCM_APB0_RESET_TIMER01 (0x1 << 2) +#define PRCM_APB0_RESET_P2WI (0x1 << 3) +#define PRCM_APB0_RESET_UART (0x1 << 4) +#define PRCM_APB0_RESET_1WIRE (0x1 << 5) +#define PRCM_APB0_RESET_I2C (0x1 << 6) + +#define __PRCM_CLK_OUTD_M(n) (((n) & 0x7) << 8) +#define PRCM_CLK_OUTD_M_MASK __PRCM_CLK_OUTD_M(0x7) +#define __PRCM_CLK_OUTD_M_X() ((n) - 1) +#define PRCM_CLK_OUTD_M(n) __PRCM_CLK_OUTD_M(__PRCM_CLK_OUTD_M_X(n)) +#define __PRCM_CLK_OUTD_N(n) (((n) & 0x7) << 20) +#define PRCM_CLK_OUTD_N_MASK __PRCM_CLK_OUTD_N(0x7) +#define __PRCM_CLK_OUTD_N_X(n) (((n) >> 1) - 1) +#define PRCM_CLK_OUTD_N(n) __PRCM_CLK_OUTD_N(__PRCM_CLK_OUTD_N_X(n) +#define __PRCM_CLK_OUTD_SRC_SEL(n) (((n) & 0x3) << 24) +#define PRCM_CLK_OUTD_SRC_SEL_MASK __PRCM_CLK_OUTD_SRC_SEL(0x3) +#define __PRCM_CLK_OUTD_SRC_LOSC2 0x0 +#define __PRCM_CLK_OUTD_SRC_LOSC 0x1 +#define __PRCM_CLK_OUTD_SRC_HOSC 0x2 +#define __PRCM_CLK_OUTD_SRC_ERR 0x3 +#define PRCM_CLK_OUTD_SRC_LOSC2 \ +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC2) +#define PRCM_CLK_OUTD_SRC_LOSC \ +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC) +#define PRCM_CLK_OUTD_SRC_HOSC \ +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_HOSC) +#define PRCM_CLK_OUTD_SRC_ERR \ +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_ERR) +#define PRCM_CLK_OUTD_EN (0x1 << 31) + +#define PRCM_CPU0_PWROFF (0x1 << 0) +#define PRCM_CPU1_PWROFF (0x1 << 1) +#define PRCM_CPU2_PWROFF (0x1 << 2) +#define PRCM_CPU3_PWROFF (0x1 << 3) +#define PRCM_CPU_ALL_PWROFF (0xf << 0) + +#define PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF (0x1 << 0) +#define PRCM_VDD_SYS_DRAM_CH1_PAD_HOLD_PWROFF (0x1 << 1) +#define PRCM_VDD_SYS_AVCC_A_PWROFF (0x1 << 2) +#define PRCM_VDD_SYS_CPU0_VDD_PWROFF (0x1 << 3) + +#define PRCM_VDD_GPU_PWROFF (0x1 << 0) + +#define PRCM_VDD_SYS_RESET (0x1 << 0) + +#define PRCM_CPU1_PWR_CLAMP(n) (((n) & 0xff) << 0) +#define PRCM_CPU1_PWR_CLAMP_MASK PRCM_CPU1_PWR_CLAMP(0xff) + +#define PRCM_CPU2_PWR_CLAMP(n) (((n) & 0xff) << 0) +#define PRCM_CPU2_PWR_CLAMP_MASK PRCM_CPU2_PWR_CLAMP(0xff) + +#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0) +#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff) + +#define PRCM_SEC_SWITCH_APB0_CLK_NONSEC (0x1 << 0) +#define PRCM_SEC_SWITCH_PLL_CFG_NONSEC (0x1 << 1) +#define PRCM_SEC_SWITCH_PWR_GATE_NONSEC (0x1 << 2) + +#ifndef __ASSEMBLY__ +#include + +struct sunxi_prcm_reg { + u32 cpus_cfg; /* 0x000 */ + u8 res0[0x8]; /* 0x004 */ + u32 apb0_ratio; /* 0x00c */ + u32 cpu0_cfg; /* 0x010 */ + u32 cpu1_cfg; /* 0x014 */ + u32 cpu2_cfg; /* 0x018 */ + u32 cpu3_cfg; /* 0x01c */ + u8 res1[0x8]; /* 0x020 */ + u32 apb0_gate; /* 0x028 */ + u8 res2[0x14]; /* 0x02c */ + u32 pll_ctrl0; /* 0x040 */ + u32 pll_ctrl1; /* 0x044 */ + u8 res3[0x8]; /* 0x048 */ + u32 clk_1wire; /* 0x050 */ + u32 clk_ir; /* 0x054 */ + u8 res4[0x58]; /* 0x058 */ + u32 apb0_reset; /* 0x0b0 */ + u8 res5[0x3c]; /* 0x0b4 */ + u32 clk_outd; /* 0x0f0 */ + u8 res6[0xc]; /* 0x0f4 */ + u32 cpu_pwroff; /* 0x100 */ + u8 res7[0xc]; /* 0x104 */ + u32 vdd_sys_pwroff; /* 0x110 */ + u8 res8[0x4]; /* 0x114 */ + u32 gpu_pwroff; /* 0x118 */ + u8 res9[0x4]; /* 0x11c */ + u32 vdd_pwr_reset; /* 0x120 */ + u8 res10[0x1c]; /* 0x124 */ + u32 cpu_pwr_clamp[4]; /* 0x140 but first one is actually unused */ + u8 res11[0x30]; /* 0x150 */ + u32 dram_pwr; /* 0x180 */ + u8 res12[0xc]; /* 0x184 */ + u32 dram_tst; /* 0x190 */ + u8 res13[0x3c]; /* 0x194 */ + u32 prcm_sec_switch; /* 0x1d0 */ +}; + +void prcm_apb0_enable(u32 flags); +void prcm_apb0_disable(u32 flags); + +#endif /* __ASSEMBLY__ */ +#endif /* _PRCM_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/pwm.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/pwm.h new file mode 100644 index 000000000..b89bddd2e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/pwm.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Hans de Goede + */ + +#ifndef _SUNXI_PWM_H +#define _SUNXI_PWM_H + +#ifndef __ASSEMBLY__ +#include +#endif + +#define SUNXI_PWM_CTRL_REG (SUNXI_PWM_BASE + 0) +#define SUNXI_PWM_CH0_PERIOD (SUNXI_PWM_BASE + 4) + +#define SUNXI_PWM_CTRL_PRESCALE0(x) ((x) & 0xf) +#define SUNXI_PWM_CTRL_PRESCALE0_MASK 0xf +#define SUNXI_PWM_CTRL_ENABLE0 (0x5 << 4) +#define SUNXI_PWM_CTRL_POLARITY0(x) ((x) << 5) +#define SUNXI_PWM_CTRL_CH0_ACT_STA BIT(5) +#define SUNXI_PWM_CTRL_CLK_GATE BIT(6) + +#define SUNXI_PWM_CH0_PERIOD_MAX (0xffff) +#define SUNXI_PWM_CH0_PERIOD_PRD(x) ((x & 0xffff) << 16) +#define SUNXI_PWM_CH0_PERIOD_DUTY(x) ((x) & 0xffff) + +#define SUNXI_PWM_PERIOD_80PCT 0x04af03c0 + +#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN5I +#define SUNXI_PWM_PIN0 SUNXI_GPB(2) +#define SUNXI_PWM_MUX SUN4I_GPB_PWM +#endif + +#if defined CONFIG_MACH_SUN6I +#define SUNXI_PWM_PIN0 SUNXI_GPH(13) +#define SUNXI_PWM_MUX SUN6I_GPH_PWM +#endif + +#if defined CONFIG_MACH_SUN8I_A23 || defined CONFIG_MACH_SUN8I_A33 +#define SUNXI_PWM_PIN0 SUNXI_GPH(0) +#define SUNXI_PWM_MUX SUN8I_GPH_PWM +#endif + +struct sunxi_pwm { + u32 ctrl; + u32 ch0_period; +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/rsb.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/rsb.h new file mode 100644 index 000000000..8c64a995f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/rsb.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2014 Hans de Goede + * + * Based on allwinner u-boot sources rsb code which is: + * (C) Copyright 2007-2013 + * Allwinner Technology Co., Ltd. + * lixiang + */ + +#ifndef __SUNXI_RSB_H +#define __SUNXI_RSB_H + +#include + +struct sunxi_rsb_reg { + u32 ctrl; /* 0x00 */ + u32 ccr; /* 0x04 */ + u32 inte; /* 0x08 */ + u32 stat; /* 0x0c */ + u32 addr; /* 0x10 */ + u8 res0[8]; /* 0x14 */ + u32 data; /* 0x1c */ + u8 res1[4]; /* 0x20 */ + u32 lcr; /* 0x24 */ + u32 dmcr; /* 0x28 */ + u32 cmd; /* 0x2c */ + u32 devaddr; /* 0x30 */ +}; + +#define RSB_CTRL_SOFT_RST (1 << 0) +#define RSB_CTRL_START_TRANS (1 << 7) + +#define RSB_STAT_TOVER_INT (1 << 0) +#define RSB_STAT_TERR_INT (1 << 1) +#define RSB_STAT_LBSY_INT (1 << 2) + +#define RSB_DMCR_DEVICE_MODE_DATA 0x7c3e00 +#define RSB_DMCR_DEVICE_MODE_START (1 << 31) + +#define RSB_CMD_BYTE_WRITE 0x4e +#define RSB_CMD_BYTE_READ 0x8b +#define RSB_CMD_SET_RTSADDR 0xe8 + +#define RSB_DEVADDR_RUNTIME_ADDR(x) ((x) << 16) +#define RSB_DEVADDR_DEVICE_ADDR(x) ((x) << 0) + +int rsb_init(void); +int rsb_set_device_address(u16 device_addr, u16 runtime_addr); +int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data); +int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/spl.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/spl.h new file mode 100644 index 000000000..58cdf806d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/spl.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + */ +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_ARCH_SPL_H_ + +#include + +#define SPL_ADDR CONFIG_SUNXI_SRAM_ADDRESS + +/* The low 8-bits of the 'boot_media' field in the SPL header */ +#define SUNXI_BOOTED_FROM_MMC0 0 +#define SUNXI_BOOTED_FROM_NAND 1 +#define SUNXI_BOOTED_FROM_MMC2 2 +#define SUNXI_BOOTED_FROM_SPI 3 +#define SUNXI_BOOTED_FROM_MMC0_HIGH 0x10 +#define SUNXI_BOOTED_FROM_MMC2_HIGH 0x12 + +#define is_boot0_magic(addr) (memcmp((void *)(addr), BOOT0_MAGIC, 8) == 0) + +uint32_t sunxi_get_boot_device(void); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/sys_proto.h new file mode 100644 index 000000000..064602292 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/sys_proto.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Tom Cubie + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +#include + +void sdelay(unsigned long); + +/* return_to_fel() - Return to BROM from SPL + * + * This returns back into the BROM after U-Boot SPL has performed its initial + * init. It uses the provided lr and sp to do so. + * + * @lr: BROM link register value (return address) + * @sp: BROM stack pointer + */ +void return_to_fel(uint32_t lr, uint32_t sp); + +/* Board / SoC level designware gmac init */ +#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUN7I_GMAC +void eth_init_board(void); +#else +static inline void eth_init_board(void) {} +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/timer.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/timer.h new file mode 100644 index 000000000..bb5626d89 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/timer.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * Configuration settings for the Allwinner A10-evb board. + */ + +#ifndef _SUNXI_TIMER_H_ +#define _SUNXI_TIMER_H_ + +#ifndef __ASSEMBLY__ + +#include +#include + +/* General purpose timer */ +struct sunxi_timer { + u32 ctl; + u32 inter; + u32 val; + u8 res[4]; +}; + +/* Audio video sync*/ +struct sunxi_avs { + u32 ctl; /* 0x80 */ + u32 cnt0; /* 0x84 */ + u32 cnt1; /* 0x88 */ + u32 div; /* 0x8c */ +}; + +/* 64 bit counter */ +struct sunxi_64cnt { + u32 ctl; /* 0xa0 */ + u32 lo; /* 0xa4 */ + u32 hi; /* 0xa8 */ +}; + +/* Rtc */ +struct sunxi_rtc { + u32 ctl; /* 0x100 */ + u32 yymmdd; /* 0x104 */ + u32 hhmmss; /* 0x108 */ +}; + +/* Alarm */ +struct sunxi_alarm { + u32 ddhhmmss; /* 0x10c */ + u32 hhmmss; /* 0x110 */ + u32 en; /* 0x114 */ + u32 irqen; /* 0x118 */ + u32 irqsta; /* 0x11c */ +}; + +/* Timer general purpose register */ +struct sunxi_tgp { + u32 tgpd; +}; + +struct sunxi_timer_reg { + u32 tirqen; /* 0x00 */ + u32 tirqsta; /* 0x04 */ + u8 res1[8]; + struct sunxi_timer timer[6]; /* We have 6 timers */ + u8 res2[16]; + struct sunxi_avs avs; +#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40) + struct sunxi_wdog wdog; /* 0x90 */ + /* XXX the following is not accurate for sun5i/sun7i */ + struct sunxi_64cnt cnt64; /* 0xa0 */ + u8 res4[0x58]; + struct sunxi_rtc rtc; + struct sunxi_alarm alarm; + struct sunxi_tgp tgp[4]; + u8 res5[8]; + u32 cpu_cfg; +#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) + u8 res3[16]; + struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */ +#endif +}; + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/tve.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/tve.h new file mode 100644 index 000000000..46cd87e79 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/tve.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Sunxi TV encoder register and constant defines + * + * (C) Copyright 2014 Hans de Goede + * (C) Copyright 2017 Jernej Skrabec + */ + +#ifndef _TVE_H +#define _TVE_H + +enum tve_mode { + tve_mode_vga, + tve_mode_composite_pal, + tve_mode_composite_ntsc, + tve_mode_composite_pal_m, + tve_mode_composite_pal_nc, +}; + +/* + * This is based on the A10s User Manual, and the A10s only supports + * composite video and not vga like the A10 / A20 does, still other + * than the removed vga out capability the tvencoder seems to be the same. + * "unknown#" registers are registers which are used in the A10 kernel code, + * but not documented in the A10s User Manual. + */ +struct sunxi_tve_reg { + u32 gctrl; /* 0x000 */ + u32 cfg0; /* 0x004 */ + u32 dac_cfg0; /* 0x008 */ + u32 filter; /* 0x00c */ + u32 chroma_freq; /* 0x010 */ + u32 porch_num; /* 0x014 */ + u32 unknown0; /* 0x018 */ + u32 line_num; /* 0x01c */ + u32 blank_black_level; /* 0x020 */ + u32 unknown1; /* 0x024, seems to be 1 byte per dac */ + u8 res0[0x08]; /* 0x028 */ + u32 auto_detect_en; /* 0x030 */ + u32 auto_detect_int_status; /* 0x034 */ + u32 auto_detect_status; /* 0x038 */ + u32 auto_detect_debounce; /* 0x03c */ + u32 csc_reg0; /* 0x040 */ + u32 csc_reg1; /* 0x044 */ + u32 csc_reg2; /* 0x048 */ + u32 csc_reg3; /* 0x04c */ + u8 res1[0xb0]; /* 0x050 */ + u32 color_burst; /* 0x100 */ + u32 vsync_num; /* 0x104 */ + u32 notch_freq; /* 0x108 */ + u32 cbr_level; /* 0x10c */ + u32 burst_phase; /* 0x110 */ + u32 burst_width; /* 0x114 */ + u32 unknown2; /* 0x118 */ + u32 sync_vbi_level; /* 0x11c */ + u32 white_level; /* 0x120 */ + u32 active_num; /* 0x124 */ + u32 chroma_bw_gain; /* 0x128 */ + u32 notch_width; /* 0x12c */ + u32 resync_num; /* 0x130 */ + u32 slave_para; /* 0x134 */ + u32 cfg1; /* 0x138 */ + u32 cfg2; /* 0x13c */ +}; + +/* + * TVE register constants. + */ +#define SUNXI_TVE_GCTRL_ENABLE (1 << 0) +/* + * Select input 0 to disable dac, 1 - 4 to feed dac from tve0, 5 - 8 to feed + * dac from tve1. When using tve1 the mux value must be written to both tve0's + * and tve1's gctrl reg. + */ +#define SUNXI_TVE_GCTRL_DAC_INPUT_MASK(dac) (0xf << (((dac) + 1) * 4)) +#define SUNXI_TVE_GCTRL_DAC_INPUT(dac, sel) ((sel) << (((dac) + 1) * 4)) +#define SUNXI_TVE_CFG0_VGA 0x20000000 +#define SUNXI_TVE_CFG0_PAL 0x07030001 +#define SUNXI_TVE_CFG0_NTSC 0x07030000 +#define SUNXI_TVE_DAC_CFG0_VGA 0x403e1ac7 +#ifdef CONFIG_MACH_SUN5I +#define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x433f0009 +#else +#define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x403f0008 +#endif +#define SUNXI_TVE_FILTER_COMPOSITE 0x00000120 +#define SUNXI_TVE_CHROMA_FREQ_PAL_M 0x21e6efe3 +#define SUNXI_TVE_CHROMA_FREQ_PAL_NC 0x21f69446 +#define SUNXI_TVE_PORCH_NUM_PAL 0x008a0018 +#define SUNXI_TVE_PORCH_NUM_NTSC 0x00760020 +#define SUNXI_TVE_LINE_NUM_PAL 0x00160271 +#define SUNXI_TVE_LINE_NUM_NTSC 0x0016020d +#define SUNXI_TVE_BLANK_BLACK_LEVEL_PAL 0x00fc00fc +#define SUNXI_TVE_BLANK_BLACK_LEVEL_NTSC 0x00f0011a +#define SUNXI_TVE_UNKNOWN1_VGA 0x00000000 +#define SUNXI_TVE_UNKNOWN1_COMPOSITE 0x18181818 +#define SUNXI_TVE_AUTO_DETECT_EN_DET_EN(dac) (1 << ((dac) + 0)) +#define SUNXI_TVE_AUTO_DETECT_EN_INT_EN(dac) (1 << ((dac) + 16)) +#define SUNXI_TVE_AUTO_DETECT_INT_STATUS(dac) (1 << ((dac) + 0)) +#define SUNXI_TVE_AUTO_DETECT_STATUS_SHIFT(dac) ((dac) * 8) +#define SUNXI_TVE_AUTO_DETECT_STATUS_MASK(dac) (3 << ((dac) * 8)) +#define SUNXI_TVE_AUTO_DETECT_STATUS_NONE 0 +#define SUNXI_TVE_AUTO_DETECT_STATUS_CONNECTED 1 +#define SUNXI_TVE_AUTO_DETECT_STATUS_SHORT_GND 3 +#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_SHIFT(d) ((d) * 8) +#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_MASK(d) (0xf << ((d) * 8)) +#define SUNXI_TVE_CSC_REG0_ENABLE (1 << 31) +#define SUNXI_TVE_CSC_REG0 0x08440832 +#define SUNXI_TVE_CSC_REG1 0x3b6dace1 +#define SUNXI_TVE_CSC_REG2 0x0e1d13dc +#define SUNXI_TVE_CSC_REG3 0x00108080 +#define SUNXI_TVE_COLOR_BURST_PAL_M 0x00000000 +#define SUNXI_TVE_CBR_LEVEL_PAL 0x00002828 +#define SUNXI_TVE_CBR_LEVEL_NTSC 0x0000004f +#define SUNXI_TVE_BURST_PHASE_NTSC 0x00000000 +#define SUNXI_TVE_BURST_WIDTH_COMPOSITE 0x0016447e +#define SUNXI_TVE_UNKNOWN2_PAL 0x0000e0e0 +#define SUNXI_TVE_UNKNOWN2_NTSC 0x0000a0a0 +#define SUNXI_TVE_SYNC_VBI_LEVEL_NTSC 0x001000f0 +#define SUNXI_TVE_ACTIVE_NUM_COMPOSITE 0x000005a0 +#define SUNXI_TVE_CHROMA_BW_GAIN_COMP 0x00000002 +#define SUNXI_TVE_NOTCH_WIDTH_COMPOSITE 0x00000101 +#define SUNXI_TVE_RESYNC_NUM_PAL 0x800d000c +#define SUNXI_TVE_RESYNC_NUM_NTSC 0x000e000c +#define SUNXI_TVE_SLAVE_PARA_COMPOSITE 0x00000000 + +void tvencoder_mode_set(struct sunxi_tve_reg * const tve, enum tve_mode mode); +void tvencoder_enable(struct sunxi_tve_reg * const tve); + +#endif /* _TVE_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/tzpc.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/tzpc.h new file mode 100644 index 000000000..7a6fcaebd --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/tzpc.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Chen-Yu Tsai + */ + +#ifndef _SUNXI_TZPC_H +#define _SUNXI_TZPC_H + +#ifndef __ASSEMBLY__ +struct sunxi_tzpc { + u32 r0size; /* 0x00 Size of secure RAM region */ + u32 decport0_status; /* 0x04 Status of decode protection port 0 */ + u32 decport0_set; /* 0x08 Set decode protection port 0 */ + u32 decport0_clear; /* 0x0c Clear decode protection port 0 */ + /* For A80 and later SoCs */ + u32 decport1_status; /* 0x10 Status of decode protection port 1 */ + u32 decport1_set; /* 0x14 Set decode protection port 1 */ + u32 decport1_clear; /* 0x18 Clear decode protection port 1 */ + u32 decport2_status; /* 0x1c Status of decode protection port 2 */ + u32 decport2_set; /* 0x20 Set decode protection port 2 */ + u32 decport2_clear; /* 0x24 Clear decode protection port 2 */ +}; +#endif + +#define SUN6I_TZPC_DECPORT0_RTC (1 << 1) + +#define SUN8I_H3_TZPC_DECPORT0_ALL 0xbe +#define SUN8I_H3_TZPC_DECPORT1_ALL 0xff +#define SUN8I_H3_TZPC_DECPORT2_ALL 0x7f + +void tzpc_init(void); + +#endif /* _SUNXI_TZPC_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-sunxi/watchdog.h b/roms/u-boot/arch/arm/include/asm/arch-sunxi/watchdog.h new file mode 100644 index 000000000..38e2ef2ac --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-sunxi/watchdog.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2014 + * Chen-Yu Tsai + * + * Watchdog register definitions + */ + +#ifndef _SUNXI_WATCHDOG_H_ +#define _SUNXI_WATCHDOG_H_ + +#define WDT_CTRL_RESTART (0x1 << 0) +#define WDT_CTRL_KEY (0x0a57 << 1) + +#if defined(CONFIG_MACH_SUN4I) || \ + defined(CONFIG_MACH_SUN5I) || \ + defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + +#define WDT_MODE_EN (0x1 << 0) +#define WDT_MODE_RESET_EN (0x1 << 1) + +struct sunxi_wdog { + u32 ctl; /* 0x00 */ + u32 mode; /* 0x04 */ + u32 res[2]; +}; + +#else + +#define WDT_CFG_RESET (0x1) +#define WDT_MODE_EN (0x1) + +struct sunxi_wdog { + u32 irq_en; /* 0x00 */ + u32 irq_sta; /* 0x04 */ + u32 res1[2]; + u32 ctl; /* 0x10 */ + u32 cfg; /* 0x14 */ + u32 mode; /* 0x18 */ + u32 res2; +}; + +#endif + +#endif /* _SUNXI_WATCHDOG_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/ap.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/ap.h new file mode 100644 index 000000000..de21dffa5 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/ap.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010-2015 + * NVIDIA Corporation + */ +#include + +/* Stabilization delays, in usec */ +#define PLL_STABILIZATION_DELAY (300) +#define IO_STABILIZATION_DELAY (1000) + +#define PLLX_ENABLED (1 << 30) +#define CCLK_BURST_POLICY 0x20008888 +#define SUPER_CCLK_DIVIDER 0x80000000 + +/* Calculate clock fractional divider value from ref and target frequencies */ +#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) + +/* Calculate clock frequency value from reference and clock divider value */ +#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) + +/* AVP/CPU ID */ +#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ +#define PG_UP_TAG_0 0x0 + +/* AP base physical address of internal SRAM */ +#define NV_PA_BASE_SRAM 0x40000000 + +#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) +#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) +#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) + +#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) +#define FLOW_MODE_STOP 2 +#define HALT_COP_EVENT_JTAG (1 << 28) +#define HALT_COP_EVENT_IRQ_1 (1 << 11) +#define HALT_COP_EVENT_FIQ_1 (1 << 9) + +/* This is the main entry into U-Boot, used by the Cortex-A9 */ +extern void _start(void); + +/** + * Works out the SOC/SKU type used for clocks settings + * + * @return SOC type - see TEGRA_SOC... + */ +int tegra_get_chip_sku(void); + +/** + * Returns the pure SOC (chip ID) from the HIDREV register + * + * @return SOC ID - see CHIPID_TEGRAxx... + */ +int tegra_get_chip(void); + +/** + * Returns the SKU ID from the sku_info register + * + * @return SKU ID - see SKU_ID_Txx... + */ +int tegra_get_sku_info(void); + +/* Do any chip-specific cache config */ +void config_cache(void); + +#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) +bool tegra_cpu_is_non_secure(void); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/apb_misc.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/apb_misc.h new file mode 100644 index 000000000..d438966af --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/apb_misc.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2012 The Chromium OS Authors. + */ + +#ifndef _GP_PADCTRL_H_ +#define _GP_PADCTRL_H_ + +/* APB_MISC_PP registers */ +struct apb_misc_pp_ctlr { + u32 reserved0[2]; + u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */ + u32 reserved1[6]; /* 0x0c .. 0x20 */ + u32 cfg_ctl; /* 0x24 */ +}; + +/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */ +#define RAM_CODE_SHIFT 4 +#define RAM_CODE_MASK (0xf << RAM_CODE_SHIFT) + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/board.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/board.h new file mode 100644 index 000000000..24d0db8ce --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/board.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + */ + +#ifndef _TEGRA_BOARD_H_ +#define _TEGRA_BOARD_H_ + +/* Set up pinmux to make UART usable */ +void gpio_early_init_uart(void); + +/* Set up early UART output */ +void board_init_uart_f(void); + +/* Set up any early GPIOs the board might need for proper operation */ +void gpio_early_init(void); /* overrideable GPIO config */ + +/* + * Hooks to allow boards to set up the pinmux for a specific function. + * Has to be implemented in the board files as we don't yet support pinmux + * setup from FDT. If a board file does not implement one of those functions + * an empty stub function will be called. + */ + +void pinmux_init(void); /* overridable general pinmux setup */ +void pin_mux_usb(void); /* overridable USB pinmux setup */ +void pin_mux_spi(void); /* overridable SPI pinmux setup */ +void pin_mux_nand(void); /* overridable NAND pinmux setup */ +void pin_mux_mmc(void); /* overridable mmc pinmux setup */ +void pin_mux_display(void); /* overridable DISPLAY pinmux setup */ + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/bpmp_abi.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/bpmp_abi.h new file mode 100644 index 000000000..373da526e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/bpmp_abi.h @@ -0,0 +1,1590 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2014-2016, NVIDIA CORPORATION. + */ + +#ifndef _ABI_BPMP_ABI_H_ +#define _ABI_BPMP_ABI_H_ + +#ifdef LK +#include +#endif + +#ifndef __ABI_PACKED +#define __ABI_PACKED __attribute__((packed)) +#endif + +#ifdef NO_GCC_EXTENSIONS +#define EMPTY char empty; +#define EMPTY_ARRAY 1 +#else +#define EMPTY +#define EMPTY_ARRAY 0 +#endif + +#ifndef __UNION_ANON +#define __UNION_ANON +#endif +/** + * @file + */ + + +/** + * @defgroup MRQ MRQ Messages + * @brief Messages sent to/from BPMP via IPC + * @{ + * @defgroup MRQ_Format Message Format + * @defgroup MRQ_Codes Message Request (MRQ) Codes + * @defgroup MRQ_Payloads Message Payloads + * @defgroup Error_Codes Error Codes + * @} + */ + +/** + * @addtogroup MRQ_Format Message Format + * @{ + * The CPU requests the BPMP to perform a particular service by + * sending it an IVC frame containing a single MRQ message. An MRQ + * message consists of a @ref mrq_request followed by a payload whose + * format depends on mrq_request::mrq. + * + * The BPMP processes the data and replies with an IVC frame (on the + * same IVC channel) containing and MRQ response. An MRQ response + * consists of a @ref mrq_response followed by a payload whose format + * depends on the associated mrq_request::mrq. + * + * A well-defined subset of the MRQ messages that the CPU sends to the + * BPMP can lead to BPMP eventually sending an MRQ message to the + * CPU. For example, when the CPU uses an #MRQ_THERMAL message to set + * a thermal trip point, the BPMP may eventually send a single + * #MRQ_THERMAL message of its own to the CPU indicating that the trip + * point has been crossed. + * @} + */ + +/** + * @ingroup MRQ_Format + * @brief header for an MRQ message + * + * Provides the MRQ number for the MRQ message: #mrq. The remainder of + * the MRQ message is a payload (immediately following the + * mrq_request) whose format depends on mrq. + * + * @todo document the flags + */ +struct mrq_request { + /** @brief MRQ number of the request */ + uint32_t mrq; + /** @brief flags for the request */ + uint32_t flags; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Format + * @brief header for an MRQ response + * + * Provides an error code for the associated MRQ message. The + * remainder of the MRQ response is a payload (immediately following + * the mrq_response) whose format depends on the associated + * mrq_request::mrq + * + * @todo document the flags + */ +struct mrq_response { + /** @brief error code for the MRQ request itself */ + int32_t err; + /** @brief flags for the response */ + uint32_t flags; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Format + * Minimum needed size for an IPC message buffer + */ +#define MSG_MIN_SZ 128 +/** + * @ingroup MRQ_Format + * Minimum size guaranteed for data in an IPC message buffer + */ +#define MSG_DATA_MIN_SZ 120 + +/** + * @ingroup MRQ_Codes + * @name Legal MRQ codes + * These are the legal values for mrq_request::mrq + * @{ + */ + +#define MRQ_PING 0 +#define MRQ_QUERY_TAG 1 +#define MRQ_MODULE_LOAD 4 +#define MRQ_MODULE_UNLOAD 5 +#define MRQ_TRACE_MODIFY 7 +#define MRQ_WRITE_TRACE 8 +#define MRQ_THREADED_PING 9 +#define MRQ_MODULE_MAIL 11 +#define MRQ_DEBUGFS 19 +#define MRQ_RESET 20 +#define MRQ_I2C 21 +#define MRQ_CLK 22 +#define MRQ_QUERY_ABI 23 +#define MRQ_PG_READ_STATE 25 +#define MRQ_PG_UPDATE_STATE 26 +#define MRQ_THERMAL 27 +#define MRQ_CPU_VHINT 28 +#define MRQ_ABI_RATCHET 29 +#define MRQ_EMC_DVFS_LATENCY 31 +#define MRQ_TRACE_ITER 64 + +/** @} */ + +/** + * @ingroup MRQ_Codes + * @brief Maximum MRQ code to be sent by CPU software to + * BPMP. Subject to change in future + */ +#define MAX_CPU_MRQ_ID 64 + +/** + * @addtogroup MRQ_Payloads Message Payloads + * @{ + * @defgroup Ping + * @defgroup Query_Tag Query Tag + * @defgroup Module Loadable Modules + * @defgroup Trace + * @defgroup Debugfs + * @defgroup Reset + * @defgroup I2C + * @defgroup Clocks + * @defgroup ABI_info ABI Info + * @defgroup MC_Flush MC Flush + * @defgroup Powergating + * @defgroup Thermal + * @defgroup Vhint CPU Voltage hint + * @defgroup MRQ_Deprecated Deprecated MRQ messages + * @defgroup EMC + * @} + */ + + +/** + * @ingroup MRQ_Codes + * @def MRQ_PING + * @brief A simple ping + * + * * Platforms: All + * * Initiators: Any + * * Targets: Any + * * Request Payload: @ref mrq_ping_request + * * Response Payload: @ref mrq_ping_response + * + * @ingroup MRQ_Codes + * @def MRQ_THREADED_PING + * @brief A deeper ping + * + * * Platforms: All + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_ping_request + * * Response Payload: @ref mrq_ping_response + * + * Behavior is equivalent to a simple #MRQ_PING except that BPMP + * responds from a thread context (providing a slightly more robust + * sign of life). + * + */ + +/** + * @ingroup Ping + * @brief request with #MRQ_PING + * + * Used by the sender of an #MRQ_PING message to request a pong from + * recipient. The response from the recipient is computed based on + * #challenge. + */ +struct mrq_ping_request { +/** @brief arbitrarily chosen value */ + uint32_t challenge; +} __ABI_PACKED; + +/** + * @ingroup Ping + * @brief response to #MRQ_PING + * + * Sent in response to an #MRQ_PING message. #reply should be the + * mrq_ping_request challenge left shifted by 1 with the carry-bit + * dropped. + * + */ +struct mrq_ping_response { + /** @brief response to the MRQ_PING challege */ + uint32_t reply; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_QUERY_TAG + * @brief Query BPMP firmware's tag (i.e. version information) + * + * * Platforms: All + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_query_tag_request + * * Response Payload: N/A + * + */ + +/** + * @ingroup Query_Tag + * @brief request with #MRQ_QUERY_TAG + * + * Used by #MRQ_QUERY_TAG call to ask BPMP to fill in the memory + * pointed by #addr with BPMP firmware header. + * + * The sender is reponsible for ensuring that #addr is mapped in to + * the recipient's address map. + */ +struct mrq_query_tag_request { + /** @brief base address to store the firmware header */ + uint32_t addr; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_MODULE_LOAD + * @brief dynamically load a BPMP code module + * + * * Platforms: All + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_module_load_request + * * Response Payload: @ref mrq_module_load_response + * + * @note This MRQ is disabled on production systems + * + */ + +/** + * @ingroup Module + * @brief request with #MRQ_MODULE_LOAD + * + * Used by #MRQ_MODULE_LOAD calls to ask the recipient to dynamically + * load the code located at #phys_addr and having size #size + * bytes. #phys_addr is treated as a void pointer. + * + * The recipient copies the code from #phys_addr to locally allocated + * memory prior to responding to this message. + * + * @todo document the module header format + * + * The sender is responsible for ensuring that the code is mapped in + * the recipient's address map. + * + */ +struct mrq_module_load_request { + /** @brief base address of the code to load. Treated as (void *) */ + uint32_t phys_addr; /* (void *) */ + /** @brief size in bytes of code to load */ + uint32_t size; +} __ABI_PACKED; + +/** + * @ingroup Module + * @brief response to #MRQ_MODULE_LOAD + * + * @todo document mrq_response::err + */ +struct mrq_module_load_response { + /** @brief handle to the loaded module */ + uint32_t base; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_MODULE_UNLOAD + * @brief unload a previously loaded code module + * + * * Platforms: All + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_module_unload_request + * * Response Payload: N/A + * + * @note This MRQ is disabled on production systems + */ + +/** + * @ingroup Module + * @brief request with #MRQ_MODULE_UNLOAD + * + * Used by #MRQ_MODULE_UNLOAD calls to request that a previously loaded + * module be unloaded. + */ +struct mrq_module_unload_request { + /** @brief handle of the module to unload */ + uint32_t base; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_TRACE_MODIFY + * @brief modify the set of enabled trace events + * + * * Platforms: All + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_trace_modify_request + * * Response Payload: @ref mrq_trace_modify_response + * + * @note This MRQ is disabled on production systems + */ + +/** + * @ingroup Trace + * @brief request with #MRQ_TRACE_MODIFY + * + * Used by %MRQ_TRACE_MODIFY calls to enable or disable specify trace + * events. #set takes precedence for any bit set in both #set and + * #clr. + */ +struct mrq_trace_modify_request { + /** @brief bit mask of trace events to disable */ + uint32_t clr; + /** @brief bit mask of trace events to enable */ + uint32_t set; +} __ABI_PACKED; + +/** + * @ingroup Trace + * @brief response to #MRQ_TRACE_MODIFY + * + * Sent in repsonse to an #MRQ_TRACE_MODIFY message. #mask reflects the + * state of which events are enabled after the recipient acted on the + * message. + * + */ +struct mrq_trace_modify_response { + /** @brief bit mask of trace event enable states */ + uint32_t mask; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_WRITE_TRACE + * @brief Write trace data to a buffer + * + * * Platforms: All + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_write_trace_request + * * Response Payload: @ref mrq_write_trace_response + * + * mrq_response::err depends on the @ref mrq_write_trace_request field + * values. err is -#BPMP_EINVAL if size is zero or area is NULL or + * area is in an illegal range. A positive value for err indicates the + * number of bytes written to area. + * + * @note This MRQ is disabled on production systems + */ + +/** + * @ingroup Trace + * @brief request with #MRQ_WRITE_TRACE + * + * Used by MRQ_WRITE_TRACE calls to ask the recipient to copy trace + * data from the recipient's local buffer to the output buffer. #area + * is treated as a byte-aligned pointer in the recipient's address + * space. + * + * The sender is responsible for ensuring that the output + * buffer is mapped in the recipient's address map. The recipient is + * responsible for protecting its own code and data from accidental + * overwrites. + */ +struct mrq_write_trace_request { + /** @brief base address of output buffer */ + uint32_t area; + /** @brief size in bytes of the output buffer */ + uint32_t size; +} __ABI_PACKED; + +/** + * @ingroup Trace + * @brief response to #MRQ_WRITE_TRACE + * + * Once this response is sent, the respondent will not access the + * output buffer further. + */ +struct mrq_write_trace_response { + /** + * @brief flag whether more data remains in local buffer + * + * Value is 1 if the entire local trace buffer has been + * drained to the outputbuffer. Value is 0 otherwise. + */ + uint32_t eof; +} __ABI_PACKED; + +/** @private */ +struct mrq_threaded_ping_request { + uint32_t challenge; +} __ABI_PACKED; + +/** @private */ +struct mrq_threaded_ping_response { + uint32_t reply; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_MODULE_MAIL + * @brief send a message to a loadable module + * + * * Platforms: All + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_module_mail_request + * * Response Payload: @ref mrq_module_mail_response + * + * @note This MRQ is disabled on production systems + */ + +/** + * @ingroup Module + * @brief request with #MRQ_MODULE_MAIL + */ +struct mrq_module_mail_request { + /** @brief handle to the previously loaded module */ + uint32_t base; + /** @brief module-specific mail payload + * + * The length of data[ ] is unknown to the BPMP core firmware + * but it is limited to the size of an IPC message. + */ + uint8_t data[EMPTY_ARRAY]; +} __ABI_PACKED; + +/** + * @ingroup Module + * @brief response to #MRQ_MODULE_MAIL + */ +struct mrq_module_mail_response { + /** @brief module-specific mail payload + * + * The length of data[ ] is unknown to the BPMP core firmware + * but it is limited to the size of an IPC message. + */ + uint8_t data[EMPTY_ARRAY]; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_DEBUGFS + * @brief Interact with BPMP's debugfs file nodes + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_debugfs_request + * * Response Payload: @ref mrq_debugfs_response + */ + +/** + * @addtogroup Debugfs + * @{ + * + * The BPMP firmware implements a pseudo-filesystem called + * debugfs. Any driver within the firmware may register with debugfs + * to expose an arbitrary set of "files" in the filesystem. When + * software on the CPU writes to a debugfs file, debugfs passes the + * written data to a callback provided by the driver. When software on + * the CPU reads a debugfs file, debugfs queries the driver for the + * data to return to the CPU. The intention of the debugfs filesystem + * is to provide information useful for debugging the system at + * runtime. + * + * @note The files exposed via debugfs are not part of the + * BPMP firmware's ABI. debugfs files may be added or removed in any + * given version of the firmware. Typically the semantics of a debugfs + * file are consistent from version to version but even that is not + * guaranteed. + * + * @} + */ +/** @ingroup Debugfs */ +enum mrq_debugfs_commands { + CMD_DEBUGFS_READ = 1, + CMD_DEBUGFS_WRITE = 2, + CMD_DEBUGFS_DUMPDIR = 3, + CMD_DEBUGFS_MAX +}; + +/** + * @ingroup Debugfs + * @brief parameters for CMD_DEBUGFS_READ/WRITE command + */ +struct cmd_debugfs_fileop_request { + /** @brief physical address pointing at filename */ + uint32_t fnameaddr; + /** @brief length in bytes of filename buffer */ + uint32_t fnamelen; + /** @brief physical address pointing to data buffer */ + uint32_t dataaddr; + /** @brief length in bytes of data buffer */ + uint32_t datalen; +} __ABI_PACKED; + +/** + * @ingroup Debugfs + * @brief parameters for CMD_DEBUGFS_READ/WRITE command + */ +struct cmd_debugfs_dumpdir_request { + /** @brief physical address pointing to data buffer */ + uint32_t dataaddr; + /** @brief length in bytes of data buffer */ + uint32_t datalen; +} __ABI_PACKED; + +/** + * @ingroup Debugfs + * @brief response data for CMD_DEBUGFS_READ/WRITE command + */ +struct cmd_debugfs_fileop_response { + /** @brief always 0 */ + uint32_t reserved; + /** @brief number of bytes read from or written to data buffer */ + uint32_t nbytes; +} __ABI_PACKED; + +/** + * @ingroup Debugfs + * @brief response data for CMD_DEBUGFS_DUMPDIR command + */ +struct cmd_debugfs_dumpdir_response { + /** @brief always 0 */ + uint32_t reserved; + /** @brief number of bytes read from or written to data buffer */ + uint32_t nbytes; +} __ABI_PACKED; + +/** + * @ingroup Debugfs + * @brief request with #MRQ_DEBUGFS. + * + * The sender of an MRQ_DEBUGFS message uses #cmd to specify a debugfs + * command to execute. Legal commands are the values of @ref + * mrq_debugfs_commands. Each command requires a specific additional + * payload of data. + * + * |command |payload| + * |-------------------|-------| + * |CMD_DEBUGFS_READ |fop | + * |CMD_DEBUGFS_WRITE |fop | + * |CMD_DEBUGFS_DUMPDIR|dumpdir| + */ +struct mrq_debugfs_request { + uint32_t cmd; + union { + struct cmd_debugfs_fileop_request fop; + struct cmd_debugfs_dumpdir_request dumpdir; + } __UNION_ANON; +} __ABI_PACKED; + +/** + * @ingroup Debugfs + */ +struct mrq_debugfs_response { + /** @brief always 0 */ + int32_t reserved; + union { + /** @brief response data for CMD_DEBUGFS_READ OR + * CMD_DEBUGFS_WRITE command + */ + struct cmd_debugfs_fileop_response fop; + /** @brief response data for CMD_DEBUGFS_DUMPDIR command */ + struct cmd_debugfs_dumpdir_response dumpdir; + } __UNION_ANON; +} __ABI_PACKED; + +/** + * @addtogroup Debugfs + * @{ + */ +#define DEBUGFS_S_ISDIR (1 << 9) +#define DEBUGFS_S_IRUSR (1 << 8) +#define DEBUGFS_S_IWUSR (1 << 7) +/** @} */ + + +/** + * @ingroup MRQ_Codes + * @def MRQ_RESET + * @brief reset an IP block + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_reset_request + * * Response Payload: N/A + */ + +/** + * @ingroup Reset + */ +enum mrq_reset_commands { + CMD_RESET_ASSERT = 1, + CMD_RESET_DEASSERT = 2, + CMD_RESET_MODULE = 3, + CMD_RESET_MAX, /* not part of ABI and subject to change */ +}; + +/** + * @ingroup Reset + * @brief request with MRQ_RESET + * + * Used by the sender of an #MRQ_RESET message to request BPMP to + * assert or or deassert a given reset line. + */ +struct mrq_reset_request { + /** @brief reset action to perform (@enum mrq_reset_commands) */ + uint32_t cmd; + /** @brief id of the reset to affected */ + uint32_t reset_id; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_I2C + * @brief issue an i2c transaction + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_i2c_request + * * Response Payload: @ref mrq_i2c_response + */ + +/** + * @addtogroup I2C + * @{ + */ +#define TEGRA_I2C_IPC_MAX_IN_BUF_SIZE (MSG_DATA_MIN_SZ - 12) +#define TEGRA_I2C_IPC_MAX_OUT_BUF_SIZE (MSG_DATA_MIN_SZ - 4) +/** @} */ + +/** + * @ingroup I2C + * @name Serial I2C flags + * Use these flags with serial_i2c_request::flags + * @{ + */ +#define SERIALI2C_TEN 0x0010 +#define SERIALI2C_RD 0x0001 +#define SERIALI2C_STOP 0x8000 +#define SERIALI2C_NOSTART 0x4000 +#define SERIALI2C_REV_DIR_ADDR 0x2000 +#define SERIALI2C_IGNORE_NAK 0x1000 +#define SERIALI2C_NO_RD_ACK 0x0800 +#define SERIALI2C_RECV_LEN 0x0400 +/** @} */ +/** @ingroup I2C */ +enum { + CMD_I2C_XFER = 1 +}; + +/** + * @ingroup I2C + * @brief serializable i2c request + * + * Instances of this structure are packed (little-endian) into + * cmd_i2c_xfer_request::data_buf. Each instance represents a single + * transaction (or a portion of a transaction with repeated starts) on + * an i2c bus. + * + * Because these structures are packed, some instances are likely to + * be misaligned. Additionally because #data is variable length, it is + * not possible to iterate through a serialized list of these + * structures without inspecting #len in each instance. It may be + * easier to serialize or deserialize cmd_i2c_xfer_request::data_buf + * manually rather than using this structure definition. +*/ +struct serial_i2c_request { + /** @brief I2C slave address */ + uint16_t addr; + /** @brief bitmask of SERIALI2C_ flags */ + uint16_t flags; + /** @brief length of I2C transaction in bytes */ + uint16_t len; + /** @brief for write transactions only, #len bytes of data */ + uint8_t data[]; +} __ABI_PACKED; + +/** + * @ingroup I2C + * @brief trigger one or more i2c transactions + */ +struct cmd_i2c_xfer_request { + /** @brief valid bus number from mach-t186/i2c-t186.h*/ + uint32_t bus_id; + + /** @brief count of valid bytes in #data_buf*/ + uint32_t data_size; + + /** @brief serialized packed instances of @ref serial_i2c_request*/ + uint8_t data_buf[TEGRA_I2C_IPC_MAX_IN_BUF_SIZE]; +} __ABI_PACKED; + +/** + * @ingroup I2C + * @brief container for data read from the i2c bus + * + * Processing an cmd_i2c_xfer_request::data_buf causes BPMP to execute + * zero or more I2C reads. The data read from the bus is serialized + * into #data_buf. + */ +struct cmd_i2c_xfer_response { + /** @brief count of valid bytes in #data_buf*/ + uint32_t data_size; + /** @brief i2c read data */ + uint8_t data_buf[TEGRA_I2C_IPC_MAX_OUT_BUF_SIZE]; +} __ABI_PACKED; + +/** + * @ingroup I2C + * @brief request with #MRQ_I2C + */ +struct mrq_i2c_request { + /** @brief always CMD_I2C_XFER (i.e. 1) */ + uint32_t cmd; + /** @brief parameters of the transfer request */ + struct cmd_i2c_xfer_request xfer; +} __ABI_PACKED; + +/** + * @ingroup I2C + * @brief response to #MRQ_I2C + */ +struct mrq_i2c_response { + struct cmd_i2c_xfer_response xfer; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_CLK + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_clk_request + * * Response Payload: @ref mrq_clk_response + * @addtogroup Clocks + * @{ + */ + +/** + * @name MRQ_CLK sub-commands + * @{ + */ +enum { + CMD_CLK_GET_RATE = 1, + CMD_CLK_SET_RATE = 2, + CMD_CLK_ROUND_RATE = 3, + CMD_CLK_GET_PARENT = 4, + CMD_CLK_SET_PARENT = 5, + CMD_CLK_IS_ENABLED = 6, + CMD_CLK_ENABLE = 7, + CMD_CLK_DISABLE = 8, + CMD_CLK_GET_ALL_INFO = 14, + CMD_CLK_GET_MAX_CLK_ID = 15, + CMD_CLK_MAX, +}; +/** @} */ + +#define MRQ_CLK_NAME_MAXLEN 40 +#define MRQ_CLK_MAX_PARENTS 16 + +/** @private */ +struct cmd_clk_get_rate_request { + EMPTY +} __ABI_PACKED; + +struct cmd_clk_get_rate_response { + int64_t rate; +} __ABI_PACKED; + +struct cmd_clk_set_rate_request { + int32_t unused; + int64_t rate; +} __ABI_PACKED; + +struct cmd_clk_set_rate_response { + int64_t rate; +} __ABI_PACKED; + +struct cmd_clk_round_rate_request { + int32_t unused; + int64_t rate; +} __ABI_PACKED; + +struct cmd_clk_round_rate_response { + int64_t rate; +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_get_parent_request { + EMPTY +} __ABI_PACKED; + +struct cmd_clk_get_parent_response { + uint32_t parent_id; +} __ABI_PACKED; + +struct cmd_clk_set_parent_request { + uint32_t parent_id; +} __ABI_PACKED; + +struct cmd_clk_set_parent_response { + uint32_t parent_id; +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_is_enabled_request { + EMPTY +} __ABI_PACKED; + +struct cmd_clk_is_enabled_response { + int32_t state; +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_enable_request { + EMPTY +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_enable_response { + EMPTY +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_disable_request { + EMPTY +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_disable_response { + EMPTY +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_get_all_info_request { + EMPTY +} __ABI_PACKED; + +struct cmd_clk_get_all_info_response { + uint32_t flags; + uint32_t parent; + uint32_t parents[MRQ_CLK_MAX_PARENTS]; + uint8_t num_parents; + uint8_t name[MRQ_CLK_NAME_MAXLEN]; +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_get_max_clk_id_request { + EMPTY +} __ABI_PACKED; + +struct cmd_clk_get_max_clk_id_response { + uint32_t max_id; +} __ABI_PACKED; +/** @} */ + +/** + * @ingroup Clocks + * @brief request with #MRQ_CLK + * + * Used by the sender of an #MRQ_CLK message to control clocks. The + * clk_request is split into several sub-commands. Some sub-commands + * require no additional data. Others have a sub-command specific + * payload + * + * |sub-command |payload | + * |----------------------------|-----------------------| + * |CMD_CLK_GET_RATE |- | + * |CMD_CLK_SET_RATE |clk_set_rate | + * |CMD_CLK_ROUND_RATE |clk_round_rate | + * |CMD_CLK_GET_PARENT |- | + * |CMD_CLK_SET_PARENT |clk_set_parent | + * |CMD_CLK_IS_ENABLED |- | + * |CMD_CLK_ENABLE |- | + * |CMD_CLK_DISABLE |- | + * |CMD_CLK_GET_ALL_INFO |- | + * |CMD_CLK_GET_MAX_CLK_ID |- | + * + */ + +struct mrq_clk_request { + /** @brief sub-command and clock id concatenated to 32-bit word. + * - bits[31..24] is the sub-cmd. + * - bits[23..0] is the clock id + */ + uint32_t cmd_and_id; + + union { + /** @private */ + struct cmd_clk_get_rate_request clk_get_rate; + struct cmd_clk_set_rate_request clk_set_rate; + struct cmd_clk_round_rate_request clk_round_rate; + /** @private */ + struct cmd_clk_get_parent_request clk_get_parent; + struct cmd_clk_set_parent_request clk_set_parent; + /** @private */ + struct cmd_clk_enable_request clk_enable; + /** @private */ + struct cmd_clk_disable_request clk_disable; + /** @private */ + struct cmd_clk_is_enabled_request clk_is_enabled; + /** @private */ + struct cmd_clk_get_all_info_request clk_get_all_info; + /** @private */ + struct cmd_clk_get_max_clk_id_request clk_get_max_clk_id; + } __UNION_ANON; +} __ABI_PACKED; + +/** + * @ingroup Clocks + * @brief response to MRQ_CLK + * + * Each sub-command supported by @ref mrq_clk_request may return + * sub-command-specific data. Some do and some do not as indicated in + * the following table + * + * |sub-command |payload | + * |----------------------------|------------------------| + * |CMD_CLK_GET_RATE |clk_get_rate | + * |CMD_CLK_SET_RATE |clk_set_rate | + * |CMD_CLK_ROUND_RATE |clk_round_rate | + * |CMD_CLK_GET_PARENT |clk_get_parent | + * |CMD_CLK_SET_PARENT |clk_set_parent | + * |CMD_CLK_IS_ENABLED |clk_is_enabled | + * |CMD_CLK_ENABLE |- | + * |CMD_CLK_DISABLE |- | + * |CMD_CLK_GET_ALL_INFO |clk_get_all_info | + * |CMD_CLK_GET_MAX_CLK_ID |clk_get_max_id | + * + */ + +struct mrq_clk_response { + union { + struct cmd_clk_get_rate_response clk_get_rate; + struct cmd_clk_set_rate_response clk_set_rate; + struct cmd_clk_round_rate_response clk_round_rate; + struct cmd_clk_get_parent_response clk_get_parent; + struct cmd_clk_set_parent_response clk_set_parent; + /** @private */ + struct cmd_clk_enable_response clk_enable; + /** @private */ + struct cmd_clk_disable_response clk_disable; + struct cmd_clk_is_enabled_response clk_is_enabled; + struct cmd_clk_get_all_info_response clk_get_all_info; + struct cmd_clk_get_max_clk_id_response clk_get_max_clk_id; + } __UNION_ANON; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_QUERY_ABI + * @brief check if an MRQ is implemented + * + * * Platforms: All + * * Initiators: Any + * * Targets: Any + * * Request Payload: @ref mrq_query_abi_request + * * Response Payload: @ref mrq_query_abi_response + */ + +/** + * @ingroup ABI_info + * @brief request with MRQ_QUERY_ABI + * + * Used by #MRQ_QUERY_ABI call to check if MRQ code #mrq is supported + * by the recipient. + */ +struct mrq_query_abi_request { + /** @brief MRQ code to query */ + uint32_t mrq; +} __ABI_PACKED; + +/** + * @ingroup ABI_info + * @brief response to MRQ_QUERY_ABI + */ +struct mrq_query_abi_response { + /** @brief 0 if queried MRQ is supported. Else, -#BPMP_ENODEV */ + int32_t status; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_PG_READ_STATE + * @brief read the power-gating state of a partition + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_pg_read_state_request + * * Response Payload: @ref mrq_pg_read_state_response + * @addtogroup Powergating + * @{ + */ + +/** + * @brief request with #MRQ_PG_READ_STATE + * + * Used by MRQ_PG_READ_STATE call to read the current state of a + * partition. + */ +struct mrq_pg_read_state_request { + /** @brief ID of partition */ + uint32_t partition_id; +} __ABI_PACKED; + +/** + * @brief response to MRQ_PG_READ_STATE + * @todo define possible errors. + */ +struct mrq_pg_read_state_response { + /** @brief read as don't care */ + uint32_t sram_state; + /** @brief state of power partition + * * 0 : off + * * 1 : on + */ + uint32_t logic_state; +} __ABI_PACKED; + +/** @} */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_PG_UPDATE_STATE + * @brief modify the power-gating state of a partition + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_pg_update_state_request + * * Response Payload: N/A + * @addtogroup Powergating + * @{ + */ + +/** + * @brief request with mrq_pg_update_state_request + * + * Used by #MRQ_PG_UPDATE_STATE call to request BPMP to change the + * state of a power partition #partition_id. + */ +struct mrq_pg_update_state_request { + /** @brief ID of partition */ + uint32_t partition_id; + /** @brief secondary control of power partition + * @details Ignored by many versions of the BPMP + * firmware. For maximum compatibility, set the value + * according to @logic_state + * * 0x1: power ON partition (@ref logic_state == 0x3) + * * 0x3: power OFF partition (@ref logic_state == 0x1) + */ + uint32_t sram_state; + /** @brief controls state of power partition, legal values are + * * 0x1 : power OFF partition + * * 0x3 : power ON partition + */ + uint32_t logic_state; + /** @brief change state of clocks of the power partition, legal values + * * 0x0 : do not change clock state + * * 0x1 : disable partition clocks (only applicable when + * @ref logic_state == 0x1) + * * 0x3 : enable partition clocks (only applicable when + * @ref logic_state == 0x3) + */ + uint32_t clock_state; +} __ABI_PACKED; +/** @} */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_THERMAL + * @brief interact with BPMP thermal framework + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: Any + * * Request Payload: TODO + * * Response Payload: TODO + * + * @addtogroup Thermal + * + * The BPMP firmware includes a thermal framework. Drivers within the + * bpmp firmware register with the framework to provide thermal + * zones. Each thermal zone corresponds to an entity whose temperature + * can be measured. The framework also has a notion of trip points. A + * trip point consists of a thermal zone id, a temperature, and a + * callback routine. The framework invokes the callback when the zone + * hits the indicated temperature. The BPMP firmware uses this thermal + * framework interally to implement various temperature-dependent + * functions. + * + * Software on the CPU can use #MRQ_THERMAL (with payload @ref + * mrq_thermal_host_to_bpmp_request) to interact with the BPMP thermal + * framework. The CPU must It can query the number of supported zones, + * query zone temperatures, and set trip points. + * + * When a trip point set by the CPU gets crossed, BPMP firmware issues + * an IPC to the CPU having mrq_request::mrq = #MRQ_THERMAL and a + * payload of @ref mrq_thermal_bpmp_to_host_request. + * @{ + */ +enum mrq_thermal_host_to_bpmp_cmd { + /** + * @brief Check whether the BPMP driver supports the specified + * request type. + * + * Host needs to supply request parameters. + * + * mrq_response::err is 0 if the specified request is + * supported and -#BPMP_ENODEV otherwise. + */ + CMD_THERMAL_QUERY_ABI = 0, + + /** + * @brief Get the current temperature of the specified zone. + * + * Host needs to supply request parameters. + * + * mrq_response::err is + * * 0: Temperature query succeeded. + * * -#BPMP_EINVAL: Invalid request parameters. + * * -#BPMP_ENOENT: No driver registered for thermal zone.. + * * -#BPMP_EFAULT: Problem reading temperature measurement. + */ + CMD_THERMAL_GET_TEMP = 1, + + /** + * @brief Enable or disable and set the lower and upper + * thermal limits for a thermal trip point. Each zone has + * one trip point. + * + * Host needs to supply request parameters. Once the + * temperature hits a trip point, the BPMP will send a message + * to the CPU having MRQ=MRQ_THERMAL and + * type=CMD_THERMAL_HOST_TRIP_REACHED + * + * mrq_response::err is + * * 0: Trip successfully set. + * * -#BPMP_EINVAL: Invalid request parameters. + * * -#BPMP_ENOENT: No driver registered for thermal zone. + * * -#BPMP_EFAULT: Problem setting trip point. + */ + CMD_THERMAL_SET_TRIP = 2, + + /** + * @brief Get the number of supported thermal zones. + * + * No request parameters required. + * + * mrq_response::err is always 0, indicating success. + */ + CMD_THERMAL_GET_NUM_ZONES = 3, + + /** @brief: number of supported host-to-bpmp commands. May + * increase in future + */ + CMD_THERMAL_HOST_TO_BPMP_NUM +}; + +enum mrq_thermal_bpmp_to_host_cmd { + /** + * @brief Indication that the temperature for a zone has + * exceeded the range indicated in the thermal trip point + * for the zone. + * + * BPMP needs to supply request parameters. Host only needs to + * acknowledge. + */ + CMD_THERMAL_HOST_TRIP_REACHED = 100, + + /** @brief: number of supported bpmp-to-host commands. May + * increase in future + */ + CMD_THERMAL_BPMP_TO_HOST_NUM +}; + +/* + * Host->BPMP request data for request type CMD_THERMAL_QUERY_ABI + * + * zone: Request type for which to check existence. + */ +struct cmd_thermal_query_abi_request { + uint32_t type; +} __ABI_PACKED; + +/* + * Host->BPMP request data for request type CMD_THERMAL_GET_TEMP + * + * zone: Number of thermal zone. + */ +struct cmd_thermal_get_temp_request { + uint32_t zone; +} __ABI_PACKED; + +/* + * BPMP->Host reply data for request CMD_THERMAL_GET_TEMP + * + * error: 0 if request succeeded. + * -BPMP_EINVAL if request parameters were invalid. + * -BPMP_ENOENT if no driver was registered for the specified thermal zone. + * -BPMP_EFAULT for other thermal zone driver errors. + * temp: Current temperature in millicelsius. + */ +struct cmd_thermal_get_temp_response { + int32_t temp; +} __ABI_PACKED; + +/* + * Host->BPMP request data for request type CMD_THERMAL_SET_TRIP + * + * zone: Number of thermal zone. + * low: Temperature of lower trip point in millicelsius + * high: Temperature of upper trip point in millicelsius + * enabled: 1 to enable trip point, 0 to disable trip point + */ +struct cmd_thermal_set_trip_request { + uint32_t zone; + int32_t low; + int32_t high; + uint32_t enabled; +} __ABI_PACKED; + +/* + * BPMP->Host request data for request type CMD_THERMAL_HOST_TRIP_REACHED + * + * zone: Number of thermal zone where trip point was reached. + */ +struct cmd_thermal_host_trip_reached_request { + uint32_t zone; +} __ABI_PACKED; + +/* + * BPMP->Host reply data for request type CMD_THERMAL_GET_NUM_ZONES + * + * num: Number of supported thermal zones. The thermal zones are indexed + * starting from zero. + */ +struct cmd_thermal_get_num_zones_response { + uint32_t num; +} __ABI_PACKED; + +/* + * Host->BPMP request data. + * + * Reply type is union mrq_thermal_bpmp_to_host_response. + * + * type: Type of request. Values listed in enum mrq_thermal_type. + * data: Request type specific parameters. + */ +struct mrq_thermal_host_to_bpmp_request { + uint32_t type; + union { + struct cmd_thermal_query_abi_request query_abi; + struct cmd_thermal_get_temp_request get_temp; + struct cmd_thermal_set_trip_request set_trip; + } __UNION_ANON; +} __ABI_PACKED; + +/* + * BPMP->Host request data. + * + * type: Type of request. Values listed in enum mrq_thermal_type. + * data: Request type specific parameters. + */ +struct mrq_thermal_bpmp_to_host_request { + uint32_t type; + union { + struct cmd_thermal_host_trip_reached_request host_trip_reached; + } __UNION_ANON; +} __ABI_PACKED; + +/* + * Data in reply to a Host->BPMP request. + */ +union mrq_thermal_bpmp_to_host_response { + struct cmd_thermal_get_temp_response get_temp; + struct cmd_thermal_get_num_zones_response get_num_zones; +} __ABI_PACKED; +/** @} */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_CPU_VHINT + * @brief Query CPU voltage hint data + * + * * Platforms: T186 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_cpu_vhint_request + * * Response Payload: N/A + * + * @addtogroup Vhint CPU Voltage hint + * @{ + */ + +/** + * @brief request with #MRQ_CPU_VHINT + * + * Used by #MRQ_CPU_VHINT call by CCPLEX to retrieve voltage hint data + * from BPMP to memory space pointed by #addr. CCPLEX is responsible + * to allocate sizeof(cpu_vhint_data) sized block of memory and + * appropriately map it for BPMP before sending the request. + */ +struct mrq_cpu_vhint_request { + /** @brief IOVA address for the #cpu_vhint_data */ + uint32_t addr; /* struct cpu_vhint_data * */ + /** @brief ID of the cluster whose data is requested */ + uint32_t cluster_id; /* enum cluster_id */ +} __ABI_PACKED; + +/** + * @brief description of the CPU v/f relation + * + * Used by #MRQ_CPU_VHINT call to carry data pointed by #addr of + * struct mrq_cpu_vhint_request + */ +struct cpu_vhint_data { + uint32_t ref_clk_hz; /**< reference frequency in Hz */ + uint16_t pdiv; /**< post divider value */ + uint16_t mdiv; /**< input divider value */ + uint16_t ndiv_max; /**< fMAX expressed with max NDIV value */ + /** table of ndiv values as a function of vINDEX (voltage index) */ + uint16_t ndiv[80]; + /** minimum allowed NDIV value */ + uint16_t ndiv_min; + /** minimum allowed voltage hint value (as in vINDEX) */ + uint16_t vfloor; + /** maximum allowed voltage hint value (as in vINDEX) */ + uint16_t vceil; + /** post-multiplier for vindex value */ + uint16_t vindex_mult; + /** post-divider for vindex value */ + uint16_t vindex_div; + /** reserved for future use */ + uint16_t reserved[328]; +} __ABI_PACKED; + +/** @} */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_ABI_RATCHET + * @brief ABI ratchet value query + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_abi_ratchet_request + * * Response Payload: @ref mrq_abi_ratchet_response + * @addtogroup ABI_info + * @{ + */ + +/** + * @brief an ABI compatibility mechanism + * + * BPMP_ABI_RATCHET_VALUE may increase for various reasons in a future + * revision of this header file. + * 1. That future revision deprecates some MRQ + * 2. That future revision introduces a breaking change to an existing + * MRQ or + * 3. A bug is discovered in an existing implementation of the BPMP-FW + * (or possibly one of its clients) which warrants deprecating that + * implementation. + */ +#define BPMP_ABI_RATCHET_VALUE 3 + +/** + * @brief request with #MRQ_ABI_RATCHET. + * + * #ratchet should be #BPMP_ABI_RATCHET_VALUE from the ABI header + * against which the requester was compiled. + * + * If ratchet is less than BPMP's #BPMP_ABI_RATCHET_VALUE, BPMP may + * reply with mrq_response::err = -#BPMP_ERANGE to indicate that + * BPMP-FW cannot interoperate correctly with the requester. Requester + * should cease further communication with BPMP. + * + * Otherwise, err shall be 0. + */ +struct mrq_abi_ratchet_request { + /** @brief requester's ratchet value */ + uint16_t ratchet; +}; + +/** + * @brief response to #MRQ_ABI_RATCHET + * + * #ratchet shall be #BPMP_ABI_RATCHET_VALUE from the ABI header + * against which BPMP firwmare was compiled. + * + * If #ratchet is less than the requester's #BPMP_ABI_RATCHET_VALUE, + * the requster must either interoperate with BPMP according to an ABI + * header version with BPMP_ABI_RATCHET_VALUE = ratchet or cease + * communication with BPMP. + * + * If mrq_response::err is 0 and ratchet is greater than or equal to the + * requester's BPMP_ABI_RATCHET_VALUE, the requester should continue + * normal operation. + */ +struct mrq_abi_ratchet_response { + /** @brief BPMP's ratchet value */ + uint16_t ratchet; +}; +/** @} */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_EMC_DVFS_LATENCY + * @brief query frequency dependent EMC DVFS latency + * + * * Platforms: T186 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: N/A + * * Response Payload: @ref mrq_emc_dvfs_latency_response + * @addtogroup EMC + * @{ + */ + +/** + * @brief used by @ref mrq_emc_dvfs_latency_response + */ +struct emc_dvfs_latency { + /** @brief EMC frequency in kHz */ + uint32_t freq; + /** @brief EMC DVFS latency in nanoseconds */ + uint32_t latency; +} __ABI_PACKED; + +#define EMC_DVFS_LATENCY_MAX_SIZE 14 +/** + * @brief response to #MRQ_EMC_DVFS_LATENCY + */ +struct mrq_emc_dvfs_latency_response { + /** @brief the number valid entries in #pairs */ + uint32_t num_pairs; + /** @brief EMC information */ + struct emc_dvfs_latency pairs[EMC_DVFS_LATENCY_MAX_SIZE]; +} __ABI_PACKED; + +/** @} */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_TRACE_ITER + * @brief manage the trace iterator + * + * * Platforms: All + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: N/A + * * Response Payload: @ref mrq_trace_iter_request + * @addtogroup Trace + * @{ + */ +enum { + /** @brief (re)start the tracing now. Ignore older events */ + TRACE_ITER_INIT = 0, + /** @brief clobber all events in the trace buffer */ + TRACE_ITER_CLEAN = 1 +}; + +/** + * @brief request with #MRQ_TRACE_ITER + */ +struct mrq_trace_iter_request { + /** @brief TRACE_ITER_INIT or TRACE_ITER_CLEAN */ + uint32_t cmd; +} __ABI_PACKED; + +/** @} */ + +/* + * 4. Enumerations + */ + +/* + * 4.1 CPU enumerations + * + * See + * + * 4.2 CPU Cluster enumerations + * + * See + * + * 4.3 System low power state enumerations + * + * See + */ + +/* + * 4.4 Clock enumerations + * + * For clock enumerations, see + */ + +/* + * 4.5 Reset enumerations + * + * For reset enumerations, see + */ + +/* + * 4.6 Thermal sensor enumerations + * + * For thermal sensor enumerations, see + */ + +/** + * @defgroup Error_Codes + * Negative values for mrq_response::err generally indicate some + * error. The ABI defines the following error codes. Negating these + * defines is an exercise left to the user. + * @{ + */ +/** @brief No such file or directory */ +#define BPMP_ENOENT 2 +/** @brief No MRQ handler */ +#define BPMP_ENOHANDLER 3 +/** @brief I/O error */ +#define BPMP_EIO 5 +/** @brief Bad sub-MRQ command */ +#define BPMP_EBADCMD 6 +/** @brief Not enough memory */ +#define BPMP_ENOMEM 12 +/** @brief Permission denied */ +#define BPMP_EACCES 13 +/** @brief Bad address */ +#define BPMP_EFAULT 14 +/** @brief No such device */ +#define BPMP_ENODEV 19 +/** @brief Argument is a directory */ +#define BPMP_EISDIR 21 +/** @brief Invalid argument */ +#define BPMP_EINVAL 22 +/** @brief Timeout during operation */ +#define BPMP_ETIMEDOUT 23 +/** @brief Out of range */ +#define BPMP_ERANGE 34 +/** @} */ +/** @} */ +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/cboot.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/cboot.h new file mode 100644 index 000000000..4e1da98d1 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/cboot.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 NVIDIA Corporation. All rights reserved. + */ + +#ifndef _TEGRA_CBOOT_H_ +#define _TEGRA_CBOOT_H_ + +#include + +#ifdef CONFIG_ARM64 + +extern unsigned long cboot_boot_x0; + +void cboot_save_boot_params(unsigned long x0, unsigned long x1, + unsigned long x2, unsigned long x3); +int cboot_dram_init(void); +int cboot_dram_init_banksize(void); +ulong cboot_get_usable_ram_top(ulong total_size); +int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN]); +#else +static inline void cboot_save_boot_params(unsigned long x0, unsigned long x1, + unsigned long x2, unsigned long x3) +{ +} + +static inline int cboot_dram_init(void) +{ + return -ENOSYS; +} + +static inline int cboot_dram_init_banksize(void) +{ + return -ENOSYS; +} + +static inline ulong cboot_get_usable_ram_top(ulong total_size) +{ + return 0; +} + +static inline int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN]) +{ + return -ENOSYS; +} +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/clk_rst.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/clk_rst.h new file mode 100644 index 000000000..2359e142f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -0,0 +1,451 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010-2014 + * NVIDIA Corporation + */ + +#ifndef _TEGRA_CLK_RST_H_ +#define _TEGRA_CLK_RST_H_ + +/* PLL registers - there are several PLLs in the clock controller */ +struct clk_pll { + uint pll_base; /* the control register */ + /* pll_out[0] is output A control, pll_out[1] is output B control */ + uint pll_out[2]; + uint pll_misc; /* other misc things */ +}; + +/* PLL registers - there are several PLLs in the clock controller */ +struct clk_pll_simple { + uint pll_base; /* the control register */ + uint pll_misc; /* other misc things */ +}; + +struct clk_pllm { + uint pllm_base; /* the control register */ + uint pllm_out; /* output control */ + uint pllm_misc1; /* misc1 */ + uint pllm_misc2; /* misc2 */ +}; + +/* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */ +struct clk_set_clr { + uint set; + uint clr; +}; + +/* + * Most PLLs use the clk_pll structure, but some have a simpler two-member + * structure for which we use clk_pll_simple. The reason for this non- + * othogonal setup is not stated. + */ +enum { + TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */ + TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */ + TEGRA_CLK_REGS = 3, /* Number of clock enable regs L/H/U */ + TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */ + TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */ + TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */ + TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */ + TEGRA_CLK_SOURCES_Y = 18, /* Number of ppl clock sources Y */ +}; + +/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ +struct clk_rst_ctlr { + uint crc_rst_src; /* _RST_SOURCE_0,0x00 */ + uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */ + uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */ + uint crc_reserved0; /* reserved_0, 0x1C */ + uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */ + uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */ + uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ + uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */ + uint crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */ + uint crc_prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */ + uint crc_aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38 */ + uint crc_reserved1; /* reserved_1, 0x3C */ + uint crc_cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */ + uint crc_clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */ + uint crc_misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */ + uint crc_clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */ + uint crc_osc_ctrl; /* _OSC_CTRL_0, 0x50 */ + uint crc_pll_lfsr; /* _PLL_LFSR_0, 0x54 */ + uint crc_osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */ + uint crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */ + uint crc_reserved2[8]; /* reserved_2[8], 0x60-7C */ + + struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */ + + /* PLLs from 0xe0 to 0xf4 */ + struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS]; + + uint crc_reserved10; /* _reserved_10, 0xF8 */ + uint crc_reserved11; /* _reserved_11, 0xFC */ + + uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */ + + uint crc_reserved20[32]; /* _reserved_20, 0x200-27c */ + + uint crc_clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ + uint crc_clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ + uint crc_clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ + + uint crc_rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */ + uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ + uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ + + uint crc_clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */ + uint crc_clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */ + uint crc_clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */ + + uint crc_rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */ + uint crc_rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */ + uint crc_rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */ + + uint crc_reserved21[17]; /* _reserved_21, 0x2b0-2f0 */ + + uint crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */ + + uint crc_reserved22[2]; /* _reserved_22, 0x2f8-2fc */ + + /* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */ + struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS]; + + uint crc_reserved30[2]; /* _reserved_30, 0x318, 0x31c */ + + /* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */ + struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS]; + + uint crc_reserved31[2]; /* _reserved_31, 0x338, 0x33c */ + + uint crc_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */ + uint crc_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */ + + /* Additional (T30) registers */ + uint crc_clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */ + uint crc_clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */ + + uint crc_reserved32[2]; /* _reserved_32, 0x350,0x354 */ + + uint crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */ + uint crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */ + uint crc_cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */ + uint crc_super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */ + uint crc_cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */ + uint crc_super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */ + uint crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */ + uint crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */ + uint crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */ + uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */ + uint crc_cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */ + uint crc_reserved33[9]; /* _reserved_33, 0x38c-3ac */ + uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* 0x3B0-0x42C */ + /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */ + struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW]; + /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */ + struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW]; + /* Additional (T114+) registers */ + uint crc_rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */ + uint crc_rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */ + uint crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */ + uint crc_rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45C */ + uint crc_clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */ + uint crc_clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */ + uint crc_clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */ + uint crc_clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46C */ + uint crc_cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */ + uint crc_reserved40[1]; /* _reserved_40, 0x474 */ + uint crc_intstatus; /* __INTSTATUS_0, 0x478 */ + uint crc_intmask; /* __INTMASK_0, 0x47C */ + uint crc_utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */ + uint crc_utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */ + uint crc_utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */ + + uint crc_plle_aux; /* _PLLE_AUX_0, 0x48C */ + uint crc_sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */ + uint crc_sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */ + uint crc_pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */ + + uint crc_prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49C */ + uint crc_audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */ + uint crc_audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */ + uint crc_audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */ + uint crc_audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */ + uint crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */ + uint crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */ + + uint crc_plld2_base; /* _PLLD2_BASE_0, 0x4B8 */ + uint crc_plld2_misc; /* _PLLD2_MISC_0, 0x4BC */ + uint crc_utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */ + uint crc_pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */ + uint crc_pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */ + uint crs_reserved_50[7]; /* _reserved_50, 0x4CC-0x4E4 */ + uint crc_pllc2_base; /* _PLLC2_BASE_0, 0x4E8 */ + uint crc_pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4EC */ + uint crc_pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4F0 */ + uint crc_pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4F4 */ + uint crc_pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4F8 */ + uint crc_pllc3_base; /* _PLLC3_BASE_0, 0x4FC */ + uint crc_pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */ + uint crc_pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */ + uint crc_pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */ + uint crc_pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50C */ + uint crc_pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */ + uint crc_pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */ + uint crc_pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */ + uint crc_xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51C */ + uint crc_xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */ + uint crc_plle_aux1; /* _PLLE_AUX1_0, 0x524 */ + uint crc_pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */ + uint crc_utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */ + uint crc_pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */ + uint crc_xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */ + uint crc_reserved51[1]; /* _reserved_51, 0x538 */ + uint crc_clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53C */ + uint crc_clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */ + uint crc_clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */ + uint crc_pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */ + uint crc_pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54C */ + uint crc_pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */ + uint crc_reserved52[1]; /* _reserved_52, 0x554 */ + uint crc_super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */ + uint crc_spare_reg0; /* _SPARE_REG0_0, 0x55C */ + u32 _rsv32[4]; /* 0x560-0x56c */ + u32 crc_plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */ + u32 _rsv32_1[7]; /* 0x574-58c */ + struct clk_pll_simple plldp; /* _PLLDP_BASE, 0x590 _PLLDP_MISC */ + u32 crc_plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ + + /* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */ + uint _rsrv32_2[25]; /* _0x59C - 0x5FC */ + uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */ + + /* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */ + uint crc_reserved61[5]; /* _reserved_61, 0x680 - 0x690 */ + /* + * NOTE: PLLA1 regs are in the middle of this Y region. Break this in + * two later if PLLA1 is needed, but for now this is cleaner. + */ + uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */ +}; + +/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */ +#define CPU3_CLK_STP_SHIFT 11 +#define CPU2_CLK_STP_SHIFT 10 +#define CPU1_CLK_STP_SHIFT 9 +#define CPU0_CLK_STP_SHIFT 8 +#define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT) + +/* CLK_RST_CONTROLLER_PLLx_BASE_0 */ +#define PLL_BYPASS_SHIFT 31 +#define PLL_BYPASS_MASK (1U << PLL_BYPASS_SHIFT) + +#define PLL_ENABLE_SHIFT 30 +#define PLL_ENABLE_MASK (1U << PLL_ENABLE_SHIFT) + +#define PLL_BASE_OVRRIDE_MASK (1U << 28) + +#define PLL_LOCK_SHIFT 27 +#define PLL_LOCK_MASK (1U << PLL_LOCK_SHIFT) + +/* CLK_RST_CONTROLLER_PLLx_OUTx_0 */ +#define PLL_OUT_RSTN (1 << 0) +#define PLL_OUT_CLKEN (1 << 1) +#define PLL_OUT_OVRRIDE (1 << 2) + +#define PLL_OUT_RATIO_SHIFT 8 +#define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT) + +/* CLK_RST_CONTROLLER_PLLx_MISC_0 */ +#define PLL_DCCON_SHIFT 20 +#define PLL_DCCON_MASK (1U << PLL_DCCON_SHIFT) + +#define PLLP_OUT1_OVR (1 << 2) +#define PLLP_OUT2_OVR (1 << 18) +#define PLLP_OUT3_OVR (1 << 2) +#define PLLP_OUT4_OVR (1 << 18) +#define PLLP_OUT1_RATIO 8 +#define PLLP_OUT2_RATIO 24 +#define PLLP_OUT3_RATIO 8 +#define PLLP_OUT4_RATIO 24 + +enum { + IN_408_OUT_204_DIVISOR = 2, + IN_408_OUT_102_DIVISOR = 6, + IN_408_OUT_48_DIVISOR = 15, + IN_408_OUT_9_6_DIVISOR = 83, +}; + +#define PLLP_OUT1_RSTN_DIS (1 << 0) +#define PLLP_OUT1_RSTN_EN (0 << 0) +#define PLLP_OUT1_CLKEN (1 << 1) +#define PLLP_OUT2_RSTN_DIS (1 << 16) +#define PLLP_OUT2_RSTN_EN (0 << 16) +#define PLLP_OUT2_CLKEN (1 << 17) + +#define PLLP_OUT3_RSTN_DIS (1 << 0) +#define PLLP_OUT3_RSTN_EN (0 << 0) +#define PLLP_OUT3_CLKEN (1 << 1) +#define PLLP_OUT4_RSTN_DIS (1 << 16) +#define PLLP_OUT4_RSTN_EN (0 << 16) +#define PLLP_OUT4_CLKEN (1 << 17) + +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */ +#define PLLU_POWERDOWN (1 << 16) +#define PLL_ENABLE_POWERDOWN (1 << 14) +#define PLL_ACTIVE_POWERDOWN (1 << 12) + +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */ +#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) +#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) +#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) + +/* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */ +#define OSC_XOE_SHIFT 0 +#define OSC_XOE_MASK (1 << OSC_XOE_SHIFT) +#define OSC_XOE_ENABLE (1 << OSC_XOE_SHIFT) +#define OSC_XOBP_SHIFT 1 +#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT) +#define OSC_XOFS_SHIFT 4 +#define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT) +#define OSC_DRIVE_STRENGTH 7 + +/* + * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits + * but can be 16. We could use knowledge we have to restrict the mask in + * the 8-bit cases (the divider_bits value returned by + * get_periph_clock_source()) but it does not seem worth it since the code + * already checks the ranges of values it is writing, in clk_get_divider(). + */ +#define OUT_CLK_DIVISOR_SHIFT 0 +#define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT) + +#define OUT_CLK_SOURCE_31_30_SHIFT 30 +#define OUT_CLK_SOURCE_31_30_MASK (3U << OUT_CLK_SOURCE_31_30_SHIFT) + +#define OUT_CLK_SOURCE_31_29_SHIFT 29 +#define OUT_CLK_SOURCE_31_29_MASK (7U << OUT_CLK_SOURCE_31_29_SHIFT) + +/* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */ +#define OUT_CLK_SOURCE_31_28_SHIFT 28 +#define OUT_CLK_SOURCE_31_28_MASK (15U << OUT_CLK_SOURCE_31_28_SHIFT) + +/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */ +#define SCLK_SYS_STATE_SHIFT 28U +#define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT) +enum { + SCLK_SYS_STATE_STDBY, + SCLK_SYS_STATE_IDLE, + SCLK_SYS_STATE_RUN, + SCLK_SYS_STATE_IRQ = 4U, + SCLK_SYS_STATE_FIQ = 8U, +}; +#define SCLK_COP_FIQ_MASK (1 << 27) +#define SCLK_CPU_FIQ_MASK (1 << 26) +#define SCLK_COP_IRQ_MASK (1 << 25) +#define SCLK_CPU_IRQ_MASK (1 << 24) + +#define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT 12 +#define SCLK_SWAKEUP_FIQ_SOURCE_MASK \ + (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) +#define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT 8 +#define SCLK_SWAKEUP_IRQ_SOURCE_MASK \ + (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) +#define SCLK_SWAKEUP_RUN_SOURCE_SHIFT 4 +#define SCLK_SWAKEUP_RUN_SOURCE_MASK \ + (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) +#define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT 0 + +#define SCLK_SWAKEUP_IDLE_SOURCE_MASK \ + (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) +enum { + SCLK_SOURCE_CLKM, + SCLK_SOURCE_PLLC_OUT1, + SCLK_SOURCE_PLLP_OUT4, + SCLK_SOURCE_PLLP_OUT3, + SCLK_SOURCE_PLLP_OUT2, + SCLK_SOURCE_CLKD, + SCLK_SOURCE_CLKS, + SCLK_SOURCE_PLLM_OUT1, +}; +#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12) +#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8) +#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4) +#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0) + +/* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER */ +#define SUPER_SCLK_ENB_SHIFT 31U +#define SUPER_SCLK_ENB_MASK (1U << 31) +#define SUPER_SCLK_DIVIDEND_SHIFT 8 +#define SUPER_SCLK_DIVIDEND_MASK (0xff << SUPER_SCLK_DIVIDEND_SHIFT) +#define SUPER_SCLK_DIVISOR_SHIFT 0 +#define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT) + +/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */ +#define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7 +#define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) +#define CLK_SYS_RATE_AHB_RATE_SHIFT 4 +#define CLK_SYS_RATE_AHB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT) +#define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3 +#define CLK_SYS_RATE_PCLK_DISABLE_MASK (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) +#define CLK_SYS_RATE_APB_RATE_SHIFT 0 +#define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT) + +/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */ +#define CLR_CPURESET0 (1 << 0) +#define CLR_CPURESET1 (1 << 1) +#define CLR_CPURESET2 (1 << 2) +#define CLR_CPURESET3 (1 << 3) +#define CLR_DBGRESET0 (1 << 12) +#define CLR_DBGRESET1 (1 << 13) +#define CLR_DBGRESET2 (1 << 14) +#define CLR_DBGRESET3 (1 << 15) +#define CLR_CORERESET0 (1 << 16) +#define CLR_CORERESET1 (1 << 17) +#define CLR_CORERESET2 (1 << 18) +#define CLR_CORERESET3 (1 << 19) +#define CLR_CXRESET0 (1 << 20) +#define CLR_CXRESET1 (1 << 21) +#define CLR_CXRESET2 (1 << 22) +#define CLR_CXRESET3 (1 << 23) +#define CLR_L2RESET (1 << 24) +#define CLR_NONCPURESET (1 << 29) +#define CLR_PRESETDBG (1 << 30) + +/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */ +#define CLR_CPU0_CLK_STP (1 << 8) +#define CLR_CPU1_CLK_STP (1 << 9) +#define CLR_CPU2_CLK_STP (1 << 10) +#define CLR_CPU3_CLK_STP (1 << 11) + +/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */ +#define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29) + +/* CRC_CLK_ENB_V_SET_0 0x440 */ +#define SET_CLK_ENB_CPUG_ENABLE (1 << 0) +#define SET_CLK_ENB_CPULP_ENABLE (1 << 1) +#define SET_CLK_ENB_MSELECT_ENABLE (1 << 3) + +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */ +#define PLL_ACTIVE_POWERDOWN (1 << 12) +#define PLL_ENABLE_POWERDOWN (1 << 14) +#define PLLU_POWERDOWN (1 << 16) + +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */ +#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) +#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) +#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) + +/* CLK_RST_CONTROLLER_PLLX_MISC_3 */ +#define PLLX_IDDQ_SHIFT 3 +#define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT) + +/* CLK_RST_PLLDP_SS_CFG */ +#define PLLDP_SS_CFG_CLAMP (1 << 22) +#define PLLDP_SS_CFG_UNDOCUMENTED (1 << 24) +#define PLLDP_SS_CFG_DITHER (1 << 28) + +/* CLK_RST_PLLD_MISC */ +#define PLLD_CLKENABLE 30 + +#endif /* _TEGRA_CLK_RST_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/clock.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/clock.h new file mode 100644 index 000000000..1d80d9e94 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/clock.h @@ -0,0 +1,423 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + */ + +/* Tegra clock control functions */ + +#ifndef _TEGRA_CLOCK_H_ +#define _TEGRA_CLOCK_H_ + +struct udevice; + +/* Set of oscillator frequencies supported in the internal API. */ +enum clock_osc_freq { + /* All in MHz, so 13_0 is 13.0MHz */ + CLOCK_OSC_FREQ_13_0, + CLOCK_OSC_FREQ_19_2, + CLOCK_OSC_FREQ_12_0, + CLOCK_OSC_FREQ_26_0, + CLOCK_OSC_FREQ_38_4, + CLOCK_OSC_FREQ_48_0, + + CLOCK_OSC_FREQ_COUNT, +}; + +/* + * Note that no Tegra clock register actually uses all of bits 31:28 as + * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in + * those cases, nothing is stored in the bits about the mux field, so it's + * safe to pretend that the mux field extends all the way to the end of the + * register. As such, the U-Boot clock driver is currently a bit lazy, and + * doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps + * them all together and pretends they're all 31:28. + */ +enum { + MASK_BITS_31_30, + MASK_BITS_31_29, + MASK_BITS_31_28, +}; + +#include +/* PLL stabilization delay in usec */ +#define CLOCK_PLL_STABLE_DELAY_US 300 + +/* return the current oscillator clock frequency */ +enum clock_osc_freq clock_get_osc_freq(void); + +/* return the clk_m frequency */ +unsigned int clk_m_get_rate(unsigned int parent_rate); + +/** + * Start PLL using the provided configuration parameters. + * + * @param id clock id + * @param divm input divider + * @param divn feedback divider + * @param divp post divider 2^n + * @param cpcon charge pump setup control + * @param lfcon loop filter setup control + * + * @returns monotonic time in us that the PLL will be stable + */ +unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, + u32 divp, u32 cpcon, u32 lfcon); + +/** + * Set PLL output frequency + * + * @param clkid clock id + * @param pllout pll output id + * @param rate desired output rate + * + * @return 0 if ok, -1 on error (invalid clock id or no suitable divider) + */ +int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, + unsigned rate); + +/** + * Read low-level parameters of a PLL. + * + * @param id clock id to read (note: USB is not supported) + * @param divm returns input divider + * @param divn returns feedback divider + * @param divp returns post divider 2^n + * @param cpcon returns charge pump setup control + * @param lfcon returns loop filter setup control + * + * @returns 0 if ok, -1 on error (invalid clock id) + */ +int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, + u32 *divp, u32 *cpcon, u32 *lfcon); + +/* + * Enable a clock + * + * @param id clock id + */ +void clock_enable(enum periph_id clkid); + +/* + * Disable a clock + * + * @param id clock id + */ +void clock_disable(enum periph_id clkid); + +/* + * Set whether a clock is enabled or disabled. + * + * @param id clock id + * @param enable 1 to enable, 0 to disable + */ +void clock_set_enable(enum periph_id clkid, int enable); + +/** + * Reset a peripheral. This puts it in reset, waits for a delay, then takes + * it out of reset and waits for th delay again. + * + * @param periph_id peripheral to reset + * @param us_delay time to delay in microseconds + */ +void reset_periph(enum periph_id periph_id, int us_delay); + +/** + * Put a peripheral into or out of reset. + * + * @param periph_id peripheral to reset + * @param enable 1 to put into reset, 0 to take out of reset + */ +void reset_set_enable(enum periph_id periph_id, int enable); + + +/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ +enum crc_reset_id { + /* Things we can hold in reset for each CPU */ + crc_rst_cpu = 1, + crc_rst_de = 1 << 4, /* What is de? */ + crc_rst_watchdog = 1 << 8, + crc_rst_debug = 1 << 12, +}; + +/** + * Put parts of the CPU complex into or out of reset.\ + * + * @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3) + * @param which which parts of the complex to affect (OR of crc_reset_id) + * @param reset 1 to assert reset, 0 to de-assert + */ +void reset_cmplx_set_enable(int cpu, int which, int reset); + +/** + * Set the source for a peripheral clock. This plus the divisor sets the + * clock rate. You need to look up the datasheet to see the meaning of the + * source parameter as it changes for each peripheral. + * + * Warning: This function is only for use pre-relocation. Please use + * clock_start_periph_pll() instead. + * + * @param periph_id peripheral to adjust + * @param source source clock (0, 1, 2 or 3) + */ +void clock_ll_set_source(enum periph_id periph_id, unsigned source); + +/** + * This function is similar to clock_ll_set_source() except that it can be + * used for clocks with more than 2 mux bits. + * + * @param periph_id peripheral to adjust + * @param mux_bits number of mux bits for the clock + * @param source source clock (0-15 depending on mux_bits) + */ +int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits, + unsigned source); + +/** + * Set the source and divisor for a peripheral clock. This sets the + * clock rate. You need to look up the datasheet to see the meaning of the + * source parameter as it changes for each peripheral. + * + * Warning: This function is only for use pre-relocation. Please use + * clock_start_periph_pll() instead. + * + * @param periph_id peripheral to adjust + * @param source source clock (0, 1, 2 or 3) + * @param divisor divisor value to use + */ +void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, + unsigned divisor); + +/** + * Returns the current parent clock ID of a given peripheral. This can be + * useful in order to call clock_*_periph_*() from generic code that has no + * specific knowledge of system-level clock tree structure. + * + * @param periph_id peripheral to query + * @return clock ID of the peripheral's current parent clock + */ +enum clock_id clock_get_periph_parent(enum periph_id periph_id); + +/** + * Start a peripheral PLL clock at the given rate. This also resets the + * peripheral. + * + * @param periph_id peripheral to start + * @param parent PLL id of required parent clock + * @param rate Required clock rate in Hz + * @return rate selected in Hz, or -1U if something went wrong + */ +unsigned clock_start_periph_pll(enum periph_id periph_id, + enum clock_id parent, unsigned rate); + +/** + * Returns the rate of a peripheral clock in Hz. Since the caller almost + * certainly knows the parent clock (having just set it) we require that + * this be passed in so we don't need to work it out. + * + * @param periph_id peripheral to start + * @param parent PLL id of parent clock (used to calculate rate, you + * must know this!) + * @return clock rate of peripheral in Hz + */ +unsigned long clock_get_periph_rate(enum periph_id periph_id, + enum clock_id parent); + +/** + * Adjust peripheral PLL clock to the given rate. This does not reset the + * peripheral. If a second stage divisor is not available, pass NULL for + * extra_div. If it is available, then this parameter will return the + * divisor selected (which will be a power of 2 from 1 to 256). + * + * @param periph_id peripheral to start + * @param parent PLL id of required parent clock + * @param rate Required clock rate in Hz + * @param extra_div value for the second-stage divisor (NULL if one is + not available) + * @return rate selected in Hz, or -1U if something went wrong + */ +unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, + enum clock_id parent, unsigned rate, int *extra_div); + +/** + * Returns the clock rate of a specified clock, in Hz. + * + * @param parent PLL id of clock to check + * @return rate of clock in Hz + */ +unsigned clock_get_rate(enum clock_id clkid); + +/** + * Start up a UART using low-level calls + * + * Prior to relocation clock_start_periph_pll() cannot be called. This + * function provides a way to set up a UART using low-level calls which + * do not require BSS. + * + * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1) + */ +void clock_ll_start_uart(enum periph_id periph_id); + +/** + * Decode a peripheral ID from a device tree node. + * + * This works by looking up the peripheral's 'clocks' node and reading out + * the second cell, which is the clock number / peripheral ID. + * + * @param blob FDT blob to use + * @param node Node to look at + * @return peripheral ID, or PERIPH_ID_NONE if none + */ +int clock_decode_periph_id(struct udevice *dev); + +/** + * Checks if the oscillator bypass is enabled (XOBP bit) + * + * @return 1 if bypass is enabled, 0 if not + */ +int clock_get_osc_bypass(void); + +/* + * Checks that clocks are valid and prints a warning if not + * + * @return 0 if ok, -1 on error + */ +int clock_verify(void); + +/* Initialize the clocks */ +void clock_init(void); + +/* Initialize the PLLs */ +void clock_early_init(void); + +/* @return true if hardware indicates that clock_early_init() was called */ +bool clock_early_init_done(void); + +/* Returns a pointer to the clock source register for a peripheral */ +u32 *get_periph_source_reg(enum periph_id periph_id); + +/* Returns a pointer to the given 'simple' PLL */ +struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid); + +/* + * Given a peripheral ID, determine where the mux bits are in the peripheral + * clock's register, the number of divider bits the clock has, and the SoC- + * specific clock type. + * + * This is an internal API between the core Tegra clock code and the SoC- + * specific clock code. + * + * @param periph_id peripheral to query + * @param mux_bits Set to number of bits in mux register + * @param divider_bits Set to the relevant MASK_BITS_* value + * @param type Set to the SoC-specific clock type + * @return 0 on success, -1 on error + */ +int get_periph_clock_info(enum periph_id periph_id, int *mux_bits, + int *divider_bits, int *type); + +/* + * Given a peripheral ID and clock source mux value, determine the clock_id + * of that peripheral's parent. + * + * This is an internal API between the core Tegra clock code and the SoC- + * specific clock code. + * + * @param periph_id peripheral to query + * @param source raw clock source mux value + * @return the CLOCK_ID_* value @source represents + */ +enum clock_id get_periph_clock_id(enum periph_id periph_id, int source); + +/** + * Given a peripheral ID and the required source clock, this returns which + * value should be programmed into the source mux for that peripheral. + * + * There is special code here to handle the one source type with 5 sources. + * + * @param periph_id peripheral to start + * @param source PLL id of required parent clock + * @param mux_bits Set to number of bits in mux register: 2 or 4 + * @param divider_bits Set to number of divider bits (8 or 16) + * @return mux value (0-4, or -1 if not found) + */ +int get_periph_clock_source(enum periph_id periph_id, + enum clock_id parent, int *mux_bits, int *divider_bits); + +/* + * Convert a device tree clock ID to our peripheral ID. They are mostly + * the same but we are very cautious so we check that a valid clock ID is + * provided. + * + * @param clk_id Clock ID according to tegra30 device tree binding + * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid + */ +enum periph_id clk_id_to_periph_id(int clk_id); + +/** + * Set the output frequency you want for each PLL clock. + * PLL output frequencies are programmed by setting their N, M and P values. + * The governing equations are: + * VCO = (Fi / m) * n, Fo = VCO / (2^p) + * where Fo is the output frequency from the PLL. + * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi) + * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1 + * Please see Tegra TRM section 5.3 to get the detail for PLL Programming + * + * @param n PLL feedback divider(DIVN) + * @param m PLL input divider(DIVN) + * @param p post divider(DIVP) + * @param cpcon base PLL charge pump(CPCON) + * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot + * be overridden), 1 if PLL is already correct + */ +int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon); + +/* return 1 if a peripheral ID is in range */ +#define clock_type_id_isvalid(id) ((id) >= 0 && \ + (id) < CLOCK_TYPE_COUNT) + +/* return 1 if a periphc_internal_id is in range */ +#define periphc_internal_id_isvalid(id) ((id) >= 0 && \ + (id) < PERIPHC_COUNT) + +/* SoC-specific TSC init */ +void arch_timer_init(void); + +void tegra30_set_up_pllp(void); + +/* Number of PLL-based clocks (i.e. not OSC, MCLK or 32KHz) */ +#define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 3) + +struct clk_pll_info { + u32 m_shift:5; /* DIVM_SHIFT */ + u32 n_shift:5; /* DIVN_SHIFT */ + u32 p_shift:5; /* DIVP_SHIFT */ + u32 kcp_shift:5; /* KCP/cpcon SHIFT */ + u32 kvco_shift:5; /* KVCO/lfcon SHIFT */ + u32 lock_ena:6; /* LOCK_ENABLE/EN_LOCKDET shift */ + u32 rsvd:1; + u32 m_mask:10; /* DIVM_MASK */ + u32 n_mask:12; /* DIVN_MASK */ + u32 p_mask:10; /* DIVP_MASK or VCO_MASK */ + u32 kcp_mask:10; /* KCP/CPCON MASK */ + u32 kvco_mask:10; /* KVCO/LFCON MASK */ + u32 lock_det:6; /* LOCK_DETECT/LOCKED shift */ + u32 rsvd2:6; +}; +extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT]; + +struct periph_clk_init { + enum periph_id periph_id; + enum clock_id parent_clock_id; +}; +extern struct periph_clk_init periph_clk_init_table[]; + +/** + * Enable output clock for external peripherals + * + * @param clk_id Clock ID to output (1, 2 or 3) + * @return 0 if OK. -ve on error + */ +int clock_external_output(int clk_id); + +#endif /* _TEGRA_CLOCK_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/dc.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/dc.h new file mode 100644 index 000000000..6444af299 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/dc.h @@ -0,0 +1,572 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * NVIDIA Corporation + */ + +#ifndef __ASM_ARCH_TEGRA_DC_H +#define __ASM_ARCH_TEGRA_DC_H + +#ifndef __ASSEMBLY__ +#include +#endif + +/* Register definitions for the Tegra display controller */ + +/* CMD register 0x000 ~ 0x43 */ +struct dc_cmd_reg { + /* Address 0x000 ~ 0x002 */ + uint gen_incr_syncpt; /* _CMD_GENERAL_INCR_SYNCPT_0 */ + uint gen_incr_syncpt_ctrl; /* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */ + uint gen_incr_syncpt_err; /* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */ + + uint reserved0[5]; /* reserved_0[5] */ + + /* Address 0x008 ~ 0x00a */ + uint win_a_incr_syncpt; /* _CMD_WIN_A_INCR_SYNCPT_0 */ + uint win_a_incr_syncpt_ctrl; /* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */ + uint win_a_incr_syncpt_err; /* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */ + + uint reserved1[5]; /* reserved_1[5] */ + + /* Address 0x010 ~ 0x012 */ + uint win_b_incr_syncpt; /* _CMD_WIN_B_INCR_SYNCPT_0 */ + uint win_b_incr_syncpt_ctrl; /* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */ + uint win_b_incr_syncpt_err; /* _CMD_WIN_B_INCR_SYNCPT_ERROR_0 */ + + uint reserved2[5]; /* reserved_2[5] */ + + /* Address 0x018 ~ 0x01a */ + uint win_c_incr_syncpt; /* _CMD_WIN_C_INCR_SYNCPT_0 */ + uint win_c_incr_syncpt_ctrl; /* _CMD_WIN_C_INCR_SYNCPT_CNTRL_0 */ + uint win_c_incr_syncpt_err; /* _CMD_WIN_C_INCR_SYNCPT_ERROR_0 */ + + uint reserved3[13]; /* reserved_3[13] */ + + /* Address 0x028 */ + uint cont_syncpt_vsync; /* _CMD_CONT_SYNCPT_VSYNC_0 */ + + uint reserved4[7]; /* reserved_4[7] */ + + /* Address 0x030 ~ 0x033 */ + uint ctxsw; /* _CMD_CTXSW_0 */ + uint disp_cmd_opt0; /* _CMD_DISPLAY_COMMAND_OPTION0_0 */ + uint disp_cmd; /* _CMD_DISPLAY_COMMAND_0 */ + uint sig_raise; /* _CMD_SIGNAL_RAISE_0 */ + + uint reserved5[2]; /* reserved_0[2] */ + + /* Address 0x036 ~ 0x03e */ + uint disp_pow_ctrl; /* _CMD_DISPLAY_POWER_CONTROL_0 */ + uint int_stat; /* _CMD_INT_STATUS_0 */ + uint int_mask; /* _CMD_INT_MASK_0 */ + uint int_enb; /* _CMD_INT_ENABLE_0 */ + uint int_type; /* _CMD_INT_TYPE_0 */ + uint int_polarity; /* _CMD_INT_POLARITY_0 */ + uint sig_raise1; /* _CMD_SIGNAL_RAISE1_0 */ + uint sig_raise2; /* _CMD_SIGNAL_RAISE2_0 */ + uint sig_raise3; /* _CMD_SIGNAL_RAISE3_0 */ + + uint reserved6; /* reserved_6 */ + + /* Address 0x040 ~ 0x043 */ + uint state_access; /* _CMD_STATE_ACCESS_0 */ + uint state_ctrl; /* _CMD_STATE_CONTROL_0 */ + uint disp_win_header; /* _CMD_DISPLAY_WINDOW_HEADER_0 */ + uint reg_act_ctrl; /* _CMD_REG_ACT_CONTROL_0 */ +}; + +enum { + PIN_REG_COUNT = 4, + PIN_OUTPUT_SEL_COUNT = 7, +}; + +/* COM register 0x300 ~ 0x329 */ +struct dc_com_reg { + /* Address 0x300 ~ 0x301 */ + uint crc_ctrl; /* _COM_CRC_CONTROL_0 */ + uint crc_checksum; /* _COM_CRC_CHECKSUM_0 */ + + /* _COM_PIN_OUTPUT_ENABLE0/1/2/3_0: Address 0x302 ~ 0x305 */ + uint pin_output_enb[PIN_REG_COUNT]; + + /* _COM_PIN_OUTPUT_POLARITY0/1/2/3_0: Address 0x306 ~ 0x309 */ + uint pin_output_polarity[PIN_REG_COUNT]; + + /* _COM_PIN_OUTPUT_DATA0/1/2/3_0: Address 0x30a ~ 0x30d */ + uint pin_output_data[PIN_REG_COUNT]; + + /* _COM_PIN_INPUT_ENABLE0_0: Address 0x30e ~ 0x311 */ + uint pin_input_enb[PIN_REG_COUNT]; + + /* Address 0x312 ~ 0x313 */ + uint pin_input_data0; /* _COM_PIN_INPUT_DATA0_0 */ + uint pin_input_data1; /* _COM_PIN_INPUT_DATA1_0 */ + + /* _COM_PIN_OUTPUT_SELECT0/1/2/3/4/5/6_0: Address 0x314 ~ 0x31a */ + uint pin_output_sel[PIN_OUTPUT_SEL_COUNT]; + + /* Address 0x31b ~ 0x329 */ + uint pin_misc_ctrl; /* _COM_PIN_MISC_CONTROL_0 */ + uint pm0_ctrl; /* _COM_PM0_CONTROL_0 */ + uint pm0_duty_cycle; /* _COM_PM0_DUTY_CYCLE_0 */ + uint pm1_ctrl; /* _COM_PM1_CONTROL_0 */ + uint pm1_duty_cycle; /* _COM_PM1_DUTY_CYCLE_0 */ + uint spi_ctrl; /* _COM_SPI_CONTROL_0 */ + uint spi_start_byte; /* _COM_SPI_START_BYTE_0 */ + uint hspi_wr_data_ab; /* _COM_HSPI_WRITE_DATA_AB_0 */ + uint hspi_wr_data_cd; /* _COM_HSPI_WRITE_DATA_CD */ + uint hspi_cs_dc; /* _COM_HSPI_CS_DC_0 */ + uint scratch_reg_a; /* _COM_SCRATCH_REGISTER_A_0 */ + uint scratch_reg_b; /* _COM_SCRATCH_REGISTER_B_0 */ + uint gpio_ctrl; /* _COM_GPIO_CTRL_0 */ + uint gpio_debounce_cnt; /* _COM_GPIO_DEBOUNCE_COUNTER_0 */ + uint crc_checksum_latched; /* _COM_CRC_CHECKSUM_LATCHED_0 */ +}; + +enum dc_disp_h_pulse_pos { + H_PULSE0_POSITION_A, + H_PULSE0_POSITION_B, + H_PULSE0_POSITION_C, + H_PULSE0_POSITION_D, + H_PULSE0_POSITION_COUNT, +}; + +struct _disp_h_pulse { + /* _DISP_H_PULSE0/1/2_CONTROL_0 */ + uint h_pulse_ctrl; + /* _DISP_H_PULSE0/1/2_POSITION_A/B/C/D_0 */ + uint h_pulse_pos[H_PULSE0_POSITION_COUNT]; +}; + +enum dc_disp_v_pulse_pos { + V_PULSE0_POSITION_A, + V_PULSE0_POSITION_B, + V_PULSE0_POSITION_C, + V_PULSE0_POSITION_COUNT, +}; + +struct _disp_v_pulse0 { + /* _DISP_H_PULSE0/1_CONTROL_0 */ + uint v_pulse_ctrl; + /* _DISP_H_PULSE0/1_POSITION_A/B/C_0 */ + uint v_pulse_pos[V_PULSE0_POSITION_COUNT]; +}; + +struct _disp_v_pulse2 { + /* _DISP_H_PULSE2/3_CONTROL_0 */ + uint v_pulse_ctrl; + /* _DISP_H_PULSE2/3_POSITION_A_0 */ + uint v_pulse_pos_a; +}; + +enum dc_disp_h_pulse_reg { + H_PULSE0, + H_PULSE1, + H_PULSE2, + H_PULSE_COUNT, +}; + +enum dc_disp_pp_select { + PP_SELECT_A, + PP_SELECT_B, + PP_SELECT_C, + PP_SELECT_D, + PP_SELECT_COUNT, +}; + +/* DISP register 0x400 ~ 0x4c1 */ +struct dc_disp_reg { + /* Address 0x400 ~ 0x40a */ + uint disp_signal_opt0; /* _DISP_DISP_SIGNAL_OPTIONS0_0 */ + uint disp_signal_opt1; /* _DISP_DISP_SIGNAL_OPTIONS1_0 */ + uint disp_win_opt; /* _DISP_DISP_WIN_OPTIONS_0 */ + uint mem_high_pri; /* _DISP_MEM_HIGH_PRIORITY_0 */ + uint mem_high_pri_timer; /* _DISP_MEM_HIGH_PRIORITY_TIMER_0 */ + uint disp_timing_opt; /* _DISP_DISP_TIMING_OPTIONS_0 */ + uint ref_to_sync; /* _DISP_REF_TO_SYNC_0 */ + uint sync_width; /* _DISP_SYNC_WIDTH_0 */ + uint back_porch; /* _DISP_BACK_PORCH_0 */ + uint disp_active; /* _DISP_DISP_ACTIVE_0 */ + uint front_porch; /* _DISP_FRONT_PORCH_0 */ + + /* Address 0x40b ~ 0x419: _DISP_H_PULSE0/1/2_ */ + struct _disp_h_pulse h_pulse[H_PULSE_COUNT]; + + /* Address 0x41a ~ 0x421 */ + struct _disp_v_pulse0 v_pulse0; /* _DISP_V_PULSE0_ */ + struct _disp_v_pulse0 v_pulse1; /* _DISP_V_PULSE1_ */ + + /* Address 0x422 ~ 0x425 */ + struct _disp_v_pulse2 v_pulse3; /* _DISP_V_PULSE2_ */ + struct _disp_v_pulse2 v_pulse4; /* _DISP_V_PULSE3_ */ + + /* Address 0x426 ~ 0x429 */ + uint m0_ctrl; /* _DISP_M0_CONTROL_0 */ + uint m1_ctrl; /* _DISP_M1_CONTROL_0 */ + uint di_ctrl; /* _DISP_DI_CONTROL_0 */ + uint pp_ctrl; /* _DISP_PP_CONTROL_0 */ + + /* Address 0x42a ~ 0x42d: _DISP_PP_SELECT_A/B/C/D_0 */ + uint pp_select[PP_SELECT_COUNT]; + + /* Address 0x42e ~ 0x435 */ + uint disp_clk_ctrl; /* _DISP_DISP_CLOCK_CONTROL_0 */ + uint disp_interface_ctrl; /* _DISP_DISP_INTERFACE_CONTROL_0 */ + uint disp_color_ctrl; /* _DISP_DISP_COLOR_CONTROL_0 */ + uint shift_clk_opt; /* _DISP_SHIFT_CLOCK_OPTIONS_0 */ + uint data_enable_opt; /* _DISP_DATA_ENABLE_OPTIONS_0 */ + uint serial_interface_opt; /* _DISP_SERIAL_INTERFACE_OPTIONS_0 */ + uint lcd_spi_opt; /* _DISP_LCD_SPI_OPTIONS_0 */ + uint border_color; /* _DISP_BORDER_COLOR_0 */ + + /* Address 0x436 ~ 0x439 */ + uint color_key0_lower; /* _DISP_COLOR_KEY0_LOWER_0 */ + uint color_key0_upper; /* _DISP_COLOR_KEY0_UPPER_0 */ + uint color_key1_lower; /* _DISP_COLOR_KEY1_LOWER_0 */ + uint color_key1_upper; /* _DISP_COLOR_KEY1_UPPER_0 */ + + uint reserved0[2]; /* reserved_0[2] */ + + /* Address 0x43c ~ 0x442 */ + uint cursor_foreground; /* _DISP_CURSOR_FOREGROUND_0 */ + uint cursor_background; /* _DISP_CURSOR_BACKGROUND_0 */ + uint cursor_start_addr; /* _DISP_CURSOR_START_ADDR_0 */ + uint cursor_start_addr_ns; /* _DISP_CURSOR_START_ADDR_NS_0 */ + uint cursor_pos; /* _DISP_CURSOR_POSITION_0 */ + uint cursor_pos_ns; /* _DISP_CURSOR_POSITION_NS_0 */ + uint seq_ctrl; /* _DISP_INIT_SEQ_CONTROL_0 */ + + /* Address 0x443 ~ 0x446 */ + uint spi_init_seq_data_a; /* _DISP_SPI_INIT_SEQ_DATA_A_0 */ + uint spi_init_seq_data_b; /* _DISP_SPI_INIT_SEQ_DATA_B_0 */ + uint spi_init_seq_data_c; /* _DISP_SPI_INIT_SEQ_DATA_C_0 */ + uint spi_init_seq_data_d; /* _DISP_SPI_INIT_SEQ_DATA_D_0 */ + + uint reserved1[0x39]; /* reserved1[0x39], */ + + /* Address 0x480 ~ 0x484 */ + uint dc_mccif_fifoctrl; /* _DISP_DC_MCCIF_FIFOCTRL_0 */ + uint mccif_disp0a_hyst; /* _DISP_MCCIF_DISPLAY0A_HYST_0 */ + uint mccif_disp0b_hyst; /* _DISP_MCCIF_DISPLAY0B_HYST_0 */ + uint mccif_disp0c_hyst; /* _DISP_MCCIF_DISPLAY0C_HYST_0 */ + uint mccif_disp1b_hyst; /* _DISP_MCCIF_DISPLAY1B_HYST_0 */ + + uint reserved2[0x3b]; /* reserved2[0x3b] */ + + /* Address 0x4c0 ~ 0x4c1 */ + uint dac_crt_ctrl; /* _DISP_DAC_CRT_CTRL_0 */ + uint disp_misc_ctrl; /* _DISP_DISP_MISC_CONTROL_0 */ + + u32 rsvd_4c2[34]; /* 4c2 - 4e3 */ + + /* Address 0x4e4 */ + u32 blend_background_color; /* _DISP_BLEND_BACKGROUND_COLOR_0 */ +}; + +enum dc_winc_filter_p { + WINC_FILTER_COUNT = 0x10, +}; + +/* Window A/B/C register 0x500 ~ 0x628 */ +struct dc_winc_reg { + + /* Address 0x500 */ + uint color_palette; /* _WINC_COLOR_PALETTE_0 */ + + uint reserved0[0xff]; /* reserved_0[0xff] */ + + /* Address 0x600 */ + uint palette_color_ext; /* _WINC_PALETTE_COLOR_EXT_0 */ + + /* _WINC_H_FILTER_P00~0F_0 */ + /* Address 0x601 ~ 0x610 */ + uint h_filter_p[WINC_FILTER_COUNT]; + + /* Address 0x611 ~ 0x618 */ + uint csc_yof; /* _WINC_CSC_YOF_0 */ + uint csc_kyrgb; /* _WINC_CSC_KYRGB_0 */ + uint csc_kur; /* _WINC_CSC_KUR_0 */ + uint csc_kvr; /* _WINC_CSC_KVR_0 */ + uint csc_kug; /* _WINC_CSC_KUG_0 */ + uint csc_kvg; /* _WINC_CSC_KVG_0 */ + uint csc_kub; /* _WINC_CSC_KUB_0 */ + uint csc_kvb; /* _WINC_CSC_KVB_0 */ + + /* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */ + uint v_filter_p[WINC_FILTER_COUNT]; +}; + +/* WIN A/B/C Register 0x700 ~ 0x719*/ +struct dc_win_reg { + /* Address 0x700 ~ 0x719 */ + uint win_opt; /* _WIN_WIN_OPTIONS_0 */ + uint byte_swap; /* _WIN_BYTE_SWAP_0 */ + uint buffer_ctrl; /* _WIN_BUFFER_CONTROL_0 */ + uint color_depth; /* _WIN_COLOR_DEPTH_0 */ + uint pos; /* _WIN_POSITION_0 */ + uint size; /* _WIN_SIZE_0 */ + uint prescaled_size; /* _WIN_PRESCALED_SIZE_0 */ + uint h_initial_dda; /* _WIN_H_INITIAL_DDA_0 */ + uint v_initial_dda; /* _WIN_V_INITIAL_DDA_0 */ + uint dda_increment; /* _WIN_DDA_INCREMENT_0 */ + uint line_stride; /* _WIN_LINE_STRIDE_0 */ + uint buf_stride; /* _WIN_BUF_STRIDE_0 */ + uint uv_buf_stride; /* _WIN_UV_BUF_STRIDE_0 */ + uint buffer_addr_mode; /* _WIN_BUFFER_ADDR_MODE_0 */ + uint dv_ctrl; /* _WIN_DV_CONTROL_0 */ + uint blend_nokey; /* _WIN_BLEND_NOKEY_0 */ + uint blend_1win; /* _WIN_BLEND_1WIN_0 */ + uint blend_2win_x; /* _WIN_BLEND_2WIN_X_0 */ + uint blend_2win_y; /* _WIN_BLEND_2WIN_Y_0 */ + uint blend_3win_xy; /* _WIN_BLEND_3WIN_XY_0 */ + uint hp_fetch_ctrl; /* _WIN_HP_FETCH_CONTROL_0 */ + uint global_alpha; /* _WIN_GLOBAL_ALPHA */ + uint blend_layer_ctrl; /* _WINBUF_BLEND_LAYER_CONTROL_0 */ + uint blend_match_select; /* _WINBUF_BLEND_MATCH_SELECT_0 */ + uint blend_nomatch_select; /* _WINBUF_BLEND_NOMATCH_SELECT_0 */ + uint blend_alpha_1bit; /* _WINBUF_BLEND_ALPHA_1BIT_0 */ +}; + +/* WINBUF A/B/C Register 0x800 ~ 0x80d */ +struct dc_winbuf_reg { + /* Address 0x800 ~ 0x80d */ + uint start_addr; /* _WINBUF_START_ADDR_0 */ + uint start_addr_ns; /* _WINBUF_START_ADDR_NS_0 */ + uint start_addr_u; /* _WINBUF_START_ADDR_U_0 */ + uint start_addr_u_ns; /* _WINBUF_START_ADDR_U_NS_0 */ + uint start_addr_v; /* _WINBUF_START_ADDR_V_0 */ + uint start_addr_v_ns; /* _WINBUF_START_ADDR_V_NS_0 */ + uint addr_h_offset; /* _WINBUF_ADDR_H_OFFSET_0 */ + uint addr_h_offset_ns; /* _WINBUF_ADDR_H_OFFSET_NS_0 */ + uint addr_v_offset; /* _WINBUF_ADDR_V_OFFSET_0 */ + uint addr_v_offset_ns; /* _WINBUF_ADDR_V_OFFSET_NS_0 */ + uint uflow_status; /* _WINBUF_UFLOW_STATUS_0 */ + uint buffer_surface_kind; /* DC_WIN_BUFFER_SURFACE_KIND */ + uint rsvd_80c; + uint start_addr_hi; /* DC_WINBUF_START_ADDR_HI_0 */ +}; + +/* Display Controller (DC_) regs */ +struct dc_ctlr { + struct dc_cmd_reg cmd; /* CMD register 0x000 ~ 0x43 */ + uint reserved0[0x2bc]; + + struct dc_com_reg com; /* COM register 0x300 ~ 0x329 */ + uint reserved1[0xd6]; + + struct dc_disp_reg disp; /* DISP register 0x400 ~ 0x4e4 */ + uint reserved2[0x1b]; + + struct dc_winc_reg winc; /* Window A/B/C 0x500 ~ 0x628 */ + uint reserved3[0xd7]; + + struct dc_win_reg win; /* WIN A/B/C 0x700 ~ 0x719*/ + uint reserved4[0xe6]; + + struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80d */ +}; + +/* DC_CMD_DISPLAY_COMMAND 0x032 */ +#define CTRL_MODE_SHIFT 5 +#define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT) +enum { + CTRL_MODE_STOP, + CTRL_MODE_C_DISPLAY, + CTRL_MODE_NC_DISPLAY, +}; + +/* _WIN_COLOR_DEPTH_0 */ +enum win_color_depth_id { + COLOR_DEPTH_P1, + COLOR_DEPTH_P2, + COLOR_DEPTH_P4, + COLOR_DEPTH_P8, + COLOR_DEPTH_B4G4R4A4, + COLOR_DEPTH_B5G5R5A, + COLOR_DEPTH_B5G6R5, + COLOR_DEPTH_AB5G5R5, + COLOR_DEPTH_B8G8R8A8 = 12, + COLOR_DEPTH_R8G8B8A8, + COLOR_DEPTH_B6x2G6x2R6x2A8, + COLOR_DEPTH_R6x2G6x2B6x2A8, + COLOR_DEPTH_YCbCr422, + COLOR_DEPTH_YUV422, + COLOR_DEPTH_YCbCr420P, + COLOR_DEPTH_YUV420P, + COLOR_DEPTH_YCbCr422P, + COLOR_DEPTH_YUV422P, + COLOR_DEPTH_YCbCr422R, + COLOR_DEPTH_YUV422R, + COLOR_DEPTH_YCbCr422RA, + COLOR_DEPTH_YUV422RA, +}; + +/* DC_CMD_DISPLAY_POWER_CONTROL 0x036 */ +#define PW0_ENABLE BIT(0) +#define PW1_ENABLE BIT(2) +#define PW2_ENABLE BIT(4) +#define PW3_ENABLE BIT(6) +#define PW4_ENABLE BIT(8) +#define PM0_ENABLE BIT(16) +#define PM1_ENABLE BIT(18) +#define SPI_ENABLE BIT(24) +#define HSPI_ENABLE BIT(25) + +/* DC_CMD_STATE_ACCESS 0x040 */ +#define READ_MUX_ASSEMBLY (0 << 0) +#define READ_MUX_ACTIVE (1 << 0) +#define WRITE_MUX_ASSEMBLY (0 << 2) +#define WRITE_MUX_ACTIVE (1 << 2) + +/* DC_CMD_STATE_CONTROL 0x041 */ +#define GENERAL_ACT_REQ BIT(0) +#define WIN_A_ACT_REQ BIT(1) +#define WIN_B_ACT_REQ BIT(2) +#define WIN_C_ACT_REQ BIT(3) +#define WIN_D_ACT_REQ BIT(4) +#define WIN_H_ACT_REQ BIT(5) +#define CURSOR_ACT_REQ BIT(7) +#define GENERAL_UPDATE BIT(8) +#define WIN_A_UPDATE BIT(9) +#define WIN_B_UPDATE BIT(10) +#define WIN_C_UPDATE BIT(11) +#define WIN_D_UPDATE BIT(12) +#define WIN_H_UPDATE BIT(13) +#define CURSOR_UPDATE BIT(15) +#define NC_HOST_TRIG BIT(24) + +/* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */ +#define WINDOW_A_SELECT BIT(4) +#define WINDOW_B_SELECT BIT(5) +#define WINDOW_C_SELECT BIT(6) +#define WINDOW_D_SELECT BIT(7) +#define WINDOW_H_SELECT BIT(8) + +/* DC_DISP_DISP_WIN_OPTIONS 0x402 */ +#define CURSOR_ENABLE BIT(16) +#define SOR_ENABLE BIT(25) +#define TVO_ENABLE BIT(28) +#define DSI_ENABLE BIT(29) +#define HDMI_ENABLE BIT(30) + +/* DC_DISP_DISP_TIMING_OPTIONS 0x405 */ +#define VSYNC_H_POSITION(x) ((x) & 0xfff) + +/* DC_DISP_DISP_CLOCK_CONTROL 0x42e */ +#define SHIFT_CLK_DIVIDER_SHIFT 0 +#define SHIFT_CLK_DIVIDER_MASK (0xff << SHIFT_CLK_DIVIDER_SHIFT) +#define PIXEL_CLK_DIVIDER_SHIFT 8 +#define PIXEL_CLK_DIVIDER_MSK (0xf << PIXEL_CLK_DIVIDER_SHIFT) +enum { + PIXEL_CLK_DIVIDER_PCD1, + PIXEL_CLK_DIVIDER_PCD1H, + PIXEL_CLK_DIVIDER_PCD2, + PIXEL_CLK_DIVIDER_PCD3, + PIXEL_CLK_DIVIDER_PCD4, + PIXEL_CLK_DIVIDER_PCD6, + PIXEL_CLK_DIVIDER_PCD8, + PIXEL_CLK_DIVIDER_PCD9, + PIXEL_CLK_DIVIDER_PCD12, + PIXEL_CLK_DIVIDER_PCD16, + PIXEL_CLK_DIVIDER_PCD18, + PIXEL_CLK_DIVIDER_PCD24, + PIXEL_CLK_DIVIDER_PCD13, +}; + +/* DC_DISP_DISP_INTERFACE_CONTROL 0x42f */ +#define DATA_FORMAT_SHIFT 0 +#define DATA_FORMAT_MASK (0xf << DATA_FORMAT_SHIFT) +enum { + DATA_FORMAT_DF1P1C, + DATA_FORMAT_DF1P2C24B, + DATA_FORMAT_DF1P2C18B, + DATA_FORMAT_DF1P2C16B, + DATA_FORMAT_DF2S, + DATA_FORMAT_DF3S, + DATA_FORMAT_DFSPI, + DATA_FORMAT_DF1P3C24B, + DATA_FORMAT_DF1P3C18B, +}; +#define DATA_ALIGNMENT_SHIFT 8 +enum { + DATA_ALIGNMENT_MSB, + DATA_ALIGNMENT_LSB, +}; +#define DATA_ORDER_SHIFT 9 +enum { + DATA_ORDER_RED_BLUE, + DATA_ORDER_BLUE_RED, +}; + +/* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */ +#define DE_SELECT_SHIFT 0 +#define DE_SELECT_MASK (0x3 << DE_SELECT_SHIFT) +#define DE_SELECT_ACTIVE_BLANK 0x0 +#define DE_SELECT_ACTIVE 0x1 +#define DE_SELECT_ACTIVE_IS 0x2 +#define DE_CONTROL_SHIFT 2 +#define DE_CONTROL_MASK (0x7 << DE_CONTROL_SHIFT) +enum { + DE_CONTROL_ONECLK, + DE_CONTROL_NORMAL, + DE_CONTROL_EARLY_EXT, + DE_CONTROL_EARLY, + DE_CONTROL_ACTIVE_BLANK, +}; + +/* DC_WIN_WIN_OPTIONS 0x700 */ +#define H_DIRECTION BIT(0) +enum { + H_DIRECTION_INCREMENT, + H_DIRECTION_DECREMENT, +}; +#define V_DIRECTION BIT(2) +enum { + V_DIRECTION_INCREMENT, + V_DIRECTION_DECREMENT, +}; +#define COLOR_EXPAND BIT(6) +#define CP_ENABLE BIT(16) +#define DV_ENABLE BIT(20) +#define WIN_ENABLE BIT(30) + +/* DC_WIN_BYTE_SWAP 0x701 */ +#define BYTE_SWAP_SHIFT 0 +#define BYTE_SWAP_MASK (3 << BYTE_SWAP_SHIFT) +enum { + BYTE_SWAP_NOSWAP, + BYTE_SWAP_SWAP2, + BYTE_SWAP_SWAP4, + BYTE_SWAP_SWAP4HW +}; + +/* DC_WIN_POSITION 0x704 */ +#define H_POSITION_SHIFT 0 +#define H_POSITION_MASK (0x1FFF << H_POSITION_SHIFT) +#define V_POSITION_SHIFT 16 +#define V_POSITION_MASK (0x1FFF << V_POSITION_SHIFT) + +/* DC_WIN_SIZE 0x705 */ +#define H_SIZE_SHIFT 0 +#define H_SIZE_MASK (0x1FFF << H_SIZE_SHIFT) +#define V_SIZE_SHIFT 16 +#define V_SIZE_MASK (0x1FFF << V_SIZE_SHIFT) + +/* DC_WIN_PRESCALED_SIZE 0x706 */ +#define H_PRESCALED_SIZE_SHIFT 0 +#define H_PRESCALED_SIZE_MASK (0x7FFF << H_PRESCALED_SIZE) +#define V_PRESCALED_SIZE_SHIFT 16 +#define V_PRESCALED_SIZE_MASK (0x1FFF << V_PRESCALED_SIZE) + +/* DC_WIN_DDA_INCREMENT 0x709 */ +#define H_DDA_INC_SHIFT 0 +#define H_DDA_INC_MASK (0xFFFF << H_DDA_INC_SHIFT) +#define V_DDA_INC_SHIFT 16 +#define V_DDA_INC_MASK (0xFFFF << V_DDA_INC_SHIFT) + +#define DC_POLL_TIMEOUT_MS 50 +#define DC_N_WINDOWS 5 +#define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5) + +#endif /* __ASM_ARCH_TEGRA_DC_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/funcmux.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/funcmux.h new file mode 100644 index 000000000..cf3ce3b41 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/funcmux.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + */ + +/* Tegra high-level function multiplexing */ + +#ifndef _TEGRA_FUNCMUX_H_ +#define _TEGRA_FUNCMUX_H_ + +/** + * Select a config for a particular peripheral. + * + * Each peripheral can operate through a number of configurations, + * which are sets of pins that it uses to bring out its signals. + * The basic config is 0, and higher numbers indicate different + * pinmux settings to bring the peripheral out on other pins, + * + * This function also disables tristate for the function's pins, + * so that they operate in normal mode. + * + * @param id Peripheral id + * @param config Configuration to use (FUNCMUX_...), 0 for default + * @return 0 if ok, -1 on error (e.g. incorrect id or config) + */ +int funcmux_select(enum periph_id id, int config); + +#endif /* _TEGRA_FUNCMUX_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/fuse.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/fuse.h new file mode 100644 index 000000000..5b8e0bd8d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/fuse.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + */ + +#ifndef _FUSE_H_ +#define _FUSE_H_ + +/* FUSE registers */ +struct fuse_regs { + u32 reserved0[64]; /* 0x00 - 0xFC: */ + u32 production_mode; /* 0x100: FUSE_PRODUCTION_MODE */ + u32 reserved1[3]; /* 0x104 - 0x10c: */ + u32 sku_info; /* 0x110 */ + u32 reserved2[13]; /* 0x114 - 0x144: */ + u32 fa; /* 0x148: FUSE_FA */ + u32 reserved3[21]; /* 0x14C - 0x19C: */ + u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */ +}; + +#endif /* ifndef _FUSE_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/gp_padctrl.h new file mode 100644 index 000000000..4362c53d8 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/gp_padctrl.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010-2015 + * NVIDIA Corporation + */ + +#ifndef _TEGRA_GP_PADCTRL_H_ +#define _TEGRA_GP_PADCTRL_H_ + +#define GP_HIDREV 0x804 + +/* bit fields definitions for APB_MISC_GP_HIDREV register */ +#define HIDREV_CHIPID_SHIFT 8 +#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT) +#define HIDREV_MAJORPREV_SHIFT 4 +#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT) + +/* CHIPID field returned from APB_MISC_GP_HIDREV register */ +#define CHIPID_TEGRA20 0x20 +#define CHIPID_TEGRA30 0x30 +#define CHIPID_TEGRA114 0x35 +#define CHIPID_TEGRA124 0x40 +#define CHIPID_TEGRA210 0x21 + +#endif /* _TEGRA_GP_PADCTRL_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/gpio.h new file mode 100644 index 000000000..fe7b3a50e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/gpio.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011, Google Inc. All rights reserved. + */ + +#ifndef _TEGRA_GPIO_H_ +#define _TEGRA_GPIO_H_ + +#include + +#define TEGRA_GPIOS_PER_PORT 8 +#define TEGRA_PORTS_PER_BANK 4 +#define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8) +#define GPIO_NAME_SIZE 20 /* gpio_request max label len */ + +#define GPIO_BANK(x) ((x) >> 5) +#define GPIO_PORT(x) (((x) >> 3) & 0x3) +#define GPIO_FULLPORT(x) ((x) >> 3) +#define GPIO_BIT(x) ((x) & 0x7) + +enum tegra_gpio_init { + TEGRA_GPIO_INIT_IN, + TEGRA_GPIO_INIT_OUT0, + TEGRA_GPIO_INIT_OUT1, +}; + +struct tegra_gpio_config { + u32 gpio:16; + u32 init:2; +}; + +/** + * Configure a list of GPIOs + * + * @param config List of GPIO configurations + * @param len Number of config items in list + */ +void gpio_config_table(const struct tegra_gpio_config *config, int len); + +#endif /* TEGRA_GPIO_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/gpu.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/gpu.h new file mode 100644 index 000000000..d4d6deb49 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/gpu.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 + * NVIDIA Corporation + */ + +#ifndef __ASM_ARCH_TEGRA_GPU_H +#define __ASM_ARCH_TEGRA_GPU_H + +#if defined(CONFIG_TEGRA_GPU) + +void tegra_gpu_config(void); + +#else /* CONFIG_TEGRA_GPU */ + +static inline void tegra_gpu_config(void) +{ +} + +#endif /* CONFIG_TEGRA_GPU */ + +#if defined(CONFIG_OF_LIBFDT) + +int tegra_gpu_enable_node(void *blob, const char *gpupath); + +#else /* CONFIG_OF_LIBFDT */ + +static inline int tegra_gpu_enable_node(void *blob, const char *compat) +{ + return 0; +} + +#endif /* CONFIG_OF_LIBFDT */ + +#endif /* __ASM_ARCH_TEGRA_GPU_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/ivc.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/ivc.h new file mode 100644 index 000000000..52c10b8fa --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/ivc.h @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + */ + +#ifndef _ASM_ARCH_TEGRA_IVC_H +#define _ASM_ARCH_TEGRA_IVC_H + +/* + * Tegra IVC is a communication protocol that transfers fixed-size frames + * bi-directionally and in-order between the local CPU and some remote entity. + * Communication is via a statically sized and allocated buffer in shared + * memory and a notification mechanism. + * + * This API handles all aspects of the shared memory buffer's metadata, and + * leaves all aspects of the frame content to the calling code; frames + * typically contain some higher-level protocol. The notification mechanism is + * also handled externally to this API, since it can vary from instance to + * instance. + * + * The client model is to first find some free (for TX) or filled (for RX) + * frame, process that frame's memory buffer (fill or read it), and then + * inform the protocol that the frame has been filled/read, i.e. advance the + * write/read pointer. If the channel is full, there may be no available frames + * to fill/read. In this case, client code may either poll for an available + * frame, or wait for the remote entity to send a notification to the local + * CPU. + */ + +/** + * struct tegra_ivc - In-memory shared memory layout. + * + * This is described in detail in ivc.c. + */ +struct tegra_ivc_channel_header; + +/** + * struct tegra_ivc - Software state of an IVC channel. + * + * This state is internal to the IVC code and should not be accessed directly + * by clients. It is public solely so clients can allocate storage for the + * structure. + */ +struct tegra_ivc { + /** + * rx_channel - Pointer to the shared memory region used to receive + * messages from the remote entity. + */ + struct tegra_ivc_channel_header *rx_channel; + /** + * tx_channel - Pointer to the shared memory region used to send + * messages to the remote entity. + */ + struct tegra_ivc_channel_header *tx_channel; + /** + * r_pos - The position in list of frames in rx_channel that we are + * reading from. + */ + uint32_t r_pos; + /** + * w_pos - The position in list of frames in tx_channel that we are + * writing to. + */ + uint32_t w_pos; + /** + * nframes - The number of frames allocated (in each direction) in + * shared memory. + */ + uint32_t nframes; + /** + * frame_size - The size of each frame in shared memory. + */ + uint32_t frame_size; + /** + * notify - Function to call to notify the remote processor of a + * change in channel state. + */ + void (*notify)(struct tegra_ivc *); +}; + +/** + * tegra_ivc_read_get_next_frame - Locate the next frame to receive. + * + * Locate the next frame to be received/processed, return the address of the + * frame, and do not remove it from the queue. Repeated calls to this function + * will return the same address until tegra_ivc_read_advance() is called. + * + * @ivc The IVC channel. + * @frame Pointer to be filled with the address of the frame to receive. + * + * @return 0 if a frame is available, else a negative error code. + */ +int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, void **frame); + +/** + * tegra_ivc_read_advance - Advance the read queue. + * + * Inform the protocol and remote entity that the frame returned by + * tegra_ivc_read_get_next_frame() has been processed. The remote end may then + * re-use it to transmit further data. Subsequent to this function returning, + * tegra_ivc_read_get_next_frame() will return a different frame. + * + * @ivc The IVC channel. + * + * @return 0 if OK, else a negative error code. + */ +int tegra_ivc_read_advance(struct tegra_ivc *ivc); + +/** + * tegra_ivc_write_get_next_frame - Locate the next frame to fill for transmit. + * + * Locate the next frame to be filled for transmit, return the address of the + * frame, and do not add it to the queue. Repeated calls to this function + * will return the same address until tegra_ivc_read_advance() is called. + * + * @ivc The IVC channel. + * @frame Pointer to be filled with the address of the frame to fill. + * + * @return 0 if a frame is available, else a negative error code. + */ +int tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc, void **frame); + +/** + * tegra_ivc_write_advance - Advance the write queue. + * + * Inform the protocol and remote entity that the frame returned by + * tegra_ivc_write_get_next_frame() has been filled and should be transmitted. + * The remote end may then read data from it. Subsequent to this function + * returning, tegra_ivc_write_get_next_frame() will return a different frame. + * + * @ivc The IVC channel. + * + * @return 0 if OK, else a negative error code. + */ +int tegra_ivc_write_advance(struct tegra_ivc *ivc); + +/** + * tegra_ivc_channel_notified - handle internal messages + * + * This function must be called following every notification. + * + * @ivc The IVC channel. + * + * @return 0 if the channel is ready for communication, or -EAGAIN if a + * channel reset is in progress. + */ +int tegra_ivc_channel_notified(struct tegra_ivc *ivc); + +/** + * tegra_ivc_channel_reset - initiates a reset of the shared memory state + * + * This function must be called after a channel is initialized but before it + * is used for communication. The channel will be ready for use when a + * subsequent call to notify the remote of the channel reset indicates the + * reset operation is complete. + * + * @ivc The IVC channel. + */ +void tegra_ivc_channel_reset(struct tegra_ivc *ivc); + +/** + * tegra_ivc_init - Initialize a channel's software state. + * + * @ivc The IVC channel. + * @rx_base Address of the the RX shared memory buffer. + * @tx_base Address of the the TX shared memory buffer. + * @nframes Number of frames in each shared memory buffer. + * @frame_size Size of each frame. + * + * @return 0 if OK, else a negative error code. + */ +int tegra_ivc_init(struct tegra_ivc *ivc, ulong rx_base, ulong tx_base, + uint32_t nframes, uint32_t frame_size, + void (*notify)(struct tegra_ivc *)); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/pinmux.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/pinmux.h new file mode 100644 index 000000000..4b6e84195 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/pinmux.h @@ -0,0 +1,249 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010-2014 + * NVIDIA Corporation + */ + +#ifndef _TEGRA_PINMUX_H_ +#define _TEGRA_PINMUX_H_ + +#include + +#include + +/* The pullup/pulldown state of a pin group */ +enum pmux_pull { + PMUX_PULL_NORMAL = 0, + PMUX_PULL_DOWN, + PMUX_PULL_UP, +}; + +/* Defines whether a pin group is tristated or in normal operation */ +enum pmux_tristate { + PMUX_TRI_NORMAL = 0, + PMUX_TRI_TRISTATE = 1, +}; + +#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT +enum pmux_pin_io { + PMUX_PIN_OUTPUT = 0, + PMUX_PIN_INPUT = 1, + PMUX_PIN_NONE, +}; +#endif + +#ifdef TEGRA_PMX_PINS_HAVE_LOCK +enum pmux_pin_lock { + PMUX_PIN_LOCK_DEFAULT = 0, + PMUX_PIN_LOCK_DISABLE, + PMUX_PIN_LOCK_ENABLE, +}; +#endif + +#ifdef TEGRA_PMX_PINS_HAVE_OD +enum pmux_pin_od { + PMUX_PIN_OD_DEFAULT = 0, + PMUX_PIN_OD_DISABLE, + PMUX_PIN_OD_ENABLE, +}; +#endif + +#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET +enum pmux_pin_ioreset { + PMUX_PIN_IO_RESET_DEFAULT = 0, + PMUX_PIN_IO_RESET_DISABLE, + PMUX_PIN_IO_RESET_ENABLE, +}; +#endif + +#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL +enum pmux_pin_rcv_sel { + PMUX_PIN_RCV_SEL_DEFAULT = 0, + PMUX_PIN_RCV_SEL_NORMAL, + PMUX_PIN_RCV_SEL_HIGH, +}; +#endif + +#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV +enum pmux_pin_e_io_hv { + PMUX_PIN_E_IO_HV_DEFAULT = 0, + PMUX_PIN_E_IO_HV_NORMAL, + PMUX_PIN_E_IO_HV_HIGH, +}; +#endif + +#ifdef TEGRA_PMX_GRPS_HAVE_LPMD +/* Defines a pin group cfg's low-power mode select */ +enum pmux_lpmd { + PMUX_LPMD_X8 = 0, + PMUX_LPMD_X4, + PMUX_LPMD_X2, + PMUX_LPMD_X, + PMUX_LPMD_NONE = -1, +}; +#endif + +#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT) +/* Defines whether a pin group cfg's schmidt is enabled or not */ +enum pmux_schmt { + PMUX_SCHMT_DISABLE = 0, + PMUX_SCHMT_ENABLE = 1, + PMUX_SCHMT_NONE = -1, +}; +#endif + +#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM) +/* Defines whether a pin group cfg's high-speed mode is enabled or not */ +enum pmux_hsm { + PMUX_HSM_DISABLE = 0, + PMUX_HSM_ENABLE = 1, + PMUX_HSM_NONE = -1, +}; +#endif + +/* + * This defines the configuration for a pin, including the function assigned, + * pull up/down settings and tristate settings. Having set up one of these + * you can call pinmux_config_pingroup() to configure a pin in one step. Also + * available is pinmux_config_table() to configure a list of pins. + */ +struct pmux_pingrp_config { + u32 pingrp:16; /* pin group PMUX_PINGRP_... */ + u32 func:8; /* function to assign PMUX_FUNC_... */ + u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/ + u32 tristate:2; /* tristate or normal PMUX_TRI_... */ +#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT + u32 io:2; /* input or output PMUX_PIN_... */ +#endif +#ifdef TEGRA_PMX_PINS_HAVE_LOCK + u32 lock:2; /* lock enable/disable PMUX_PIN... */ +#endif +#ifdef TEGRA_PMX_PINS_HAVE_OD + u32 od:2; /* open-drain or push-pull driver */ +#endif +#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET + u32 ioreset:2; /* input/output reset PMUX_PIN... */ +#endif +#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL + u32 rcv_sel:2; /* select between High and Normal */ + /* VIL/VIH receivers */ +#endif +#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV + u32 e_io_hv:2; /* select 3.3v tolerant receivers */ +#endif +#ifdef TEGRA_PMX_PINS_HAVE_SCHMT + u32 schmt:2; /* schmitt enable */ +#endif +#ifdef TEGRA_PMX_PINS_HAVE_HSM + u32 hsm:2; /* high-speed mode enable */ +#endif +}; + +#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING +/* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */ +void pinmux_set_tristate_input_clamping(void); +void pinmux_clear_tristate_input_clamping(void); +#endif + +/* Set the mux function for a pin group */ +void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); + +/* Set the pull up/down feature for a pin group */ +void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); + +/* Set a pin group to tristate */ +void pinmux_tristate_enable(enum pmux_pingrp pin); + +/* Set a pin group to normal (non tristate) */ +void pinmux_tristate_disable(enum pmux_pingrp pin); + +#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT +/* Set a pin group as input or output */ +void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); +#endif + +/** + * Configure a list of pin groups + * + * @param config List of config items + * @param len Number of config items in list + */ +void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, + int len); + +struct pmux_pingrp_desc { + u8 funcs[4]; +#if defined(CONFIG_TEGRA20) + u8 ctl_id; + u8 pull_id; +#endif /* CONFIG_TEGRA20 */ +}; + +extern const struct pmux_pingrp_desc *tegra_soc_pingroups; + +#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS + +#define PMUX_SLWF_MIN 0 +#define PMUX_SLWF_MAX 3 +#define PMUX_SLWF_NONE -1 + +#define PMUX_SLWR_MIN 0 +#define PMUX_SLWR_MAX 3 +#define PMUX_SLWR_NONE -1 + +#define PMUX_DRVUP_MIN 0 +#define PMUX_DRVUP_MAX 127 +#define PMUX_DRVUP_NONE -1 + +#define PMUX_DRVDN_MIN 0 +#define PMUX_DRVDN_MAX 127 +#define PMUX_DRVDN_NONE -1 + +/* + * This defines the configuration for a pin group's pad control config + */ +struct pmux_drvgrp_config { + u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */ + u32 slwf:3; /* falling edge slew */ + u32 slwr:3; /* rising edge slew */ + u32 drvup:8; /* pull-up drive strength */ + u32 drvdn:8; /* pull-down drive strength */ +#ifdef TEGRA_PMX_GRPS_HAVE_LPMD + u32 lpmd:3; /* low-power mode selection */ +#endif +#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT + u32 schmt:2; /* schmidt enable */ +#endif +#ifdef TEGRA_PMX_GRPS_HAVE_HSM + u32 hsm:2; /* high-speed mode enable */ +#endif +}; + +/** + * Set the GP pad configs + * + * @param config List of config items + * @param len Number of config items in list + */ +void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, + int len); + +#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ + +#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS +struct pmux_mipipadctrlgrp_config { + u32 grp:16; /* pin group PMUX_MIPIPADCTRLGRP_x */ + u32 func:8; /* function to assign PMUX_FUNC_... */ +}; + +void pinmux_config_mipipadctrlgrp_table( + const struct pmux_mipipadctrlgrp_config *config, int len); + +struct pmux_mipipadctrlgrp_desc { + u8 funcs[2]; +}; + +extern const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups; +#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */ + +#endif /* _TEGRA_PINMUX_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/pmc.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/pmc.h new file mode 100644 index 000000000..e1f5a7381 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/pmc.h @@ -0,0 +1,413 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010-2019 + * NVIDIA Corporation + */ + +#ifndef _PMC_H_ +#define _PMC_H_ + +#ifndef __ASSEMBLY__ +#include +#endif + +/* Power Management Controller (APBDEV_PMC_) registers */ +struct pmc_ctlr { + uint pmc_cntrl; /* _CNTRL_0, offset 00 */ + uint pmc_sec_disable; /* _SEC_DISABLE_0, offset 04 */ + uint pmc_pmc_swrst; /* _PMC_SWRST_0, offset 08 */ + uint pmc_wake_mask; /* _WAKE_MASK_0, offset 0C */ + uint pmc_wake_lvl; /* _WAKE_LVL_0, offset 10 */ + uint pmc_wake_status; /* _WAKE_STATUS_0, offset 14 */ + uint pmc_sw_wake_status; /* _SW_WAKE_STATUS_0, offset 18 */ + uint pmc_dpd_pads_oride; /* _DPD_PADS_ORIDE_0, offset 1C */ + uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */ + uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */ + uint pmc_pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, offset 28 */ +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) + uint pmc_pwrgate_timer_on; /* _PWRGATE_TIMER_ON_0, offset 2C */ +#else + uint pmc_clamp_status; /* _CLAMP_STATUS_0, offset 2C */ +#endif + uint pmc_pwrgate_toggle; /* _PWRGATE_TOGGLE_0, offset 30 */ + uint pmc_remove_clamping; /* _REMOVE_CLAMPING_CMD_0, offset 34 */ + uint pmc_pwrgate_status; /* _PWRGATE_STATUS_0, offset 38 */ + uint pmc_pwrgood_timer; /* _PWRGOOD_TIMER_0, offset 3C */ + uint pmc_blink_timer; /* _BLINK_TIMER_0, offset 40 */ + uint pmc_no_iopower; /* _NO_IOPOWER_0, offset 44 */ + uint pmc_pwr_det; /* _PWR_DET_0, offset 48 */ + uint pmc_pwr_det_latch; /* _PWR_DET_LATCH_0, offset 4C */ + + uint pmc_scratch0; /* _SCRATCH0_0, offset 50 */ + uint pmc_scratch1; /* _SCRATCH1_0, offset 54 */ + uint pmc_scratch2; /* _SCRATCH2_0, offset 58 */ + uint pmc_scratch3; /* _SCRATCH3_0, offset 5C */ + uint pmc_scratch4; /* _SCRATCH4_0, offset 60 */ + uint pmc_scratch5; /* _SCRATCH5_0, offset 64 */ + uint pmc_scratch6; /* _SCRATCH6_0, offset 68 */ + uint pmc_scratch7; /* _SCRATCH7_0, offset 6C */ + uint pmc_scratch8; /* _SCRATCH8_0, offset 70 */ + uint pmc_scratch9; /* _SCRATCH9_0, offset 74 */ + uint pmc_scratch10; /* _SCRATCH10_0, offset 78 */ + uint pmc_scratch11; /* _SCRATCH11_0, offset 7C */ + uint pmc_scratch12; /* _SCRATCH12_0, offset 80 */ + uint pmc_scratch13; /* _SCRATCH13_0, offset 84 */ + uint pmc_scratch14; /* _SCRATCH14_0, offset 88 */ + uint pmc_scratch15; /* _SCRATCH15_0, offset 8C */ + uint pmc_scratch16; /* _SCRATCH16_0, offset 90 */ + uint pmc_scratch17; /* _SCRATCH17_0, offset 94 */ + uint pmc_scratch18; /* _SCRATCH18_0, offset 98 */ + uint pmc_scratch19; /* _SCRATCH19_0, offset 9C */ + uint pmc_scratch20; /* _SCRATCH20_0, offset A0 */ + uint pmc_scratch21; /* _SCRATCH21_0, offset A4 */ + uint pmc_scratch22; /* _SCRATCH22_0, offset A8 */ + uint pmc_scratch23; /* _SCRATCH23_0, offset AC */ + + uint pmc_secure_scratch0; /* _SECURE_SCRATCH0_0, offset B0 */ + uint pmc_secure_scratch1; /* _SECURE_SCRATCH1_0, offset B4 */ + uint pmc_secure_scratch2; /* _SECURE_SCRATCH2_0, offset B8 */ + uint pmc_secure_scratch3; /* _SECURE_SCRATCH3_0, offset BC */ + uint pmc_secure_scratch4; /* _SECURE_SCRATCH4_0, offset C0 */ + uint pmc_secure_scratch5; /* _SECURE_SCRATCH5_0, offset C4 */ + + uint pmc_cpupwrgood_timer; /* _CPUPWRGOOD_TIMER_0, offset C8 */ + uint pmc_cpupwroff_timer; /* _CPUPWROFF_TIMER_0, offset CC */ + uint pmc_pg_mask; /* _PG_MASK_0, offset D0 */ + uint pmc_pg_mask_1; /* _PG_MASK_1_0, offset D4 */ + uint pmc_auto_wake_lvl; /* _AUTO_WAKE_LVL_0, offset D8 */ + uint pmc_auto_wake_lvl_mask; /* _AUTO_WAKE_LVL_MASK_0, offset DC */ + uint pmc_wake_delay; /* _WAKE_DELAY_0, offset E0 */ + uint pmc_pwr_det_val; /* _PWR_DET_VAL_0, offset E4 */ + uint pmc_ddr_pwr; /* _DDR_PWR_0, offset E8 */ + uint pmc_usb_debounce_del; /* _USB_DEBOUNCE_DEL_0, offset EC */ + uint pmc_usb_ao; /* _USB_AO_0, offset F0 */ + uint pmc_crypto_op; /* _CRYPTO_OP__0, offset F4 */ + uint pmc_pllp_wb0_override; /* _PLLP_WB0_OVERRIDE_0, offset F8 */ + + uint pmc_scratch24; /* _SCRATCH24_0, offset FC */ + uint pmc_scratch25; /* _SCRATCH24_0, offset 100 */ + uint pmc_scratch26; /* _SCRATCH24_0, offset 104 */ + uint pmc_scratch27; /* _SCRATCH24_0, offset 108 */ + uint pmc_scratch28; /* _SCRATCH24_0, offset 10C */ + uint pmc_scratch29; /* _SCRATCH24_0, offset 110 */ + uint pmc_scratch30; /* _SCRATCH24_0, offset 114 */ + uint pmc_scratch31; /* _SCRATCH24_0, offset 118 */ + uint pmc_scratch32; /* _SCRATCH24_0, offset 11C */ + uint pmc_scratch33; /* _SCRATCH24_0, offset 120 */ + uint pmc_scratch34; /* _SCRATCH24_0, offset 124 */ + uint pmc_scratch35; /* _SCRATCH24_0, offset 128 */ + uint pmc_scratch36; /* _SCRATCH24_0, offset 12C */ + uint pmc_scratch37; /* _SCRATCH24_0, offset 130 */ + uint pmc_scratch38; /* _SCRATCH24_0, offset 134 */ + uint pmc_scratch39; /* _SCRATCH24_0, offset 138 */ + uint pmc_scratch40; /* _SCRATCH24_0, offset 13C */ + uint pmc_scratch41; /* _SCRATCH24_0, offset 140 */ + uint pmc_scratch42; /* _SCRATCH24_0, offset 144 */ + + uint pmc_bo_mirror0; /* _BOUNDOUT_MIRROR0_0, offset 148 */ + uint pmc_bo_mirror1; /* _BOUNDOUT_MIRROR1_0, offset 14C */ + uint pmc_bo_mirror2; /* _BOUNDOUT_MIRROR2_0, offset 150 */ + uint pmc_sys_33v_en; /* _SYS_33V_EN_0, offset 154 */ + uint pmc_bo_mirror_access; /* _BOUNDOUT_MIRROR_ACCESS_0, off158 */ + uint pmc_gate; /* _GATE_0, offset 15C */ + /* The following fields are in Tegra124 and later only */ + uint pmc_wake2_mask; /* _WAKE2_MASK_0, offset 160 */ + uint pmc_wake2_lvl; /* _WAKE2_LVL_0, offset 164 */ + uint pmc_wake2_stat; /* _WAKE2_STATUS_0, offset 168 */ + uint pmc_sw_wake2_stat; /* _SW_WAKE2_STATUS_0, offset 16C */ + uint pmc_auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, offset 170 */ + uint pmc_pg_mask2; /* _PG_MASK_2_0, offset 174 */ + uint pmc_pg_mask_ce1; /* _PG_MASK_CE1_0, offset 178 */ + uint pmc_pg_mask_ce2; /* _PG_MASK_CE2_0, offset 17C */ + uint pmc_pg_mask_ce3; /* _PG_MASK_CE3_0, offset 180 */ + uint pmc_pwrgate_timer_ce0; /* _PWRGATE_TIMER_CE_0_0, offset 184 */ + uint pmc_pwrgate_timer_ce1; /* _PWRGATE_TIMER_CE_1_0, offset 188 */ + uint pmc_pwrgate_timer_ce2; /* _PWRGATE_TIMER_CE_2_0, offset 18C */ + uint pmc_pwrgate_timer_ce3; /* _PWRGATE_TIMER_CE_3_0, offset 190 */ + uint pmc_pwrgate_timer_ce4; /* _PWRGATE_TIMER_CE_4_0, offset 194 */ + uint pmc_pwrgate_timer_ce5; /* _PWRGATE_TIMER_CE_5_0, offset 198 */ + uint pmc_pwrgate_timer_ce6; /* _PWRGATE_TIMER_CE_6_0, offset 19C */ + uint pmc_pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, offset 1A0 */ + uint pmc_osc_edpd_over; /* _OSC_EDPD_OVER_0, offset 1A4 */ + uint pmc_clk_out_cntrl; /* _CLK_OUT_CNTRL_0, offset 1A8 */ + uint pmc_sata_pwrgate; /* _SATA_PWRGT_0, offset 1AC */ + uint pmc_sensor_ctrl; /* _SENSOR_CTRL_0, offset 1B0 */ + uint pmc_reset_status; /* _RTS_STATUS_0, offset 1B4 */ + uint pmc_io_dpd_req; /* _IO_DPD_REQ_0, offset 1B8 */ + uint pmc_io_dpd_stat; /* _IO_DPD_STATUS_0, offset 1BC */ + uint pmc_io_dpd2_req; /* _IO_DPD2_REQ_0, offset 1C0 */ + uint pmc_io_dpd2_stat; /* _IO_DPD2_STATUS_0, offset 1C4 */ + uint pmc_sel_dpd_tim; /* _SEL_DPD_TIM_0, offset 1C8 */ + uint pmc_vddp_sel; /* _VDDP_SEL_0, offset 1CC */ + + uint pmc_ddr_cfg; /* _DDR_CFG_0, offset 1D0 */ + uint pmc_e_no_vttgen; /* _E_NO_VTTGEN_0, offset 1D4 */ + uint pmc_reserved0; /* _RESERVED, offset 1D8 */ + uint pmc_pllm_wb0_ovrride_frq; /* _PLLM_WB0_OVERRIDE_FREQ_0, off 1DC */ + uint pmc_test_pwrgate; /* _TEST_PWRGATE_0, offset 1E0 */ + uint pmc_pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, offset 1E4 */ + uint pmc_dsi_sel_dpd; /* _DSI_SEL_DPD_0, offset 1E8 */ + uint pmc_utmip_uhsic_triggers; /* _UTMIP_UHSIC_TRIGGERS_0, off 1EC */ + uint pmc_utmip_uhsic_saved_st; /* _UTMIP_UHSIC_SAVED_STATE_0, off1F0 */ + uint pmc_utmip_pad_cfg; /* _UTMIP_PAD_CFG_0, offset 1F4 */ + uint pmc_utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */ + uint pmc_utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, off 1FC */ + + uint pmc_todo_0[9]; /* offset 200-220 */ + uint pmc_secure_scratch6; /* _SECURE_SCRATCH6_0, offset 224 */ + uint pmc_secure_scratch7; /* _SECURE_SCRATCH7_0, offset 228 */ + uint pmc_scratch43; /* _SCRATCH43_0, offset 22C */ + uint pmc_scratch44; /* _SCRATCH44_0, offset 230 */ + uint pmc_scratch45; + uint pmc_scratch46; + uint pmc_scratch47; + uint pmc_scratch48; + uint pmc_scratch49; + uint pmc_scratch50; + uint pmc_scratch51; + uint pmc_scratch52; + uint pmc_scratch53; + uint pmc_scratch54; + uint pmc_scratch55; /* _SCRATCH55_0, offset 25C */ + uint pmc_scratch0_eco; /* _SCRATCH0_ECO_0, offset 260 */ + uint pmc_por_dpd_ctrl; /* _POR_DPD_CTRL_0, offset 264 */ + uint pmc_scratch2_eco; /* _SCRATCH2_ECO_0, offset 268 */ + uint pmc_todo_1[17]; /* TODO: 26C ~ 2AC */ + uint pmc_pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2, offset 2B0 */ + uint pmc_tsc_mult; /* _TSC_MULT_0, offset 2B4 */ + uint pmc_cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */ + uint pmc_glb_amap_cfg; /* _GLB_AMAP_CFG_0, offset 2BC */ + uint pmc_sticky_bits; /* _STICKY_BITS_0, offset 2C0 */ + uint pmc_sec_disable2; /* _SEC_DISALBE2, offset 2C4 */ + uint pmc_weak_bias; /* _WEAK_BIAS_0, offset 2C8 */ + uint pmc_todo_3[13]; /* TODO: 2CC ~ 2FC */ + uint pmc_secure_scratch8; /* _SECURE_SCRATCH8_0, offset 300 */ + uint pmc_secure_scratch9; + uint pmc_secure_scratch10; + uint pmc_secure_scratch11; + uint pmc_secure_scratch12; + uint pmc_secure_scratch13; + uint pmc_secure_scratch14; + uint pmc_secure_scratch15; + uint pmc_secure_scratch16; + uint pmc_secure_scratch17; + uint pmc_secure_scratch18; + uint pmc_secure_scratch19; + uint pmc_secure_scratch20; + uint pmc_secure_scratch21; + uint pmc_secure_scratch22; + uint pmc_secure_scratch23; + uint pmc_secure_scratch24; /* _SECURE_SCRATCH24_0, offset 340 */ + uint pmc_secure_scratch25; + uint pmc_secure_scratch26; + uint pmc_secure_scratch27; + uint pmc_secure_scratch28; + uint pmc_secure_scratch29; + uint pmc_secure_scratch30; + uint pmc_secure_scratch31; + uint pmc_secure_scratch32; + uint pmc_secure_scratch33; + uint pmc_secure_scratch34; + uint pmc_secure_scratch35; /* _SECURE_SCRATCH35_0, offset 36C */ + + uint pmc_reserved1[52]; /* RESERVED: 370 ~ 43C */ + uint pmc_cntrl2; /* _CNTRL2_0, offset 440 */ + uint pmc_reserved2[6]; /* RESERVED: 444 ~ 458 */ + uint pmc_io_dpd3_req; /* _IO_DPD3_REQ_0, offset 45c */ + uint pmc_io_dpd3_stat; /* _IO_DPD3_STATUS_0, offset 460 */ + uint pmc_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 464 */ + uint pmc_reserved3[102]; /* RESERVED: 468 ~ 5FC */ + + uint pmc_scratch56; /* _SCRATCH56_0, offset 600 */ + uint pmc_scratch57; + uint pmc_scratch58; + uint pmc_scratch59; + uint pmc_scratch60; + uint pmc_scratch61; + uint pmc_scratch62; + uint pmc_scratch63; + uint pmc_scratch64; + uint pmc_scratch65; + uint pmc_scratch66; + uint pmc_scratch67; + uint pmc_scratch68; + uint pmc_scratch69; + uint pmc_scratch70; + uint pmc_scratch71; + uint pmc_scratch72; + uint pmc_scratch73; + uint pmc_scratch74; + uint pmc_scratch75; + uint pmc_scratch76; + uint pmc_scratch77; + uint pmc_scratch78; + uint pmc_scratch79; + uint pmc_scratch80; + uint pmc_scratch81; + uint pmc_scratch82; + uint pmc_scratch83; + uint pmc_scratch84; + uint pmc_scratch85; + uint pmc_scratch86; + uint pmc_scratch87; + uint pmc_scratch88; + uint pmc_scratch89; + uint pmc_scratch90; + uint pmc_scratch91; + uint pmc_scratch92; + uint pmc_scratch93; + uint pmc_scratch94; + uint pmc_scratch95; + uint pmc_scratch96; + uint pmc_scratch97; + uint pmc_scratch98; + uint pmc_scratch99; + uint pmc_scratch100; + uint pmc_scratch101; + uint pmc_scratch102; + uint pmc_scratch103; + uint pmc_scratch104; + uint pmc_scratch105; + uint pmc_scratch106; + uint pmc_scratch107; + uint pmc_scratch108; + uint pmc_scratch109; + uint pmc_scratch110; + uint pmc_scratch111; + uint pmc_scratch112; + uint pmc_scratch113; + uint pmc_scratch114; + uint pmc_scratch115; + uint pmc_scratch116; + uint pmc_scratch117; + uint pmc_scratch118; + uint pmc_scratch119; + uint pmc_scratch1_eco; /* offset 700 */ +}; + +#define CPU_PWRED 1 +#define CPU_CLMP 1 + +#define PARTID_CP 0xFFFFFFF8 +#define START_CP (1 << 8) + +#define CPUPWRREQ_OE (1 << 16) +#define CPUPWRREQ_POL (1 << 15) + +#define CRAIL 0 +#define CE0 14 +#define C0NC 15 +#define SOR 17 + +#define PMC_XOFS_SHIFT 1 +#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT) + +#if defined(CONFIG_TEGRA114) +#define TIMER_MULT_SHIFT 0 +#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT) +#define TIMER_MULT_CPU_SHIFT 2 +#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT) +#elif defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) +#define TIMER_MULT_SHIFT 0 +#define TIMER_MULT_MASK (7 << TIMER_MULT_SHIFT) +#define TIMER_MULT_CPU_SHIFT 3 +#define TIMER_MULT_CPU_MASK (7 << TIMER_MULT_CPU_SHIFT) +#endif + +#define MULT_1 0 +#define MULT_2 1 +#define MULT_4 2 +#define MULT_8 3 +#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) +#define MULT_16 4 +#endif + +#define AMAP_WRITE_SHIFT 20 +#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT) + +/* SEC_DISABLE_0, 0x04 */ +#define SEC_DISABLE_WRITE0_ON (1 << 4) +#define SEC_DISABLE_READ0_ON (1 << 5) +#define SEC_DISABLE_WRITE1_ON (1 << 6) +#define SEC_DISABLE_READ1_ON (1 << 7) +#define SEC_DISABLE_WRITE2_ON (1 << 8) +#define SEC_DISABLE_READ2_ON (1 << 9) +#define SEC_DISABLE_WRITE3_ON (1 << 10) +#define SEC_DISABLE_READ3_ON (1 << 11) +#define SEC_DISABLE_AMAP_WRITE_ON (1 << 20) + +/* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */ +#define PWRGATE_TOGGLE_PARTID_CRAIL 0 +#define PWRGATE_TOGGLE_PARTID_TD 1 +#define PWRGATE_TOGGLE_PARTID_VE 2 +#define PWRGATE_TOGGLE_PARTID_PCX 3 +#define PWRGATE_TOGGLE_PARTID_VDE 4 +#define PWRGATE_TOGGLE_PARTID_L2C 5 +#define PWRGATE_TOGGLE_PARTID_MPE 6 +#define PWRGATE_TOGGLE_PARTID_HEG 7 +#define PWRGATE_TOGGLE_PARTID_SAX 8 +#define PWRGATE_TOGGLE_PARTID_CE1 9 +#define PWRGATE_TOGGLE_PARTID_CE2 10 +#define PWRGATE_TOGGLE_PARTID_CE3 11 +#define PWRGATE_TOGGLE_PARTID_CELP 12 +#define PWRGATE_TOGGLE_PARTID_CE0 14 +#define PWRGATE_TOGGLE_PARTID_C0NC 15 +#define PWRGATE_TOGGLE_PARTID_C1NC 16 +#define PWRGATE_TOGGLE_PARTID_SOR 17 +#define PWRGATE_TOGGLE_PARTID_DIS 18 +#define PWRGATE_TOGGLE_PARTID_DISB 19 +#define PWRGATE_TOGGLE_PARTID_XUSBA 20 +#define PWRGATE_TOGGLE_PARTID_XUSBB 21 +#define PWRGATE_TOGGLE_PARTID_XUSBC 22 +#define PWRGATE_TOGGLE_PARTID_VIC 23 +#define PWRGATE_TOGGLE_PARTID_IRAM 24 +#define PWRGATE_TOGGLE_START (1 << 8) + +/* APBDEV_PMC_PWRGATE_STATUS_0 0x38 */ +#define PWRGATE_STATUS_CRAIL_ENABLE (1 << 0) +#define PWRGATE_STATUS_TD_ENABLE (1 << 1) +#define PWRGATE_STATUS_VE_ENABLE (1 << 2) +#define PWRGATE_STATUS_PCX_ENABLE (1 << 3) +#define PWRGATE_STATUS_VDE_ENABLE (1 << 4) +#define PWRGATE_STATUS_L2C_ENABLE (1 << 5) +#define PWRGATE_STATUS_MPE_ENABLE (1 << 6) +#define PWRGATE_STATUS_HEG_ENABLE (1 << 7) +#define PWRGATE_STATUS_SAX_ENABLE (1 << 8) +#define PWRGATE_STATUS_CE1_ENABLE (1 << 9) +#define PWRGATE_STATUS_CE2_ENABLE (1 << 10) +#define PWRGATE_STATUS_CE3_ENABLE (1 << 11) +#define PWRGATE_STATUS_CELP_ENABLE (1 << 12) +#define PWRGATE_STATUS_CE0_ENABLE (1 << 14) +#define PWRGATE_STATUS_C0NC_ENABLE (1 << 15) +#define PWRGATE_STATUS_C1NC_ENABLE (1 << 16) +#define PWRGATE_STATUS_SOR_ENABLE (1 << 17) +#define PWRGATE_STATUS_DIS_ENABLE (1 << 18) +#define PWRGATE_STATUS_DISB_ENABLE (1 << 19) +#define PWRGATE_STATUS_XUSBA_ENABLE (1 << 20) +#define PWRGATE_STATUS_XUSBB_ENABLE (1 << 21) +#define PWRGATE_STATUS_XUSBC_ENABLE (1 << 22) +#define PWRGATE_STATUS_VIC_ENABLE (1 << 23) +#define PWRGATE_STATUS_IRAM_ENABLE (1 << 24) + +/* APBDEV_PMC_CNTRL2_0 0x440 */ +#define HOLD_CKE_LOW_EN (1 << 12) + +/* PMC read/write functions */ +u32 tegra_pmc_readl(unsigned long offset); +void tegra_pmc_writel(u32 value, unsigned long offset); + +#define PMC_CNTRL 0x0 +#define PMC_CNTRL_MAIN_RST BIT(4) + +#if IS_ENABLED(CONFIG_TEGRA186) +# define PMC_SCRATCH0 0x32000 +#else +# define PMC_SCRATCH0 0x00050 +#endif + +/* for secure PMC */ +#define TEGRA_SMC_PMC 0xc2fffe00 +#define TEGRA_SMC_PMC_READ 0xaa +#define TEGRA_SMC_PMC_WRITE 0xbb + +#endif /* PMC_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/pmu.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/pmu.h new file mode 100644 index 000000000..e850875d3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/pmu.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + */ + +#ifndef _TEGRA_PMU_H_ +#define _TEGRA_PMU_H_ + +/* Set core and CPU voltages to nominal levels */ +int pmu_set_nominal(void); + +#endif /* _TEGRA_PMU_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/powergate.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/powergate.h new file mode 100644 index 000000000..2e491f190 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/powergate.h @@ -0,0 +1,39 @@ +#ifndef _TEGRA_POWERGATE_H_ +#define _TEGRA_POWERGATE_H_ + +#include + +enum tegra_powergate { + TEGRA_POWERGATE_CPU, + TEGRA_POWERGATE_3D, + TEGRA_POWERGATE_VENC, + TEGRA_POWERGATE_PCIE, + TEGRA_POWERGATE_VDEC, + TEGRA_POWERGATE_L2, + TEGRA_POWERGATE_MPE, + TEGRA_POWERGATE_HEG, + TEGRA_POWERGATE_SATA, + TEGRA_POWERGATE_CPU1, + TEGRA_POWERGATE_CPU2, + TEGRA_POWERGATE_CPU3, + TEGRA_POWERGATE_CELP, + TEGRA_POWERGATE_3D1, + TEGRA_POWERGATE_CPU0, + TEGRA_POWERGATE_C0NC, + TEGRA_POWERGATE_C1NC, + TEGRA_POWERGATE_SOR, + TEGRA_POWERGATE_DIS, + TEGRA_POWERGATE_DISB, + TEGRA_POWERGATE_XUSBA, + TEGRA_POWERGATE_XUSBB, + TEGRA_POWERGATE_XUSBC, + TEGRA_POWERGATE_VIC, + TEGRA_POWERGATE_IRAM, +}; + +int tegra_powergate_sequence_power_up(enum tegra_powergate id, + enum periph_id periph); +int tegra_powergate_power_on(enum tegra_powergate id); +int tegra_powergate_power_off(enum tegra_powergate id); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/pwm.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/pwm.h new file mode 100644 index 000000000..eebd104de --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/pwm.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Tegra pulse width frequency modulator definitions + * + * Copyright (c) 2011 The Chromium OS Authors. + */ + +#ifndef __ASM_ARCH_TEGRA_PWM_H +#define __ASM_ARCH_TEGRA_PWM_H + +/* This is a single PWM channel */ +struct pwm_ctlr { + uint control; /* Control register */ + uint reserved[3]; /* Space space */ +}; + +#define PWM_NUM_CHANNELS 4 + +/* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */ +#define PWM_ENABLE_SHIFT 31 +#define PWM_ENABLE_MASK (0x1 << PWM_ENABLE_SHIFT) + +#define PWM_WIDTH_SHIFT 16 +#define PWM_WIDTH_MASK (0x7FFF << PWM_WIDTH_SHIFT) + +#define PWM_DIVIDER_SHIFT 0 +#define PWM_DIVIDER_MASK (0x1FFF << PWM_DIVIDER_SHIFT) + +#endif /* __ASM_ARCH_TEGRA_PWM_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/scu.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/scu.h new file mode 100644 index 000000000..afe076419 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/scu.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + */ + +#ifndef _SCU_H_ +#define _SCU_H_ + +/* ARM Snoop Control Unit (SCU) registers */ +struct scu_ctlr { + uint scu_ctrl; /* SCU Control Register, offset 00 */ + uint scu_cfg; /* SCU Config Register, offset 04 */ + uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */ + uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */ + uint scu_reserved0[12]; /* reserved, offset 10-3C */ + uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */ + uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */ + uint scu_reserved1[2]; /* reserved, offset 48-4C */ + uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */ + uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */ +}; + +#define SCU_CTRL_ENABLE (1 << 0) + +#endif /* SCU_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/sys_proto.h new file mode 100644 index 000000000..62e1c7bcd --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/sys_proto.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +void invalidate_dcache(void); + +/** + * tegra_board_id() - Get the board iD + * + * @return a board ID, or -ve on error + */ +int tegra_board_id(void); + +/** + * tegra_lcd_pmic_init() - Set up the PMIC for a board + * + * @board_id: Board ID which may be used to select LCD type + * @return 0 if OK, -ve on error + */ +int tegra_lcd_pmic_init(int board_id); + +/** + * nvidia_board_init() - perform any board-specific init + * + * @return 0 if OK, -ve on error + */ +int nvidia_board_init(void); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra.h new file mode 100644 index 000000000..7a4e0972f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010-2015 + * NVIDIA Corporation + */ + +#ifndef _TEGRA_H_ +#define _TEGRA_H_ + +#define NV_PA_ARM_PERIPHBASE 0x50040000 +#define NV_PA_PG_UP_BASE 0x60000000 +#define NV_PA_TMRUS_BASE 0x60005010 +#define NV_PA_CLK_RST_BASE 0x60006000 +#define NV_PA_FLOW_BASE 0x60007000 +#define NV_PA_GPIO_BASE 0x6000D000 +#define NV_PA_EVP_BASE 0x6000F000 +#define NV_PA_APB_MISC_BASE 0x70000000 +#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800) +#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000) +#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040) +#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200) +#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) +#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) +#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000) +#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) +#define NV_PA_SLINK1_BASE (NV_PA_APB_MISC_BASE + 0xD400) +#define NV_PA_SLINK2_BASE (NV_PA_APB_MISC_BASE + 0xD600) +#define NV_PA_SLINK3_BASE (NV_PA_APB_MISC_BASE + 0xD800) +#define NV_PA_SLINK4_BASE (NV_PA_APB_MISC_BASE + 0xDA00) +#define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00) +#define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00) +#define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000) +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ + defined(CONFIG_TEGRA114) || defined(CONFIG_TEGRA124) || \ + defined(CONFIG_TEGRA132) || defined(CONFIG_TEGRA210) +#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) +#else +#define NV_PA_PMC_BASE 0xc360000 +#endif +#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400) +#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ + defined(CONFIG_TEGRA114) +#define NV_PA_CSITE_BASE 0x70040000 +#else +#define NV_PA_CSITE_BASE 0x70800000 +#endif +#define TEGRA_USB_ADDR_MASK 0xFFFFC000 + +#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE +#define LOW_LEVEL_SRAM_STACK 0x4000FFFC +#define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000) +#define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096) +#define PG_UP_TAG_AVP 0xAAAAAAAA + +#ifndef __ASSEMBLY__ +struct timerus { + unsigned int cntr_1us; +}; + +/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */ +#define NV_WB_RUN_ADDRESS 0x40020000 + +#define NVBOOTTYPE_RECOVERY 2 /* BR entered RCM */ +#define NVBOOTINFOTABLE_BOOTTYPE 0xC /* Boot type in BIT in IRAM */ +#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */ +#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */ + +/* These are the available SKUs (product types) for Tegra */ +enum { + SKU_ID_T20_7 = 0x7, + SKU_ID_T20 = 0x8, + SKU_ID_T25SE = 0x14, + SKU_ID_AP25 = 0x17, + SKU_ID_T25 = 0x18, + SKU_ID_AP25E = 0x1b, + SKU_ID_T25E = 0x1c, + SKU_ID_T33 = 0x80, + SKU_ID_T30 = 0x81, /* Cardhu value */ + SKU_ID_TM30MQS_P_A3 = 0xb1, + SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */ + SKU_ID_T114_1 = 0x01, + SKU_ID_T124_ENG = 0x00, /* Venice2 value, unfused */ + SKU_ID_T210_ENG = 0x00, /* unfused value TBD */ +}; + +/* + * These are used to distinguish SOC types for setting up clocks. Mostly + * we can tell the clocking required by looking at the SOC sku_id, but + * for T30 it is a user option as to whether to run PLLP in fast or slow + * mode, so we have two options there. + */ +enum { + TEGRA_SOC_T20, + TEGRA_SOC_T25, + TEGRA_SOC_T30, + TEGRA_SOC_T114, + TEGRA_SOC_T124, + TEGRA_SOC_T210, + + TEGRA_SOC_CNT, + TEGRA_SOC_UNKNOWN = -1, +}; + +/* Tegra system controller (SYSCON) devices */ +enum { + TEGRA_SYSCON_PMC, +}; + +#else /* __ASSEMBLY__ */ +#define PRM_RSTCTRL NV_PA_PMC_BASE +#endif + +#endif /* TEGRA_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_ahub.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_ahub.h new file mode 100644 index 000000000..96d542a91 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_ahub.h @@ -0,0 +1,475 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * tegra_ahub.h - Definitions for Tegra124 audio hub driver + * Taken from dc tegra_ahub.h + * + * Copyright 2018 Google LLC + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA_AHUB_H_ +#define _TEGRA_AHUB_H_ + +/* + * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio + * transmitted by a particular TX CIF. + */ +struct xbar_regs { + u32 apbif_rx0; /* AUDIO_APBIF_RX0, offset 0x00 */ + u32 apbif_rx1; /* AUDIO_APBIF_RX1, offset 0x04 */ + u32 apbif_rx2; /* AUDIO_APBIF_RX2, offset 0x08 */ + u32 apbif_rx3; /* AUDIO_APBIF_RX3, offset 0x0C */ + + u32 i2s0_rx0; /* AUDIO_I2S0_RX0, offset 0x10 */ + u32 i2s1_rx0; /* AUDIO_I2S1_RX0, offset 0x14 */ + u32 i2s2_rx0; /* AUDIO_I2S2_RX0, offset 0x18 */ + u32 i2s3_rx0; /* AUDIO_I2S3_RX0, offset 0x1C */ + u32 i2s4_rx0; /* AUDIO_I2S4_RX0, offset 0x20 */ + + u32 dam0_rx0; /* AUDIO_DAM0_RX0, offset 0x24 */ + u32 dam0_rx1; /* AUDIO_DAM0_RX1, offset 0x28 */ + u32 dam1_rx0; /* AUDIO_DAM1_RX0, offset 0x2C */ + u32 dam1_rx1; /* AUDIO_DAM1_RX1, offset 0x30 */ + u32 dam2_rx0; /* AUDIO_DAM2_RX0, offset 0x34 */ + u32 dam2_rx1; /* AUDIO_DAM2_RX1, offset 0x38 */ + + u32 spdif_rx0; /* AUDIO_SPDIF_RX0, offset 0x3C */ + u32 spdif_rx1; /* AUDIO_SPDIF_RX1, offset 0x40 */ + + u32 apbif_rx4; /* AUDIO_APBIF_RX4, offset 0x44 */ + u32 apbif_rx5; /* AUDIO_APBIF_RX4, offset 0x48 */ + u32 apbif_rx6; /* AUDIO_APBIF_RX4, offset 0x4C */ + u32 apbif_rx7; /* AUDIO_APBIF_RX4, offset 0x50 */ + u32 apbif_rx8; /* AUDIO_APBIF_RX4, offset 0x54 */ + u32 apbif_rx9; /* AUDIO_APBIF_RX4, offset 0x58 */ + + u32 amx0_rx0; /* AUDIO_AMX0_RX0, offset 0x5C */ + u32 amx0_rx1; /* AUDIO_AMX0_RX1, offset 0x60 */ + u32 amx0_rx2; /* AUDIO_AMX0_RX2, offset 0x64 */ + u32 amx0_rx3; /* AUDIO_AMX0_RX3, offset 0x68 */ + + u32 adx0_rx0; /* AUDIO_ADX0_RX0, offset 0x6C */ +}; + +struct apbif_regs { + u32 channel0_ctrl; /* APBIF_CHANNEL0_CTRL */ + u32 channel0_clr; /* APBIF_CHANNEL0_CLEAR */ + u32 channel0_stat; /* APBIF_CHANNEL0_STATUS */ + u32 channel0_txfifo; /* APBIF_CHANNEL0_TXFIFO */ + u32 channel0_rxfifo; /* APBIF_CHANNEL0_RXFIFO */ + u32 channel0_cif_tx0_ctrl; /* APBIF_AUDIOCIF_TX0_CTRL */ + u32 channel0_cif_rx0_ctrl; /* APBIF_AUDIOCIF_RX0_CTRL */ + u32 channel0_reserved0; /* RESERVED, offset 0x1C */ + /* ahub_channel1_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */ + /* ahub_channel2_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */ + /* ahub_channel3_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */ + u32 reserved123[3 * 8]; + u32 config_link_ctrl; /* APBIF_CONFIG_LINK_CTRL_0, off 0x80 */ + u32 misc_ctrl; /* APBIF_MISC_CTRL_0, offset 0x84 */ + u32 apbdma_live_stat; /* APBIF_APBDMA_LIVE_STATUS_0 */ + u32 i2s_live_stat; /* APBIF_I2S_LIVE_STATUS_0 */ + u32 dam0_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */ + u32 dam1_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */ + u32 dam2_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */ + u32 spdif_live_stat; /* APBIF_SPDIF_LIVE_STATUS_0 */ + u32 i2s_int_mask; /* APBIF_I2S_INT_MASK_0, offset B0 */ + u32 dam_int_mask; /* APBIF_DAM_INT_MASK_0 */ + u32 reserved_int_mask; /* RESERVED, offset 0xB8 */ + u32 spdif_int_mask; /* APBIF_SPDIF_INT_MASK_0 */ + u32 apbif_int_mask; /* APBIF_APBIF_INT_MASK_0, off C0 */ + u32 reserved2_int_mask; /* RESERVED, offset 0xC4 */ + u32 i2s_int_stat; /* APBIF_I2S_INT_STATUS_0, offset C8 */ + u32 dam_int_stat; /* APBIF_DAM_INT_STATUS_0 */ + u32 reserved_int_stat; /* RESERVED, offset 0xD0 */ + u32 spdif_int_stat; /* APBIF_SPDIF_INT_STATUS_0 */ + u32 apbif_int_stat; /* APBIF_APBIF_INT_STATUS_0 */ + u32 reserved2_int_stat; /* RESERVED, offset 0xDC */ + u32 i2s_int_src; /* APBIF_I2S_INT_SOURCE_0, offset E0 */ + u32 dam_int_src; /* APBIF_DAM_INT_SOURCE_0 */ + u32 reserved_int_src; /* RESERVED, offset 0xE8 */ + u32 spdif_int_src; /* APBIF_SPDIF_INT_SOURCE_0 */ + u32 apbif_int_src; /* APBIF_APBIF_INT_SOURCE_0, off F0 */ + u32 reserved2_int_src; /* RESERVED, offset 0xF4 */ + u32 i2s_int_set; /* APBIF_I2S_INT_SET_0, offset 0xF8 */ + u32 dam_int_set; /* APBIF_DAM_INT_SET_0, offset 0xFC */ + u32 spdif_int_set; /* APBIF_SPDIF_INT_SET_0, off 0x100 */ + u32 apbif_int_set; /* APBIF_APBIF_INT_SET_0, off 0x104 */ +}; + +/* + * Tegra AHUB Registers Definition + */ +enum { + TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT = 24, + TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US = 0x3f, + TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK = + TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << + TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT, + + /* Channel count minus 1 */ + TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT = 20, + TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US = 0xf, + TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK = + TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << + TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT, + + /* Channel count minus 1 */ + TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT = 16, + TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US = 0xf, + TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK = + TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << + TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT, + + TEGRA_AUDIOCIF_BITS_4 = 0, + TEGRA_AUDIOCIF_BITS_8 = 1, + TEGRA_AUDIOCIF_BITS_12 = 2, + TEGRA_AUDIOCIF_BITS_16 = 3, + TEGRA_AUDIOCIF_BITS_20 = 4, + TEGRA_AUDIOCIF_BITS_24 = 5, + TEGRA_AUDIOCIF_BITS_28 = 6, + TEGRA_AUDIOCIF_BITS_32 = 7, + + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT = 12, + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_MASK = + 7 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_4 = + TEGRA_AUDIOCIF_BITS_4 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_8 = + TEGRA_AUDIOCIF_BITS_8 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_12 = + TEGRA_AUDIOCIF_BITS_12 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_16 = + TEGRA_AUDIOCIF_BITS_16 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_20 = + TEGRA_AUDIOCIF_BITS_20 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_24 = + TEGRA_AUDIOCIF_BITS_24 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_28 = + TEGRA_AUDIOCIF_BITS_28 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_32 = + TEGRA_AUDIOCIF_BITS_32 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, + + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT = 8, + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_MASK = + 7 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_4 = + TEGRA_AUDIOCIF_BITS_4 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_8 = + TEGRA_AUDIOCIF_BITS_8 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_12 = + TEGRA_AUDIOCIF_BITS_12 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_16 = + TEGRA_AUDIOCIF_BITS_16 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_20 = + TEGRA_AUDIOCIF_BITS_20 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_24 = + TEGRA_AUDIOCIF_BITS_24 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_28 = + TEGRA_AUDIOCIF_BITS_28 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_32 = + TEGRA_AUDIOCIF_BITS_32 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, + + TEGRA_AUDIOCIF_EXPAND_ZERO = 0, + TEGRA_AUDIOCIF_EXPAND_ONE = 1, + TEGRA_AUDIOCIF_EXPAND_LFSR = 2, + + TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT = 6, + TEGRA_AUDIOCIF_CTRL_EXPAND_MASK = 3 << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT, + TEGRA_AUDIOCIF_CTRL_EXPAND_ZERO = + TEGRA_AUDIOCIF_EXPAND_ZERO << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT, + TEGRA_AUDIOCIF_CTRL_EXPAND_ONE = + TEGRA_AUDIOCIF_EXPAND_ONE << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT, + TEGRA_AUDIOCIF_CTRL_EXPAND_LFSR = + TEGRA_AUDIOCIF_EXPAND_LFSR << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT, + + TEGRA_AUDIOCIF_STEREO_CONV_CH0 = 0, + TEGRA_AUDIOCIF_STEREO_CONV_CH1 = 1, + TEGRA_AUDIOCIF_STEREO_CONV_AVG = 2, + + TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT = 4, + TEGRA_AUDIOCIF_CTRL_STEREO_CONV_MASK = + 3 << TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT, + TEGRA_AUDIOCIF_CTRL_STEREO_CONV_CH0 = + TEGRA_AUDIOCIF_STEREO_CONV_CH0 << + TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT, + TEGRA_AUDIOCIF_CTRL_STEREO_CONV_CH1 = + TEGRA_AUDIOCIF_STEREO_CONV_CH1 << + TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT, + TEGRA_AUDIOCIF_CTRL_STEREO_CONV_AVG = + TEGRA_AUDIOCIF_STEREO_CONV_AVG << + TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT, + + TEGRA_AUDIOCIF_CTRL_REPLICATE = 3, + + TEGRA_AUDIOCIF_DIRECTION_TX = 0, + TEGRA_AUDIOCIF_DIRECTION_RX = 1, + + TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT = 2, + TEGRA_AUDIOCIF_CTRL_DIRECTION_MASK = + 1 << TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT, + TEGRA_AUDIOCIF_CTRL_DIRECTION_TX = + TEGRA_AUDIOCIF_DIRECTION_TX << + TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT, + TEGRA_AUDIOCIF_CTRL_DIRECTION_RX = + TEGRA_AUDIOCIF_DIRECTION_RX << + TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT, + + TEGRA_AUDIOCIF_TRUNCATE_ROUND = 0, + TEGRA_AUDIOCIF_TRUNCATE_CHOP = 1, + + TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT = 1, + TEGRA_AUDIOCIF_CTRL_TRUNCATE_MASK = + 1 << TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT, + TEGRA_AUDIOCIF_CTRL_TRUNCATE_ROUND = + TEGRA_AUDIOCIF_TRUNCATE_ROUND << + TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT, + TEGRA_AUDIOCIF_CTRL_TRUNCATE_CHOP = + TEGRA_AUDIOCIF_TRUNCATE_CHOP << + TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT, + + TEGRA_AUDIOCIF_MONO_CONV_ZERO = 0, + TEGRA_AUDIOCIF_MONO_CONV_COPY = 1, + + TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT = 0, + TEGRA_AUDIOCIF_CTRL_MONO_CONV_MASK = + 1 << TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT, + TEGRA_AUDIOCIF_CTRL_MONO_CONV_ZERO = + TEGRA_AUDIOCIF_MONO_CONV_ZERO << + TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT, + TEGRA_AUDIOCIF_CTRL_MONO_CONV_COPY = + TEGRA_AUDIOCIF_MONO_CONV_COPY << + TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT, + + /* Registers within TEGRA_AUDIO_CLUSTER_BASE */ + + TEGRA_AHUB_CHANNEL_CTRL = 0x0, + TEGRA_AHUB_CHANNEL_CTRL_STRIDE = 0x20, + TEGRA_AHUB_CHANNEL_CTRL_COUNT = 4, + TEGRA_AHUB_CHANNEL_CTRL_TX_EN = 1 << 31, + TEGRA_AHUB_CHANNEL_CTRL_RX_EN = 1 << 30, + TEGRA_AHUB_CHANNEL_CTRL_LOOPBACK = 1 << 29, + + TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT = 16, + TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US = 0xff, + TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK = + TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US << + TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT, + + TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT = 8, + TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US = 0xff, + TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK = + TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US << + TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT, + + TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_EN = 1 << 6, + + TEGRA_PACK_8_4 = 2, + TEGRA_PACK_16 = 3, + + TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT = 4, + TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US = 3, + TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK = + TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US << + TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT, + TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_8_4 = + TEGRA_PACK_8_4 << TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT, + TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_16 = + TEGRA_PACK_16 << TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT, + + TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_EN = 1 << 2, + + TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT = 0, + TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US = 3, + TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK = + TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US << + TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT, + TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_8_4 = + TEGRA_PACK_8_4 << TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT, + TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_16 = + TEGRA_PACK_16 << TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT, + + /* TEGRA_AHUB_CHANNEL_CLEAR */ + + TEGRA_AHUB_CHANNEL_CLEAR = 0x4, + TEGRA_AHUB_CHANNEL_CLEAR_STRIDE = 0x20, + TEGRA_AHUB_CHANNEL_CLEAR_COUNT = 4, + TEGRA_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET = 1 << 31, + TEGRA_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET = 1 << 30, + + TEGRA_AHUB_CHANNEL_STATUS = 0x8, + TEGRA_AHUB_CHANNEL_STATUS_STRIDE = 0x20, + TEGRA_AHUB_CHANNEL_STATUS_COUNT = 4, + TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT = 24, + TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US = 0xff, + TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK = + TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US << + TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT, + TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT = 16, + TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US = 0xff, + TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK = + TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US << + TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT, + TEGRA_AHUB_CHANNEL_STATUS_TX_TRIG = 1 << 1, + TEGRA_AHUB_CHANNEL_STATUS_RX_TRIG = 1 << 0, + + TEGRA_AHUB_CHANNEL_TXFIFO = 0xc, + TEGRA_AHUB_CHANNEL_TXFIFO_STRIDE = 0x20, + TEGRA_AHUB_CHANNEL_TXFIFO_COUNT = 4, + + TEGRA_AHUB_CHANNEL_RXFIFO = 0x10, + TEGRA_AHUB_CHANNEL_RXFIFO_STRIDE = 0x20, + TEGRA_AHUB_CHANNEL_RXFIFO_COUNT = 4, + + TEGRA_AHUB_CIF_TX_CTRL = 0x14, + TEGRA_AHUB_CIF_TX_CTRL_STRIDE = 0x20, + TEGRA_AHUB_CIF_TX_CTRL_COUNT = 4, + /* Uses field from TEGRA_AUDIOCIF_CTRL_* */ + + TEGRA_AHUB_CIF_RX_CTRL = 0x18, + TEGRA_AHUB_CIF_RX_CTRL_STRIDE = 0x20, + TEGRA_AHUB_CIF_RX_CTRL_COUNT = 4, + /* Uses field from TEGRA_AUDIOCIF_CTRL_* */ + + TEGRA_AHUB_CONFIG_LINK_CTRL = 0x80, + TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT = 28, + TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US = 0xf, + TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK = + TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US << + TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT, + TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT = 16, + TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US = 0xfff, + TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK = + TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US << + TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT, + TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT = 4, + TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US = 0xfff, + TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK = + TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US << + TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT, + TEGRA_AHUB_CONFIG_LINK_CTRL_CG_EN = 1 << 2, + TEGRA_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR = 1 << 1, + TEGRA_AHUB_CONFIG_LINK_CTRL_SOFT_RESET = 1 << 0, + + TEGRA_AHUB_MISC_CTRL = 0x84, + TEGRA_AHUB_MISC_CTRL_AUDIO_ACTIVE = 1 << 31, + TEGRA_AHUB_MISC_CTRL_AUDIO_CG_EN = 1 << 8, + TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT = 0, + TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK = + 0x1f << TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT, + + TEGRA_AHUB_APBDMA_LIVE_STATUS = 0x88, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL = 1 << 31, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL = 1 << 30, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL = 1 << 29, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL = 1 << 28, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL = 1 << 27, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL = 1 << 26, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL = 1 << 25, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL = 1 << 24, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY = 1 << 23, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY = 1 << 22, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY = 1 << 21, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY = 1 << 20, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY = 1 << 19, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY = 1 << 18, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY = 1 << 17, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY = 1 << 16, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL = 1 << 15, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL = 1 << 14, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL = 1 << 13, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL = 1 << 12, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL = 1 << 11, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL = 1 << 10, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL = 1 << 9, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL = 1 << 8, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY = 1 << 7, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY = 1 << 6, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY = 1 << 5, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY = 1 << 4, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY = 1 << 3, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY = 1 << 2, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY = 1 << 1, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY = 1 << 0, + + TEGRA_AHUB_I2S_LIVE_STATUS = 0x8c, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL = 1 << 29, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL = 1 << 28, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL = 1 << 27, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL = 1 << 26, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL = 1 << 25, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL = 1 << 24, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL = 1 << 23, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL = 1 << 22, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL = 1 << 21, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL = 1 << 20, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED = 1 << 19, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED = 1 << 18, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED = 1 << 17, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED = 1 << 16, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED = 1 << 15, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED = 1 << 14, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED = 1 << 13, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED = 1 << 12, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED = 1 << 11, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED = 1 << 10, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY = 1 << 9, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY = 1 << 8, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY = 1 << 7, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY = 1 << 6, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY = 1 << 5, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY = 1 << 4, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY = 1 << 3, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY = 1 << 2, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY = 1 << 1, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY = 1 << 0, + + TEGRA_AHUB_DAM_LIVE_STATUS = 0x90, + TEGRA_AHUB_DAM_LIVE_STATUS_STRIDE = 0x8, + TEGRA_AHUB_DAM_LIVE_STATUS_COUNT = 3, + TEGRA_AHUB_DAM_LIVE_STATUS_TX_ENABLED = 1 << 26, + TEGRA_AHUB_DAM_LIVE_STATUS_RX1_ENABLED = 1 << 25, + TEGRA_AHUB_DAM_LIVE_STATUS_RX0_ENABLED = 1 << 24, + TEGRA_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL = 1 << 15, + TEGRA_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL = 1 << 9, + TEGRA_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL = 1 << 8, + TEGRA_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY = 1 << 7, + TEGRA_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY = 1 << 1, + TEGRA_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY = 1 << 0, + + TEGRA_AHUB_SPDIF_LIVE_STATUS = 0xa8, + TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED = 1 << 11, + TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED = 1 << 10, + TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED = 1 << 9, + TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED = 1 << 8, + TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL = 1 << 7, + TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL = 1 << 6, + TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL = 1 << 5, + TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL = 1 << 4, + TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY = 1 << 3, + TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY = 1 << 2, + TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY = 1 << 1, + TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY = 1 << 0, + + TEGRA_AHUB_I2S_INT_MASK = 0xb0, + TEGRA_AHUB_DAM_INT_MASK = 0xb4, + TEGRA_AHUB_SPDIF_INT_MASK = 0xbc, + TEGRA_AHUB_APBIF_INT_MASK = 0xc0, + TEGRA_AHUB_I2S_INT_STATUS = 0xc8, + TEGRA_AHUB_DAM_INT_STATUS = 0xcc, + TEGRA_AHUB_SPDIF_INT_STATUS = 0xd4, + TEGRA_AHUB_APBIF_INT_STATUS = 0xd8, + TEGRA_AHUB_I2S_INT_SOURCE = 0xe0, + TEGRA_AHUB_DAM_INT_SOURCE = 0xe4, + TEGRA_AHUB_SPDIF_INT_SOURCE = 0xec, + TEGRA_AHUB_APBIF_INT_SOURCE = 0xf0, + TEGRA_AHUB_I2S_INT_SET = 0xf8, + TEGRA_AHUB_DAM_INT_SET = 0xfc, + TEGRA_AHUB_SPDIF_INT_SET = 0x100, + TEGRA_AHUB_APBIF_INT_SET = 0x104, + + TEGRA_AHUB_AUDIO_RX = 0x0, + TEGRA_AHUB_AUDIO_RX_STRIDE = 0x4, + TEGRA_AHUB_AUDIO_RX_COUNT = 17, +}; + +#endif /* _TEGRA_I2C_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_i2c.h new file mode 100644 index 000000000..e57b9ef9c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_i2c.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * NVIDIA Tegra I2C controller + * + * Copyright 2010-2011 NVIDIA Corporation + */ + +#ifndef _TEGRA_I2C_H_ +#define _TEGRA_I2C_H_ + +#include + +struct udevice; + +enum { + I2C_TIMEOUT_USEC = 10000, /* Wait time for completion */ + I2C_FIFO_DEPTH = 8, /* I2C fifo depth */ +}; + +enum i2c_transaction_flags { + I2C_IS_WRITE = 0x1, /* for I2C write operation */ + I2C_IS_10_BIT_ADDRESS = 0x2, /* for 10-bit I2C slave address */ + I2C_USE_REPEATED_START = 0x4, /* for repeat start */ + I2C_NO_ACK = 0x8, /* for slave that won't generate ACK */ + I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */ + I2C_NO_STOP = 0x20, +}; + +/* Contians the I2C transaction details */ +struct i2c_trans_info { + /* flags to indicate the transaction details */ + enum i2c_transaction_flags flags; + u32 address; /* I2C slave device address */ + u32 num_bytes; /* number of bytes to be transferred */ + /* + * Send/receive buffer. For the I2C send operation this buffer should + * be filled with the data to be sent to the slave device. For the I2C + * receive operation this buffer is filled with the data received from + * the slave device. + */ + u8 *buf; + int is_10bit_address; +}; + +struct i2c_control { + u32 tx_fifo; + u32 rx_fifo; + u32 packet_status; + u32 fifo_control; + u32 fifo_status; + u32 int_mask; + u32 int_status; +}; + +struct dvc_ctlr { + u32 ctrl1; /* 00: DVC_CTRL_REG1 */ + u32 ctrl2; /* 04: DVC_CTRL_REG2 */ + u32 ctrl3; /* 08: DVC_CTRL_REG3 */ + u32 status; /* 0C: DVC_STATUS_REG */ + u32 ctrl; /* 10: DVC_I2C_CTRL_REG */ + u32 addr_data; /* 14: DVC_I2C_ADDR_DATA_REG */ + u32 reserved_0[2]; /* 18: */ + u32 req; /* 20: DVC_REQ_REGISTER */ + u32 addr_data3; /* 24: DVC_I2C_ADDR_DATA_REG_3 */ + u32 reserved_1[6]; /* 28: */ + u32 cnfg; /* 40: DVC_I2C_CNFG */ + u32 cmd_addr0; /* 44: DVC_I2C_CMD_ADDR0 */ + u32 cmd_addr1; /* 48: DVC_I2C_CMD_ADDR1 */ + u32 cmd_data1; /* 4C: DVC_I2C_CMD_DATA1 */ + u32 cmd_data2; /* 50: DVC_I2C_CMD_DATA2 */ + u32 reserved_2[2]; /* 54: */ + u32 i2c_status; /* 5C: DVC_I2C_STATUS */ + struct i2c_control control; /* 60 ~ 78 */ +}; + +struct i2c_ctlr { + u32 cnfg; /* 00: I2C_I2C_CNFG */ + u32 cmd_addr0; /* 04: I2C_I2C_CMD_ADDR0 */ + u32 cmd_addr1; /* 08: I2C_I2C_CMD_DATA1 */ + u32 cmd_data1; /* 0C: I2C_I2C_CMD_DATA2 */ + u32 cmd_data2; /* 10: DVC_I2C_CMD_DATA2 */ + u32 reserved_0[2]; /* 14: */ + u32 status; /* 1C: I2C_I2C_STATUS */ + u32 sl_cnfg; /* 20: I2C_I2C_SL_CNFG */ + u32 sl_rcvd; /* 24: I2C_I2C_SL_RCVD */ + u32 sl_status; /* 28: I2C_I2C_SL_STATUS */ + u32 sl_addr1; /* 2C: I2C_I2C_SL_ADDR1 */ + u32 sl_addr2; /* 30: I2C_I2C_SL_ADDR2 */ + u32 reserved_1[2]; /* 34: */ + u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */ + u32 reserved_2[4]; /* 40: */ + struct i2c_control control; /* 50 ~ 68 */ + u32 clk_div; /* 6C: I2C_I2C_CLOCK_DIVISOR */ +}; + +/* bit fields definitions for IO Packet Header 1 format */ +#define PKT_HDR1_PROTOCOL_SHIFT 4 +#define PKT_HDR1_PROTOCOL_MASK (0xf << PKT_HDR1_PROTOCOL_SHIFT) +#define PKT_HDR1_CTLR_ID_SHIFT 12 +#define PKT_HDR1_CTLR_ID_MASK (0xf << PKT_HDR1_CTLR_ID_SHIFT) +#define PKT_HDR1_PKT_ID_SHIFT 16 +#define PKT_HDR1_PKT_ID_MASK (0xff << PKT_HDR1_PKT_ID_SHIFT) +#define PROTOCOL_TYPE_I2C 1 + +/* bit fields definitions for IO Packet Header 2 format */ +#define PKT_HDR2_PAYLOAD_SIZE_SHIFT 0 +#define PKT_HDR2_PAYLOAD_SIZE_MASK (0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT) + +/* bit fields definitions for IO Packet Header 3 format */ +#define PKT_HDR3_READ_MODE_SHIFT 19 +#define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT) +#define PKT_HDR3_REPEAT_START_SHIFT 16 +#define PKT_HDR3_REPEAT_START_MASK (1 << PKT_HDR3_REPEAT_START_SHIFT) +#define PKT_HDR3_SLAVE_ADDR_SHIFT 0 +#define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT) + +#define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT 26 +#define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK \ + (1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT) + +/* I2C_CNFG */ +#define I2C_CNFG_NEW_MASTER_FSM_SHIFT 11 +#define I2C_CNFG_NEW_MASTER_FSM_MASK (1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT) +#define I2C_CNFG_PACKET_MODE_SHIFT 10 +#define I2C_CNFG_PACKET_MODE_MASK (1 << I2C_CNFG_PACKET_MODE_SHIFT) + +/* I2C_SL_CNFG */ +#define I2C_SL_CNFG_NEWSL_SHIFT 2 +#define I2C_SL_CNFG_NEWSL_MASK (1 << I2C_SL_CNFG_NEWSL_SHIFT) + +/* I2C_FIFO_STATUS */ +#define TX_FIFO_FULL_CNT_SHIFT 0 +#define TX_FIFO_FULL_CNT_MASK (0xf << TX_FIFO_FULL_CNT_SHIFT) +#define TX_FIFO_EMPTY_CNT_SHIFT 4 +#define TX_FIFO_EMPTY_CNT_MASK (0xf << TX_FIFO_EMPTY_CNT_SHIFT) + +/* I2C_INTERRUPT_STATUS */ +#define I2C_INT_XFER_COMPLETE_SHIFT 7 +#define I2C_INT_XFER_COMPLETE_MASK (1 << I2C_INT_XFER_COMPLETE_SHIFT) +#define I2C_INT_NO_ACK_SHIFT 3 +#define I2C_INT_NO_ACK_MASK (1 << I2C_INT_NO_ACK_SHIFT) +#define I2C_INT_ARBITRATION_LOST_SHIFT 2 +#define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT) + +/* I2C_CLK_DIVISOR_REGISTER */ +#define CLK_DIV_STD_FAST_MODE 0x19 +#define CLK_DIV_HS_MODE 1 +#define CLK_MULT_STD_FAST_MODE 8 + +/** + * Returns the bus number of the DVC controller + * + * @return number of bus, or -1 if there is no DVC active + */ +int tegra_i2c_get_dvc_bus(struct udevice **busp); + +#endif /* _TEGRA_I2C_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_i2s.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_i2s.h new file mode 100644 index 000000000..9319383f7 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_i2s.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * tegra_i2s.h - Definitions for Tegra124 I2S driver. + * Note, some structures (ex, CIF) are different in Tegra114. + * + * NVIDIA Tegra I2S controller + * Modified from dc tegra_regs.h + * + * Copyright 2018 Google LLC + * + * Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA_I2S_H_ +#define _TEGRA_I2S_H_ + +struct i2s_ctlr { + u32 ctrl; /* I2S_CTRL_0, 0x00 */ + u32 timing; /* I2S_TIMING_0, 0x04 */ + u32 offset; /* I2S_OFFSET_0, 0x08 */ + u32 ch_ctrl; /* I2S_CH_CTRL_0, 0x0C */ + u32 slot_ctrl; /* I2S_SLOT_CTRL_0, 0x10 */ + u32 cif_tx_ctrl; /* I2S_CIF_TX_CTRL_0, 0x14 */ + u32 cif_rx_ctrl; /* I2S_CIF_RX_CTRL_0, 0x18 */ + u32 flowctl; /* I2S_FLOWCTL_0, 0x1C */ + u32 tx_step; /* I2S_TX_STEP_0, 0x20 */ + u32 flow_status; /* I2S_FLOW_STATUS_0, 0x24 */ + u32 flow_total; /* I2S_FLOW_TOTAL_0, 0x28 */ + u32 flow_over; /* I2S_FLOW_OVER_0, 0x2C */ + u32 flow_under; /* I2S_FLOW_UNDER_0, 0x30 */ + u32 reserved[12]; /* RESERVED, 0x34 - 0x60 */ + u32 slot_ctrl2; /* I2S_SLOT_CTRL2_0, 0x64*/ +}; + +enum { + I2S_CTRL_XFER_EN_TX = 1 << 31, + I2S_CTRL_XFER_EN_RX = 1 << 30, + I2S_CTRL_CG_EN = 1 << 29, + I2S_CTRL_SOFT_RESET = 1 << 28, + I2S_CTRL_TX_FLOWCTL_EN = 1 << 27, + + I2S_CTRL_OBS_SEL_SHIFT = 24, + I2S_CTRL_OBS_SEL_MASK = 7 << I2S_CTRL_OBS_SEL_SHIFT, + + I2S_FRAME_FORMAT_LRCK = 0, + I2S_FRAME_FORMAT_FSYNC = 1, + + I2S_CTRL_FRAME_FORMAT_SHIFT = 12, + I2S_CTRL_FRAME_FORMAT_MASK = 7 << I2S_CTRL_FRAME_FORMAT_SHIFT, + I2S_CTRL_FRAME_FORMAT_LRCK = I2S_FRAME_FORMAT_LRCK << + I2S_CTRL_FRAME_FORMAT_SHIFT, + I2S_CTRL_FRAME_FORMAT_FSYNC = I2S_FRAME_FORMAT_FSYNC << + I2S_CTRL_FRAME_FORMAT_SHIFT, + + I2S_CTRL_MASTER_ENABLE = 1 << 10, + + I2S_LRCK_LEFT_LOW = 0, + I2S_LRCK_RIGHT_LOW = 1, + + I2S_CTRL_LRCK_SHIFT = 9, + I2S_CTRL_LRCK_MASK = 1 << I2S_CTRL_LRCK_SHIFT, + I2S_CTRL_LRCK_L_LOW = I2S_LRCK_LEFT_LOW << I2S_CTRL_LRCK_SHIFT, + I2S_CTRL_LRCK_R_LOW = I2S_LRCK_RIGHT_LOW << I2S_CTRL_LRCK_SHIFT, + + I2S_CTRL_LPBK_ENABLE = 1 << 8, + + I2S_BIT_CODE_LINEAR = 0, + I2S_BIT_CODE_ULAW = 1, + I2S_BIT_CODE_ALAW = 2, + + I2S_CTRL_BIT_CODE_SHIFT = 4, + I2S_CTRL_BIT_CODE_MASK = 3 << I2S_CTRL_BIT_CODE_SHIFT, + I2S_CTRL_BIT_CODE_LINEAR = I2S_BIT_CODE_LINEAR << + I2S_CTRL_BIT_CODE_SHIFT, + I2S_CTRL_BIT_CODE_ULAW = I2S_BIT_CODE_ULAW << I2S_CTRL_BIT_CODE_SHIFT, + I2S_CTRL_BIT_CODE_ALAW = I2S_BIT_CODE_ALAW << I2S_CTRL_BIT_CODE_SHIFT, + + I2S_BITS_8 = 1, + I2S_BITS_12 = 2, + I2S_BITS_16 = 3, + I2S_BITS_20 = 4, + I2S_BITS_24 = 5, + I2S_BITS_28 = 6, + I2S_BITS_32 = 7, + + /* Sample container size; see {RX,TX}_MASK field in CH_CTRL below */ + I2S_CTRL_BIT_SIZE_SHIFT = 0, + I2S_CTRL_BIT_SIZE_MASK = 7 << I2S_CTRL_BIT_SIZE_SHIFT, + I2S_CTRL_BIT_SIZE_8 = I2S_BITS_8 << I2S_CTRL_BIT_SIZE_SHIFT, + I2S_CTRL_BIT_SIZE_12 = I2S_BITS_12 << I2S_CTRL_BIT_SIZE_SHIFT, + I2S_CTRL_BIT_SIZE_16 = I2S_BITS_16 << I2S_CTRL_BIT_SIZE_SHIFT, + I2S_CTRL_BIT_SIZE_20 = I2S_BITS_20 << I2S_CTRL_BIT_SIZE_SHIFT, + I2S_CTRL_BIT_SIZE_24 = I2S_BITS_24 << I2S_CTRL_BIT_SIZE_SHIFT, + I2S_CTRL_BIT_SIZE_28 = I2S_BITS_28 << I2S_CTRL_BIT_SIZE_SHIFT, + I2S_CTRL_BIT_SIZE_32 = I2S_BITS_32 << I2S_CTRL_BIT_SIZE_SHIFT, + + I2S_TIMING_NON_SYM_ENABLE = 1 << 12, + I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT = 0, + I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US = 0x7ff, + I2S_TIMING_CHANNEL_BIT_COUNT_MASK = + I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << + I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT, + + I2S_OFFSET_RX_DATA_OFFSET_SHIFT = 16, + I2S_OFFSET_RX_DATA_OFFSET_MASK_US = 0x7ff, + I2S_OFFSET_RX_DATA_OFFSET_MASK = I2S_OFFSET_RX_DATA_OFFSET_MASK_US << + I2S_OFFSET_RX_DATA_OFFSET_SHIFT, + I2S_OFFSET_TX_DATA_OFFSET_SHIFT = 0, + I2S_OFFSET_TX_DATA_OFFSET_MASK_US = 0x7ff, + I2S_OFFSET_TX_DATA_OFFSET_MASK = I2S_OFFSET_TX_DATA_OFFSET_MASK_US << + I2S_OFFSET_TX_DATA_OFFSET_SHIFT, + + /* FSYNC width - 1 in bit clocks */ + I2S_CH_CTRL_FSYNC_WIDTH_SHIFT = 24, + I2S_CH_CTRL_FSYNC_WIDTH_MASK_US = 0xff, + I2S_CH_CTRL_FSYNC_WIDTH_MASK = I2S_CH_CTRL_FSYNC_WIDTH_MASK_US << + I2S_CH_CTRL_FSYNC_WIDTH_SHIFT, + + I2S_HIGHZ_NO = 0, + I2S_HIGHZ_YES = 1, + I2S_HIGHZ_ON_HALF_BIT_CLK = 2, + + I2S_CH_CTRL_HIGHZ_CTRL_SHIFT = 12, + I2S_CH_CTRL_HIGHZ_CTRL_MASK = 3 << I2S_CH_CTRL_HIGHZ_CTRL_SHIFT, + I2S_CH_CTRL_HIGHZ_CTRL_NO = I2S_HIGHZ_NO << + I2S_CH_CTRL_HIGHZ_CTRL_SHIFT, + I2S_CH_CTRL_HIGHZ_CTRL_YES = I2S_HIGHZ_YES << + I2S_CH_CTRL_HIGHZ_CTRL_SHIFT, + I2S_CH_CTRL_HIGHZ_CTRL_ON_HALF_BIT_CLK = I2S_HIGHZ_ON_HALF_BIT_CLK << + I2S_CH_CTRL_HIGHZ_CTRL_SHIFT, + + I2S_MSB_FIRST = 0, + I2S_LSB_FIRST = 1, + + I2S_CH_CTRL_RX_BIT_ORDER_SHIFT = 10, + I2S_CH_CTRL_RX_BIT_ORDER_MASK = 1 << I2S_CH_CTRL_RX_BIT_ORDER_SHIFT, + I2S_CH_CTRL_RX_BIT_ORDER_MSB_FIRST = I2S_MSB_FIRST << + I2S_CH_CTRL_RX_BIT_ORDER_SHIFT, + I2S_CH_CTRL_RX_BIT_ORDER_LSB_FIRST = I2S_LSB_FIRST << + I2S_CH_CTRL_RX_BIT_ORDER_SHIFT, + I2S_CH_CTRL_TX_BIT_ORDER_SHIFT = 9, + I2S_CH_CTRL_TX_BIT_ORDER_MASK = 1 << I2S_CH_CTRL_TX_BIT_ORDER_SHIFT, + I2S_CH_CTRL_TX_BIT_ORDER_MSB_FIRST = I2S_MSB_FIRST << + I2S_CH_CTRL_TX_BIT_ORDER_SHIFT, + I2S_CH_CTRL_TX_BIT_ORDER_LSB_FIRST = I2S_LSB_FIRST << + I2S_CH_CTRL_TX_BIT_ORDER_SHIFT, + + I2S_POS_EDGE = 0, + I2S_NEG_EDGE = 1, + + I2S_CH_CTRL_EGDE_CTRL_SHIFT = 8, + I2S_CH_CTRL_EGDE_CTRL_MASK = 1 << I2S_CH_CTRL_EGDE_CTRL_SHIFT, + I2S_CH_CTRL_EGDE_CTRL_POS_EDGE = I2S_POS_EDGE << + I2S_CH_CTRL_EGDE_CTRL_SHIFT, + I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE = I2S_NEG_EDGE << + I2S_CH_CTRL_EGDE_CTRL_SHIFT, + + /* Sample size is # bits from BIT_SIZE minus this field */ + I2S_CH_CTRL_RX_MASK_BITS_SHIFT = 4, + I2S_CH_CTRL_RX_MASK_BITS_MASK_US = 7, + I2S_CH_CTRL_RX_MASK_BITS_MASK = I2S_CH_CTRL_RX_MASK_BITS_MASK_US << + I2S_CH_CTRL_RX_MASK_BITS_SHIFT, + + I2S_CH_CTRL_TX_MASK_BITS_SHIFT = 0, + I2S_CH_CTRL_TX_MASK_BITS_MASK_US = 7, + I2S_CH_CTRL_TX_MASK_BITS_MASK = I2S_CH_CTRL_TX_MASK_BITS_MASK_US << + I2S_CH_CTRL_TX_MASK_BITS_SHIFT, + + /* Number of slots in frame, minus 1 */ + I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT = 16, + I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US = 7, + I2S_SLOT_CTRL_TOTAL_SLOTS_MASK = I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US << + I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT, + + /* TDM mode slot enable bitmask */ + I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT = 8, + I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK = + 0xff << I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT, + + I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT = 0, + I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK = 0xff << + I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT, + + I2S_FILTER_LINEAR = 0, + I2S_FILTER_QUAD = 1, + + I2S_FLOWCTL_FILTER_SHIFT = 31, + I2S_FLOWCTL_FILTER_MASK = 1 << I2S_FLOWCTL_FILTER_SHIFT, + I2S_FLOWCTL_FILTER_LINEAR = I2S_FILTER_LINEAR << + I2S_FLOWCTL_FILTER_SHIFT, + I2S_FLOWCTL_FILTER_QUAD = I2S_FILTER_QUAD << I2S_FLOWCTL_FILTER_SHIFT, + + I2S_TX_STEP_SHIFT = 0, + I2S_TX_STEP_MASK_US = 0xffff, + I2S_TX_STEP_MASK = I2S_TX_STEP_MASK_US << I2S_TX_STEP_SHIFT, + + I2S_FLOW_STATUS_UNDERFLOW = 1 << 31, + I2S_FLOW_STATUS_OVERFLOW = 1 << 30, + I2S_FLOW_STATUS_MONITOR_INT_EN = 1 << 4, + I2S_FLOW_STATUS_COUNTER_CLR = 1 << 3, + I2S_FLOW_STATUS_MONITOR_CLR = 1 << 2, + I2S_FLOW_STATUS_COUNTER_EN = 1 << 1, + I2S_FLOW_STATUS_MONITOR_EN = 1 << 0, +}; + +#endif /* _TEGRA_I2C_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_mmc.h new file mode 100644 index 000000000..d6a55764b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 SAMSUNG Electronics + * Minkyu Kang + * Portions Copyright (C) 2011-2012,2019 NVIDIA Corporation + */ + +#ifndef __TEGRA_MMC_H_ +#define __TEGRA_MMC_H_ + +#include +#include +#include +#include + +/* for mmc_config definition */ +#include + +#ifndef __ASSEMBLY__ +struct tegra_mmc { + unsigned int sysad; /* _SYSTEM_ADDRESS_0 */ + unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */ + unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */ + unsigned int argument; /* _ARGUMENT_0 */ + unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */ + unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */ + unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */ + unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */ + unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */ + unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */ + unsigned int bdata; /* _BUFFER_DATA_PORT_0 */ + unsigned int prnsts; /* _PRESENT_STATE_0 */ + unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */ + unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */ + unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */ + unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */ + unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */ + unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */ + unsigned char swrst; /* _SW_RESET_ 31:24 */ + unsigned int norintsts; /* _INTERRUPT_STATUS_0 */ + unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */ + unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */ + unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */ + unsigned char res1[2]; /* _RESERVED 31:16 */ + unsigned int capareg; /* _CAPABILITIES_0 */ + unsigned char res2[4]; /* RESERVED, offset 44h-47h */ + unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */ + unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */ + unsigned short setacmd12err; /* offset 50h */ + unsigned short setinterr; /* offset 52h */ + unsigned char admaerr; /* offset 54h */ + unsigned char res4[3]; /* RESERVED, offset 55h-57h */ + unsigned long admaaddr; /* offset 58h-5Fh */ + unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */ + unsigned short slotintstatus; /* offset FCh */ + unsigned short hcver; /* HOST Version */ + unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */ + unsigned int venspictl; /* _VENDOR_SPI_CNTRL_0, 104h */ + unsigned int venspiintsts; /* _VENDOR_SPI_INT_STATUS_0, 108h */ + unsigned int venceatactl; /* _VENDOR_CEATA_CNTRL_0, 10Ch */ + unsigned int venbootctl; /* _VENDOR_BOOT_CNTRL_0, 110h */ + unsigned int venbootacktout; /* _VENDOR_BOOT_ACK_TIMEOUT, 114h */ + unsigned int venbootdattout; /* _VENDOR_BOOT_DAT_TIMEOUT, 118h */ + unsigned int vendebouncecnt; /* _VENDOR_DEBOUNCE_COUNT_0, 11Ch */ + unsigned int venmiscctl; /* _VENDOR_MISC_CNTRL_0, 120h */ + unsigned int res6[47]; /* 0x124 ~ 0x1DC */ + unsigned int sdmemcmppadctl; /* _SDMEMCOMPPADCTRL_0, 1E0h */ + unsigned int autocalcfg; /* _AUTO_CAL_CONFIG_0, 1E4h */ + unsigned int autocalintval; /* _AUTO_CAL_INTERVAL_0, 1E8h */ + unsigned int autocalsts; /* _AUTO_CAL_STATUS_0, 1ECh */ +}; + +#define TEGRA_MMC_PWRCTL_SD_BUS_POWER (1 << 0) +#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8 (5 << 1) +#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0 (6 << 1) +#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3 (7 << 1) + +#define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3) +#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3) +#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3) +#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3) + +#define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0) +#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1) +#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4) +#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4) +#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5) + +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0) +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0) +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0) +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0) +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0) + +#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3) +#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4) +#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5) + +#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0) +#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1) + +#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0) +#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1) +#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2) + +#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8 +#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8) + +#define TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK (1 << 17) + +#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0) +#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1) +#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2) + +#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0) +#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1) +#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3) +#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15) +#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16) + +#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0) +#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1) +#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3) +#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4) +#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5) + +#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1) + +/* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */ +#define MEMCOMP_PADCTRL_VREF 7 +#define AUTO_CAL_ENABLE (1 << 29) +#define AUTO_CAL_ACTIVE (1 << 31) +#define AUTO_CAL_START (1 << 31) +#if defined(CONFIG_TEGRA210) +#define AUTO_CAL_PD_OFFSET (0x7D << 8) +#define AUTO_CAL_PU_OFFSET (0 << 0) +#define IO_TRIM_BYPASS_MASK (1 << 2) +#define TRIM_VAL_SHIFT 24 +#define TRIM_VAL_MASK (0x1F << TRIM_VAL_SHIFT) +#define TAP_VAL_SHIFT 16 +#define TAP_VAL_MASK (0xFF << TAP_VAL_SHIFT) +#else +#define AUTO_CAL_PD_OFFSET (0x70 << 8) +#define AUTO_CAL_PU_OFFSET (0x62 << 0) +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __TEGRA_MMC_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/timer.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/timer.h new file mode 100644 index 000000000..1c4decacd --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/timer.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + */ + +/* Tegra20 timer functions */ + +#ifndef _TEGRA_TIMER_H +#define _TEGRA_TIMER_H + +/* returns the current monotonic timer value in microseconds */ +unsigned long timer_get_us(void); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/uart.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/uart.h new file mode 100644 index 000000000..24f0bdd51 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/uart.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + */ + +#ifndef _UART_H_ +#define _UART_H_ + +/* UART registers */ +struct uart_ctlr { + uint uart_thr_dlab_0; /* UART_THR_DLAB_0_0, offset 00 */ + uint uart_ier_dlab_0; /* UART_IER_DLAB_0_0, offset 04 */ + uint uart_iir_fcr; /* UART_IIR_FCR_0, offset 08 */ + uint uart_lcr; /* UART_LCR_0, offset 0C */ + uint uart_mcr; /* UART_MCR_0, offset 10 */ + uint uart_lsr; /* UART_LSR_0, offset 14 */ + uint uart_msr; /* UART_MSR_0, offset 18 */ + uint uart_spr; /* UART_SPR_0, offset 1C */ + uint uart_irda_csr; /* UART_IRDA_CSR_0, offset 20 */ + uint uart_reserved[6]; /* Reserved, unused, offset 24-38*/ + uint uart_asr; /* UART_ASR_0, offset 3C */ +}; + +#define NVRM_PLLP_FIXED_FREQ_KHZ 216000 +#define NV_DEFAULT_DEBUG_BAUD 115200 + +#define UART_FCR_TRIGGER_3 0x30 /* Mask for trigger set at 3 */ + +#endif /* UART_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/usb.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/usb.h new file mode 100644 index 000000000..6e6ea1443 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/usb.h @@ -0,0 +1,360 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2013 NVIDIA Corporation + */ + +#ifndef _TEGRA_USB_H_ +#define _TEGRA_USB_H_ + +/* USB Controller (USBx_CONTROLLER_) regs */ +struct usb_ctlr { + /* 0x000 */ + uint id; + uint reserved0; + uint host; + uint device; + + /* 0x010 */ + uint txbuf; + uint rxbuf; + uint reserved1[2]; + + /* 0x020 */ + uint reserved2[56]; + + /* 0x100 */ + u16 cap_length; + u16 hci_version; + uint hcs_params; + uint hcc_params; + uint reserved3[5]; + + /* 0x120 */ + uint dci_version; + uint dcc_params; + uint reserved4[2]; + +#ifdef CONFIG_TEGRA20 + /* 0x130 */ + uint reserved4_2[4]; + + /* 0x140 */ + uint usb_cmd; + uint usb_sts; + uint usb_intr; + uint frindex; + + /* 0x150 */ + uint reserved5; + uint periodic_list_base; + uint async_list_addr; + uint async_tt_sts; + + /* 0x160 */ + uint burst_size; + uint tx_fill_tuning; + uint reserved6; /* is this port_sc1 on some controllers? */ + uint icusb_ctrl; + + /* 0x170 */ + uint ulpi_viewport; + uint reserved7; + uint endpt_nak; + uint endpt_nak_enable; + + /* 0x180 */ + uint reserved; + uint port_sc1; + uint reserved8[6]; + + /* 0x1a0 */ + uint reserved9; + uint otgsc; + uint usb_mode; + uint endpt_setup_stat; + + /* 0x1b0 */ + uint reserved10[20]; + + /* 0x200 */ + uint reserved11[0x80]; +#else + /* 0x130 */ + uint usb_cmd; + uint usb_sts; + uint usb_intr; + uint frindex; + + /* 0x140 */ + uint reserved5; + uint periodic_list_base; + uint async_list_addr; + uint reserved5_1; + + /* 0x150 */ + uint burst_size; + uint tx_fill_tuning; + uint reserved6; + uint icusb_ctrl; + + /* 0x160 */ + uint ulpi_viewport; + uint reserved7[3]; + + /* 0x170 */ + uint reserved; + uint port_sc1; + uint reserved8[6]; + + /* 0x190 */ + uint reserved9[8]; + + /* 0x1b0 */ + uint reserved10; + uint hostpc1_devlc; + uint reserved10_1[2]; + + /* 0x1c0 */ + uint reserved10_2[4]; + + /* 0x1d0 */ + uint reserved10_3[4]; + + /* 0x1e0 */ + uint reserved10_4[4]; + + /* 0x1f0 */ + uint reserved10_5; + uint otgsc; + uint usb_mode; + uint reserved10_6; + + /* 0x200 */ + uint endpt_nak; + uint endpt_nak_enable; + uint endpt_setup_stat; + uint reserved11_1[0x7D]; +#endif + + /* 0x400 */ + uint susp_ctrl; + uint phy_vbus_sensors; + uint phy_vbus_wakeup_id; + uint phy_alt_vbus_sys; + +#ifdef CONFIG_TEGRA20 + /* 0x410 */ + uint usb1_legacy_ctrl; + uint reserved12[4]; + + /* 0x424 */ + uint ulpi_timing_ctrl_0; + uint ulpi_timing_ctrl_1; + uint reserved13[53]; +#else + + /* 0x410 */ + uint usb1_legacy_ctrl; + uint reserved12[3]; + + /* 0x420 */ + uint reserved13[56]; +#endif + + /* 0x500 */ + uint reserved14[64 * 3]; + + /* 0x800 */ + uint utmip_pll_cfg0; + uint utmip_pll_cfg1; + uint utmip_xcvr_cfg0; + uint utmip_bias_cfg0; + + /* 0x810 */ + uint utmip_hsrx_cfg0; + uint utmip_hsrx_cfg1; + uint utmip_fslsrx_cfg0; + uint utmip_fslsrx_cfg1; + + /* 0x820 */ + uint utmip_tx_cfg0; + uint utmip_misc_cfg0; + uint utmip_misc_cfg1; + uint utmip_debounce_cfg0; + + /* 0x830 */ + uint utmip_bat_chrg_cfg0; + uint utmip_spare_cfg0; + uint utmip_xcvr_cfg1; + uint utmip_bias_cfg1; +}; + +/* USB1_LEGACY_CTRL */ +#define USB1_NO_LEGACY_MODE 1 + +#define VBUS_SENSE_CTL_SHIFT 1 +#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT) +#define VBUS_SENSE_CTL_VBUS_WAKEUP 0 +#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1 +#define VBUS_SENSE_CTL_AB_SESS_VLD 2 +#define VBUS_SENSE_CTL_A_SESS_VLD 3 + +/* USBx_IF_USB_SUSP_CTRL_0 */ +#define UTMIP_PHY_ENB (1 << 12) +#define UTMIP_RESET (1 << 11) +#define USB_PHY_CLK_VALID (1 << 7) +#define USB_SUSP_CLR (1 << 5) + +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) +/* USB2_IF_USB_SUSP_CTRL_0 */ +#define ULPI_PHY_ENB (1 << 13) + +/* USB2_IF_ULPI_TIMING_CTRL_0 */ +#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) +#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) + +/* USB2_IF_ULPI_TIMING_CTRL_1 */ +#define ULPI_DATA_TRIMMER_LOAD (1 << 0) +#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) +#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) +#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) +#define ULPI_DIR_TRIMMER_LOAD (1 << 24) +#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) +#endif + +/* USBx_UTMIP_MISC_CFG0 */ +#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) + +/* USBx_UTMIP_MISC_CFG1 */ +#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) + +/* + * Tegra 3 and later: Moved to Clock and Reset register space, see + * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 + */ +#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6 +#define UTMIP_PLLU_STABLE_COUNT_MASK \ + (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT) +/* + * Tegra 3 and later: Moved to Clock and Reset register space, see + * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 + */ +#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18 +#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \ + (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT) + +/* USBx_UTMIP_PLL_CFG1_0 */ +/* Tegra 3 and later: Moved to Clock and Reset register space */ +#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27 +#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \ + (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT) +#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0 +#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff + +/* USBx_UTMIP_BIAS_CFG0_0 */ +#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24) +#define UTMIP_OTGPD (1 << 11) +#define UTMIP_BIASPD (1 << 10) +#define UTMIP_HSDISCON_LEVEL_SHIFT 2 +#define UTMIP_HSDISCON_LEVEL_MASK \ + (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT) +#define UTMIP_HSSQUELCH_LEVEL_SHIFT 0 +#define UTMIP_HSSQUELCH_LEVEL_MASK \ + (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT) + +/* USBx_UTMIP_BIAS_CFG1_0 */ +#define UTMIP_FORCE_PDTRK_POWERDOWN 1 +#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT 8 +#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK \ + (0x3f << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT) +#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3 +#define UTMIP_BIAS_PDTRK_COUNT_MASK \ + (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT) + +/* USBx_UTMIP_DEBOUNCE_CFG0_0 */ +#define UTMIP_DEBOUNCE_CFG0_SHIFT 0 +#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff + +/* USBx_UTMIP_TX_CFG0_0 */ +#define UTMIP_FS_PREAMBLE_J (1 << 19) + +/* USBx_UTMIP_BAT_CHRG_CFG0_0 */ +#define UTMIP_PD_CHRG 1 + +/* USBx_UTMIP_SPARE_CFG0_0 */ +#define FUSE_SETUP_SEL (1 << 3) + +/* USBx_UTMIP_HSRX_CFG0_0 */ +#define UTMIP_IDLE_WAIT_SHIFT 15 +#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT) +#define UTMIP_ELASTIC_LIMIT_SHIFT 10 +#define UTMIP_ELASTIC_LIMIT_MASK \ + (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT) + +/* USBx_UTMIP_HSRX_CFG1_0 */ +#define UTMIP_HS_SYNC_START_DLY_SHIFT 1 +#define UTMIP_HS_SYNC_START_DLY_MASK \ + (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT) + +/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */ +#define IC_ENB1 (1 << 3) + +#ifdef CONFIG_TEGRA20 +/* PORTSC1, USB1 */ +#define PTS1_SHIFT 31 +#define PTS1_MASK (1 << PTS1_SHIFT) +#define STS1 (1 << 30) + +/* PORTSC, USB2, USB3 */ +#define PTS_SHIFT 30 +#define PTS_MASK (3U << PTS_SHIFT) +#define STS (1 << 29) +#else +/* USB2D_HOSTPC1_DEVLC_0 */ +#define PTS_SHIFT 29 +#define PTS_MASK (0x7U << PTS_SHIFT) +#define STS (1 << 28) +#endif + +#define PTS_UTMI 0 +#define PTS_RESERVED 1 +#define PTS_ULPI 2 +#define PTS_ICUSB_SER 3 +#define PTS_HSIC 4 + +/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */ +#define WKOC (1 << 22) +#define WKDS (1 << 21) +#define WKCN (1 << 20) + +/* USBx_UTMIP_XCVR_CFG0_0 */ +#define UTMIP_FORCE_PD_POWERDOWN (1 << 14) +#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) +#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) +#define UTMIP_XCVR_LSBIAS_SE (1 << 21) +#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25 +#define UTMIP_XCVR_HSSLEW_MSB_MASK \ + (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT) +#define UTMIP_XCVR_SETUP_MSB_SHIFT 22 +#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT) +#define UTMIP_XCVR_SETUP_SHIFT 0 +#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT) + +/* USBx_UTMIP_XCVR_CFG1_0 */ +#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18 +#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \ + (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT) +#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) +#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) +#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) + +/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */ +#define VBUS_VLD_STS (1 << 26) +#define VBUS_B_SESS_VLD_SW_VALUE (1 << 12) +#define VBUS_B_SESS_VLD_SW_EN (1 << 11) + +/* Setup USB on the board */ +int usb_process_devicetree(const void *blob); + +#endif /* _TEGRA_USB_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/warmboot.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/warmboot.h new file mode 100644 index 000000000..3f02073ee --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/warmboot.h @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010, 2011 + * NVIDIA Corporation + */ + +#ifndef _WARM_BOOT_H_ +#define _WARM_BOOT_H_ + +#define STRAP_OPT_A_RAM_CODE_SHIFT 4 +#define STRAP_OPT_A_RAM_CODE_MASK (0xf << STRAP_OPT_A_RAM_CODE_SHIFT) + +/* Defines the supported operating modes */ +enum fuse_operating_mode { + MODE_PRODUCTION = 3, + MODE_UNDEFINED, +}; + +/* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) */ +enum { + HASH_LENGTH = 4 +}; + +/* Defines the storage for a hash value (128 bits) */ +struct hash { + u32 hash[HASH_LENGTH]; +}; + +/* + * Defines the code header information for the boot rom. + * + * The code immediately follows the code header. + * + * Note that the code header needs to be 16 bytes aligned to preserve + * the alignment of relevant data for hash and decryption computations without + * requiring extra copies to temporary memory areas. + */ +struct wb_header { + u32 length_insecure; /* length of the code header */ + u32 reserved[3]; + struct hash hash; /* hash of header+code, starts next field*/ + struct hash random_aes_block; /* a data block to aid security. */ + u32 length_secure; /* length of the code header */ + u32 destination; /* destination address to put the wb code */ + u32 entry_point; /* execution address of the wb code */ + u32 code_length; /* length of the code */ +}; + +/* + * The warm boot code needs direct access to these registers since it runs in + * SRAM and cannot call other U-Boot code. + */ +union osc_ctrl_reg { + struct { + u32 xoe:1; + u32 xobp:1; + u32 reserved0:2; + u32 xofs:6; + u32 reserved1:2; + u32 xods:5; + u32 reserved2:3; + u32 oscfi_spare:8; + u32 pll_ref_div:2; + u32 osc_freq:2; + }; + u32 word; +}; + +union pllx_base_reg { + struct { + u32 divm:5; + u32 reserved0:3; + u32 divn:10; + u32 reserved1:2; + u32 divp:3; + u32 reserved2:4; + u32 lock:1; + u32 reserved3:1; + u32 ref_dis:1; + u32 enable:1; + u32 bypass:1; + }; + u32 word; +}; + +union pllx_misc_reg { + struct { + u32 vcocon:4; + u32 lfcon:4; + u32 cpcon:4; + u32 lock_sel:6; + u32 reserved0:1; + u32 lock_enable:1; + u32 reserved1:1; + u32 dccon:1; + u32 pts:2; + u32 reserved2:6; + u32 out1_div_byp:1; + u32 out1_inv_clk:1; + }; + u32 word; +}; + +/* + * TODO: This register is not documented in the TRM yet. We could move this + * into the EMC and give it a proper interface, but not while it is + * undocumented. + */ +union scratch3_reg { + struct { + u32 pllx_base_divm:5; + u32 pllx_base_divn:10; + u32 pllx_base_divp:3; + u32 pllx_misc_lfcon:4; + u32 pllx_misc_cpcon:4; + }; + u32 word; +}; + + +/** + * Save warmboot memory settings for a later resume + * + * @return 0 if ok, -1 on error + */ +int warmboot_save_sdram_params(void); + +int warmboot_prepare_code(u32 seg_address, u32 seg_length); +int sign_data_block(u8 *source, u32 length, u8 *signature); +void wb_start(void); /* Start of WB assembly code */ +void wb_end(void); /* End of WB assembly code */ + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra/xusb-padctl.h b/roms/u-boot/arch/arm/include/asm/arch-tegra/xusb-padctl.h new file mode 100644 index 000000000..7e14d8109 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra/xusb-padctl.h @@ -0,0 +1,25 @@ +#ifndef _TEGRA_XUSB_PADCTL_H_ +#define _TEGRA_XUSB_PADCTL_H_ + +struct tegra_xusb_phy; + +/** + * tegra_xusb_phy_get() - obtain a reference to a specified padctl PHY + * @type: the type of PHY to obtain + * + * The type of PHY varies between SoC generations. Typically there are XUSB, + * PCIe and SATA PHYs, though not all generations support all of them. The + * value of type can usually be directly parsed from a device tree. + * + * Return: a pointer to the PHY or NULL if no such PHY exists + */ +struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type); + +void tegra_xusb_padctl_init(void); +void tegra_xusb_padctl_exit(void); +int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy); +int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy); +int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy); +int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra114/clock-tables.h b/roms/u-boot/arch/arm/include/asm/arch-tegra114/clock-tables.h new file mode 100644 index 000000000..9b95b339e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra114/clock-tables.h @@ -0,0 +1,392 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + */ + +/* Tegra114 clock PLL tables */ + +#ifndef _TEGRA114_CLOCK_TABLES_H_ +#define _TEGRA114_CLOCK_TABLES_H_ + +/* The PLLs supported by the hardware */ +enum clock_id { + CLOCK_ID_FIRST, + CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, + CLOCK_ID_MEMORY, + CLOCK_ID_PERIPH, + CLOCK_ID_AUDIO, + CLOCK_ID_USB, + CLOCK_ID_DISPLAY, + + /* now the simple ones */ + CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_EPCI, + CLOCK_ID_SFROM32KHZ, + + /* These are the base clocks (inputs to the Tegra SOC) */ + CLOCK_ID_32KHZ, + CLOCK_ID_OSC, + CLOCK_ID_CLK_M, + + CLOCK_ID_COUNT, /* number of PLLs */ + CLOCK_ID_DISPLAY2, /* placeholder */ + CLOCK_ID_NONE = -1, +}; + +/* The clocks supported by the hardware */ +enum periph_id { + PERIPH_ID_FIRST, + + /* Low word: 31:0 (DEVICES_L) */ + PERIPH_ID_CPU = PERIPH_ID_FIRST, + PERIPH_ID_COP, + PERIPH_ID_TRIGSYS, + PERIPH_ID_RESERVED3, + PERIPH_ID_RTC, + PERIPH_ID_TMR, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + + /* 8 */ + PERIPH_ID_GPIO, + PERIPH_ID_SDMMC2, + PERIPH_ID_SPDIF, + PERIPH_ID_I2S1, + PERIPH_ID_I2C1, + PERIPH_ID_NDFLASH, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC4, + + /* 16 */ + PERIPH_ID_RESERVED16, + PERIPH_ID_PWM, + PERIPH_ID_I2S2, + PERIPH_ID_EPP, + PERIPH_ID_VI, + PERIPH_ID_2D, + PERIPH_ID_USBD, + PERIPH_ID_ISP, + + /* 24 */ + PERIPH_ID_3D, + PERIPH_ID_RESERVED24, + PERIPH_ID_DISP2, + PERIPH_ID_DISP1, + PERIPH_ID_HOST1X, + PERIPH_ID_VCP, + PERIPH_ID_I2S0, + PERIPH_ID_CACHE2, + + /* Middle word: 63:32 (DEVICES_H) */ + PERIPH_ID_MEM, + PERIPH_ID_AHBDMA, + PERIPH_ID_APBDMA, + PERIPH_ID_RESERVED35, + PERIPH_ID_KBC, + PERIPH_ID_STAT_MON, + PERIPH_ID_PMC, + PERIPH_ID_FUSE, + + /* 40 */ + PERIPH_ID_KFUSE, + PERIPH_ID_SBC1, + PERIPH_ID_SNOR, + PERIPH_ID_RESERVED43, + PERIPH_ID_SBC2, + PERIPH_ID_RESERVED45, + PERIPH_ID_SBC3, + PERIPH_ID_I2C5, + + /* 48 */ + PERIPH_ID_DSI, + PERIPH_ID_TVO, + PERIPH_ID_MIPI, + PERIPH_ID_HDMI, + PERIPH_ID_CSI, + PERIPH_ID_TVDAC, + PERIPH_ID_I2C2, + PERIPH_ID_UART3, + + /* 56 */ + PERIPH_ID_RESERVED56, + PERIPH_ID_EMC, + PERIPH_ID_USB2, + PERIPH_ID_USB3, + PERIPH_ID_MPE, + PERIPH_ID_VDE, + PERIPH_ID_BSEA, + PERIPH_ID_BSEV, + + /* Upper word 95:64 (DEVICES_U) */ + PERIPH_ID_SPEEDO, + PERIPH_ID_UART4, + PERIPH_ID_UART5, + PERIPH_ID_I2C3, + PERIPH_ID_SBC4, + PERIPH_ID_SDMMC3, + PERIPH_ID_PCIE, + PERIPH_ID_OWR, + + /* 72 */ + PERIPH_ID_AFI, + PERIPH_ID_CORESIGHT, + PERIPH_ID_PCIEXCLK, + PERIPH_ID_AVPUCQ, + PERIPH_ID_RESERVED76, + PERIPH_ID_RESERVED77, + PERIPH_ID_RESERVED78, + PERIPH_ID_DTV, + + /* 80 */ + PERIPH_ID_NANDSPEED, + PERIPH_ID_I2CSLOW, + PERIPH_ID_DSIB, + PERIPH_ID_RESERVED83, + PERIPH_ID_IRAMA, + PERIPH_ID_IRAMB, + PERIPH_ID_IRAMC, + PERIPH_ID_IRAMD, + + /* 88 */ + PERIPH_ID_CRAM2, + PERIPH_ID_RESERVED89, + PERIPH_ID_MDOUBLER, + PERIPH_ID_RESERVED91, + PERIPH_ID_SUSOUT, + PERIPH_ID_RESERVED93, + PERIPH_ID_RESERVED94, + PERIPH_ID_RESERVED95, + + PERIPH_ID_VW_FIRST, + /* V word: 31:0 */ + PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST, + PERIPH_ID_CPULP, + PERIPH_ID_3D2, + PERIPH_ID_MSELECT, + PERIPH_ID_TSENSOR, + PERIPH_ID_I2S3, + PERIPH_ID_I2S4, + PERIPH_ID_I2C4, + + /* 104 */ + PERIPH_ID_SBC5, + PERIPH_ID_SBC6, + PERIPH_ID_AUDIO, + PERIPH_ID_APBIF, + PERIPH_ID_DAM0, + PERIPH_ID_DAM1, + PERIPH_ID_DAM2, + PERIPH_ID_HDA2CODEC2X, + + /* 112 */ + PERIPH_ID_ATOMICS, + PERIPH_ID_EX_RESERVED17, + PERIPH_ID_EX_RESERVED18, + PERIPH_ID_EX_RESERVED19, + PERIPH_ID_EX_RESERVED20, + PERIPH_ID_EX_RESERVED21, + PERIPH_ID_EX_RESERVED22, + PERIPH_ID_ACTMON, + + /* 120 */ + PERIPH_ID_EX_RESERVED24, + PERIPH_ID_EX_RESERVED25, + PERIPH_ID_EX_RESERVED26, + PERIPH_ID_EX_RESERVED27, + PERIPH_ID_SATA, + PERIPH_ID_HDA, + PERIPH_ID_EX_RESERVED30, + PERIPH_ID_EX_RESERVED31, + + /* W word: 31:0 */ + PERIPH_ID_HDA2HDMICODEC, + PERIPH_ID_RESERVED1_SATACOLD, + PERIPH_ID_RESERVED2_PCIERX0, + PERIPH_ID_RESERVED3_PCIERX1, + PERIPH_ID_RESERVED4_PCIERX2, + PERIPH_ID_RESERVED5_PCIERX3, + PERIPH_ID_RESERVED6_PCIERX4, + PERIPH_ID_RESERVED7_PCIERX5, + + /* 136 */ + PERIPH_ID_CEC, + PERIPH_ID_PCIE2_IOBIST, + PERIPH_ID_EMC_IOBIST, + PERIPH_ID_HDMI_IOBIST, + PERIPH_ID_SATA_IOBIST, + PERIPH_ID_MIPI_IOBIST, + PERIPH_ID_EMC1_IOBIST, + PERIPH_ID_XUSB, + + /* 144 */ + PERIPH_ID_CILAB, + PERIPH_ID_CILCD, + PERIPH_ID_CILE, + PERIPH_ID_DSIA_LP, + PERIPH_ID_DSIB_LP, + PERIPH_ID_RESERVED21_ENTROPY, + PERIPH_ID_RESERVED22_W, + PERIPH_ID_RESERVED23_W, + + /* 152 */ + PERIPH_ID_RESERVED24_W, + PERIPH_ID_AMX0, + PERIPH_ID_ADX0, + PERIPH_ID_DVFS, + PERIPH_ID_XUSB_SS, + PERIPH_ID_EMC_DLL, + PERIPH_ID_MC1, + PERIPH_ID_EMC1, + + PERIPH_ID_COUNT, + PERIPH_ID_NONE = -1, +}; + +enum pll_out_id { + PLL_OUT1, + PLL_OUT2, + PLL_OUT3, + PLL_OUT4 +}; + +/* + * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want + * callers to use the PERIPH_ID for all access to peripheral clocks to avoid + * confusion bewteen PERIPH_ID_... and PERIPHC_... + * + * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be + * confusing. + */ +enum periphc_internal_id { + /* 0x00 */ + PERIPHC_I2S1, + PERIPHC_I2S2, + PERIPHC_SPDIF_OUT, + PERIPHC_SPDIF_IN, + PERIPHC_PWM, + PERIPHC_05h, + PERIPHC_SBC2, + PERIPHC_SBC3, + + /* 0x08 */ + PERIPHC_08h, + PERIPHC_I2C1, + PERIPHC_I2C5, + PERIPHC_0bh, + PERIPHC_0ch, + PERIPHC_SBC1, + PERIPHC_DISP1, + PERIPHC_DISP2, + + /* 0x10 */ + PERIPHC_CVE, + PERIPHC_11h, + PERIPHC_VI, + PERIPHC_13h, + PERIPHC_SDMMC1, + PERIPHC_SDMMC2, + PERIPHC_G3D, + PERIPHC_G2D, + + /* 0x18 */ + PERIPHC_NDFLASH, + PERIPHC_SDMMC4, + PERIPHC_VFIR, + PERIPHC_EPP, + PERIPHC_MPE, + PERIPHC_MIPI, + PERIPHC_UART1, + PERIPHC_UART2, + + /* 0x20 */ + PERIPHC_HOST1X, + PERIPHC_21h, + PERIPHC_TVO, + PERIPHC_HDMI, + PERIPHC_24h, + PERIPHC_TVDAC, + PERIPHC_I2C2, + PERIPHC_EMC, + + /* 0x28 */ + PERIPHC_UART3, + PERIPHC_29h, + PERIPHC_VI_SENSOR, + PERIPHC_2bh, + PERIPHC_2ch, + PERIPHC_SBC4, + PERIPHC_I2C3, + PERIPHC_SDMMC3, + + /* 0x30 */ + PERIPHC_UART4, + PERIPHC_UART5, + PERIPHC_VDE, + PERIPHC_OWR, + PERIPHC_NOR, + PERIPHC_CSITE, + PERIPHC_I2S0, + PERIPHC_37h, + + PERIPHC_VW_FIRST, + /* 0x38 */ + PERIPHC_G3D2 = PERIPHC_VW_FIRST, + PERIPHC_MSELECT, + PERIPHC_TSENSOR, + PERIPHC_I2S3, + PERIPHC_I2S4, + PERIPHC_I2C4, + PERIPHC_SBC5, + PERIPHC_SBC6, + + /* 0x40 */ + PERIPHC_AUDIO, + PERIPHC_41h, + PERIPHC_DAM0, + PERIPHC_DAM1, + PERIPHC_DAM2, + PERIPHC_HDA2CODEC2X, + PERIPHC_ACTMON, + PERIPHC_EXTPERIPH1, + + /* 0x48 */ + PERIPHC_EXTPERIPH2, + PERIPHC_EXTPERIPH3, + PERIPHC_NANDSPEED, + PERIPHC_I2CSLOW, + PERIPHC_SYS, + PERIPHC_SPEEDO, + PERIPHC_4eh, + PERIPHC_4fh, + + /* 0x50 */ + PERIPHC_50h, + PERIPHC_51h, + PERIPHC_52h, + PERIPHC_53h, + PERIPHC_SATAOOB, + PERIPHC_SATA, + PERIPHC_HDA, + + PERIPHC_COUNT, + + PERIPHC_NONE = -1, +}; + +/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */ +#define PERIPH_REG(id) \ + (id < PERIPH_ID_VW_FIRST) ? \ + ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5) + +/* Mask value for a clock (within PERIPH_REG(id)) */ +#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) + +/* return 1 if a PLL ID is in range */ +#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) + +/* return 1 if a peripheral ID is in range */ +#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ + (id) < PERIPH_ID_COUNT) + +#endif /* _TEGRA114_CLOCK_TABLES_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra114/clock.h b/roms/u-boot/arch/arm/include/asm/arch-tegra114/clock.h new file mode 100644 index 000000000..84e1da42e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra114/clock.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + */ + +/* Tegra114 clock control functions */ + +#ifndef _TEGRA114_CLOCK_H_ +#define _TEGRA114_CLOCK_H_ + +#include + +/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ +#define OSC_FREQ_SHIFT 28 +#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) + +/* CLK_RST_CONTROLLER_PLLC_MISC_0 */ +#define PLLC_IDDQ (1 << 26) + +#endif /* _TEGRA114_CLOCK_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra114/flow.h b/roms/u-boot/arch/arm/include/asm/arch-tegra114/flow.h new file mode 100644 index 000000000..4f0fc3b7f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra114/flow.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA114_FLOW_H_ +#define _TEGRA114_FLOW_H_ + +struct flow_ctlr { + u32 halt_cpu_events; + u32 halt_cop_events; + u32 cpu_csr; + u32 cop_csr; + u32 xrq_events; + u32 halt_cpu1_events; + u32 cpu1_csr; + u32 halt_cpu2_events; + u32 cpu2_csr; + u32 halt_cpu3_events; + u32 cpu3_csr; + u32 cluster_control; +}; + +#endif /* _TEGRA114_FLOW_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra114/funcmux.h b/roms/u-boot/arch/arm/include/asm/arch-tegra114/funcmux.h new file mode 100644 index 000000000..f3b1bd47e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra114/funcmux.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + */ + +/* Tegra114 high-level function multiplexing */ + +#ifndef _TEGRA114_FUNCMUX_H_ +#define _TEGRA114_FUNCMUX_H_ + +#include + +/* Configs supported by the func mux */ +enum { + FUNCMUX_DEFAULT = 0, /* default config */ + + /* UART configs */ + FUNCMUX_UART4_GMI = 0, +}; +#endif /* _TEGRA114_FUNCMUX_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/roms/u-boot/arch/arm/include/asm/arch-tegra114/gp_padctrl.h new file mode 100644 index 000000000..69b35a141 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra114/gp_padctrl.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA114_GP_PADCTRL_H_ +#define _TEGRA114_GP_PADCTRL_H_ + +#include + +/* APB_MISC_GP and padctrl registers */ +struct apb_misc_gp_ctlr { + u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ + u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ + u32 reserved0[22]; /* 0x08 - 0x5C: */ + u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ + u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ + u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ + u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ + u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ + u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ + u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ + u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ + u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ + u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ + u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ + u32 reserved1; /* 0x8C: */ + u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ + u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ + u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ + u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ + u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ + u32 reserved2[3]; /* 0xA4 - 0xAC: */ + u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ + u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ + u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ + u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ + u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ + u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ + u32 reserved3[9]; /* 0xC8-0xE8: */ + u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ + u32 reserved4[3]; /* 0xF0-0xF8: */ + u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ + u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ + u32 reserved5[3]; /* 0x104-0x10C: */ + u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ + u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ + u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ + u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ + u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ + u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ + u32 reserved6; /* 0x128: */ + u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ + u32 reserved7[2]; /* 0x130 - 0x134: */ + u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ + u32 reserved8[22]; /* 0x13C - 0x190: */ + u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ + u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ + u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ + u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ + u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ + u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ + u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ +}; + +/* SDMMC1/3 settings from section 27.5 of T114 TRM */ +#define SDIOCFG_DRVUP_SLWF 0 +#define SDIOCFG_DRVDN_SLWR 0 +#define SDIOCFG_DRVUP 0x24 +#define SDIOCFG_DRVDN 0x14 + +#endif /* _TEGRA114_GP_PADCTRL_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra114/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-tegra114/gpio.h new file mode 100644 index 000000000..4f084e2de --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra114/gpio.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA114_GPIO_H_ +#define _TEGRA114_GPIO_H_ + +/* + * The Tegra114 GPIO controller has 246 GPIOS in 8 banks of 4 ports, + * each with 8 GPIOs. + */ +#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ +#define TEGRA_GPIO_BANKS 8 /* number of banks */ + +#include +#include + +#endif /* _TEGRA114_GPIO_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra114/mc.h b/roms/u-boot/arch/arm/include/asm/arch-tegra114/mc.h new file mode 100644 index 000000000..3930bab57 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra114/mc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2014 + * NVIDIA Corporation + */ + +#ifndef _TEGRA114_MC_H_ +#define _TEGRA114_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[4]; /* offset 0x00 - 0x0C */ + u32 mc_smmu_config; /* offset 0x10 */ + u32 mc_smmu_tlb_config; /* offset 0x14 */ + u32 mc_smmu_ptc_config; /* offset 0x18 */ + u32 mc_smmu_ptb_asid; /* offset 0x1C */ + u32 mc_smmu_ptb_data; /* offset 0x20 */ + u32 reserved1[3]; /* offset 0x24 - 0x2C */ + u32 mc_smmu_tlb_flush; /* offset 0x30 */ + u32 mc_smmu_ptc_flush; /* offset 0x34 */ + u32 reserved2[6]; /* offset 0x38 - 0x4C */ + u32 mc_emem_cfg; /* offset 0x50 */ + u32 mc_emem_adr_cfg; /* offset 0x54 */ + u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ + u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ + u32 reserved3[12]; /* offset 0x60 - 0x8C */ + u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ + u32 reserved4[338]; /* offset 0x100 - 0x644 */ + u32 mc_video_protect_bom; /* offset 0x648 */ + u32 mc_video_protect_size_mb; /* offset 0x64c */ + u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ +}; + +#endif /* _TEGRA114_MC_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra114/pinmux.h b/roms/u-boot/arch/arm/include/asm/arch-tegra114/pinmux.h new file mode 100644 index 000000000..414b22e20 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra114/pinmux.h @@ -0,0 +1,328 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA114_PINMUX_H_ +#define _TEGRA114_PINMUX_H_ + +enum pmux_pingrp { + PMUX_PINGRP_ULPI_DATA0_PO1, + PMUX_PINGRP_ULPI_DATA1_PO2, + PMUX_PINGRP_ULPI_DATA2_PO3, + PMUX_PINGRP_ULPI_DATA3_PO4, + PMUX_PINGRP_ULPI_DATA4_PO5, + PMUX_PINGRP_ULPI_DATA5_PO6, + PMUX_PINGRP_ULPI_DATA6_PO7, + PMUX_PINGRP_ULPI_DATA7_PO0, + PMUX_PINGRP_ULPI_CLK_PY0, + PMUX_PINGRP_ULPI_DIR_PY1, + PMUX_PINGRP_ULPI_NXT_PY2, + PMUX_PINGRP_ULPI_STP_PY3, + PMUX_PINGRP_DAP3_FS_PP0, + PMUX_PINGRP_DAP3_DIN_PP1, + PMUX_PINGRP_DAP3_DOUT_PP2, + PMUX_PINGRP_DAP3_SCLK_PP3, + PMUX_PINGRP_PV0, + PMUX_PINGRP_PV1, + PMUX_PINGRP_SDMMC1_CLK_PZ0, + PMUX_PINGRP_SDMMC1_CMD_PZ1, + PMUX_PINGRP_SDMMC1_DAT3_PY4, + PMUX_PINGRP_SDMMC1_DAT2_PY5, + PMUX_PINGRP_SDMMC1_DAT1_PY6, + PMUX_PINGRP_SDMMC1_DAT0_PY7, + PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4), + PMUX_PINGRP_CLK2_REQ_PCC5, + PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4), + PMUX_PINGRP_DDC_SCL_PV4, + PMUX_PINGRP_DDC_SDA_PV5, + PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4), + PMUX_PINGRP_UART2_TXD_PC2, + PMUX_PINGRP_UART2_RTS_N_PJ6, + PMUX_PINGRP_UART2_CTS_N_PJ5, + PMUX_PINGRP_UART3_TXD_PW6, + PMUX_PINGRP_UART3_RXD_PW7, + PMUX_PINGRP_UART3_CTS_N_PA1, + PMUX_PINGRP_UART3_RTS_N_PC0, + PMUX_PINGRP_PU0, + PMUX_PINGRP_PU1, + PMUX_PINGRP_PU2, + PMUX_PINGRP_PU3, + PMUX_PINGRP_PU4, + PMUX_PINGRP_PU5, + PMUX_PINGRP_PU6, + PMUX_PINGRP_GEN1_I2C_SDA_PC5, + PMUX_PINGRP_GEN1_I2C_SCL_PC4, + PMUX_PINGRP_DAP4_FS_PP4, + PMUX_PINGRP_DAP4_DIN_PP5, + PMUX_PINGRP_DAP4_DOUT_PP6, + PMUX_PINGRP_DAP4_SCLK_PP7, + PMUX_PINGRP_CLK3_OUT_PEE0, + PMUX_PINGRP_CLK3_REQ_PEE1, + PMUX_PINGRP_GMI_WP_N_PC7, + PMUX_PINGRP_GMI_IORDY_PI5, + PMUX_PINGRP_GMI_WAIT_PI7, + PMUX_PINGRP_GMI_ADV_N_PK0, + PMUX_PINGRP_GMI_CLK_PK1, + PMUX_PINGRP_GMI_CS0_N_PJ0, + PMUX_PINGRP_GMI_CS1_N_PJ2, + PMUX_PINGRP_GMI_CS2_N_PK3, + PMUX_PINGRP_GMI_CS3_N_PK4, + PMUX_PINGRP_GMI_CS4_N_PK2, + PMUX_PINGRP_GMI_CS6_N_PI3, + PMUX_PINGRP_GMI_CS7_N_PI6, + PMUX_PINGRP_GMI_AD0_PG0, + PMUX_PINGRP_GMI_AD1_PG1, + PMUX_PINGRP_GMI_AD2_PG2, + PMUX_PINGRP_GMI_AD3_PG3, + PMUX_PINGRP_GMI_AD4_PG4, + PMUX_PINGRP_GMI_AD5_PG5, + PMUX_PINGRP_GMI_AD6_PG6, + PMUX_PINGRP_GMI_AD7_PG7, + PMUX_PINGRP_GMI_AD8_PH0, + PMUX_PINGRP_GMI_AD9_PH1, + PMUX_PINGRP_GMI_AD10_PH2, + PMUX_PINGRP_GMI_AD11_PH3, + PMUX_PINGRP_GMI_AD12_PH4, + PMUX_PINGRP_GMI_AD13_PH5, + PMUX_PINGRP_GMI_AD14_PH6, + PMUX_PINGRP_GMI_AD15_PH7, + PMUX_PINGRP_GMI_A16_PJ7, + PMUX_PINGRP_GMI_A17_PB0, + PMUX_PINGRP_GMI_A18_PB1, + PMUX_PINGRP_GMI_A19_PK7, + PMUX_PINGRP_GMI_WR_N_PI0, + PMUX_PINGRP_GMI_OE_N_PI1, + PMUX_PINGRP_GMI_DQS_P_PJ3, + PMUX_PINGRP_GMI_RST_N_PI4, + PMUX_PINGRP_GEN2_I2C_SCL_PT5, + PMUX_PINGRP_GEN2_I2C_SDA_PT6, + PMUX_PINGRP_SDMMC4_CLK_PCC4, + PMUX_PINGRP_SDMMC4_CMD_PT7, + PMUX_PINGRP_SDMMC4_DAT0_PAA0, + PMUX_PINGRP_SDMMC4_DAT1_PAA1, + PMUX_PINGRP_SDMMC4_DAT2_PAA2, + PMUX_PINGRP_SDMMC4_DAT3_PAA3, + PMUX_PINGRP_SDMMC4_DAT4_PAA4, + PMUX_PINGRP_SDMMC4_DAT5_PAA5, + PMUX_PINGRP_SDMMC4_DAT6_PAA6, + PMUX_PINGRP_SDMMC4_DAT7_PAA7, + PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4), + PMUX_PINGRP_PCC1, + PMUX_PINGRP_PBB0, + PMUX_PINGRP_CAM_I2C_SCL_PBB1, + PMUX_PINGRP_CAM_I2C_SDA_PBB2, + PMUX_PINGRP_PBB3, + PMUX_PINGRP_PBB4, + PMUX_PINGRP_PBB5, + PMUX_PINGRP_PBB6, + PMUX_PINGRP_PBB7, + PMUX_PINGRP_PCC2, + PMUX_PINGRP_JTAG_RTCK, + PMUX_PINGRP_PWR_I2C_SCL_PZ6, + PMUX_PINGRP_PWR_I2C_SDA_PZ7, + PMUX_PINGRP_KB_ROW0_PR0, + PMUX_PINGRP_KB_ROW1_PR1, + PMUX_PINGRP_KB_ROW2_PR2, + PMUX_PINGRP_KB_ROW3_PR3, + PMUX_PINGRP_KB_ROW4_PR4, + PMUX_PINGRP_KB_ROW5_PR5, + PMUX_PINGRP_KB_ROW6_PR6, + PMUX_PINGRP_KB_ROW7_PR7, + PMUX_PINGRP_KB_ROW8_PS0, + PMUX_PINGRP_KB_ROW9_PS1, + PMUX_PINGRP_KB_ROW10_PS2, + PMUX_PINGRP_KB_COL0_PQ0 = (0x2fc / 4), + PMUX_PINGRP_KB_COL1_PQ1, + PMUX_PINGRP_KB_COL2_PQ2, + PMUX_PINGRP_KB_COL3_PQ3, + PMUX_PINGRP_KB_COL4_PQ4, + PMUX_PINGRP_KB_COL5_PQ5, + PMUX_PINGRP_KB_COL6_PQ6, + PMUX_PINGRP_KB_COL7_PQ7, + PMUX_PINGRP_CLK_32K_OUT_PA0, + PMUX_PINGRP_SYS_CLK_REQ_PZ5, + PMUX_PINGRP_CORE_PWR_REQ, + PMUX_PINGRP_CPU_PWR_REQ, + PMUX_PINGRP_PWR_INT_N, + PMUX_PINGRP_CLK_32K_IN, + PMUX_PINGRP_OWR, + PMUX_PINGRP_DAP1_FS_PN0, + PMUX_PINGRP_DAP1_DIN_PN1, + PMUX_PINGRP_DAP1_DOUT_PN2, + PMUX_PINGRP_DAP1_SCLK_PN3, + PMUX_PINGRP_CLK1_REQ_PEE2, + PMUX_PINGRP_CLK1_OUT_PW4, + PMUX_PINGRP_SPDIF_IN_PK6, + PMUX_PINGRP_SPDIF_OUT_PK5, + PMUX_PINGRP_DAP2_FS_PA2, + PMUX_PINGRP_DAP2_DIN_PA4, + PMUX_PINGRP_DAP2_DOUT_PA5, + PMUX_PINGRP_DAP2_SCLK_PA3, + PMUX_PINGRP_DVFS_PWM_PX0, + PMUX_PINGRP_GPIO_X1_AUD_PX1, + PMUX_PINGRP_GPIO_X3_AUD_PX3, + PMUX_PINGRP_DVFS_CLK_PX2, + PMUX_PINGRP_GPIO_X4_AUD_PX4, + PMUX_PINGRP_GPIO_X5_AUD_PX5, + PMUX_PINGRP_GPIO_X6_AUD_PX6, + PMUX_PINGRP_GPIO_X7_AUD_PX7, + PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4), + PMUX_PINGRP_SDMMC3_CMD_PA7, + PMUX_PINGRP_SDMMC3_DAT0_PB7, + PMUX_PINGRP_SDMMC3_DAT1_PB6, + PMUX_PINGRP_SDMMC3_DAT2_PB5, + PMUX_PINGRP_SDMMC3_DAT3_PB4, + PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4), + PMUX_PINGRP_SDMMC1_WP_N_PV3, + PMUX_PINGRP_SDMMC3_CD_N_PV2, + PMUX_PINGRP_GPIO_W2_AUD_PW2, + PMUX_PINGRP_GPIO_W3_AUD_PW3, + PMUX_PINGRP_USB_VBUS_EN0_PN4, + PMUX_PINGRP_USB_VBUS_EN1_PN5, + PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5, + PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4, + PMUX_PINGRP_GMI_CLK_LB, + PMUX_PINGRP_RESET_OUT_N, + PMUX_PINGRP_COUNT, +}; + +enum pmux_drvgrp { + PMUX_DRVGRP_AO1, + PMUX_DRVGRP_AO2, + PMUX_DRVGRP_AT1, + PMUX_DRVGRP_AT2, + PMUX_DRVGRP_AT3, + PMUX_DRVGRP_AT4, + PMUX_DRVGRP_AT5, + PMUX_DRVGRP_CDEV1, + PMUX_DRVGRP_CDEV2, + PMUX_DRVGRP_DAP1 = (0x28 / 4), + PMUX_DRVGRP_DAP2, + PMUX_DRVGRP_DAP3, + PMUX_DRVGRP_DAP4, + PMUX_DRVGRP_DBG, + PMUX_DRVGRP_SDIO3 = (0x48 / 4), + PMUX_DRVGRP_SPI, + PMUX_DRVGRP_UAA, + PMUX_DRVGRP_UAB, + PMUX_DRVGRP_UART2, + PMUX_DRVGRP_UART3, + PMUX_DRVGRP_SDIO1 = (0x84 / 4), + PMUX_DRVGRP_DDC = (0x94 / 4), + PMUX_DRVGRP_GMA, + PMUX_DRVGRP_GME = (0xa8 / 4), + PMUX_DRVGRP_GMF, + PMUX_DRVGRP_GMG, + PMUX_DRVGRP_GMH, + PMUX_DRVGRP_OWR, + PMUX_DRVGRP_UDA, + PMUX_DRVGRP_DEV3 = (0xc4 / 4), + PMUX_DRVGRP_CEC = (0xd0 / 4), + PMUX_DRVGRP_AT6 = (0x12c / 4), + PMUX_DRVGRP_DAP5, + PMUX_DRVGRP_USB_VBUS_EN, + PMUX_DRVGRP_AO3, + PMUX_DRVGRP_HV0, + PMUX_DRVGRP_SDIO4, + PMUX_DRVGRP_AO0, + PMUX_DRVGRP_COUNT, +}; + +enum pmux_func { + PMUX_FUNC_DEFAULT, + PMUX_FUNC_BLINK, + PMUX_FUNC_CEC, + PMUX_FUNC_CLDVFS, + PMUX_FUNC_CLK, + PMUX_FUNC_CLK12, + PMUX_FUNC_CPU, + PMUX_FUNC_DAP, + PMUX_FUNC_DAP1, + PMUX_FUNC_DAP2, + PMUX_FUNC_DEV3, + PMUX_FUNC_DISPLAYA, + PMUX_FUNC_DISPLAYA_ALT, + PMUX_FUNC_DISPLAYB, + PMUX_FUNC_DTV, + PMUX_FUNC_EMC_DLL, + PMUX_FUNC_EXTPERIPH1, + PMUX_FUNC_EXTPERIPH2, + PMUX_FUNC_EXTPERIPH3, + PMUX_FUNC_GMI, + PMUX_FUNC_GMI_ALT, + PMUX_FUNC_HDA, + PMUX_FUNC_HSI, + PMUX_FUNC_I2C1, + PMUX_FUNC_I2C2, + PMUX_FUNC_I2C3, + PMUX_FUNC_I2C4, + PMUX_FUNC_I2CPWR, + PMUX_FUNC_I2S0, + PMUX_FUNC_I2S1, + PMUX_FUNC_I2S2, + PMUX_FUNC_I2S3, + PMUX_FUNC_I2S4, + PMUX_FUNC_IRDA, + PMUX_FUNC_KBC, + PMUX_FUNC_NAND, + PMUX_FUNC_NAND_ALT, + PMUX_FUNC_OWR, + PMUX_FUNC_PMI, + PMUX_FUNC_PWM0, + PMUX_FUNC_PWM1, + PMUX_FUNC_PWM2, + PMUX_FUNC_PWM3, + PMUX_FUNC_PWRON, + PMUX_FUNC_RESET_OUT_N, + PMUX_FUNC_RTCK, + PMUX_FUNC_SDMMC1, + PMUX_FUNC_SDMMC2, + PMUX_FUNC_SDMMC3, + PMUX_FUNC_SDMMC4, + PMUX_FUNC_SOC, + PMUX_FUNC_SPDIF, + PMUX_FUNC_SPI1, + PMUX_FUNC_SPI2, + PMUX_FUNC_SPI3, + PMUX_FUNC_SPI4, + PMUX_FUNC_SPI5, + PMUX_FUNC_SPI6, + PMUX_FUNC_SYSCLK, + PMUX_FUNC_TRACE, + PMUX_FUNC_UARTA, + PMUX_FUNC_UARTB, + PMUX_FUNC_UARTC, + PMUX_FUNC_UARTD, + PMUX_FUNC_ULPI, + PMUX_FUNC_USB, + PMUX_FUNC_VGP1, + PMUX_FUNC_VGP2, + PMUX_FUNC_VGP3, + PMUX_FUNC_VGP4, + PMUX_FUNC_VGP5, + PMUX_FUNC_VGP6, + PMUX_FUNC_VI, + PMUX_FUNC_VI_ALT1, + PMUX_FUNC_VI_ALT3, + PMUX_FUNC_RSVD1, + PMUX_FUNC_RSVD2, + PMUX_FUNC_RSVD3, + PMUX_FUNC_RSVD4, + PMUX_FUNC_COUNT, +}; + +#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 +#define TEGRA_PMX_SOC_HAS_IO_CLAMPING +#define TEGRA_PMX_SOC_HAS_DRVGRPS +#define TEGRA_PMX_GRPS_HAVE_LPMD +#define TEGRA_PMX_GRPS_HAVE_SCHMT +#define TEGRA_PMX_GRPS_HAVE_HSM +#define TEGRA_PMX_PINS_HAVE_E_INPUT +#define TEGRA_PMX_PINS_HAVE_LOCK +#define TEGRA_PMX_PINS_HAVE_OD +#define TEGRA_PMX_PINS_HAVE_IO_RESET +#define TEGRA_PMX_PINS_HAVE_RCV_SEL +#include + +#endif /* _TEGRA114_PINMUX_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra114/powergate.h b/roms/u-boot/arch/arm/include/asm/arch-tegra114/powergate.h new file mode 100644 index 000000000..260ea801b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra114/powergate.h @@ -0,0 +1,6 @@ +#ifndef _TEGRA114_POWERGATE_H_ +#define _TEGRA114_POWERGATE_H_ + +#include + +#endif /* _TEGRA114_POWERGATE_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra114/sysctr.h b/roms/u-boot/arch/arm/include/asm/arch-tegra114/sysctr.h new file mode 100644 index 000000000..228f423be --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra114/sysctr.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA114_SYSCTR_H_ +#define _TEGRA114_SYSCTR_H_ + +struct sysctr_ctlr { + u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ + u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ + u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ + u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ + u32 reserved1[4]; /* 0x10 - 0x1C */ + u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ + u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ + u32 reserved2[1002]; /* 0x28 - 0xFCC */ + u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ +}; + +#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ +#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ + +#endif /* _TEGRA114_SYSCTR_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra114/tegra.h b/roms/u-boot/arch/arm/include/asm/arch-tegra114/tegra.h new file mode 100644 index 000000000..317b4bc14 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra114/tegra.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA114_H_ +#define _TEGRA114_H_ + +#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */ +#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ +#define NV_PA_MC_BASE 0x70019000 + +#include + +#define BCT_ODMDATA_OFFSET 1752 /* offset to ODMDATA word */ + +#undef NVBOOTINFOTABLE_BCTSIZE +#undef NVBOOTINFOTABLE_BCTPTR +#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ +#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ + +#define MAX_NUM_CPU 4 + +#endif /* TEGRA114_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra124/ahb.h b/roms/u-boot/arch/arm/include/asm/arch-tegra124/ahb.h new file mode 100644 index 000000000..d88cdfece --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra124/ahb.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + */ + +#ifndef _TEGRA124_AHB_H_ +#define _TEGRA124_AHB_H_ + +struct ahb_ctlr { + u32 reserved0; /* 00h */ + u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */ + u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */ + u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */ + u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */ + u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */ + u32 reserved6[2]; /* 18h, 1ch */ + u32 gizmo_usb; /* _GIZMO_USB_0, 20h */ + u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */ + u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */ + u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */ + u32 gizmo_xbar_apb_ctlr; /* _GIZMO_XBAR_APB_CTLR_0, 30h */ + u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */ + u32 reserved13[2]; /* 38h, 3ch */ + u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */ + u32 reserved15; /* 44h */ + u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */ + u32 reserved17; /* 4ch */ + u32 gizmo_se; /* _GIZMO_SE_0, 50h */ + u32 gizmo_tzram; /* _GIZMO_TZRAM_0, 54h */ + u32 reserved20[3]; /* 58h, 5ch, 60h */ + u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */ + u32 reserved22[3]; /* 68h, 6ch, 70h */ + u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */ + u32 gizmo_nor; /* _GIZMO_NOR_0, 78h */ + u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */ + u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */ + u32 gizmo_sdmmc1; /* _GIZMO_SDMMC1_0, 84h */ + u32 gizmo_sdmmc2; /* _GIZMO_SDMMC2_0, 88h */ + u32 gizmo_sdmmc3; /* _GIZMO_SDMMC3_0, 8ch */ + u32 reserved30[13]; /* 90h ~ c0h */ + u32 ahb_wrq_empty; /* _AHB_WRQ_EMPTY_0, c4h */ + u32 reserved32[5]; /* c8h ~ d8h */ + u32 ahb_mem_prefetch_cfg_x; /* _AHB_MEM_PREFETCH_CFG_X_0, dch */ + u32 arbitration_xbar_ctrl; /* _ARBITRATION_XBAR_CTRL_0, e0h */ + u32 ahb_mem_prefetch_cfg3; /* _AHB_MEM_PREFETCH_CFG3_0, e4h */ + u32 ahb_mem_prefetch_cfg4; /* _AHB_MEM_PREFETCH_CFG3_0, e8h */ + u32 avp_ppcs_rd_coh_status; /* _AVP_PPCS_RD_COH_STATUS_0, ech */ + u32 ahb_mem_prefetch_cfg1; /* _AHB_MEM_PREFETCH_CFG1_0, f0h */ + u32 ahb_mem_prefetch_cfg2; /* _AHB_MEM_PREFETCH_CFG2_0, f4h */ + u32 ahbslvmem_status; /* _AHBSLVMEM_STATUS_0, f8h */ + /* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */ + u32 arbitration_ahb_mem_wrque_mst_id; + u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */ + u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */ + u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */ + u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */ + u32 reserved46[4]; /* 110h ~ 11ch */ + u32 avpc_mccif_fifoctrl; /* _AVPC_MCCIF_FIFOCTRL_0, 120h */ + u32 timeout_wcoal_avpc; /* _TIMEOUT_WCOAL_AVPC_0, 124h */ + u32 mpcorelp_mccif_fifoctrl; /* _MPCORELP_MCCIF_FIFOCTRL_0, 128h */ + u32 mpcore_mccif_fifoctrl; /* _MPCORE_MCCIF_FIFOCTRL_0, 12ch */ + u32 axicif_fastsync_ctrl; /* AXICIF_FASTSYNC_CTRL_0, 130h */ + u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */ + /* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */ + u32 axicif_fastsync0_cpuclk_to_mcclk; + /* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */ + u32 axicif_fastsync1_cpuclk_to_mcclk; + /* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */ + u32 axicif_fastsync2_cpuclk_to_mcclk; + /* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */ + u32 axicif_fastsync0_mcclk_to_cpuclk; + /* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */ + u32 axicif_fastsync1_mcclk_to_cpuclk; + /* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */ + u32 axicif_fastsync2_mcclk_to_cpuclk; +}; + +#define PPSB_STOPCLK_ENABLE (1 << 2) + +#define GIZ_ENABLE_SPLIT (1 << 0) +#define GIZ_ENB_FAST_REARB (1 << 2) +#define GIZ_DONT_SPLIT_AHB_WR (1 << 7) + +#define GIZ_USB_IMMEDIATE (1 << 18) + +/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */ +#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2) + +#endif /* _TEGRA124_AHB_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra124/clock-tables.h b/roms/u-boot/arch/arm/include/asm/arch-tegra124/clock-tables.h new file mode 100644 index 000000000..9f5312531 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra124/clock-tables.h @@ -0,0 +1,497 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + */ + +/* Tegra124 clock PLL tables */ + +#ifndef _TEGRA124_CLOCK_TABLES_H_ +#define _TEGRA124_CLOCK_TABLES_H_ + +/* The PLLs supported by the hardware */ +enum clock_id { + CLOCK_ID_FIRST, + CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, + CLOCK_ID_MEMORY, + CLOCK_ID_PERIPH, + CLOCK_ID_AUDIO, + CLOCK_ID_USB, + CLOCK_ID_DISPLAY, + + /* now the simple ones */ + CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_EPCI, + CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DP, /* Special for Tegra124 */ + + /* These are the base clocks (inputs to the Tegra SoC) */ + CLOCK_ID_32KHZ, + CLOCK_ID_OSC, + CLOCK_ID_CLK_M, + + CLOCK_ID_COUNT, /* number of PLLs */ + + /* + * These are clock IDs that are used in table clock_source[][] + * but will not be assigned as a clock source for any peripheral. + */ + CLOCK_ID_DISPLAY2, + CLOCK_ID_CGENERAL2, + CLOCK_ID_CGENERAL3, + CLOCK_ID_MEMORY2, + CLOCK_ID_SRC2, + + CLOCK_ID_NONE = -1, +}; + +/* The clocks supported by the hardware */ +enum periph_id { + PERIPH_ID_FIRST, + + /* Low word: 31:0 (DEVICES_L) */ + PERIPH_ID_CPU = PERIPH_ID_FIRST, + PERIPH_ID_COP, + PERIPH_ID_TRIGSYS, + PERIPH_ID_ISPB, + PERIPH_ID_RESERVED4, + PERIPH_ID_TMR, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + + /* 8 */ + PERIPH_ID_GPIO, + PERIPH_ID_SDMMC2, + PERIPH_ID_SPDIF, + PERIPH_ID_I2S1, + PERIPH_ID_I2C1, + PERIPH_ID_RESERVED13, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC4, + + /* 16 */ + PERIPH_ID_TCW, + PERIPH_ID_PWM, + PERIPH_ID_I2S2, + PERIPH_ID_RESERVED19, + PERIPH_ID_VI, + PERIPH_ID_RESERVED21, + PERIPH_ID_USBD, + PERIPH_ID_ISP, + + /* 24 */ + PERIPH_ID_RESERVED24, + PERIPH_ID_RESERVED25, + PERIPH_ID_DISP2, + PERIPH_ID_DISP1, + PERIPH_ID_HOST1X, + PERIPH_ID_VCP, + PERIPH_ID_I2S0, + PERIPH_ID_CACHE2, + + /* Middle word: 63:32 (DEVICES_H) */ + PERIPH_ID_MEM, + PERIPH_ID_AHBDMA, + PERIPH_ID_APBDMA, + PERIPH_ID_RESERVED35, + PERIPH_ID_RESERVED36, + PERIPH_ID_STAT_MON, + PERIPH_ID_RESERVED38, + PERIPH_ID_FUSE, + + /* 40 */ + PERIPH_ID_KFUSE, + PERIPH_ID_SBC1, + PERIPH_ID_SNOR, + PERIPH_ID_RESERVED43, + PERIPH_ID_SBC2, + PERIPH_ID_XIO, + PERIPH_ID_SBC3, + PERIPH_ID_I2C5, + + /* 48 */ + PERIPH_ID_DSI, + PERIPH_ID_RESERVED49, + PERIPH_ID_HSI, + PERIPH_ID_HDMI, + PERIPH_ID_CSI, + PERIPH_ID_RESERVED53, + PERIPH_ID_I2C2, + PERIPH_ID_UART3, + + /* 56 */ + PERIPH_ID_MIPI_CAL, + PERIPH_ID_EMC, + PERIPH_ID_USB2, + PERIPH_ID_USB3, + PERIPH_ID_RESERVED60, + PERIPH_ID_VDE, + PERIPH_ID_BSEA, + PERIPH_ID_BSEV, + + /* Upper word 95:64 (DEVICES_U) */ + PERIPH_ID_RESERVED64, + PERIPH_ID_UART4, + PERIPH_ID_UART5, + PERIPH_ID_I2C3, + PERIPH_ID_SBC4, + PERIPH_ID_SDMMC3, + PERIPH_ID_PCIE, + PERIPH_ID_OWR, + + /* 72 */ + PERIPH_ID_AFI, + PERIPH_ID_CORESIGHT, + PERIPH_ID_PCIEXCLK, + PERIPH_ID_AVPUCQ, + PERIPH_ID_LA, + PERIPH_ID_TRACECLKIN, + PERIPH_ID_SOC_THERM, + PERIPH_ID_DTV, + + /* 80 */ + PERIPH_ID_RESERVED80, + PERIPH_ID_I2CSLOW, + PERIPH_ID_DSIB, + PERIPH_ID_TSEC, + PERIPH_ID_RESERVED84, + PERIPH_ID_RESERVED85, + PERIPH_ID_RESERVED86, + PERIPH_ID_EMUCIF, + + /* 88 */ + PERIPH_ID_RESERVED88, + PERIPH_ID_XUSB_HOST, + PERIPH_ID_RESERVED90, + PERIPH_ID_MSENC, + PERIPH_ID_RESERVED92, + PERIPH_ID_RESERVED93, + PERIPH_ID_RESERVED94, + PERIPH_ID_XUSB_DEV, + + PERIPH_ID_VW_FIRST, + /* V word: 31:0 */ + PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST, + PERIPH_ID_CPULP, + PERIPH_ID_V_RESERVED2, + PERIPH_ID_MSELECT, + PERIPH_ID_V_RESERVED4, + PERIPH_ID_I2S3, + PERIPH_ID_I2S4, + PERIPH_ID_I2C4, + + /* 104 */ + PERIPH_ID_SBC5, + PERIPH_ID_SBC6, + PERIPH_ID_AUDIO, + PERIPH_ID_APBIF, + PERIPH_ID_DAM0, + PERIPH_ID_DAM1, + PERIPH_ID_DAM2, + PERIPH_ID_HDA2CODEC2X, + + /* 112 */ + PERIPH_ID_ATOMICS, + PERIPH_ID_V_RESERVED17, + PERIPH_ID_V_RESERVED18, + PERIPH_ID_V_RESERVED19, + PERIPH_ID_V_RESERVED20, + PERIPH_ID_V_RESERVED21, + PERIPH_ID_V_RESERVED22, + PERIPH_ID_ACTMON, + + /* 120 */ + PERIPH_ID_EXTPERIPH1, + PERIPH_ID_EXTPERIPH2, + PERIPH_ID_EXTPERIPH3, + PERIPH_ID_OOB, + PERIPH_ID_SATA, + PERIPH_ID_HDA, + PERIPH_ID_V_RESERVED30, + PERIPH_ID_V_RESERVED31, + + /* W word: 31:0 */ + PERIPH_ID_HDA2HDMICODEC, + PERIPH_ID_SATACOLD, + PERIPH_ID_W_RESERVED2, + PERIPH_ID_W_RESERVED3, + PERIPH_ID_W_RESERVED4, + PERIPH_ID_W_RESERVED5, + PERIPH_ID_W_RESERVED6, + PERIPH_ID_W_RESERVED7, + + /* 136 */ + PERIPH_ID_CEC, + PERIPH_ID_W_RESERVED9, + PERIPH_ID_W_RESERVED10, + PERIPH_ID_W_RESERVED11, + PERIPH_ID_W_RESERVED12, + PERIPH_ID_W_RESERVED13, + PERIPH_ID_XUSB_PADCTL, + PERIPH_ID_W_RESERVED15, + + /* 144 */ + PERIPH_ID_W_RESERVED16, + PERIPH_ID_W_RESERVED17, + PERIPH_ID_W_RESERVED18, + PERIPH_ID_W_RESERVED19, + PERIPH_ID_W_RESERVED20, + PERIPH_ID_ENTROPY, + PERIPH_ID_DDS, + PERIPH_ID_W_RESERVED23, + + /* 152 */ + PERIPH_ID_DP2, + PERIPH_ID_AMX0, + PERIPH_ID_ADX0, + PERIPH_ID_DVFS, + PERIPH_ID_XUSB_SS, + PERIPH_ID_W_RESERVED29, + PERIPH_ID_W_RESERVED30, + PERIPH_ID_W_RESERVED31, + + PERIPH_ID_X_FIRST, + /* X word: 31:0 */ + PERIPH_ID_SPARE = PERIPH_ID_X_FIRST, + PERIPH_ID_X_RESERVED1, + PERIPH_ID_X_RESERVED2, + PERIPH_ID_X_RESERVED3, + PERIPH_ID_CAM_MCLK, + PERIPH_ID_CAM_MCLK2, + PERIPH_ID_I2C6, + PERIPH_ID_X_RESERVED7, + + /* 168 */ + PERIPH_ID_X_RESERVED8, + PERIPH_ID_X_RESERVED9, + PERIPH_ID_X_RESERVED10, + PERIPH_ID_VIM2_CLK, + PERIPH_ID_X_RESERVED12, + PERIPH_ID_X_RESERVED13, + PERIPH_ID_EMC_DLL, + PERIPH_ID_X_RESERVED15, + + /* 176 */ + PERIPH_ID_HDMI_AUDIO, + PERIPH_ID_CLK72MHZ, + PERIPH_ID_VIC, + PERIPH_ID_X_RESERVED19, + PERIPH_ID_ADX1, + PERIPH_ID_DPAUX, + PERIPH_ID_SOR0, + PERIPH_ID_X_RESERVED23, + + /* 184 */ + PERIPH_ID_GPU, + PERIPH_ID_AMX1, + PERIPH_ID_AFC5, + PERIPH_ID_AFC4, + PERIPH_ID_AFC3, + PERIPH_ID_AFC2, + PERIPH_ID_AFC1, + PERIPH_ID_AFC0, + + PERIPH_ID_COUNT, + PERIPH_ID_NONE = -1, +}; + +enum pll_out_id { + PLL_OUT1, + PLL_OUT2, + PLL_OUT3, + PLL_OUT4 +}; + +/* + * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want + * callers to use the PERIPH_ID for all access to peripheral clocks to avoid + * confusion bewteen PERIPH_ID_... and PERIPHC_... + * + * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be + * confusing. + */ +enum periphc_internal_id { + /* 0x00 */ + PERIPHC_I2S1, + PERIPHC_I2S2, + PERIPHC_SPDIF_OUT, + PERIPHC_SPDIF_IN, + PERIPHC_PWM, + PERIPHC_05h, + PERIPHC_SBC2, + PERIPHC_SBC3, + + /* 0x08 */ + PERIPHC_08h, + PERIPHC_I2C1, + PERIPHC_I2C5, + PERIPHC_0bh, + PERIPHC_0ch, + PERIPHC_SBC1, + PERIPHC_DISP1, + PERIPHC_DISP2, + + /* 0x10 */ + PERIPHC_10h, + PERIPHC_11h, + PERIPHC_VI, + PERIPHC_13h, + PERIPHC_SDMMC1, + PERIPHC_SDMMC2, + PERIPHC_G3D, + PERIPHC_G2D, + + /* 0x18 */ + PERIPHC_18h, + PERIPHC_SDMMC4, + PERIPHC_VFIR, + PERIPHC_1Bh, + PERIPHC_1Ch, + PERIPHC_HSI, + PERIPHC_UART1, + PERIPHC_UART2, + + /* 0x20 */ + PERIPHC_HOST1X, + PERIPHC_21h, + PERIPHC_22h, + PERIPHC_HDMI, + PERIPHC_24h, + PERIPHC_25h, + PERIPHC_I2C2, + PERIPHC_EMC, + + /* 0x28 */ + PERIPHC_UART3, + PERIPHC_29h, + PERIPHC_VI_SENSOR, + PERIPHC_2bh, + PERIPHC_2ch, + PERIPHC_SBC4, + PERIPHC_I2C3, + PERIPHC_SDMMC3, + + /* 0x30 */ + PERIPHC_UART4, + PERIPHC_UART5, + PERIPHC_VDE, + PERIPHC_OWR, + PERIPHC_NOR, + PERIPHC_CSITE, + PERIPHC_I2S0, + PERIPHC_DTV, + + /* 0x38 */ + PERIPHC_38h, + PERIPHC_39h, + PERIPHC_3ah, + PERIPHC_3bh, + PERIPHC_MSENC, + PERIPHC_TSEC, + PERIPHC_3eh, + PERIPHC_OSC, + + PERIPHC_VW_FIRST, + /* 0x40 */ + PERIPHC_40h = PERIPHC_VW_FIRST, + PERIPHC_MSELECT, + PERIPHC_TSENSOR, + PERIPHC_I2S3, + PERIPHC_I2S4, + PERIPHC_I2C4, + PERIPHC_SBC5, + PERIPHC_SBC6, + + /* 0x48 */ + PERIPHC_AUDIO, + PERIPHC_49h, + PERIPHC_DAM0, + PERIPHC_DAM1, + PERIPHC_DAM2, + PERIPHC_HDA2CODEC2X, + PERIPHC_ACTMON, + PERIPHC_EXTPERIPH1, + + /* 0x50 */ + PERIPHC_EXTPERIPH2, + PERIPHC_EXTPERIPH3, + PERIPHC_52h, + PERIPHC_I2CSLOW, + PERIPHC_SYS, + PERIPHC_55h, + PERIPHC_56h, + PERIPHC_57h, + + /* 0x58 */ + PERIPHC_58h, + PERIPHC_SOR, + PERIPHC_5ah, + PERIPHC_5bh, + PERIPHC_SATAOOB, + PERIPHC_SATA, + PERIPHC_HDA, /* 0x428 */ + PERIPHC_5fh, + + PERIPHC_X_FIRST, + /* 0x60 */ + PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */ + PERIPHC_XUSB_FALCON, + PERIPHC_XUSB_FS, + PERIPHC_XUSB_CORE_DEV, + PERIPHC_XUSB_SS, + PERIPHC_CILAB, + PERIPHC_CILCD, + PERIPHC_CILE, + + /* 0x68 */ + PERIPHC_DSIA_LP, + PERIPHC_DSIB_LP, + PERIPHC_ENTROPY, + PERIPHC_DVFS_REF, + PERIPHC_DVFS_SOC, + PERIPHC_TRACECLKIN, + PERIPHC_ADX0, + PERIPHC_AMX0, + + /* 0x70 */ + PERIPHC_EMC_LATENCY, + PERIPHC_SOC_THERM, + PERIPHC_72h, + PERIPHC_73h, + PERIPHC_74h, + PERIPHC_75h, + PERIPHC_VI_SENSOR2, + PERIPHC_I2C6, + + /* 0x78 */ + PERIPHC_78h, + PERIPHC_EMC_DLL, + PERIPHC_HDMI_AUDIO, + PERIPHC_CLK72MHZ, + PERIPHC_ADX1, + PERIPHC_AMX1, + PERIPHC_VIC, + PERIPHC_7fh, + + PERIPHC_COUNT, + + PERIPHC_NONE = -1, +}; + +/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */ +#define PERIPH_REG(id) \ + (id < PERIPH_ID_VW_FIRST) ? \ + ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5) + +/* Mask value for a clock (within PERIPH_REG(id)) */ +#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) + +/* return 1 if a PLL ID is in range */ +#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) + +/* return 1 if a peripheral ID is in range */ +#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ + (id) < PERIPH_ID_COUNT) + +#endif /* _TEGRA124_CLOCK_TABLES_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra124/clock.h b/roms/u-boot/arch/arm/include/asm/arch-tegra124/clock.h new file mode 100644 index 000000000..3f54d3627 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra124/clock.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + */ + +/* Tegra124 clock control definitions */ + +#ifndef _TEGRA124_CLOCK_H_ +#define _TEGRA124_CLOCK_H_ + +#include + +/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ +#define OSC_FREQ_SHIFT 28 +#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) + +/* CLK_RST_CONTROLLER_PLLC_MISC_0 */ +#define PLLC_IDDQ (1 << 26) + +/* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */ +#define SOR0_CLK_SEL0 (1 << 14) +#define SOR0_CLK_SEL1 (1 << 15) + +int tegra_plle_enable(void); + +void clock_sor_enable_edp_clock(void); + +/** + * clock_set_display_rate() - Set the display clock rate + * + * @frequency: the requested PLLD frequency + * + * Return the PLLD frequenc (which may not quite what was requested), or 0 + * on failure + */ +u32 clock_set_display_rate(u32 frequency); + +/** + * clock_set_up_plldp() - Set up the EDP clock ready for use + */ +void clock_set_up_plldp(void); + +#endif /* _TEGRA124_CLOCK_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra124/display.h b/roms/u-boot/arch/arm/include/asm/arch-tegra124/display.h new file mode 100644 index 000000000..47e0056dd --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra124/display.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * NVIDIA Corporation + */ + +#ifndef __ASM_ARCH_TEGRA_DISPLAY_H +#define __ASM_ARCH_TEGRA_DISPLAY_H + +/** + * Register a new display based on device tree configuration. + * + * The frame buffer can be positioned by U-Boot or overridden by the fdt. + * You should pass in the U-Boot address here, and check the contents of + * struct fdt_disp_config to see what was actually chosen. + * + * @param blob Device tree blob + * @param default_lcd_base Default address of LCD frame buffer + * @return 0 if ok, -1 on error (unsupported bits per pixel) + */ +int tegra_display_probe(const void *blob, void *default_lcd_base); + +/** + * Return the current display configuration + * + * @return pointer to display configuration, or NULL if there is no valid + * config + */ +struct fdt_disp_config *tegra_display_get_config(void); + +/** + * Perform the next stage of the LCD init if it is time to do so. + * + * LCD init can be time-consuming because of the number of delays we need + * while waiting for the backlight power supply, etc. This function can + * be called at various times during U-Boot operation to advance the + * initialization of the LCD to the next stage if sufficient time has + * passed since the last stage. It keeps track of what stage it is up to + * and the time that it is permitted to move to the next stage. + * + * The final call should have wait=1 to complete the init. + * + * @param blob fdt blob containing LCD information + * @param wait 1 to wait until all init is complete, and then return + * 0 to return immediately, potentially doing nothing if it is + * not yet time for the next init. + */ +int tegra_lcd_check_next_stage(const void *blob, int wait); + +/** + * Set up the maximum LCD size so we can size the frame buffer. + * + * @param blob fdt blob containing LCD information + */ +void tegra_lcd_early_init(const void *blob); + +#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra124/flow.h b/roms/u-boot/arch/arm/include/asm/arch-tegra124/flow.h new file mode 100644 index 000000000..ebcb22f1c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra124/flow.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + */ + +#ifndef _TEGRA124_FLOW_H_ +#define _TEGRA124_FLOW_H_ + +#ifndef __ASSEMBLY__ +#include +#endif + +struct flow_ctlr { + u32 halt_cpu_events; /* offset 0x00 */ + u32 halt_cop_events; /* offset 0x04 */ + u32 cpu_csr; /* offset 0x08 */ + u32 cop_csr; /* offset 0x0c */ + u32 xrq_events; /* offset 0x10 */ + u32 halt_cpu1_events; /* offset 0x14 */ + u32 cpu1_csr; /* offset 0x18 */ + u32 halt_cpu2_events; /* offset 0x1c */ + u32 cpu2_csr; /* offset 0x20 */ + u32 halt_cpu3_events; /* offset 0x24 */ + u32 cpu3_csr; /* offset 0x28 */ + u32 cluster_control; /* offset 0x2c */ + u32 halt_cop1_events; /* offset 0x30 */ + u32 halt_cop1_csr; /* offset 0x34 */ + u32 cpu_pwr_csr; /* offset 0x38 */ + u32 mpid; /* offset 0x3c */ + u32 ram_repair; /* offset 0x40 */ + u32 flow_dbg_sel; /* offset 0x44 */ + u32 flow_dbg_cnt0; /* offset 0x48 */ + u32 flow_dbg_cnt1; /* offset 0x4c */ + u32 flow_dbg_qual; /* offset 0x50 */ + u32 flow_ctrl_spare; /* offset 0x54 */ + u32 ram_repair_cluster1;/* offset 0x58 */ +}; + +/* HALT_COP_EVENTS_0, 0x04 */ +#define EVENT_MSEC (1 << 24) +#define EVENT_USEC (1 << 25) +#define EVENT_JTAG (1 << 28) +#define EVENT_MODE_STOP (2 << 29) + +/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ +#define ACTIVE_LP (1 << 0) + +/* CPUn_CSR_0 */ +#define CSR_ENABLE (1 << 0) +#define CSR_IMMEDIATE_WAKE (1 << 3) +#define CSR_WAIT_WFI_SHIFT 8 +#define CSR_PWR_OFF_STS (1 << 16) + +#define RAM_REPAIR_REQ BIT(0) +#define RAM_REPAIR_STS BIT(1) +#define RAM_REPAIR_BYPASS_EN BIT(2) + +#endif /* _TEGRA124_FLOW_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra124/funcmux.h b/roms/u-boot/arch/arm/include/asm/arch-tegra124/funcmux.h new file mode 100644 index 000000000..8d4501e7d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra124/funcmux.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + */ + +/* Tegra124 high-level function multiplexing */ + +#ifndef _TEGRA124_FUNCMUX_H_ +#define _TEGRA124_FUNCMUX_H_ + +#include + +/* Configs supported by the func mux */ +enum { + FUNCMUX_DEFAULT = 0, /* default config */ + + /* UART configs */ + FUNCMUX_UART1_KBC = 0, + FUNCMUX_UART4_GPIO = 0, +}; +#endif /* _TEGRA124_FUNCMUX_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra124/gp_padctrl.h b/roms/u-boot/arch/arm/include/asm/arch-tegra124/gp_padctrl.h new file mode 100644 index 000000000..750a2dc64 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra124/gp_padctrl.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + */ + +#ifndef _TEGRA124_GP_PADCTRL_H_ +#define _TEGRA124_GP_PADCTRL_H_ + +#include + +/* APB_MISC_GP and padctrl registers */ +struct apb_misc_gp_ctlr { + u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ + u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ + u32 reserved0[22]; /* 0x08 - 0x5C: */ + u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ + u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ + u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ + u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ + u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ + u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ + u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ + u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ + u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ + u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ + u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ + u32 reserved1; /* 0x8C: */ + u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ + u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ + u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ + u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ + u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ + u32 reserved2[3]; /* 0xA4 - 0xAC: */ + u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ + u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ + u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ + u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ + u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ + u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ + u32 reserved3[9]; /* 0xC8-0xE8: */ + u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ + u32 reserved4[3]; /* 0xF0-0xF8: */ + u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ + u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ + u32 reserved5[3]; /* 0x104-0x10C: */ + u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ + u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ + u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ + u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ + u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ + u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ + u32 reserved6; /* 0x128: */ + u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ + u32 reserved7[2]; /* 0x130 - 0x134: */ + u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ + u32 reserved8[22]; /* 0x13C - 0x190: */ + u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ + u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ + u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ + u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ + u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ + u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ + u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ +}; + +/* SDMMC1/3 settings from section 27.5 of T114 TRM */ +#define SDIOCFG_DRVUP_SLWF 0 +#define SDIOCFG_DRVDN_SLWR 0 +#define SDIOCFG_DRVUP 0x24 +#define SDIOCFG_DRVDN 0x14 + +#endif /* _TEGRA124_GP_PADCTRL_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra124/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-tegra124/gpio.h new file mode 100644 index 000000000..e5ea2815a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra124/gpio.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + */ + +#ifndef _TEGRA124_GPIO_H_ +#define _TEGRA124_GPIO_H_ + +/* + * The Tegra124 GPIO controller has 256 GPIOS in 8 banks of 4 ports, + * each with 8 GPIOs. + */ +#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ +#define TEGRA_GPIO_BANKS 8 /* number of banks */ + +#include + +/* GPIO Controller registers for a single bank */ +struct gpio_ctlr_bank { + uint gpio_config[TEGRA_GPIO_PORTS]; + uint gpio_dir_out[TEGRA_GPIO_PORTS]; + uint gpio_out[TEGRA_GPIO_PORTS]; + uint gpio_in[TEGRA_GPIO_PORTS]; + uint gpio_int_status[TEGRA_GPIO_PORTS]; + uint gpio_int_enable[TEGRA_GPIO_PORTS]; + uint gpio_int_level[TEGRA_GPIO_PORTS]; + uint gpio_int_clear[TEGRA_GPIO_PORTS]; + uint gpio_masked_config[TEGRA_GPIO_PORTS]; + uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; + uint gpio_masked_out[TEGRA_GPIO_PORTS]; + uint gpio_masked_in[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_clear[TEGRA_GPIO_PORTS]; +}; + +struct gpio_ctlr { + struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; +}; + +#endif /* _TEGRA124_GPIO_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra124/mc.h b/roms/u-boot/arch/arm/include/asm/arch-tegra124/mc.h new file mode 100644 index 000000000..617e55af2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra124/mc.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA124_MC_H_ +#define _TEGRA124_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[4]; /* offset 0x00 - 0x0C */ + u32 mc_smmu_config; /* offset 0x10 */ + u32 mc_smmu_tlb_config; /* offset 0x14 */ + u32 mc_smmu_ptc_config; /* offset 0x18 */ + u32 mc_smmu_ptb_asid; /* offset 0x1C */ + u32 mc_smmu_ptb_data; /* offset 0x20 */ + u32 reserved1[3]; /* offset 0x24 - 0x2C */ + u32 mc_smmu_tlb_flush; /* offset 0x30 */ + u32 mc_smmu_ptc_flush; /* offset 0x34 */ + u32 reserved2[6]; /* offset 0x38 - 0x4C */ + u32 mc_emem_cfg; /* offset 0x50 */ + u32 mc_emem_adr_cfg; /* offset 0x54 */ + u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ + u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ + u32 reserved3[4]; /* offset 0x60 - 0x6C */ + u32 mc_security_cfg0; /* offset 0x70 */ + u32 mc_security_cfg1; /* offset 0x74 */ + u32 reserved4[6]; /* offset 0x7C - 0x8C */ + u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ + u32 reserved5[74]; /* offset 0x100 - 0x224 */ + u32 mc_smmu_translation_enable_0; /* offset 0x228 */ + u32 mc_smmu_translation_enable_1; /* offset 0x22C */ + u32 mc_smmu_translation_enable_2; /* offset 0x230 */ + u32 mc_smmu_translation_enable_3; /* offset 0x234 */ + u32 mc_smmu_afi_asid; /* offset 0x238 */ + u32 mc_smmu_avpc_asid; /* offset 0x23C */ + u32 mc_smmu_dc_asid; /* offset 0x240 */ + u32 mc_smmu_dcb_asid; /* offset 0x244 */ + u32 reserved6[2]; /* offset 0x248 - 0x24C */ + u32 mc_smmu_hc_asid; /* offset 0x250 */ + u32 mc_smmu_hda_asid; /* offset 0x254 */ + u32 mc_smmu_isp2_asid; /* offset 0x258 */ + u32 reserved7[2]; /* offset 0x25C - 0x260 */ + u32 mc_smmu_msenc_asid; /* offset 0x264 */ + u32 mc_smmu_nv_asid; /* offset 0x268 */ + u32 mc_smmu_nv2_asid; /* offset 0x26C */ + u32 mc_smmu_ppcs_asid; /* offset 0x270 */ + u32 mc_smmu_sata_asid; /* offset 0x274 */ + u32 reserved8[1]; /* offset 0x278 */ + u32 mc_smmu_vde_asid; /* offset 0x27C */ + u32 mc_smmu_vi_asid; /* offset 0x280 */ + u32 mc_smmu_vic_asid; /* offset 0x284 */ + u32 mc_smmu_xusb_host_asid; /* offset 0x288 */ + u32 mc_smmu_xusb_dev_asid; /* offset 0x28C */ + u32 reserved9[1]; /* offset 0x290 */ + u32 mc_smmu_tsec_asid; /* offset 0x294 */ + u32 mc_smmu_ppcs1_asid; /* offset 0x298 */ + u32 reserved10[235]; /* offset 0x29C - 0x644 */ + u32 mc_video_protect_bom; /* offset 0x648 */ + u32 mc_video_protect_size_mb; /* offset 0x64c */ + u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ +}; + +#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0) + +#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) +#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) + +#endif /* _TEGRA124_MC_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra124/pinmux.h b/roms/u-boot/arch/arm/include/asm/arch-tegra124/pinmux.h new file mode 100644 index 000000000..4c593aae7 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra124/pinmux.h @@ -0,0 +1,359 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA124_PINMUX_H_ +#define _TEGRA124_PINMUX_H_ + +enum pmux_pingrp { + PMUX_PINGRP_ULPI_DATA0_PO1, + PMUX_PINGRP_ULPI_DATA1_PO2, + PMUX_PINGRP_ULPI_DATA2_PO3, + PMUX_PINGRP_ULPI_DATA3_PO4, + PMUX_PINGRP_ULPI_DATA4_PO5, + PMUX_PINGRP_ULPI_DATA5_PO6, + PMUX_PINGRP_ULPI_DATA6_PO7, + PMUX_PINGRP_ULPI_DATA7_PO0, + PMUX_PINGRP_ULPI_CLK_PY0, + PMUX_PINGRP_ULPI_DIR_PY1, + PMUX_PINGRP_ULPI_NXT_PY2, + PMUX_PINGRP_ULPI_STP_PY3, + PMUX_PINGRP_DAP3_FS_PP0, + PMUX_PINGRP_DAP3_DIN_PP1, + PMUX_PINGRP_DAP3_DOUT_PP2, + PMUX_PINGRP_DAP3_SCLK_PP3, + PMUX_PINGRP_PV0, + PMUX_PINGRP_PV1, + PMUX_PINGRP_SDMMC1_CLK_PZ0, + PMUX_PINGRP_SDMMC1_CMD_PZ1, + PMUX_PINGRP_SDMMC1_DAT3_PY4, + PMUX_PINGRP_SDMMC1_DAT2_PY5, + PMUX_PINGRP_SDMMC1_DAT1_PY6, + PMUX_PINGRP_SDMMC1_DAT0_PY7, + PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4), + PMUX_PINGRP_CLK2_REQ_PCC5, + PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4), + PMUX_PINGRP_DDC_SCL_PV4, + PMUX_PINGRP_DDC_SDA_PV5, + PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4), + PMUX_PINGRP_UART2_TXD_PC2, + PMUX_PINGRP_UART2_RTS_N_PJ6, + PMUX_PINGRP_UART2_CTS_N_PJ5, + PMUX_PINGRP_UART3_TXD_PW6, + PMUX_PINGRP_UART3_RXD_PW7, + PMUX_PINGRP_UART3_CTS_N_PA1, + PMUX_PINGRP_UART3_RTS_N_PC0, + PMUX_PINGRP_PU0, + PMUX_PINGRP_PU1, + PMUX_PINGRP_PU2, + PMUX_PINGRP_PU3, + PMUX_PINGRP_PU4, + PMUX_PINGRP_PU5, + PMUX_PINGRP_PU6, + PMUX_PINGRP_GEN1_I2C_SDA_PC5, + PMUX_PINGRP_GEN1_I2C_SCL_PC4, + PMUX_PINGRP_DAP4_FS_PP4, + PMUX_PINGRP_DAP4_DIN_PP5, + PMUX_PINGRP_DAP4_DOUT_PP6, + PMUX_PINGRP_DAP4_SCLK_PP7, + PMUX_PINGRP_CLK3_OUT_PEE0, + PMUX_PINGRP_CLK3_REQ_PEE1, + PMUX_PINGRP_PC7, + PMUX_PINGRP_PI5, + PMUX_PINGRP_PI7, + PMUX_PINGRP_PK0, + PMUX_PINGRP_PK1, + PMUX_PINGRP_PJ0, + PMUX_PINGRP_PJ2, + PMUX_PINGRP_PK3, + PMUX_PINGRP_PK4, + PMUX_PINGRP_PK2, + PMUX_PINGRP_PI3, + PMUX_PINGRP_PI6, + PMUX_PINGRP_PG0, + PMUX_PINGRP_PG1, + PMUX_PINGRP_PG2, + PMUX_PINGRP_PG3, + PMUX_PINGRP_PG4, + PMUX_PINGRP_PG5, + PMUX_PINGRP_PG6, + PMUX_PINGRP_PG7, + PMUX_PINGRP_PH0, + PMUX_PINGRP_PH1, + PMUX_PINGRP_PH2, + PMUX_PINGRP_PH3, + PMUX_PINGRP_PH4, + PMUX_PINGRP_PH5, + PMUX_PINGRP_PH6, + PMUX_PINGRP_PH7, + PMUX_PINGRP_PJ7, + PMUX_PINGRP_PB0, + PMUX_PINGRP_PB1, + PMUX_PINGRP_PK7, + PMUX_PINGRP_PI0, + PMUX_PINGRP_PI1, + PMUX_PINGRP_PI2, + PMUX_PINGRP_PI4, + PMUX_PINGRP_GEN2_I2C_SCL_PT5, + PMUX_PINGRP_GEN2_I2C_SDA_PT6, + PMUX_PINGRP_SDMMC4_CLK_PCC4, + PMUX_PINGRP_SDMMC4_CMD_PT7, + PMUX_PINGRP_SDMMC4_DAT0_PAA0, + PMUX_PINGRP_SDMMC4_DAT1_PAA1, + PMUX_PINGRP_SDMMC4_DAT2_PAA2, + PMUX_PINGRP_SDMMC4_DAT3_PAA3, + PMUX_PINGRP_SDMMC4_DAT4_PAA4, + PMUX_PINGRP_SDMMC4_DAT5_PAA5, + PMUX_PINGRP_SDMMC4_DAT6_PAA6, + PMUX_PINGRP_SDMMC4_DAT7_PAA7, + PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4), + PMUX_PINGRP_PCC1, + PMUX_PINGRP_PBB0, + PMUX_PINGRP_CAM_I2C_SCL_PBB1, + PMUX_PINGRP_CAM_I2C_SDA_PBB2, + PMUX_PINGRP_PBB3, + PMUX_PINGRP_PBB4, + PMUX_PINGRP_PBB5, + PMUX_PINGRP_PBB6, + PMUX_PINGRP_PBB7, + PMUX_PINGRP_PCC2, + PMUX_PINGRP_JTAG_RTCK, + PMUX_PINGRP_PWR_I2C_SCL_PZ6, + PMUX_PINGRP_PWR_I2C_SDA_PZ7, + PMUX_PINGRP_KB_ROW0_PR0, + PMUX_PINGRP_KB_ROW1_PR1, + PMUX_PINGRP_KB_ROW2_PR2, + PMUX_PINGRP_KB_ROW3_PR3, + PMUX_PINGRP_KB_ROW4_PR4, + PMUX_PINGRP_KB_ROW5_PR5, + PMUX_PINGRP_KB_ROW6_PR6, + PMUX_PINGRP_KB_ROW7_PR7, + PMUX_PINGRP_KB_ROW8_PS0, + PMUX_PINGRP_KB_ROW9_PS1, + PMUX_PINGRP_KB_ROW10_PS2, + PMUX_PINGRP_KB_ROW11_PS3, + PMUX_PINGRP_KB_ROW12_PS4, + PMUX_PINGRP_KB_ROW13_PS5, + PMUX_PINGRP_KB_ROW14_PS6, + PMUX_PINGRP_KB_ROW15_PS7, + PMUX_PINGRP_KB_COL0_PQ0, + PMUX_PINGRP_KB_COL1_PQ1, + PMUX_PINGRP_KB_COL2_PQ2, + PMUX_PINGRP_KB_COL3_PQ3, + PMUX_PINGRP_KB_COL4_PQ4, + PMUX_PINGRP_KB_COL5_PQ5, + PMUX_PINGRP_KB_COL6_PQ6, + PMUX_PINGRP_KB_COL7_PQ7, + PMUX_PINGRP_CLK_32K_OUT_PA0, + PMUX_PINGRP_CORE_PWR_REQ = (0x324 / 4), + PMUX_PINGRP_CPU_PWR_REQ, + PMUX_PINGRP_PWR_INT_N, + PMUX_PINGRP_CLK_32K_IN, + PMUX_PINGRP_OWR, + PMUX_PINGRP_DAP1_FS_PN0, + PMUX_PINGRP_DAP1_DIN_PN1, + PMUX_PINGRP_DAP1_DOUT_PN2, + PMUX_PINGRP_DAP1_SCLK_PN3, + PMUX_PINGRP_DAP_MCLK1_REQ_PEE2, + PMUX_PINGRP_DAP_MCLK1_PW4, + PMUX_PINGRP_SPDIF_IN_PK6, + PMUX_PINGRP_SPDIF_OUT_PK5, + PMUX_PINGRP_DAP2_FS_PA2, + PMUX_PINGRP_DAP2_DIN_PA4, + PMUX_PINGRP_DAP2_DOUT_PA5, + PMUX_PINGRP_DAP2_SCLK_PA3, + PMUX_PINGRP_DVFS_PWM_PX0, + PMUX_PINGRP_GPIO_X1_AUD_PX1, + PMUX_PINGRP_GPIO_X3_AUD_PX3, + PMUX_PINGRP_DVFS_CLK_PX2, + PMUX_PINGRP_GPIO_X4_AUD_PX4, + PMUX_PINGRP_GPIO_X5_AUD_PX5, + PMUX_PINGRP_GPIO_X6_AUD_PX6, + PMUX_PINGRP_GPIO_X7_AUD_PX7, + PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4), + PMUX_PINGRP_SDMMC3_CMD_PA7, + PMUX_PINGRP_SDMMC3_DAT0_PB7, + PMUX_PINGRP_SDMMC3_DAT1_PB6, + PMUX_PINGRP_SDMMC3_DAT2_PB5, + PMUX_PINGRP_SDMMC3_DAT3_PB4, + PMUX_PINGRP_PEX_L0_RST_N_PDD1 = (0x3bc / 4), + PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2, + PMUX_PINGRP_PEX_WAKE_N_PDD3, + PMUX_PINGRP_PEX_L1_RST_N_PDD5 = (0x3cc / 4), + PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6, + PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4), + PMUX_PINGRP_SDMMC1_WP_N_PV3, + PMUX_PINGRP_SDMMC3_CD_N_PV2, + PMUX_PINGRP_GPIO_W2_AUD_PW2, + PMUX_PINGRP_GPIO_W3_AUD_PW3, + PMUX_PINGRP_USB_VBUS_EN0_PN4, + PMUX_PINGRP_USB_VBUS_EN1_PN5, + PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5, + PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4, + PMUX_PINGRP_GMI_CLK_LB, + PMUX_PINGRP_RESET_OUT_N, + PMUX_PINGRP_KB_ROW16_PT0, + PMUX_PINGRP_KB_ROW17_PT1, + PMUX_PINGRP_USB_VBUS_EN2_PFF1, + PMUX_PINGRP_PFF2, + PMUX_PINGRP_DP_HPD_PFF0 = (0x430 / 4), + PMUX_PINGRP_COUNT, +}; + +enum pmux_drvgrp { + PMUX_DRVGRP_AO1, + PMUX_DRVGRP_AO2, + PMUX_DRVGRP_AT1, + PMUX_DRVGRP_AT2, + PMUX_DRVGRP_AT3, + PMUX_DRVGRP_AT4, + PMUX_DRVGRP_AT5, + PMUX_DRVGRP_CDEV1, + PMUX_DRVGRP_CDEV2, + PMUX_DRVGRP_DAP1 = (0x28 / 4), + PMUX_DRVGRP_DAP2, + PMUX_DRVGRP_DAP3, + PMUX_DRVGRP_DAP4, + PMUX_DRVGRP_DBG, + PMUX_DRVGRP_SDIO3 = (0x48 / 4), + PMUX_DRVGRP_SPI, + PMUX_DRVGRP_UAA, + PMUX_DRVGRP_UAB, + PMUX_DRVGRP_UART2, + PMUX_DRVGRP_UART3, + PMUX_DRVGRP_SDIO1 = (0x84 / 4), + PMUX_DRVGRP_DDC = (0x94 / 4), + PMUX_DRVGRP_GMA, + PMUX_DRVGRP_GME = (0xa8 / 4), + PMUX_DRVGRP_GMF, + PMUX_DRVGRP_GMG, + PMUX_DRVGRP_GMH, + PMUX_DRVGRP_OWR, + PMUX_DRVGRP_UDA, + PMUX_DRVGRP_GPV, + PMUX_DRVGRP_DEV3, + PMUX_DRVGRP_CEC = (0xd0 / 4), + PMUX_DRVGRP_AT6 = (0x12c / 4), + PMUX_DRVGRP_DAP5, + PMUX_DRVGRP_USB_VBUS_EN, + PMUX_DRVGRP_AO3 = (0x140 / 4), + PMUX_DRVGRP_AO0 = (0x148 / 4), + PMUX_DRVGRP_HV0, + PMUX_DRVGRP_SDIO4 = (0x15c / 4), + PMUX_DRVGRP_AO4, + PMUX_DRVGRP_COUNT, +}; + +enum pmux_mipipadctrlgrp { + PMUX_MIPIPADCTRLGRP_DSI_B, + PMUX_MIPIPADCTRLGRP_COUNT, +}; + +enum pmux_func { + PMUX_FUNC_DEFAULT, + PMUX_FUNC_BLINK, + PMUX_FUNC_CCLA, + PMUX_FUNC_CEC, + PMUX_FUNC_CLDVFS, + PMUX_FUNC_CLK, + PMUX_FUNC_CLK12, + PMUX_FUNC_CPU, + PMUX_FUNC_CSI, + PMUX_FUNC_DAP, + PMUX_FUNC_DAP1, + PMUX_FUNC_DAP2, + PMUX_FUNC_DEV3, + PMUX_FUNC_DISPLAYA, + PMUX_FUNC_DISPLAYA_ALT, + PMUX_FUNC_DISPLAYB, + PMUX_FUNC_DP, + PMUX_FUNC_DSI_B, + PMUX_FUNC_DTV, + PMUX_FUNC_EXTPERIPH1, + PMUX_FUNC_EXTPERIPH2, + PMUX_FUNC_EXTPERIPH3, + PMUX_FUNC_GMI, + PMUX_FUNC_GMI_ALT, + PMUX_FUNC_HDA, + PMUX_FUNC_HSI, + PMUX_FUNC_I2C1, + PMUX_FUNC_I2C2, + PMUX_FUNC_I2C3, + PMUX_FUNC_I2C4, + PMUX_FUNC_I2CPWR, + PMUX_FUNC_I2S0, + PMUX_FUNC_I2S1, + PMUX_FUNC_I2S2, + PMUX_FUNC_I2S3, + PMUX_FUNC_I2S4, + PMUX_FUNC_IRDA, + PMUX_FUNC_KBC, + PMUX_FUNC_OWR, + PMUX_FUNC_PE, + PMUX_FUNC_PE0, + PMUX_FUNC_PE1, + PMUX_FUNC_PMI, + PMUX_FUNC_PWM0, + PMUX_FUNC_PWM1, + PMUX_FUNC_PWM2, + PMUX_FUNC_PWM3, + PMUX_FUNC_PWRON, + PMUX_FUNC_RESET_OUT_N, + PMUX_FUNC_RTCK, + PMUX_FUNC_SATA, + PMUX_FUNC_SDMMC1, + PMUX_FUNC_SDMMC2, + PMUX_FUNC_SDMMC3, + PMUX_FUNC_SDMMC4, + PMUX_FUNC_SOC, + PMUX_FUNC_SPDIF, + PMUX_FUNC_SPI1, + PMUX_FUNC_SPI2, + PMUX_FUNC_SPI3, + PMUX_FUNC_SPI4, + PMUX_FUNC_SPI5, + PMUX_FUNC_SPI6, + PMUX_FUNC_SYS, + PMUX_FUNC_TMDS, + PMUX_FUNC_TRACE, + PMUX_FUNC_UARTA, + PMUX_FUNC_UARTB, + PMUX_FUNC_UARTC, + PMUX_FUNC_UARTD, + PMUX_FUNC_ULPI, + PMUX_FUNC_USB, + PMUX_FUNC_VGP1, + PMUX_FUNC_VGP2, + PMUX_FUNC_VGP3, + PMUX_FUNC_VGP4, + PMUX_FUNC_VGP5, + PMUX_FUNC_VGP6, + PMUX_FUNC_VI, + PMUX_FUNC_VI_ALT1, + PMUX_FUNC_VI_ALT3, + PMUX_FUNC_VIMCLK2, + PMUX_FUNC_VIMCLK2_ALT, + PMUX_FUNC_RSVD1, + PMUX_FUNC_RSVD2, + PMUX_FUNC_RSVD3, + PMUX_FUNC_RSVD4, + PMUX_FUNC_COUNT, +}; + +#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 +#define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820 +#define TEGRA_PMX_SOC_HAS_IO_CLAMPING +#define TEGRA_PMX_SOC_HAS_DRVGRPS +#define TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS +#define TEGRA_PMX_GRPS_HAVE_LPMD +#define TEGRA_PMX_GRPS_HAVE_SCHMT +#define TEGRA_PMX_GRPS_HAVE_HSM +#define TEGRA_PMX_PINS_HAVE_E_INPUT +#define TEGRA_PMX_PINS_HAVE_LOCK +#define TEGRA_PMX_PINS_HAVE_OD +#define TEGRA_PMX_PINS_HAVE_IO_RESET +#define TEGRA_PMX_PINS_HAVE_RCV_SEL +#include + +#endif /* _TEGRA124_PINMUX_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra124/powergate.h b/roms/u-boot/arch/arm/include/asm/arch-tegra124/powergate.h new file mode 100644 index 000000000..8a0cfbaf9 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra124/powergate.h @@ -0,0 +1,6 @@ +#ifndef _TEGRA124_POWERGATE_H_ +#define _TEGRA124_POWERGATE_H_ + +#include + +#endif /* _TEGRA124_POWERGATE_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra124/pwm.h b/roms/u-boot/arch/arm/include/asm/arch-tegra124/pwm.h new file mode 100644 index 000000000..9ab23e8f2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra124/pwm.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Tegra pulse width frequency modulator definitions + * + * Copyright (c) 2011 The Chromium OS Authors. + */ + +#ifndef __ASM_ARCH_TEGRA124_PWM_H +#define __ASM_ARCH_TEGRA124_PWM_H + +#include + +#endif /* __ASM_ARCH_TEGRA124_PWM_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra124/sysctr.h b/roms/u-boot/arch/arm/include/asm/arch-tegra124/sysctr.h new file mode 100644 index 000000000..6567104d0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra124/sysctr.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + */ + +#ifndef _TEGRA124_SYSCTR_H_ +#define _TEGRA124_SYSCTR_H_ + +struct sysctr_ctlr { + u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ + u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ + u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ + u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ + u32 reserved1[4]; /* 0x10 - 0x1C */ + u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ + u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ + u32 reserved2[1002]; /* 0x28 - 0xFCC */ + u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ +}; + +#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ +#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ + +#endif /* _TEGRA124_SYSCTR_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra124/tegra.h b/roms/u-boot/arch/arm/include/asm/arch-tegra124/tegra.h new file mode 100644 index 000000000..34070b863 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra124/tegra.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + */ + +#ifndef _TEGRA124_H_ +#define _TEGRA124_H_ + +#define NV_PA_SDRAM_BASE 0x80000000 +#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ +#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */ +#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */ + +#include + +#define BCT_ODMDATA_OFFSET 1704 /* offset to ODMDATA word */ + +#undef NVBOOTINFOTABLE_BCTSIZE +#undef NVBOOTINFOTABLE_BCTPTR +#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ +#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ + +#define MAX_NUM_CPU 4 +#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) + +#define TEGRA_USB1_BASE 0x7D000000 + +#endif /* _TEGRA124_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra186/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-tegra186/gpio.h new file mode 100644 index 000000000..8b7e40975 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra186/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + */ + +#ifndef _TEGRA186_GPIO_H_ +#define _TEGRA186_GPIO_H_ + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra186/tegra.h b/roms/u-boot/arch/arm/include/asm/arch-tegra186/tegra.h new file mode 100644 index 000000000..d86cedbab --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra186/tegra.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2013-2016, NVIDIA CORPORATION. + */ + +#ifndef _TEGRA186_TEGRA_H_ +#define _TEGRA186_TEGRA_H_ + +#define GICD_BASE 0x03881000 /* Generic Int Cntrlr Distrib */ +#define GICC_BASE 0x03882000 /* Generic Int Cntrlr CPU I/F */ +#define NV_PA_SDRAM_BASE 0x80000000 + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra20/clock-tables.h b/roms/u-boot/arch/arm/include/asm/arch-tegra20/clock-tables.h new file mode 100644 index 000000000..861b3d5d0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra20/clock-tables.h @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2010-2012 NVIDIA Corporation + */ + +/* Tegra20 clock PLL tables */ + +#ifndef _CLOCK_TABLES_H_ +#define _CLOCK_TABLES_H_ + +/* The PLLs supported by the hardware */ +enum clock_id { + CLOCK_ID_FIRST, + CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, + CLOCK_ID_MEMORY, + CLOCK_ID_PERIPH, + CLOCK_ID_AUDIO, + CLOCK_ID_USB, + CLOCK_ID_DISPLAY, + + /* now the simple ones */ + CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_EPCI, + CLOCK_ID_SFROM32KHZ, + + /* These are the base clocks (inputs to the Tegra SOC) */ + CLOCK_ID_32KHZ, + CLOCK_ID_OSC, + CLOCK_ID_CLK_M, + + CLOCK_ID_COUNT, /* number of clocks */ + CLOCK_ID_NONE = -1, +}; + +/* The clocks supported by the hardware */ +enum periph_id { + PERIPH_ID_FIRST, + + /* Low word: 31:0 */ + PERIPH_ID_CPU = PERIPH_ID_FIRST, + PERIPH_ID_RESERVED1, + PERIPH_ID_RESERVED2, + PERIPH_ID_AC97, + PERIPH_ID_RTC, + PERIPH_ID_TMR, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + + /* 8 */ + PERIPH_ID_GPIO, + PERIPH_ID_SDMMC2, + PERIPH_ID_SPDIF, + PERIPH_ID_I2S1, + PERIPH_ID_I2C1, + PERIPH_ID_NDFLASH, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC4, + + /* 16 */ + PERIPH_ID_TWC, + PERIPH_ID_PWM, + PERIPH_ID_I2S2, + PERIPH_ID_EPP, + PERIPH_ID_VI, + PERIPH_ID_2D, + PERIPH_ID_USBD, + PERIPH_ID_ISP, + + /* 24 */ + PERIPH_ID_3D, + PERIPH_ID_IDE, + PERIPH_ID_DISP2, + PERIPH_ID_DISP1, + PERIPH_ID_HOST1X, + PERIPH_ID_VCP, + PERIPH_ID_RESERVED30, + PERIPH_ID_CACHE2, + + /* Middle word: 63:32 */ + PERIPH_ID_MEM, + PERIPH_ID_AHBDMA, + PERIPH_ID_APBDMA, + PERIPH_ID_RESERVED35, + PERIPH_ID_KBC, + PERIPH_ID_STAT_MON, + PERIPH_ID_PMC, + PERIPH_ID_FUSE, + + /* 40 */ + PERIPH_ID_KFUSE, + PERIPH_ID_SBC1, + PERIPH_ID_SNOR, + PERIPH_ID_SPI1, + PERIPH_ID_SBC2, + PERIPH_ID_XIO, + PERIPH_ID_SBC3, + PERIPH_ID_DVC_I2C, + + /* 48 */ + PERIPH_ID_DSI, + PERIPH_ID_TVO, + PERIPH_ID_MIPI, + PERIPH_ID_HDMI, + PERIPH_ID_CSI, + PERIPH_ID_TVDAC, + PERIPH_ID_I2C2, + PERIPH_ID_UART3, + + /* 56 */ + PERIPH_ID_RESERVED56, + PERIPH_ID_EMC, + PERIPH_ID_USB2, + PERIPH_ID_USB3, + PERIPH_ID_MPE, + PERIPH_ID_VDE, + PERIPH_ID_BSEA, + PERIPH_ID_BSEV, + + /* Upper word 95:64 */ + PERIPH_ID_SPEEDO, + PERIPH_ID_UART4, + PERIPH_ID_UART5, + PERIPH_ID_I2C3, + PERIPH_ID_SBC4, + PERIPH_ID_SDMMC3, + PERIPH_ID_PCIE, + PERIPH_ID_OWR, + + /* 72 */ + PERIPH_ID_AFI, + PERIPH_ID_CORESIGHT, + PERIPH_ID_PCIEXCLK, + PERIPH_ID_AVPUCQ, + PERIPH_ID_RESERVED76, + PERIPH_ID_RESERVED77, + PERIPH_ID_RESERVED78, + PERIPH_ID_RESERVED79, + + /* 80 */ + PERIPH_ID_RESERVED80, + PERIPH_ID_RESERVED81, + PERIPH_ID_RESERVED82, + PERIPH_ID_RESERVED83, + PERIPH_ID_IRAMA, + PERIPH_ID_IRAMB, + PERIPH_ID_IRAMC, + PERIPH_ID_IRAMD, + + /* 88 */ + PERIPH_ID_CRAM2, + PERIPH_ID_SYNC_CLK_DOUBLER, + PERIPH_ID_CLK_M_DOUBLER, + PERIPH_ID_RESERVED91, + PERIPH_ID_SUS_OUT, + PERIPH_ID_DEV2_OUT, + PERIPH_ID_DEV1_OUT, + + PERIPH_ID_COUNT, + PERIPH_ID_NONE = -1, +}; + +enum pll_out_id { + PLL_OUT1, + PLL_OUT2, + PLL_OUT3, + PLL_OUT4 +}; + +/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */ +#define PERIPH_REG(id) ((id) >> 5) + +/* Mask value for a clock (within PERIPH_REG(id)) */ +#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) + +/* return 1 if a PLL ID is in range, and not a simple PLL */ +#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \ + (id) < CLOCK_ID_FIRST_SIMPLE) + +/* return 1 if a peripheral ID is in range */ +#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ + (id) < PERIPH_ID_COUNT) + +#endif /* _CLOCK_TABLES_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra20/clock.h b/roms/u-boot/arch/arm/include/asm/arch-tegra20/clock.h new file mode 100644 index 000000000..8158b8344 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra20/clock.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + */ + +/* Tegra20 clock control functions */ + +#ifndef _TEGRA20_CLOCK_H +#define _TEGRA20_CLOCK_H + +#include + +/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ +#define OSC_FREQ_SHIFT 30 +#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT) + +int tegra_plle_enable(void); + +#endif /* _TEGRA20_CLOCK_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra20/display.h b/roms/u-boot/arch/arm/include/asm/arch-tegra20/display.h new file mode 100644 index 000000000..e7b3cffd4 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra20/display.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * NVIDIA Corporation + */ + +#ifndef __ASM_ARCH_TEGRA_DISPLAY_H +#define __ASM_ARCH_TEGRA_DISPLAY_H + +#include + +/* This holds information about a window which can be displayed */ +struct disp_ctl_win { + enum win_color_depth_id fmt; /* Color depth/format */ + unsigned bpp; /* Bits per pixel */ + phys_addr_t phys_addr; /* Physical address in memory */ + unsigned x; /* Horizontal address offset (bytes) */ + unsigned y; /* Veritical address offset (bytes) */ + unsigned w; /* Width of source window */ + unsigned h; /* Height of source window */ + unsigned stride; /* Number of bytes per line */ + unsigned out_x; /* Left edge of output window (col) */ + unsigned out_y; /* Top edge of output window (row) */ + unsigned out_w; /* Width of output window in pixels */ + unsigned out_h; /* Height of output window in pixels */ +}; + +#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra20/emc.h b/roms/u-boot/arch/arm/include/asm/arch-tegra20/emc.h new file mode 100644 index 000000000..58ee08c9f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra20/emc.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010,2011 NVIDIA Corporation + */ + +#ifndef _ARCH_EMC_H_ +#define _ARCH_EMC_H_ + +#include + +#define TEGRA_EMC_NUM_REGS 46 + +/* EMC Registers */ +struct emc_ctlr { + u32 cfg; /* 0x00: EMC_CFG */ + u32 reserved0[3]; /* 0x04 ~ 0x0C */ + u32 adr_cfg; /* 0x10: EMC_ADR_CFG */ + u32 adr_cfg1; /* 0x14: EMC_ADR_CFG_1 */ + u32 reserved1[2]; /* 0x18 ~ 0x18 */ + u32 refresh_ctrl; /* 0x20: EMC_REFCTRL */ + u32 pin; /* 0x24: EMC_PIN */ + u32 timing_ctrl; /* 0x28: EMC_TIMING_CONTROL */ + u32 rc; /* 0x2C: EMC_RC */ + u32 rfc; /* 0x30: EMC_RFC */ + u32 ras; /* 0x34: EMC_RAS */ + u32 rp; /* 0x38: EMC_RP */ + u32 r2w; /* 0x3C: EMC_R2W */ + u32 w2r; /* 0x40: EMC_W2R */ + u32 r2p; /* 0x44: EMC_R2P */ + u32 w2p; /* 0x48: EMC_W2P */ + u32 rd_rcd; /* 0x4C: EMC_RD_RCD */ + u32 wd_rcd; /* 0x50: EMC_WD_RCD */ + u32 rrd; /* 0x54: EMC_RRD */ + u32 rext; /* 0x58: EMC_REXT */ + u32 wdv; /* 0x5C: EMC_WDV */ + u32 quse; /* 0x60: EMC_QUSE */ + u32 qrst; /* 0x64: EMC_QRST */ + u32 qsafe; /* 0x68: EMC_QSAFE */ + u32 rdv; /* 0x6C: EMC_RDV */ + u32 refresh; /* 0x70: EMC_REFRESH */ + u32 burst_refresh_num; /* 0x74: EMC_BURST_REFRESH_NUM */ + u32 pdex2wr; /* 0x78: EMC_PDEX2WR */ + u32 pdex2rd; /* 0x7c: EMC_PDEX2RD */ + u32 pchg2pden; /* 0x80: EMC_PCHG2PDEN */ + u32 act2pden; /* 0x84: EMC_ACT2PDEN */ + u32 ar2pden; /* 0x88: EMC_AR2PDEN */ + u32 rw2pden; /* 0x8C: EMC_RW2PDEN */ + u32 txsr; /* 0x90: EMC_TXSR */ + u32 tcke; /* 0x94: EMC_TCKE */ + u32 tfaw; /* 0x98: EMC_TFAW */ + u32 trpab; /* 0x9C: EMC_TRPAB */ + u32 tclkstable; /* 0xA0: EMC_TCLKSTABLE */ + u32 tclkstop; /* 0xA4: EMC_TCLKSTOP */ + u32 trefbw; /* 0xA8: EMC_TREFBW */ + u32 quse_extra; /* 0xAC: EMC_QUSE_EXTRA */ + u32 odt_write; /* 0xB0: EMC_ODT_WRITE */ + u32 odt_read; /* 0xB4: EMC_ODT_READ */ + u32 reserved2[5]; /* 0xB8 ~ 0xC8 */ + u32 mrs; /* 0xCC: EMC_MRS */ + u32 emrs; /* 0xD0: EMC_EMRS */ + u32 ref; /* 0xD4: EMC_REF */ + u32 pre; /* 0xD8: EMC_PRE */ + u32 nop; /* 0xDC: EMC_NOP */ + u32 self_ref; /* 0xE0: EMC_SELF_REF */ + u32 dpd; /* 0xE4: EMC_DPD */ + u32 mrw; /* 0xE8: EMC_MRW */ + u32 mrr; /* 0xEC: EMC_MRR */ + u32 reserved3; /* 0xF0: */ + u32 fbio_cfg1; /* 0xF4: EMC_FBIO_CFG1 */ + u32 fbio_dqsib_dly; /* 0xF8: EMC_FBIO_DQSIB_DLY */ + u32 fbio_dqsib_dly_msb; /* 0xFC: EMC_FBIO_DQSIB_DLY_MSG */ + u32 fbio_spare; /* 0x100: SBIO_SPARE */ + /* There are more registers ... */ +}; + +/** + * Set up the EMC for the given rate. The timing parameters are retrieved + * from the device tree "nvidia,tegra20-emc" node and its + * "nvidia,tegra20-emc-table" sub-nodes. + * + * @param blob Device tree blob + * @param rate Clock speed of memory controller in Hz (=2x memory bus rate) + * @return 0 if ok, else -ve error code (look in emc.c to decode it) + */ +int tegra_set_emc(const void *blob, unsigned rate); + +/** + * Get a pointer to the EMC controller from the device tree. + * + * @param blob Device tree blob + * @return pointer to EMC controller + */ +struct emc_ctlr *emc_get_controller(const void *blob); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra20/flow.h b/roms/u-boot/arch/arm/include/asm/arch-tegra20/flow.h new file mode 100644 index 000000000..33be841dd --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra20/flow.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010, 2011 + * NVIDIA Corporation + */ + +#ifndef _FLOW_H_ +#define _FLOW_H_ + +struct flow_ctlr { + u32 halt_cpu_events; + u32 halt_cop_events; + u32 cpu_csr; + u32 cop_csr; + u32 halt_cpu1_events; + u32 cpu1_csr; +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra20/funcmux.h b/roms/u-boot/arch/arm/include/asm/arch-tegra20/funcmux.h new file mode 100644 index 000000000..e9e96c1f9 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra20/funcmux.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + */ + +/* Tegra20 high-level function multiplexing */ + +#ifndef _TEGRA20_FUNCMUX_H_ +#define _TEGRA20_FUNCMUX_H_ + +#include + +/* Configs supported by the func mux */ +enum { + FUNCMUX_DEFAULT = 0, /* default config */ + + /* UART configs */ + FUNCMUX_UART1_IRRX_IRTX = 0, + FUNCMUX_UART1_UAA_UAB, + FUNCMUX_UART1_GPU, + FUNCMUX_UART1_SDIO1, + FUNCMUX_UART2_UAD = 0, + FUNCMUX_UART4_GMC = 0, + + /* I2C configs */ + FUNCMUX_DVC_I2CP = 0, + FUNCMUX_I2C1_RM = 0, + FUNCMUX_I2C2_DDC = 0, + FUNCMUX_I2C2_PTA, + FUNCMUX_I2C3_DTF = 0, + + /* SDMMC configs */ + FUNCMUX_SDMMC1_SDIO1_4BIT = 0, + FUNCMUX_SDMMC2_DTA_DTD_8BIT = 0, + FUNCMUX_SDMMC3_SDB_4BIT = 0, + FUNCMUX_SDMMC3_SDB_SLXA_8BIT, + FUNCMUX_SDMMC4_ATC_ATD_8BIT = 0, + FUNCMUX_SDMMC4_ATB_GMA_4_BIT, + FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT, + + /* USB configs */ + FUNCMUX_USB2_ULPI = 0, + + /* Serial Flash configs */ + FUNCMUX_SPI1_GMC_GMD = 0, + + /* NAND flags */ + FUNCMUX_NDFLASH_ATC = 0, + FUNCMUX_NDFLASH_KBC_8_BIT, +}; +#endif /* _TEGRA20_FUNCMUX_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra20/gp_padctrl.h b/roms/u-boot/arch/arm/include/asm/arch-tegra20/gp_padctrl.h new file mode 100644 index 000000000..dd2ee1265 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra20/gp_padctrl.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + */ + +#ifndef _TEGRA20_GP_PADCTRL_H_ +#define _TEGRA20_GP_PADCTRL_H_ + +#include + +/* APB_MISC_GP and padctrl registers */ +struct apb_misc_gp_ctlr { + u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ + u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ + u32 reserved0[22]; /* 0x08 - 0x5C: */ + u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ + u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ + u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ + u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ + u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ + u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ + u32 cdevcfg1; /* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */ + u32 cdevcfg2; /* 0x7C: APB_MISC_GP_CDEV2CFGPADCTRL */ + u32 csuscfg; /* 0x80: APB_MISC_GP_CSUSCFGPADCTRL */ + u32 dap1cfg; /* 0x84: APB_MISC_GP_DAP1CFGPADCTRL */ + u32 dap2cfg; /* 0x88: APB_MISC_GP_DAP2CFGPADCTRL */ + u32 dap3cfg; /* 0x8C: APB_MISC_GP_DAP3CFGPADCTRL */ + u32 dap4cfg; /* 0x90: APB_MISC_GP_DAP4CFGPADCTRL */ + u32 dbgcfg; /* 0x94: APB_MISC_GP_DBGCFGPADCTRL */ + u32 lcdcfg1; /* 0x98: APB_MISC_GP_LCDCFG1PADCTRL */ + u32 lcdcfg2; /* 0x9C: APB_MISC_GP_LCDCFG2PADCTRL */ + u32 sdmmc2_cfg; /* 0xA0: APB_MISC_GP_SDMMC2CFGPADCTRL */ + u32 sdmmc3_cfg; /* 0xA4: APB_MISC_GP_SDMMC3CFGPADCTRL */ + u32 spicfg; /* 0xA8: APB_MISC_GP_SPICFGPADCTRL */ + u32 uaacfg; /* 0xAC: APB_MISC_GP_UAACFGPADCTRL */ + u32 uabcfg; /* 0xB0: APB_MISC_GP_UABCFGPADCTRL */ + u32 uart2cfg; /* 0xB4: APB_MISC_GP_UART2CFGPADCTRL */ + u32 uart3cfg; /* 0xB8: APB_MISC_GP_UART3CFGPADCTRL */ + u32 vicfg1; /* 0xBC: APB_MISC_GP_VICFG1PADCTRL */ + u32 vicfg2; /* 0xC0: APB_MISC_GP_VICFG2PADCTRL */ + u32 xm2cfga; /* 0xC4: APB_MISC_GP_XM2CFGAPADCTRL */ + u32 xm2cfgc; /* 0xC8: APB_MISC_GP_XM2CFGCPADCTRL */ + u32 xm2cfgd; /* 0xCC: APB_MISC_GP_XM2CFGDPADCTRL */ + u32 xm2clkcfg; /* 0xD0: APB_MISC_GP_XM2CLKCFGPADCTRL */ + u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */ +}; + +#endif /* _TEGRA20_GP_PADCTRL_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra20/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-tegra20/gpio.h new file mode 100644 index 000000000..6818c2872 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra20/gpio.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011, Google Inc. All rights reserved. + * Portions Copyright 2011-2012 NVIDIA Corporation + */ + +#ifndef _TEGRA20_GPIO_H_ +#define _TEGRA20_GPIO_H_ + +/* + * The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports, + * each with 8 GPIOs. + */ +#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ +#define TEGRA_GPIO_BANKS 7 /* number of banks */ + +#include + +/* GPIO Controller registers for a single bank */ +struct gpio_ctlr_bank { + uint gpio_config[TEGRA_GPIO_PORTS]; + uint gpio_dir_out[TEGRA_GPIO_PORTS]; + uint gpio_out[TEGRA_GPIO_PORTS]; + uint gpio_in[TEGRA_GPIO_PORTS]; + uint gpio_int_status[TEGRA_GPIO_PORTS]; + uint gpio_int_enable[TEGRA_GPIO_PORTS]; + uint gpio_int_level[TEGRA_GPIO_PORTS]; + uint gpio_int_clear[TEGRA_GPIO_PORTS]; +}; + +struct gpio_ctlr { + struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; +}; + +#endif /* TEGRA20_GPIO_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra20/mc.h b/roms/u-boot/arch/arm/include/asm/arch-tegra20/mc.h new file mode 100644 index 000000000..71283e4e2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra20/mc.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2014 + * NVIDIA Corporation + */ + +#ifndef _TEGRA20_MC_H_ +#define _TEGRA20_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[3]; /* offset 0x00 - 0x08 */ + u32 mc_emem_cfg; /* offset 0x0C */ + u32 mc_emem_adr_cfg; /* offset 0x10 */ + u32 mc_emem_arb_cfg0; /* offset 0x14 */ + u32 mc_emem_arb_cfg1; /* offset 0x18 */ + u32 mc_emem_arb_cfg2; /* offset 0x1C */ + u32 reserved1; /* offset 0x20 */ + u32 mc_gart_cfg; /* offset 0x24 */ + u32 mc_gart_entry_addr; /* offset 0x28 */ + u32 mc_gart_entry_data; /* offset 0x2C */ + u32 mc_gart_error_req; /* offset 0x30 */ + u32 mc_gart_error_addr; /* offset 0x34 */ + u32 reserved2; /* offset 0x38 */ + u32 mc_timeout_ctrl; /* offset 0x3C */ + u32 reserved3[6]; /* offset 0x40 - 0x54 */ + u32 mc_decerr_emem_others_status; /* offset 0x58 */ + u32 mc_decerr_emem_others_adr; /* offset 0x5C */ + u32 reserved4[40]; /* offset 0x60 - 0xFC */ + u32 reserved5[93]; /* offset 0x100 - 0x270 */ +}; + +#endif /* _TEGRA20_MC_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra20/pinmux.h b/roms/u-boot/arch/arm/include/asm/arch-tegra20/pinmux.h new file mode 100644 index 000000000..e9e3801e6 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra20/pinmux.h @@ -0,0 +1,238 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + */ + +#ifndef _TEGRA20_PINMUX_H_ +#define _TEGRA20_PINMUX_H_ + +/* + * Pin groups which we adjust. There are three basic attributes of each pin + * group which use this enum: + * + * - function + * - pullup / pulldown + * - tristate or normal + */ +enum pmux_pingrp { + /* APB_MISC_PP_TRISTATE_REG_A_0 */ + PMUX_PINGRP_ATA, + PMUX_PINGRP_ATB, + PMUX_PINGRP_ATC, + PMUX_PINGRP_ATD, + PMUX_PINGRP_CDEV1, + PMUX_PINGRP_CDEV2, + PMUX_PINGRP_CSUS, + PMUX_PINGRP_DAP1, + + PMUX_PINGRP_DAP2, + PMUX_PINGRP_DAP3, + PMUX_PINGRP_DAP4, + PMUX_PINGRP_DTA, + PMUX_PINGRP_DTB, + PMUX_PINGRP_DTC, + PMUX_PINGRP_DTD, + PMUX_PINGRP_DTE, + + PMUX_PINGRP_GPU, + PMUX_PINGRP_GPV, + PMUX_PINGRP_I2CP, + PMUX_PINGRP_IRTX, + PMUX_PINGRP_IRRX, + PMUX_PINGRP_KBCB, + PMUX_PINGRP_KBCA, + PMUX_PINGRP_PMC, + + PMUX_PINGRP_PTA, + PMUX_PINGRP_RM, + PMUX_PINGRP_KBCE, + PMUX_PINGRP_KBCF, + PMUX_PINGRP_GMA, + PMUX_PINGRP_GMC, + PMUX_PINGRP_SDIO1, + PMUX_PINGRP_OWC, + + /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */ + PMUX_PINGRP_GME, + PMUX_PINGRP_SDC, + PMUX_PINGRP_SDD, + PMUX_PINGRP_RESERVED0, + PMUX_PINGRP_SLXA, + PMUX_PINGRP_SLXC, + PMUX_PINGRP_SLXD, + PMUX_PINGRP_SLXK, + + PMUX_PINGRP_SPDI, + PMUX_PINGRP_SPDO, + PMUX_PINGRP_SPIA, + PMUX_PINGRP_SPIB, + PMUX_PINGRP_SPIC, + PMUX_PINGRP_SPID, + PMUX_PINGRP_SPIE, + PMUX_PINGRP_SPIF, + + PMUX_PINGRP_SPIG, + PMUX_PINGRP_SPIH, + PMUX_PINGRP_UAA, + PMUX_PINGRP_UAB, + PMUX_PINGRP_UAC, + PMUX_PINGRP_UAD, + PMUX_PINGRP_UCA, + PMUX_PINGRP_UCB, + + PMUX_PINGRP_RESERVED1, + PMUX_PINGRP_ATE, + PMUX_PINGRP_KBCC, + PMUX_PINGRP_RESERVED2, + PMUX_PINGRP_RESERVED3, + PMUX_PINGRP_GMB, + PMUX_PINGRP_GMD, + PMUX_PINGRP_DDC, + + /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */ + PMUX_PINGRP_LD0, + PMUX_PINGRP_LD1, + PMUX_PINGRP_LD2, + PMUX_PINGRP_LD3, + PMUX_PINGRP_LD4, + PMUX_PINGRP_LD5, + PMUX_PINGRP_LD6, + PMUX_PINGRP_LD7, + + PMUX_PINGRP_LD8, + PMUX_PINGRP_LD9, + PMUX_PINGRP_LD10, + PMUX_PINGRP_LD11, + PMUX_PINGRP_LD12, + PMUX_PINGRP_LD13, + PMUX_PINGRP_LD14, + PMUX_PINGRP_LD15, + + PMUX_PINGRP_LD16, + PMUX_PINGRP_LD17, + PMUX_PINGRP_LHP0, + PMUX_PINGRP_LHP1, + PMUX_PINGRP_LHP2, + PMUX_PINGRP_LVP0, + PMUX_PINGRP_LVP1, + PMUX_PINGRP_HDINT, + + PMUX_PINGRP_LM0, + PMUX_PINGRP_LM1, + PMUX_PINGRP_LVS, + PMUX_PINGRP_LSC0, + PMUX_PINGRP_LSC1, + PMUX_PINGRP_LSCK, + PMUX_PINGRP_LDC, + PMUX_PINGRP_LCSN, + + /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */ + PMUX_PINGRP_LSPI, + PMUX_PINGRP_LSDA, + PMUX_PINGRP_LSDI, + PMUX_PINGRP_LPW0, + PMUX_PINGRP_LPW1, + PMUX_PINGRP_LPW2, + PMUX_PINGRP_LDI, + PMUX_PINGRP_LHS, + + PMUX_PINGRP_LPP, + PMUX_PINGRP_RESERVED4, + PMUX_PINGRP_KBCD, + PMUX_PINGRP_GPU7, + PMUX_PINGRP_DTF, + PMUX_PINGRP_UDA, + PMUX_PINGRP_CRTP, + PMUX_PINGRP_SDB, + + /* these pin groups only have pullup and pull down control */ + PMUX_PINGRP_CK32, + PMUX_PINGRP_DDRC, + PMUX_PINGRP_PMCA, + PMUX_PINGRP_PMCB, + PMUX_PINGRP_PMCC, + PMUX_PINGRP_PMCD, + PMUX_PINGRP_PMCE, + PMUX_PINGRP_XM2C, + PMUX_PINGRP_XM2D, + PMUX_PINGRP_COUNT, +}; + +/* + * Functions which can be assigned to each of the pin groups. The values here + * bear no relation to the values programmed into pinmux registers and are + * purely a convenience. The translation is done through a table search. + */ +enum pmux_func { + PMUX_FUNC_DEFAULT, + PMUX_FUNC_AHB_CLK, + PMUX_FUNC_APB_CLK, + PMUX_FUNC_AUDIO_SYNC, + PMUX_FUNC_CRT, + PMUX_FUNC_DAP1, + PMUX_FUNC_DAP2, + PMUX_FUNC_DAP3, + PMUX_FUNC_DAP4, + PMUX_FUNC_DAP5, + PMUX_FUNC_DISPA, + PMUX_FUNC_DISPB, + PMUX_FUNC_EMC_TEST0_DLL, + PMUX_FUNC_EMC_TEST1_DLL, + PMUX_FUNC_GMI, + PMUX_FUNC_GMI_INT, + PMUX_FUNC_HDMI, + PMUX_FUNC_I2C, + PMUX_FUNC_I2C2, + PMUX_FUNC_I2C3, + PMUX_FUNC_IDE, + PMUX_FUNC_KBC, + PMUX_FUNC_MIO, + PMUX_FUNC_MIPI_HS, + PMUX_FUNC_NAND, + PMUX_FUNC_OSC, + PMUX_FUNC_OWR, + PMUX_FUNC_PCIE, + PMUX_FUNC_PLLA_OUT, + PMUX_FUNC_PLLC_OUT1, + PMUX_FUNC_PLLM_OUT1, + PMUX_FUNC_PLLP_OUT2, + PMUX_FUNC_PLLP_OUT3, + PMUX_FUNC_PLLP_OUT4, + PMUX_FUNC_PWM, + PMUX_FUNC_PWR_INTR, + PMUX_FUNC_PWR_ON, + PMUX_FUNC_RTCK, + PMUX_FUNC_SDIO1, + PMUX_FUNC_SDIO2, + PMUX_FUNC_SDIO3, + PMUX_FUNC_SDIO4, + PMUX_FUNC_SFLASH, + PMUX_FUNC_SPDIF, + PMUX_FUNC_SPI1, + PMUX_FUNC_SPI2, + PMUX_FUNC_SPI2_ALT, + PMUX_FUNC_SPI3, + PMUX_FUNC_SPI4, + PMUX_FUNC_TRACE, + PMUX_FUNC_TWC, + PMUX_FUNC_UARTA, + PMUX_FUNC_UARTB, + PMUX_FUNC_UARTC, + PMUX_FUNC_UARTD, + PMUX_FUNC_UARTE, + PMUX_FUNC_ULPI, + PMUX_FUNC_VI, + PMUX_FUNC_VI_SENSOR_CLK, + PMUX_FUNC_XIO, + PMUX_FUNC_RSVD1, + PMUX_FUNC_RSVD2, + PMUX_FUNC_RSVD3, + PMUX_FUNC_RSVD4, + PMUX_FUNC_COUNT, +}; + +#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 +#include + +#endif /* _TEGRA20_PINMUX_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra20/powergate.h b/roms/u-boot/arch/arm/include/asm/arch-tegra20/powergate.h new file mode 100644 index 000000000..439d88b70 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra20/powergate.h @@ -0,0 +1,6 @@ +#ifndef _TEGRA20_POWERGATE_H_ +#define _TEGRA20_POWERGATE_H_ + +#include + +#endif /* _TEGRA20_POWERGATE_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra20/pwm.h b/roms/u-boot/arch/arm/include/asm/arch-tegra20/pwm.h new file mode 100644 index 000000000..9467617b5 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra20/pwm.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Tegra pulse width frequency modulator definitions + * + * Copyright (c) 2011 The Chromium OS Authors. + */ + +#ifndef __ASM_ARCH_TEGRA20_PWM_H +#define __ASM_ARCH_TEGRA20_PWM_H + +#include + +#endif /* __ASM_ARCH_TEGRA20_PWM_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra20/sdram_param.h b/roms/u-boot/arch/arm/include/asm/arch-tegra20/sdram_param.h new file mode 100644 index 000000000..3d1405fa3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra20/sdram_param.h @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010, 2011 + * NVIDIA Corporation + */ + +#ifndef _SDRAM_PARAM_H_ +#define _SDRAM_PARAM_H_ + +/* + * Defines the number of 32-bit words provided in each set of SDRAM parameters + * for arbitration configuration data. + */ +#define BCT_SDRAM_ARB_CONFIG_WORDS 27 + +enum memory_type { + MEMORY_TYPE_NONE = 0, + MEMORY_TYPE_DDR, + MEMORY_TYPE_LPDDR, + MEMORY_TYPE_DDR2, + MEMORY_TYPE_LPDDR2, + MEMORY_TYPE_NUM, + MEMORY_TYPE_FORCE32 = 0x7FFFFFFF +}; + +/* Defines the SDRAM parameter structure */ +struct sdram_params { + enum memory_type memory_type; + u32 pllm_charge_pump_setup_control; + u32 pllm_loop_filter_setup_control; + u32 pllm_input_divider; + u32 pllm_feedback_divider; + u32 pllm_post_divider; + u32 pllm_stable_time; + u32 emc_clock_divider; + u32 emc_auto_cal_interval; + u32 emc_auto_cal_config; + u32 emc_auto_cal_wait; + u32 emc_pin_program_wait; + u32 emc_rc; + u32 emc_rfc; + u32 emc_ras; + u32 emc_rp; + u32 emc_r2w; + u32 emc_w2r; + u32 emc_r2p; + u32 emc_w2p; + u32 emc_rd_rcd; + u32 emc_wr_rcd; + u32 emc_rrd; + u32 emc_rext; + u32 emc_wdv; + u32 emc_quse; + u32 emc_qrst; + u32 emc_qsafe; + u32 emc_rdv; + u32 emc_refresh; + u32 emc_burst_refresh_num; + u32 emc_pdex2wr; + u32 emc_pdex2rd; + u32 emc_pchg2pden; + u32 emc_act2pden; + u32 emc_ar2pden; + u32 emc_rw2pden; + u32 emc_txsr; + u32 emc_tcke; + u32 emc_tfaw; + u32 emc_trpab; + u32 emc_tclkstable; + u32 emc_tclkstop; + u32 emc_trefbw; + u32 emc_quseextra; + u32 emc_fbioc_fg1; + u32 emc_fbio_dqsib_dly; + u32 emc_fbio_dqsib_dly_msb; + u32 emc_fbio_quse_dly; + u32 emc_fbio_quse_dly_msb; + u32 emc_fbio_cfg5; + u32 emc_fbio_cfg6; + u32 emc_fbio_spare; + u32 emc_mrs; + u32 emc_emrs; + u32 emc_mrw1; + u32 emc_mrw2; + u32 emc_mrw3; + u32 emc_mrw_reset_command; + u32 emc_mrw_reset_init_wait; + u32 emc_adr_cfg; + u32 emc_adr_cfg1; + u32 emc_emem_cfg; + u32 emc_low_latency_config; + u32 emc_cfg; + u32 emc_cfg2; + u32 emc_dbg; + u32 ahb_arbitration_xbar_ctrl; + u32 emc_cfg_dig_dll; + u32 emc_dll_xform_dqs; + u32 emc_dll_xform_quse; + u32 warm_boot_wait; + u32 emc_ctt_term_ctrl; + u32 emc_odt_write; + u32 emc_odt_read; + u32 emc_zcal_ref_cnt; + u32 emc_zcal_wait_cnt; + u32 emc_zcal_mrw_cmd; + u32 emc_mrs_reset_dll; + u32 emc_mrw_zq_init_dev0; + u32 emc_mrw_zq_init_dev1; + u32 emc_mrw_zq_init_wait; + u32 emc_mrs_reset_dll_wait; + u32 emc_emrs_emr2; + u32 emc_emrs_emr3; + u32 emc_emrs_ddr2_dll_enable; + u32 emc_mrs_ddr2_dll_reset; + u32 emc_emrs_ddr2_ocd_calib; + u32 emc_edr2_wait; + u32 emc_cfg_clktrim0; + u32 emc_cfg_clktrim1; + u32 emc_cfg_clktrim2; + u32 pmc_ddr_pwr; + u32 apb_misc_gp_xm2cfga_padctrl; + u32 apb_misc_gp_xm2cfgc_padctrl; + u32 apb_misc_gp_xm2cfgc_padctrl2; + u32 apb_misc_gp_xm2cfgd_padctrl; + u32 apb_misc_gp_xm2cfgd_padctrl2; + u32 apb_misc_gp_xm2clkcfg_padctrl; + u32 apb_misc_gp_xm2comp_padctrl; + u32 apb_misc_gp_xm2vttgen_padctrl; + u32 arbitration_config[BCT_SDRAM_ARB_CONFIG_WORDS]; +}; +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra.h b/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra.h new file mode 100644 index 000000000..3fecbcdb6 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + */ + +#ifndef _TEGRA20_H_ +#define _TEGRA20_H_ + +#define NV_PA_SDRAM_BASE 0x00000000 +#define NV_PA_MC_BASE 0x7000F000 + +#include + +#define TEGRA_USB1_BASE 0xC5000000 + +#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */ + +#define MAX_NUM_CPU 2 + +#endif /* TEGRA20_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra210/ahb.h b/roms/u-boot/arch/arm/include/asm/arch-tegra210/ahb.h new file mode 100644 index 000000000..8ecd6d9ba --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra210/ahb.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation + */ + +#ifndef _TEGRA210_AHB_H_ +#define _TEGRA210_AHB_H_ + +struct ahb_ctlr { + u32 reserved0; /* 00h */ + u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */ + u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */ + u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */ + u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */ + u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */ + u32 reserved6[2]; /* 18h, 1ch */ + u32 gizmo_usb; /* _GIZMO_USB_0, 20h */ + u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */ + u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */ + u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */ + u32 gizmo_xbar_apb_ctlr; /* _GIZMO_XBAR_APB_CTLR_0, 30h */ + u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */ + u32 reserved13[2]; /* 38h, 3ch */ + u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */ + u32 reserved15; /* 44h */ + u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */ + u32 reserved17; /* 4ch */ + u32 gizmo_se; /* _GIZMO_SE_0, 50h */ + u32 gizmo_tzram; /* _GIZMO_TZRAM_0, 54h */ + u32 reserved20[3]; /* 58h, 5ch, 60h */ + u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */ + u32 reserved22[3]; /* 68h, 6ch, 70h */ + u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */ + u32 gizmo_nor; /* _GIZMO_NOR_0, 78h */ + u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */ + u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */ + u32 gizmo_sdmmc1; /* _GIZMO_SDMMC1_0, 84h */ + u32 gizmo_sdmmc2; /* _GIZMO_SDMMC2_0, 88h */ + u32 gizmo_sdmmc3; /* _GIZMO_SDMMC3_0, 8ch */ + u32 reserved30[13]; /* 90h ~ c0h */ + u32 ahb_wrq_empty; /* _AHB_WRQ_EMPTY_0, c4h */ + u32 reserved32[5]; /* c8h ~ d8h */ + u32 ahb_mem_prefetch_cfg_x; /* _AHB_MEM_PREFETCH_CFG_X_0, dch */ + u32 arbitration_xbar_ctrl; /* _ARBITRATION_XBAR_CTRL_0, e0h */ + u32 ahb_mem_prefetch_cfg3; /* _AHB_MEM_PREFETCH_CFG3_0, e4h */ + u32 ahb_mem_prefetch_cfg4; /* _AHB_MEM_PREFETCH_CFG3_0, e8h */ + u32 avp_ppcs_rd_coh_status; /* _AVP_PPCS_RD_COH_STATUS_0, ech */ + u32 ahb_mem_prefetch_cfg1; /* _AHB_MEM_PREFETCH_CFG1_0, f0h */ + u32 ahb_mem_prefetch_cfg2; /* _AHB_MEM_PREFETCH_CFG2_0, f4h */ + u32 ahbslvmem_status; /* _AHBSLVMEM_STATUS_0, f8h */ + /* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */ + u32 arbitration_ahb_mem_wrque_mst_id; + u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */ + u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */ + u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */ + u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */ + u32 reserved46[4]; /* 110h ~ 11ch */ + u32 avpc_mccif_fifoctrl; /* _AVPC_MCCIF_FIFOCTRL_0, 120h */ + u32 timeout_wcoal_avpc; /* _TIMEOUT_WCOAL_AVPC_0, 124h */ + u32 mpcorelp_mccif_fifoctrl; /* _MPCORELP_MCCIF_FIFOCTRL_0, 128h */ + u32 mpcore_mccif_fifoctrl; /* _MPCORE_MCCIF_FIFOCTRL_0, 12ch */ + u32 axicif_fastsync_ctrl; /* AXICIF_FASTSYNC_CTRL_0, 130h */ + u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */ + /* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */ + u32 axicif_fastsync0_cpuclk_to_mcclk; + /* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */ + u32 axicif_fastsync1_cpuclk_to_mcclk; + /* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */ + u32 axicif_fastsync2_cpuclk_to_mcclk; + /* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */ + u32 axicif_fastsync0_mcclk_to_cpuclk; + /* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */ + u32 axicif_fastsync1_mcclk_to_cpuclk; + /* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */ + u32 axicif_fastsync2_mcclk_to_cpuclk; +}; + +#define PPSB_STOPCLK_ENABLE (1 << 2) + +#define GIZ_ENABLE_SPLIT (1 << 0) +#define GIZ_ENB_FAST_REARB (1 << 2) +#define GIZ_DONT_SPLIT_AHB_WR (1 << 7) + +#define GIZ_USB_IMMEDIATE (1 << 18) + +/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */ +#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2) + +#endif /* _TEGRA210_AHB_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra210/clock-tables.h b/roms/u-boot/arch/arm/include/asm/arch-tegra210/clock-tables.h new file mode 100644 index 000000000..c6d7487e6 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra210/clock-tables.h @@ -0,0 +1,567 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation + */ + +/* Tegra210 clock PLL tables */ + +#ifndef _TEGRA210_CLOCK_TABLES_H_ +#define _TEGRA210_CLOCK_TABLES_H_ + +/* The PLLs supported by the hardware */ +enum clock_id { + CLOCK_ID_FIRST, + CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, + CLOCK_ID_MEMORY, + CLOCK_ID_PERIPH, + CLOCK_ID_AUDIO, + CLOCK_ID_USB, + CLOCK_ID_DISPLAY, + + /* now the simple ones */ + CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_EPCI, + CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DP, + + /* These are the base clocks (inputs to the Tegra SoC) */ + CLOCK_ID_32KHZ, + CLOCK_ID_OSC, + CLOCK_ID_CLK_M, + + CLOCK_ID_COUNT, /* number of PLLs */ + + /* + * These are clock IDs that are used in table clock_source[][] + * but will not be assigned as a clock source for any peripheral. + */ + CLOCK_ID_DISPLAY2, + CLOCK_ID_CGENERAL_0, + CLOCK_ID_CGENERAL_1, + CLOCK_ID_CGENERAL2, + CLOCK_ID_CGENERAL3, + CLOCK_ID_CGENERAL4_0, + CLOCK_ID_CGENERAL4_1, + CLOCK_ID_CGENERAL4_2, + CLOCK_ID_MEMORY2, + CLOCK_ID_SRC2, + + CLOCK_ID_NONE = -1, +}; + +/* The clocks supported by the hardware */ +enum periph_id { + PERIPH_ID_FIRST, + + /* Low word: 31:0 (DEVICES_L) */ + PERIPH_ID_CPU = PERIPH_ID_FIRST, + PERIPH_ID_COP, + PERIPH_ID_TRIGSYS, + PERIPH_ID_ISPB, + PERIPH_ID_RESERVED4, + PERIPH_ID_TMR, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + + /* 8 */ + PERIPH_ID_GPIO, + PERIPH_ID_SDMMC2, + PERIPH_ID_SPDIF, + PERIPH_ID_I2S2, + PERIPH_ID_I2C1, + PERIPH_ID_RESERVED13, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC4, + + /* 16 */ + PERIPH_ID_TCW, + PERIPH_ID_PWM, + PERIPH_ID_I2S3, + PERIPH_ID_RESERVED19, + PERIPH_ID_VI, + PERIPH_ID_RESERVED21, + PERIPH_ID_USBD, + PERIPH_ID_ISP, + + /* 24 */ + PERIPH_ID_RESERVED24, + PERIPH_ID_RESERVED25, + PERIPH_ID_DISP2, + PERIPH_ID_DISP1, + PERIPH_ID_HOST1X, + PERIPH_ID_VCP, + PERIPH_ID_I2S1, + PERIPH_ID_CACHE2, + + /* Middle word: 63:32 (DEVICES_H) */ + PERIPH_ID_MEM, + PERIPH_ID_AHBDMA, + PERIPH_ID_APBDMA, + PERIPH_ID_RESERVED35, + PERIPH_ID_RESERVED36, + PERIPH_ID_STAT_MON, + PERIPH_ID_RESERVED38, + PERIPH_ID_FUSE, + + /* 40 */ + PERIPH_ID_KFUSE, + PERIPH_ID_SBC1, + PERIPH_ID_SNOR, + PERIPH_ID_RESERVED43, + PERIPH_ID_SBC2, + PERIPH_ID_XIO, + PERIPH_ID_SBC3, + PERIPH_ID_I2C5, + + /* 48 */ + PERIPH_ID_DSI, + PERIPH_ID_RESERVED49, + PERIPH_ID_HSI, + PERIPH_ID_HDMI, + PERIPH_ID_CSI, + PERIPH_ID_RESERVED53, + PERIPH_ID_I2C2, + PERIPH_ID_UART3, + + /* 56 */ + PERIPH_ID_MIPI_CAL, + PERIPH_ID_EMC, + PERIPH_ID_USB2, + PERIPH_ID_USB3, + PERIPH_ID_RESERVED60, + PERIPH_ID_VDE, + PERIPH_ID_BSEA, + PERIPH_ID_BSEV, + + /* Upper word 95:64 (DEVICES_U) */ + PERIPH_ID_RESERVED64, + PERIPH_ID_UART4, + PERIPH_ID_UART5, + PERIPH_ID_I2C3, + PERIPH_ID_SBC4, + PERIPH_ID_SDMMC3, + PERIPH_ID_PCIE, + PERIPH_ID_OWR, + + /* 72 */ + PERIPH_ID_AFI, + PERIPH_ID_CORESIGHT, + PERIPH_ID_PCIEXCLK, + PERIPH_ID_AVPUCQ, + PERIPH_ID_LA, + PERIPH_ID_TRACECLKIN, + PERIPH_ID_SOC_THERM, + PERIPH_ID_DTV, + + /* 80 */ + PERIPH_ID_RESERVED80, + PERIPH_ID_I2CSLOW, + PERIPH_ID_DSIB, + PERIPH_ID_TSEC, + PERIPH_ID_RESERVED84, + PERIPH_ID_RESERVED85, + PERIPH_ID_RESERVED86, + PERIPH_ID_EMUCIF, + + /* 88 */ + PERIPH_ID_RESERVED88, + PERIPH_ID_XUSB_HOST, + PERIPH_ID_RESERVED90, + PERIPH_ID_MSENC, + PERIPH_ID_RESERVED92, + PERIPH_ID_RESERVED93, + PERIPH_ID_RESERVED94, + PERIPH_ID_XUSB_DEV, + + PERIPH_ID_VW_FIRST, + /* V word: 31:0 */ + PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST, + PERIPH_ID_CPULP, + PERIPH_ID_V_RESERVED2, + PERIPH_ID_MSELECT, + PERIPH_ID_V_RESERVED4, + PERIPH_ID_I2S4, + PERIPH_ID_I2S5, + PERIPH_ID_I2C4, + + /* 104 */ + PERIPH_ID_SBC5, + PERIPH_ID_SBC6, + PERIPH_ID_AHUB, + PERIPH_ID_APB2APE, + PERIPH_ID_V_RESERVED12, + PERIPH_ID_V_RESERVED13, + PERIPH_ID_V_RESERVED14, + PERIPH_ID_HDA2CODEC2X, + + /* 112 */ + PERIPH_ID_ATOMICS, + PERIPH_ID_V_RESERVED17, + PERIPH_ID_V_RESERVED18, + PERIPH_ID_V_RESERVED19, + PERIPH_ID_V_RESERVED20, + PERIPH_ID_V_RESERVED21, + PERIPH_ID_V_RESERVED22, + PERIPH_ID_ACTMON, + + /* 120 */ + PERIPH_ID_EXTPERIPH1, + PERIPH_ID_EXTPERIPH2, + PERIPH_ID_EXTPERIPH3, + PERIPH_ID_OOB, + PERIPH_ID_SATA, + PERIPH_ID_HDA, + PERIPH_ID_V_RESERVED30, + PERIPH_ID_V_RESERVED31, + + /* W word: 31:0 */ + PERIPH_ID_HDA2HDMICODEC, + PERIPH_ID_SATACOLD, + PERIPH_ID_W_RESERVED2, + PERIPH_ID_W_RESERVED3, + PERIPH_ID_W_RESERVED4, + PERIPH_ID_W_RESERVED5, + PERIPH_ID_W_RESERVED6, + PERIPH_ID_W_RESERVED7, + + /* 136 */ + PERIPH_ID_CEC, + PERIPH_ID_W_RESERVED9, + PERIPH_ID_W_RESERVED10, + PERIPH_ID_W_RESERVED11, + PERIPH_ID_W_RESERVED12, + PERIPH_ID_W_RESERVED13, + PERIPH_ID_XUSB_PADCTL, + PERIPH_ID_W_RESERVED15, + + /* 144 */ + PERIPH_ID_W_RESERVED16, + PERIPH_ID_W_RESERVED17, + PERIPH_ID_W_RESERVED18, + PERIPH_ID_W_RESERVED19, + PERIPH_ID_W_RESERVED20, + PERIPH_ID_ENTROPY, + PERIPH_ID_DDS, + PERIPH_ID_W_RESERVED23, + + /* 152 */ + PERIPH_ID_W_RESERVED24, + PERIPH_ID_W_RESERVED25, + PERIPH_ID_W_RESERVED26, + PERIPH_ID_DVFS, + PERIPH_ID_XUSB_SS, + PERIPH_ID_W_RESERVED29, + PERIPH_ID_W_RESERVED30, + PERIPH_ID_W_RESERVED31, + + PERIPH_ID_X_FIRST, + /* X word: 31:0 */ + PERIPH_ID_SPARE = PERIPH_ID_X_FIRST, + PERIPH_ID_X_RESERVED1, + PERIPH_ID_X_RESERVED2, + PERIPH_ID_X_RESERVED3, + PERIPH_ID_CAM_MCLK, + PERIPH_ID_CAM_MCLK2, + PERIPH_ID_I2C6, + PERIPH_ID_X_RESERVED7, + + /* 168 */ + PERIPH_ID_X_RESERVED8, + PERIPH_ID_X_RESERVED9, + PERIPH_ID_X_RESERVED10, + PERIPH_ID_VIM2_CLK, + PERIPH_ID_X_RESERVED12, + PERIPH_ID_X_RESERVED13, + PERIPH_ID_EMC_DLL, + PERIPH_ID_X_RESERVED15, + + /* 176 */ + PERIPH_ID_HDMI_AUDIO, + PERIPH_ID_CLK72MHZ, + PERIPH_ID_VIC, + PERIPH_ID_X_RESERVED19, + PERIPH_ID_X_RESERVED20, + PERIPH_ID_DPAUX, + PERIPH_ID_SOR0, + PERIPH_ID_X_RESERVED23, + + /* 184 */ + PERIPH_ID_GPU, + PERIPH_ID_X_RESERVED25, + PERIPH_ID_X_RESERVED26, + PERIPH_ID_X_RESERVED27, + PERIPH_ID_X_RESERVED28, + PERIPH_ID_X_RESERVED29, + PERIPH_ID_X_RESERVED30, + PERIPH_ID_X_RESERVED31, + + PERIPH_ID_Y_FIRST, + /* Y word: 31:0 (192:223) */ + PERIPH_ID_SPARE1 = PERIPH_ID_Y_FIRST, + PERIPH_ID_Y_RESERVED1, + PERIPH_ID_Y_RESERVED2, + PERIPH_ID_Y_RESERVED3, + PERIPH_ID_Y_RESERVED4, + PERIPH_ID_Y_RESERVED5, + PERIPH_ID_APE, + PERIPH_ID_Y_RESERVED7, + + /* 200 */ + PERIPH_ID_MC_CDPA, + PERIPH_ID_Y_RESERVED9, + PERIPH_ID_Y_RESERVED10, + PERIPH_ID_Y_RESERVED11, + PERIPH_ID_Y_RESERVED12, + PERIPH_ID_PEX_USB_UPHY, + PERIPH_ID_Y_RESERVED14, + PERIPH_ID_Y_RESERVED15, + + /* 208 */ + PERIPH_ID_VI_I2C, + PERIPH_ID_Y_RESERVED17, + PERIPH_ID_Y_RESERVED18, + PERIPH_ID_QSPI, + PERIPH_ID_Y_RESERVED20, + PERIPH_ID_Y_RESERVED21, + PERIPH_ID_Y_RESERVED22, + PERIPH_ID_Y_RESERVED23, + + /* 216 */ + PERIPH_ID_Y_RESERVED24, + PERIPH_ID_Y_RESERVED25, + PERIPH_ID_Y_RESERVED26, + PERIPH_ID_Y_RESERVED27, + PERIPH_ID_Y_RESERVED28, + PERIPH_ID_Y_RESERVED29, + PERIPH_ID_Y_RESERVED30, + PERIPH_ID_Y_RESERVED31, + + PERIPH_ID_COUNT, + PERIPH_ID_NONE = -1, +}; + +enum pll_out_id { + PLL_OUT1, + PLL_OUT2, + PLL_OUT3, + PLL_OUT4 +}; + +/* + * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want + * callers to use the PERIPH_ID for all access to peripheral clocks to avoid + * confusion bewteen PERIPH_ID_... and PERIPHC_... + * + * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be + * confusing. + */ +enum periphc_internal_id { + /* 0x00 */ + PERIPHC_I2S2, + PERIPHC_I2S3, + PERIPHC_SPDIF_OUT, + PERIPHC_SPDIF_IN, + PERIPHC_PWM, + PERIPHC_05h, + PERIPHC_SBC2, + PERIPHC_SBC3, + + /* 0x08 */ + PERIPHC_08h, + PERIPHC_I2C1, + PERIPHC_I2C5, + PERIPHC_0bh, + PERIPHC_0ch, + PERIPHC_SBC1, + PERIPHC_DISP1, + PERIPHC_DISP2, + + /* 0x10 */ + PERIPHC_10h, + PERIPHC_11h, + PERIPHC_VI, + PERIPHC_13h, + PERIPHC_SDMMC1, + PERIPHC_SDMMC2, + PERIPHC_G3D, + PERIPHC_G2D, + + /* 0x18 */ + PERIPHC_18h, + PERIPHC_SDMMC4, + PERIPHC_VFIR, + PERIPHC_1Bh, + PERIPHC_1Ch, + PERIPHC_HSI, + PERIPHC_UART1, + PERIPHC_UART2, + + /* 0x20 */ + PERIPHC_HOST1X, + PERIPHC_21h, + PERIPHC_22h, + PERIPHC_HDMI, + PERIPHC_24h, + PERIPHC_25h, + PERIPHC_I2C2, + PERIPHC_EMC, + + /* 0x28 */ + PERIPHC_UART3, + PERIPHC_29h, + PERIPHC_VI_SENSOR, + PERIPHC_2bh, + PERIPHC_2ch, + PERIPHC_SBC4, + PERIPHC_I2C3, + PERIPHC_SDMMC3, + + /* 0x30 */ + PERIPHC_UART4, + PERIPHC_UART5, + PERIPHC_VDE, + PERIPHC_OWR, + PERIPHC_NOR, + PERIPHC_CSITE, + PERIPHC_I2S1, + PERIPHC_DTV, + + /* 0x38 */ + PERIPHC_38h, + PERIPHC_39h, + PERIPHC_3ah, + PERIPHC_3bh, + PERIPHC_MSENC, + PERIPHC_TSEC, + PERIPHC_3eh, + PERIPHC_OSC, + + PERIPHC_VW_FIRST, + /* 0x40 */ + PERIPHC_40h = PERIPHC_VW_FIRST, + PERIPHC_MSELECT, + PERIPHC_TSENSOR, + PERIPHC_I2S4, + PERIPHC_I2S5, + PERIPHC_I2C4, + PERIPHC_SBC5, + PERIPHC_SBC6, + + /* 0x48 */ + PERIPHC_AUDIO, + PERIPHC_49h, + PERIPHC_4ah, + PERIPHC_4bh, + PERIPHC_4ch, + PERIPHC_HDA2CODEC2X, + PERIPHC_ACTMON, + PERIPHC_EXTPERIPH1, + + /* 0x50 */ + PERIPHC_EXTPERIPH2, + PERIPHC_EXTPERIPH3, + PERIPHC_52h, + PERIPHC_I2CSLOW, + PERIPHC_SYS, + PERIPHC_55h, + PERIPHC_56h, + PERIPHC_57h, + + /* 0x58 */ + PERIPHC_58h, + PERIPHC_59h, + PERIPHC_5ah, + PERIPHC_5bh, + PERIPHC_SATAOOB, + PERIPHC_SATA, + PERIPHC_HDA, /* 0x428 */ + PERIPHC_5fh, + + PERIPHC_X_FIRST, + /* 0x60 */ + PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */ + PERIPHC_XUSB_FALCON, + PERIPHC_XUSB_FS, + PERIPHC_XUSB_CORE_DEV, + PERIPHC_XUSB_SS, + PERIPHC_CILAB, + PERIPHC_CILCD, + PERIPHC_CILE, + + /* 0x68 */ + PERIPHC_DSIA_LP, + PERIPHC_DSIB_LP, + PERIPHC_ENTROPY, + PERIPHC_DVFS_REF, + PERIPHC_DVFS_SOC, + PERIPHC_TRACECLKIN, + PERIPHC_6Eh, + PERIPHC_6Fh, + + /* 0x70 */ + PERIPHC_EMC_LATENCY, + PERIPHC_SOC_THERM, + PERIPHC_72h, + PERIPHC_73h, + PERIPHC_74h, + PERIPHC_75h, + PERIPHC_VI_SENSOR2, + PERIPHC_I2C6, + + /* 0x78 */ + PERIPHC_78h, + PERIPHC_EMC_DLL, + PERIPHC_7ah, + PERIPHC_CLK72MHZ, + PERIPHC_7ch, + PERIPHC_7dh, + PERIPHC_VIC, + PERIPHC_7fh, + + PERIPHC_Y_FIRST, + /* 0x80 */ + PERIPHC_SDMMC_LEGACY_TM = PERIPHC_Y_FIRST, /* 0x694 */ + PERIPHC_NVDEC, /* 0x698 */ + PERIPHC_NVJPG, /* 0x69c */ + PERIPHC_NVENC, /* 0x6a0 */ + PERIPHC_84h, + PERIPHC_85h, + PERIPHC_86h, + PERIPHC_87h, + + /* 0x88 */ + PERIPHC_88h, + PERIPHC_89h, + PERIPHC_DMIC3, /* 0x6bc: */ + PERIPHC_APE, /* 0x6c0: */ + PERIPHC_QSPI, /* 0x6c4: */ + PERIPHC_VI_I2C, /* 0x6c8: */ + PERIPHC_USB2_HSIC_TRK, /* 0x6cc: */ + PERIPHC_PEX_SATA_USB_RX_BYP, /* 0x6d0: */ + + /* 0x90 */ + PERIPHC_MAUD, /* 0x6d4: */ + PERIPHC_TSECB, /* 0x6d8: */ + + PERIPHC_COUNT, + PERIPHC_NONE = -1, +}; + +/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */ +#define PERIPH_REG(id) \ + (id < PERIPH_ID_VW_FIRST) ? \ + ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5) + +/* Mask value for a clock (within PERIPH_REG(id)) */ +#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) + +/* return 1 if a PLL ID is in range */ +#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) + +/* return 1 if a peripheral ID is in range */ +#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ + (id) < PERIPH_ID_COUNT) + +#endif /* _TEGRA210_CLOCK_TABLES_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra210/clock.h b/roms/u-boot/arch/arm/include/asm/arch-tegra210/clock.h new file mode 100644 index 000000000..438a6f46c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra210/clock.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010-2015 + * NVIDIA Corporation + */ + +/* Tegra210 clock control definitions */ + +#ifndef _TEGRA210_CLOCK_H_ +#define _TEGRA210_CLOCK_H_ + +#include + +/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ +#define OSC_FREQ_SHIFT 28 +#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) + +/* PLL bits that differ from generic clk_rst.h */ +#define PLLC_RESET 30 +#define PLLC_IDDQ 27 +#define PLLD_ENABLE_CLK 21 +#define PLLD_EN_LCKDET 28 + +int tegra_plle_enable(void); + +#endif /* _TEGRA210_CLOCK_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra210/flow.h b/roms/u-boot/arch/arm/include/asm/arch-tegra210/flow.h new file mode 100644 index 000000000..ef0be19e5 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra210/flow.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010-2015 + * NVIDIA Corporation + */ + +#ifndef _TEGRA210_FLOW_H_ +#define _TEGRA210_FLOW_H_ + +struct flow_ctlr { + u32 halt_cpu_events; /* offset 0x00 */ + u32 halt_cop_events; /* offset 0x04 */ + u32 cpu_csr; /* offset 0x08 */ + u32 cop_csr; /* offset 0x0c */ + u32 xrq_events; /* offset 0x10 */ + u32 halt_cpu1_events; /* offset 0x14 */ + u32 cpu1_csr; /* offset 0x18 */ + u32 halt_cpu2_events; /* offset 0x1c */ + u32 cpu2_csr; /* offset 0x20 */ + u32 halt_cpu3_events; /* offset 0x24 */ + u32 cpu3_csr; /* offset 0x28 */ + u32 cluster_control; /* offset 0x2c */ + u32 halt_cop1_events; /* offset 0x30 */ + u32 halt_cop1_csr; /* offset 0x34 */ + u32 cpu_pwr_csr; /* offset 0x38 */ + u32 mpid; /* offset 0x3c */ + u32 ram_repair; /* offset 0x40 */ +}; + +/* HALT_COP_EVENTS_0, 0x04 */ +#define EVENT_MSEC (1 << 24) +#define EVENT_USEC (1 << 25) +#define EVENT_JTAG (1 << 28) +#define EVENT_MODE_STOP (2 << 29) + +/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ +#define ACTIVE_LP (1 << 0) + +/* CPUn_CSR_0 */ +#define CSR_ENABLE (1 << 0) +#define CSR_IMMEDIATE_WAKE (1 << 3) +#define CSR_WAIT_WFI_SHIFT 8 + +#endif /* _TEGRA210_FLOW_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra210/funcmux.h b/roms/u-boot/arch/arm/include/asm/arch-tegra210/funcmux.h new file mode 100644 index 000000000..f6270e57a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra210/funcmux.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation + */ + +/* Tegra210 high-level function multiplexing */ + +#ifndef _TEGRA210_FUNCMUX_H_ +#define _TEGRA210_FUNCMUX_H_ + +#include + +/* Configs supported by the func mux */ +enum { + FUNCMUX_DEFAULT = 0, /* default config */ + + /* UART configs */ + FUNCMUX_UART1_UART1 = 0, + FUNCMUX_UART4_UART4 = 0, +}; +#endif /* _TEGRA210_FUNCMUX_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra210/gp_padctrl.h b/roms/u-boot/arch/arm/include/asm/arch-tegra210/gp_padctrl.h new file mode 100644 index 000000000..e9ff90375 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra210/gp_padctrl.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010-2015 + * NVIDIA Corporation + */ + +#ifndef _TEGRA210_GP_PADCTRL_H_ +#define _TEGRA210_GP_PADCTRL_H_ + +#include + +/* APB_MISC_GP and padctrl registers */ +struct apb_misc_gp_ctlr { + u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ + u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ + u32 reserved0[22]; /* 0x08 - 0x5C: */ + u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ + u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ + u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ + u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ + u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ + u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ + u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ + u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ + u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ + u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ + u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ + u32 reserved1; /* 0x8C: */ + u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ + u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ + u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ + u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ + u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ + u32 reserved2[3]; /* 0xA4 - 0xAC: */ + u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ + u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ + u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ + u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ + u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ + u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ + u32 reserved3[9]; /* 0xC8-0xE8: */ + u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ + u32 reserved4[3]; /* 0xF0-0xF8: */ + u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ + u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ + u32 reserved5[3]; /* 0x104-0x10C: */ + u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ + u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ + u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ + u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ + u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ + u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ + u32 reserved6; /* 0x128: */ + u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ + u32 reserved7[2]; /* 0x130 - 0x134: */ + u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ + u32 reserved8[22]; /* 0x13C - 0x190: */ + u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ + u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ + u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ + u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ + u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ + u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ + u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ +}; + +/* SDMMC1/3 settings from section 27.5 of T114 TRM */ +#define SDIOCFG_DRVUP_SLWF 0 +#define SDIOCFG_DRVDN_SLWR 0 +#define SDIOCFG_DRVUP 0x24 +#define SDIOCFG_DRVDN 0x14 + +#endif /* _TEGRA210_GP_PADCTRL_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra210/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-tegra210/gpio.h new file mode 100644 index 000000000..cb91b10be --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra210/gpio.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation + */ + +#ifndef _TEGRA210_GPIO_H_ +#define _TEGRA210_GPIO_H_ + +/* + * The Tegra210 GPIO controller has 256 GPIOS in 8 banks of 4 ports, + * each with 8 GPIOs. + */ +#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ +#define TEGRA_GPIO_BANKS 8 /* number of banks */ + +#include + +/* GPIO Controller registers for a single bank */ +struct gpio_ctlr_bank { + uint gpio_config[TEGRA_GPIO_PORTS]; + uint gpio_dir_out[TEGRA_GPIO_PORTS]; + uint gpio_out[TEGRA_GPIO_PORTS]; + uint gpio_in[TEGRA_GPIO_PORTS]; + uint gpio_int_status[TEGRA_GPIO_PORTS]; + uint gpio_int_enable[TEGRA_GPIO_PORTS]; + uint gpio_int_level[TEGRA_GPIO_PORTS]; + uint gpio_int_clear[TEGRA_GPIO_PORTS]; + uint gpio_masked_config[TEGRA_GPIO_PORTS]; + uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; + uint gpio_masked_out[TEGRA_GPIO_PORTS]; + uint gpio_masked_in[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_clear[TEGRA_GPIO_PORTS]; +}; + +struct gpio_ctlr { + struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; +}; + +#endif /* _TEGRA210_GPIO_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra210/mc.h b/roms/u-boot/arch/arm/include/asm/arch-tegra210/mc.h new file mode 100644 index 000000000..5a2a5681d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra210/mc.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA210_MC_H_ +#define _TEGRA210_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[4]; /* offset 0x00 - 0x0C */ + u32 mc_smmu_config; /* offset 0x10 */ + u32 mc_smmu_tlb_config; /* offset 0x14 */ + u32 mc_smmu_ptc_config; /* offset 0x18 */ + u32 mc_smmu_ptb_asid; /* offset 0x1C */ + u32 mc_smmu_ptb_data; /* offset 0x20 */ + u32 reserved1[3]; /* offset 0x24 - 0x2C */ + u32 mc_smmu_tlb_flush; /* offset 0x30 */ + u32 mc_smmu_ptc_flush; /* offset 0x34 */ + u32 reserved2[6]; /* offset 0x38 - 0x4C */ + u32 mc_emem_cfg; /* offset 0x50 */ + u32 mc_emem_adr_cfg; /* offset 0x54 */ + u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ + u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ + u32 reserved3[4]; /* offset 0x60 - 0x6C */ + u32 mc_security_cfg0; /* offset 0x70 */ + u32 mc_security_cfg1; /* offset 0x74 */ + u32 reserved4[6]; /* offset 0x7C - 0x8C */ + u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ + u32 reserved5[74]; /* offset 0x100 - 0x224 */ + u32 mc_smmu_translation_enable_0; /* offset 0x228 */ + u32 mc_smmu_translation_enable_1; /* offset 0x22C */ + u32 mc_smmu_translation_enable_2; /* offset 0x230 */ + u32 mc_smmu_translation_enable_3; /* offset 0x234 */ + u32 mc_smmu_afi_asid; /* offset 0x238 */ + u32 mc_smmu_avpc_asid; /* offset 0x23C */ + u32 mc_smmu_dc_asid; /* offset 0x240 */ + u32 mc_smmu_dcb_asid; /* offset 0x244 */ + u32 reserved6[2]; /* offset 0x248 - 0x24C */ + u32 mc_smmu_hc_asid; /* offset 0x250 */ + u32 mc_smmu_hda_asid; /* offset 0x254 */ + u32 mc_smmu_isp2_asid; /* offset 0x258 */ + u32 reserved7[2]; /* offset 0x25C - 0x260 */ + u32 mc_smmu_msenc_asid; /* offset 0x264 */ + u32 mc_smmu_nv_asid; /* offset 0x268 */ + u32 mc_smmu_nv2_asid; /* offset 0x26C */ + u32 mc_smmu_ppcs_asid; /* offset 0x270 */ + u32 mc_smmu_sata_asid; /* offset 0x274 */ + u32 reserved8[1]; /* offset 0x278 */ + u32 mc_smmu_vde_asid; /* offset 0x27C */ + u32 mc_smmu_vi_asid; /* offset 0x280 */ + u32 mc_smmu_vic_asid; /* offset 0x284 */ + u32 mc_smmu_xusb_host_asid; /* offset 0x288 */ + u32 mc_smmu_xusb_dev_asid; /* offset 0x28C */ + u32 reserved9[1]; /* offset 0x290 */ + u32 mc_smmu_tsec_asid; /* offset 0x294 */ + u32 mc_smmu_ppcs1_asid; /* offset 0x298 */ + u32 reserved10[235]; /* offset 0x29C - 0x644 */ + u32 mc_video_protect_bom; /* offset 0x648 */ + u32 mc_video_protect_size_mb; /* offset 0x64c */ + u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ +}; + +#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0) + +#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) +#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) + +#endif /* _TEGRA210_MC_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra210/pinmux.h b/roms/u-boot/arch/arm/include/asm/arch-tegra210/pinmux.h new file mode 100644 index 000000000..9e9407462 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra210/pinmux.h @@ -0,0 +1,415 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA210_PINMUX_H_ +#define _TEGRA210_PINMUX_H_ + +enum pmux_pingrp { + PMUX_PINGRP_SDMMC1_CLK_PM0, + PMUX_PINGRP_SDMMC1_CMD_PM1, + PMUX_PINGRP_SDMMC1_DAT3_PM2, + PMUX_PINGRP_SDMMC1_DAT2_PM3, + PMUX_PINGRP_SDMMC1_DAT1_PM4, + PMUX_PINGRP_SDMMC1_DAT0_PM5, + PMUX_PINGRP_SDMMC3_CLK_PP0 = (0x1c / 4), + PMUX_PINGRP_SDMMC3_CMD_PP1, + PMUX_PINGRP_SDMMC3_DAT0_PP5, + PMUX_PINGRP_SDMMC3_DAT1_PP4, + PMUX_PINGRP_SDMMC3_DAT2_PP3, + PMUX_PINGRP_SDMMC3_DAT3_PP2, + PMUX_PINGRP_PEX_L0_RST_N_PA0 = (0x38 / 4), + PMUX_PINGRP_PEX_L0_CLKREQ_N_PA1, + PMUX_PINGRP_PEX_WAKE_N_PA2, + PMUX_PINGRP_PEX_L1_RST_N_PA3, + PMUX_PINGRP_PEX_L1_CLKREQ_N_PA4, + PMUX_PINGRP_SATA_LED_ACTIVE_PA5, + PMUX_PINGRP_SPI1_MOSI_PC0, + PMUX_PINGRP_SPI1_MISO_PC1, + PMUX_PINGRP_SPI1_SCK_PC2, + PMUX_PINGRP_SPI1_CS0_PC3, + PMUX_PINGRP_SPI1_CS1_PC4, + PMUX_PINGRP_SPI2_MOSI_PB4, + PMUX_PINGRP_SPI2_MISO_PB5, + PMUX_PINGRP_SPI2_SCK_PB6, + PMUX_PINGRP_SPI2_CS0_PB7, + PMUX_PINGRP_SPI2_CS1_PDD0, + PMUX_PINGRP_SPI4_MOSI_PC7, + PMUX_PINGRP_SPI4_MISO_PD0, + PMUX_PINGRP_SPI4_SCK_PC5, + PMUX_PINGRP_SPI4_CS0_PC6, + PMUX_PINGRP_QSPI_SCK_PEE0, + PMUX_PINGRP_QSPI_CS_N_PEE1, + PMUX_PINGRP_QSPI_IO0_PEE2, + PMUX_PINGRP_QSPI_IO1_PEE3, + PMUX_PINGRP_QSPI_IO2_PEE4, + PMUX_PINGRP_QSPI_IO3_PEE5, + PMUX_PINGRP_DMIC1_CLK_PE0 = (0xa4 / 4), + PMUX_PINGRP_DMIC1_DAT_PE1, + PMUX_PINGRP_DMIC2_CLK_PE2, + PMUX_PINGRP_DMIC2_DAT_PE3, + PMUX_PINGRP_DMIC3_CLK_PE4, + PMUX_PINGRP_DMIC3_DAT_PE5, + PMUX_PINGRP_GEN1_I2C_SCL_PJ1, + PMUX_PINGRP_GEN1_I2C_SDA_PJ0, + PMUX_PINGRP_GEN2_I2C_SCL_PJ2, + PMUX_PINGRP_GEN2_I2C_SDA_PJ3, + PMUX_PINGRP_GEN3_I2C_SCL_PF0, + PMUX_PINGRP_GEN3_I2C_SDA_PF1, + PMUX_PINGRP_CAM_I2C_SCL_PS2, + PMUX_PINGRP_CAM_I2C_SDA_PS3, + PMUX_PINGRP_PWR_I2C_SCL_PY3, + PMUX_PINGRP_PWR_I2C_SDA_PY4, + PMUX_PINGRP_UART1_TX_PU0, + PMUX_PINGRP_UART1_RX_PU1, + PMUX_PINGRP_UART1_RTS_PU2, + PMUX_PINGRP_UART1_CTS_PU3, + PMUX_PINGRP_UART2_TX_PG0, + PMUX_PINGRP_UART2_RX_PG1, + PMUX_PINGRP_UART2_RTS_PG2, + PMUX_PINGRP_UART2_CTS_PG3, + PMUX_PINGRP_UART3_TX_PD1, + PMUX_PINGRP_UART3_RX_PD2, + PMUX_PINGRP_UART3_RTS_PD3, + PMUX_PINGRP_UART3_CTS_PD4, + PMUX_PINGRP_UART4_TX_PI4, + PMUX_PINGRP_UART4_RX_PI5, + PMUX_PINGRP_UART4_RTS_PI6, + PMUX_PINGRP_UART4_CTS_PI7, + PMUX_PINGRP_DAP1_FS_PB0, + PMUX_PINGRP_DAP1_DIN_PB1, + PMUX_PINGRP_DAP1_DOUT_PB2, + PMUX_PINGRP_DAP1_SCLK_PB3, + PMUX_PINGRP_DAP2_FS_PAA0, + PMUX_PINGRP_DAP2_DIN_PAA2, + PMUX_PINGRP_DAP2_DOUT_PAA3, + PMUX_PINGRP_DAP2_SCLK_PAA1, + PMUX_PINGRP_DAP4_FS_PJ4, + PMUX_PINGRP_DAP4_DIN_PJ5, + PMUX_PINGRP_DAP4_DOUT_PJ6, + PMUX_PINGRP_DAP4_SCLK_PJ7, + PMUX_PINGRP_CAM1_MCLK_PS0, + PMUX_PINGRP_CAM2_MCLK_PS1, + PMUX_PINGRP_JTAG_RTCK, + PMUX_PINGRP_CLK_32K_IN, + PMUX_PINGRP_CLK_32K_OUT_PY5, + PMUX_PINGRP_BATT_BCL, + PMUX_PINGRP_CLK_REQ, + PMUX_PINGRP_CPU_PWR_REQ, + PMUX_PINGRP_PWR_INT_N, + PMUX_PINGRP_SHUTDOWN, + PMUX_PINGRP_CORE_PWR_REQ, + PMUX_PINGRP_AUD_MCLK_PBB0, + PMUX_PINGRP_DVFS_PWM_PBB1, + PMUX_PINGRP_DVFS_CLK_PBB2, + PMUX_PINGRP_GPIO_X1_AUD_PBB3, + PMUX_PINGRP_GPIO_X3_AUD_PBB4, + PMUX_PINGRP_PCC7, + PMUX_PINGRP_HDMI_CEC_PCC0, + PMUX_PINGRP_HDMI_INT_DP_HPD_PCC1, + PMUX_PINGRP_SPDIF_OUT_PCC2, + PMUX_PINGRP_SPDIF_IN_PCC3, + PMUX_PINGRP_USB_VBUS_EN0_PCC4, + PMUX_PINGRP_USB_VBUS_EN1_PCC5, + PMUX_PINGRP_DP_HPD0_PCC6, + PMUX_PINGRP_WIFI_EN_PH0, + PMUX_PINGRP_WIFI_RST_PH1, + PMUX_PINGRP_WIFI_WAKE_AP_PH2, + PMUX_PINGRP_AP_WAKE_BT_PH3, + PMUX_PINGRP_BT_RST_PH4, + PMUX_PINGRP_BT_WAKE_AP_PH5, + PMUX_PINGRP_AP_WAKE_NFC_PH7, + PMUX_PINGRP_NFC_EN_PI0, + PMUX_PINGRP_NFC_INT_PI1, + PMUX_PINGRP_GPS_EN_PI2, + PMUX_PINGRP_GPS_RST_PI3, + PMUX_PINGRP_CAM_RST_PS4, + PMUX_PINGRP_CAM_AF_EN_PS5, + PMUX_PINGRP_CAM_FLASH_EN_PS6, + PMUX_PINGRP_CAM1_PWDN_PS7, + PMUX_PINGRP_CAM2_PWDN_PT0, + PMUX_PINGRP_CAM1_STROBE_PT1, + PMUX_PINGRP_LCD_TE_PY2, + PMUX_PINGRP_LCD_BL_PWM_PV0, + PMUX_PINGRP_LCD_BL_EN_PV1, + PMUX_PINGRP_LCD_RST_PV2, + PMUX_PINGRP_LCD_GPIO1_PV3, + PMUX_PINGRP_LCD_GPIO2_PV4, + PMUX_PINGRP_AP_READY_PV5, + PMUX_PINGRP_TOUCH_RST_PV6, + PMUX_PINGRP_TOUCH_CLK_PV7, + PMUX_PINGRP_MODEM_WAKE_AP_PX0, + PMUX_PINGRP_TOUCH_INT_PX1, + PMUX_PINGRP_MOTION_INT_PX2, + PMUX_PINGRP_ALS_PROX_INT_PX3, + PMUX_PINGRP_TEMP_ALERT_PX4, + PMUX_PINGRP_BUTTON_POWER_ON_PX5, + PMUX_PINGRP_BUTTON_VOL_UP_PX6, + PMUX_PINGRP_BUTTON_VOL_DOWN_PX7, + PMUX_PINGRP_BUTTON_SLIDE_SW_PY0, + PMUX_PINGRP_BUTTON_HOME_PY1, + PMUX_PINGRP_PA6, + PMUX_PINGRP_PE6, + PMUX_PINGRP_PE7, + PMUX_PINGRP_PH6, + PMUX_PINGRP_PK0, + PMUX_PINGRP_PK1, + PMUX_PINGRP_PK2, + PMUX_PINGRP_PK3, + PMUX_PINGRP_PK4, + PMUX_PINGRP_PK5, + PMUX_PINGRP_PK6, + PMUX_PINGRP_PK7, + PMUX_PINGRP_PL0, + PMUX_PINGRP_PL1, + PMUX_PINGRP_PZ0, + PMUX_PINGRP_PZ1, + PMUX_PINGRP_PZ2, + PMUX_PINGRP_PZ3, + PMUX_PINGRP_PZ4, + PMUX_PINGRP_PZ5, + PMUX_PINGRP_COUNT, +}; + +enum pmux_drvgrp { + PMUX_DRVGRP_ALS_PROX_INT = (0x10 / 4), + PMUX_DRVGRP_AP_READY, + PMUX_DRVGRP_AP_WAKE_BT, + PMUX_DRVGRP_AP_WAKE_NFC, + PMUX_DRVGRP_AUD_MCLK, + PMUX_DRVGRP_BATT_BCL, + PMUX_DRVGRP_BT_RST, + PMUX_DRVGRP_BT_WAKE_AP, + PMUX_DRVGRP_BUTTON_HOME, + PMUX_DRVGRP_BUTTON_POWER_ON, + PMUX_DRVGRP_BUTTON_SLIDE_SW, + PMUX_DRVGRP_BUTTON_VOL_DOWN, + PMUX_DRVGRP_BUTTON_VOL_UP, + PMUX_DRVGRP_CAM1_MCLK, + PMUX_DRVGRP_CAM1_PWDN, + PMUX_DRVGRP_CAM1_STROBE, + PMUX_DRVGRP_CAM2_MCLK, + PMUX_DRVGRP_CAM2_PWDN, + PMUX_DRVGRP_CAM_AF_EN, + PMUX_DRVGRP_CAM_FLASH_EN, + PMUX_DRVGRP_CAM_I2C_SCL, + PMUX_DRVGRP_CAM_I2C_SDA, + PMUX_DRVGRP_CAM_RST, + PMUX_DRVGRP_CLK_32K_IN, + PMUX_DRVGRP_CLK_32K_OUT, + PMUX_DRVGRP_CLK_REQ, + PMUX_DRVGRP_CORE_PWR_REQ, + PMUX_DRVGRP_CPU_PWR_REQ, + PMUX_DRVGRP_DAP1_DIN, + PMUX_DRVGRP_DAP1_DOUT, + PMUX_DRVGRP_DAP1_FS, + PMUX_DRVGRP_DAP1_SCLK, + PMUX_DRVGRP_DAP2_DIN, + PMUX_DRVGRP_DAP2_DOUT, + PMUX_DRVGRP_DAP2_FS, + PMUX_DRVGRP_DAP2_SCLK, + PMUX_DRVGRP_DAP4_DIN, + PMUX_DRVGRP_DAP4_DOUT, + PMUX_DRVGRP_DAP4_FS, + PMUX_DRVGRP_DAP4_SCLK, + PMUX_DRVGRP_DMIC1_CLK, + PMUX_DRVGRP_DMIC1_DAT, + PMUX_DRVGRP_DMIC2_CLK, + PMUX_DRVGRP_DMIC2_DAT, + PMUX_DRVGRP_DMIC3_CLK, + PMUX_DRVGRP_DMIC3_DAT, + PMUX_DRVGRP_DP_HPD0, + PMUX_DRVGRP_DVFS_CLK, + PMUX_DRVGRP_DVFS_PWM, + PMUX_DRVGRP_GEN1_I2C_SCL, + PMUX_DRVGRP_GEN1_I2C_SDA, + PMUX_DRVGRP_GEN2_I2C_SCL, + PMUX_DRVGRP_GEN2_I2C_SDA, + PMUX_DRVGRP_GEN3_I2C_SCL, + PMUX_DRVGRP_GEN3_I2C_SDA, + PMUX_DRVGRP_PA6, + PMUX_DRVGRP_PCC7, + PMUX_DRVGRP_PE6, + PMUX_DRVGRP_PE7, + PMUX_DRVGRP_PH6, + PMUX_DRVGRP_PK0, + PMUX_DRVGRP_PK1, + PMUX_DRVGRP_PK2, + PMUX_DRVGRP_PK3, + PMUX_DRVGRP_PK4, + PMUX_DRVGRP_PK5, + PMUX_DRVGRP_PK6, + PMUX_DRVGRP_PK7, + PMUX_DRVGRP_PL0, + PMUX_DRVGRP_PL1, + PMUX_DRVGRP_PZ0, + PMUX_DRVGRP_PZ1, + PMUX_DRVGRP_PZ2, + PMUX_DRVGRP_PZ3, + PMUX_DRVGRP_PZ4, + PMUX_DRVGRP_PZ5, + PMUX_DRVGRP_GPIO_X1_AUD, + PMUX_DRVGRP_GPIO_X3_AUD, + PMUX_DRVGRP_GPS_EN, + PMUX_DRVGRP_GPS_RST, + PMUX_DRVGRP_HDMI_CEC, + PMUX_DRVGRP_HDMI_INT_DP_HPD, + PMUX_DRVGRP_JTAG_RTCK, + PMUX_DRVGRP_LCD_BL_EN, + PMUX_DRVGRP_LCD_BL_PWM, + PMUX_DRVGRP_LCD_GPIO1, + PMUX_DRVGRP_LCD_GPIO2, + PMUX_DRVGRP_LCD_RST, + PMUX_DRVGRP_LCD_TE, + PMUX_DRVGRP_MODEM_WAKE_AP, + PMUX_DRVGRP_MOTION_INT, + PMUX_DRVGRP_NFC_EN, + PMUX_DRVGRP_NFC_INT, + PMUX_DRVGRP_PEX_L0_CLKREQ_N, + PMUX_DRVGRP_PEX_L0_RST_N, + PMUX_DRVGRP_PEX_L1_CLKREQ_N, + PMUX_DRVGRP_PEX_L1_RST_N, + PMUX_DRVGRP_PEX_WAKE_N, + PMUX_DRVGRP_PWR_I2C_SCL, + PMUX_DRVGRP_PWR_I2C_SDA, + PMUX_DRVGRP_PWR_INT_N, + PMUX_DRVGRP_QSPI_SCK = (0x1bc / 4), + PMUX_DRVGRP_SATA_LED_ACTIVE, + PMUX_DRVGRP_SDMMC1, + PMUX_DRVGRP_SDMMC2, + PMUX_DRVGRP_SDMMC3 = (0x1dc / 4), + PMUX_DRVGRP_SDMMC4, + PMUX_DRVGRP_SHUTDOWN = (0x1f4 / 4), + PMUX_DRVGRP_SPDIF_IN, + PMUX_DRVGRP_SPDIF_OUT, + PMUX_DRVGRP_SPI1_CS0, + PMUX_DRVGRP_SPI1_CS1, + PMUX_DRVGRP_SPI1_MISO, + PMUX_DRVGRP_SPI1_MOSI, + PMUX_DRVGRP_SPI1_SCK, + PMUX_DRVGRP_SPI2_CS0, + PMUX_DRVGRP_SPI2_CS1, + PMUX_DRVGRP_SPI2_MISO, + PMUX_DRVGRP_SPI2_MOSI, + PMUX_DRVGRP_SPI2_SCK, + PMUX_DRVGRP_SPI4_CS0, + PMUX_DRVGRP_SPI4_MISO, + PMUX_DRVGRP_SPI4_MOSI, + PMUX_DRVGRP_SPI4_SCK, + PMUX_DRVGRP_TEMP_ALERT, + PMUX_DRVGRP_TOUCH_CLK, + PMUX_DRVGRP_TOUCH_INT, + PMUX_DRVGRP_TOUCH_RST, + PMUX_DRVGRP_UART1_CTS, + PMUX_DRVGRP_UART1_RTS, + PMUX_DRVGRP_UART1_RX, + PMUX_DRVGRP_UART1_TX, + PMUX_DRVGRP_UART2_CTS, + PMUX_DRVGRP_UART2_RTS, + PMUX_DRVGRP_UART2_RX, + PMUX_DRVGRP_UART2_TX, + PMUX_DRVGRP_UART3_CTS, + PMUX_DRVGRP_UART3_RTS, + PMUX_DRVGRP_UART3_RX, + PMUX_DRVGRP_UART3_TX, + PMUX_DRVGRP_UART4_CTS, + PMUX_DRVGRP_UART4_RTS, + PMUX_DRVGRP_UART4_RX, + PMUX_DRVGRP_UART4_TX, + PMUX_DRVGRP_USB_VBUS_EN0, + PMUX_DRVGRP_USB_VBUS_EN1, + PMUX_DRVGRP_WIFI_EN, + PMUX_DRVGRP_WIFI_RST, + PMUX_DRVGRP_WIFI_WAKE_AP, + PMUX_DRVGRP_COUNT, +}; + +enum pmux_func { + PMUX_FUNC_DEFAULT, + PMUX_FUNC_AUD, + PMUX_FUNC_BCL, + PMUX_FUNC_BLINK, + PMUX_FUNC_CCLA, + PMUX_FUNC_CEC, + PMUX_FUNC_CLDVFS, + PMUX_FUNC_CLK, + PMUX_FUNC_CORE, + PMUX_FUNC_CPU, + PMUX_FUNC_DISPLAYA, + PMUX_FUNC_DISPLAYB, + PMUX_FUNC_DMIC1, + PMUX_FUNC_DMIC2, + PMUX_FUNC_DMIC3, + PMUX_FUNC_DP, + PMUX_FUNC_DTV, + PMUX_FUNC_EXTPERIPH3, + PMUX_FUNC_I2C1, + PMUX_FUNC_I2C2, + PMUX_FUNC_I2C3, + PMUX_FUNC_I2CPMU, + PMUX_FUNC_I2CVI, + PMUX_FUNC_I2S1, + PMUX_FUNC_I2S2, + PMUX_FUNC_I2S3, + PMUX_FUNC_I2S4A, + PMUX_FUNC_I2S4B, + PMUX_FUNC_I2S5A, + PMUX_FUNC_I2S5B, + PMUX_FUNC_IQC0, + PMUX_FUNC_IQC1, + PMUX_FUNC_JTAG, + PMUX_FUNC_PE, + PMUX_FUNC_PE0, + PMUX_FUNC_PE1, + PMUX_FUNC_PMI, + PMUX_FUNC_PWM0, + PMUX_FUNC_PWM1, + PMUX_FUNC_PWM2, + PMUX_FUNC_PWM3, + PMUX_FUNC_QSPI, + PMUX_FUNC_SATA, + PMUX_FUNC_SDMMC1, + PMUX_FUNC_SDMMC3, + PMUX_FUNC_SHUTDOWN, + PMUX_FUNC_SOC, + PMUX_FUNC_SOR0, + PMUX_FUNC_SOR1, + PMUX_FUNC_SPDIF, + PMUX_FUNC_SPI1, + PMUX_FUNC_SPI2, + PMUX_FUNC_SPI3, + PMUX_FUNC_SPI4, + PMUX_FUNC_SYS, + PMUX_FUNC_TOUCH, + PMUX_FUNC_UART, + PMUX_FUNC_UARTA, + PMUX_FUNC_UARTB, + PMUX_FUNC_UARTC, + PMUX_FUNC_UARTD, + PMUX_FUNC_USB, + PMUX_FUNC_VGP1, + PMUX_FUNC_VGP2, + PMUX_FUNC_VGP3, + PMUX_FUNC_VGP4, + PMUX_FUNC_VGP5, + PMUX_FUNC_VGP6, + PMUX_FUNC_VIMCLK, + PMUX_FUNC_VIMCLK2, + PMUX_FUNC_RSVD0, + PMUX_FUNC_RSVD1, + PMUX_FUNC_RSVD2, + PMUX_FUNC_RSVD3, + PMUX_FUNC_COUNT, +}; + +#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x8d4 +#define TEGRA_PMX_SOC_HAS_IO_CLAMPING +#define TEGRA_PMX_SOC_HAS_DRVGRPS +#define TEGRA_PMX_PINS_HAVE_E_INPUT +#define TEGRA_PMX_PINS_HAVE_LOCK +#define TEGRA_PMX_PINS_HAVE_OD +#define TEGRA_PMX_PINS_HAVE_E_IO_HV +#include + +#endif /* _TEGRA210_PINMUX_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra210/powergate.h b/roms/u-boot/arch/arm/include/asm/arch-tegra210/powergate.h new file mode 100644 index 000000000..ec8f518dd --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra210/powergate.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA210_POWERGATE_H_ +#define _TEGRA210_POWERGATE_H_ + +#include + +#endif /* _TEGRA210_POWERGATE_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra210/sysctr.h b/roms/u-boot/arch/arm/include/asm/arch-tegra210/sysctr.h new file mode 100644 index 000000000..cb1c4997f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra210/sysctr.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation + */ + +#ifndef _TEGRA210_SYSCTR_H_ +#define _TEGRA210_SYSCTR_H_ + +struct sysctr_ctlr { + u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ + u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ + u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ + u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ + u32 reserved1[4]; /* 0x10 - 0x1C */ + u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ + u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ + u32 reserved2[1002]; /* 0x28 - 0xFCC */ + u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ +}; + +#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ +#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ + +#endif /* _TEGRA210_SYSCTR_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra210/tegra.h b/roms/u-boot/arch/arm/include/asm/arch-tegra210/tegra.h new file mode 100644 index 000000000..1c6fba64c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra210/tegra.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation + */ + +#ifndef _TEGRA210_TEGRA_H_ +#define _TEGRA210_TEGRA_H_ + +#define GICD_BASE 0x50041000 /* Generic Int Cntrlr Distrib */ +#define GICC_BASE 0x50042000 /* Generic Int Cntrlr CPU I/F */ +#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */ +#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ +#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */ +#define NV_PA_SDRAM_BASE 0x80000000 + +#include + +#define BCT_ODMDATA_OFFSET 1288 /* offset to ODMDATA word */ + +#undef NVBOOTINFOTABLE_BCTSIZE +#undef NVBOOTINFOTABLE_BCTPTR +#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ +#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ + +#define MAX_NUM_CPU 4 +#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) + +#define TEGRA_USB1_BASE 0x7D000000 + +#endif /* _TEGRA210_TEGRA_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra30/clock-tables.h b/roms/u-boot/arch/arm/include/asm/arch-tegra30/clock-tables.h new file mode 100644 index 000000000..8588009c6 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra30/clock-tables.h @@ -0,0 +1,372 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + */ + +/* Tegra30 clock PLL tables */ + +#ifndef _TEGRA30_CLOCK_TABLES_H_ +#define _TEGRA30_CLOCK_TABLES_H_ + +/* The PLLs supported by the hardware */ +enum clock_id { + CLOCK_ID_FIRST, + CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, + CLOCK_ID_MEMORY, + CLOCK_ID_PERIPH, + CLOCK_ID_AUDIO, + CLOCK_ID_USB, + CLOCK_ID_DISPLAY, + + /* now the simple ones */ + CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_EPCI, + CLOCK_ID_SFROM32KHZ, + + /* These are the base clocks (inputs to the Tegra SOC) */ + CLOCK_ID_32KHZ, + CLOCK_ID_OSC, + CLOCK_ID_CLK_M, + + CLOCK_ID_COUNT, /* number of PLLs */ + CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */ + CLOCK_ID_NONE = -1, +}; + +/* The clocks supported by the hardware */ +enum periph_id { + PERIPH_ID_FIRST, + + /* Low word: 31:0 */ + PERIPH_ID_CPU = PERIPH_ID_FIRST, + PERIPH_ID_COP, + PERIPH_ID_TRIGSYS, + PERIPH_ID_RESERVED3, + PERIPH_ID_RESERVED4, + PERIPH_ID_TMR, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + + /* 8 */ + PERIPH_ID_GPIO, + PERIPH_ID_SDMMC2, + PERIPH_ID_SPDIF, + PERIPH_ID_I2S1, + PERIPH_ID_I2C1, + PERIPH_ID_NDFLASH, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC4, + + /* 16 */ + PERIPH_ID_RESERVED16, + PERIPH_ID_PWM, + PERIPH_ID_I2S2, + PERIPH_ID_EPP, + PERIPH_ID_VI, + PERIPH_ID_2D, + PERIPH_ID_USBD, + PERIPH_ID_ISP, + + /* 24 */ + PERIPH_ID_3D, + PERIPH_ID_RESERVED24, + PERIPH_ID_DISP2, + PERIPH_ID_DISP1, + PERIPH_ID_HOST1X, + PERIPH_ID_VCP, + PERIPH_ID_I2S0, + PERIPH_ID_CACHE2, + + /* Middle word: 63:32 */ + PERIPH_ID_MEM, + PERIPH_ID_AHBDMA, + PERIPH_ID_APBDMA, + PERIPH_ID_RESERVED35, + PERIPH_ID_KBC, + PERIPH_ID_STAT_MON, + PERIPH_ID_PMC, + PERIPH_ID_FUSE, + + /* 40 */ + PERIPH_ID_KFUSE, + PERIPH_ID_SBC1, + PERIPH_ID_SNOR, + PERIPH_ID_RESERVED43, + PERIPH_ID_SBC2, + PERIPH_ID_RESERVED45, + PERIPH_ID_SBC3, + PERIPH_ID_DVC_I2C, + + /* 48 */ + PERIPH_ID_DSI, + PERIPH_ID_TVO, + PERIPH_ID_MIPI, + PERIPH_ID_HDMI, + PERIPH_ID_CSI, + PERIPH_ID_TVDAC, + PERIPH_ID_I2C2, + PERIPH_ID_UART3, + + /* 56 */ + PERIPH_ID_RESERVED56, + PERIPH_ID_EMC, + PERIPH_ID_USB2, + PERIPH_ID_USB3, + PERIPH_ID_MPE, + PERIPH_ID_VDE, + PERIPH_ID_BSEA, + PERIPH_ID_BSEV, + + /* Upper word 95:64 */ + PERIPH_ID_SPEEDO, + PERIPH_ID_UART4, + PERIPH_ID_UART5, + PERIPH_ID_I2C3, + PERIPH_ID_SBC4, + PERIPH_ID_SDMMC3, + PERIPH_ID_PCIE, + PERIPH_ID_OWR, + + /* 72 */ + PERIPH_ID_AFI, + PERIPH_ID_CORESIGHT, + PERIPH_ID_PCIEXCLK, + PERIPH_ID_AVPUCQ, + PERIPH_ID_RESERVED76, + PERIPH_ID_RESERVED77, + PERIPH_ID_RESERVED78, + PERIPH_ID_DTV, + + /* 80 */ + PERIPH_ID_NANDSPEED, + PERIPH_ID_I2CSLOW, + PERIPH_ID_DSIB, + PERIPH_ID_RESERVED83, + PERIPH_ID_IRAMA, + PERIPH_ID_IRAMB, + PERIPH_ID_IRAMC, + PERIPH_ID_IRAMD, + + /* 88 */ + PERIPH_ID_CRAM2, + PERIPH_ID_RESERVED89, + PERIPH_ID_MDOUBLER, + PERIPH_ID_RESERVED91, + PERIPH_ID_SUSOUT, + PERIPH_ID_RESERVED93, + PERIPH_ID_RESERVED94, + PERIPH_ID_RESERVED95, + + PERIPH_ID_VW_FIRST, + /* V word: 31:0 */ + PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST, + PERIPH_ID_CPULP, + PERIPH_ID_3D2, + PERIPH_ID_MSELECT, + PERIPH_ID_TSENSOR, + PERIPH_ID_I2S3, + PERIPH_ID_I2S4, + PERIPH_ID_I2C4, + + /* 08 */ + PERIPH_ID_SBC5, + PERIPH_ID_SBC6, + PERIPH_ID_AUDIO, + PERIPH_ID_APBIF, + PERIPH_ID_DAM0, + PERIPH_ID_DAM1, + PERIPH_ID_DAM2, + PERIPH_ID_HDA2CODEC2X, + + /* 16 */ + PERIPH_ID_ATOMICS, + PERIPH_ID_EX_RESERVED17, + PERIPH_ID_EX_RESERVED18, + PERIPH_ID_EX_RESERVED19, + PERIPH_ID_EX_RESERVED20, + PERIPH_ID_EX_RESERVED21, + PERIPH_ID_EX_RESERVED22, + PERIPH_ID_ACTMON, + + /* 24 */ + PERIPH_ID_EX_RESERVED24, + PERIPH_ID_EX_RESERVED25, + PERIPH_ID_EX_RESERVED26, + PERIPH_ID_EX_RESERVED27, + PERIPH_ID_SATA, + PERIPH_ID_HDA, + PERIPH_ID_EX_RESERVED30, + PERIPH_ID_EX_RESERVED31, + + /* W word: 31:0 */ + PERIPH_ID_HDA2HDMICODEC, + PERIPH_ID_SATACOLD, + PERIPH_ID_RESERVED0_PCIERX0, + PERIPH_ID_RESERVED1_PCIERX1, + PERIPH_ID_RESERVED2_PCIERX2, + PERIPH_ID_RESERVED3_PCIERX3, + PERIPH_ID_RESERVED4_PCIERX4, + PERIPH_ID_RESERVED5_PCIERX5, + + /* 40 */ + PERIPH_ID_CEC, + PERIPH_ID_RESERVED6_PCIE2, + PERIPH_ID_RESERVED7_EMC, + PERIPH_ID_RESERVED8_HDMI, + PERIPH_ID_RESERVED9_SATA, + PERIPH_ID_RESERVED10_MIPI, + PERIPH_ID_EX_RESERVED46, + PERIPH_ID_EX_RESERVED47, + + PERIPH_ID_COUNT, + PERIPH_ID_NONE = -1, +}; + +enum pll_out_id { + PLL_OUT1, + PLL_OUT2, + PLL_OUT3, + PLL_OUT4 +}; + +/* + * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want + * callers to use the PERIPH_ID for all access to peripheral clocks to avoid + * confusion bewteen PERIPH_ID_... and PERIPHC_... + * + * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be + * confusing. + */ +enum periphc_internal_id { + /* 0x00 */ + PERIPHC_I2S1, + PERIPHC_I2S2, + PERIPHC_SPDIF_OUT, + PERIPHC_SPDIF_IN, + PERIPHC_PWM, + PERIPHC_05h, + PERIPHC_SBC2, + PERIPHC_SBC3, + + /* 0x08 */ + PERIPHC_08h, + PERIPHC_I2C1, + PERIPHC_DVC_I2C, + PERIPHC_0bh, + PERIPHC_0ch, + PERIPHC_SBC1, + PERIPHC_DISP1, + PERIPHC_DISP2, + + /* 0x10 */ + PERIPHC_CVE, + PERIPHC_11h, + PERIPHC_VI, + PERIPHC_13h, + PERIPHC_SDMMC1, + PERIPHC_SDMMC2, + PERIPHC_G3D, + PERIPHC_G2D, + + /* 0x18 */ + PERIPHC_NDFLASH, + PERIPHC_SDMMC4, + PERIPHC_VFIR, + PERIPHC_EPP, + PERIPHC_MPE, + PERIPHC_MIPI, + PERIPHC_UART1, + PERIPHC_UART2, + + /* 0x20 */ + PERIPHC_HOST1X, + PERIPHC_21h, + PERIPHC_TVO, + PERIPHC_HDMI, + PERIPHC_24h, + PERIPHC_TVDAC, + PERIPHC_I2C2, + PERIPHC_EMC, + + /* 0x28 */ + PERIPHC_UART3, + PERIPHC_29h, + PERIPHC_VI_SENSOR, + PERIPHC_2bh, + PERIPHC_2ch, + PERIPHC_SBC4, + PERIPHC_I2C3, + PERIPHC_SDMMC3, + + /* 0x30 */ + PERIPHC_UART4, + PERIPHC_UART5, + PERIPHC_VDE, + PERIPHC_OWR, + PERIPHC_NOR, + PERIPHC_CSITE, + PERIPHC_I2S0, + PERIPHC_37h, + + PERIPHC_VW_FIRST, + /* 0x38 */ + PERIPHC_G3D2 = PERIPHC_VW_FIRST, + PERIPHC_MSELECT, + PERIPHC_TSENSOR, + PERIPHC_I2S3, + PERIPHC_I2S4, + PERIPHC_I2C4, + PERIPHC_SBC5, + PERIPHC_SBC6, + + /* 0x40 */ + PERIPHC_AUDIO, + PERIPHC_41h, + PERIPHC_DAM0, + PERIPHC_DAM1, + PERIPHC_DAM2, + PERIPHC_HDA2CODEC2X, + PERIPHC_ACTMON, + PERIPHC_EXTPERIPH1, + + /* 0x48 */ + PERIPHC_EXTPERIPH2, + PERIPHC_EXTPERIPH3, + PERIPHC_NANDSPEED, + PERIPHC_I2CSLOW, + PERIPHC_SYS, + PERIPHC_SPEEDO, + PERIPHC_4eh, + PERIPHC_4fh, + + /* 0x50 */ + PERIPHC_50h, + PERIPHC_51h, + PERIPHC_52h, + PERIPHC_53h, + PERIPHC_SATAOOB, + PERIPHC_SATA, + PERIPHC_HDA, + + PERIPHC_COUNT, + + PERIPHC_NONE = -1, +}; + +/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */ +#define PERIPH_REG(id) \ + (id < PERIPH_ID_VW_FIRST) ? \ + ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5) + +/* Mask value for a clock (within PERIPH_REG(id)) */ +#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) + +/* return 1 if a PLL ID is in range */ +#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) + +/* return 1 if a peripheral ID is in range */ +#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ + (id) < PERIPH_ID_COUNT) + +#endif /* _TEGRA30_CLOCK_TABLES_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra30/clock.h b/roms/u-boot/arch/arm/include/asm/arch-tegra30/clock.h new file mode 100644 index 000000000..7f5a115bc --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra30/clock.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + */ + +/* Tegra30 clock control functions */ + +#ifndef _TEGRA30_CLOCK_H_ +#define _TEGRA30_CLOCK_H_ + +#include + +/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ +#define OSC_FREQ_SHIFT 28 +#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) + +int tegra_plle_enable(void); + +#endif /* _TEGRA30_CLOCK_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra30/flow.h b/roms/u-boot/arch/arm/include/asm/arch-tegra30/flow.h new file mode 100644 index 000000000..f3e947e9e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra30/flow.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA30_FLOW_H_ +#define _TEGRA30_FLOW_H_ + +struct flow_ctlr { + u32 halt_cpu_events; + u32 halt_cop_events; + u32 cpu_csr; + u32 cop_csr; + u32 xrq_events; + u32 halt_cpu1_events; + u32 cpu1_csr; + u32 halt_cpu2_events; + u32 cpu2_csr; + u32 halt_cpu3_events; + u32 cpu3_csr; + u32 cluster_control; +}; + +#endif /* _TEGRA30_FLOW_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra30/funcmux.h b/roms/u-boot/arch/arm/include/asm/arch-tegra30/funcmux.h new file mode 100644 index 000000000..2e8b33591 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra30/funcmux.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + */ + +/* Tegra30 high-level function multiplexing */ + +#ifndef _TEGRA30_FUNCMUX_H_ +#define _TEGRA30_FUNCMUX_H_ + +#include + +/* Configs supported by the func mux */ +enum { + FUNCMUX_DEFAULT = 0, /* default config */ + + /* UART configs */ + FUNCMUX_UART1_ULPI = 0, +}; +#endif /* _TEGRA30_FUNCMUX_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra30/gp_padctrl.h b/roms/u-boot/arch/arm/include/asm/arch-tegra30/gp_padctrl.h new file mode 100644 index 000000000..4ff785de8 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra30/gp_padctrl.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA30_GP_PADCTRL_H_ +#define _TEGRA30_GP_PADCTRL_H_ + +#include + +/* APB_MISC_GP and padctrl registers */ +struct apb_misc_gp_ctlr { + u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ + u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ + u32 reserved0[22]; /* 0x08 - 0x5C: */ + u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ + u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ + u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ + u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ + u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ + u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ + u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ + u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ + u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ + u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ + u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ + u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */ + u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ + u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ + u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ + u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ + u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ + u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */ + u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */ + u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */ + u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ + u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ + u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ + u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ + u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ + u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ + u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */ + u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */ + u32 reserved1[7]; /* 0xD0-0xE8: */ + u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ +}; + +/* SDMMC1/3 settings from section 24.6 of T30 TRM */ +#define SDIOCFG_DRVUP_SLWF 1 +#define SDIOCFG_DRVDN_SLWR 1 +#define SDIOCFG_DRVUP 0x2E +#define SDIOCFG_DRVDN 0x2A + +#endif /* _TEGRA30_GP_PADCTRL_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra30/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-tegra30/gpio.h new file mode 100644 index 000000000..1dd2e426b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra30/gpio.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA30_GPIO_H_ +#define _TEGRA30_GPIO_H_ + +/* + * The Tegra 3x GPIO controller has 246 GPIOS in 8 banks of 4 ports, + * each with 8 GPIOs. + */ +#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ +#define TEGRA_GPIO_BANKS 8 /* number of banks */ + +#include + +/* GPIO Controller registers for a single bank */ +struct gpio_ctlr_bank { + uint gpio_config[TEGRA_GPIO_PORTS]; + uint gpio_dir_out[TEGRA_GPIO_PORTS]; + uint gpio_out[TEGRA_GPIO_PORTS]; + uint gpio_in[TEGRA_GPIO_PORTS]; + uint gpio_int_status[TEGRA_GPIO_PORTS]; + uint gpio_int_enable[TEGRA_GPIO_PORTS]; + uint gpio_int_level[TEGRA_GPIO_PORTS]; + uint gpio_int_clear[TEGRA_GPIO_PORTS]; + uint gpio_masked_config[TEGRA_GPIO_PORTS]; + uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; + uint gpio_masked_out[TEGRA_GPIO_PORTS]; + uint gpio_masked_in[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_clear[TEGRA_GPIO_PORTS]; +}; + +struct gpio_ctlr { + struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; +}; + +#endif /* _TEGRA30_GPIO_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra30/mc.h b/roms/u-boot/arch/arm/include/asm/arch-tegra30/mc.h new file mode 100644 index 000000000..bbb0fe77b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra30/mc.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2014 + * NVIDIA Corporation + */ + +#ifndef _TEGRA30_MC_H_ +#define _TEGRA30_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[4]; /* offset 0x00 - 0x0C */ + u32 mc_smmu_config; /* offset 0x10 */ + u32 mc_smmu_tlb_config; /* offset 0x14 */ + u32 mc_smmu_ptc_config; /* offset 0x18 */ + u32 mc_smmu_ptb_asid; /* offset 0x1C */ + u32 mc_smmu_ptb_data; /* offset 0x20 */ + u32 reserved1[3]; /* offset 0x24 - 0x2C */ + u32 mc_smmu_tlb_flush; /* offset 0x30 */ + u32 mc_smmu_ptc_flush; /* offset 0x34 */ + u32 mc_smmu_asid_security; /* offset 0x38 */ + u32 reserved2[5]; /* offset 0x3C - 0x4C */ + u32 mc_emem_cfg; /* offset 0x50 */ + u32 mc_emem_adr_cfg; /* offset 0x54 */ + u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ + u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ + u32 reserved3[12]; /* offset 0x60 - 0x8C */ + u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ + u32 reserved4[338]; /* offset 0x100 - 0x644 */ + u32 mc_video_protect_bom; /* offset 0x648 */ + u32 mc_video_protect_size_mb; /* offset 0x64c */ + u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ +}; + +#endif /* _TEGRA30_MC_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra30/pinmux.h b/roms/u-boot/arch/arm/include/asm/arch-tegra30/pinmux.h new file mode 100644 index 000000000..1261943f5 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra30/pinmux.h @@ -0,0 +1,404 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA30_PINMUX_H_ +#define _TEGRA30_PINMUX_H_ + +enum pmux_pingrp { + PMUX_PINGRP_ULPI_DATA0_PO1, + PMUX_PINGRP_ULPI_DATA1_PO2, + PMUX_PINGRP_ULPI_DATA2_PO3, + PMUX_PINGRP_ULPI_DATA3_PO4, + PMUX_PINGRP_ULPI_DATA4_PO5, + PMUX_PINGRP_ULPI_DATA5_PO6, + PMUX_PINGRP_ULPI_DATA6_PO7, + PMUX_PINGRP_ULPI_DATA7_PO0, + PMUX_PINGRP_ULPI_CLK_PY0, + PMUX_PINGRP_ULPI_DIR_PY1, + PMUX_PINGRP_ULPI_NXT_PY2, + PMUX_PINGRP_ULPI_STP_PY3, + PMUX_PINGRP_DAP3_FS_PP0, + PMUX_PINGRP_DAP3_DIN_PP1, + PMUX_PINGRP_DAP3_DOUT_PP2, + PMUX_PINGRP_DAP3_SCLK_PP3, + PMUX_PINGRP_PV0, + PMUX_PINGRP_PV1, + PMUX_PINGRP_SDMMC1_CLK_PZ0, + PMUX_PINGRP_SDMMC1_CMD_PZ1, + PMUX_PINGRP_SDMMC1_DAT3_PY4, + PMUX_PINGRP_SDMMC1_DAT2_PY5, + PMUX_PINGRP_SDMMC1_DAT1_PY6, + PMUX_PINGRP_SDMMC1_DAT0_PY7, + PMUX_PINGRP_PV2, + PMUX_PINGRP_PV3, + PMUX_PINGRP_CLK2_OUT_PW5, + PMUX_PINGRP_CLK2_REQ_PCC5, + PMUX_PINGRP_LCD_PWR1_PC1, + PMUX_PINGRP_LCD_PWR2_PC6, + PMUX_PINGRP_LCD_SDIN_PZ2, + PMUX_PINGRP_LCD_SDOUT_PN5, + PMUX_PINGRP_LCD_WR_N_PZ3, + PMUX_PINGRP_LCD_CS0_N_PN4, + PMUX_PINGRP_LCD_DC0_PN6, + PMUX_PINGRP_LCD_SCK_PZ4, + PMUX_PINGRP_LCD_PWR0_PB2, + PMUX_PINGRP_LCD_PCLK_PB3, + PMUX_PINGRP_LCD_DE_PJ1, + PMUX_PINGRP_LCD_HSYNC_PJ3, + PMUX_PINGRP_LCD_VSYNC_PJ4, + PMUX_PINGRP_LCD_D0_PE0, + PMUX_PINGRP_LCD_D1_PE1, + PMUX_PINGRP_LCD_D2_PE2, + PMUX_PINGRP_LCD_D3_PE3, + PMUX_PINGRP_LCD_D4_PE4, + PMUX_PINGRP_LCD_D5_PE5, + PMUX_PINGRP_LCD_D6_PE6, + PMUX_PINGRP_LCD_D7_PE7, + PMUX_PINGRP_LCD_D8_PF0, + PMUX_PINGRP_LCD_D9_PF1, + PMUX_PINGRP_LCD_D10_PF2, + PMUX_PINGRP_LCD_D11_PF3, + PMUX_PINGRP_LCD_D12_PF4, + PMUX_PINGRP_LCD_D13_PF5, + PMUX_PINGRP_LCD_D14_PF6, + PMUX_PINGRP_LCD_D15_PF7, + PMUX_PINGRP_LCD_D16_PM0, + PMUX_PINGRP_LCD_D17_PM1, + PMUX_PINGRP_LCD_D18_PM2, + PMUX_PINGRP_LCD_D19_PM3, + PMUX_PINGRP_LCD_D20_PM4, + PMUX_PINGRP_LCD_D21_PM5, + PMUX_PINGRP_LCD_D22_PM6, + PMUX_PINGRP_LCD_D23_PM7, + PMUX_PINGRP_LCD_CS1_N_PW0, + PMUX_PINGRP_LCD_M1_PW1, + PMUX_PINGRP_LCD_DC1_PD2, + PMUX_PINGRP_HDMI_INT_PN7, + PMUX_PINGRP_DDC_SCL_PV4, + PMUX_PINGRP_DDC_SDA_PV5, + PMUX_PINGRP_CRT_HSYNC_PV6, + PMUX_PINGRP_CRT_VSYNC_PV7, + PMUX_PINGRP_VI_D0_PT4, + PMUX_PINGRP_VI_D1_PD5, + PMUX_PINGRP_VI_D2_PL0, + PMUX_PINGRP_VI_D3_PL1, + PMUX_PINGRP_VI_D4_PL2, + PMUX_PINGRP_VI_D5_PL3, + PMUX_PINGRP_VI_D6_PL4, + PMUX_PINGRP_VI_D7_PL5, + PMUX_PINGRP_VI_D8_PL6, + PMUX_PINGRP_VI_D9_PL7, + PMUX_PINGRP_VI_D10_PT2, + PMUX_PINGRP_VI_D11_PT3, + PMUX_PINGRP_VI_PCLK_PT0, + PMUX_PINGRP_VI_MCLK_PT1, + PMUX_PINGRP_VI_VSYNC_PD6, + PMUX_PINGRP_VI_HSYNC_PD7, + PMUX_PINGRP_UART2_RXD_PC3, + PMUX_PINGRP_UART2_TXD_PC2, + PMUX_PINGRP_UART2_RTS_N_PJ6, + PMUX_PINGRP_UART2_CTS_N_PJ5, + PMUX_PINGRP_UART3_TXD_PW6, + PMUX_PINGRP_UART3_RXD_PW7, + PMUX_PINGRP_UART3_CTS_N_PA1, + PMUX_PINGRP_UART3_RTS_N_PC0, + PMUX_PINGRP_PU0, + PMUX_PINGRP_PU1, + PMUX_PINGRP_PU2, + PMUX_PINGRP_PU3, + PMUX_PINGRP_PU4, + PMUX_PINGRP_PU5, + PMUX_PINGRP_PU6, + PMUX_PINGRP_GEN1_I2C_SDA_PC5, + PMUX_PINGRP_GEN1_I2C_SCL_PC4, + PMUX_PINGRP_DAP4_FS_PP4, + PMUX_PINGRP_DAP4_DIN_PP5, + PMUX_PINGRP_DAP4_DOUT_PP6, + PMUX_PINGRP_DAP4_SCLK_PP7, + PMUX_PINGRP_CLK3_OUT_PEE0, + PMUX_PINGRP_CLK3_REQ_PEE1, + PMUX_PINGRP_GMI_WP_N_PC7, + PMUX_PINGRP_GMI_IORDY_PI5, + PMUX_PINGRP_GMI_WAIT_PI7, + PMUX_PINGRP_GMI_ADV_N_PK0, + PMUX_PINGRP_GMI_CLK_PK1, + PMUX_PINGRP_GMI_CS0_N_PJ0, + PMUX_PINGRP_GMI_CS1_N_PJ2, + PMUX_PINGRP_GMI_CS2_N_PK3, + PMUX_PINGRP_GMI_CS3_N_PK4, + PMUX_PINGRP_GMI_CS4_N_PK2, + PMUX_PINGRP_GMI_CS6_N_PI3, + PMUX_PINGRP_GMI_CS7_N_PI6, + PMUX_PINGRP_GMI_AD0_PG0, + PMUX_PINGRP_GMI_AD1_PG1, + PMUX_PINGRP_GMI_AD2_PG2, + PMUX_PINGRP_GMI_AD3_PG3, + PMUX_PINGRP_GMI_AD4_PG4, + PMUX_PINGRP_GMI_AD5_PG5, + PMUX_PINGRP_GMI_AD6_PG6, + PMUX_PINGRP_GMI_AD7_PG7, + PMUX_PINGRP_GMI_AD8_PH0, + PMUX_PINGRP_GMI_AD9_PH1, + PMUX_PINGRP_GMI_AD10_PH2, + PMUX_PINGRP_GMI_AD11_PH3, + PMUX_PINGRP_GMI_AD12_PH4, + PMUX_PINGRP_GMI_AD13_PH5, + PMUX_PINGRP_GMI_AD14_PH6, + PMUX_PINGRP_GMI_AD15_PH7, + PMUX_PINGRP_GMI_A16_PJ7, + PMUX_PINGRP_GMI_A17_PB0, + PMUX_PINGRP_GMI_A18_PB1, + PMUX_PINGRP_GMI_A19_PK7, + PMUX_PINGRP_GMI_WR_N_PI0, + PMUX_PINGRP_GMI_OE_N_PI1, + PMUX_PINGRP_GMI_DQS_PI2, + PMUX_PINGRP_GMI_RST_N_PI4, + PMUX_PINGRP_GEN2_I2C_SCL_PT5, + PMUX_PINGRP_GEN2_I2C_SDA_PT6, + PMUX_PINGRP_SDMMC4_CLK_PCC4, + PMUX_PINGRP_SDMMC4_CMD_PT7, + PMUX_PINGRP_SDMMC4_DAT0_PAA0, + PMUX_PINGRP_SDMMC4_DAT1_PAA1, + PMUX_PINGRP_SDMMC4_DAT2_PAA2, + PMUX_PINGRP_SDMMC4_DAT3_PAA3, + PMUX_PINGRP_SDMMC4_DAT4_PAA4, + PMUX_PINGRP_SDMMC4_DAT5_PAA5, + PMUX_PINGRP_SDMMC4_DAT6_PAA6, + PMUX_PINGRP_SDMMC4_DAT7_PAA7, + PMUX_PINGRP_SDMMC4_RST_N_PCC3, + PMUX_PINGRP_CAM_MCLK_PCC0, + PMUX_PINGRP_PCC1, + PMUX_PINGRP_PBB0, + PMUX_PINGRP_CAM_I2C_SCL_PBB1, + PMUX_PINGRP_CAM_I2C_SDA_PBB2, + PMUX_PINGRP_PBB3, + PMUX_PINGRP_PBB4, + PMUX_PINGRP_PBB5, + PMUX_PINGRP_PBB6, + PMUX_PINGRP_PBB7, + PMUX_PINGRP_PCC2, + PMUX_PINGRP_JTAG_RTCK_PU7, + PMUX_PINGRP_PWR_I2C_SCL_PZ6, + PMUX_PINGRP_PWR_I2C_SDA_PZ7, + PMUX_PINGRP_KB_ROW0_PR0, + PMUX_PINGRP_KB_ROW1_PR1, + PMUX_PINGRP_KB_ROW2_PR2, + PMUX_PINGRP_KB_ROW3_PR3, + PMUX_PINGRP_KB_ROW4_PR4, + PMUX_PINGRP_KB_ROW5_PR5, + PMUX_PINGRP_KB_ROW6_PR6, + PMUX_PINGRP_KB_ROW7_PR7, + PMUX_PINGRP_KB_ROW8_PS0, + PMUX_PINGRP_KB_ROW9_PS1, + PMUX_PINGRP_KB_ROW10_PS2, + PMUX_PINGRP_KB_ROW11_PS3, + PMUX_PINGRP_KB_ROW12_PS4, + PMUX_PINGRP_KB_ROW13_PS5, + PMUX_PINGRP_KB_ROW14_PS6, + PMUX_PINGRP_KB_ROW15_PS7, + PMUX_PINGRP_KB_COL0_PQ0, + PMUX_PINGRP_KB_COL1_PQ1, + PMUX_PINGRP_KB_COL2_PQ2, + PMUX_PINGRP_KB_COL3_PQ3, + PMUX_PINGRP_KB_COL4_PQ4, + PMUX_PINGRP_KB_COL5_PQ5, + PMUX_PINGRP_KB_COL6_PQ6, + PMUX_PINGRP_KB_COL7_PQ7, + PMUX_PINGRP_CLK_32K_OUT_PA0, + PMUX_PINGRP_SYS_CLK_REQ_PZ5, + PMUX_PINGRP_CORE_PWR_REQ, + PMUX_PINGRP_CPU_PWR_REQ, + PMUX_PINGRP_PWR_INT_N, + PMUX_PINGRP_CLK_32K_IN, + PMUX_PINGRP_OWR, + PMUX_PINGRP_DAP1_FS_PN0, + PMUX_PINGRP_DAP1_DIN_PN1, + PMUX_PINGRP_DAP1_DOUT_PN2, + PMUX_PINGRP_DAP1_SCLK_PN3, + PMUX_PINGRP_CLK1_REQ_PEE2, + PMUX_PINGRP_CLK1_OUT_PW4, + PMUX_PINGRP_SPDIF_IN_PK6, + PMUX_PINGRP_SPDIF_OUT_PK5, + PMUX_PINGRP_DAP2_FS_PA2, + PMUX_PINGRP_DAP2_DIN_PA4, + PMUX_PINGRP_DAP2_DOUT_PA5, + PMUX_PINGRP_DAP2_SCLK_PA3, + PMUX_PINGRP_SPI2_MOSI_PX0, + PMUX_PINGRP_SPI2_MISO_PX1, + PMUX_PINGRP_SPI2_CS0_N_PX3, + PMUX_PINGRP_SPI2_SCK_PX2, + PMUX_PINGRP_SPI1_MOSI_PX4, + PMUX_PINGRP_SPI1_SCK_PX5, + PMUX_PINGRP_SPI1_CS0_N_PX6, + PMUX_PINGRP_SPI1_MISO_PX7, + PMUX_PINGRP_SPI2_CS1_N_PW2, + PMUX_PINGRP_SPI2_CS2_N_PW3, + PMUX_PINGRP_SDMMC3_CLK_PA6, + PMUX_PINGRP_SDMMC3_CMD_PA7, + PMUX_PINGRP_SDMMC3_DAT0_PB7, + PMUX_PINGRP_SDMMC3_DAT1_PB6, + PMUX_PINGRP_SDMMC3_DAT2_PB5, + PMUX_PINGRP_SDMMC3_DAT3_PB4, + PMUX_PINGRP_SDMMC3_DAT4_PD1, + PMUX_PINGRP_SDMMC3_DAT5_PD0, + PMUX_PINGRP_SDMMC3_DAT6_PD3, + PMUX_PINGRP_SDMMC3_DAT7_PD4, + PMUX_PINGRP_PEX_L0_PRSNT_N_PDD0, + PMUX_PINGRP_PEX_L0_RST_N_PDD1, + PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2, + PMUX_PINGRP_PEX_WAKE_N_PDD3, + PMUX_PINGRP_PEX_L1_PRSNT_N_PDD4, + PMUX_PINGRP_PEX_L1_RST_N_PDD5, + PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6, + PMUX_PINGRP_PEX_L2_PRSNT_N_PDD7, + PMUX_PINGRP_PEX_L2_RST_N_PCC6, + PMUX_PINGRP_PEX_L2_CLKREQ_N_PCC7, + PMUX_PINGRP_HDMI_CEC_PEE3, + PMUX_PINGRP_COUNT, +}; + +enum pmux_drvgrp { + PMUX_DRVGRP_AO1, + PMUX_DRVGRP_AO2, + PMUX_DRVGRP_AT1, + PMUX_DRVGRP_AT2, + PMUX_DRVGRP_AT3, + PMUX_DRVGRP_AT4, + PMUX_DRVGRP_AT5, + PMUX_DRVGRP_CDEV1, + PMUX_DRVGRP_CDEV2, + PMUX_DRVGRP_CSUS, + PMUX_DRVGRP_DAP1, + PMUX_DRVGRP_DAP2, + PMUX_DRVGRP_DAP3, + PMUX_DRVGRP_DAP4, + PMUX_DRVGRP_DBG, + PMUX_DRVGRP_LCD1, + PMUX_DRVGRP_LCD2, + PMUX_DRVGRP_SDIO2, + PMUX_DRVGRP_SDIO3, + PMUX_DRVGRP_SPI, + PMUX_DRVGRP_UAA, + PMUX_DRVGRP_UAB, + PMUX_DRVGRP_UART2, + PMUX_DRVGRP_UART3, + PMUX_DRVGRP_VI1, + PMUX_DRVGRP_SDIO1 = (0x84 / 4), + PMUX_DRVGRP_CRT = (0x90 / 4), + PMUX_DRVGRP_DDC, + PMUX_DRVGRP_GMA, + PMUX_DRVGRP_GMB, + PMUX_DRVGRP_GMC, + PMUX_DRVGRP_GMD, + PMUX_DRVGRP_GME, + PMUX_DRVGRP_GMF, + PMUX_DRVGRP_GMG, + PMUX_DRVGRP_GMH, + PMUX_DRVGRP_OWR, + PMUX_DRVGRP_UDA, + PMUX_DRVGRP_GPV, + PMUX_DRVGRP_DEV3, + PMUX_DRVGRP_CEC = (0xd0 / 4), + PMUX_DRVGRP_COUNT, +}; + +enum pmux_func { + PMUX_FUNC_DEFAULT, + PMUX_FUNC_BLINK, + PMUX_FUNC_CEC, + PMUX_FUNC_CLK_12M_OUT, + PMUX_FUNC_CLK_32K_IN, + PMUX_FUNC_CORE_PWR_REQ, + PMUX_FUNC_CPU_PWR_REQ, + PMUX_FUNC_CRT, + PMUX_FUNC_DAP, + PMUX_FUNC_DDR, + PMUX_FUNC_DEV3, + PMUX_FUNC_DISPLAYA, + PMUX_FUNC_DISPLAYB, + PMUX_FUNC_DTV, + PMUX_FUNC_EXTPERIPH1, + PMUX_FUNC_EXTPERIPH2, + PMUX_FUNC_EXTPERIPH3, + PMUX_FUNC_GMI, + PMUX_FUNC_GMI_ALT, + PMUX_FUNC_HDA, + PMUX_FUNC_HDCP, + PMUX_FUNC_HDMI, + PMUX_FUNC_HSI, + PMUX_FUNC_I2C1, + PMUX_FUNC_I2C2, + PMUX_FUNC_I2C3, + PMUX_FUNC_I2C4, + PMUX_FUNC_I2CPWR, + PMUX_FUNC_I2S0, + PMUX_FUNC_I2S1, + PMUX_FUNC_I2S2, + PMUX_FUNC_I2S3, + PMUX_FUNC_I2S4, + PMUX_FUNC_INVALID, + PMUX_FUNC_KBC, + PMUX_FUNC_MIO, + PMUX_FUNC_NAND, + PMUX_FUNC_NAND_ALT, + PMUX_FUNC_OWR, + PMUX_FUNC_PCIE, + PMUX_FUNC_PWM0, + PMUX_FUNC_PWM1, + PMUX_FUNC_PWM2, + PMUX_FUNC_PWM3, + PMUX_FUNC_PWR_INT_N, + PMUX_FUNC_RTCK, + PMUX_FUNC_SATA, + PMUX_FUNC_SDMMC1, + PMUX_FUNC_SDMMC2, + PMUX_FUNC_SDMMC3, + PMUX_FUNC_SDMMC4, + PMUX_FUNC_SPDIF, + PMUX_FUNC_SPI1, + PMUX_FUNC_SPI2, + PMUX_FUNC_SPI2_ALT, + PMUX_FUNC_SPI3, + PMUX_FUNC_SPI4, + PMUX_FUNC_SPI5, + PMUX_FUNC_SPI6, + PMUX_FUNC_SYSCLK, + PMUX_FUNC_TEST, + PMUX_FUNC_TRACE, + PMUX_FUNC_UARTA, + PMUX_FUNC_UARTB, + PMUX_FUNC_UARTC, + PMUX_FUNC_UARTD, + PMUX_FUNC_UARTE, + PMUX_FUNC_ULPI, + PMUX_FUNC_VGP1, + PMUX_FUNC_VGP2, + PMUX_FUNC_VGP3, + PMUX_FUNC_VGP4, + PMUX_FUNC_VGP5, + PMUX_FUNC_VGP6, + PMUX_FUNC_VI, + PMUX_FUNC_VI_ALT1, + PMUX_FUNC_VI_ALT2, + PMUX_FUNC_VI_ALT3, + PMUX_FUNC_RSVD1, + PMUX_FUNC_RSVD2, + PMUX_FUNC_RSVD3, + PMUX_FUNC_RSVD4, + PMUX_FUNC_COUNT, +}; + +#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 +#define TEGRA_PMX_SOC_HAS_DRVGRPS +#define TEGRA_PMX_GRPS_HAVE_LPMD +#define TEGRA_PMX_GRPS_HAVE_SCHMT +#define TEGRA_PMX_GRPS_HAVE_HSM +#define TEGRA_PMX_PINS_HAVE_E_INPUT +#define TEGRA_PMX_PINS_HAVE_LOCK +#define TEGRA_PMX_PINS_HAVE_OD +#define TEGRA_PMX_PINS_HAVE_IO_RESET +#include + +#endif /* _TEGRA30_PINMUX_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra30/powergate.h b/roms/u-boot/arch/arm/include/asm/arch-tegra30/powergate.h new file mode 100644 index 000000000..c70e44b62 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra30/powergate.h @@ -0,0 +1,6 @@ +#ifndef _TEGRA30_POWERGATE_H_ +#define _TEGRA30_POWERGATE_H_ + +#include + +#endif /* _TEGRA30_POWERGATE_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-tegra30/tegra.h b/roms/u-boot/arch/arm/include/asm/arch-tegra30/tegra.h new file mode 100644 index 000000000..1de7d2ff2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-tegra30/tegra.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA30_H_ +#define _TEGRA30_H_ + +#define NV_PA_MC_BASE 0x7000F000 +#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */ + +#include + +#define TEGRA_USB1_BASE 0x7D000000 + +#define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */ + +#define MAX_NUM_CPU 4 + +#endif /* TEGRA30_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-vf610/clock.h b/roms/u-boot/arch/arm/include/asm/arch-vf610/clock.h new file mode 100644 index 000000000..ec9786ce4 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-vf610/clock.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_BUS_CLK, + MXC_IPG_CLK, + MXC_UART_CLK, + MXC_ESDHC_CLK, + MXC_FEC_CLK, + MXC_I2C_CLK, + MXC_DSPI_CLK, +}; + +void enable_ocotp_clk(unsigned char enable); +unsigned int mxc_get_clock(enum mxc_clock clk); +u32 get_lpuart_clk(void); +#ifdef CONFIG_SYS_I2C_MXC +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); +#endif + +#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-vf610/crm_regs.h b/roms/u-boot/arch/arm/include/asm/arch-vf610/crm_regs.h new file mode 100644 index 000000000..0c9ed5293 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -0,0 +1,275 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + */ + +#ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__ +#define __ARCH_ARM_MACH_VF610_CCM_REGS_H__ + +#ifndef __ASSEMBLY__ + +#include + +/* Clock Controller Module (CCM) */ +struct ccm_reg { + u32 ccr; + u32 csr; + u32 ccsr; + u32 cacrr; + u32 cscmr1; + u32 cscdr1; + u32 cscdr2; + u32 cscdr3; + u32 cscmr2; + u32 cscdr4; + u32 ctor; + u32 clpcr; + u32 cisr; + u32 cimr; + u32 ccosr; + u32 cgpr; + u32 ccgr0; + u32 ccgr1; + u32 ccgr2; + u32 ccgr3; + u32 ccgr4; + u32 ccgr5; + u32 ccgr6; + u32 ccgr7; + u32 ccgr8; + u32 ccgr9; + u32 ccgr10; + u32 ccgr11; + u32 cmeor0; + u32 cmeor1; + u32 cmeor2; + u32 cmeor3; + u32 cmeor4; + u32 cmeor5; + u32 cppdsr; + u32 ccowr; + u32 ccpgr0; + u32 ccpgr1; + u32 ccpgr2; + u32 ccpgr3; +}; + +/* Analog components control digital interface (ANADIG) */ +struct anadig_reg { + u32 reserved_0x000[4]; + u32 pll3_ctrl; + u32 reserved_0x014[3]; + u32 pll7_ctrl; + u32 reserved_0x024[3]; + u32 pll2_ctrl; + u32 reserved_0x034[3]; + u32 pll2_ss; + u32 reserved_0x044[3]; + u32 pll2_num; + u32 reserved_0x054[3]; + u32 pll2_denom; + u32 reserved_0x064[3]; + u32 pll4_ctrl; + u32 reserved_0x074[3]; + u32 pll4_num; + u32 reserved_0x084[3]; + u32 pll4_denom; + u32 reserved_0x094[3]; + u32 pll6_ctrl; + u32 reserved_0x0A4[3]; + u32 pll6_num; + u32 reserved_0x0B4[3]; + u32 pll6_denom; + u32 reserved_0x0C4[7]; + u32 pll5_ctrl; + u32 reserved_0x0E4[3]; + u32 pll3_pfd; + u32 reserved_0x0F4[3]; + u32 pll2_pfd; + u32 reserved_0x104[3]; + u32 reg_1p1; + u32 reserved_0x114[3]; + u32 reg_3p0; + u32 reserved_0x124[3]; + u32 reg_2p5; + u32 reserved_0x134[7]; + u32 ana_misc0; + u32 reserved_0x154[3]; + u32 ana_misc1; + u32 reserved_0x164[63]; + u32 anadig_digprog; + u32 reserved_0x264[3]; + u32 pll1_ctrl; + u32 reserved_0x274[3]; + u32 pll1_ss; + u32 reserved_0x284[3]; + u32 pll1_num; + u32 reserved_0x294[3]; + u32 pll1_denom; + u32 reserved_0x2A4[3]; + u32 pll1_pdf; + u32 reserved_0x2B4[3]; + u32 pll_lock; +}; +#endif + +#define CCM_CCR_FIRC_EN (1 << 16) +#define CCM_CCR_OSCNT_MASK 0xff +#define CCM_CCR_OSCNT(v) ((v) & 0xff) + +#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19 +#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19) +#define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19) + +#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16 +#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16) +#define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16) + +#define CCM_CCSR_PLL2_PFD4_EN (1 << 15) +#define CCM_CCSR_PLL2_PFD3_EN (1 << 14) +#define CCM_CCSR_PLL2_PFD2_EN (1 << 13) +#define CCM_CCSR_PLL2_PFD1_EN (1 << 12) +#define CCM_CCSR_PLL1_PFD4_EN (1 << 11) +#define CCM_CCSR_PLL1_PFD3_EN (1 << 10) +#define CCM_CCSR_PLL1_PFD2_EN (1 << 9) +#define CCM_CCSR_PLL1_PFD1_EN (1 << 8) + +#define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6) +#define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5) + +#define CCM_CCSR_SYS_CLK_SEL_OFFSET 0 +#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7 +#define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7) + +#define CCM_CACRR_IPG_CLK_DIV_OFFSET 11 +#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11) +#define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11) +#define CCM_CACRR_BUS_CLK_DIV_OFFSET 3 +#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3) +#define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3) +#define CCM_CACRR_ARM_CLK_DIV_OFFSET 0 +#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7 +#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7) + +#define CCM_CSCMR1_DCU1_CLK_SEL (1 << 29) +#define CCM_CSCMR1_DCU0_CLK_SEL (1 << 28) + +#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET 22 +#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22) +#define CCM_CSCMR1_QSPI0_CLK_SEL(v) (((v) & 0x3) << 22) +#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18 +#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18) +#define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18) +#define CCM_CSCMR1_NFC_CLK_SEL_OFFSET 12 +#define CCM_CSCMR1_NFC_CLK_SEL_MASK (0x3 << 12) +#define CCM_CSCMR1_NFC_CLK_SEL(v) (((v) & 0x3) << 12) + +#define CCM_CSCDR1_RMII_CLK_EN (1 << 24) + +#define CCM_CSCDR2_NFC_EN (1 << 9) +#define CCM_CSCDR2_NFC_FRAC_DIV_EN (1 << 13) +#define CCM_CSCDR2_NFC_CLK_INV (1 << 14) +#define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET 4 +#define CCM_CSCDR2_NFC_FRAC_DIV_MASK (0xf << 4) +#define CCM_CSCDR2_NFC_FRAC_DIV(v) (((v) & 0xf) << 4) + +#define CCM_CSCDR2_ESDHC1_EN (1 << 29) +#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20 +#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20) +#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20) + +#define CCM_CSCDR3_DCU1_EN (1 << 23) +#define CCM_CSCDR3_DCU1_DIV_MASK (0x7 << 20) +#define CCM_CSCDR3_DCU1_DIV(v) (((v) & 0x7) << 20) +#define CCM_CSCDR3_DCU0_EN (1 << 19) +#define CCM_CSCDR3_DCU0_DIV_MASK (0x7 << 16) +#define CCM_CSCDR3_DCU0_DIV(v) (((v) & 0x7) << 16) + +#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET 13 +#define CCM_CSCDR3_NFC_PRE_DIV_MASK (0x7 << 13) +#define CCM_CSCDR3_NFC_PRE_DIV(v) (((v) & 0x7) << 13) +#define CCM_CSCDR3_QSPI0_EN (1 << 4) +#define CCM_CSCDR3_QSPI0_DIV(v) ((v) << 3) +#define CCM_CSCDR3_QSPI0_X2_DIV(v) ((v) << 2) +#define CCM_CSCDR3_QSPI0_X4_DIV(v) ((v) & 0x3) + +#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4 +#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4) +#define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4) + +#define CCM_REG_CTRL_MASK 0xffffffff +#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14) +#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) +#define CCM_CCGR0_UART2_CTRL_MASK (0x3 << 18) +#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24) +#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26) +#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8) +#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) +#define CCM_CCGR1_TCON0_CTRL_MASK (0x3 << 26) +#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) +#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8) +#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16) +#define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18) +#define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20) +#define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22) +#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24) +#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26) +#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3 +#define CCM_CCGR3_SCSC_CTRL_MASK (0x3 << 4) +#define CCM_CCGR3_DCU0_CTRL_MASK (0x3 << 16) +#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20) +#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22) +#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) +#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12) +#define CCM_CCGR4_I2C1_CTRL_MASK (0x3 << 14) +#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10) +#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24) +#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26) +#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28) +#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) +#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8) +#define CCM_CCGR9_FEC0_CTRL_MASK 0x3 +#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) +#define CCM_CCGR10_NFC_CTRL_MASK 0x3 +#define CCM_CCGR10_I2C2_CTRL_MASK (0x3 << 12) +#define CCM_CCGR10_I2C3_CTRL_MASK (0x3 << 14) + +#define ANADIG_PLL7_CTRL_BYPASS (1 << 16) +#define ANADIG_PLL7_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL7_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL7_CTRL_DIV_SELECT (1 << 1) +#define ANADIG_PLL5_CTRL_BYPASS (1 << 16) +#define ANADIG_PLL5_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL5_CTRL_DIV_SELECT 1 +#define ANADIG_PLL3_CTRL_BYPASS (1 << 16) +#define ANADIG_PLL3_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL3_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL3_CTRL_DIV_SELECT (1 << 1) +#define ANADIG_PLL2_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL2_CTRL_DIV_SELECT 1 +#define ANADIG_PLL1_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL1_CTRL_DIV_SELECT 1 + +#define FASE_CLK_FREQ 24000000 +#define SLOW_CLK_FREQ 32000 +#define PLL1_PFD1_FREQ 500000000 +#define PLL1_PFD2_FREQ 452000000 +#define PLL1_PFD3_FREQ 396000000 +#define PLL1_PFD4_FREQ 528000000 +#define PLL1_MAIN_FREQ 528000000 +#define PLL2_PFD1_FREQ 500000000 +#define PLL2_PFD2_FREQ 396000000 +#define PLL2_PFD3_FREQ 339000000 +#define PLL2_PFD4_FREQ 413000000 +#define PLL2_MAIN_FREQ 528000000 +#define PLL3_MAIN_FREQ 480000000 +#define PLL3_PFD3_FREQ 298000000 +#define PLL5_MAIN_FREQ 500000000 + +#define ENET_EXTERNAL_CLK 50000000 +#define AUDIO_EXTERNAL_CLK 24576000 + +#endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h b/roms/u-boot/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h new file mode 100644 index 000000000..03e3cecb9 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 + * Toradex, Inc. + * + * Authors: Stefan Agner + * Sanchayan Maity + */ + +#ifndef __ASM_ARCH_VF610_DDRMC_H +#define __ASM_ARCH_VF610_DDRMC_H + +#include + +struct ddr3_jedec_timings { + u8 tinit; + u32 trst_pwron; + u32 cke_inactive; + u8 wrlat; + u8 caslat_lin; + u8 trc; + u8 trrd; + u8 tccd; + u8 tbst_int_interval; + u8 tfaw; + u8 trp; + u8 twtr; + u8 tras_min; + u8 tmrd; + u8 trtp; + u32 tras_max; + u8 tmod; + u8 tckesr; + u8 tcke; + u8 trcd_int; + u8 tras_lockout; + u8 tdal; + u8 bstlen; + u16 tdll; + u8 trp_ab; + u16 tref; + u8 trfc; + u16 tref_int; + u8 tpdex; + u8 txpdll; + u8 txsnr; + u16 txsr; + u8 cksrx; + u8 cksre; + u8 freq_chg_en; + u16 zqcl; + u16 zqinit; + u8 zqcs; + u8 ref_per_zq; + u8 zqcs_rotate; + u8 aprebit; + u8 cmd_age_cnt; + u8 age_cnt; + u8 q_fullness; + u8 odt_rd_mapcs0; + u8 odt_wr_mapcs0; + u8 wlmrd; + u8 wldqsen; +}; + +struct ddrmc_cr_setting { + u32 setting; + int cr_rnum; /* CR register ; -1 for last entry */ +}; + +struct ddrmc_phy_setting { + u32 setting; + int phy_rnum; /* PHY register ; -1 for last entry */ +}; + +void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count); +void ddrmc_phy_init(void); +void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, + struct ddrmc_cr_setting *board_cr_settings, + struct ddrmc_phy_setting *board_phy_settings, + int col_diff, int row_diff); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-vf610/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-vf610/gpio.h new file mode 100644 index 000000000..0b9e10f51 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-vf610/gpio.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2015 + * Bhuvanchandra DV, Toradex, Inc. + */ + +#ifndef __ASM_ARCH_VF610_GPIO_H +#define __ASM_ARCH_VF610_GPIO_H + +#define VYBRID_GPIO_COUNT 32 +#define VF610_GPIO_DIRECTION_IN 0x0 +#define VF610_GPIO_DIRECTION_OUT 0x1 + +/* GPIO registers */ +struct vybrid_gpio_regs { + u32 gpio_pdor; + u32 gpio_psor; + u32 gpio_pcor; + u32 gpio_ptor; + u32 gpio_pdir; +}; + +struct vybrid_gpio_plat { + unsigned int chip; + u32 base; + const char *port_name; +}; +#endif /* __ASM_ARCH_VF610_GPIO_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-vf610/imx-regs.h b/roms/u-boot/arch/arm/include/asm/arch-vf610/imx-regs.h new file mode 100644 index 000000000..97211f4b1 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -0,0 +1,480 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + */ + +#ifndef __ASM_ARCH_IMX_REGS_H__ +#define __ASM_ARCH_IMX_REGS_H__ + +#define ARCH_MXC + +#define IRAM_BASE_ADDR 0x3F000000 /* internal ram */ +#define IRAM_SIZE 0x00080000 /* 512 KB */ + +#define AIPS0_BASE_ADDR 0x40000000 +#define AIPS1_BASE_ADDR 0x40080000 + +/* AIPS 0 */ +#define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000) +#define MSCM_IR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001800) +#define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000) +#define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000) +#define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000) +#define NIC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00008000) +#define NIC1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00009000) +#define NIC2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000) +#define NIC3_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000) +#define NIC4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000C000) +#define NIC5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000) +#define NIC6_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000E000) +#define NIC7_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000F000) +#define AHBTZASC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000) +#define TZASC_SYS0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00011000) +#define TZASC_SYS1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00012000) +#define TZASC_GFX_BASE_ADDR (AIPS0_BASE_ADDR + 0x00013000) +#define TZASC_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00014000) +#define TZASC_DDR1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00015000) +#define CSU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00017000) +#define DMA0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00018000) +#define DMA0_TCD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00019000) +#define SEMA4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001D000) +#define FB_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001E000) +#define DMA_MUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00024000) +#define UART0_BASE (AIPS0_BASE_ADDR + 0x00027000) +#define UART1_BASE (AIPS0_BASE_ADDR + 0x00028000) +#define UART2_BASE (AIPS0_BASE_ADDR + 0x00029000) +#define UART3_BASE (AIPS0_BASE_ADDR + 0x0002A000) +#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002C000) +#define SPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002D000) +#define SAI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002F000) +#define SAI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000) +#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000) +#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000) +#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000) +#define USBC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000) +#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000) +#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000) +#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000) +#define FTM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000) +#define ADC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003B000) +#define TCON0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003D000) +#define WDOG1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000) +#define LPTMR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00040000) +#define RLE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000) +#define MLB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00043000) +#define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000) +#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000) +#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000) +#define USB_PHY0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050800) +#define USB_PHY1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050C00) +#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000) +#define DCU0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00058000) +#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000) +#define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000) +#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000) +#define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000) +#define WDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000) +#define I2C1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000) +#define I2C2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00067000) +#define I2C3_BASE_ADDR (AIPS0_BASE_ADDR + 0x000E6000) +#define I2C4_BASE_ADDR (AIPS0_BASE_ADDR + 0x000E7000) +#define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000) +#define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000) +#define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000) +#define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000) +#define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000) +#define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000) +#define GPIO0_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF000) +#define GPIO1_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF040) +#define GPIO2_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF080) +#define GPIO3_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF0C0) +#define GPIO4_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF100) + +/* AIPS 1 */ +#define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000) +#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000) +#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000) +#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000) +#define USBC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00034000) +#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000) +#define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000) +#define DCU1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00058000) +#define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x00060000) + +#define QSPI0_AMBA_BASE 0x20000000 + +/* MUX mode and PAD ctrl are in one register */ +#define CONFIG_IOMUX_SHARE_CONF_REG + +#define FEC_QUIRK_ENET_MAC +#define I2C_QUIRK_REG + +/* MSCM interrupt rounter */ +#define MSCM_IRSPRC_CP0_EN 1 +#define MSCM_IRSPRC_NUM 112 + +/* DDRMC */ +#define DDRMC_PHY_DQ_TIMING 0x00002613 +#define DDRMC_PHY_DQS_TIMING 0x00002615 +#define DDRMC_PHY_CTRL 0x00210000 +#define DDRMC_PHY_MASTER_CTRL 0x0001012a +#define DDRMC_PHY_SLAVE_CTRL 0x00002000 +#define DDRMC_PHY_OFF 0x00000000 +#define DDRMC_PHY_PROC_PAD_ODT 0x00010101 + +#define DDRMC_PHY50_DDR3_MODE (1 << 12) +#define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8) + +#define DDRMC_CR00_DRAM_CLASS_DDR3 (0x6 << 8) +#define DDRMC_CR00_DRAM_CLASS_LPDDR2 (0x5 << 8) +#define DDRMC_CR00_START 1 +#define DDRMC_CR02_DRAM_TINIT(v) ((v) & 0xffffff) +#define DDRMC_CR10_TRST_PWRON(v) (v) +#define DDRMC_CR11_CKE_INACTIVE(v) (v) +#define DDRMC_CR12_WRLAT(v) (((v) & 0x1f) << 8) +#define DDRMC_CR12_CASLAT_LIN(v) ((v) & 0x3f) +#define DDRMC_CR13_TRC(v) (((v) & 0xff) << 24) +#define DDRMC_CR13_TRRD(v) (((v) & 0xff) << 16) +#define DDRMC_CR13_TCCD(v) (((v) & 0x1f) << 8) +#define DDRMC_CR13_TBST_INT_INTERVAL(v) ((v) & 0x7) +#define DDRMC_CR14_TFAW(v) (((v) & 0x3f) << 24) +#define DDRMC_CR14_TRP(v) (((v) & 0x1f) << 16) +#define DDRMC_CR14_TWTR(v) (((v) & 0xf) << 8) +#define DDRMC_CR14_TRAS_MIN(v) ((v) & 0xff) +#define DDRMC_CR16_TMRD(v) (((v) & 0x1f) << 24) +#define DDRMC_CR16_TRTP(v) (((v) & 0xf) << 16) +#define DDRMC_CR17_TRAS_MAX(v) (((v) & 0x1ffff) << 8) +#define DDRMC_CR17_TMOD(v) ((v) & 0xff) +#define DDRMC_CR18_TCKESR(v) (((v) & 0x1f) << 8) +#define DDRMC_CR18_TCKE(v) ((v) & 0x7) +#define DDRMC_CR20_AP_EN (1 << 24) +#define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16) +#define DDRMC_CR21_TRAS_LOCKOUT(v) ((v) << 8) +#define DDRMC_CR21_CCMAP_EN 1 +#define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16) +#define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24) +#define DDRMC_CR23_TDLL(v) ((v) & 0xffff) +#define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f) +#define DDRMC_CR25_TREF_EN (1 << 16) +#define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16) +#define DDRMC_CR26_TRFC(v) ((v) & 0x3ff) +#define DDRMC_CR28_TREF_INT(v) ((v) & 0xffff) +#define DDRMC_CR29_TPDEX(v) ((v) & 0xffff) +#define DDRMC_CR30_TXPDLL(v) ((v) & 0xffff) +#define DDRMC_CR31_TXSNR(v) (((v) & 0xffff) << 16) +#define DDRMC_CR31_TXSR(v) ((v) & 0xffff) +#define DDRMC_CR33_EN_QK_SREF (1 << 16) +#define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16) +#define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8) +#define DDRMC_CR38_FREQ_CHG_EN(v) (((v) & 0x1) << 8) +#define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0xffff) << 16) +#define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8) +#define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3) +#define DDRMC_CR41_PHY_INI_STRT_INI_DIS 1 +#define DDRMC_CR48_MR1_DA_0(v) (((v) & 0xffff) << 16) +#define DDRMC_CR48_MR0_DA_0(v) ((v) & 0xffff) +#define DDRMC_CR66_ZQCL(v) (((v) & 0xfff) << 16) +#define DDRMC_CR66_ZQINIT(v) ((v) & 0xfff) +#define DDRMC_CR67_ZQCS(v) ((v) & 0xfff) +#define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8) +#define DDRMC_CR70_REF_PER_ZQ(v) (v) +#define DDRMC_CR72_ZQCS_ROTATE(v) (((v) & 0x1) << 24) +#define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24) +#define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16) +#define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8) +#define DDRMC_CR74_BANKSPLT_EN (1 << 24) +#define DDRMC_CR74_ADDR_CMP_EN (1 << 16) +#define DDRMC_CR74_CMD_AGE_CNT(v) (((v) & 0xff) << 8) +#define DDRMC_CR74_AGE_CNT(v) ((v) & 0xff) +#define DDRMC_CR75_RW_PG_EN (1 << 24) +#define DDRMC_CR75_RW_EN (1 << 16) +#define DDRMC_CR75_PRI_EN (1 << 8) +#define DDRMC_CR75_PLEN 1 +#define DDRMC_CR76_NQENT_ACTDIS(v) (((v) & 0x7) << 24) +#define DDRMC_CR76_D_RW_G_BKCN(v) (((v) & 0x3) << 16) +#define DDRMC_CR76_W2R_SPLT_EN (1 << 8) +#define DDRMC_CR76_CS_EN 1 +#define DDRMC_CR77_CS_MAP (1 << 24) +#define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8) +#define DDRMC_CR77_SWAP_EN 1 +#define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24) +#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf) +#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24) +#define DDRMC_CR80_MC_INIT_COMPLETE (1 << 8) +#define DDRMC_CR82_INT_MASK (1 << 28) +#define DDRMC_CR87_ODT_WR_MAPCS0(v) ((v) << 24) +#define DDRMC_CR87_ODT_RD_MAPCS0(v) ((v) << 16) +#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) +#define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf) +#define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16) +#define DDRMC_CR93_SW_LVL_MODE_OFF (8) +#define DDRMC_CR93_SW_LVL_MODE(v) (((v) & 0x3) << DDRMC_CR93_SW_LVL_MODE_OFF) +#define DDRMC_CR93_SWLVL_LOAD BIT(16) +#define DDRMC_CR93_SWLVL_START BIT(24) +#define DDRMC_CR94_SWLVL_EXIT BIT(0) +#define DDRMC_CR94_SWLVL_OP_DONE BIT(8) +#define DDRMC_CR94_SWLVL_RESP_0_OFF (24) +#define DDRMC_CR95_SWLVL_RESP_1_OFF (0) +#define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) +#define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) +#define DDRMC_CR97_WRLVL_EN (1 << 24) +#define DDRMC_CR98_WRLVL_DL_0(v) ((v) & 0xffff) +#define DDRMC_CR99_WRLVL_DL_1(v) ((v) & 0xffff) +#define DDRMC_CR101_PHY_RDLVL_EDGE_OFF (24) +#define DDRMC_CR101_PHY_RDLVL_EDGE BIT(DDRMC_CR101_PHY_RDLVL_EDGE_OFF) +#define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16) +#define DDRMC_CR102_RDLVL_REG_EN (1 << 8) +#define DDRMC_CR105_RDLVL_DL_0_OFF (8) +#define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << DDRMC_CR105_RDLVL_DL_0_OFF) +#define DDRMC_CR106_RDLVL_GTDL_0(v) ((v) & 0xff) +#define DDRMC_CR110_RDLVL_DL_1_OFF (0) +#define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff) +#define DDRMC_CR110_RDLVL_GTDL_1(v) (((v) & 0xff) << 16) +#define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8) +#define DDRMC_CR115_RDLVL_GTDL_2(v) ((v) & 0xff) +#define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8) +#define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3) +#define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24) +#define DDRMC_CR118_AXI1_R_PRI(v) (((v) & 0x3) << 16) +#define DDRMC_CR120_AXI0_PRI1_RPRI(v) (((v) & 0xf) << 24) +#define DDRMC_CR120_AXI0_PRI0_RPRI(v) (((v) & 0xf) << 16) +#define DDRMC_CR121_AXI0_PRI3_RPRI(v) (((v) & 0xf) << 8) +#define DDRMC_CR121_AXI0_PRI2_RPRI(v) ((v) & 0xf) +#define DDRMC_CR122_AXI1_PRI1_RPRI(v) (((v) & 0xf) << 24) +#define DDRMC_CR122_AXI1_PRI0_RPRI(v) (((v) & 0xf) << 16) +#define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff) +#define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8) +#define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf) +#define DDRMC_CR123_AXI1_P_ODR_EN (1 << 16) +#define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff) +#define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8) +#define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8) +#define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f) +#define DDRMC_CR137_PHYCTL_DL(v) (((v) & 0xf) << 16) +#define DDRMC_CR138_PHY_WRLV_MXDL(v) (((v) & 0xffff) << 16) +#define DDRMC_CR138_PHYDRAM_CK_EN(v) (((v) & 0x7) << 8) +#define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24) +#define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16) +#define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8) +#define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff) +#define DDRMC_CR140_PHY_WRLV_WW(v) ((v) & 0x3ff) +#define DDRMC_CR143_RDLV_GAT_MXDL(v) (((v) & 0xffff) << 16) +#define DDRMC_CR143_RDLV_MXDL(v) ((v) & 0xffff) +#define DDRMC_CR144_PHY_RDLVL_RES(v) (((v) & 0xff) << 24) +#define DDRMC_CR144_PHY_RDLV_LOAD(v) (((v) & 0xff) << 16) +#define DDRMC_CR144_PHY_RDLV_DLL(v) (((v) & 0xff) << 8) +#define DDRMC_CR144_PHY_RDLV_EN(v) ((v) & 0xff) +#define DDRMC_CR145_PHY_RDLV_RR(v) ((v) & 0x3ff) +#define DDRMC_CR146_PHY_RDLVL_RESP(v) (v) +#define DDRMC_CR147_RDLV_RESP_MASK(v) ((v) & 0xfffff) +#define DDRMC_CR148_RDLV_GATE_RESP_MASK(v) ((v) & 0xfffff) +#define DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(v) (((v) & 0xf) << 8) +#define DDRMC_CR151_RDLVL_DQ_ZERO_CNT(v) ((v) & 0xf) +#define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27) +#define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21) +#define DDRMC_CR154_DDR_SEL_PAD_CONTR(v) (((v) & 0x3) << 18) +#define DDRMC_CR154_PAD_ZQ_HW_FOR(v) (((v) & 0x1) << 14) +#define DDRMC_CR155_AXI0_AWCACHE (1 << 10) +#define DDRMC_CR155_PAD_ODT_BYTE1(v) (((v) & 0x7) << 3) +#define DDRMC_CR155_PAD_ODT_BYTE0(v) ((v) & 0x7) +#define DDRMC_CR158_TWR(v) ((v) & 0x3f) +#define DDRMC_CR161_ODT_EN(v) (((v) & 0x1) << 16) +#define DDRMC_CR161_TODTH_RD(v) (((v) & 0xf) << 8) +#define DDRMC_CR161_TODTH_WR(v) ((v) & 0xf) + +/* System Reset Controller (SRC) */ +#define SRC_SRSR_SW_RST (0x1 << 18) +#define SRC_SRSR_RESETB (0x1 << 7) +#define SRC_SRSR_JTAG_RST (0x1 << 5) +#define SRC_SRSR_WDOG_M4 (0x1 << 4) +#define SRC_SRSR_WDOG_A5 (0x1 << 3) +#define SRC_SRSR_POR_RST (0x1 << 0) +#define SRC_SBMR1_BOOTCFG1_SDMMC BIT(6) +#define SRC_SBMR1_BOOTCFG1_MMC BIT(4) +#define SRC_SBMR2_BMOD_MASK (0x3 << 24) +#define SRC_SBMR2_BMOD_SHIFT 24 +#define SRC_SBMR2_BMOD_FUSES 0x0 +#define SRC_SBMR2_BMOD_SERIAL 0x1 +#define SRC_SBMR2_BMOD_RCON 0x2 + +/* Slow Clock Source Controller Module (SCSC) */ +#define SCSC_SOSC_CTR_SOSC_EN 0x1 + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include +#include + +/* System Reset Controller (SRC) */ +struct src { + u32 scr; + u32 sbmr1; + u32 srsr; + u32 secr; + u32 gpsr; + u32 sicr; + u32 simr; + u32 sbmr2; + u32 gpr0; + u32 gpr1; + u32 gpr2; + u32 gpr3; + u32 gpr4; + u32 hab0; + u32 hab1; + u32 hab2; + u32 hab3; + u32 hab4; + u32 hab5; + u32 misc0; + u32 misc1; + u32 misc2; + u32 misc3; +}; + +/* Periodic Interrupt Timer (PIT) */ +struct pit_reg { + u32 mcr; + u32 recv0[55]; + u32 ltmr64h; + u32 ltmr64l; + u32 recv1[6]; + u32 ldval0; + u32 cval0; + u32 tctrl0; + u32 tflg0; + u32 ldval1; + u32 cval1; + u32 tctrl1; + u32 tflg1; + u32 ldval2; + u32 cval2; + u32 tctrl2; + u32 tflg2; + u32 ldval3; + u32 cval3; + u32 tctrl3; + u32 tflg3; + u32 ldval4; + u32 cval4; + u32 tctrl4; + u32 tflg4; + u32 ldval5; + u32 cval5; + u32 tctrl5; + u32 tflg5; + u32 ldval6; + u32 cval6; + u32 tctrl6; + u32 tflg6; + u32 ldval7; + u32 cval7; + u32 tctrl7; + u32 tflg7; +}; + +/* Watchdog Timer (WDOG) */ +struct wdog_regs { + u16 wcr; + u16 wsr; + u16 wrsr; + u16 wicr; + u16 wmcr; +}; + +/* LPDDR2/DDR3 SDRAM Memory Controller (DDRMC) */ +struct ddrmr_regs { + u32 cr[162]; + u32 rsvd[94]; + u32 phy[53]; +}; + +/* On-Chip One Time Programmable Controller (OCOTP) */ +struct ocotp_regs { + u32 ctrl; + u32 ctrl_set; + u32 ctrl_clr; + u32 ctrl_tog; + u32 timing; + u32 rsvd0[3]; + u32 data; + u32 rsvd1[3]; + u32 read_ctrl; + u32 rsvd2[3]; + u32 read_fuse_data; + u32 rsvd3[7]; + u32 scs; + u32 scs_set; + u32 scs_clr; + u32 scs_tog; + u32 crc_addr; + u32 rsvd4[3]; + u32 crc_value; + u32 rsvd5[3]; + u32 version; + u32 rsvd6[0xdb]; + + struct fuse_bank { + u32 fuse_regs[0x20]; + } bank[16]; +}; + +struct fuse_bank0_regs { + u32 lock; + u32 rsvd0[3]; + u32 uid_low; + u32 rsvd1[3]; + u32 uid_high; + u32 rsvd2[0x17]; +}; + +struct fuse_bank4_regs { + u32 sjc_resp0; + u32 rsvd0[3]; + u32 sjc_resp1; + u32 rsvd1[3]; + u32 mac_addr0; + u32 rsvd2[3]; + u32 mac_addr1; + u32 rsvd3[3]; + u32 mac_addr2; + u32 rsvd4[3]; + u32 mac_addr3; + u32 rsvd5[3]; + u32 gp1; + u32 rsvd6[3]; + u32 gp2; + u32 rsvd7[3]; +}; + +/* MSCM Interrupt Router */ +struct mscm_ir { + u32 ircp0ir; + u32 ircp1ir; + u32 rsvd1[6]; + u32 ircpgir; + u32 rsvd2[23]; + u16 irsprc[112]; + u16 rsvd3[848]; +}; + +/* SCSC */ +struct scsc_reg { + u32 sirc_ctr; + u32 sosc_ctr; +}; + +/* MSCM */ +struct mscm { + u32 cpxtype; + u32 cpxnum; + u32 cpxmaster; + u32 cpxcount; + u32 cpxcfg0; + u32 cpxcfg1; + u32 cpxcfg2; + u32 cpxcfg3; +}; + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/roms/u-boot/arch/arm/include/asm/arch-vf610/iomux-vf610.h new file mode 100644 index 000000000..8ba03e5a1 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -0,0 +1,255 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + */ + +#ifndef __IOMUX_VF610_H__ +#define __IOMUX_VF610_H__ + +#include + +/* Pad control groupings */ +#define VF610_UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_25ohm | \ + PAD_CTL_OBE_IBE_ENABLE) +#define VF610_SDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_20ohm | \ + PAD_CTL_OBE_IBE_ENABLE) +#define VF610_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ + PAD_CTL_OBE_IBE_ENABLE) +#define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm +#define VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_25ohm | \ + PAD_CTL_INPUT_DIFFERENTIAL) +#define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_ODE | \ + PAD_CTL_OBE_IBE_ENABLE) +#define VF610_NFC_IO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \ + PAD_CTL_DSE_50ohm | PAD_CTL_PUS_47K_UP | \ + PAD_CTL_OBE_IBE_ENABLE) +#define VF610_NFC_CN_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \ + PAD_CTL_DSE_25ohm | PAD_CTL_OBE_ENABLE) +#define VF610_NFC_RB_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_IBE_ENABLE) + +#define VF610_QSPI_PAD_CTRL (PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE) + +#define VF610_GPIO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | \ + PAD_CTL_IBE_ENABLE) + +#define VF610_DSPI_PAD_CTRL (PAD_CTL_OBE_ENABLE | PAD_CTL_DSE_20ohm | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH) +#define VF610_DSPI_SIN_PAD_CTRL (PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH) +#define VF610_DCU_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \ + PAD_CTL_DSE_37ohm | PAD_CTL_OBE_ENABLE) + +enum { + VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTA7__GPIO_134 = IOMUX_PAD(0x0218, 0x0218, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA17__GPIO_7 = IOMUX_PAD(0x001c, 0x001c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA20__GPIO_10 = IOMUX_PAD(0x0028, 0x0028, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA21__GPIO_11 = IOMUX_PAD(0x002c, 0x002c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA30__GPIO_20 = IOMUX_PAD(0x0050, 0x0050, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA31__GPIO_21 = IOMUX_PAD(0x0054, 0x0054, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB0__GPIO_22 = IOMUX_PAD(0x0058, 0x0058, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB1__GPIO_23 = IOMUX_PAD(0x005C, 0x005C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB6__GPIO_28 = IOMUX_PAD(0x0070, 0x0070, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB7__GPIO_29 = IOMUX_PAD(0x0074, 0x0074, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB8__GPIO_30 = IOMUX_PAD(0x0078, 0x0078, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB9__GPIO_31 = IOMUX_PAD(0x007C, 0x007C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB10__UART0_TX = IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB11__UART0_RX = IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB12__GPIO_34 = IOMUX_PAD(0x0088, 0x0088, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB13__GPIO_35 = IOMUX_PAD(0x008c, 0x008c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB16__GPIO_38 = IOMUX_PAD(0x0098, 0x0098, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB17__GPIO_39 = IOMUX_PAD(0x009c, 0x009c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB18__GPIO_40 = IOMUX_PAD(0x00a0, 0x00a0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB21__GPIO_43 = IOMUX_PAD(0x00ac, 0x00ac, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB22__GPIO_44 = IOMUX_PAD(0x00b0, 0x00b0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB23__GPIO_93 = IOMUX_PAD(0x0174, 0x0174, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB26__GPIO_96 = IOMUX_PAD(0x0180, 0x0180, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB28__GPIO_98 = IOMUX_PAD(0x0188, 0x0188, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC1__GPIO_46 = IOMUX_PAD(0x00b8, 0x00b8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC0__GPIO_45 = IOMUX_PAD(0x00b4, 0x00b4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC2__GPIO_47 = IOMUX_PAD(0x00bc, 0x00bc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC3__RMII0_RD1 = IOMUX_PAD(0x00c0, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC3__GPIO_48 = IOMUX_PAD(0x00c0, 0x00c0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC4__RMII0_RD0 = IOMUX_PAD(0x00c4, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC4__GPIO_49 = IOMUX_PAD(0x00c4, 0x00c4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC5__RMII0_RXER = IOMUX_PAD(0x00c8, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC5__GPIO_50 = IOMUX_PAD(0x00c8, 0x00c8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC6__GPIO_51 = IOMUX_PAD(0x00cc, 0x00cc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC7__GPIO_52 = IOMUX_PAD(0x00D0, 0x00D0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC8__GPIO_53 = IOMUX_PAD(0x00D4, 0x00D4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC10__RMII1_MDIO = IOMUX_PAD(0x00dc, 0x00dc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC9__RMII1_MDC = IOMUX_PAD(0x00d8, 0x00d8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC11__RMII1_CRS_DV = IOMUX_PAD(0x00e0, 0x00e0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC12__RMII1_RD1 = IOMUX_PAD(0x00e4, 0x00e4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC13__RMII1_RD0 = IOMUX_PAD(0x00e8, 0x00e8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC14__RMII1_RXER = IOMUX_PAD(0x00ec, 0x00ec, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC15__RMII1_TD1 = IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC16__RMII1_TD0 = IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC17__RMII1_TXEN = IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTD5__DSPI1_CS0 = IOMUX_PAD(0x0150, 0x0150, 3, 0x300, 1, VF610_DSPI_PAD_CTRL), + VF610_PAD_PTD6__DSPI1_SIN = IOMUX_PAD(0x0154, 0x0154, 3, 0x2fc, 1, VF610_DSPI_SIN_PAD_CTRL), + VF610_PAD_PTD7__DSPI1_SOUT = IOMUX_PAD(0x0158, 0x0158, 3, __NA_, 0, VF610_DSPI_PAD_CTRL), + VF610_PAD_PTD8__DSPI1_SCK = IOMUX_PAD(0x015c, 0x015c, 3, 0x2f8, 1, VF610_DSPI_PAD_CTRL), + VF610_PAD_PTC29__GPIO_102 = IOMUX_PAD(0x0198, 0x0198, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC30__GPIO_103 = IOMUX_PAD(0x019c, 0x019c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA27__ESDHC1_DAT1 = IOMUX_PAD(0x0044, 0x0044, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA28__ESDHC1_DAT2 = IOMUX_PAD(0x0048, 0x0048, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL), + VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL), + VF610_PAD_PTA22__I2C2_SCL = IOMUX_PAD(0x0030, 0x0030, 6, 0x034c, 0, VF610_I2C_PAD_CTRL), + VF610_PAD_PTA23__I2C2_SDA = IOMUX_PAD(0x0034, 0x0034, 6, 0x0350, 0, VF610_I2C_PAD_CTRL), + VF610_PAD_PTD31__NF_IO15 = IOMUX_PAD(0x00fc, 0x00fc, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD31__GPIO_63 = IOMUX_PAD(0x00fc, 0x00fc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD30__NF_IO14 = IOMUX_PAD(0x0100, 0x0100, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD30__GPIO_64 = IOMUX_PAD(0x0100, 0x0100, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD29__NF_IO13 = IOMUX_PAD(0x0104, 0x0104, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD29__GPIO_65 = IOMUX_PAD(0x0104, 0x0104, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD28__NF_IO12 = IOMUX_PAD(0x0108, 0x0108, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD28__GPIO_66 = IOMUX_PAD(0x0108, 0x0108, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD27__NF_IO11 = IOMUX_PAD(0x010c, 0x010c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD27__GPIO_67 = IOMUX_PAD(0x010c, 0x010c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD26__NF_IO10 = IOMUX_PAD(0x0110, 0x0110, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD26__GPIO_68 = IOMUX_PAD(0x0110, 0x0110, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD25__NF_IO9 = IOMUX_PAD(0x0114, 0x0114, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD25__GPIO_69 = IOMUX_PAD(0x0114, 0x0114, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD24__NF_IO8 = IOMUX_PAD(0x0118, 0x0118, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD24__GPIO_70 = IOMUX_PAD(0x0118, 0x0118, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD23__NF_IO7 = IOMUX_PAD(0x011c, 0x011c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD0__QSPI0_A_QSCK = IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD0__UART2_TX = IOMUX_PAD(0x013c, 0x013c, 2, 0x38c, 2, VF610_UART_PAD_CTRL), + VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD1__UART2_RX = IOMUX_PAD(0x0140, 0x0140, 2, 0x388, 2, VF610_UART_PAD_CTRL), + VF610_PAD_PTD2__QSPI0_A_DATA3 = IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD2__GPIO_81 = IOMUX_PAD(0x0144, 0x0144, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD3__QSPI0_A_DATA2 = IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD3__GPIO_82 = IOMUX_PAD(0x0148, 0x0148, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD4__GPIO_83 = IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD4__QSPI0_A_DATA1 = IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD5__QSPI0_A_DATA0 = IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD7__QSPI0_B_QSCK = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD8__QSPI0_B_CS0 = IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD9__QSPI0_B_DATA3 = IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD9__GPIO_88 = IOMUX_PAD(0x0160, 0x0160, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD10__QSPI0_B_DATA2 = IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD10__GPIO_89 = IOMUX_PAD(0x0164, 0x0164, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD11__QSPI0_B_DATA1 = IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD11__GPIO_90 = IOMUX_PAD(0x0168, 0x0168, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD12__QSPI0_B_DATA0 = IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD12__GPIO_91 = IOMUX_PAD(0x016c, 0x016c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD13__GPIO_92 = IOMUX_PAD(0x0170, 0x0170, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD22__NF_IO6 = IOMUX_PAD(0x0120, 0x0120, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD21__NF_IO5 = IOMUX_PAD(0x0124, 0x0124, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD20__NF_IO4 = IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD19__NF_IO3 = IOMUX_PAD(0x012c, 0x012c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD18__NF_IO2 = IOMUX_PAD(0x0130, 0x0130, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD17__NF_IO1 = IOMUX_PAD(0x0134, 0x0134, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD16__NF_IO0 = IOMUX_PAD(0x0138, 0x0138, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTB24__NF_WE_B = IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + VF610_PAD_PTB25__NF_CE0_B = IOMUX_PAD(0x017c, 0x017c, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + + VF610_PAD_PTB27__NF_RE_B = IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + + VF610_PAD_PTC26__NF_RB_B = IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL), + + VF610_PAD_PTC27__NF_ALE = IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + + VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + + VF610_PAD_PTE0__DCU0_HSYNC = IOMUX_PAD(0x01a4, 0x01a4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE1__DCU0_VSYNC = IOMUX_PAD(0x01a8, 0x01a8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE2__DCU0_PCLK = IOMUX_PAD(0x01ac, 0x01ac, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE4__DCU0_DE = IOMUX_PAD(0x01b4, 0x01b4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE5__DCU0_R0 = IOMUX_PAD(0x01b8, 0x01b8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE6__DCU0_R1 = IOMUX_PAD(0x01bc, 0x01bc, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE7__DCU0_R2 = IOMUX_PAD(0x01c0, 0x01c0, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE8__DCU0_R3 = IOMUX_PAD(0x01c4, 0x01c4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE9__DCU0_R4 = IOMUX_PAD(0x01c8, 0x01c8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE10__DCU0_R5 = IOMUX_PAD(0x01cc, 0x01cc, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE11__DCU0_R6 = IOMUX_PAD(0x01d0, 0x01d0, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE12__DCU0_R7 = IOMUX_PAD(0x01d4, 0x01d4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE13__DCU0_G0 = IOMUX_PAD(0x01d8, 0x01d8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE14__DCU0_G1 = IOMUX_PAD(0x01dc, 0x01dc, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE15__DCU0_G2 = IOMUX_PAD(0x01e0, 0x01e0, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE16__DCU0_G3 = IOMUX_PAD(0x01e4, 0x01e4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE17__DCU0_G4 = IOMUX_PAD(0x01e8, 0x01e8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE18__DCU0_G5 = IOMUX_PAD(0x01ec, 0x01ec, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE19__DCU0_G6 = IOMUX_PAD(0x01f0, 0x01f0, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE20__DCU0_G7 = IOMUX_PAD(0x01f4, 0x01f4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE21__DCU0_B0 = IOMUX_PAD(0x01f8, 0x01f8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE22__DCU0_B1 = IOMUX_PAD(0x01fc, 0x01fc, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE23__DCU0_B2 = IOMUX_PAD(0x0200, 0x0200, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE24__DCU0_B3 = IOMUX_PAD(0x0204, 0x0204, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE25__DCU0_B4 = IOMUX_PAD(0x0208, 0x0208, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE26__DCU0_B5 = IOMUX_PAD(0x020c, 0x020c, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE27__DCU0_B6 = IOMUX_PAD(0x0210, 0x0210, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE28__DCU0_B7 = IOMUX_PAD(0x0214, 0x0214, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + + VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, 0x022c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, 0x0230, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, 0x0234, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, 0x0238, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, 0x023c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, 0x0240, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, 0x0244, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, 0x0248, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, 0x024c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, 0x025c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, 0x026c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 = IOMUX_PAD(0x02dc, 0x02dc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 = IOMUX_PAD(0x02e0, 0x02e0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), +}; + +#endif /* __IOMUX_VF610_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/armv7.h b/roms/u-boot/arch/arm/include/asm/armv7.h new file mode 100644 index 000000000..2fb824b69 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/armv7.h @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments, + * Aneesh V + */ +#ifndef ARMV7_H +#define ARMV7_H + +/* Cortex-A9 revisions */ +#define MIDR_CORTEX_A9_R0P1 0x410FC091 +#define MIDR_CORTEX_A9_R1P2 0x411FC092 +#define MIDR_CORTEX_A9_R1P3 0x411FC093 +#define MIDR_CORTEX_A9_R2P10 0x412FC09A + +/* Cortex-A15 revisions */ +#define MIDR_CORTEX_A15_R0P0 0x410FC0F0 +#define MIDR_CORTEX_A15_R2P2 0x412FC0F2 + +/* Cortex-A7 revisions */ +#define MIDR_CORTEX_A7_R0P0 0x410FC070 + +#define MIDR_PRIMARY_PART_MASK 0xFF0FFFF0 + +/* ID_PFR1 feature fields */ +#define CPUID_ARM_SEC_SHIFT 4 +#define CPUID_ARM_SEC_MASK (0xF << CPUID_ARM_SEC_SHIFT) +#define CPUID_ARM_VIRT_SHIFT 12 +#define CPUID_ARM_VIRT_MASK (0xF << CPUID_ARM_VIRT_SHIFT) +#define CPUID_ARM_GENTIMER_SHIFT 16 +#define CPUID_ARM_GENTIMER_MASK (0xF << CPUID_ARM_GENTIMER_SHIFT) + +/* valid bits in CBAR register / PERIPHBASE value */ +#define CBAR_MASK 0xFFFF8000 + +/* CCSIDR */ +#define CCSIDR_LINE_SIZE_OFFSET 0 +#define CCSIDR_LINE_SIZE_MASK 0x7 +#define CCSIDR_ASSOCIATIVITY_OFFSET 3 +#define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3) +#define CCSIDR_NUM_SETS_OFFSET 13 +#define CCSIDR_NUM_SETS_MASK (0x7FFF << 13) + +/* + * Values for InD field in CSSELR + * Selects the type of cache + */ +#define ARMV7_CSSELR_IND_DATA_UNIFIED 0 +#define ARMV7_CSSELR_IND_INSTRUCTION 1 + +/* Values for Ctype fields in CLIDR */ +#define ARMV7_CLIDR_CTYPE_NO_CACHE 0 +#define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1 +#define ARMV7_CLIDR_CTYPE_DATA_ONLY 2 +#define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3 +#define ARMV7_CLIDR_CTYPE_UNIFIED 4 + +#ifndef __ASSEMBLY__ +#include +#include +#include + +/* read L2 control register (L2CTLR) */ +static inline uint32_t read_l2ctlr(void) +{ + uint32_t val = 0; + + asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); + + return val; +} + +/* write L2 control register (L2CTLR) */ +static inline void write_l2ctlr(uint32_t val) +{ + /* + * Note: L2CTLR can only be written when the L2 memory system + * is idle, ie before the MMU is enabled. + */ + asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory"); + isb(); +} + +/* + * Workaround for ARM errata # 798870 + * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been + * stalled for 1024 cycles to verify that its hazard condition still exists. + */ +static inline void v7_enable_l2_hazard_detect(void) +{ + uint32_t val; + + /* L2ACTLR[7]: Enable hazard detect timeout */ + asm volatile ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(val)); + val |= (1 << 7); + asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(val)); +} + +/* + * Workaround for ARM errata # 799270 + * Ensure that the L2 logic has been used within the previous 256 cycles + * before modifying the ACTLR.SMP bit. This is required during boot before + * MMU has been enabled, or during a specified reset or power down sequence. + */ +static inline void v7_enable_smp(uint32_t address) +{ + uint32_t temp, val; + + /* Read auxiliary control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val)); + + /* Enable SMP */ + val |= (1 << 6); + + /* Dummy read to assure L2 access */ + temp = readl(address); + temp &= 0; + val |= temp; + + /* Write auxiliary control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val)); + + CP15DSB; + CP15ISB; +} + +void v7_en_l2_hazard_detect(void); +void v7_outer_cache_enable(void); +void v7_outer_cache_disable(void); +void v7_outer_cache_flush_all(void); +void v7_outer_cache_inval_all(void); +void v7_outer_cache_flush_range(u32 start, u32 end); +void v7_outer_cache_inval_range(u32 start, u32 end); + +#ifdef CONFIG_ARMV7_NONSEC + +int armv7_init_nonsec(void); +int armv7_apply_memory_carveout(u64 *start, u64 *size); +bool armv7_boot_nonsec(void); + +/* defined in assembly file */ +unsigned int _nonsec_init(void); +void _do_nonsec_entry(void *target_pc, unsigned long r0, + unsigned long r1, unsigned long r2); +void _smp_pen(void); + +extern char __secure_start[]; +extern char __secure_end[]; +extern char __secure_stack_start[]; +extern char __secure_stack_end[]; + +#endif /* CONFIG_ARMV7_NONSEC */ + +void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr, + u32 cpu_rev_comb, u32 cpu_variant, + u32 cpu_rev); +void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, + u32 cpu_variant, u32 cpu_rev); +#endif /* ! __ASSEMBLY__ */ + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/armv7_mpu.h b/roms/u-boot/arch/arm/include/asm/armv7_mpu.h new file mode 100644 index 000000000..16b9d0d1a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/armv7_mpu.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Vikas Manocha, for STMicroelectronics. + */ + +#ifndef _ASM_ARMV7_MPU_H +#define _ASM_ARMV7_MPU_H + +#ifndef __ASSEMBLY__ +#include +#endif + +#ifdef CONFIG_CPU_V7M +#define AP_SHIFT 24 +#define XN_SHIFT 28 +#define TEX_SHIFT 19 +#define S_SHIFT 18 +#define C_SHIFT 17 +#define B_SHIFT 16 +#else /* CONFIG_CPU_V7R */ +#define XN_SHIFT 12 +#define AP_SHIFT 8 +#define TEX_SHIFT 3 +#define S_SHIFT 2 +#define C_SHIFT 1 +#define B_SHIFT 0 +#endif /* CONFIG_CPU_V7R */ + +#define CACHEABLE BIT(C_SHIFT) +#define BUFFERABLE BIT(B_SHIFT) +#define SHAREABLE BIT(S_SHIFT) +#define REGION_SIZE_SHIFT 1 +#define ENABLE_REGION BIT(0) +#define DISABLE_REGION 0 + +enum region_number { + REGION_0 = 0, + REGION_1, + REGION_2, + REGION_3, + REGION_4, + REGION_5, + REGION_6, + REGION_7, +}; + +enum ap { + NO_ACCESS = 0, + PRIV_RW_USR_NO, + PRIV_RW_USR_RO, + PRIV_RW_USR_RW, + UNPREDICTABLE, + PRIV_RO_USR_NO, + PRIV_RO_USR_RO, +}; + +enum mr_attr { + STRONG_ORDER = 0, + SHARED_WRITE_BUFFERED, + O_I_WT_NO_WR_ALLOC, + O_I_WB_NO_WR_ALLOC, + O_I_NON_CACHEABLE, + O_I_WB_RD_WR_ALLOC, + DEVICE_NON_SHARED, +}; +enum size { + REGION_8MB = 22, + REGION_16MB, + REGION_32MB, + REGION_64MB, + REGION_128MB, + REGION_256MB, + REGION_512MB, + REGION_1GB, + REGION_2GB, + REGION_4GB, +}; + +enum xn { + XN_DIS = 0, + XN_EN, +}; + +struct mpu_region_config { + uint32_t start_addr; + enum region_number region_no; + enum xn xn; + enum ap ap; + enum mr_attr mr_attr; + enum size reg_size; +}; + +void disable_mpu(void); +void enable_mpu(void); +int mpu_enabled(void); +void mpu_config(struct mpu_region_config *reg_config); +void setup_mpu_regions(struct mpu_region_config *rgns, u32 num_rgns); + +static inline u32 get_attr_encoding(u32 mr_attr) +{ + u32 attr; + + switch (mr_attr) { + case STRONG_ORDER: + attr = SHAREABLE; + break; + case SHARED_WRITE_BUFFERED: + attr = BUFFERABLE; + break; + case O_I_WT_NO_WR_ALLOC: + attr = CACHEABLE; + break; + case O_I_WB_NO_WR_ALLOC: + attr = CACHEABLE | BUFFERABLE; + break; + case O_I_NON_CACHEABLE: + attr = 1 << TEX_SHIFT; + break; + case O_I_WB_RD_WR_ALLOC: + attr = (1 << TEX_SHIFT) | CACHEABLE | BUFFERABLE; + break; + case DEVICE_NON_SHARED: + attr = (2 << TEX_SHIFT) | BUFFERABLE; + break; + default: + attr = 0; /* strongly ordered */ + break; + }; + + return attr; +} + +#endif /* _ASM_ARMV7_MPU_H */ diff --git a/roms/u-boot/arch/arm/include/asm/armv7m.h b/roms/u-boot/arch/arm/include/asm/armv7m.h new file mode 100644 index 000000000..ad67b4fa3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/armv7m.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010,2011 + * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com + * + * (C) Copyright 2015 + * Kamil Lulko, + */ + +#ifndef ARMV7M_H +#define ARMV7M_H + +/* armv7m fixed base addresses */ +#define V7M_SCS_BASE 0xE000E000 +#define V7M_NVIC_BASE (V7M_SCS_BASE + 0x0100) +#define V7M_SCB_BASE (V7M_SCS_BASE + 0x0D00) +#define V7M_PROC_FTR_BASE (V7M_SCS_BASE + 0x0D78) +#define V7M_MPU_BASE (V7M_SCS_BASE + 0x0D90) +#define V7M_FPU_BASE (V7M_SCS_BASE + 0x0F30) +#define V7M_CACHE_MAINT_BASE (V7M_SCS_BASE + 0x0F50) +#define V7M_ACCESS_CNTL_BASE (V7M_SCS_BASE + 0x0F90) + +#define V7M_SCB_VTOR 0x08 + +#if !defined(__ASSEMBLY__) +struct v7m_scb { + uint32_t cpuid; /* CPUID Base Register */ + uint32_t icsr; /* Interrupt Control and State Register */ + uint32_t vtor; /* Vector Table Offset Register */ + uint32_t aircr; /* App Interrupt and Reset Control Register */ + uint32_t scr; /* offset 0x10: System Control Register */ + uint32_t ccr; /* offset 0x14: Config and Control Register */ + uint32_t shpr1; /* offset 0x18: System Handler Priority Reg 1 */ + uint32_t shpr2; /* offset 0x1c: System Handler Priority Reg 2 */ + uint32_t shpr3; /* offset 0x20: System Handler Priority Reg 3 */ + uint32_t shcrs; /* offset 0x24: System Handler Control State */ + uint32_t cfsr; /* offset 0x28: Configurable Fault Status Reg */ + uint32_t hfsr; /* offset 0x2C: HardFault Status Register */ + uint32_t res; /* offset 0x30: reserved */ + uint32_t mmar; /* offset 0x34: MemManage Fault Address Reg */ + uint32_t bfar; /* offset 0x38: BusFault Address Reg */ + uint32_t afsr; /* offset 0x3C: Auxiliary Fault Status Reg */ +}; +#define V7M_SCB ((struct v7m_scb *)V7M_SCB_BASE) + +#define V7M_AIRCR_VECTKEY 0x5fa +#define V7M_AIRCR_VECTKEY_SHIFT 16 +#define V7M_AIRCR_ENDIAN (1 << 15) +#define V7M_AIRCR_PRIGROUP_SHIFT 8 +#define V7M_AIRCR_PRIGROUP_MSK (0x7 << V7M_AIRCR_PRIGROUP_SHIFT) +#define V7M_AIRCR_SYSRESET (1 << 2) + +#define V7M_ICSR_VECTACT_MSK 0xFF + +#define V7M_CCR_DCACHE 16 +#define V7M_CCR_ICACHE 17 + +struct v7m_mpu { + uint32_t type; /* Type Register */ + uint32_t ctrl; /* Control Register */ + uint32_t rnr; /* Region Number Register */ + uint32_t rbar; /* Region Base Address Register */ + uint32_t rasr; /* Region Attribute and Size Register */ +}; +#define V7M_MPU ((struct v7m_mpu *)V7M_MPU_BASE) + +#endif /* !defined(__ASSEMBLY__) */ +#endif /* ARMV7M_H */ diff --git a/roms/u-boot/arch/arm/include/asm/armv8/cpu.h b/roms/u-boot/arch/arm/include/asm/armv8/cpu.h new file mode 100644 index 000000000..40d54dc85 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/armv8/cpu.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define MIDR_PARTNUM_CORTEX_A35 0xD04 +#define MIDR_PARTNUM_CORTEX_A53 0xD03 +#define MIDR_PARTNUM_CORTEX_A72 0xD08 +#define MIDR_PARTNUM_SHIFT 0x4 +#define MIDR_PARTNUM_MASK (0xFFF << 0x4) + +static inline unsigned int read_midr(void) +{ + unsigned long val; + + asm volatile("mrs %0, midr_el1" : "=r" (val)); + + return val; +} + +#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \ + MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35) +#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \ + MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53) +#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\ + MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72) diff --git a/roms/u-boot/arch/arm/include/asm/armv8/mmu.h b/roms/u-boot/arch/arm/include/asm/armv8/mmu.h new file mode 100644 index 000000000..fc97c5511 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/armv8/mmu.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 + * David Feng + */ + +#ifndef _ASM_ARMV8_MMU_H_ +#define _ASM_ARMV8_MMU_H_ + +#include +#include + +/* + * block/section address mask and size definitions. + */ + +/* PAGE_SHIFT determines the page size */ +#undef PAGE_SIZE +#define PAGE_SHIFT 12 +#define PAGE_SIZE (1 << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE - 1)) + +/***************************************************************/ + +/* + * Memory types + */ +#define MT_DEVICE_NGNRNE 0 +#define MT_DEVICE_NGNRE 1 +#define MT_DEVICE_GRE 2 +#define MT_NORMAL_NC 3 +#define MT_NORMAL 4 + +#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \ + (0x04 << (MT_DEVICE_NGNRE * 8)) | \ + (0x0c << (MT_DEVICE_GRE * 8)) | \ + (0x44 << (MT_NORMAL_NC * 8)) | \ + (UL(0xff) << (MT_NORMAL * 8))) + +/* + * Hardware page table definitions. + * + */ + +#define PTE_TYPE_MASK (3 << 0) +#define PTE_TYPE_FAULT (0 << 0) +#define PTE_TYPE_TABLE (3 << 0) +#define PTE_TYPE_PAGE (3 << 0) +#define PTE_TYPE_BLOCK (1 << 0) +#define PTE_TYPE_VALID (1 << 0) + +#define PTE_TABLE_PXN (1UL << 59) +#define PTE_TABLE_XN (1UL << 60) +#define PTE_TABLE_AP (1UL << 61) +#define PTE_TABLE_NS (1UL << 63) + +/* + * Block + */ +#define PTE_BLOCK_MEMTYPE(x) ((x) << 2) +#define PTE_BLOCK_NS (1 << 5) +#define PTE_BLOCK_NON_SHARE (0 << 8) +#define PTE_BLOCK_OUTER_SHARE (2 << 8) +#define PTE_BLOCK_INNER_SHARE (3 << 8) +#define PTE_BLOCK_AF (1 << 10) +#define PTE_BLOCK_NG (1 << 11) +#define PTE_BLOCK_PXN (UL(1) << 53) +#define PTE_BLOCK_UXN (UL(1) << 54) + +/* + * AttrIndx[2:0] + */ +#define PMD_ATTRINDX(t) ((t) << 2) +#define PMD_ATTRINDX_MASK (7 << 2) +#define PMD_ATTRMASK (PTE_BLOCK_PXN | \ + PTE_BLOCK_UXN | \ + PMD_ATTRINDX_MASK | \ + PTE_TYPE_VALID) + +/* + * TCR flags. + */ +#define TCR_T0SZ(x) ((64 - (x)) << 0) +#define TCR_IRGN_NC (0 << 8) +#define TCR_IRGN_WBWA (1 << 8) +#define TCR_IRGN_WT (2 << 8) +#define TCR_IRGN_WBNWA (3 << 8) +#define TCR_IRGN_MASK (3 << 8) +#define TCR_ORGN_NC (0 << 10) +#define TCR_ORGN_WBWA (1 << 10) +#define TCR_ORGN_WT (2 << 10) +#define TCR_ORGN_WBNWA (3 << 10) +#define TCR_ORGN_MASK (3 << 10) +#define TCR_SHARED_NON (0 << 12) +#define TCR_SHARED_OUTER (2 << 12) +#define TCR_SHARED_INNER (3 << 12) +#define TCR_TG0_4K (0 << 14) +#define TCR_TG0_64K (1 << 14) +#define TCR_TG0_16K (2 << 14) +#define TCR_EPD1_DISABLE (1 << 23) + +#define TCR_EL1_RSVD (1 << 31) +#define TCR_EL2_RSVD (1 << 31 | 1 << 23) +#define TCR_EL3_RSVD (1 << 31 | 1 << 23) + +#ifndef __ASSEMBLY__ +static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) +{ + asm volatile("dsb sy"); + if (el == 1) { + asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory"); + asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory"); + asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory"); + } else if (el == 2) { + asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory"); + asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory"); + asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory"); + } else if (el == 3) { + asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory"); + asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory"); + asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory"); + } else { + hang(); + } + asm volatile("isb"); +} + +struct mm_region { + u64 virt; + u64 phys; + u64 size; + u64 attrs; +}; + +extern struct mm_region *mem_map; +void setup_pgtables(void); +u64 get_tcr(int el, u64 *pips, u64 *pva_bits); +#endif + +#endif /* _ASM_ARMV8_MMU_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/armv8/sec_firmware.h b/roms/u-boot/arch/arm/include/asm/armv8/sec_firmware.h new file mode 100644 index 000000000..0f86c72b2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/armv8/sec_firmware.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 NXP Semiconductor, Inc. + */ + +#ifndef __SEC_FIRMWARE_H_ +#define __SEC_FIRMWARE_H_ + +#define PSCI_INVALID_VER 0xffffffff +#define SEC_JR3_OFFSET 0x40000 +#define WORD_MASK 0xffffffff +#define WORD_SHIFT 32 + +int sec_firmware_init(const void *, u32 *, u32 *, u32 *, u32 *); +int _sec_firmware_entry(const void *, u32 *, u32 *); +bool sec_firmware_is_valid(const void *); +bool sec_firmware_support_hwrng(void); +int sec_firmware_get_random(uint8_t *rand, int bytes); +int fdt_fixup_kaslr(void *fdt); +#ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI +unsigned int sec_firmware_support_psci_version(void); +unsigned int _sec_firmware_support_psci_version(void); +#else +static inline unsigned int sec_firmware_support_psci_version(void) +{ + return PSCI_INVALID_VER; +} +#endif + +static inline unsigned int sec_firmware_used_jobring_offset(void) +{ + return SEC_JR3_OFFSET; +} + +#endif /* __SEC_FIRMWARE_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/assembler.h b/roms/u-boot/arch/arm/include/asm/assembler.h new file mode 100644 index 000000000..b14691858 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/assembler.h @@ -0,0 +1,84 @@ +/* + * arch/arm/include/asm/assembler.h + * + * Copyright (C) 1996-2000 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This file contains arm architecture specific defines + * for the different processors. + * + * Do not include any C declarations in this file - it is included by + * assembler source. + */ + +#include +#include + +/* + * Endian independent macros for shifting bytes within registers. + */ +#ifndef __ARMEB__ +#define lspull lsr +#define lspush lsl +#define get_byte_0 lsl #0 +#define get_byte_1 lsr #8 +#define get_byte_2 lsr #16 +#define get_byte_3 lsr #24 +#define put_byte_0 lsl #0 +#define put_byte_1 lsl #8 +#define put_byte_2 lsl #16 +#define put_byte_3 lsl #24 +#else +#define lspull lsl +#define lspush lsr +#define get_byte_0 lsr #24 +#define get_byte_1 lsr #16 +#define get_byte_2 lsr #8 +#define get_byte_3 lsl #0 +#define put_byte_0 lsl #24 +#define put_byte_1 lsl #16 +#define put_byte_2 lsl #8 +#define put_byte_3 lsl #0 +#endif + +/* + * Data preload for architectures that support it + */ +#if defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) || \ + defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \ + defined(__ARM_ARCH_6T2__) || defined(__ARM_ARCH_6Z__) || \ + defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_7A__) || \ + defined(__ARM_ARCH_7R__) +#define PLD(code...) code +#else +#define PLD(code...) +#endif + +/* + * We only support cores that support at least Thumb-1 and thus we use + * 'bx lr' + */ + .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo + .macro ret\c, reg + .ifeqs "\reg", "lr" + bx\c \reg + .else + mov\c pc, \reg + .endif + .endm + .endr + +/* + * Cache aligned, used for optimized memcpy/memset + * In the kernel this is only enabled for Feroceon CPU's... + * We disable it especially for Thumb builds since those instructions + * are not made in a Thumb ready way... + */ +#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) +#define CALGN(code...) +#else +#define CALGN(code...) code +#endif diff --git a/roms/u-boot/arch/arm/include/asm/atomic.h b/roms/u-boot/arch/arm/include/asm/atomic.h new file mode 100644 index 000000000..5822b0a52 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/atomic.h @@ -0,0 +1,32 @@ +/* + * linux/include/asm-arm/atomic.h + * + * Copyright (c) 1996 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Changelog: + * 27-06-1996 RMK Created + * 13-04-1997 RMK Made functions atomic! + * 07-12-1997 RMK Upgraded for v2.1. + * 26-08-1998 PJB Added #ifdef __KERNEL__ + */ +#ifndef __ASM_ARM_ATOMIC_H +#define __ASM_ARM_ATOMIC_H + +#ifdef CONFIG_SMP +#error SMP not supported +#endif + +#include +#include + +/* Atomic operations are already serializing on ARM */ +#define smp_mb__before_atomic_dec() barrier() +#define smp_mb__after_atomic_dec() barrier() +#define smp_mb__before_atomic_inc() barrier() +#define smp_mb__after_atomic_inc() barrier() + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/barriers.h b/roms/u-boot/arch/arm/include/asm/barriers.h new file mode 100644 index 000000000..75b9eb4bc --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/barriers.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 ARM Ltd. + * + * ARM and ARM64 barrier instructions + * split from armv7.h to allow sharing between ARM and ARM64 + * + * Original copyright in armv7.h was: + * (C) Copyright 2010 Texas Instruments, Aneesh V + * + * Much of the original barrier code was contributed by: + * Valentine Barshak + */ +#ifndef __BARRIERS_H__ +#define __BARRIERS_H__ + +#ifndef __ASSEMBLY__ + +#ifndef CONFIG_ARM64 +/* + * CP15 Barrier instructions + * Please note that we have separate barrier instructions in ARMv7 + * However, we use the CP15 based instructtions because we use + * -march=armv5 in U-Boot + */ +#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) +#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) +#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) + +#endif /* !CONFIG_ARM64 */ + +#if __LINUX_ARM_ARCH__ >= 7 +#define ISB asm volatile ("isb sy" : : : "memory") +#define DSB asm volatile ("dsb sy" : : : "memory") +#define DMB asm volatile ("dmb sy" : : : "memory") +#elif __LINUX_ARM_ARCH__ == 6 +#define ISB CP15ISB +#define DSB CP15DSB +#define DMB CP15DMB +#else +#define ISB asm volatile ("" : : : "memory") +#define DSB CP15DSB +#define DMB asm volatile ("" : : : "memory") +#endif + +#define isb() ISB +#define dsb() DSB +#define dmb() DMB +#endif /* __ASSEMBLY__ */ +#endif /* __BARRIERS_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/bitops.h b/roms/u-boot/arch/arm/include/asm/bitops.h new file mode 100644 index 000000000..fa8548624 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/bitops.h @@ -0,0 +1,185 @@ +/* + * Copyright 1995, Russell King. + * Various bits and pieces copyrights include: + * Linus Torvalds (test_bit). + * + * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). + * + * Please note that the code in this file should never be included + * from user space. Many of these are not implemented in assembler + * since they would be too costly. Also, they require priviledged + * instructions (which are not available from user mode) to ensure + * that they are atomic. + */ + +#ifndef __ASM_ARM_BITOPS_H +#define __ASM_ARM_BITOPS_H + +#include +#include +#include +#include + +#ifdef __KERNEL__ + +#ifndef __ASSEMBLY__ +#include +#endif +#include + +#define smp_mb__before_clear_bit() do { } while (0) +#define smp_mb__after_clear_bit() do { } while (0) + +/* + * Function prototypes to keep gcc -Wall happy. + */ +extern void set_bit(int nr, volatile void * addr); + +extern void clear_bit(int nr, volatile void * addr); + +extern void change_bit(int nr, volatile void * addr); + +static inline void __change_bit(int nr, volatile void *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p ^= mask; +} + +static inline int __test_and_set_bit(int nr, volatile void *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old | mask; + return (old & mask) != 0; +} + +static inline int test_and_set_bit(int nr, volatile void * addr) +{ + unsigned long flags = 0; + int out; + + local_irq_save(flags); + out = __test_and_set_bit(nr, addr); + local_irq_restore(flags); + + return out; +} + +static inline int __test_and_clear_bit(int nr, volatile void *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old & ~mask; + return (old & mask) != 0; +} + +static inline int test_and_clear_bit(int nr, volatile void * addr) +{ + unsigned long flags = 0; + int out; + + local_irq_save(flags); + out = __test_and_clear_bit(nr, addr); + local_irq_restore(flags); + + return out; +} + +extern int test_and_change_bit(int nr, volatile void * addr); + +static inline int __test_and_change_bit(int nr, volatile void *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old ^ mask; + return (old & mask) != 0; +} + +/* + * This routine doesn't need to be atomic. + */ +static inline int test_bit(int nr, const void * addr) +{ + return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7)); +} + +static inline int __ilog2(unsigned int x) +{ + return generic_fls(x) - 1; +} + +#define ffz(x) __ffs(~(x)) + +static inline int find_next_zero_bit(void *addr, int size, int offset) +{ + unsigned long *p = ((unsigned long *)addr) + (offset / BITS_PER_LONG); + unsigned long result = offset & ~(BITS_PER_LONG - 1); + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= (BITS_PER_LONG - 1); + if (offset) { + tmp = *(p++); + tmp |= ~0UL >> (BITS_PER_LONG - offset); + if (size < BITS_PER_LONG) + goto found_first; + if (~tmp) + goto found_middle; + size -= BITS_PER_LONG; + result += BITS_PER_LONG; + } + while (size & ~(BITS_PER_LONG - 1)) { + tmp = *(p++); + if (~tmp) + goto found_middle; + result += BITS_PER_LONG; + size -= BITS_PER_LONG; + } + if (!size) + return result; + tmp = *p; + +found_first: + tmp |= ~0UL << size; +found_middle: + return result + ffz(tmp); +} + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +#define find_first_zero_bit(addr, size) \ + find_next_zero_bit((addr), (size), 0) + +#define ext2_set_bit test_and_set_bit +#define ext2_clear_bit test_and_clear_bit +#define ext2_test_bit test_bit +#define ext2_find_first_zero_bit find_first_zero_bit +#define ext2_find_next_zero_bit find_next_zero_bit + +/* Bitmap functions for the minix filesystem. */ +#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) +#define minix_set_bit(nr,addr) set_bit(nr,addr) +#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) +#define minix_test_bit(nr,addr) test_bit(nr,addr) +#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) + +#endif /* __KERNEL__ */ + +#endif /* _ARM_BITOPS_H */ diff --git a/roms/u-boot/arch/arm/include/asm/boot0-linux-kernel-header.h b/roms/u-boot/arch/arm/include/asm/boot0-linux-kernel-header.h new file mode 100644 index 000000000..c6cd76f32 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/boot0-linux-kernel-header.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2017 NVIDIA Corporation + * + * Derived from Linux kernel v4.14 files: + * + * arch/arm64/include/asm/assembler.h: + * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S + * Copyright (C) 1996-2000 Russell King + * Copyright (C) 2012 ARM Ltd. + * + * arch/arm64/kernel/head.S: + * Based on arch/arm/kernel/head.S + * Copyright (C) 1994-2002 Russell King + * Copyright (C) 2003-2012 ARM Ltd. + * Authors: Catalin Marinas + * Will Deacon + * + * arch/arm64/kernel/image.h: + * Copyright (C) 2014 ARM Ltd. + */ + + /* + * Emit a 64-bit absolute little endian symbol reference in a way that + * ensures that it will be resolved at build time, even when building a + * PIE binary. This requires cooperation from the linker script, which + * must emit the lo32/hi32 halves individually. + */ + .macro le64sym, sym + .long \sym\()_lo32 + .long \sym\()_hi32 + .endm + +.globl _start +_start: + /* + * DO NOT MODIFY. Image header expected by Linux boot-loaders. + */ + b reset /* branch to kernel start, magic */ + .long 0 /* reserved */ + le64sym _kernel_offset_le /* Image load offset from start of RAM, little-endian */ + le64sym _kernel_size_le /* Effective size of kernel image, little-endian */ + le64sym _kernel_flags_le /* Informative flags, little-endian */ + .quad 0 /* reserved */ + .quad 0 /* reserved */ + .quad 0 /* reserved */ + .ascii "ARM\x64" /* Magic number */ + .long 0 /* reserved */ diff --git a/roms/u-boot/arch/arm/include/asm/bootm.h b/roms/u-boot/arch/arm/include/asm/bootm.h new file mode 100644 index 000000000..a2131ca07 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/bootm.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2013, Google Inc. + * + * Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz + */ +#ifndef ARM_BOOTM_H +#define ARM_BOOTM_H + +extern void udc_disconnect(void); + +#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ + defined(CONFIG_CMDLINE_TAG) || \ + defined(CONFIG_INITRD_TAG) || \ + defined(CONFIG_SERIAL_TAG) || \ + defined(CONFIG_REVISION_TAG) +# define BOOTM_ENABLE_TAGS 1 +#else +# define BOOTM_ENABLE_TAGS 0 +#endif + +#ifdef CONFIG_SETUP_MEMORY_TAGS +# define BOOTM_ENABLE_MEMORY_TAGS 1 +#else +# define BOOTM_ENABLE_MEMORY_TAGS 0 +#endif + +#ifdef CONFIG_CMDLINE_TAG + #define BOOTM_ENABLE_CMDLINE_TAG 1 +#else + #define BOOTM_ENABLE_CMDLINE_TAG 0 +#endif + +#ifdef CONFIG_INITRD_TAG + #define BOOTM_ENABLE_INITRD_TAG 1 +#else + #define BOOTM_ENABLE_INITRD_TAG 0 +#endif + +struct tag_serialnr; +#ifdef CONFIG_SERIAL_TAG + #define BOOTM_ENABLE_SERIAL_TAG 1 +void get_board_serial(struct tag_serialnr *serialnr); +#else + #define BOOTM_ENABLE_SERIAL_TAG 0 +static inline void get_board_serial(struct tag_serialnr *serialnr) +{ +} +#endif + +#ifdef CONFIG_REVISION_TAG + #define BOOTM_ENABLE_REVISION_TAG 1 +u32 get_board_rev(void); +#else + #define BOOTM_ENABLE_REVISION_TAG 0 +static inline u32 get_board_rev(void) +{ + return 0; +} +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/byteorder.h b/roms/u-boot/arch/arm/include/asm/byteorder.h new file mode 100644 index 000000000..20cce7657 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/byteorder.h @@ -0,0 +1,32 @@ +/* + * linux/include/asm-arm/byteorder.h + * + * ARM Endian-ness. In little endian mode, the data bus is connected such + * that byte accesses appear as: + * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 + * and word accesses (data or instruction) appear as: + * d0...d31 + * + * When in big endian mode, byte accesses appear as: + * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 + * and word accesses (data or instruction) appear as: + * d0...d31 + */ +#ifndef __ASM_ARM_BYTEORDER_H +#define __ASM_ARM_BYTEORDER_H + + +#include + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#if defined(__ARMEB__) || defined(__AARCH64EB__) +#include +#else +#include +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/cache.h b/roms/u-boot/arch/arm/include/asm/cache.h new file mode 100644 index 000000000..b10edf805 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/cache.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + */ + +#ifndef _ASM_CACHE_H +#define _ASM_CACHE_H + +#include + +#ifndef CONFIG_ARM64 + +/* + * Invalidate L2 Cache using co-proc instruction + */ +#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) +void invalidate_l2_cache(void); +#else +static inline void invalidate_l2_cache(void) +{ + unsigned int val=0; + + asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" + : : "r" (val) : "cc"); + isb(); +} +#endif + +int check_cache_range(unsigned long start, unsigned long stop); + +void l2_cache_enable(void); +void l2_cache_disable(void); +void set_section_dcache(int section, enum dcache_option option); + +void arm_init_before_mmu(void); +void cpu_cache_initialization(void); +void dram_bank_mmu_setup(int bank); + +#endif + +/* + * The value of the largest data cache relevant to DMA operations shall be set + * for us in CONFIG_SYS_CACHELINE_SIZE. In some cases this may be a larger + * value than found in the L1 cache but this is OK to use in terms of + * alignment. + */ +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE + +/* + * arm_reserve_mmu() - Reserve memory for MMU TLB table + * + * Default implementation for reserving memory for MMU TLB table. It is used + * during generic board init sequence in common/board_f.c. Weakly defined, so + * that machines can override it if needed. + * + * Return: 0 if OK + */ +int arm_reserve_mmu(void); + +#endif /* _ASM_CACHE_H */ diff --git a/roms/u-boot/arch/arm/include/asm/config.h b/roms/u-boot/arch/arm/include/asm/config.h new file mode 100644 index 000000000..14860d89b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/config.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#define CONFIG_SYS_BOOT_RAMDISK_HIGH + +#if defined(CONFIG_ARCH_LS1021A) || \ + defined(CONFIG_CPU_PXA27X) || \ + defined(CONFIG_CPU_MONAHANS) || \ + defined(CONFIG_CPU_PXA25X) || \ + defined(CONFIG_FSL_LAYERSCAPE) +#include +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/davinci_rtc.h b/roms/u-boot/arch/arm/include/asm/davinci_rtc.h new file mode 100644 index 000000000..7894bd9ce --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/davinci_rtc.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Based on: + * + * ------------------------------------------------------------------------- + * + * linux/include/asm-arm/arch-davinci/hardware.h + * + * Copyright (C) 2006 Texas Instruments. + */ +#ifndef __ASM_DAVINCI_RTC_H +#define __ASM_DAVINCI_RTC_H + +struct davinci_rtc { + unsigned int second; + unsigned int minutes; + unsigned int hours; + unsigned int day; + unsigned int month; /* 0x10 */ + unsigned int year; + unsigned int dotw; + unsigned int resv1; + unsigned int alarmsecond; /* 0x20 */ + unsigned int alarmminute; + unsigned int alarmhour; + unsigned int alarmday; + unsigned int alarmmonth; /* 0x30 */ + unsigned int alarmyear; + unsigned int resv2[2]; + unsigned int ctrl; /* 0x40 */ + unsigned int status; + unsigned int irq; + unsigned int complsb; + unsigned int compmsb; /* 0x50 */ + unsigned int osc; + unsigned int resv3[2]; + unsigned int scratch0; /* 0x60 */ + unsigned int scratch1; + unsigned int scratch2; + unsigned int kick0r; + unsigned int kick1r; /* 0x70 */ +}; + +#define RTC_STATE_BUSY 0x01 +#define RTC_STATE_RUN 0x02 + +#define RTC_KICK0R_WE 0x83e70b13 +#define RTC_KICK1R_WE 0x95a4f1e0 +#endif diff --git a/roms/u-boot/arch/arm/include/asm/dma-mapping.h b/roms/u-boot/arch/arm/include/asm/dma-mapping.h new file mode 100644 index 000000000..8af1ea0aa --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/dma-mapping.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007 + * Stelian Pop + * Lead Tech Design + */ +#ifndef __ASM_ARM_DMA_MAPPING_H +#define __ASM_ARM_DMA_MAPPING_H + +#include +#include +#include +#include +#include +#include + +static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) +{ + *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, ROUND(len, ARCH_DMA_MINALIGN)); + return (void *)*handle; +} + +static inline void dma_free_coherent(void *addr) +{ + free(addr); +} + +#endif /* __ASM_ARM_DMA_MAPPING_H */ diff --git a/roms/u-boot/arch/arm/include/asm/ehci-omap.h b/roms/u-boot/arch/arm/include/asm/ehci-omap.h new file mode 100644 index 000000000..f970bba93 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/ehci-omap.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * OMAP EHCI port support + * Based on LINUX KERNEL + * drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com* + * Author: Govindraj R + */ + +#ifndef _OMAP_COMMON_EHCI_H_ +#define _OMAP_COMMON_EHCI_H_ + +enum usbhs_omap_port_mode { + OMAP_USBHS_PORT_MODE_UNUSED, + OMAP_EHCI_PORT_MODE_PHY, + OMAP_EHCI_PORT_MODE_TLL, + OMAP_EHCI_PORT_MODE_HSIC, +}; + +#define OMAP_HS_USB_PORTS 3 + +#define is_ehci_phy_mode(x) ((x) == OMAP_EHCI_PORT_MODE_PHY) +#define is_ehci_tll_mode(x) ((x) == OMAP_EHCI_PORT_MODE_TLL) +#define is_ehci_hsic_mode(x) ((x) == OMAP_EHCI_PORT_MODE_HSIC) + +/* Values of UHH_REVISION - Note: these are not given in the TRM */ +#define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */ +#define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */ +#define OMAP_USBHS_REV2_1 0x50700101 /* OMAP5 */ + +/* UHH Register Set */ +#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2) +#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3) +#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4) +#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5) + +#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS 1 +#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11) +#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12) +#define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31) + +#define OMAP_P1_MODE_CLEAR (3 << 16) +#define OMAP_P1_MODE_TLL (1 << 16) +#define OMAP_P1_MODE_HSIC (3 << 16) +#define OMAP_P2_MODE_CLEAR (3 << 18) +#define OMAP_P2_MODE_TLL (1 << 18) +#define OMAP_P2_MODE_HSIC (3 << 18) +#define OMAP_P3_MODE_CLEAR (3 << 20) +#define OMAP_P3_MODE_HSIC (3 << 20) + +/* EHCI Register Set */ +#define EHCI_INSNREG04_DISABLE_UNSUSPEND (1 << 5) +#define EHCI_INSNREG05_ULPI_CONTROL_SHIFT 31 +#define EHCI_INSNREG05_ULPI_PORTSEL_SHIFT 24 +#define EHCI_INSNREG05_ULPI_OPSEL_SHIFT 22 +#define EHCI_INSNREG05_ULPI_REGADD_SHIFT 16 + +#define OMAP_REV1_TLL_CHANNEL_COUNT 3 +#define OMAP_REV2_TLL_CHANNEL_COUNT 2 + +/* TLL Register Set */ +#define OMAP_TLL_CHANNEL_CONF(num) (0x004 * num) +#define OMAP_TLL_CHANNEL_CONF_DRVVBUS (1 << 16) +#define OMAP_TLL_CHANNEL_CONF_CHRGVBUS (1 << 15) +#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11) +#define OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI (2 << 1) +#define OMAP_TLL_CHANNEL_CONF_CHANEN 1 + +struct omap_usbhs_board_data { + enum usbhs_omap_port_mode port_mode[OMAP_HS_USB_PORTS]; +}; + +struct omap_usbtll { + u32 rev; /* 0x00 */ + u32 hwinfo; /* 0x04 */ + u8 reserved1[0x8]; + u32 sysc; /* 0x10 */ + u32 syss; /* 0x14 */ + u32 irqst; /* 0x18 */ + u32 irqen; /* 0x1c */ + u8 reserved2[0x10]; + u32 shared_conf; /* 0x30 */ + u8 reserved3[0xc]; + u32 channel_conf; /* 0x40 */ +}; + +struct omap_uhh { + u32 rev; /* 0x00 */ + u32 hwinfo; /* 0x04 */ + u8 reserved1[0x8]; + u32 sysc; /* 0x10 */ + u32 syss; /* 0x14 */ + u8 reserved2[0x28]; + u32 hostconfig; /* 0x40 */ + u32 debugcsr; /* 0x44 */ +}; + +struct omap_ehci { + u32 hccapbase; /* 0x00 */ + u32 hcsparams; /* 0x04 */ + u32 hccparams; /* 0x08 */ + u8 reserved1[0x04]; + u32 usbcmd; /* 0x10 */ + u32 usbsts; /* 0x14 */ + u32 usbintr; /* 0x18 */ + u32 frindex; /* 0x1c */ + u32 ctrldssegment; /* 0x20 */ + u32 periodiclistbase; /* 0x24 */ + u32 asysnclistaddr; /* 0x28 */ + u8 reserved2[0x24]; + u32 configflag; /* 0x50 */ + u32 portsc_i; /* 0x54 */ + u8 reserved3[0x38]; + u32 insreg00; /* 0x90 */ + u32 insreg01; /* 0x94 */ + u32 insreg02; /* 0x98 */ + u32 insreg03; /* 0x9c */ + u32 insreg04; /* 0xa0 */ + u32 insreg05_utmi_ulpi; /* 0xa4 */ + u32 insreg06; /* 0xa8 */ + u32 insreg07; /* 0xac */ + u32 insreg08; /* 0xb0 */ +}; + +#if !CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL) +/* + * FIXME: forward declaration of this structs needed because omap got the + * ehci implementation backwards. move out ehci_hcd_x from board files + */ +struct ehci_hccr; +struct ehci_hcor; + +int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata, + struct ehci_hccr **hccr, struct ehci_hcor **hcor); +int omap_ehci_hcd_stop(void); +#endif + +#endif /* _OMAP_COMMON_EHCI_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/emif.h b/roms/u-boot/arch/arm/include/asm/emif.h new file mode 100644 index 000000000..35424345b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/emif.h @@ -0,0 +1,1303 @@ +/* + * OMAP44xx EMIF header + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Aneesh V + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _EMIF_H_ +#define _EMIF_H_ +#include +#include + +/* Base address */ +#ifndef EMIF1_BASE +#define EMIF1_BASE 0x4c000000 +#endif +#define EMIF2_BASE 0x4d000000 + +#define EMIF_4D 0x4 +#define EMIF_4D5 0x5 + +/* Registers shifts, masks and values */ + +/* EMIF_MOD_ID_REV */ +#define EMIF_REG_SCHEME_SHIFT 30 +#define EMIF_REG_SCHEME_MASK (0x3 << 30) +#define EMIF_REG_MODULE_ID_SHIFT 16 +#define EMIF_REG_MODULE_ID_MASK (0xfff << 16) +#define EMIF_REG_RTL_VERSION_SHIFT 11 +#define EMIF_REG_RTL_VERSION_MASK (0x1f << 11) +#define EMIF_REG_MAJOR_REVISION_SHIFT 8 +#define EMIF_REG_MAJOR_REVISION_MASK (0x7 << 8) +#define EMIF_REG_MINOR_REVISION_SHIFT 0 +#define EMIF_REG_MINOR_REVISION_MASK (0x3f << 0) + +/* STATUS */ +#define EMIF_REG_BE_SHIFT 31 +#define EMIF_REG_BE_MASK (1 << 31) +#define EMIF_REG_DUAL_CLK_MODE_SHIFT 30 +#define EMIF_REG_DUAL_CLK_MODE_MASK (1 << 30) +#define EMIF_REG_FAST_INIT_SHIFT 29 +#define EMIF_REG_FAST_INIT_MASK (1 << 29) +#define EMIF_REG_LEVLING_TO_SHIFT 4 +#define EMIF_REG_LEVELING_TO_MASK (7 << 4) +#define EMIF_REG_PHY_DLL_READY_SHIFT 2 +#define EMIF_REG_PHY_DLL_READY_MASK (1 << 2) + +/* SDRAM_CONFIG */ +#define EMIF_REG_SDRAM_TYPE_SHIFT 29 +#define EMIF_REG_SDRAM_TYPE_MASK (0x7 << 29) +#define EMIF_REG_SDRAM_TYPE_DDR1 0 +#define EMIF_REG_SDRAM_TYPE_LPDDR1 1 +#define EMIF_REG_SDRAM_TYPE_DDR2 2 +#define EMIF_REG_SDRAM_TYPE_DDR3 3 +#define EMIF_REG_SDRAM_TYPE_LPDDR2_S4 4 +#define EMIF_REG_SDRAM_TYPE_LPDDR2_S2 5 +#define EMIF_REG_IBANK_POS_SHIFT 27 +#define EMIF_REG_IBANK_POS_MASK (0x3 << 27) +#define EMIF_REG_DDR_TERM_SHIFT 24 +#define EMIF_REG_DDR_TERM_MASK (0x7 << 24) +#define EMIF_REG_DDR2_DDQS_SHIFT 23 +#define EMIF_REG_DDR2_DDQS_MASK (1 << 23) +#define EMIF_REG_DYN_ODT_SHIFT 21 +#define EMIF_REG_DYN_ODT_MASK (0x3 << 21) +#define EMIF_REG_DDR_DISABLE_DLL_SHIFT 20 +#define EMIF_REG_DDR_DISABLE_DLL_MASK (1 << 20) +#define EMIF_REG_SDRAM_DRIVE_SHIFT 18 +#define EMIF_REG_SDRAM_DRIVE_MASK (0x3 << 18) +#define EMIF_REG_CWL_SHIFT 16 +#define EMIF_REG_CWL_MASK (0x3 << 16) +#define EMIF_REG_NARROW_MODE_SHIFT 14 +#define EMIF_REG_NARROW_MODE_MASK (0x3 << 14) +#define EMIF_REG_CL_SHIFT 10 +#define EMIF_REG_CL_MASK (0xf << 10) +#define EMIF_REG_ROWSIZE_SHIFT 7 +#define EMIF_REG_ROWSIZE_MASK (0x7 << 7) +#define EMIF_REG_IBANK_SHIFT 4 +#define EMIF_REG_IBANK_MASK (0x7 << 4) +#define EMIF_REG_EBANK_SHIFT 3 +#define EMIF_REG_EBANK_MASK (1 << 3) +#define EMIF_REG_PAGESIZE_SHIFT 0 +#define EMIF_REG_PAGESIZE_MASK (0x7 << 0) + +/* SDRAM_CONFIG_2 */ +#define EMIF_REG_CS1NVMEN_SHIFT 30 +#define EMIF_REG_CS1NVMEN_MASK (1 << 30) +#define EMIF_REG_EBANK_POS_SHIFT 27 +#define EMIF_REG_EBANK_POS_MASK (1 << 27) +#define EMIF_REG_RDBNUM_SHIFT 4 +#define EMIF_REG_RDBNUM_MASK (0x3 << 4) +#define EMIF_REG_RDBSIZE_SHIFT 0 +#define EMIF_REG_RDBSIZE_MASK (0x7 << 0) + +/* SDRAM_REF_CTRL */ +#define EMIF_REG_INITREF_DIS_SHIFT 31 +#define EMIF_REG_INITREF_DIS_MASK (1 << 31) +#define EMIF_REG_SRT_SHIFT 29 +#define EMIF_REG_SRT_MASK (1 << 29) +#define EMIF_REG_ASR_SHIFT 28 +#define EMIF_REG_ASR_MASK (1 << 28) +#define EMIF_REG_PASR_SHIFT 24 +#define EMIF_REG_PASR_MASK (0x7 << 24) +#define EMIF_REG_REFRESH_RATE_SHIFT 0 +#define EMIF_REG_REFRESH_RATE_MASK (0xffff << 0) + +/* SDRAM_REF_CTRL_SHDW */ +#define EMIF_REG_REFRESH_RATE_SHDW_SHIFT 0 +#define EMIF_REG_REFRESH_RATE_SHDW_MASK (0xffff << 0) + +/* SDRAM_TIM_1 */ +#define EMIF_REG_T_RP_SHIFT 25 +#define EMIF_REG_T_RP_MASK (0xf << 25) +#define EMIF_REG_T_RCD_SHIFT 21 +#define EMIF_REG_T_RCD_MASK (0xf << 21) +#define EMIF_REG_T_WR_SHIFT 17 +#define EMIF_REG_T_WR_MASK (0xf << 17) +#define EMIF_REG_T_RAS_SHIFT 12 +#define EMIF_REG_T_RAS_MASK (0x1f << 12) +#define EMIF_REG_T_RC_SHIFT 6 +#define EMIF_REG_T_RC_MASK (0x3f << 6) +#define EMIF_REG_T_RRD_SHIFT 3 +#define EMIF_REG_T_RRD_MASK (0x7 << 3) +#define EMIF_REG_T_WTR_SHIFT 0 +#define EMIF_REG_T_WTR_MASK (0x7 << 0) + +/* SDRAM_TIM_1_SHDW */ +#define EMIF_REG_T_RP_SHDW_SHIFT 25 +#define EMIF_REG_T_RP_SHDW_MASK (0xf << 25) +#define EMIF_REG_T_RCD_SHDW_SHIFT 21 +#define EMIF_REG_T_RCD_SHDW_MASK (0xf << 21) +#define EMIF_REG_T_WR_SHDW_SHIFT 17 +#define EMIF_REG_T_WR_SHDW_MASK (0xf << 17) +#define EMIF_REG_T_RAS_SHDW_SHIFT 12 +#define EMIF_REG_T_RAS_SHDW_MASK (0x1f << 12) +#define EMIF_REG_T_RC_SHDW_SHIFT 6 +#define EMIF_REG_T_RC_SHDW_MASK (0x3f << 6) +#define EMIF_REG_T_RRD_SHDW_SHIFT 3 +#define EMIF_REG_T_RRD_SHDW_MASK (0x7 << 3) +#define EMIF_REG_T_WTR_SHDW_SHIFT 0 +#define EMIF_REG_T_WTR_SHDW_MASK (0x7 << 0) + +/* SDRAM_TIM_2 */ +#define EMIF_REG_T_XP_SHIFT 28 +#define EMIF_REG_T_XP_MASK (0x7 << 28) +#define EMIF_REG_T_ODT_SHIFT 25 +#define EMIF_REG_T_ODT_MASK (0x7 << 25) +#define EMIF_REG_T_XSNR_SHIFT 16 +#define EMIF_REG_T_XSNR_MASK (0x1ff << 16) +#define EMIF_REG_T_XSRD_SHIFT 6 +#define EMIF_REG_T_XSRD_MASK (0x3ff << 6) +#define EMIF_REG_T_RTP_SHIFT 3 +#define EMIF_REG_T_RTP_MASK (0x7 << 3) +#define EMIF_REG_T_CKE_SHIFT 0 +#define EMIF_REG_T_CKE_MASK (0x7 << 0) + +/* SDRAM_TIM_2_SHDW */ +#define EMIF_REG_T_XP_SHDW_SHIFT 28 +#define EMIF_REG_T_XP_SHDW_MASK (0x7 << 28) +#define EMIF_REG_T_ODT_SHDW_SHIFT 25 +#define EMIF_REG_T_ODT_SHDW_MASK (0x7 << 25) +#define EMIF_REG_T_XSNR_SHDW_SHIFT 16 +#define EMIF_REG_T_XSNR_SHDW_MASK (0x1ff << 16) +#define EMIF_REG_T_XSRD_SHDW_SHIFT 6 +#define EMIF_REG_T_XSRD_SHDW_MASK (0x3ff << 6) +#define EMIF_REG_T_RTP_SHDW_SHIFT 3 +#define EMIF_REG_T_RTP_SHDW_MASK (0x7 << 3) +#define EMIF_REG_T_CKE_SHDW_SHIFT 0 +#define EMIF_REG_T_CKE_SHDW_MASK (0x7 << 0) + +/* SDRAM_TIM_3 */ +#define EMIF_REG_T_CKESR_SHIFT 21 +#define EMIF_REG_T_CKESR_MASK (0x7 << 21) +#define EMIF_REG_ZQ_ZQCS_SHIFT 15 +#define EMIF_REG_ZQ_ZQCS_MASK (0x3f << 15) +#define EMIF_REG_T_TDQSCKMAX_SHIFT 13 +#define EMIF_REG_T_TDQSCKMAX_MASK (0x3 << 13) +#define EMIF_REG_T_RFC_SHIFT 4 +#define EMIF_REG_T_RFC_MASK (0x1ff << 4) +#define EMIF_REG_T_RAS_MAX_SHIFT 0 +#define EMIF_REG_T_RAS_MAX_MASK (0xf << 0) + +/* SDRAM_TIM_3_SHDW */ +#define EMIF_REG_T_CKESR_SHDW_SHIFT 21 +#define EMIF_REG_T_CKESR_SHDW_MASK (0x7 << 21) +#define EMIF_REG_ZQ_ZQCS_SHDW_SHIFT 15 +#define EMIF_REG_ZQ_ZQCS_SHDW_MASK (0x3f << 15) +#define EMIF_REG_T_TDQSCKMAX_SHDW_SHIFT 13 +#define EMIF_REG_T_TDQSCKMAX_SHDW_MASK (0x3 << 13) +#define EMIF_REG_T_RFC_SHDW_SHIFT 4 +#define EMIF_REG_T_RFC_SHDW_MASK (0x1ff << 4) +#define EMIF_REG_T_RAS_MAX_SHDW_SHIFT 0 +#define EMIF_REG_T_RAS_MAX_SHDW_MASK (0xf << 0) + +/* LPDDR2_NVM_TIM */ +#define EMIF_REG_NVM_T_XP_SHIFT 28 +#define EMIF_REG_NVM_T_XP_MASK (0x7 << 28) +#define EMIF_REG_NVM_T_WTR_SHIFT 24 +#define EMIF_REG_NVM_T_WTR_MASK (0x7 << 24) +#define EMIF_REG_NVM_T_RP_SHIFT 20 +#define EMIF_REG_NVM_T_RP_MASK (0xf << 20) +#define EMIF_REG_NVM_T_WRA_SHIFT 16 +#define EMIF_REG_NVM_T_WRA_MASK (0xf << 16) +#define EMIF_REG_NVM_T_RRD_SHIFT 8 +#define EMIF_REG_NVM_T_RRD_MASK (0xff << 8) +#define EMIF_REG_NVM_T_RCDMIN_SHIFT 0 +#define EMIF_REG_NVM_T_RCDMIN_MASK (0xff << 0) + +/* LPDDR2_NVM_TIM_SHDW */ +#define EMIF_REG_NVM_T_XP_SHDW_SHIFT 28 +#define EMIF_REG_NVM_T_XP_SHDW_MASK (0x7 << 28) +#define EMIF_REG_NVM_T_WTR_SHDW_SHIFT 24 +#define EMIF_REG_NVM_T_WTR_SHDW_MASK (0x7 << 24) +#define EMIF_REG_NVM_T_RP_SHDW_SHIFT 20 +#define EMIF_REG_NVM_T_RP_SHDW_MASK (0xf << 20) +#define EMIF_REG_NVM_T_WRA_SHDW_SHIFT 16 +#define EMIF_REG_NVM_T_WRA_SHDW_MASK (0xf << 16) +#define EMIF_REG_NVM_T_RRD_SHDW_SHIFT 8 +#define EMIF_REG_NVM_T_RRD_SHDW_MASK (0xff << 8) +#define EMIF_REG_NVM_T_RCDMIN_SHDW_SHIFT 0 +#define EMIF_REG_NVM_T_RCDMIN_SHDW_MASK (0xff << 0) + +/* PWR_MGMT_CTRL */ +#define EMIF_REG_IDLEMODE_SHIFT 30 +#define EMIF_REG_IDLEMODE_MASK (0x3 << 30) +#define EMIF_REG_PD_TIM_SHIFT 12 +#define EMIF_REG_PD_TIM_MASK (0xf << 12) +#define EMIF_REG_DPD_EN_SHIFT 11 +#define EMIF_REG_DPD_EN_MASK (1 << 11) +#define EMIF_REG_LP_MODE_SHIFT 8 +#define EMIF_REG_LP_MODE_MASK (0x7 << 8) +#define EMIF_REG_SR_TIM_SHIFT 4 +#define EMIF_REG_SR_TIM_MASK (0xf << 4) +#define EMIF_REG_CS_TIM_SHIFT 0 +#define EMIF_REG_CS_TIM_MASK (0xf << 0) + +/* PWR_MGMT_CTRL_SHDW */ +#define EMIF_REG_PD_TIM_SHDW_SHIFT 12 +#define EMIF_REG_PD_TIM_SHDW_MASK (0xf << 12) +#define EMIF_REG_SR_TIM_SHDW_SHIFT 4 +#define EMIF_REG_SR_TIM_SHDW_MASK (0xf << 4) +#define EMIF_REG_CS_TIM_SHDW_SHIFT 0 +#define EMIF_REG_CS_TIM_SHDW_MASK (0xf << 0) + +/* LPDDR2_MODE_REG_DATA */ +#define EMIF_REG_VALUE_0_SHIFT 0 +#define EMIF_REG_VALUE_0_MASK (0x7f << 0) + +/* LPDDR2_MODE_REG_CFG */ +#define EMIF_REG_CS_SHIFT 31 +#define EMIF_REG_CS_MASK (1 << 31) +#define EMIF_REG_REFRESH_EN_SHIFT 30 +#define EMIF_REG_REFRESH_EN_MASK (1 << 30) +#define EMIF_REG_ADDRESS_SHIFT 0 +#define EMIF_REG_ADDRESS_MASK (0xff << 0) + +/* OCP_CONFIG */ +#define EMIF_REG_SYS_THRESH_MAX_SHIFT 24 +#define EMIF_REG_SYS_THRESH_MAX_MASK (0xf << 24) +#define EMIF_REG_MPU_THRESH_MAX_SHIFT 20 +#define EMIF_REG_MPU_THRESH_MAX_MASK (0xf << 20) +#define EMIF_REG_LL_THRESH_MAX_SHIFT 16 +#define EMIF_REG_LL_THRESH_MAX_MASK (0xf << 16) +#define EMIF_REG_PR_OLD_COUNT_SHIFT 0 +#define EMIF_REG_PR_OLD_COUNT_MASK (0xff << 0) + +/* OCP_CFG_VAL_1 */ +#define EMIF_REG_SYS_BUS_WIDTH_SHIFT 30 +#define EMIF_REG_SYS_BUS_WIDTH_MASK (0x3 << 30) +#define EMIF_REG_LL_BUS_WIDTH_SHIFT 28 +#define EMIF_REG_LL_BUS_WIDTH_MASK (0x3 << 28) +#define EMIF_REG_WR_FIFO_DEPTH_SHIFT 8 +#define EMIF_REG_WR_FIFO_DEPTH_MASK (0xff << 8) +#define EMIF_REG_CMD_FIFO_DEPTH_SHIFT 0 +#define EMIF_REG_CMD_FIFO_DEPTH_MASK (0xff << 0) + +/* OCP_CFG_VAL_2 */ +#define EMIF_REG_RREG_FIFO_DEPTH_SHIFT 16 +#define EMIF_REG_RREG_FIFO_DEPTH_MASK (0xff << 16) +#define EMIF_REG_RSD_FIFO_DEPTH_SHIFT 8 +#define EMIF_REG_RSD_FIFO_DEPTH_MASK (0xff << 8) +#define EMIF_REG_RCMD_FIFO_DEPTH_SHIFT 0 +#define EMIF_REG_RCMD_FIFO_DEPTH_MASK (0xff << 0) + +/* IODFT_TLGC */ +#define EMIF_REG_TLEC_SHIFT 16 +#define EMIF_REG_TLEC_MASK (0xffff << 16) +#define EMIF_REG_MT_SHIFT 14 +#define EMIF_REG_MT_MASK (1 << 14) +#define EMIF_REG_ACT_CAP_EN_SHIFT 13 +#define EMIF_REG_ACT_CAP_EN_MASK (1 << 13) +#define EMIF_REG_OPG_LD_SHIFT 12 +#define EMIF_REG_OPG_LD_MASK (1 << 12) +#define EMIF_REG_RESET_PHY_SHIFT 10 +#define EMIF_REG_RESET_PHY_MASK (1 << 10) +#define EMIF_REG_MMS_SHIFT 8 +#define EMIF_REG_MMS_MASK (1 << 8) +#define EMIF_REG_MC_SHIFT 4 +#define EMIF_REG_MC_MASK (0x3 << 4) +#define EMIF_REG_PC_SHIFT 1 +#define EMIF_REG_PC_MASK (0x7 << 1) +#define EMIF_REG_TM_SHIFT 0 +#define EMIF_REG_TM_MASK (1 << 0) + +/* IODFT_CTRL_MISR_RSLT */ +#define EMIF_REG_DQM_TLMR_SHIFT 16 +#define EMIF_REG_DQM_TLMR_MASK (0x3ff << 16) +#define EMIF_REG_CTL_TLMR_SHIFT 0 +#define EMIF_REG_CTL_TLMR_MASK (0x7ff << 0) + +/* IODFT_ADDR_MISR_RSLT */ +#define EMIF_REG_ADDR_TLMR_SHIFT 0 +#define EMIF_REG_ADDR_TLMR_MASK (0x1fffff << 0) + +/* IODFT_DATA_MISR_RSLT_1 */ +#define EMIF_REG_DATA_TLMR_31_0_SHIFT 0 +#define EMIF_REG_DATA_TLMR_31_0_MASK (0xffffffff << 0) + +/* IODFT_DATA_MISR_RSLT_2 */ +#define EMIF_REG_DATA_TLMR_63_32_SHIFT 0 +#define EMIF_REG_DATA_TLMR_63_32_MASK (0xffffffff << 0) + +/* IODFT_DATA_MISR_RSLT_3 */ +#define EMIF_REG_DATA_TLMR_66_64_SHIFT 0 +#define EMIF_REG_DATA_TLMR_66_64_MASK (0x7 << 0) + +/* PERF_CNT_1 */ +#define EMIF_REG_COUNTER1_SHIFT 0 +#define EMIF_REG_COUNTER1_MASK (0xffffffff << 0) + +/* PERF_CNT_2 */ +#define EMIF_REG_COUNTER2_SHIFT 0 +#define EMIF_REG_COUNTER2_MASK (0xffffffff << 0) + +/* PERF_CNT_CFG */ +#define EMIF_REG_CNTR2_MCONNID_EN_SHIFT 31 +#define EMIF_REG_CNTR2_MCONNID_EN_MASK (1 << 31) +#define EMIF_REG_CNTR2_REGION_EN_SHIFT 30 +#define EMIF_REG_CNTR2_REGION_EN_MASK (1 << 30) +#define EMIF_REG_CNTR2_CFG_SHIFT 16 +#define EMIF_REG_CNTR2_CFG_MASK (0xf << 16) +#define EMIF_REG_CNTR1_MCONNID_EN_SHIFT 15 +#define EMIF_REG_CNTR1_MCONNID_EN_MASK (1 << 15) +#define EMIF_REG_CNTR1_REGION_EN_SHIFT 14 +#define EMIF_REG_CNTR1_REGION_EN_MASK (1 << 14) +#define EMIF_REG_CNTR1_CFG_SHIFT 0 +#define EMIF_REG_CNTR1_CFG_MASK (0xf << 0) + +/* PERF_CNT_SEL */ +#define EMIF_REG_MCONNID2_SHIFT 24 +#define EMIF_REG_MCONNID2_MASK (0xff << 24) +#define EMIF_REG_REGION_SEL2_SHIFT 16 +#define EMIF_REG_REGION_SEL2_MASK (0x3 << 16) +#define EMIF_REG_MCONNID1_SHIFT 8 +#define EMIF_REG_MCONNID1_MASK (0xff << 8) +#define EMIF_REG_REGION_SEL1_SHIFT 0 +#define EMIF_REG_REGION_SEL1_MASK (0x3 << 0) + +/* PERF_CNT_TIM */ +#define EMIF_REG_TOTAL_TIME_SHIFT 0 +#define EMIF_REG_TOTAL_TIME_MASK (0xffffffff << 0) + +/* READ_IDLE_CTRL */ +#define EMIF_REG_READ_IDLE_LEN_SHIFT 16 +#define EMIF_REG_READ_IDLE_LEN_MASK (0xf << 16) +#define EMIF_REG_READ_IDLE_INTERVAL_SHIFT 0 +#define EMIF_REG_READ_IDLE_INTERVAL_MASK (0x1ff << 0) + +/* READ_IDLE_CTRL_SHDW */ +#define EMIF_REG_READ_IDLE_LEN_SHDW_SHIFT 16 +#define EMIF_REG_READ_IDLE_LEN_SHDW_MASK (0xf << 16) +#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_SHIFT 0 +#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_MASK (0x1ff << 0) + +/* IRQ_EOI */ +#define EMIF_REG_EOI_SHIFT 0 +#define EMIF_REG_EOI_MASK (1 << 0) + +/* IRQSTATUS_RAW_SYS */ +#define EMIF_REG_DNV_SYS_SHIFT 2 +#define EMIF_REG_DNV_SYS_MASK (1 << 2) +#define EMIF_REG_TA_SYS_SHIFT 1 +#define EMIF_REG_TA_SYS_MASK (1 << 1) +#define EMIF_REG_ERR_SYS_SHIFT 0 +#define EMIF_REG_ERR_SYS_MASK (1 << 0) + +/* IRQSTATUS_RAW_LL */ +#define EMIF_REG_DNV_LL_SHIFT 2 +#define EMIF_REG_DNV_LL_MASK (1 << 2) +#define EMIF_REG_TA_LL_SHIFT 1 +#define EMIF_REG_TA_LL_MASK (1 << 1) +#define EMIF_REG_ERR_LL_SHIFT 0 +#define EMIF_REG_ERR_LL_MASK (1 << 0) + +/* IRQSTATUS_SYS */ + +/* IRQSTATUS_LL */ + +/* IRQENABLE_SET_SYS */ +#define EMIF_REG_EN_DNV_SYS_SHIFT 2 +#define EMIF_REG_EN_DNV_SYS_MASK (1 << 2) +#define EMIF_REG_EN_TA_SYS_SHIFT 1 +#define EMIF_REG_EN_TA_SYS_MASK (1 << 1) +#define EMIF_REG_EN_ERR_SYS_SHIFT 0 +#define EMIF_REG_EN_ERR_SYS_MASK (1 << 0) + +/* IRQENABLE_SET_LL */ +#define EMIF_REG_EN_DNV_LL_SHIFT 2 +#define EMIF_REG_EN_DNV_LL_MASK (1 << 2) +#define EMIF_REG_EN_TA_LL_SHIFT 1 +#define EMIF_REG_EN_TA_LL_MASK (1 << 1) +#define EMIF_REG_EN_ERR_LL_SHIFT 0 +#define EMIF_REG_EN_ERR_LL_MASK (1 << 0) + +/* IRQENABLE_CLR_SYS */ + +/* IRQENABLE_CLR_LL */ + +/* ZQ_CONFIG */ +#define EMIF_REG_ZQ_CS1EN_SHIFT 31 +#define EMIF_REG_ZQ_CS1EN_MASK (1 << 31) +#define EMIF_REG_ZQ_CS0EN_SHIFT 30 +#define EMIF_REG_ZQ_CS0EN_MASK (1 << 30) +#define EMIF_REG_ZQ_DUALCALEN_SHIFT 29 +#define EMIF_REG_ZQ_DUALCALEN_MASK (1 << 29) +#define EMIF_REG_ZQ_SFEXITEN_SHIFT 28 +#define EMIF_REG_ZQ_SFEXITEN_MASK (1 << 28) +#define EMIF_REG_ZQ_ZQINIT_MULT_SHIFT 18 +#define EMIF_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18) +#define EMIF_REG_ZQ_ZQCL_MULT_SHIFT 16 +#define EMIF_REG_ZQ_ZQCL_MULT_MASK (0x3 << 16) +#define EMIF_REG_ZQ_REFINTERVAL_SHIFT 0 +#define EMIF_REG_ZQ_REFINTERVAL_MASK (0xffff << 0) + +/* TEMP_ALERT_CONFIG */ +#define EMIF_REG_TA_CS1EN_SHIFT 31 +#define EMIF_REG_TA_CS1EN_MASK (1 << 31) +#define EMIF_REG_TA_CS0EN_SHIFT 30 +#define EMIF_REG_TA_CS0EN_MASK (1 << 30) +#define EMIF_REG_TA_SFEXITEN_SHIFT 28 +#define EMIF_REG_TA_SFEXITEN_MASK (1 << 28) +#define EMIF_REG_TA_DEVWDT_SHIFT 26 +#define EMIF_REG_TA_DEVWDT_MASK (0x3 << 26) +#define EMIF_REG_TA_DEVCNT_SHIFT 24 +#define EMIF_REG_TA_DEVCNT_MASK (0x3 << 24) +#define EMIF_REG_TA_REFINTERVAL_SHIFT 0 +#define EMIF_REG_TA_REFINTERVAL_MASK (0x3fffff << 0) + +/* OCP_ERR_LOG */ +#define EMIF_REG_MADDRSPACE_SHIFT 14 +#define EMIF_REG_MADDRSPACE_MASK (0x3 << 14) +#define EMIF_REG_MBURSTSEQ_SHIFT 11 +#define EMIF_REG_MBURSTSEQ_MASK (0x7 << 11) +#define EMIF_REG_MCMD_SHIFT 8 +#define EMIF_REG_MCMD_MASK (0x7 << 8) +#define EMIF_REG_MCONNID_SHIFT 0 +#define EMIF_REG_MCONNID_MASK (0xff << 0) + +/* DDR_PHY_CTRL_1 */ +#define EMIF_REG_DDR_PHY_CTRL_1_SHIFT 4 +#define EMIF_REG_DDR_PHY_CTRL_1_MASK (0xfffffff << 4) +#define EMIF_REG_READ_LATENCY_SHIFT 0 +#define EMIF_REG_READ_LATENCY_MASK (0xf << 0) +#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT 4 +#define EMIF_REG_DLL_SLAVE_DLY_CTRL_MASK (0xFF << 4) +#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT 12 +#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK (0xFFFFF << 12) + +/* DDR_PHY_CTRL_1_SHDW */ +#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_SHIFT 4 +#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_MASK (0xfffffff << 4) +#define EMIF_REG_READ_LATENCY_SHDW_SHIFT 0 +#define EMIF_REG_READ_LATENCY_SHDW_MASK (0xf << 0) +#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT 4 +#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4) +#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12 +#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12) +#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_SHIFT 25 +#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK (1 << 25) +#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_SHIFT 26 +#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK (1 << 26) +#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_SHIFT 27 +#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK (1 << 27) + +/* DDR_PHY_CTRL_2 */ +#define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0 +#define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0) + +/*EMIF_READ_WRITE_LEVELING_CONTROL*/ +#define EMIF_REG_RDWRLVLFULL_START_SHIFT 31 +#define EMIF_REG_RDWRLVLFULL_START_MASK (1 << 31) +#define EMIF_REG_RDWRLVLINC_PRE_SHIFT 24 +#define EMIF_REG_RDWRLVLINC_PRE_MASK (0x7F << 24) +#define EMIF_REG_RDLVLINC_INT_SHIFT 16 +#define EMIF_REG_RDLVLINC_INT_MASK (0xFF << 16) +#define EMIF_REG_RDLVLGATEINC_INT_SHIFT 8 +#define EMIF_REG_RDLVLGATEINC_INT_MASK (0xFF << 8) +#define EMIF_REG_WRLVLINC_INT_SHIFT 0 +#define EMIF_REG_WRLVLINC_INT_MASK (0xFF << 0) + +/*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/ +#define EMIF_REG_RDWRLVL_EN_SHIFT 31 +#define EMIF_REG_RDWRLVL_EN_MASK (1 << 31) +#define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT 24 +#define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK (0x7F << 24) +#define EMIF_REG_RDLVLINC_RMP_INT_SHIFT 16 +#define EMIF_REG_RDLVLINC_RMP_INT_MASK (0xFF << 16) +#define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT 8 +#define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK (0xFF << 8) +#define EMIF_REG_WRLVLINC_RMP_INT_SHIFT 0 +#define EMIF_REG_WRLVLINC_RMP_INT_MASK (0xFF << 0) + +/*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/ +#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0 +#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0) + +/* EMIF_PHY_CTRL_36 */ +#define EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR (1 << 8) + +#define PHY_RDDQS_RATIO_REGS 5 +#define PHY_FIFO_WE_SLAVE_RATIO_REGS 5 +#define PHY_REG_WR_DQ_SLAVE_RATIO_REGS 10 + +/*Leveling Fields */ +#define DDR3_WR_LVL_INT 0x73 +#define DDR3_RD_LVL_INT 0x33 +#define DDR3_RD_LVL_GATE_INT 0x59 +#define RD_RW_LVL_INC_PRE 0x0 +#define DDR3_FULL_LVL (1 << EMIF_REG_RDWRLVL_EN_SHIFT) + +#define DDR3_INC_LVL ((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT) \ + | (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \ + | (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT) \ + | (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT)) + +#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7 +#define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7 +#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7 + +/* DMM */ +#define DMM_BASE 0x4E000040 + +/* Memory Adapter */ +#define MA_BASE 0x482AF040 +#define MA_PRIORITY 0x482A2000 +#define MA_HIMEM_INTERLEAVE_UN_SHIFT 8 +#define MA_HIMEM_INTERLEAVE_UN_MASK (1 << 8) + +/* DMM_LISA_MAP */ +#define EMIF_SYS_ADDR_SHIFT 24 +#define EMIF_SYS_ADDR_MASK (0xff << 24) +#define EMIF_SYS_SIZE_SHIFT 20 +#define EMIF_SYS_SIZE_MASK (0x7 << 20) +#define EMIF_SDRC_INTL_SHIFT 18 +#define EMIF_SDRC_INTL_MASK (0x3 << 18) +#define EMIF_SDRC_ADDRSPC_SHIFT 16 +#define EMIF_SDRC_ADDRSPC_MASK (0x3 << 16) +#define EMIF_SDRC_MAP_SHIFT 8 +#define EMIF_SDRC_MAP_MASK (0x3 << 8) +#define EMIF_SDRC_ADDR_SHIFT 0 +#define EMIF_SDRC_ADDR_MASK (0xff << 0) + +/* DMM_LISA_MAP fields */ +#define DMM_SDRC_MAP_UNMAPPED 0 +#define DMM_SDRC_MAP_EMIF1_ONLY 1 +#define DMM_SDRC_MAP_EMIF2_ONLY 2 +#define DMM_SDRC_MAP_EMIF1_AND_EMIF2 3 + +#define DMM_SDRC_INTL_NONE 0 +#define DMM_SDRC_INTL_128B 1 +#define DMM_SDRC_INTL_256B 2 +#define DMM_SDRC_INTL_512 3 + +#define DMM_SDRC_ADDR_SPC_SDRAM 0 +#define DMM_SDRC_ADDR_SPC_NVM 1 +#define DMM_SDRC_ADDR_SPC_INVALID 2 + +#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL (\ + (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\ + (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\ + (DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\ + (CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT)) + +#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\ + (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\ + (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\ + (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)) + +#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL (\ + (DMM_SDRC_MAP_EMIF2_ONLY << EMIF_SDRC_MAP_SHIFT)|\ + (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\ + (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)) + +/* Trap for invalid TILER PAT entries */ +#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\ + (0 << EMIF_SDRC_ADDR_SHIFT) |\ + (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\ + (DMM_SDRC_ADDR_SPC_INVALID << EMIF_SDRC_ADDRSPC_SHIFT)|\ + (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)|\ + (0xFF << EMIF_SYS_ADDR_SHIFT)) + +#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5 + +/* EMIF ECC CTRL reg */ +#define EMIF_ECC_CTRL_REG_ECC_EN_SHIFT 31 +#define EMIF_ECC_CTRL_REG_ECC_EN_MASK (1 << 31) +#define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_SHIFT 30 +#define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK (1 << 30) +#define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_SHIFT 29 +#define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK (1 << 29) +#define EMIF_ECC_REG_RMW_EN_SHIFT 28 +#define EMIF_ECC_REG_RMW_EN_MASK (1 << 28) +#define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_SHIFT 1 +#define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK (1 << 1) +#define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_SHIFT 0 +#define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK (1 << 0) + +/* EMIF ECC ADDRESS RANGE */ +#define EMIF_ECC_REG_ECC_END_ADDR_SHIFT 16 +#define EMIF_ECC_REG_ECC_END_ADDR_MASK (0xffff << 16) +#define EMIF_ECC_REG_ECC_START_ADDR_SHIFT 0 +#define EMIF_ECC_REG_ECC_START_ADDR_MASK (0xffff << 0) + +/* EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS */ +#define EMIF_INT_ONEBIT_ECC_ERR_SYS_SHIFT 5 +#define EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK (1 << 5) +#define EMIF_INT_TWOBIT_ECC_ERR_SYS_SHIFT 4 +#define EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK (1 << 4) +#define EMIF_INT_WR_ECC_ERR_SYS_SHIFT 3 +#define EMIF_INT_WR_ECC_ERR_SYS_MASK (1 << 3) + +/* Reg mapping structure */ +struct emif_reg_struct { + u32 emif_mod_id_rev; + u32 emif_status; + u32 emif_sdram_config; + u32 emif_lpddr2_nvm_config; + u32 emif_sdram_ref_ctrl; + u32 emif_sdram_ref_ctrl_shdw; + u32 emif_sdram_tim_1; + u32 emif_sdram_tim_1_shdw; + u32 emif_sdram_tim_2; + u32 emif_sdram_tim_2_shdw; + u32 emif_sdram_tim_3; + u32 emif_sdram_tim_3_shdw; + u32 emif_lpddr2_nvm_tim; + u32 emif_lpddr2_nvm_tim_shdw; + u32 emif_pwr_mgmt_ctrl; + u32 emif_pwr_mgmt_ctrl_shdw; + u32 emif_lpddr2_mode_reg_data; + u32 padding1[1]; + u32 emif_lpddr2_mode_reg_data_es2; + u32 padding11[1]; + u32 emif_lpddr2_mode_reg_cfg; + u32 emif_l3_config; + u32 emif_l3_cfg_val_1; + u32 emif_l3_cfg_val_2; + u32 emif_iodft_tlgc; + u32 padding2[7]; + u32 emif_perf_cnt_1; + u32 emif_perf_cnt_2; + u32 emif_perf_cnt_cfg; + u32 emif_perf_cnt_sel; + u32 emif_perf_cnt_tim; + u32 padding3; + u32 emif_read_idlectrl; + u32 emif_read_idlectrl_shdw; + u32 padding4; + u32 emif_irqstatus_raw_sys; + u32 emif_irqstatus_raw_ll; + u32 emif_irqstatus_sys; + u32 emif_irqstatus_ll; + u32 emif_irqenable_set_sys; + u32 emif_irqenable_set_ll; + u32 emif_irqenable_clr_sys; + u32 emif_irqenable_clr_ll; + u32 padding5; + u32 emif_zq_config; + u32 emif_temp_alert_config; + u32 emif_l3_err_log; + u32 emif_rd_wr_lvl_rmp_win; + u32 emif_rd_wr_lvl_rmp_ctl; + u32 emif_rd_wr_lvl_ctl; + u32 padding6[1]; + u32 emif_ddr_phy_ctrl_1; + u32 emif_ddr_phy_ctrl_1_shdw; + u32 emif_ddr_phy_ctrl_2; + u32 padding7[4]; + u32 emif_prio_class_serv_map; + u32 emif_connect_id_serv_1_map; + u32 emif_connect_id_serv_2_map; + u32 padding8; + u32 emif_ecc_ctrl_reg; + u32 emif_ecc_address_range_1; + u32 emif_ecc_address_range_2; + u32 padding8_1; + u32 emif_rd_wr_exec_thresh; + u32 emif_cos_config; +#if defined(CONFIG_DRA7XX) || defined(CONFIG_ARCH_KEYSTONE) + u32 padding9[2]; + u32 emif_1b_ecc_err_cnt; + u32 emif_1b_ecc_err_thrush; + u32 emif_1b_ecc_err_dist_1; + u32 emif_1b_ecc_err_addr_log; + u32 emif_2b_ecc_err_addr_log; + u32 emif_ddr_phy_status[28]; + u32 padding10[19]; +#else + u32 padding9[6]; + u32 emif_ddr_phy_status[28]; + u32 padding10[20]; +#endif + u32 emif_ddr_ext_phy_ctrl_1; + u32 emif_ddr_ext_phy_ctrl_1_shdw; + u32 emif_ddr_ext_phy_ctrl_2; + u32 emif_ddr_ext_phy_ctrl_2_shdw; + u32 emif_ddr_ext_phy_ctrl_3; + u32 emif_ddr_ext_phy_ctrl_3_shdw; + u32 emif_ddr_ext_phy_ctrl_4; + u32 emif_ddr_ext_phy_ctrl_4_shdw; + u32 emif_ddr_ext_phy_ctrl_5; + u32 emif_ddr_ext_phy_ctrl_5_shdw; + u32 emif_ddr_ext_phy_ctrl_6; + u32 emif_ddr_ext_phy_ctrl_6_shdw; + u32 emif_ddr_ext_phy_ctrl_7; + u32 emif_ddr_ext_phy_ctrl_7_shdw; + u32 emif_ddr_ext_phy_ctrl_8; + u32 emif_ddr_ext_phy_ctrl_8_shdw; + u32 emif_ddr_ext_phy_ctrl_9; + u32 emif_ddr_ext_phy_ctrl_9_shdw; + u32 emif_ddr_ext_phy_ctrl_10; + u32 emif_ddr_ext_phy_ctrl_10_shdw; + u32 emif_ddr_ext_phy_ctrl_11; + u32 emif_ddr_ext_phy_ctrl_11_shdw; + u32 emif_ddr_ext_phy_ctrl_12; + u32 emif_ddr_ext_phy_ctrl_12_shdw; + u32 emif_ddr_ext_phy_ctrl_13; + u32 emif_ddr_ext_phy_ctrl_13_shdw; + u32 emif_ddr_ext_phy_ctrl_14; + u32 emif_ddr_ext_phy_ctrl_14_shdw; + u32 emif_ddr_ext_phy_ctrl_15; + u32 emif_ddr_ext_phy_ctrl_15_shdw; + u32 emif_ddr_ext_phy_ctrl_16; + u32 emif_ddr_ext_phy_ctrl_16_shdw; + u32 emif_ddr_ext_phy_ctrl_17; + u32 emif_ddr_ext_phy_ctrl_17_shdw; + u32 emif_ddr_ext_phy_ctrl_18; + u32 emif_ddr_ext_phy_ctrl_18_shdw; + u32 emif_ddr_ext_phy_ctrl_19; + u32 emif_ddr_ext_phy_ctrl_19_shdw; + u32 emif_ddr_ext_phy_ctrl_20; + u32 emif_ddr_ext_phy_ctrl_20_shdw; + u32 emif_ddr_ext_phy_ctrl_21; + u32 emif_ddr_ext_phy_ctrl_21_shdw; + u32 emif_ddr_ext_phy_ctrl_22; + u32 emif_ddr_ext_phy_ctrl_22_shdw; + u32 emif_ddr_ext_phy_ctrl_23; + u32 emif_ddr_ext_phy_ctrl_23_shdw; + u32 emif_ddr_ext_phy_ctrl_24; + u32 emif_ddr_ext_phy_ctrl_24_shdw; + u32 emif_ddr_ext_phy_ctrl_25; + u32 emif_ddr_ext_phy_ctrl_25_shdw; + u32 emif_ddr_ext_phy_ctrl_26; + u32 emif_ddr_ext_phy_ctrl_26_shdw; + u32 emif_ddr_ext_phy_ctrl_27; + u32 emif_ddr_ext_phy_ctrl_27_shdw; + u32 emif_ddr_ext_phy_ctrl_28; + u32 emif_ddr_ext_phy_ctrl_28_shdw; + u32 emif_ddr_ext_phy_ctrl_29; + u32 emif_ddr_ext_phy_ctrl_29_shdw; + u32 emif_ddr_ext_phy_ctrl_30; + u32 emif_ddr_ext_phy_ctrl_30_shdw; + u32 emif_ddr_ext_phy_ctrl_31; + u32 emif_ddr_ext_phy_ctrl_31_shdw; + u32 emif_ddr_ext_phy_ctrl_32; + u32 emif_ddr_ext_phy_ctrl_32_shdw; + u32 emif_ddr_ext_phy_ctrl_33; + u32 emif_ddr_ext_phy_ctrl_33_shdw; + u32 emif_ddr_ext_phy_ctrl_34; + u32 emif_ddr_ext_phy_ctrl_34_shdw; + u32 emif_ddr_ext_phy_ctrl_35; + u32 emif_ddr_ext_phy_ctrl_35_shdw; + union { + u32 emif_ddr_ext_phy_ctrl_36; + u32 emif_ddr_fifo_misaligned_clear_1; + }; + union { + u32 emif_ddr_ext_phy_ctrl_36_shdw; + u32 emif_ddr_fifo_misaligned_clear_2; + }; +}; + +struct dmm_lisa_map_regs { + u32 dmm_lisa_map_0; + u32 dmm_lisa_map_1; + u32 dmm_lisa_map_2; + u32 dmm_lisa_map_3; + u8 is_ma_present; +}; + +#define CS0 0 +#define CS1 1 +/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/ +#define MAX_LPDDR2_FREQ 400000000 /* 400 MHz */ + +/* + * The period of DDR clk is represented as numerator and denominator for + * better accuracy in integer based calculations. However, if the numerator + * and denominator are very huge there may be chances of overflow in + * calculations. So, as a trade-off keep denominator(and consequently + * numerator) within a limit sacrificing some accuracy - but not much + * If denominator and numerator are already small (such as at 400 MHz) + * no adjustment is needed + */ +#define EMIF_PERIOD_DEN_LIMIT 1000 +/* + * Maximum number of different frequencies supported by EMIF driver + * Determines the number of entries in the pointer array for register + * cache + */ +#define EMIF_MAX_NUM_FREQUENCIES 6 +/* + * Indices into the Addressing Table array. + * One entry each for all the different types of devices with different + * addressing schemes + */ +#define ADDR_TABLE_INDEX64M 0 +#define ADDR_TABLE_INDEX128M 1 +#define ADDR_TABLE_INDEX256M 2 +#define ADDR_TABLE_INDEX512M 3 +#define ADDR_TABLE_INDEX1GS4 4 +#define ADDR_TABLE_INDEX2GS4 5 +#define ADDR_TABLE_INDEX4G 6 +#define ADDR_TABLE_INDEX8G 7 +#define ADDR_TABLE_INDEX1GS2 8 +#define ADDR_TABLE_INDEX2GS2 9 +#define ADDR_TABLE_INDEXMAX 10 + +/* Number of Row bits */ +#define ROW_9 0 +#define ROW_10 1 +#define ROW_11 2 +#define ROW_12 3 +#define ROW_13 4 +#define ROW_14 5 +#define ROW_15 6 +#define ROW_16 7 + +/* Number of Column bits */ +#define COL_8 0 +#define COL_9 1 +#define COL_10 2 +#define COL_11 3 +#define COL_7 4 /*Not supported by OMAP included for completeness */ + +/* Number of Banks*/ +#define BANKS1 0 +#define BANKS2 1 +#define BANKS4 2 +#define BANKS8 3 + +/* Refresh rate in micro seconds x 10 */ +#define T_REFI_15_6 156 +#define T_REFI_7_8 78 +#define T_REFI_3_9 39 + +#define EBANK_CS1_DIS 0 +#define EBANK_CS1_EN 1 + +/* Read Latency used by the device at reset */ +#define RL_BOOT 3 +/* Read Latency for the highest frequency you want to use */ +#ifdef CONFIG_OMAP54XX +#define RL_FINAL 8 +#else +#define RL_FINAL 6 +#endif + + +/* Interleaving policies at EMIF level- between banks and Chip Selects */ +#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0 +#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3 + +/* + * Interleaving policy to be used + * Currently set to MAX interleaving for better performance + */ +#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING + +/* State of the core voltage: + * This is important for some parameters such as read idle control and + * ZQ calibration timings. Timings are much stricter when voltage ramp + * is happening compared to when the voltage is stable. + * We need to calculate two sets of values for these parameters and use + * them accordingly + */ +#define LPDDR2_VOLTAGE_STABLE 0 +#define LPDDR2_VOLTAGE_RAMPING 1 + +/* Length of the forced read idle period in terms of cycles */ +#define EMIF_REG_READ_IDLE_LEN_VAL 5 + +/* Interval between forced 'read idles' */ +/* To be used when voltage is changed for DPS/DVFS - 1us */ +#define READ_IDLE_INTERVAL_DVFS (1*1000) +/* + * To be used when voltage is not scaled except by Smart Reflex + * 50us - or maximum value will do + */ +#define READ_IDLE_INTERVAL_NORMAL (50*1000) + + +/* + * Unless voltage is changing due to DVFS one ZQCS command every 50ms should + * be enough. This shoule be enough also in the case when voltage is changing + * due to smart-reflex. + */ +#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US (50*1000) +/* + * If voltage is changing due to DVFS ZQCS should be performed more + * often(every 50us) + */ +#define EMIF_ZQCS_INTERVAL_DVFS_IN_US 50 + +/* The interval between ZQCL commands as a multiple of ZQCS interval */ +#define REG_ZQ_ZQCL_MULT 4 +/* The interval between ZQINIT commands as a multiple of ZQCL interval */ +#define REG_ZQ_ZQINIT_MULT 3 +/* Enable ZQ Calibration on exiting Self-refresh */ +#define REG_ZQ_SFEXITEN_ENABLE 1 +/* + * ZQ Calibration simultaneously on both chip-selects: + * Needs one calibration resistor per CS + * None of the boards that we know of have this capability + * So disabled by default + */ +#define REG_ZQ_DUALCALEN_DISABLE 0 +/* + * Enable ZQ Calibration by default on CS0. If we are asked to program + * the EMIF there will be something connected to CS0 for sure + */ +#define REG_ZQ_CS0EN_ENABLE 1 + +/* EMIF_PWR_MGMT_CTRL register */ +/* Low power modes */ +#define LP_MODE_DISABLE 0 +#define LP_MODE_CLOCK_STOP 1 +#define LP_MODE_SELF_REFRESH 2 +#define LP_MODE_PWR_DN 3 + +/* REG_DPD_EN */ +#define DPD_DISABLE 0 +#define DPD_ENABLE 1 + +/* Maximum delay before Low Power Modes */ +#define REG_CS_TIM 0x0 +#define REG_SR_TIM 0xF +#define REG_PD_TIM 0xF + + +/* EMIF_PWR_MGMT_CTRL register */ +#define EMIF_PWR_MGMT_CTRL (\ + ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\ + ((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\ + ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\ + ((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)\ + & EMIF_REG_LP_MODE_MASK) |\ + ((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\ + & EMIF_REG_DPD_EN_MASK))\ + +#define EMIF_PWR_MGMT_CTRL_SHDW (\ + ((REG_CS_TIM << EMIF_REG_CS_TIM_SHDW_SHIFT)\ + & EMIF_REG_CS_TIM_SHDW_MASK) |\ + ((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\ + & EMIF_REG_SR_TIM_SHDW_MASK) |\ + ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\ + & EMIF_REG_PD_TIM_SHDW_MASK)) + +/* EMIF_L3_CONFIG register value */ +#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF +#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000 +#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0 0x0A500000 + +/* + * Value of bits 12:31 of DDR_PHY_CTRL_1 register: + * All these fields have magic values dependent on frequency and + * determined by PHY and DLL integration with EMIF. Setting the magic + * values suggested by hw team. + */ +#define EMIF_DDR_PHY_CTRL_1_BASE_VAL 0x049FF +#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ 0x41 +#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ 0x80 +#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS 0xFF + +/* +* MR1 value: +* Burst length : 8 +* Burst type : sequential +* Wrap : enabled +* nWR : 3(default). EMIF does not do pre-charge. +* : So nWR is don't care +*/ +#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3 0x23 +#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8 0xc3 + +/* MR2 */ +#define MR2_RL3_WL1 1 +#define MR2_RL4_WL2 2 +#define MR2_RL5_WL2 3 +#define MR2_RL6_WL3 4 + +/* MR10: ZQ calibration codes */ +#define MR10_ZQ_ZQCS 0x56 +#define MR10_ZQ_ZQCL 0xAB +#define MR10_ZQ_ZQINIT 0xFF +#define MR10_ZQ_ZQRESET 0xC3 + +/* TEMP_ALERT_CONFIG */ +#define TEMP_ALERT_POLL_INTERVAL_MS 360 /* for temp gradient - 5 C/s */ +#define TEMP_ALERT_CONFIG_DEVCT_1 0 +#define TEMP_ALERT_CONFIG_DEVWDT_32 2 + +/* MR16 value: refresh full array(no partial array self refresh) */ +#define MR16_REF_FULL_ARRAY 0 + +/* + * Maximum number of entries we keep in our array of timing tables + * We need not keep all the speed bins supported by the device + * We need to keep timing tables for only the speed bins that we + * are interested in + */ +#define MAX_NUM_SPEEDBINS 4 + +/* LPDDR2 Densities */ +#define LPDDR2_DENSITY_64Mb 0 +#define LPDDR2_DENSITY_128Mb 1 +#define LPDDR2_DENSITY_256Mb 2 +#define LPDDR2_DENSITY_512Mb 3 +#define LPDDR2_DENSITY_1Gb 4 +#define LPDDR2_DENSITY_2Gb 5 +#define LPDDR2_DENSITY_4Gb 6 +#define LPDDR2_DENSITY_8Gb 7 +#define LPDDR2_DENSITY_16Gb 8 +#define LPDDR2_DENSITY_32Gb 9 + +/* LPDDR2 type */ +#define LPDDR2_TYPE_S4 0 +#define LPDDR2_TYPE_S2 1 +#define LPDDR2_TYPE_NVM 2 + +/* LPDDR2 IO width */ +#define LPDDR2_IO_WIDTH_32 0 +#define LPDDR2_IO_WIDTH_16 1 +#define LPDDR2_IO_WIDTH_8 2 + +/* Mode register numbers */ +#define LPDDR2_MR0 0 +#define LPDDR2_MR1 1 +#define LPDDR2_MR2 2 +#define LPDDR2_MR3 3 +#define LPDDR2_MR4 4 +#define LPDDR2_MR5 5 +#define LPDDR2_MR6 6 +#define LPDDR2_MR7 7 +#define LPDDR2_MR8 8 +#define LPDDR2_MR9 9 +#define LPDDR2_MR10 10 +#define LPDDR2_MR11 11 +#define LPDDR2_MR16 16 +#define LPDDR2_MR17 17 +#define LPDDR2_MR18 18 + +/* MR0 */ +#define LPDDR2_MR0_DAI_SHIFT 0 +#define LPDDR2_MR0_DAI_MASK 1 +#define LPDDR2_MR0_DI_SHIFT 1 +#define LPDDR2_MR0_DI_MASK (1 << 1) +#define LPDDR2_MR0_DNVI_SHIFT 2 +#define LPDDR2_MR0_DNVI_MASK (1 << 2) + +/* MR4 */ +#define MR4_SDRAM_REF_RATE_SHIFT 0 +#define MR4_SDRAM_REF_RATE_MASK 7 +#define MR4_TUF_SHIFT 7 +#define MR4_TUF_MASK (1 << 7) + +/* MR4 SDRAM Refresh Rate field values */ +#define SDRAM_TEMP_LESS_LOW_SHUTDOWN 0x0 +#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS 0x1 +#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS 0x2 +#define SDRAM_TEMP_NOMINAL 0x3 +#define SDRAM_TEMP_RESERVED_4 0x4 +#define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5 +#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6 +#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7 + +#define LPDDR2_MANUFACTURER_SAMSUNG 1 +#define LPDDR2_MANUFACTURER_QIMONDA 2 +#define LPDDR2_MANUFACTURER_ELPIDA 3 +#define LPDDR2_MANUFACTURER_ETRON 4 +#define LPDDR2_MANUFACTURER_NANYA 5 +#define LPDDR2_MANUFACTURER_HYNIX 6 +#define LPDDR2_MANUFACTURER_MOSEL 7 +#define LPDDR2_MANUFACTURER_WINBOND 8 +#define LPDDR2_MANUFACTURER_ESMT 9 +#define LPDDR2_MANUFACTURER_SPANSION 11 +#define LPDDR2_MANUFACTURER_SST 12 +#define LPDDR2_MANUFACTURER_ZMOS 13 +#define LPDDR2_MANUFACTURER_INTEL 14 +#define LPDDR2_MANUFACTURER_NUMONYX 254 +#define LPDDR2_MANUFACTURER_MICRON 255 + +/* MR8 register fields */ +#define MR8_TYPE_SHIFT 0x0 +#define MR8_TYPE_MASK 0x3 +#define MR8_DENSITY_SHIFT 0x2 +#define MR8_DENSITY_MASK (0xF << 0x2) +#define MR8_IO_WIDTH_SHIFT 0x6 +#define MR8_IO_WIDTH_MASK (0x3 << 0x6) + +/* SDRAM TYPE */ +#define EMIF_SDRAM_TYPE_DDR2 0x2 +#define EMIF_SDRAM_TYPE_DDR3 0x3 +#define EMIF_SDRAM_TYPE_LPDDR2 0x4 + +struct lpddr2_addressing { + u8 num_banks; + u8 t_REFI_us_x10; + u8 row_sz[2]; /* One entry each for x32 and x16 */ + u8 col_sz[2]; /* One entry each for x32 and x16 */ +}; + +/* Structure for timings from the DDR datasheet */ +struct lpddr2_ac_timings { + u32 max_freq; + u8 RL; + u8 tRPab; + u8 tRCD; + u8 tWR; + u8 tRASmin; + u8 tRRD; + u8 tWTRx2; + u8 tXSR; + u8 tXPx2; + u8 tRFCab; + u8 tRTPx2; + u8 tCKE; + u8 tCKESR; + u8 tZQCS; + u32 tZQCL; + u32 tZQINIT; + u8 tDQSCKMAXx2; + u8 tRASmax; + u8 tFAW; + +}; + +/* + * Min tCK values for some of the parameters: + * If the calculated clock cycles for the respective parameter is + * less than the corresponding min tCK value, we need to set the min + * tCK value. This may happen at lower frequencies. + */ +struct lpddr2_min_tck { + u32 tRL; + u32 tRP_AB; + u32 tRCD; + u32 tWR; + u32 tRAS_MIN; + u32 tRRD; + u32 tWTR; + u32 tXP; + u32 tRTP; + u8 tCKE; + u32 tCKESR; + u32 tFAW; +}; + +struct lpddr2_device_details { + u8 type; + u8 density; + u8 io_width; + u8 manufacturer; +}; + +struct lpddr2_device_timings { + const struct lpddr2_ac_timings **ac_timings; + const struct lpddr2_min_tck *min_tck; +}; + +/* Details of the devices connected to each chip-select of an EMIF instance */ +struct emif_device_details { + const struct lpddr2_device_details *cs0_device_details; + const struct lpddr2_device_details *cs1_device_details; + const struct lpddr2_device_timings *cs0_device_timings; + const struct lpddr2_device_timings *cs1_device_timings; +}; + +/* + * Structure containing shadow of important registers in EMIF + * The calculation function fills in this structure to be later used for + * initialization and DVFS + */ +struct emif_regs { + u32 freq; + u32 sdram_config_init; + u32 sdram_config; + u32 sdram_config2; + u32 ref_ctrl; + u32 ref_ctrl_final; + u32 sdram_tim1; + u32 sdram_tim2; + u32 sdram_tim3; + u32 ocp_config; + u32 read_idle_ctrl; + u32 zq_config; + u32 temp_alert_config; + u32 emif_ddr_phy_ctlr_1_init; + u32 emif_ddr_phy_ctlr_1; + u32 emif_ddr_ext_phy_ctrl_1; + u32 emif_ddr_ext_phy_ctrl_2; + u32 emif_ddr_ext_phy_ctrl_3; + u32 emif_ddr_ext_phy_ctrl_4; + u32 emif_ddr_ext_phy_ctrl_5; + u32 emif_rd_wr_lvl_rmp_win; + u32 emif_rd_wr_lvl_rmp_ctl; + u32 emif_rd_wr_lvl_ctl; + u32 emif_rd_wr_exec_thresh; + u32 emif_prio_class_serv_map; + u32 emif_connect_id_serv_1_map; + u32 emif_connect_id_serv_2_map; + u32 emif_cos_config; + u32 emif_ecc_ctrl_reg; + u32 emif_ecc_address_range_1; + u32 emif_ecc_address_range_2; +}; + +struct lpddr2_mr_regs { + s8 mr1; + s8 mr2; + s8 mr3; + s8 mr10; + s8 mr16; +}; + +struct read_write_regs { + u32 read_reg; + u32 write_reg; +}; + +static inline u32 get_emif_rev(u32 base) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK) + >> EMIF_REG_MAJOR_REVISION_SHIFT; +} + +/* + * Get SDRAM type connected to EMIF. + * Assuming similar SDRAM parts are connected to both EMIF's + * which is typically the case. So it is sufficient to get + * SDRAM type from EMIF1. + */ +static inline u32 emif_sdram_type(u32 sdram_config) +{ + return (sdram_config & EMIF_REG_SDRAM_TYPE_MASK) + >> EMIF_REG_SDRAM_TYPE_SHIFT; +} + +/* assert macros */ +#if defined(DEBUG) +#define emif_assert(c) ({ if (!(c)) for (;;); }) +#else +#define emif_assert(c) ({ if (0) hang(); }) +#endif + +#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs); +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs); +#else +struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, + struct lpddr2_device_details *lpddr2_dev_details); +void emif_get_device_timings(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings); +#endif + +void do_ext_phy_settings(u32 base, const struct emif_regs *regs); +void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs); + +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +extern u32 *const T_num; +extern u32 *const T_den; +#endif + +void config_data_eye_leveling_samples(u32 emif_base); +const struct read_write_regs *get_bug_regs(u32 *iterations); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/fsl_secure_boot.h b/roms/u-boot/arch/arm/include/asm/fsl_secure_boot.h new file mode 100644 index 000000000..b0c7599e4 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/fsl_secure_boot.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#ifndef __FSL_SECURE_BOOT_H +#define __FSL_SECURE_BOOT_H + +#ifdef CONFIG_CHAIN_OF_TRUST +#define CONFIG_FSL_SEC_MON + +#ifdef CONFIG_SPL_BUILD +/* + * Define the key hash for U-Boot here if public/private key pair used to + * sign U-boot are different from the SRK hash put in the fuse + * Example of defining KEY_HASH is + * #define CONFIG_SPL_UBOOT_KEY_HASH \ + * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" + * else leave it defined as NULL + */ + +#define CONFIG_SPL_UBOOT_KEY_HASH NULL +#endif /* ifdef CONFIG_SPL_BUILD */ + +#define CONFIG_KEY_REVOCATION + +#if defined(CONFIG_FSL_LAYERSCAPE) +/* + * For fsl layerscape based platforms, ESBC image Address in Header + * is 64 bit. + */ +#define CONFIG_ESBC_ADDR_64BIT +#endif + +#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_SYS_RAMBOOT +/* The key used for verification of next level images + * is picked up from an Extension Table which has + * been verified by the ISBC (Internal Secure boot Code) + * in boot ROM of the SoC. + * The feature is only applicable in case of NOR boot and is + * not applicable in case of RAMBOOT (NAND, SD, SPI). + * For LS, this feature is available for all device if IE Table + * is copied to XIP memory + * Also, for LS, ISBC doesn't verify this table. + */ +#define CONFIG_FSL_ISBC_KEY_EXT + +#endif + +#ifdef CONFIG_ARCH_LS2080A +#define CONFIG_EXTRA_ENV \ + "setenv fdt_high 0xa0000000;" \ + "setenv initrd_high 0xcfffffff;" \ + "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" +#else +#define CONFIG_EXTRA_ENV \ + "setenv fdt_high 0xffffffff;" \ + "setenv initrd_high 0xffffffff;" \ + "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" +#endif + +/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from + * Non-XIP Memory (Nand/SD)*/ +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \ + defined(CONFIG_SD_BOOT) || defined(CONFIG_NAND_BOOT) +#define CONFIG_BOOTSCRIPT_COPY_RAM +#endif +/* The address needs to be modified according to NOR, NAND, SD and + * DDR memory map + */ +#ifdef CONFIG_FSL_LSCH3 +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_BS_ADDR_DEVICE 0x20600000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x20640000 +#else /* NOR BOOT */ +#define CONFIG_BS_ADDR_DEVICE 0x580600000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x580640000 +#endif /*ifdef CONFIG_QSPI_BOOT */ +#define CONFIG_BS_SIZE 0x00001000 +#define CONFIG_BS_HDR_SIZE 0x00004000 +#define CONFIG_BS_ADDR_RAM 0xa0600000 +#define CONFIG_BS_HDR_ADDR_RAM 0xa0640000 +#else +#ifdef CONFIG_SD_BOOT +/* For SD boot address and size are assigned in terms of sector + * offset and no. of sectors respectively. + */ +#define CONFIG_BS_ADDR_DEVICE 0x00003000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x00003200 +#define CONFIG_BS_SIZE 0x00000008 +#define CONFIG_BS_HDR_SIZE 0x00000010 +#elif defined(CONFIG_NAND_BOOT) +#define CONFIG_BS_ADDR_DEVICE 0x00600000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x00640000 +#define CONFIG_BS_SIZE 0x00001000 +#define CONFIG_BS_HDR_SIZE 0x00002000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_BS_ADDR_DEVICE 0x40600000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x40640000 +#define CONFIG_BS_SIZE 0x00001000 +#define CONFIG_BS_HDR_SIZE 0x00002000 +#else /* Default NOR Boot */ +#define CONFIG_BS_ADDR_DEVICE 0x60600000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x60640000 +#define CONFIG_BS_SIZE 0x00001000 +#define CONFIG_BS_HDR_SIZE 0x00002000 +#endif +#define CONFIG_BS_ADDR_RAM 0x81000000 +#define CONFIG_BS_HDR_ADDR_RAM 0x81020000 +#endif + +#ifdef CONFIG_BOOTSCRIPT_COPY_RAM +#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM +#else +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE +/* BOOTSCRIPT_ADDR is not required */ +#endif + +#ifdef CONFIG_FSL_LS_PPA +/* Define the key hash here if SRK used for signing PPA image is + * different from SRK hash put in SFP used for U-Boot. + * Example + * #define PPA_KEY_HASH \ + * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" + */ +#define PPA_KEY_HASH NULL +#endif /* ifdef CONFIG_FSL_LS_PPA */ + +#include +#endif /* #ifndef CONFIG_SPL_BUILD */ +#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ +#endif diff --git a/roms/u-boot/arch/arm/include/asm/gic-v3.h b/roms/u-boot/arch/arm/include/asm/gic-v3.h new file mode 100644 index 000000000..35efec78c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/gic-v3.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Broadcom. + */ + +#ifndef __GIC_V3_H__ +#define __GIC_V3_H__ + +#ifndef __ASSEMBLY__ +#include +#endif + +#define GICR_CTLR_ENABLE_LPIS BIT(0) +#define GICR_CTLR_RWP BIT(3) + +#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff) + +#define GICR_WAKER_PROCESSORSLEEP BIT(1) +#define GICR_WAKER_CHILDRENASLEEP BIT(2) + +#define GIC_BASER_CACHE_NCNB 0ULL +#define GIC_BASER_CACHE_SAMEASINNER 0ULL +#define GIC_BASER_CACHE_NC 1ULL +#define GIC_BASER_CACHE_RAWT 2ULL +#define GIC_BASER_CACHE_RAWB 3ULL +#define GIC_BASER_CACHE_WAWT 4ULL +#define GIC_BASER_CACHE_WAWB 5ULL +#define GIC_BASER_CACHE_RAWAWT 6ULL +#define GIC_BASER_CACHE_RAWAWB 7ULL +#define GIC_BASER_CACHE_MASK 7ULL +#define GIC_BASER_NONSHAREABLE 0ULL +#define GIC_BASER_INNERSHAREABLE 1ULL +#define GIC_BASER_OUTERSHAREABLE 2ULL +#define GIC_BASER_SHAREABILITY_MASK 3ULL + +#define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \ + (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT) + +#define GIC_BASER_SHAREABILITY(reg, type) \ + (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT) + +/* encode a size field of width @w containing @n - 1 units */ +#define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) &\ + GENMASK_ULL(((w) - 1), 0)) + +#define GICR_PROPBASER_SHAREABILITY_SHIFT (10) +#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7) +#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56) +#define GICR_PROPBASER_SHAREABILITY_MASK \ + GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK) +#define GICR_PROPBASER_INNER_CACHEABILITY_MASK \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK) +#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK) +#define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK + +#define GICR_PROPBASER_INNERSHAREABLE \ + GIC_BASER_SHAREABILITY(GICR_PROPBASER, INNERSHAREABLE) + +#define GICR_PROPBASER_NCNB \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, NCNB) +#define GICR_PROPBASER_NC \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, NC) +#define GICR_PROPBASER_RAWT \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWT) +#define GICR_PROPBASER_RAWB \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWB) +#define GICR_PROPBASER_WAWT \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WAWT) +#define GICR_PROPBASER_WAWB \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WAWB) +#define GICR_PROPBASER_RAWAWT \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWAWT) +#define GICR_PROPBASER_RAWAWB \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWAWB) + +#define GICR_PROPBASER_IDBITS_MASK (0x1f) +#define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12)) +#define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16)) + +#define GICR_PENDBASER_SHAREABILITY_SHIFT (10) +#define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7) +#define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56) +#define GICR_PENDBASER_SHAREABILITY_MASK \ + GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK) +#define GICR_PENDBASER_INNER_CACHEABILITY_MASK \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK) +#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK) +#define GICR_PENDBASER_CACHEABILITY_MASK \ + GICR_PENDBASER_INNER_CACHEABILITY_MASK + +#define GICR_PENDBASER_INNERSHAREABLE \ + GIC_BASER_SHAREABILITY(GICR_PENDBASER, INNERSHAREABLE) + +#define GICR_PENDBASER_NCNB \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, NCNB) +#define GICR_PENDBASER_NC \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, NC) +#define GICR_PENDBASER_RAWT \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RAWT) +#define GICR_PENDBASER_RAWB \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RAWB) +#define GICR_PENDBASER_WAWT \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WAWT) +#define GICR_PENDBASER_WAWB \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WAWB) +#define GICR_PENDBASER_RAWAWT \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RAWAWT) +#define GICR_PENDBASER_RAWAWB \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RAWAWB) + +#define GICR_PENDBASER_PTZ BIT_ULL(62) + +#define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */ + +#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1) +#define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1) +#define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32) + +/* Message based interrupts support */ +#define GICD_TYPER_MBIS BIT(16) +/* LPI support */ +#define GICD_TYPER_LPIS BIT(17) +#define GICD_TYPER_RSS BIT(26) + +#define GIC_REDISTRIBUTOR_OFFSET 0x20000 + +#ifdef CONFIG_GIC_V3_ITS +int gic_lpi_tables_init(void); +#else +int gic_lpi_tables_init(void) +{ + return 0; +} +#endif /* CONFIG_GIC_V3_ITS */ + +#endif /* __GIC_V3_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/gic.h b/roms/u-boot/arch/arm/include/asm/gic.h new file mode 100644 index 000000000..bd3a80cdf --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/gic.h @@ -0,0 +1,110 @@ +#ifndef __GIC_H__ +#define __GIC_H__ + +/* Register offsets for the ARM generic interrupt controller (GIC) */ + +#define GIC_DIST_OFFSET 0x1000 +#define GIC_CPU_OFFSET_A9 0x0100 +#define GIC_CPU_OFFSET_A15 0x2000 + +/* Distributor Registers */ +#define GICD_CTLR 0x0000 +#define GICD_TYPER 0x0004 +#define GICD_IIDR 0x0008 +#define GICD_STATUSR 0x0010 +#define GICD_SETSPI_NSR 0x0040 +#define GICD_CLRSPI_NSR 0x0048 +#define GICD_SETSPI_SR 0x0050 +#define GICD_CLRSPI_SR 0x0058 +#define GICD_SEIR 0x0068 +#define GICD_IGROUPRn 0x0080 +#define GICD_ISENABLERn 0x0100 +#define GICD_ICENABLERn 0x0180 +#define GICD_ISPENDRn 0x0200 +#define GICD_ICPENDRn 0x0280 +#define GICD_ISACTIVERn 0x0300 +#define GICD_ICACTIVERn 0x0380 +#define GICD_IPRIORITYRn 0x0400 +#define GICD_ITARGETSRn 0x0800 +#define GICD_ICFGR 0x0c00 +#define GICD_IGROUPMODRn 0x0d00 +#define GICD_NSACRn 0x0e00 +#define GICD_SGIR 0x0f00 +#define GICD_CPENDSGIRn 0x0f10 +#define GICD_SPENDSGIRn 0x0f20 +#define GICD_IROUTERn 0x6000 + +/* Cpu Interface Memory Mapped Registers */ +#define GICC_CTLR 0x0000 +#define GICC_PMR 0x0004 +#define GICC_BPR 0x0008 +#define GICC_IAR 0x000C +#define GICC_EOIR 0x0010 +#define GICC_RPR 0x0014 +#define GICC_HPPIR 0x0018 +#define GICC_ABPR 0x001c +#define GICC_AIAR 0x0020 +#define GICC_AEOIR 0x0024 +#define GICC_AHPPIR 0x0028 +#define GICC_APRn 0x00d0 +#define GICC_NSAPRn 0x00e0 +#define GICC_IIDR 0x00fc +#define GICC_DIR 0x1000 + +/* ReDistributor Registers for Control and Physical LPIs */ +#define GICR_CTLR 0x0000 +#define GICR_IIDR 0x0004 +#define GICR_TYPER 0x0008 +#define GICR_STATUSR 0x0010 +#define GICR_WAKER 0x0014 +#define GICR_SETLPIR 0x0040 +#define GICR_CLRLPIR 0x0048 +#define GICR_SEIR 0x0068 +#define GICR_PROPBASER 0x0070 +#define GICR_PENDBASER 0x0078 +#define GICR_INVLPIR 0x00a0 +#define GICR_INVALLR 0x00b0 +#define GICR_SYNCR 0x00c0 +#define GICR_MOVLPIR 0x0100 +#define GICR_MOVALLR 0x0110 + +/* ReDistributor Registers for SGIs and PPIs */ +#define GICR_IGROUPRn 0x0080 +#define GICR_ISENABLERn 0x0100 +#define GICR_ICENABLERn 0x0180 +#define GICR_ISPENDRn 0x0200 +#define GICR_ICPENDRn 0x0280 +#define GICR_ISACTIVERn 0x0300 +#define GICR_ICACTIVERn 0x0380 +#define GICR_IPRIORITYRn 0x0400 +#define GICR_ICFGR0 0x0c00 +#define GICR_ICFGR1 0x0c04 +#define GICR_IGROUPMODRn 0x0d00 +#define GICR_NSACRn 0x0e00 + +/* Cpu Interface System Registers */ +#define ICC_IAR0_EL1 S3_0_C12_C8_0 +#define ICC_IAR1_EL1 S3_0_C12_C12_0 +#define ICC_EOIR0_EL1 S3_0_C12_C8_1 +#define ICC_EOIR1_EL1 S3_0_C12_C12_1 +#define ICC_HPPIR0_EL1 S3_0_C12_C8_2 +#define ICC_HPPIR1_EL1 S3_0_C12_C12_2 +#define ICC_BPR0_EL1 S3_0_C12_C8_3 +#define ICC_BPR1_EL1 S3_0_C12_C12_3 +#define ICC_DIR_EL1 S3_0_C12_C11_1 +#define ICC_PMR_EL1 S3_0_C4_C6_0 +#define ICC_RPR_EL1 S3_0_C12_C11_3 +#define ICC_CTLR_EL1 S3_0_C12_C12_4 +#define ICC_CTLR_EL3 S3_6_C12_C12_4 +#define ICC_SRE_EL1 S3_0_C12_C12_5 +#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_SRE_EL3 S3_6_C12_C12_5 +#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6 +#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 +#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7 +#define ICC_SEIEN_EL1 S3_0_C12_C13_0 +#define ICC_SGI0R_EL1 S3_0_C12_C11_7 +#define ICC_SGI1R_EL1 S3_0_C12_C11_5 +#define ICC_ASGI1R_EL1 S3_0_C12_C11_6 + +#endif /* __GIC_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/global_data.h b/roms/u-boot/arch/arm/include/asm/global_data.h new file mode 100644 index 000000000..79432f3bb --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/global_data.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2002-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef __ASM_GBL_DATA_H +#define __ASM_GBL_DATA_H + +#ifndef __ASSEMBLY__ + +#include + +#include +#include + +/* Architecture-specific global data */ +struct arch_global_data { +#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_FSL_ESDHC_IMX) + u32 sdhc_clk; +#endif + +#if defined(CONFIG_FSL_ESDHC) + u32 sdhc_per_clk; +#endif + +#if defined(CONFIG_U_QE) + u32 qe_clk; + u32 brg_clk; + uint mp_alloc_base; + uint mp_alloc_top; +#endif /* CONFIG_U_QE */ + +#ifdef CONFIG_AT91FAMILY + /* "static data" needed by at91's clock.c */ + unsigned long cpu_clk_rate_hz; + unsigned long main_clk_rate_hz; + unsigned long mck_rate_hz; + unsigned long plla_rate_hz; + unsigned long pllb_rate_hz; + unsigned long at91_pllb_usb_init; +#endif + /* "static data" needed by most of timer.c on ARM platforms */ + unsigned long timer_rate_hz; + unsigned int tbu; + unsigned int tbl; + unsigned long lastinc; + unsigned long long timer_reset_value; +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + unsigned long tlb_addr; + unsigned long tlb_size; +#if defined(CONFIG_ARM64) + unsigned long tlb_fillptr; + unsigned long tlb_emerg; +#endif +#endif +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#define MEM_RESERVE_SECURE_SECURED 0x1 +#define MEM_RESERVE_SECURE_MAINTAINED 0x2 +#define MEM_RESERVE_SECURE_ADDR_MASK (~0x3) + /* + * Secure memory addr + * This variable needs maintenance if the RAM base is not zero, + * or if RAM splits into non-consecutive banks. It also has a + * flag indicating the secure memory is marked as secure by MMU. + * Flags used: 0x1 secured + * 0x2 maintained + */ + phys_addr_t secure_ram; + unsigned long tlb_allocated; +#endif +#ifdef CONFIG_RESV_RAM + /* + * Reserved RAM for memory resident, eg. Management Complex (MC) + * driver which continues to run after U-Boot exits. + */ + phys_addr_t resv_ram; +#endif + +#ifdef CONFIG_ARCH_OMAP2PLUS + u32 omap_boot_device; + u32 omap_boot_mode; + u8 omap_ch_flags; +#endif +#if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR) + unsigned long mem2_clk; +#endif + +#ifdef CONFIG_ARCH_IMX8 + struct udevice *scu_dev; +#endif +}; + +#include + +#if defined(__clang__) || defined(CONFIG_LTO) + +#define DECLARE_GLOBAL_DATA_PTR +#define gd get_gd() + +static inline gd_t *get_gd(void) +{ + gd_t *gd_ptr; + +#ifdef CONFIG_ARM64 + __asm__ volatile("mov %0, x18\n" : "=r" (gd_ptr)); +#else + __asm__ volatile("mov %0, r9\n" : "=r" (gd_ptr)); +#endif + + return gd_ptr; +} + +#else + +#ifdef CONFIG_ARM64 +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("x18") +#else +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9") +#endif +#endif + +static inline void set_gd(volatile gd_t *gd_ptr) +{ +#ifdef CONFIG_ARM64 + __asm__ volatile("ldr x18, %0\n" : : "m"(gd_ptr)); +#elif __ARM_ARCH >= 7 + __asm__ volatile("ldr r9, %0\n" : : "m"(gd_ptr)); +#else + __asm__ volatile("mov r9, %0\n" : : "r"(gd_ptr)); +#endif +} + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_GBL_DATA_H */ diff --git a/roms/u-boot/arch/arm/include/asm/gpio.h b/roms/u-boot/arch/arm/include/asm/gpio.h new file mode 100644 index 000000000..760936788 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/gpio.h @@ -0,0 +1,10 @@ +#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \ + !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM68360) && \ + !defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \ + !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \ + !defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM) && \ + !defined(CONFIG_TARGET_BCMNS3) && !defined(CONFIG_TARGET_TOTAL_COMPUTE) && \ + !defined(CONFIG_ARCH_QEMU) +#include +#endif +#include diff --git a/roms/u-boot/arch/arm/include/asm/handoff.h b/roms/u-boot/arch/arm/include/asm/handoff.h new file mode 100644 index 000000000..0790d2ab1 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/handoff.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Architecture-specific SPL handoff information for ARM + * + * Copyright 2019 Amarula Solutions, BV + * Written by Michael Trimarchi + */ + +#ifndef __asm_handoff_h +#define __asm_handoff_h + +/** + * struct arch_spl_handoff - architecture-specific handoff info + * + * @usable_ram_top: Value returned by board_get_usable_ram_top() in SPL + */ +struct arch_spl_handoff { + ulong usable_ram_top; +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/hardware.h b/roms/u-boot/arch/arm/include/asm/hardware.h new file mode 100644 index 000000000..1fd1a5b65 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/hardware.h @@ -0,0 +1,18 @@ +/* + * linux/include/asm-arm/hardware.h + * + * Copyright (C) 1996 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common hardware definitions + */ + +#ifndef __ASM_HARDWARE_H +#define __ASM_HARDWARE_H + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/io.h b/roms/u-boot/arch/arm/include/asm/io.h new file mode 100644 index 000000000..df264a170 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/io.h @@ -0,0 +1,498 @@ +/* + * linux/include/asm-arm/io.h + * + * Copyright (C) 1996-2000 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Modifications: + * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both + * constant addresses and variable addresses. + * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture + * specific IO header files. + * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. + * 04-Apr-1999 PJB Added check_signature. + * 12-Dec-1999 RMK More cleanups + * 18-Jun-2000 RMK Removed virt_to_* and friends definitions + */ +#ifndef __ASM_ARM_IO_H +#define __ASM_ARM_IO_H + +#ifdef __KERNEL__ + +#include +#include +#include +#include +#include +#if 0 /* XXX###XXX */ +#include +#endif /* XXX###XXX */ + +static inline void sync(void) +{ +} + +/* + * Generic virtual read/write. Note that we don't support half-word + * read/writes. We define __arch_*[bl] here, and leave __arch_*w + * to the architecture specific code. + */ +#define __arch_getb(a) (*(volatile unsigned char *)(a)) +#define __arch_getw(a) (*(volatile unsigned short *)(a)) +#define __arch_getl(a) (*(volatile unsigned int *)(a)) +#define __arch_getq(a) (*(volatile unsigned long long *)(a)) + +#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) +#define __arch_putq(v,a) (*(volatile unsigned long long *)(a) = (v)) + +static inline void __raw_writesb(unsigned long addr, const void *data, + int bytelen) +{ + uint8_t *buf = (uint8_t *)data; + while(bytelen--) + __arch_putb(*buf++, addr); +} + +static inline void __raw_writesw(unsigned long addr, const void *data, + int wordlen) +{ + uint16_t *buf = (uint16_t *)data; + while(wordlen--) + __arch_putw(*buf++, addr); +} + +static inline void __raw_writesl(unsigned long addr, const void *data, + int longlen) +{ + uint32_t *buf = (uint32_t *)data; + while(longlen--) + __arch_putl(*buf++, addr); +} + +static inline void __raw_readsb(unsigned long addr, void *data, int bytelen) +{ + uint8_t *buf = (uint8_t *)data; + while(bytelen--) + *buf++ = __arch_getb(addr); +} + +static inline void __raw_readsw(unsigned long addr, void *data, int wordlen) +{ + uint16_t *buf = (uint16_t *)data; + while(wordlen--) + *buf++ = __arch_getw(addr); +} + +static inline void __raw_readsl(unsigned long addr, void *data, int longlen) +{ + uint32_t *buf = (uint32_t *)data; + while(longlen--) + *buf++ = __arch_getl(addr); +} + +#define __raw_writeb(v,a) __arch_putb(v,a) +#define __raw_writew(v,a) __arch_putw(v,a) +#define __raw_writel(v,a) __arch_putl(v,a) +#define __raw_writeq(v,a) __arch_putq(v,a) + +#define __raw_readb(a) __arch_getb(a) +#define __raw_readw(a) __arch_getw(a) +#define __raw_readl(a) __arch_getl(a) +#define __raw_readq(a) __arch_getq(a) + +/* + * TODO: The kernel offers some more advanced versions of barriers, it might + * have some advantages to use them instead of the simple one here. + */ +#define mb() dsb() +#define rmb() dsb() +#define wmb() dsb() +#define __iormb() dmb() +#define __iowmb() dmb() + +#define smp_processor_id() 0 + +#define writeb(v,c) ({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; }) +#define writew(v,c) ({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; }) +#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) +#define writeq(v,c) ({ u64 __v = v; __iowmb(); __arch_putq(__v,c); __v; }) + +#define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; }) +#define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; }) +#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) +#define readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; }) + +/* + * Relaxed I/O memory access primitives. These follow the Device memory + * ordering rules but do not guarantee any ordering relative to Normal memory + * accesses. + */ +#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; }) +#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \ + __raw_readw(c)); __r; }) +#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ + __raw_readl(c)); __r; }) +#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \ + __raw_readq(c)); __r; }) + +#define writeb_relaxed(v, c) ((void)__raw_writeb((v), (c))) +#define writew_relaxed(v, c) ((void)__raw_writew((__force u16) \ + cpu_to_le16(v), (c))) +#define writel_relaxed(v, c) ((void)__raw_writel((__force u32) \ + cpu_to_le32(v), (c))) +#define writeq_relaxed(v, c) ((void)__raw_writeq((__force u64) \ + cpu_to_le64(v), (c))) + +/* + * The compiler seems to be incapable of optimising constants + * properly. Spell it out to the compiler in some cases. + * These are only valid for small values of "off" (< 1<<12) + */ +#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) +#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) +#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) + +#define __raw_base_readb(base,off) __arch_base_getb(base,off) +#define __raw_base_readw(base,off) __arch_base_getw(base,off) +#define __raw_base_readl(base,off) __arch_base_getl(base,off) + +/* + * Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single call. These macros can + * also be used to set a multiple-bit bit pattern using a mask, by + * specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a) +#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a)) + +#define out_le64(a,v) out_arch(q,le64,a,v) +#define out_le32(a,v) out_arch(l,le32,a,v) +#define out_le16(a,v) out_arch(w,le16,a,v) + +#define in_le64(a) in_arch(q,le64,a) +#define in_le32(a) in_arch(l,le32,a) +#define in_le16(a) in_arch(w,le16,a) + +#define out_be64(a,v) out_arch(l,be64,a,v) +#define out_be32(a,v) out_arch(l,be32,a,v) +#define out_be16(a,v) out_arch(w,be16,a,v) + +#define in_be64(a) in_arch(l,be64,a) +#define in_be32(a) in_arch(l,be32,a) +#define in_be16(a) in_arch(w,be16,a) + +#define out_64(a,v) __raw_writeq(v,a) +#define out_32(a,v) __raw_writel(v,a) +#define out_16(a,v) __raw_writew(v,a) +#define out_8(a,v) __raw_writeb(v,a) + +#define in_64(a) __raw_readq(a) +#define in_32(a) __raw_readl(a) +#define in_16(a) __raw_readw(a) +#define in_8(a) __raw_readb(a) + +#define clrbits(type, addr, clear) \ + out_##type((addr), in_##type(addr) & ~(clear)) + +#define setbits(type, addr, set) \ + out_##type((addr), in_##type(addr) | (set)) + +#define clrsetbits(type, addr, clear, set) \ + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) + +#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) +#define setbits_be32(addr, set) setbits(be32, addr, set) +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) + +#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) +#define setbits_le32(addr, set) setbits(le32, addr, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrbits_32(addr, clear) clrbits(32, addr, clear) +#define setbits_32(addr, set) setbits(32, addr, set) +#define clrsetbits_32(addr, clear, set) clrsetbits(32, addr, clear, set) + +#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) +#define setbits_be16(addr, set) setbits(be16, addr, set) +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) + +#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) +#define setbits_le16(addr, set) setbits(le16, addr, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) + +#define clrbits_16(addr, clear) clrbits(16, addr, clear) +#define setbits_16(addr, set) setbits(16, addr, set) +#define clrsetbits_16(addr, clear, set) clrsetbits(16, addr, clear, set) + +#define clrbits_8(addr, clear) clrbits(8, addr, clear) +#define setbits_8(addr, set) setbits(8, addr, set) +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + +#define clrbits_be64(addr, clear) clrbits(be64, addr, clear) +#define setbits_be64(addr, set) setbits(be64, addr, set) +#define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set) + +#define clrbits_le64(addr, clear) clrbits(le64, addr, clear) +#define setbits_le64(addr, set) setbits(le64, addr, set) +#define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set) + +#define clrbits_64(addr, clear) clrbits(64, addr, clear) +#define setbits_64(addr, set) setbits(64, addr, set) +#define clrsetbits_64(addr, clear, set) clrsetbits(64, addr, clear, set) + +/* + * Now, pick up the machine-defined IO definitions + */ +#if 0 /* XXX###XXX */ +#include +#endif /* XXX###XXX */ + +/* + * IO port access primitives + * ------------------------- + * + * The ARM doesn't have special IO access instructions; all IO is memory + * mapped. Note that these are defined to perform little endian accesses + * only. Their primary purpose is to access PCI and ISA peripherals. + * + * Note that for a big endian machine, this implies that the following + * big endian mode connectivity is in place, as described by numerous + * ARM documents: + * + * PCI: D0-D7 D8-D15 D16-D23 D24-D31 + * ARM: D24-D31 D16-D23 D8-D15 D0-D7 + * + * The machine specific io.h include defines __io to translate an "IO" + * address to a memory address. + * + * Note that we prevent GCC re-ordering or caching values in expressions + * by introducing sequence points into the in*() definitions. Note that + * __raw_* do not guarantee this behaviour. + * + * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. + */ +#ifdef __io +#define outb(v,p) __raw_writeb(v,__io(p)) +#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) +#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) + +#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) +#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) +#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) + +#define outsb(p,d,l) __raw_writesb(__io(p),d,l) +#define outsw(p,d,l) __raw_writesw(__io(p),d,l) +#define outsl(p,d,l) __raw_writesl(__io(p),d,l) + +#define insb(p,d,l) __raw_readsb(__io(p),d,l) +#define insw(p,d,l) __raw_readsw(__io(p),d,l) +#define insl(p,d,l) __raw_readsl(__io(p),d,l) +#endif + +#define outb_p(val,port) outb((val),(port)) +#define outw_p(val,port) outw((val),(port)) +#define outl_p(val,port) outl((val),(port)) +#define inb_p(port) inb((port)) +#define inw_p(port) inw((port)) +#define inl_p(port) inl((port)) + +#define outsb_p(port,from,len) outsb(port,from,len) +#define outsw_p(port,from,len) outsw(port,from,len) +#define outsl_p(port,from,len) outsl(port,from,len) +#define insb_p(port,to,len) insb(port,to,len) +#define insw_p(port,to,len) insw(port,to,len) +#define insl_p(port,to,len) insl(port,to,len) + +#define writesl(a, d, s) __raw_writesl((unsigned long)a, d, s) +#define readsl(a, d, s) __raw_readsl((unsigned long)a, d, s) +#define writesw(a, d, s) __raw_writesw((unsigned long)a, d, s) +#define readsw(a, d, s) __raw_readsw((unsigned long)a, d, s) +#define writesb(a, d, s) __raw_writesb((unsigned long)a, d, s) +#define readsb(a, d, s) __raw_readsb((unsigned long)a, d, s) + +/* + * DMA-consistent mapping functions. These allocate/free a region of + * uncached, unwrite-buffered mapped memory space for use with DMA + * devices. This is the "generic" version. The PCI specific version + * is in pci.h + */ +extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); +extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); +extern void consistent_sync(void *vaddr, size_t size, int rw); + +/* + * String version of IO memory access ops: + */ +extern void _memcpy_fromio(void *, unsigned long, size_t); +extern void _memcpy_toio(unsigned long, const void *, size_t); +extern void _memset_io(unsigned long, int, size_t); + +extern void __readwrite_bug(const char *fn); + +/* Optimized copy functions to read from/write to IO sapce */ +#ifdef CONFIG_ARM64 +/* + * Copy data from IO memory space to "real" memory space. + */ +static inline +void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count) +{ + while (count && !IS_ALIGNED((unsigned long)from, 8)) { + *(u8 *)to = __raw_readb(from); + from++; + to++; + count--; + } + + while (count >= 8) { + *(u64 *)to = __raw_readq(from); + from += 8; + to += 8; + count -= 8; + } + + while (count) { + *(u8 *)to = __raw_readb(from); + from++; + to++; + count--; + } +} + +/* + * Copy data from "real" memory space to IO memory space. + */ +static inline +void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count) +{ + while (count && !IS_ALIGNED((unsigned long)to, 8)) { + __raw_writeb(*(u8 *)from, to); + from++; + to++; + count--; + } + + while (count >= 8) { + __raw_writeq(*(u64 *)from, to); + from += 8; + to += 8; + count -= 8; + } + + while (count) { + __raw_writeb(*(u8 *)from, to); + from++; + to++; + count--; + } +} + +/* + * "memset" on IO memory space. + */ +static inline +void __memset_io(volatile void __iomem *dst, int c, size_t count) +{ + u64 qc = (u8)c; + + qc |= qc << 8; + qc |= qc << 16; + qc |= qc << 32; + + while (count && !IS_ALIGNED((unsigned long)dst, 8)) { + __raw_writeb(c, dst); + dst++; + count--; + } + + while (count >= 8) { + __raw_writeq(qc, dst); + dst += 8; + count -= 8; + } + + while (count) { + __raw_writeb(c, dst); + dst++; + count--; + } +} +#endif /* CONFIG_ARM64 */ + +#ifdef CONFIG_ARM64 +#define memset_io(a, b, c) __memset_io((a), (b), (c)) +#define memcpy_fromio(a, b, c) __memcpy_fromio((a), (b), (c)) +#define memcpy_toio(a, b, c) __memcpy_toio((a), (b), (c)) +#else +#define memset_io(a, b, c) memset((void *)(a), (b), (c)) +#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) +#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) +#endif + +/* + * If this architecture has ISA IO, then define the isa_read/isa_write + * macros. + */ +#ifdef __mem_isa + +#define isa_readb(addr) __raw_readb(__mem_isa(addr)) +#define isa_readw(addr) __raw_readw(__mem_isa(addr)) +#define isa_readl(addr) __raw_readl(__mem_isa(addr)) +#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) +#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) +#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) +#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) +#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) +#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) + +#define isa_eth_io_copy_and_sum(a,b,c,d) \ + eth_copy_and_sum((a),__mem_isa(b),(c),(d)) + +static inline int +isa_check_signature(unsigned long io_addr, const unsigned char *signature, + int length) +{ + int retval = 0; + do { + if (isa_readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +#else /* __mem_isa */ + +#define isa_readb(addr) (__readwrite_bug("isa_readb"),0) +#define isa_readw(addr) (__readwrite_bug("isa_readw"),0) +#define isa_readl(addr) (__readwrite_bug("isa_readl"),0) +#define isa_writeb(val,addr) __readwrite_bug("isa_writeb") +#define isa_writew(val,addr) __readwrite_bug("isa_writew") +#define isa_writel(val,addr) __readwrite_bug("isa_writel") +#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io") +#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio") +#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio") + +#define isa_eth_io_copy_and_sum(a,b,c,d) \ + __readwrite_bug("isa_eth_io_copy_and_sum") + +#define isa_check_signature(io,sig,len) (0) + +#endif /* __mem_isa */ +#endif /* __KERNEL__ */ + +#include +#include + +#endif /* __ASM_ARM_IO_H */ diff --git a/roms/u-boot/arch/arm/include/asm/iproc-common/armpll.h b/roms/u-boot/arch/arm/include/asm/iproc-common/armpll.h new file mode 100644 index 000000000..f5b60b191 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/iproc-common/armpll.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Broadcom Corporation. + */ + +#ifndef __ARMPLL_H +#define __ARMPLL_H + +#include + +uint32_t armpll_config(uint32_t clkmhz); + +#endif /*__ARMPLL_H */ diff --git a/roms/u-boot/arch/arm/include/asm/iproc-common/configs.h b/roms/u-boot/arch/arm/include/asm/iproc-common/configs.h new file mode 100644 index 000000000..4733c0793 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/iproc-common/configs.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Broadcom Corporation. + */ + +#ifndef __IPROC_COMMON_CONFIGS_H +#define __IPROC_COMMON_CONFIGS_H + +#include + +/* Architecture, CPU, chip, etc */ +#define CONFIG_IPROC + +/* Memory Info */ +#define CONFIG_SYS_SDRAM_BASE 0x61000000 + +#endif /* __IPROC_COMMON_CONFIGS_H */ diff --git a/roms/u-boot/arch/arm/include/asm/iproc-common/iproc_sdhci.h b/roms/u-boot/arch/arm/include/asm/iproc-common/iproc_sdhci.h new file mode 100644 index 000000000..4e299217f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/iproc-common/iproc_sdhci.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: */ +/* + * Copyright 2019 Broadcom + * + */ + +#ifndef __IPROC_SDHCI_H +#define __IPROC_SDHCI_H + +int iproc_sdhci_init(int dev_index, u32 quirks); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/iproc-common/sysmap.h b/roms/u-boot/arch/arm/include/asm/iproc-common/sysmap.h new file mode 100644 index 000000000..efd2f35f2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/iproc-common/sysmap.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Broadcom Corporation. + */ + +#ifndef __SYSMAP_H +#define __SYSMAP_H + +#define IHOST_PROC_CLK_PLLARMA 0X19000C00 +#define IHOST_PROC_CLK_PLLARMB 0X19000C04 +#define IHOST_PROC_CLK_PLLARMA__PLLARM_PDIV_R 24 + +#define IHOST_PROC_CLK_WR_ACCESS 0X19000000 +#define IHOST_PROC_CLK_POLICY_FREQ 0X19000008 +#define IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE 31 +#define IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R 24 +#define IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R 16 +#define IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R 8 +#define IHOST_PROC_CLK_POLICY_CTL 0X1900000C +#define IHOST_PROC_CLK_POLICY_CTL__GO 0 +#define IHOST_PROC_CLK_POLICY_CTL__GO_AC 1 +#define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_R 0 +#define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH 20 +#define IHOST_PROC_CLK_PLLARMA__PLLARM_LOCK 28 +#define IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R 0 +#define IHOST_PROC_CLK_PLLARMA__PLLARM_NDIV_INT_R 8 +#define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB 1 +#define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_RESETB 0 +#define IHOST_PROC_CLK_CORE0_CLKGATE 0X19000200 +#define IHOST_PROC_CLK_CORE1_CLKGATE 0X19000204 +#define IHOST_PROC_CLK_ARM_SWITCH_CLKGATE 0X19000210 +#define IHOST_PROC_CLK_ARM_PERIPH_CLKGATE 0X19000300 +#define IHOST_PROC_CLK_APB0_CLKGATE 0X19000400 +#define IPROC_CLKCT_HDELAY_SW_EN 0x00000303 + +#define IPROC_REG_WRITE_ACCESS 0x00a5a501 + +#define IPROC_PERIPH_BASE 0x19020000 +#define IPROC_PERIPH_INT_CTRL_REG_BASE (IPROC_PERIPH_BASE + 0x100) +#define IPROC_PERIPH_GLB_TIM_REG_BASE (IPROC_PERIPH_BASE + 0x200) +#define IPROC_PERIPH_PVT_TIM_REG_BASE (IPROC_PERIPH_BASE + 0x600) +#define IPROC_PERIPH_INT_DISTR_REG_BASE (IPROC_PERIPH_BASE + 0x1000) + +#define PLL_AXI_CLK 0x1DCD6500 + +#endif /* __SYSMAP_H */ diff --git a/roms/u-boot/arch/arm/include/asm/iproc-common/timer.h b/roms/u-boot/arch/arm/include/asm/iproc-common/timer.h new file mode 100644 index 000000000..44810c863 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/iproc-common/timer.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Broadcom Corporation. + */ + +#ifndef __TIMER_H +#define __TIMER_H + +#include + +void timer_systick_init(uint32_t tick_ms); +void timer_global_init(void); + +/* ARM A9 Private Timer */ +#define TIMER_PVT_LOAD_OFFSET 0x00000000 +#define TIMER_PVT_COUNTER_OFFSET 0x00000004 +#define TIMER_PVT_CTRL_OFFSET 0x00000008 +#define TIMER_PVT_STATUS_OFFSET 0x0000000C +#define TIMER_PVT_TIM_CTRL_TIM_EN 0x00000001 +#define TIMER_PVT_TIM_CTRL_AUTO_RELD 0x00000002 +#define TIMER_PVT_TIM_CTRL_INT_EN 0x00000004 +#define TIMER_PVT_TIM_CTRL_PRESC_MASK 0x0000FF00 +#define TIMER_PVT_TIM_INT_STATUS_SET 0x00000001 + +/* Global timer */ +#define TIMER_GLB_LOW_OFFSET 0x00000000 +#define TIMER_GLB_HI_OFFSET 0x00000004 +#define TIMER_GLB_CTRL_OFFSET 0x00000008 +#define TIMER_GLB_TIM_CTRL_TIM_EN 0x00000001 +#define TIMER_GLB_TIM_CTRL_COMP_EN 0x00000002 +#define TIMER_GLB_TIM_CTRL_INT_EN 0x00000004 +#define TIMER_GLB_TIM_CTRL_AUTO_INC 0x00000008 +#define TIMER_GLB_TIM_CTRL_PRESC_MASK 0x0000FF00 +#define TIMER_GLB_TIM_INT_STATUS_SET 0x00000001 + +#endif /*__TIMER_H */ diff --git a/roms/u-boot/arch/arm/include/asm/kona-common/clk.h b/roms/u-boot/arch/arm/include/asm/kona-common/clk.h new file mode 100644 index 000000000..fded004c2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/kona-common/clk.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013 Broadcom Corporation. + */ + +/* This API file is loosely based on u-boot/drivers/video/ipu.h and linux */ + +#ifndef __KONA_COMMON_CLK_H +#define __KONA_COMMON_CLK_H + +#include + +struct clk; + +/* Only implement required functions for your specific architecture */ +int clk_init(void); +struct clk *clk_get(const char *id); +int clk_enable(struct clk *clk); +void clk_disable(struct clk *clk); +unsigned long clk_get_rate(struct clk *clk); +long clk_round_rate(struct clk *clk, unsigned long rate); +int clk_set_rate(struct clk *clk, unsigned long rate); +int clk_set_parent(struct clk *clk, struct clk *parent); +struct clk *clk_get_parent(struct clk *clk); +int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep); +int clk_bsc_enable(void *base); +int clk_usb_otg_enable(void *base); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/kona-common/kona_sdhci.h b/roms/u-boot/arch/arm/include/asm/kona-common/kona_sdhci.h new file mode 100644 index 000000000..22db651a4 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/kona-common/kona_sdhci.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013 Broadcom Corporation. + */ + +#ifndef __KONA_SDHCI_H +#define __KONA_SDHCI_H + +int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/linkage.h b/roms/u-boot/arch/arm/include/asm/linkage.h new file mode 100644 index 000000000..dbe4b4e31 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/linkage.h @@ -0,0 +1,7 @@ +#ifndef __ASM_LINKAGE_H +#define __ASM_LINKAGE_H + +#define __ALIGN .align 0 +#define __ALIGN_STR ".align 0" + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/boot_mode.h b/roms/u-boot/arch/arm/include/asm/mach-imx/boot_mode.h new file mode 100644 index 000000000..6dc585596 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/boot_mode.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 Boundary Devices Inc. + */ + +#ifndef _ASM_BOOT_MODE_H +#define _ASM_BOOT_MODE_H +#define MAKE_CFGVAL(cfg1, cfg2, cfg3, cfg4) \ + ((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1) +#define MAKE_CFGVAL_PRIMARY_BOOT 0xfffffff0 +#define MAKE_CFGVAL_SECONDARY_BOOT 0xffffffff + +enum boot_device { + WEIM_NOR_BOOT, + ONE_NAND_BOOT, + PATA_BOOT, + SATA_BOOT, + I2C_BOOT, + SPI_NOR_BOOT, + SD1_BOOT, + SD2_BOOT, + SD3_BOOT, + SD4_BOOT, + MMC1_BOOT, + MMC2_BOOT, + MMC3_BOOT, + MMC4_BOOT, + NAND_BOOT, + QSPI_BOOT, + FLEXSPI_BOOT, + USB_BOOT, + UNKNOWN_BOOT, + BOOT_DEV_NUM = UNKNOWN_BOOT, +}; + +/* Boot device type */ +#define BOOT_TYPE_SD 0x1 +#define BOOT_TYPE_MMC 0x2 +#define BOOT_TYPE_NAND 0x3 +#define BOOT_TYPE_QSPI 0x4 +#define BOOT_TYPE_WEIM 0x5 +#define BOOT_TYPE_SPINOR 0x6 +#define BOOT_TYPE_USB 0xF + +struct boot_mode { + const char *name; + unsigned cfg_val; +}; + +void add_board_boot_modes(const struct boot_mode *p); +void boot_mode_apply(unsigned cfg_val); +extern const struct boot_mode soc_boot_modes[]; +#endif diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/dma.h b/roms/u-boot/arch/arm/include/asm/mach-imx/dma.h new file mode 100644 index 000000000..55eb84cb8 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/dma.h @@ -0,0 +1,162 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX28 APBH DMA + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2020 NXP + */ + +#ifndef __DMA_H__ +#define __DMA_H__ + +#include +#include +#include + +#define DMA_PIO_WORDS 15 +#define MXS_DMA_ALIGNMENT ARCH_DMA_MINALIGN + +/* + * MXS DMA channels + */ +#if defined(CONFIG_MX23) +enum { + MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0, + MXS_DMA_CHANNEL_AHB_APBH_SSP0, + MXS_DMA_CHANNEL_AHB_APBH_SSP1, + MXS_DMA_CHANNEL_AHB_APBH_RESERVED0, + MXS_DMA_CHANNEL_AHB_APBH_GPMI0, + MXS_DMA_CHANNEL_AHB_APBH_GPMI1, + MXS_DMA_CHANNEL_AHB_APBH_GPMI2, + MXS_DMA_CHANNEL_AHB_APBH_GPMI3, + MXS_MAX_DMA_CHANNELS, +}; +#elif defined(CONFIG_MX28) +enum { + MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0, + MXS_DMA_CHANNEL_AHB_APBH_SSP1, + MXS_DMA_CHANNEL_AHB_APBH_SSP2, + MXS_DMA_CHANNEL_AHB_APBH_SSP3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI0, + MXS_DMA_CHANNEL_AHB_APBH_GPMI1, + MXS_DMA_CHANNEL_AHB_APBH_GPMI2, + MXS_DMA_CHANNEL_AHB_APBH_GPMI3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI4, + MXS_DMA_CHANNEL_AHB_APBH_GPMI5, + MXS_DMA_CHANNEL_AHB_APBH_GPMI6, + MXS_DMA_CHANNEL_AHB_APBH_GPMI7, + MXS_DMA_CHANNEL_AHB_APBH_HSADC, + MXS_DMA_CHANNEL_AHB_APBH_LCDIF, + MXS_DMA_CHANNEL_AHB_APBH_RESERVED0, + MXS_DMA_CHANNEL_AHB_APBH_RESERVED1, + MXS_MAX_DMA_CHANNELS, +}; +#else +enum { + MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0, + MXS_DMA_CHANNEL_AHB_APBH_GPMI1, + MXS_DMA_CHANNEL_AHB_APBH_GPMI2, + MXS_DMA_CHANNEL_AHB_APBH_GPMI3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI4, + MXS_DMA_CHANNEL_AHB_APBH_GPMI5, + MXS_DMA_CHANNEL_AHB_APBH_GPMI6, + MXS_DMA_CHANNEL_AHB_APBH_GPMI7, + MXS_MAX_DMA_CHANNELS, +}; +#endif + +/* + * MXS DMA hardware command. + * + * This structure describes the in-memory layout of an entire DMA command, + * including space for the maximum number of PIO accesses. See the appropriate + * reference manual for a detailed description of what these fields mean to the + * DMA hardware. + */ +#define MXS_DMA_DESC_COMMAND_MASK 0x3 +#define MXS_DMA_DESC_COMMAND_OFFSET 0 +#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0 +#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1 +#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2 +#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3 +#define MXS_DMA_DESC_CHAIN (1 << 2) +#define MXS_DMA_DESC_IRQ (1 << 3) +#define MXS_DMA_DESC_NAND_LOCK (1 << 4) +#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5) +#define MXS_DMA_DESC_DEC_SEM (1 << 6) +#define MXS_DMA_DESC_WAIT4END (1 << 7) +#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8) +#define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9) +#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12) +#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12 +#define MXS_DMA_DESC_BYTES_MASK (0xffff << 16) +#define MXS_DMA_DESC_BYTES_OFFSET 16 + +struct mxs_dma_cmd { + u32 next; + u32 data; + union { + u32 address; + u32 alternate; + }; + u32 pio_words[DMA_PIO_WORDS]; +}; + +/* + * MXS DMA command descriptor. + * + * This structure incorporates an MXS DMA hardware command structure, along + * with metadata. + */ +#define MXS_DMA_DESC_FIRST (1 << 0) +#define MXS_DMA_DESC_LAST (1 << 1) +#define MXS_DMA_DESC_READY (1 << 31) + +struct mxs_dma_desc { + struct mxs_dma_cmd cmd; + unsigned int flags; + u32 address; + void *buffer; + struct list_head node; +} __aligned(MXS_DMA_ALIGNMENT); + +/** + * MXS DMA channel + * + * This structure represents a single DMA channel. The MXS platform code + * maintains an array of these structures to represent every DMA channel in the + * system (see mxs_dma_channels). + */ +#define MXS_DMA_FLAGS_IDLE 0 +#define MXS_DMA_FLAGS_BUSY (1 << 0) +#define MXS_DMA_FLAGS_FREE 0 +#define MXS_DMA_FLAGS_ALLOCATED (1 << 16) +#define MXS_DMA_FLAGS_VALID (1 << 31) + +struct mxs_dma_chan { + const char *name; + unsigned long dev; + struct mxs_dma_device *dma; + unsigned int flags; + unsigned int active_num; + unsigned int pending_num; + struct list_head active; + struct list_head done; +}; + +struct mxs_dma_desc *mxs_dma_desc_alloc(void); +void mxs_dma_desc_free(struct mxs_dma_desc *); +int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc); + +int mxs_dma_go(int chan); +void mxs_dma_init(void); +int mxs_dma_init_channel(int chan); +int mxs_dma_release(int chan); + +void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc); + +#endif /* __DMA_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/gpio.h b/roms/u-boot/arch/arm/include/asm/mach-imx/gpio.h new file mode 100644 index 000000000..1b7c9cd52 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/gpio.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, + */ + + +#ifndef __ASM_ARCH_IMX_GPIO_H +#define __ASM_ARCH_IMX_GPIO_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +/* GPIO registers */ +struct gpio_regs { + u32 gpio_dr; /* data */ + u32 gpio_dir; /* direction */ + u32 gpio_psr; /* pad satus */ +}; +#endif + +#define IMX_GPIO_NR(port, index) ((((port)-1)*32)+((index)&31)) + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/hab.h b/roms/u-boot/arch/arm/include/asm/mach-imx/hab.h new file mode 100644 index 000000000..2abf28ea4 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/hab.h @@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * +*/ + +#ifndef __SECURE_MX6Q_H__ +#define __SECURE_MX6Q_H__ + +#include +#include + +/* + * IVT header definitions + * Security Reference Manual for i.MX 7Dual and 7Solo Applications Processors, + * Rev. 0, 03/2017 + * Section : 6.7.1.1 + */ +#define IVT_HEADER_MAGIC 0xD1 +#define IVT_TOTAL_LENGTH 0x20 + +struct __packed ivt_header { + uint8_t magic; + uint16_t length; + uint8_t version; +}; + +struct ivt { + struct ivt_header hdr; /* IVT header above */ + uint32_t entry; /* Absolute address of first instruction */ + uint32_t reserved1; /* Reserved should be zero */ + uint32_t dcd; /* Absolute address of the image DCD */ + uint32_t boot; /* Absolute address of the boot data */ + uint32_t self; /* Absolute address of the IVT */ + uint32_t csf; /* Absolute address of the CSF */ + uint32_t reserved2; /* Reserved should be zero */ +}; + +struct __packed hab_hdr { + u8 tag; /* Tag field */ + u8 len[2]; /* Length field in bytes (big-endian) */ + u8 par; /* Parameters field */ +}; + +/* Default event structure */ +struct __packed evt_def { + struct hab_hdr hdr; /* Header */ + uint32_t sts; /* Status */ + uint32_t ctx; /* Default context */ + uint8_t *data; /* Default data location */ + size_t bytes; /* Size of default data */ +}; + +/* -------- start of HAB API updates ------------*/ +/* The following are taken from HAB4 SIS */ + +/* Status definitions */ +enum hab_status { + HAB_STS_ANY = 0x00, + HAB_FAILURE = 0x33, + HAB_WARNING = 0x69, + HAB_SUCCESS = 0xf0 +}; + +/* Security Configuration definitions */ +enum hab_config { + HAB_CFG_RETURN = 0x33, /* < Field Return IC */ + HAB_CFG_OPEN = 0xf0, /* < Non-secure IC */ + HAB_CFG_CLOSED = 0xcc /* < Secure IC */ +}; + +/* State definitions */ +enum hab_state { + HAB_STATE_INITIAL = 0x33, /* Initialising state (transitory) */ + HAB_STATE_CHECK = 0x55, /* Check state (non-secure) */ + HAB_STATE_NONSECURE = 0x66, /* Non-secure state */ + HAB_STATE_TRUSTED = 0x99, /* Trusted state */ + HAB_STATE_SECURE = 0xaa, /* Secure state */ + HAB_STATE_FAIL_SOFT = 0xcc, /* Soft fail state */ + HAB_STATE_FAIL_HARD = 0xff, /* Hard fail state (terminal) */ + HAB_STATE_NONE = 0xf0, /* No security state machine */ + HAB_STATE_MAX +}; + +enum hab_reason { + HAB_RSN_ANY = 0x00, /* Match any reason */ + HAB_ENG_FAIL = 0x30, /* Engine failure */ + HAB_INV_ADDRESS = 0x22, /* Invalid address: access denied */ + HAB_INV_ASSERTION = 0x0c, /* Invalid assertion */ + HAB_INV_CALL = 0x28, /* Function called out of sequence */ + HAB_INV_CERTIFICATE = 0x21, /* Invalid certificate */ + HAB_INV_COMMAND = 0x06, /* Invalid command: command malformed */ + HAB_INV_CSF = 0x11, /* Invalid csf */ + HAB_INV_DCD = 0x27, /* Invalid dcd */ + HAB_INV_INDEX = 0x0f, /* Invalid index: access denied */ + HAB_INV_IVT = 0x05, /* Invalid ivt */ + HAB_INV_KEY = 0x1d, /* Invalid key */ + HAB_INV_RETURN = 0x1e, /* Failed callback function */ + HAB_INV_SIGNATURE = 0x18, /* Invalid signature */ + HAB_INV_SIZE = 0x17, /* Invalid data size */ + HAB_MEM_FAIL = 0x2e, /* Memory failure */ + HAB_OVR_COUNT = 0x2b, /* Expired poll count */ + HAB_OVR_STORAGE = 0x2d, /* Exhausted storage region */ + HAB_UNS_ALGORITHM = 0x12, /* Unsupported algorithm */ + HAB_UNS_COMMAND = 0x03, /* Unsupported command */ + HAB_UNS_ENGINE = 0x0a, /* Unsupported engine */ + HAB_UNS_ITEM = 0x24, /* Unsupported configuration item */ + HAB_UNS_KEY = 0x1b, /* Unsupported key type/parameters */ + HAB_UNS_PROTOCOL = 0x14, /* Unsupported protocol */ + HAB_UNS_STATE = 0x09, /* Unsuitable state */ + HAB_RSN_MAX +}; + +enum hab_context { + HAB_CTX_ANY = 0x00, /* Match any context */ + HAB_CTX_FAB = 0xff, /* Event logged in hab_fab_test() */ + HAB_CTX_ENTRY = 0xe1, /* Event logged in hab_rvt.entry() */ + HAB_CTX_TARGET = 0x33, /* Event logged in hab_rvt.check_target() */ + HAB_CTX_AUTHENTICATE = 0x0a,/* Logged in hab_rvt.authenticate_image() */ + HAB_CTX_DCD = 0xdd, /* Event logged in hab_rvt.run_dcd() */ + HAB_CTX_CSF = 0xcf, /* Event logged in hab_rvt.run_csf() */ + HAB_CTX_COMMAND = 0xc0, /* Event logged executing csf/dcd command */ + HAB_CTX_AUT_DAT = 0xdb, /* Authenticated data block */ + HAB_CTX_ASSERT = 0xa0, /* Event logged in hab_rvt.assert() */ + HAB_CTX_EXIT = 0xee, /* Event logged in hab_rvt.exit() */ + HAB_CTX_MAX +}; + +enum hab_target { + HAB_TGT_MEMORY = 0x0f, + HAB_TGT_PERIPHERAL = 0xf0, + HAB_TGT_ANY = 0x55, +}; + +struct imx_sec_config_fuse_t { + int bank; + int word; +}; + +#if defined(CONFIG_IMX_HAB) +extern struct imx_sec_config_fuse_t const imx_sec_config_fuse; +#endif + +/*Function prototype description*/ +typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t, + uint8_t* , size_t*); +typedef enum hab_status hab_rvt_report_status_t(enum hab_config *, + enum hab_state *); +typedef enum hab_status hab_loader_callback_f_t(void**, size_t*, const void*); +typedef enum hab_status hab_rvt_entry_t(void); +typedef enum hab_status hab_rvt_exit_t(void); +typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t, + void **, size_t *, hab_loader_callback_f_t); +typedef enum hab_status hab_rvt_check_target_t(enum hab_target, const void *, + size_t); +typedef void hab_rvt_failsafe_t(void); +typedef void hapi_clock_init_t(void); + +#define HAB_ENG_ANY 0x00 /* Select first compatible engine */ +#define HAB_ENG_SCC 0x03 /* Security controller */ +#define HAB_ENG_RTIC 0x05 /* Run-time integrity checker */ +#define HAB_ENG_SAHARA 0x06 /* Crypto accelerator */ +#define HAB_ENG_CSU 0x0a /* Central Security Unit */ +#define HAB_ENG_SRTC 0x0c /* Secure clock */ +#define HAB_ENG_DCP 0x1b /* Data Co-Processor */ +#define HAB_ENG_CAAM 0x1d /* CAAM */ +#define HAB_ENG_SNVS 0x1e /* Secure Non-Volatile Storage */ +#define HAB_ENG_OCOTP 0x21 /* Fuse controller */ +#define HAB_ENG_DTCP 0x22 /* DTCP co-processor */ +#define HAB_ENG_ROM 0x36 /* Protected ROM area */ +#define HAB_ENG_HDCP 0x24 /* HDCP co-processor */ +#define HAB_ENG_RTL 0x77 /* RTL simulation engine */ +#define HAB_ENG_SW 0xff /* Software engine */ + +#ifdef CONFIG_ARM64 +#ifdef CONFIG_IMX8MQ +#define HAB_RVT_BASE 0x00000880 +#else +#define HAB_RVT_BASE 0x00000900 +#endif + +#define HAB_RVT_ENTRY (*(ulong *)(HAB_RVT_BASE + 0x08)) +#define HAB_RVT_EXIT (*(ulong *)(HAB_RVT_BASE + 0x10)) +#define HAB_RVT_CHECK_TARGET (*(ulong *)(HAB_RVT_BASE + 0x18)) +#define HAB_RVT_AUTHENTICATE_IMAGE (*(ulong *)(HAB_RVT_BASE + 0x20)) +#define HAB_RVT_REPORT_EVENT (*(ulong *)(HAB_RVT_BASE + 0x40)) +#define HAB_RVT_REPORT_STATUS (*(ulong *)(HAB_RVT_BASE + 0x48)) +#define HAB_RVT_FAILSAFE (*(ulong *)(HAB_RVT_BASE + 0x50)) +#else + +#ifdef CONFIG_ROM_UNIFIED_SECTIONS +#define HAB_RVT_BASE 0x00000100 +#else +#define HAB_RVT_BASE_NEW 0x00000098 +#define HAB_RVT_BASE_OLD 0x00000094 +#define HAB_RVT_BASE ((is_mx6dqp()) ? \ + HAB_RVT_BASE_NEW : \ + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_3)) ? \ + HAB_RVT_BASE_NEW : \ + (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ + HAB_RVT_BASE_NEW : HAB_RVT_BASE_OLD) +#endif + +#define HAB_RVT_ENTRY (*(uint32_t *)(HAB_RVT_BASE + 0x04)) +#define HAB_RVT_EXIT (*(uint32_t *)(HAB_RVT_BASE + 0x08)) +#define HAB_RVT_CHECK_TARGET (*(uint32_t *)(HAB_RVT_BASE + 0x0C)) +#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)(HAB_RVT_BASE + 0x10)) +#define HAB_RVT_REPORT_EVENT (*(uint32_t *)(HAB_RVT_BASE + 0x20)) +#define HAB_RVT_REPORT_STATUS (*(uint32_t *)(HAB_RVT_BASE + 0x24)) +#define HAB_RVT_FAILSAFE (*(uint32_t *)(HAB_RVT_BASE + 0x28)) + +#endif /*CONFIG_ARM64*/ + +#define HAB_CID_ROM 0 /**< ROM Caller ID */ +#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/ + +#define HAB_TAG_RVT 0xDD /* ROM Vector Table */ +#define HAB_CMD_HDR 0xD4 /* CSF Header */ +#define HAB_CMD_WRT_DAT 0xCC /* Write Data command tag */ +#define HAB_CMD_CHK_DAT 0xCF /* Check Data command tag */ +#define HAB_CMD_SET 0xB1 /* Set command tag */ +#define HAB_PAR_MID 0x01 /* MID parameter value */ + +#define IVT_SIZE 0x20 +#define CSF_PAD_SIZE 0x2000 + +#define HAB_TAG_EVT 0xDB +#define HAB_TAG_EVT_DEF 0x0C + +#define HAB_MAJ_VER 0x40 +#define HAB_MAJ_MASK 0xF0 + +/* ----------- end of HAB API updates ------------*/ + +int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, + uint32_t ivt_offset); +bool imx_hab_is_enabled(void); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/imx-nandbcb.h b/roms/u-boot/arch/arm/include/asm/mach-imx/imx-nandbcb.h new file mode 100644 index 000000000..74c9031d4 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/imx-nandbcb.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2017 Jagan Teki + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IMX_NAND_BCB_H_ +#define _IMX_NAND_BCB_H_ + +#define FCB_FINGERPRINT 0x20424346 /* 'FCB' */ +#define FCB_VERSION_1 0x01000000 +#define FCB_FINGERPRINT_OFF 0x4 /* FCB fingerprint offset*/ + +#define DBBT_FINGERPRINT 0x54424244 /* 'DBBT' */ +#define DBBT_VERSION_1 0x01000000 +#define DBBT_FINGERPRINT_OFF 0x4 /* DBBT fingerprint offset*/ + +struct dbbt_block { + u32 checksum; /* reserved on i.MX6 */ + u32 fingerprint; + u32 version; + u32 numberbb; /* reserved on i.MX6 */ + u32 dbbtpages; +}; + +struct fcb_block { + u32 checksum; /* First fingerprint in first byte */ + u32 fingerprint; /* 2nd fingerprint at byte 4 */ + u32 version; /* 3rd fingerprint at byte 8 */ + u8 datasetup; + u8 datahold; + u8 addr_setup; + u8 dsample_time; + + /* These are for application use only and not for ROM. */ + u8 nandtiming; + u8 rea; + u8 rloh; + u8 rhoh; + u32 pagesize; /* 2048 for 2K pages, 4096 for 4K pages */ + u32 oob_pagesize; /* 2112 for 2K pages, 4314 for 4K pages */ + u32 sectors; /* Number of 2K sections per block */ + u32 nr_nand; /* Total Number of NANDs - not used by ROM */ + u32 nr_die; /* Number of separate chips in this NAND */ + u32 celltype; /* MLC or SLC */ + u32 ecc_type; /* Type of ECC, can be one of BCH-0-20 */ + u32 ecc_nr; /* Number of bytes for Block0 - BCH */ + + /* Block size in bytes for all blocks other than Block0 - BCH */ + u32 ecc_size; + u32 ecc_level; /* Ecc level for Block 0 - BCH */ + u32 meta_size; /* Metadata size - BCH */ + /* Number of blocks per page for ROM use - BCH */ + u32 nr_blocks; + u32 ecc_type_sdk; /* Type of ECC, can be one of BCH-0-20 */ + u32 ecc_nr_sdk; /* Number of bytes for Block0 - BCH */ + /* Block size in bytes for all blocks other than Block0 - BCH */ + u32 ecc_size_sdk; + u32 ecc_level_sdk; /* Ecc level for Block 0 - BCH */ + /* Number of blocks per page for SDK use - BCH */ + u32 nr_blocks_sdk; + u32 meta_size_sdk; /* Metadata size - BCH */ + u32 erase_th; /* To set into BCH_MODE register */ + + /* + * 0: normal boot + * 1: to load patch starting next to FCB + */ + u32 bootpatch; + u32 patch_size; /* Size of patch in sectors */ + u32 fw1_start; /* Firmware image starts on this sector */ + u32 fw2_start; /* Secondary FW Image starting Sector */ + u32 fw1_pages; /* Number of sectors in firmware image */ + u32 fw2_pages; /* Number of sector in secondary FW image */ + u32 dbbt_start; /* Page address where dbbt search area begins */ + + /* + * Byte in page data that have manufacturer marked bad block marker, + * this will be swapped with metadata[0] to complete page data. + */ + u32 bb_byte; + + /* + * For BCH ECC sizes other than 8 and 16 the bad block marker does not + * start at 0th bit of bb_byte. This field is used to get to + * the start bit of bad block marker byte with in bb_byte + */ + u32 bb_start_bit; + + /* + * FCB value that gives byte offset for + * bad block marker on physical NAND page + */ + u32 phy_offset; + u32 bchtype; + + u32 readlatency; + u32 predelay; + u32 cedelay; + u32 postdelay; + u32 cmdaddpause; + u32 datapause; + u32 tmspeed; + u32 busytimeout; + + /* the flag to enable (1)/disable(0) bi swap */ + u32 disbbm; + + /* The swap position of main area in spare area */ + u32 spare_offset; + + /* Actual for iMX7 only */ + u32 onfi_sync_enable; + u32 onfi_sync_speed; + u32 onfi_sync_nand_data; + u32 reserved2[6]; + u32 disbbm_search; + u32 disbbm_search_limit; + u32 reserved3[15]; + u32 read_retry_enable; + u32 reserved4[1]; + u32 fill_to_1024[183]; +}; + +#endif /* _IMX_NAND_BCB_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/imximage.cfg b/roms/u-boot/arch/arm/include/asm/mach-imx/imximage.cfg new file mode 100644 index 000000000..8fbc0620c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/imximage.cfg @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * i.MX image header offset values + * Copyright (C) 2013 Marek Vasut + */ + +/* + * NOTE: This file must be kept in sync with tools/imximage.h because + * tools/imximage.c can not cross-include headers from arch/arm/ + * and vice-versa. + */ + +#ifndef __ASM_IMX_COMMON_IMXIMAGE_CFG__ +#define __ASM_IMX_COMMON_IMXIMAGE_CFG__ + +/* Standard image header offset for NAND, SATA, SD, SPI flash. */ +#define FLASH_OFFSET_STANDARD 0x400 +/* Specific image header offset for booting from OneNAND. */ +#define FLASH_OFFSET_ONENAND 0x100 +/* Specific image header offset for booting from memory-mapped NOR. */ +#define FLASH_OFFSET_NOR 0x1000 + +#endif /* __ASM_IMX_COMMON_IMXIMAGE_CFG__ */ diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/iomux-v3.h b/roms/u-boot/arch/arm/include/asm/mach-imx/iomux-v3.h new file mode 100644 index 000000000..1de709335 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -0,0 +1,301 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Based on Linux i.MX iomux-v3.h file: + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * + * + * Copyright (C) 2011 Freescale Semiconductor, Inc. + */ + +#ifndef __MACH_IOMUX_V3_H__ +#define __MACH_IOMUX_V3_H__ + +#include + +/* + * build IOMUX_PAD structure + * + * This iomux scheme is based around pads, which are the physical balls + * on the processor. + * + * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls + * things like driving strength and pullup/pulldown. + * - Each pad can have but not necessarily does have an output routing register + * (IOMUXC_SW_MUX_CTL_PAD_x). + * - Each pad can have but not necessarily does have an input routing register + * (IOMUXC_x_SELECT_INPUT) + * + * The three register sets do not have a fixed offset to each other, + * hence we order this table by pad control registers (which all pads + * have) and put the optional i/o routing registers into additional + * fields. + * + * The naming convention for the pad modes is SOC_PAD___ + * If or refers to a GPIO, it is named GPIO__ + * + * IOMUX/PAD Bit field definitions + * + * MUX_CTRL_OFS: 0..11 (12) + * PAD_CTRL_OFS: 12..23 (12) + * SEL_INPUT_OFS: 24..35 (12) + * MUX_MODE + SION + LPSR: 36..41 (6) + * PAD_CTRL + NO_PAD_CTRL: 42..59 (18) + * SEL_INP: 60..63 (4) +*/ + +typedef u64 iomux_v3_cfg_t; + +#define MUX_CTRL_OFS_SHIFT 0 +#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT) +#define MUX_PAD_CTRL_OFS_SHIFT 12 +#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \ + MUX_PAD_CTRL_OFS_SHIFT) +#define MUX_SEL_INPUT_OFS_SHIFT 24 +#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \ + MUX_SEL_INPUT_OFS_SHIFT) + +#define MUX_MODE_SHIFT 36 +#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x3f << MUX_MODE_SHIFT) +#define MUX_PAD_CTRL_SHIFT 42 +#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT) +#define MUX_SEL_INPUT_SHIFT 60 +#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) + +#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \ + MUX_MODE_SHIFT) +#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) + +#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ + sel_input, pad_ctrl) \ + (((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ + ((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \ + ((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \ + ((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ + ((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \ + ((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT)) + +#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \ + MUX_PAD_CTRL(pad)) + +#define __NA_ 0x000 +#define NO_MUX_I 0 +#define NO_PAD_I 0 + +#define NO_PAD_CTRL (1 << 17) + +#define IOMUX_CONFIG_LPSR 0x20 +#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ + MUX_MODE_SHIFT) +#ifdef CONFIG_IMX8M +#define PAD_CTL_DSE0 (0x0 << 0) +#define PAD_CTL_DSE1 (0x1 << 0) +#define PAD_CTL_DSE2 (0x2 << 0) +#define PAD_CTL_DSE3 (0x3 << 0) +#define PAD_CTL_DSE4 (0x4 << 0) +#define PAD_CTL_DSE5 (0x5 << 0) +#define PAD_CTL_DSE6 (0x6 << 0) +#define PAD_CTL_DSE7 (0x7 << 0) + +#define PAD_CTL_FSEL0 (0x0 << 3) +#define PAD_CTL_FSEL1 (0x1 << 3) +#define PAD_CTL_FSEL2 (0x2 << 3) +#define PAD_CTL_FSEL3 (0x3 << 3) + +#define PAD_CTL_ODE (0x1 << 5) +#define PAD_CTL_PUE (0x1 << 6) +#define PAD_CTL_HYS (0x1 << 7) +#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) +#define PAD_CTL_PE (0x1 << 8) +#else +#define PAD_CTL_LVTTL (0x1 << 8) +#endif + +#elif defined CONFIG_MX7 + +#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000 + +#define PAD_CTL_DSE_1P8V_140OHM (0x0<<0) +#define PAD_CTL_DSE_1P8V_35OHM (0x1<<0) +#define PAD_CTL_DSE_1P8V_70OHM (0x2<<0) +#define PAD_CTL_DSE_1P8V_23OHM (0x3<<0) + +#define PAD_CTL_DSE_3P3V_196OHM (0x0<<0) +#define PAD_CTL_DSE_3P3V_49OHM (0x1<<0) +#define PAD_CTL_DSE_3P3V_98OHM (0x2<<0) +#define PAD_CTL_DSE_3P3V_32OHM (0x3<<0) + +#define PAD_CTL_SRE_FAST (0 << 2) +#define PAD_CTL_SRE_SLOW (0x1 << 2) + +#define PAD_CTL_HYS (0x1 << 3) +#define PAD_CTL_PUE (0x1 << 4) + +#define PAD_CTL_PUS_PD100KOHM ((0x0 << 5) | PAD_CTL_PUE) +#define PAD_CTL_PUS_PU5KOHM ((0x1 << 5) | PAD_CTL_PUE) +#define PAD_CTL_PUS_PU47KOHM ((0x2 << 5) | PAD_CTL_PUE) +#define PAD_CTL_PUS_PU100KOHM ((0x3 << 5) | PAD_CTL_PUE) + +#else + +#ifdef CONFIG_MX6 + +#define PAD_CTL_HYS (1 << 16) + +#define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE) +#define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE) +#define PAD_CTL_PUS_100K_UP (2 << 14 | PAD_CTL_PUE) +#define PAD_CTL_PUS_22K_UP (3 << 14 | PAD_CTL_PUE) +#define PAD_CTL_PUE (1 << 13 | PAD_CTL_PKE) +#define PAD_CTL_PKE (1 << 12) + +#define PAD_CTL_ODE (1 << 11) + +#if defined(CONFIG_MX6SL) +#define PAD_CTL_SPEED_LOW (1 << 6) +#else +#define PAD_CTL_SPEED_LOW (0 << 6) +#endif +#define PAD_CTL_SPEED_MED (2 << 6) +#define PAD_CTL_SPEED_HIGH (3 << 6) + +#define PAD_CTL_DSE_DISABLE (0 << 3) +#define PAD_CTL_DSE_240ohm (1 << 3) +#define PAD_CTL_DSE_120ohm (2 << 3) +#define PAD_CTL_DSE_80ohm (3 << 3) +#define PAD_CTL_DSE_60ohm (4 << 3) +#define PAD_CTL_DSE_48ohm (5 << 3) +#define PAD_CTL_DSE_40ohm (6 << 3) +#define PAD_CTL_DSE_34ohm (7 << 3) + +#define PAD_CTL_DSE_260ohm (1 << 3) +#define PAD_CTL_DSE_130ohm (2 << 3) +#define PAD_CTL_DSE_88ohm (3 << 3) +#define PAD_CTL_DSE_65ohm (4 << 3) +#define PAD_CTL_DSE_52ohm (5 << 3) +#define PAD_CTL_DSE_43ohm (6 << 3) +#define PAD_CTL_DSE_37ohm (7 << 3) + +/* i.MX6SL/SLL */ +#define PAD_CTL_LVE (1 << 1) +#define PAD_CTL_LVE_BIT (1 << 22) + +/* i.MX6SLL */ +#define PAD_CTL_IPD_BIT (1 << 27) + +#elif defined(CONFIG_VF610) + +#define PAD_MUX_MODE_SHIFT 20 + +#define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16) + +#define PAD_CTL_SPEED_MED (1 << 12) +#define PAD_CTL_SPEED_HIGH (3 << 12) + +#define PAD_CTL_SRE (1 << 11) + +#define PAD_CTL_ODE (1 << 10) + +#define PAD_CTL_DSE_150ohm (1 << 6) +#define PAD_CTL_DSE_75ohm (2 << 6) +#define PAD_CTL_DSE_50ohm (3 << 6) +#define PAD_CTL_DSE_37ohm (4 << 6) +#define PAD_CTL_DSE_30ohm (5 << 6) +#define PAD_CTL_DSE_25ohm (6 << 6) +#define PAD_CTL_DSE_20ohm (7 << 6) + +#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PKE (1 << 3) +#define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE) + +#define PAD_CTL_OBE_IBE_ENABLE (3 << 0) +#define PAD_CTL_OBE_ENABLE (1 << 1) +#define PAD_CTL_IBE_ENABLE (1 << 0) + +#else + +#define PAD_CTL_DVS (1 << 13) +#define PAD_CTL_INPUT_DDR (1 << 9) +#define PAD_CTL_HYS (1 << 8) + +#define PAD_CTL_PKE (1 << 7) +#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE) +#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) + +#define PAD_CTL_ODE (1 << 3) + +#define PAD_CTL_DSE_LOW (0 << 1) +#define PAD_CTL_DSE_MED (1 << 1) +#define PAD_CTL_DSE_HIGH (2 << 1) +#define PAD_CTL_DSE_MAX (3 << 1) + +#endif + +#define PAD_CTL_SRE_SLOW (0 << 0) +#define PAD_CTL_SRE_FAST (1 << 0) + +#endif + +#define IOMUX_CONFIG_SION 0x10 + +#define GPIO_PIN_MASK 0x1f +#define GPIO_PORT_SHIFT 5 +#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) +#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) +#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) +#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) +#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) +#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) +#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) + +void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad); +void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, + unsigned count); +/* +* Set bits for general purpose registers +*/ +void imx_iomux_set_gpr_register(int group, int start_bit, + int num_bits, int value); +#ifdef CONFIG_IOMUX_SHARE_CONF_REG +void imx_iomux_gpio_set_direction(unsigned int gpio, + unsigned int direction); +void imx_iomux_gpio_get_function(unsigned int gpio, + u32 *gpio_state); +#endif + +/* macros for declaring and using pinmux array */ +#if defined(CONFIG_MX6QDL) +#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x) +#define SETUP_IOMUX_PAD(def) \ +if (is_mx6dq() || is_mx6dqp()) { \ + imx_iomux_v3_setup_pad(MX6Q_##def); \ +} else { \ + imx_iomux_v3_setup_pad(MX6DL_##def); \ +} +#define SETUP_IOMUX_PADS(x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2) +#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) +#define IOMUX_PADS(x) MX6Q_##x +#define SETUP_IOMUX_PAD(def) \ + imx_iomux_v3_setup_pad(MX6Q_##def); +#define SETUP_IOMUX_PADS(x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) +#elif defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) +#define IOMUX_PADS(x) MX6_##x +#define SETUP_IOMUX_PAD(def) \ + imx_iomux_v3_setup_pad(MX6_##def); +#define SETUP_IOMUX_PADS(x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) +#else +#define IOMUX_PADS(x) MX6DL_##x +#define SETUP_IOMUX_PAD(def) \ + imx_iomux_v3_setup_pad(MX6DL_##def); +#define SETUP_IOMUX_PADS(x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) +#endif + +#endif /* __MACH_IOMUX_V3_H__*/ diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/module_fuse.h b/roms/u-boot/arch/arm/include/asm/mach-imx/module_fuse.h new file mode 100644 index 000000000..a46fc3f1f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/module_fuse.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __MODULE_FUSE_H__ +#define __MODULE_FUSE_H__ + +enum fuse_module_type { + MODULE_TSC, + MODULE_ADC1, + MODULE_ADC2, + MODULE_SIM1, + MODULE_SIM2, + MODULE_FLEXCAN1, + MODULE_FLEXCAN2, + MODULE_SPDIF, + MODULE_EIM, + MODULE_SD1, + MODULE_SD2, + MODULE_SD3, + MODULE_SD4, + MODULE_QSPI1, + MODULE_QSPI2, + MODULE_GPMI, + MODULE_APBHDMA, + MODULE_LCDIF, + MODULE_PXP, + MODULE_CSI, + MODULE_ENET1, + MODULE_ENET2, + MODULE_CAAM, + MODULE_USB_OTG1, + MODULE_USB_OTG2, + MODULE_SAI2, + MODULE_SAI3, + MODULE_BEE, + MODULE_UART1, + MODULE_UART2, + MODULE_UART3, + MODULE_UART4, + MODULE_UART5, + MODULE_UART6, + MODULE_UART7, + MODULE_UART8, + MODULE_PWM5, + MODULE_PWM6, + MODULE_PWM7, + MODULE_PWM8, + MODULE_ECSPI1, + MODULE_ECSPI2, + MODULE_ECSPI3, + MODULE_ECSPI4, + MODULE_ECSPI5, + MODULE_I2C1, + MODULE_I2C2, + MODULE_I2C3, + MODULE_I2C4, + MODULE_GPT1, + MODULE_GPT2, + MODULE_EPIT1, + MODULE_EPIT2, + MODULE_EPDC, + MODULE_ESAI, + MODULE_DCP, + MODULE_DCP_CRYPTO, +}; + +struct fuse_entry_desc { + enum fuse_module_type module; + const char *node_path; + u32 fuse_word_offset; + u32 fuse_bit_offset; + u32 status; +}; + +#if !CONFIG_IS_ENABLED(IMX_MODULE_FUSE) +static inline u32 check_module_fused(enum fuse_module_type module) +{ + return 0; +}; + +static inline u32 esdhc_fused(ulong base_addr) +{ + return 0; +}; + +static inline u32 ecspi_fused(ulong base_addr) +{ + return 0; +}; + +static inline u32 uart_fused(ulong base_addr) +{ + return 0; +}; + +static inline u32 usb_fused(ulong base_addr) +{ + return 0; +}; + +static inline u32 qspi_fused(ulong base_addr) +{ + return 0; +}; + +static inline u32 i2c_fused(ulong base_addr) +{ + return 0; +}; + +static inline u32 enet_fused(ulong base_addr) +{ + return 0; +}; +#else +u32 check_module_fused(enum fuse_module_type module); +u32 esdhc_fused(ulong base_addr); +u32 ecspi_fused(ulong base_addr); +u32 uart_fused(ulong base_addr); +u32 usb_fused(ulong base_addr); +u32 qspi_fused(ulong base_addr); +u32 i2c_fused(ulong base_addr); +u32 enet_fused(ulong base_addr); +#endif +#endif /* __MODULE_FUSE_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/mx5_video.h b/roms/u-boot/arch/arm/include/asm/mach-imx/mx5_video.h new file mode 100644 index 000000000..dc6aa00c8 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/mx5_video.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 + * Anatolij Gustschin, DENX Software Engineering, + */ +#ifndef __MX5_VIDEO_H +#define __MX5_VIDEO_H + +#ifdef CONFIG_VIDEO +void lcd_enable(void); +void setup_iomux_lcd(void); +#else +static inline void lcd_enable(void) { } +static inline void setup_iomux_lcd(void) { } +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/mxc_i2c.h b/roms/u-boot/arch/arm/include/asm/mach-imx/mxc_i2c.h new file mode 100644 index 000000000..e8b330f33 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/mxc_i2c.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ +#ifndef __ASM_ARCH_MXC_MXC_I2C_H__ +#define __ASM_ARCH_MXC_MXC_I2C_H__ +#include +#include +#if CONFIG_IS_ENABLED(CLK) +#include +#endif + +struct i2c_pin_ctrl { + iomux_v3_cfg_t i2c_mode; + iomux_v3_cfg_t gpio_mode; + unsigned char gp; + unsigned char spare; +}; + +struct i2c_pads_info { + struct i2c_pin_ctrl scl; + struct i2c_pin_ctrl sda; +}; + +/* + * Information about i2c controller + * struct mxc_i2c_bus - information about the i2c[x] bus + * @index: i2c bus index + * @base: Address of I2C bus controller + * @driver_data: Flags for different platforms, such as I2C_QUIRK_FLAG. + * @speed: Speed of I2C bus + * @pads_info: pinctrl info for this i2c bus, will be used when pinctrl is ok. + * The following two is only to be compatible with non-DM part. + * @idle_bus_fn: function to force bus idle + * @idle_bus_data: parameter for idle_bus_fun + * For DM: + * bus: The device structure for i2c bus controller + * scl-gpio: specify the gpio related to SCL pin + * sda-gpio: specify the gpio related to SDA pin + */ +struct mxc_i2c_bus { + /* + * board file can use this index to locate which i2c_pads_info is for + * i2c_idle_bus. When pinmux is implement, this entry can be + * discarded. Here we do not use dev_seq(dev), because we do not want to + * export device to board file. + */ + int index; + ulong base; + ulong driver_data; + int speed; + struct i2c_pads_info *pads_info; +#if CONFIG_IS_ENABLED(CLK) + struct clk per_clk; +#endif +#if !CONFIG_IS_ENABLED(DM_I2C) + int (*idle_bus_fn)(void *p); + void *idle_bus_data; +#else + struct udevice *bus; + /* Use gpio to force bus idle when bus state is abnormal */ + struct gpio_desc scl_gpio; + struct gpio_desc sda_gpio; +#endif +}; + +#if defined(CONFIG_MX6QDL) +#define I2C_PADS(name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp) \ + struct i2c_pads_info mx6q_##name = { \ + .scl = { \ + .i2c_mode = MX6Q_##scl_i2c, \ + .gpio_mode = MX6Q_##scl_gpio, \ + .gp = scl_gp, \ + }, \ + .sda = { \ + .i2c_mode = MX6Q_##sda_i2c, \ + .gpio_mode = MX6Q_##sda_gpio, \ + .gp = sda_gp, \ + } \ + }; \ + struct i2c_pads_info mx6s_##name = { \ + .scl = { \ + .i2c_mode = MX6DL_##scl_i2c, \ + .gpio_mode = MX6DL_##scl_gpio, \ + .gp = scl_gp, \ + }, \ + .sda = { \ + .i2c_mode = MX6DL_##sda_i2c, \ + .gpio_mode = MX6DL_##sda_gpio, \ + .gp = sda_gp, \ + } \ + }; + + +#define I2C_PADS_INFO(name) \ + (is_mx6dq() || is_mx6dqp()) ? &mx6q_##name : &mx6s_##name +#endif + +int setup_i2c(unsigned i2c_index, int speed, int slave_addr, + struct i2c_pads_info *p); +void bus_i2c_init(int index, int speed, int slave_addr, + int (*idle_bus_fn)(void *p), void *p); +int force_idle_bus(void *priv); +int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/rdc-sema.h b/roms/u-boot/arch/arm/include/asm/mach-imx/rdc-sema.h new file mode 100644 index 000000000..70d6a76a9 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/rdc-sema.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#ifndef __RDC_SEMA_H__ +#define __RDC_SEMA_H__ + +/* + * rdc_peri_cfg_t and rdc_ma_cft_t use the same layout. + * + * [ 23 22 | 21 20 | 19 18 | 17 16 ] | [ 15 - 8 ] | [ 7 - 0 ] + * d3 d2 d1 d0 | master id | peri id + * d[x] means domain[x], x can be [3 - 0]. + */ +typedef u32 rdc_peri_cfg_t; +typedef u32 rdc_ma_cfg_t; + +#define RDC_PERI_SHIFT 0 +#define RDC_PERI_MASK 0xFF + +#define RDC_DOMAIN_SHIFT_BASE 16 +#define RDC_DOMAIN_MASK 0xFF0000 +#define RDC_DOMAIN_SHIFT(x) (RDC_DOMAIN_SHIFT_BASE + ((x << 1))) +#define RDC_DOMAIN(x) ((rdc_peri_cfg_t)(0x3 << RDC_DOMAIN_SHIFT(x))) + +#define RDC_MASTER_SHIFT 8 +#define RDC_MASTER_MASK 0xFF00 +#define RDC_MASTER_CFG(master_id, domain_id) (rdc_ma_cfg_t)((master_id << 8) | \ + (domain_id << RDC_DOMAIN_SHIFT_BASE)) + +/* The Following macro definitions are common to i.MX6SX and i.MX7D */ +#define SEMA_GATES_NUM 64 + +#define RDC_MDA_DID_SHIFT 0 +#define RDC_MDA_DID_MASK (0x3 << RDC_MDA_DID_SHIFT) +#define RDC_MDA_LCK_SHIFT 31 +#define RDC_MDA_LCK_MASK (0x1 << RDC_MDA_LCK_SHIFT) + +#define RDC_PDAP_DW_SHIFT(domain) ((domain) << 1) +#define RDC_PDAP_DR_SHIFT(domain) (1 + RDC_PDAP_DW_SHIFT(domain)) +#define RDC_PDAP_DW_MASK(domain) (1 << RDC_PDAP_DW_SHIFT(domain)) +#define RDC_PDAP_DR_MASK(domain) (1 << RDC_PDAP_DR_SHIFT(domain)) +#define RDC_PDAP_DRW_MASK(domain) (RDC_PDAP_DW_MASK(domain) | \ + RDC_PDAP_DR_MASK(domain)) + +#define RDC_PDAP_SREQ_SHIFT 30 +#define RDC_PDAP_SREQ_MASK (0x1 << RDC_PDAP_SREQ_SHIFT) +#define RDC_PDAP_LCK_SHIFT 31 +#define RDC_PDAP_LCK_MASK (0x1 << RDC_PDAP_LCK_SHIFT) + +#define RDC_MRSA_SADR_SHIFT 7 +#define RDC_MRSA_SADR_MASK (0x1ffffff << RDC_MRSA_SADR_SHIFT) + +#define RDC_MREA_EADR_SHIFT 7 +#define RDC_MREA_EADR_MASK (0x1ffffff << RDC_MREA_EADR_SHIFT) + +#define RDC_MRC_DW_SHIFT(domain) (domain) +#define RDC_MRC_DR_SHIFT(domain) (1 + RDC_MRC_DW_SHIFT(domain)) +#define RDC_MRC_DW_MASK(domain) (1 << RDC_MRC_DW_SHIFT(domain)) +#define RDC_MRC_DR_MASK(domain) (1 << RDC_MRC_DR_SHIFT(domain)) +#define RDC_MRC_DRW_MASK(domain) (RDC_MRC_DW_MASK(domain) | \ + RDC_MRC_DR_MASK(domain)) +#define RDC_MRC_ENA_SHIFT 30 +#define RDC_MRC_ENA_MASK (0x1 << RDC_MRC_ENA_SHIFT) +#define RDC_MRC_LCK_SHIFT 31 +#define RDC_MRC_LCK_MASK (0x1 << RDC_MRC_LCK_SHIFT) + +#define RDC_MRVS_VDID_SHIFT 0 +#define RDC_MRVS_VDID_MASK (0x3 << RDC_MRVS_VDID_SHIFT) +#define RDC_MRVS_AD_SHIFT 4 +#define RDC_MRVS_AD_MASK (0x1 << RDC_MRVS_AD_SHIFT) +#define RDC_MRVS_VADDR_SHIFT 5 +#define RDC_MRVS_VADDR_MASK (0x7ffffff << RDC_MRVS_VADDR_SHIFT) + +#define RDC_SEMA_GATE_GTFSM_SHIFT 0 +#define RDC_SEMA_GATE_GTFSM_MASK (0xf << RDC_SEMA_GATE_GTFSM_SHIFT) +#define RDC_SEMA_GATE_LDOM_SHIFT 5 +#define RDC_SEMA_GATE_LDOM_MASK (0x3 << RDC_SEMA_GATE_LDOM_SHIFT) + +#define RDC_SEMA_RSTGT_RSTGDP_SHIFT 0 +#define RDC_SEMA_RSTGT_RSTGDP_MASK (0xff << RDC_SEMA_RSTGT_RSTGDP_SHIFT) +#define RDC_SEMA_RSTGT_RSTGSM_SHIFT 2 +#define RDC_SEMA_RSTGT_RSTGSM_MASK (0x3 << RDC_SEMA_RSTGT_RSTGSM_SHIFT) +#define RDC_SEMA_RSTGT_RSTGMS_SHIFT 4 +#define RDC_SEMA_RSTGT_RSTGMS_MASK (0xf << RDC_SEMA_RSTGT_RSTGMS_SHIFT) +#define RDC_SEMA_RSTGT_RSTGTN_SHIFT 8 +#define RDC_SEMA_RSTGT_RSTGTN_MASK (0xff << RDC_SEMA_RSTGT_RSTGTN_SHIFT) + +int imx_rdc_check_permission(int per_id, int dom_id); +int imx_rdc_sema_lock(int per_id); +int imx_rdc_sema_unlock(int per_id); +int imx_rdc_setup_peri(rdc_peri_cfg_t p); +int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list, + unsigned count); +int imx_rdc_setup_ma(rdc_ma_cfg_t p); +int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count); + +#endif /* __RDC_SEMA_H__*/ diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/regs-apbh.h b/roms/u-boot/arch/arm/include/asm/mach-imx/regs-apbh.h new file mode 100644 index 000000000..94c330c7f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/regs-apbh.h @@ -0,0 +1,587 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX28 APBH Register Definitions + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2020 NXP + */ + +#ifndef __REGS_APBH_H__ +#define __REGS_APBH_H__ + +#include + +#ifndef __ASSEMBLY__ + +#if defined(CONFIG_MX23) +struct mxs_apbh_regs { + mxs_reg_32(hw_apbh_ctrl0) + mxs_reg_32(hw_apbh_ctrl1) + mxs_reg_32(hw_apbh_ctrl2) + mxs_reg_32(hw_apbh_channel_ctrl) + + union { + struct { + mxs_reg_32(hw_apbh_ch_curcmdar) + mxs_reg_32(hw_apbh_ch_nxtcmdar) + mxs_reg_32(hw_apbh_ch_cmd) + mxs_reg_32(hw_apbh_ch_bar) + mxs_reg_32(hw_apbh_ch_sema) + mxs_reg_32(hw_apbh_ch_debug1) + mxs_reg_32(hw_apbh_ch_debug2) + } ch[8]; + struct { + mxs_reg_32(hw_apbh_ch0_curcmdar) + mxs_reg_32(hw_apbh_ch0_nxtcmdar) + mxs_reg_32(hw_apbh_ch0_cmd) + mxs_reg_32(hw_apbh_ch0_bar) + mxs_reg_32(hw_apbh_ch0_sema) + mxs_reg_32(hw_apbh_ch0_debug1) + mxs_reg_32(hw_apbh_ch0_debug2) + mxs_reg_32(hw_apbh_ch1_curcmdar) + mxs_reg_32(hw_apbh_ch1_nxtcmdar) + mxs_reg_32(hw_apbh_ch1_cmd) + mxs_reg_32(hw_apbh_ch1_bar) + mxs_reg_32(hw_apbh_ch1_sema) + mxs_reg_32(hw_apbh_ch1_debug1) + mxs_reg_32(hw_apbh_ch1_debug2) + mxs_reg_32(hw_apbh_ch2_curcmdar) + mxs_reg_32(hw_apbh_ch2_nxtcmdar) + mxs_reg_32(hw_apbh_ch2_cmd) + mxs_reg_32(hw_apbh_ch2_bar) + mxs_reg_32(hw_apbh_ch2_sema) + mxs_reg_32(hw_apbh_ch2_debug1) + mxs_reg_32(hw_apbh_ch2_debug2) + mxs_reg_32(hw_apbh_ch3_curcmdar) + mxs_reg_32(hw_apbh_ch3_nxtcmdar) + mxs_reg_32(hw_apbh_ch3_cmd) + mxs_reg_32(hw_apbh_ch3_bar) + mxs_reg_32(hw_apbh_ch3_sema) + mxs_reg_32(hw_apbh_ch3_debug1) + mxs_reg_32(hw_apbh_ch3_debug2) + mxs_reg_32(hw_apbh_ch4_curcmdar) + mxs_reg_32(hw_apbh_ch4_nxtcmdar) + mxs_reg_32(hw_apbh_ch4_cmd) + mxs_reg_32(hw_apbh_ch4_bar) + mxs_reg_32(hw_apbh_ch4_sema) + mxs_reg_32(hw_apbh_ch4_debug1) + mxs_reg_32(hw_apbh_ch4_debug2) + mxs_reg_32(hw_apbh_ch5_curcmdar) + mxs_reg_32(hw_apbh_ch5_nxtcmdar) + mxs_reg_32(hw_apbh_ch5_cmd) + mxs_reg_32(hw_apbh_ch5_bar) + mxs_reg_32(hw_apbh_ch5_sema) + mxs_reg_32(hw_apbh_ch5_debug1) + mxs_reg_32(hw_apbh_ch5_debug2) + mxs_reg_32(hw_apbh_ch6_curcmdar) + mxs_reg_32(hw_apbh_ch6_nxtcmdar) + mxs_reg_32(hw_apbh_ch6_cmd) + mxs_reg_32(hw_apbh_ch6_bar) + mxs_reg_32(hw_apbh_ch6_sema) + mxs_reg_32(hw_apbh_ch6_debug1) + mxs_reg_32(hw_apbh_ch6_debug2) + mxs_reg_32(hw_apbh_ch7_curcmdar) + mxs_reg_32(hw_apbh_ch7_nxtcmdar) + mxs_reg_32(hw_apbh_ch7_cmd) + mxs_reg_32(hw_apbh_ch7_bar) + mxs_reg_32(hw_apbh_ch7_sema) + mxs_reg_32(hw_apbh_ch7_debug1) + mxs_reg_32(hw_apbh_ch7_debug2) + }; + }; + mxs_reg_32(hw_apbh_version) +}; + +#else +struct mxs_apbh_regs { + mxs_reg_32(hw_apbh_ctrl0) + mxs_reg_32(hw_apbh_ctrl1) + mxs_reg_32(hw_apbh_ctrl2) + mxs_reg_32(hw_apbh_channel_ctrl) + mxs_reg_32(hw_apbh_devsel) + mxs_reg_32(hw_apbh_dma_burst_size) + mxs_reg_32(hw_apbh_debug) + + uint32_t reserved[36]; + + union { + struct { + mxs_reg_32(hw_apbh_ch_curcmdar) + mxs_reg_32(hw_apbh_ch_nxtcmdar) + mxs_reg_32(hw_apbh_ch_cmd) + mxs_reg_32(hw_apbh_ch_bar) + mxs_reg_32(hw_apbh_ch_sema) + mxs_reg_32(hw_apbh_ch_debug1) + mxs_reg_32(hw_apbh_ch_debug2) + } ch[16]; + struct { + mxs_reg_32(hw_apbh_ch0_curcmdar) + mxs_reg_32(hw_apbh_ch0_nxtcmdar) + mxs_reg_32(hw_apbh_ch0_cmd) + mxs_reg_32(hw_apbh_ch0_bar) + mxs_reg_32(hw_apbh_ch0_sema) + mxs_reg_32(hw_apbh_ch0_debug1) + mxs_reg_32(hw_apbh_ch0_debug2) + mxs_reg_32(hw_apbh_ch1_curcmdar) + mxs_reg_32(hw_apbh_ch1_nxtcmdar) + mxs_reg_32(hw_apbh_ch1_cmd) + mxs_reg_32(hw_apbh_ch1_bar) + mxs_reg_32(hw_apbh_ch1_sema) + mxs_reg_32(hw_apbh_ch1_debug1) + mxs_reg_32(hw_apbh_ch1_debug2) + mxs_reg_32(hw_apbh_ch2_curcmdar) + mxs_reg_32(hw_apbh_ch2_nxtcmdar) + mxs_reg_32(hw_apbh_ch2_cmd) + mxs_reg_32(hw_apbh_ch2_bar) + mxs_reg_32(hw_apbh_ch2_sema) + mxs_reg_32(hw_apbh_ch2_debug1) + mxs_reg_32(hw_apbh_ch2_debug2) + mxs_reg_32(hw_apbh_ch3_curcmdar) + mxs_reg_32(hw_apbh_ch3_nxtcmdar) + mxs_reg_32(hw_apbh_ch3_cmd) + mxs_reg_32(hw_apbh_ch3_bar) + mxs_reg_32(hw_apbh_ch3_sema) + mxs_reg_32(hw_apbh_ch3_debug1) + mxs_reg_32(hw_apbh_ch3_debug2) + mxs_reg_32(hw_apbh_ch4_curcmdar) + mxs_reg_32(hw_apbh_ch4_nxtcmdar) + mxs_reg_32(hw_apbh_ch4_cmd) + mxs_reg_32(hw_apbh_ch4_bar) + mxs_reg_32(hw_apbh_ch4_sema) + mxs_reg_32(hw_apbh_ch4_debug1) + mxs_reg_32(hw_apbh_ch4_debug2) + mxs_reg_32(hw_apbh_ch5_curcmdar) + mxs_reg_32(hw_apbh_ch5_nxtcmdar) + mxs_reg_32(hw_apbh_ch5_cmd) + mxs_reg_32(hw_apbh_ch5_bar) + mxs_reg_32(hw_apbh_ch5_sema) + mxs_reg_32(hw_apbh_ch5_debug1) + mxs_reg_32(hw_apbh_ch5_debug2) + mxs_reg_32(hw_apbh_ch6_curcmdar) + mxs_reg_32(hw_apbh_ch6_nxtcmdar) + mxs_reg_32(hw_apbh_ch6_cmd) + mxs_reg_32(hw_apbh_ch6_bar) + mxs_reg_32(hw_apbh_ch6_sema) + mxs_reg_32(hw_apbh_ch6_debug1) + mxs_reg_32(hw_apbh_ch6_debug2) + mxs_reg_32(hw_apbh_ch7_curcmdar) + mxs_reg_32(hw_apbh_ch7_nxtcmdar) + mxs_reg_32(hw_apbh_ch7_cmd) + mxs_reg_32(hw_apbh_ch7_bar) + mxs_reg_32(hw_apbh_ch7_sema) + mxs_reg_32(hw_apbh_ch7_debug1) + mxs_reg_32(hw_apbh_ch7_debug2) + mxs_reg_32(hw_apbh_ch8_curcmdar) + mxs_reg_32(hw_apbh_ch8_nxtcmdar) + mxs_reg_32(hw_apbh_ch8_cmd) + mxs_reg_32(hw_apbh_ch8_bar) + mxs_reg_32(hw_apbh_ch8_sema) + mxs_reg_32(hw_apbh_ch8_debug1) + mxs_reg_32(hw_apbh_ch8_debug2) + mxs_reg_32(hw_apbh_ch9_curcmdar) + mxs_reg_32(hw_apbh_ch9_nxtcmdar) + mxs_reg_32(hw_apbh_ch9_cmd) + mxs_reg_32(hw_apbh_ch9_bar) + mxs_reg_32(hw_apbh_ch9_sema) + mxs_reg_32(hw_apbh_ch9_debug1) + mxs_reg_32(hw_apbh_ch9_debug2) + mxs_reg_32(hw_apbh_ch10_curcmdar) + mxs_reg_32(hw_apbh_ch10_nxtcmdar) + mxs_reg_32(hw_apbh_ch10_cmd) + mxs_reg_32(hw_apbh_ch10_bar) + mxs_reg_32(hw_apbh_ch10_sema) + mxs_reg_32(hw_apbh_ch10_debug1) + mxs_reg_32(hw_apbh_ch10_debug2) + mxs_reg_32(hw_apbh_ch11_curcmdar) + mxs_reg_32(hw_apbh_ch11_nxtcmdar) + mxs_reg_32(hw_apbh_ch11_cmd) + mxs_reg_32(hw_apbh_ch11_bar) + mxs_reg_32(hw_apbh_ch11_sema) + mxs_reg_32(hw_apbh_ch11_debug1) + mxs_reg_32(hw_apbh_ch11_debug2) + mxs_reg_32(hw_apbh_ch12_curcmdar) + mxs_reg_32(hw_apbh_ch12_nxtcmdar) + mxs_reg_32(hw_apbh_ch12_cmd) + mxs_reg_32(hw_apbh_ch12_bar) + mxs_reg_32(hw_apbh_ch12_sema) + mxs_reg_32(hw_apbh_ch12_debug1) + mxs_reg_32(hw_apbh_ch12_debug2) + mxs_reg_32(hw_apbh_ch13_curcmdar) + mxs_reg_32(hw_apbh_ch13_nxtcmdar) + mxs_reg_32(hw_apbh_ch13_cmd) + mxs_reg_32(hw_apbh_ch13_bar) + mxs_reg_32(hw_apbh_ch13_sema) + mxs_reg_32(hw_apbh_ch13_debug1) + mxs_reg_32(hw_apbh_ch13_debug2) + mxs_reg_32(hw_apbh_ch14_curcmdar) + mxs_reg_32(hw_apbh_ch14_nxtcmdar) + mxs_reg_32(hw_apbh_ch14_cmd) + mxs_reg_32(hw_apbh_ch14_bar) + mxs_reg_32(hw_apbh_ch14_sema) + mxs_reg_32(hw_apbh_ch14_debug1) + mxs_reg_32(hw_apbh_ch14_debug2) + mxs_reg_32(hw_apbh_ch15_curcmdar) + mxs_reg_32(hw_apbh_ch15_nxtcmdar) + mxs_reg_32(hw_apbh_ch15_cmd) + mxs_reg_32(hw_apbh_ch15_bar) + mxs_reg_32(hw_apbh_ch15_sema) + mxs_reg_32(hw_apbh_ch15_debug1) + mxs_reg_32(hw_apbh_ch15_debug2) + }; + }; + mxs_reg_32(hw_apbh_version) +}; +#endif + +#endif + +#define APBH_CTRL0_SFTRST (1 << 31) +#define APBH_CTRL0_CLKGATE (1 << 30) +#define APBH_CTRL0_AHB_BURST8_EN (1 << 29) +#define APBH_CTRL0_APB_BURST_EN (1 << 28) +#if defined(CONFIG_MX23) +#define APBH_CTRL0_RSVD0_MASK (0xf << 24) +#define APBH_CTRL0_RSVD0_OFFSET 24 +#define APBH_CTRL0_RESET_CHANNEL_MASK (0xff << 16) +#define APBH_CTRL0_RESET_CHANNEL_OFFSET 16 +#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xff << 8) +#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 8 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x02 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x04 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x10 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x20 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x40 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x80 +#elif defined(CONFIG_MX28) +#define APBH_CTRL0_RSVD0_MASK (0xfff << 16) +#define APBH_CTRL0_RSVD0_OFFSET 16 +#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff +#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x0001 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x0002 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP2 0x0004 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP3 0x0008 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0010 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0020 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0040 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0080 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0100 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0200 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0400 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800 +#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000 +#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000 +#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)) +#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0004 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0008 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0010 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0020 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0040 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0080 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP 0x0100 +#endif + +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16) +#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16 +#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0) + +#define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31) +#define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30) +#define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29) +#define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28) +#define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27) +#define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26) +#define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25) +#define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24) +#define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23) +#define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22) +#define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21) +#define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20) +#define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19) +#define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18) +#define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17) +#define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16) +#define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15) +#define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14) +#define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13) +#define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12) +#define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11) +#define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10) +#define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9) +#define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8) +#define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7) +#define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6) +#define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5) +#define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4) +#define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3) +#define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2) +#define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1) +#define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0) + +#if defined(CONFIG_MX28) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3 (0x0008 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0 (0x0010 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1 (0x0020 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2 (0x0040 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3 (0x0080 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4 (0x0100 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5 (0x0200 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6 (0x0400 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7 (0x0800 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC (0x1000 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF (0x2000 << 16) +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xffff +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET 0 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0 0x0001 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1 0x0002 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2 0x0004 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3 0x0008 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0 0x0010 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1 0x0020 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2 0x0040 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3 0x0080 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4 0x0100 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5 0x0200 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6 0x0400 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000 +#endif + +/* Not on i.MX23 */ +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 + +#if defined(CONFIG_MX23) +#define APBH_DEVSEL_CH7_MASK (0xf << 28) +#define APBH_DEVSEL_CH7_OFFSET 28 +#define APBH_DEVSEL_CH6_MASK (0xf << 24) +#define APBH_DEVSEL_CH6_OFFSET 24 +#define APBH_DEVSEL_CH5_MASK (0xf << 20) +#define APBH_DEVSEL_CH5_OFFSET 20 +#define APBH_DEVSEL_CH4_MASK (0xf << 16) +#define APBH_DEVSEL_CH4_OFFSET 16 +#define APBH_DEVSEL_CH3_MASK (0xf << 12) +#define APBH_DEVSEL_CH3_OFFSET 12 +#define APBH_DEVSEL_CH2_MASK (0xf << 8) +#define APBH_DEVSEL_CH2_OFFSET 8 +#define APBH_DEVSEL_CH1_MASK (0xf << 4) +#define APBH_DEVSEL_CH1_OFFSET 4 +#define APBH_DEVSEL_CH0_MASK (0xf << 0) +#define APBH_DEVSEL_CH0_OFFSET 0 +#elif defined(CONFIG_MX28) +#define APBH_DEVSEL_CH15_MASK (0x3 << 30) +#define APBH_DEVSEL_CH15_OFFSET 30 +#define APBH_DEVSEL_CH14_MASK (0x3 << 28) +#define APBH_DEVSEL_CH14_OFFSET 28 +#define APBH_DEVSEL_CH13_MASK (0x3 << 26) +#define APBH_DEVSEL_CH13_OFFSET 26 +#define APBH_DEVSEL_CH12_MASK (0x3 << 24) +#define APBH_DEVSEL_CH12_OFFSET 24 +#define APBH_DEVSEL_CH11_MASK (0x3 << 22) +#define APBH_DEVSEL_CH11_OFFSET 22 +#define APBH_DEVSEL_CH10_MASK (0x3 << 20) +#define APBH_DEVSEL_CH10_OFFSET 20 +#define APBH_DEVSEL_CH9_MASK (0x3 << 18) +#define APBH_DEVSEL_CH9_OFFSET 18 +#define APBH_DEVSEL_CH8_MASK (0x3 << 16) +#define APBH_DEVSEL_CH8_OFFSET 16 +#define APBH_DEVSEL_CH7_MASK (0x3 << 14) +#define APBH_DEVSEL_CH7_OFFSET 14 +#define APBH_DEVSEL_CH6_MASK (0x3 << 12) +#define APBH_DEVSEL_CH6_OFFSET 12 +#define APBH_DEVSEL_CH5_MASK (0x3 << 10) +#define APBH_DEVSEL_CH5_OFFSET 10 +#define APBH_DEVSEL_CH4_MASK (0x3 << 8) +#define APBH_DEVSEL_CH4_OFFSET 8 +#define APBH_DEVSEL_CH3_MASK (0x3 << 6) +#define APBH_DEVSEL_CH3_OFFSET 6 +#define APBH_DEVSEL_CH2_MASK (0x3 << 4) +#define APBH_DEVSEL_CH2_OFFSET 4 +#define APBH_DEVSEL_CH1_MASK (0x3 << 2) +#define APBH_DEVSEL_CH1_OFFSET 2 +#define APBH_DEVSEL_CH0_MASK (0x3 << 0) +#define APBH_DEVSEL_CH0_OFFSET 0 +#endif + +#if defined(CONFIG_MX28) +#define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30) +#define APBH_DMA_BURST_SIZE_CH15_OFFSET 30 +#define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28) +#define APBH_DMA_BURST_SIZE_CH14_OFFSET 28 +#define APBH_DMA_BURST_SIZE_CH13_MASK (0x3 << 26) +#define APBH_DMA_BURST_SIZE_CH13_OFFSET 26 +#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3 << 24) +#define APBH_DMA_BURST_SIZE_CH12_OFFSET 24 +#define APBH_DMA_BURST_SIZE_CH11_MASK (0x3 << 22) +#define APBH_DMA_BURST_SIZE_CH11_OFFSET 22 +#define APBH_DMA_BURST_SIZE_CH10_MASK (0x3 << 20) +#define APBH_DMA_BURST_SIZE_CH10_OFFSET 20 +#define APBH_DMA_BURST_SIZE_CH9_MASK (0x3 << 18) +#define APBH_DMA_BURST_SIZE_CH9_OFFSET 18 +#define APBH_DMA_BURST_SIZE_CH8_MASK (0x3 << 16) +#define APBH_DMA_BURST_SIZE_CH8_OFFSET 16 +#define APBH_DMA_BURST_SIZE_CH8_BURST0 (0x0 << 16) +#define APBH_DMA_BURST_SIZE_CH8_BURST4 (0x1 << 16) +#define APBH_DMA_BURST_SIZE_CH8_BURST8 (0x2 << 16) +#define APBH_DMA_BURST_SIZE_CH7_MASK (0x3 << 14) +#define APBH_DMA_BURST_SIZE_CH7_OFFSET 14 +#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3 << 12) +#define APBH_DMA_BURST_SIZE_CH6_OFFSET 12 +#define APBH_DMA_BURST_SIZE_CH5_MASK (0x3 << 10) +#define APBH_DMA_BURST_SIZE_CH5_OFFSET 10 +#define APBH_DMA_BURST_SIZE_CH4_MASK (0x3 << 8) +#define APBH_DMA_BURST_SIZE_CH4_OFFSET 8 +#define APBH_DMA_BURST_SIZE_CH3_MASK (0x3 << 6) +#define APBH_DMA_BURST_SIZE_CH3_OFFSET 6 +#define APBH_DMA_BURST_SIZE_CH3_BURST0 (0x0 << 6) +#define APBH_DMA_BURST_SIZE_CH3_BURST4 (0x1 << 6) +#define APBH_DMA_BURST_SIZE_CH3_BURST8 (0x2 << 6) + +#define APBH_DMA_BURST_SIZE_CH2_MASK (0x3 << 4) +#define APBH_DMA_BURST_SIZE_CH2_OFFSET 4 +#define APBH_DMA_BURST_SIZE_CH2_BURST0 (0x0 << 4) +#define APBH_DMA_BURST_SIZE_CH2_BURST4 (0x1 << 4) +#define APBH_DMA_BURST_SIZE_CH2_BURST8 (0x2 << 4) +#define APBH_DMA_BURST_SIZE_CH1_MASK (0x3 << 2) +#define APBH_DMA_BURST_SIZE_CH1_OFFSET 2 +#define APBH_DMA_BURST_SIZE_CH1_BURST0 (0x0 << 2) +#define APBH_DMA_BURST_SIZE_CH1_BURST4 (0x1 << 2) +#define APBH_DMA_BURST_SIZE_CH1_BURST8 (0x2 << 2) + +#define APBH_DMA_BURST_SIZE_CH0_MASK 0x3 +#define APBH_DMA_BURST_SIZE_CH0_OFFSET 0 +#define APBH_DMA_BURST_SIZE_CH0_BURST0 0x0 +#define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1 +#define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2 + +#define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0) +#endif + +#define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff +#define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0 + +#define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK 0xffffffff +#define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET 0 + +#define APBH_CHn_CMD_XFER_COUNT_MASK (0xffff << 16) +#define APBH_CHn_CMD_XFER_COUNT_OFFSET 16 +#define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12) +#define APBH_CHn_CMD_CMDWORDS_OFFSET 12 +#define APBH_CHn_CMD_HALTONTERMINATE (1 << 8) +#define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7) +#define APBH_CHn_CMD_SEMAPHORE (1 << 6) +#define APBH_CHn_CMD_NANDWAIT4READY (1 << 5) +#define APBH_CHn_CMD_NANDLOCK (1 << 4) +#define APBH_CHn_CMD_IRQONCMPLT (1 << 3) +#define APBH_CHn_CMD_CHAIN (1 << 2) +#define APBH_CHn_CMD_COMMAND_MASK 0x3 +#define APBH_CHn_CMD_COMMAND_OFFSET 0 +#define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0 +#define APBH_CHn_CMD_COMMAND_DMA_WRITE 0x1 +#define APBH_CHn_CMD_COMMAND_DMA_READ 0x2 +#define APBH_CHn_CMD_COMMAND_DMA_SENSE 0x3 + +#define APBH_CHn_BAR_ADDRESS_MASK 0xffffffff +#define APBH_CHn_BAR_ADDRESS_OFFSET 0 + +#define APBH_CHn_SEMA_RSVD2_MASK (0xff << 24) +#define APBH_CHn_SEMA_RSVD2_OFFSET 24 +#define APBH_CHn_SEMA_PHORE_MASK (0xff << 16) +#define APBH_CHn_SEMA_PHORE_OFFSET 16 +#define APBH_CHn_SEMA_RSVD1_MASK (0xff << 8) +#define APBH_CHn_SEMA_RSVD1_OFFSET 8 +#define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0) +#define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0 + +#define APBH_CHn_DEBUG1_REQ (1 << 31) +#define APBH_CHn_DEBUG1_BURST (1 << 30) +#define APBH_CHn_DEBUG1_KICK (1 << 29) +#define APBH_CHn_DEBUG1_END (1 << 28) +#define APBH_CHn_DEBUG1_SENSE (1 << 27) +#define APBH_CHn_DEBUG1_READY (1 << 26) +#define APBH_CHn_DEBUG1_LOCK (1 << 25) +#define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24) +#define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23) +#define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22) +#define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21) +#define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20) +#define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5) +#define APBH_CHn_DEBUG1_RSVD1_OFFSET 5 +#define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f +#define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET 0 +#define APBH_CHn_DEBUG1_STATEMACHINE_IDLE 0x00 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1 0x01 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3 0x02 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2 0x03 +#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE 0x04 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT 0x05 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4 0x06 +#define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ 0x07 +#define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH 0x08 +#define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT 0x09 +#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE 0x0c +#define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ 0x0d +#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN 0x0e +#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE 0x0f +#define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE 0x14 +#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END 0x15 +#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT 0x1c +#define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM 0x1d +#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT 0x1e +#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY 0x1f + +#define APBH_CHn_DEBUG2_APB_BYTES_MASK (0xffff << 16) +#define APBH_CHn_DEBUG2_APB_BYTES_OFFSET 16 +#define APBH_CHn_DEBUG2_AHB_BYTES_MASK 0xffff +#define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET 0 + +#define APBH_VERSION_MAJOR_MASK (0xff << 24) +#define APBH_VERSION_MAJOR_OFFSET 24 +#define APBH_VERSION_MINOR_MASK (0xff << 16) +#define APBH_VERSION_MINOR_OFFSET 16 +#define APBH_VERSION_STEP_MASK 0xffff +#define APBH_VERSION_STEP_OFFSET 0 + +#endif /* __REGS_APBH_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/regs-bch.h b/roms/u-boot/arch/arm/include/asm/mach-imx/regs-bch.h new file mode 100644 index 000000000..5a149002e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/regs-bch.h @@ -0,0 +1,234 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX28 BCH Register Definitions + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010, 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2020 NXP + * + */ + +#ifndef __MX28_REGS_BCH_H__ +#define __MX28_REGS_BCH_H__ + +#include + +#ifndef __ASSEMBLY__ +struct mxs_bch_regs { + mxs_reg_32(hw_bch_ctrl) + mxs_reg_32(hw_bch_status0) + mxs_reg_32(hw_bch_mode) + mxs_reg_32(hw_bch_encodeptr) + mxs_reg_32(hw_bch_dataptr) + mxs_reg_32(hw_bch_metaptr) + + uint32_t reserved[4]; + + mxs_reg_32(hw_bch_layoutselect) + mxs_reg_32(hw_bch_flash0layout0) + mxs_reg_32(hw_bch_flash0layout1) + mxs_reg_32(hw_bch_flash1layout0) + mxs_reg_32(hw_bch_flash1layout1) + mxs_reg_32(hw_bch_flash2layout0) + mxs_reg_32(hw_bch_flash2layout1) + mxs_reg_32(hw_bch_flash3layout0) + mxs_reg_32(hw_bch_flash3layout1) + mxs_reg_32(hw_bch_dbgkesread) + mxs_reg_32(hw_bch_dbgcsferead) + mxs_reg_32(hw_bch_dbgsyndegread) + mxs_reg_32(hw_bch_dbgahbmread) + mxs_reg_32(hw_bch_blockname) + mxs_reg_32(hw_bch_version) + mxs_reg_32(hw_bch_debug1) +}; +#endif + +#define BCH_CTRL_SFTRST (1 << 31) +#define BCH_CTRL_CLKGATE (1 << 30) +#define BCH_CTRL_DEBUGSYNDROME (1 << 22) +#define BCH_CTRL_M2M_LAYOUT_MASK (0x3 << 18) +#define BCH_CTRL_M2M_LAYOUT_OFFSET 18 +#define BCH_CTRL_M2M_ENCODE (1 << 17) +#define BCH_CTRL_M2M_ENABLE (1 << 16) +#define BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10) +#define BCH_CTRL_COMPLETE_IRQ_EN (1 << 8) +#define BCH_CTRL_BM_ERROR_IRQ (1 << 3) +#define BCH_CTRL_DEBUG_STALL_IRQ (1 << 2) +#define BCH_CTRL_COMPLETE_IRQ (1 << 0) + +#define BCH_STATUS0_HANDLE_MASK (0xfff << 20) +#define BCH_STATUS0_HANDLE_OFFSET 20 +#define BCH_STATUS0_COMPLETED_CE_MASK (0xf << 16) +#define BCH_STATUS0_COMPLETED_CE_OFFSET 16 +#define BCH_STATUS0_STATUS_BLK0_MASK (0xff << 8) +#define BCH_STATUS0_STATUS_BLK0_OFFSET 8 +#define BCH_STATUS0_STATUS_BLK0_ZERO (0x00 << 8) +#define BCH_STATUS0_STATUS_BLK0_ERROR1 (0x01 << 8) +#define BCH_STATUS0_STATUS_BLK0_ERROR2 (0x02 << 8) +#define BCH_STATUS0_STATUS_BLK0_ERROR3 (0x03 << 8) +#define BCH_STATUS0_STATUS_BLK0_ERROR4 (0x04 << 8) +#define BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE (0xfe << 8) +#define BCH_STATUS0_STATUS_BLK0_ERASED (0xff << 8) +#define BCH_STATUS0_ALLONES (1 << 4) +#define BCH_STATUS0_CORRECTED (1 << 3) +#define BCH_STATUS0_UNCORRECTABLE (1 << 2) + +#define BCH_MODE_ERASE_THRESHOLD_MASK 0xff +#define BCH_MODE_ERASE_THRESHOLD_OFFSET 0 +#define BCH_MODE_ERASE_THRESHOLD(v) \ + (((v) << BCH_MODE_ERASE_THRESHOLD_OFFSET) & \ + BCH_MODE_ERASE_THRESHOLD_MASK) + +#define BCH_ENCODEPTR_ADDR_MASK 0xffffffff +#define BCH_ENCODEPTR_ADDR_OFFSET 0 + +#define BCH_DATAPTR_ADDR_MASK 0xffffffff +#define BCH_DATAPTR_ADDR_OFFSET 0 + +#define BCH_METAPTR_ADDR_MASK 0xffffffff +#define BCH_METAPTR_ADDR_OFFSET 0 + +#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0x3 << 30) +#define BCH_LAYOUTSELECT_CS15_SELECT_OFFSET 30 +#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x3 << 28) +#define BCH_LAYOUTSELECT_CS14_SELECT_OFFSET 28 +#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0x3 << 26) +#define BCH_LAYOUTSELECT_CS13_SELECT_OFFSET 26 +#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3 << 24) +#define BCH_LAYOUTSELECT_CS12_SELECT_OFFSET 24 +#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0x3 << 22) +#define BCH_LAYOUTSELECT_CS11_SELECT_OFFSET 22 +#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x3 << 20) +#define BCH_LAYOUTSELECT_CS10_SELECT_OFFSET 20 +#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0x3 << 18) +#define BCH_LAYOUTSELECT_CS9_SELECT_OFFSET 18 +#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x3 << 16) +#define BCH_LAYOUTSELECT_CS8_SELECT_OFFSET 16 +#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0x3 << 14) +#define BCH_LAYOUTSELECT_CS7_SELECT_OFFSET 14 +#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3 << 12) +#define BCH_LAYOUTSELECT_CS6_SELECT_OFFSET 12 +#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0x3 << 10) +#define BCH_LAYOUTSELECT_CS5_SELECT_OFFSET 10 +#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x3 << 8) +#define BCH_LAYOUTSELECT_CS4_SELECT_OFFSET 8 +#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0x3 << 6) +#define BCH_LAYOUTSELECT_CS3_SELECT_OFFSET 6 +#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x3 << 4) +#define BCH_LAYOUTSELECT_CS2_SELECT_OFFSET 4 +#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0x3 << 2) +#define BCH_LAYOUTSELECT_CS1_SELECT_OFFSET 2 +#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3 << 0) +#define BCH_LAYOUTSELECT_CS0_SELECT_OFFSET 0 + +#define BCH_FLASHLAYOUT0_NBLOCKS_MASK (0xff << 24) +#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24 +#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16) +#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16 +#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)) +#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11) +#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11 +#else +#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12) +#define BCH_FLASHLAYOUT0_ECC0_OFFSET 12 +#endif +#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC6 (0x3 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC8 (0x4 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC10 (0x5 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC12 (0x6 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC14 (0x7 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC16 (0x8 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC18 (0x9 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC20 (0xa << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC22 (0xb << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC24 (0xc << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC26 (0xd << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12) +#define BCH_FLASHLAYOUT0_GF13_0_GF14_1_MASK BIT(10) +#define BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET 10 +#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0x3ff +#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0 + +#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16) +#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16 +#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)) +#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11) +#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11 +#else +#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12) +#define BCH_FLASHLAYOUT1_ECCN_OFFSET 12 +#endif +#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC6 (0x3 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC8 (0x4 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC10 (0x5 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC12 (0x6 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC14 (0x7 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC16 (0x8 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC18 (0x9 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC20 (0xa << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC22 (0xb << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC24 (0xc << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC26 (0xd << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12) +#define BCH_FLASHLAYOUT1_GF13_0_GF14_1_MASK BIT(10) +#define BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET 10 +#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0x3ff +#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0 + +#define BCH_DEBUG0_RSVD1_MASK (0x1f << 27) +#define BCH_DEBUG0_RSVD1_OFFSET 27 +#define BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26) +#define BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1ff << 16) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET 16 +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL (0x0 << 16) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE (0x1 << 16) +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15) +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14) +#define BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13) +#define BCH_DEBUG0_KES_DEBUG_KICK (1 << 12) +#define BCH_DEBUG0_KES_STANDALONE (1 << 11) +#define BCH_DEBUG0_KES_DEBUG_STEP (1 << 10) +#define BCH_DEBUG0_KES_DEBUG_STALL (1 << 9) +#define BCH_DEBUG0_BM_KES_TEST_BYPASS (1 << 8) +#define BCH_DEBUG0_RSVD0_MASK (0x3 << 6) +#define BCH_DEBUG0_RSVD0_OFFSET 6 +#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3f +#define BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET 0 + +#define BCH_DBGKESREAD_VALUES_MASK 0xffffffff +#define BCH_DBGKESREAD_VALUES_OFFSET 0 + +#define BCH_DBGCSFEREAD_VALUES_MASK 0xffffffff +#define BCH_DBGCSFEREAD_VALUES_OFFSET 0 + +#define BCH_DBGSYNDGENREAD_VALUES_MASK 0xffffffff +#define BCH_DBGSYNDGENREAD_VALUES_OFFSET 0 + +#define BCH_DBGAHBMREAD_VALUES_MASK 0xffffffff +#define BCH_DBGAHBMREAD_VALUES_OFFSET 0 + +#define BCH_BLOCKNAME_NAME_MASK 0xffffffff +#define BCH_BLOCKNAME_NAME_OFFSET 0 + +#define BCH_VERSION_MAJOR_MASK (0xff << 24) +#define BCH_VERSION_MAJOR_OFFSET 24 +#define BCH_VERSION_MINOR_MASK (0xff << 16) +#define BCH_VERSION_MINOR_OFFSET 16 +#define BCH_VERSION_STEP_MASK 0xffff +#define BCH_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_BCH_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/regs-common.h b/roms/u-boot/arch/arm/include/asm/mach-imx/regs-common.h new file mode 100644 index 000000000..0f9bd3cd7 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/regs-common.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MXS Register Accessors + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ + +#ifndef __MXS_REGS_COMMON_H__ +#define __MXS_REGS_COMMON_H__ + +#include + +/* + * The i.MXS has interesting feature when it comes to register access. There + * are four kinds of access to one particular register. Those are: + * + * 1) Common read/write access. To use this mode, just write to the address of + * the register. + * 2) Set bits only access. To set bits, write which bits you want to set to the + * address of the register + 0x4. + * 3) Clear bits only access. To clear bits, write which bits you want to clear + * to the address of the register + 0x8. + * 4) Toggle bits only access. To toggle bits, write which bits you want to + * toggle to the address of the register + 0xc. + * + * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits + * can be set/cleared by pure write as in access type 1, some need to be + * explicitly set/cleared by using access type 2-3. + * + * The following macros and structures allow the user to either access the + * register in all aforementioned modes (by accessing reg_name, reg_name_set, + * reg_name_clr, reg_name_tog) or pass the register structure further into + * various functions with correct type information (by accessing reg_name_reg). + * + */ + +#define __mxs_reg_8(name) \ + uint8_t name[4]; \ + uint8_t name##_set[4]; \ + uint8_t name##_clr[4]; \ + uint8_t name##_tog[4]; \ + +#define __mxs_reg_32(name) \ + uint32_t name; \ + uint32_t name##_set; \ + uint32_t name##_clr; \ + uint32_t name##_tog; + +struct mxs_register_8 { + __mxs_reg_8(reg) +}; + +struct mxs_register_32 { + __mxs_reg_32(reg) +}; + +#define mxs_reg_8(name) \ + union { \ + struct { __mxs_reg_8(name) }; \ + struct mxs_register_8 name##_reg; \ + }; + +#define mxs_reg_32(name) \ + union { \ + struct { __mxs_reg_32(name) }; \ + struct mxs_register_32 name##_reg; \ + }; + +#endif /* __MXS_REGS_COMMON_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/regs-gpmi.h b/roms/u-boot/arch/arm/include/asm/mach-imx/regs-gpmi.h new file mode 100644 index 000000000..33daa53c4 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/regs-gpmi.h @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX28 GPMI Register Definitions + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __MX28_REGS_GPMI_H__ +#define __MX28_REGS_GPMI_H__ + +#include + +#ifndef __ASSEMBLY__ +struct mxs_gpmi_regs { + mxs_reg_32(hw_gpmi_ctrl0) + mxs_reg_32(hw_gpmi_compare) + mxs_reg_32(hw_gpmi_eccctrl) + mxs_reg_32(hw_gpmi_ecccount) + mxs_reg_32(hw_gpmi_payload) + mxs_reg_32(hw_gpmi_auxiliary) + mxs_reg_32(hw_gpmi_ctrl1) + mxs_reg_32(hw_gpmi_timing0) + mxs_reg_32(hw_gpmi_timing1) + + uint32_t reserved[4]; + + mxs_reg_32(hw_gpmi_data) + mxs_reg_32(hw_gpmi_stat) + mxs_reg_32(hw_gpmi_debug) + mxs_reg_32(hw_gpmi_version) +}; +#endif + +#define GPMI_CTRL0_SFTRST (1 << 31) +#define GPMI_CTRL0_CLKGATE (1 << 30) +#define GPMI_CTRL0_RUN (1 << 29) +#define GPMI_CTRL0_DEV_IRQ_EN (1 << 28) +#define GPMI_CTRL0_LOCK_CS (1 << 27) +#define GPMI_CTRL0_UDMA (1 << 26) +#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3 << 24) +#define GPMI_CTRL0_COMMAND_MODE_OFFSET 24 +#define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24) +#define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24) +#define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24) +#define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24) +#define GPMI_CTRL0_WORD_LENGTH (1 << 23) +#define GPMI_CTRL0_CS_MASK (0x7 << 20) +#define GPMI_CTRL0_CS_OFFSET 20 +#define GPMI_CTRL0_ADDRESS_MASK (0x7 << 17) +#define GPMI_CTRL0_ADDRESS_OFFSET 17 +#define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17) +#define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17) +#define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17) +#define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16) +#define GPMI_CTRL0_XFER_COUNT_MASK 0xffff +#define GPMI_CTRL0_XFER_COUNT_OFFSET 0 + +#define GPMI_COMPARE_MASK_MASK (0xffff << 16) +#define GPMI_COMPARE_MASK_OFFSET 16 +#define GPMI_COMPARE_REFERENCE_MASK 0xffff +#define GPMI_COMPARE_REFERENCE_OFFSET 0 + +#define GPMI_ECCCTRL_HANDLE_MASK (0xffff << 16) +#define GPMI_ECCCTRL_HANDLE_OFFSET 16 +#define GPMI_ECCCTRL_ECC_CMD_MASK (0x3 << 13) +#define GPMI_ECCCTRL_ECC_CMD_OFFSET 13 +#define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13) +#define GPMI_ECCCTRL_ECC_CMD_ENCODE (0x1 << 13) +#define GPMI_ECCCTRL_RANDOMIZER_ENABLE (1 << 11) +#define GPMI_ECCCTRL_RANDOMIZER_TYPE0 0 +#define GPMI_ECCCTRL_RANDOMIZER_TYPE1 (1 << 9) +#define GPMI_ECCCTRL_RANDOMIZER_TYPE2 (2 << 9) + +#define GPMI_ECCCTRL_ENABLE_ECC (1 << 12) +#define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1ff +#define GPMI_ECCCTRL_BUFFER_MASK_OFFSET 0 +#define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY 0x100 +#define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE 0x1ff + +#define GPMI_ECCCOUNT_COUNT_MASK 0xffff +#define GPMI_ECCCOUNT_COUNT_OFFSET 0 + +#define GPMI_PAYLOAD_ADDRESS_MASK (0x3fffffff << 2) +#define GPMI_PAYLOAD_ADDRESS_OFFSET 2 + +#define GPMI_AUXILIARY_ADDRESS_MASK (0x3fffffff << 2) +#define GPMI_AUXILIARY_ADDRESS_OFFSET 2 + +#define GPMI_CTRL1_DECOUPLE_CS (1 << 24) +#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22) +#define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22 +#define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20) +#define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19) +#define GPMI_CTRL1_BCH_MODE (1 << 18) +#define GPMI_CTRL1_DLL_ENABLE (1 << 17) +#define GPMI_CTRL1_HALF_PERIOD (1 << 16) +#define GPMI_CTRL1_RDN_DELAY_MASK (0xf << 12) +#define GPMI_CTRL1_RDN_DELAY_OFFSET 12 +#define GPMI_CTRL1_DMA2ECC_MODE (1 << 11) +#define GPMI_CTRL1_DEV_IRQ (1 << 10) +#define GPMI_CTRL1_TIMEOUT_IRQ (1 << 9) +#define GPMI_CTRL1_BURST_EN (1 << 8) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x7 << 4) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET 4 +#define GPMI_CTRL1_DEV_RESET (1 << 3) +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2) +#define GPMI_CTRL1_CAMERA_MODE (1 << 1) +#define GPMI_CTRL1_GPMI_MODE (1 << 0) + +#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16) +#define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16 +#define GPMI_TIMING0_DATA_HOLD_MASK (0xff << 8) +#define GPMI_TIMING0_DATA_HOLD_OFFSET 8 +#define GPMI_TIMING0_DATA_SETUP_MASK 0xff +#define GPMI_TIMING0_DATA_SETUP_OFFSET 0 + +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xffff << 16) +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET 16 + +#define GPMI_TIMING2_UDMA_TRP_MASK (0xff << 24) +#define GPMI_TIMING2_UDMA_TRP_OFFSET 24 +#define GPMI_TIMING2_UDMA_ENV_MASK (0xff << 16) +#define GPMI_TIMING2_UDMA_ENV_OFFSET 16 +#define GPMI_TIMING2_UDMA_HOLD_MASK (0xff << 8) +#define GPMI_TIMING2_UDMA_HOLD_OFFSET 8 +#define GPMI_TIMING2_UDMA_SETUP_MASK 0xff +#define GPMI_TIMING2_UDMA_SETUP_OFFSET 0 + +#define GPMI_DATA_DATA_MASK 0xffffffff +#define GPMI_DATA_DATA_OFFSET 0 + +#define GPMI_STAT_READY_BUSY_MASK (0xff << 24) +#define GPMI_STAT_READY_BUSY_OFFSET 24 +#define GPMI_STAT_RDY_TIMEOUT_MASK (0xff << 16) +#define GPMI_STAT_RDY_TIMEOUT_OFFSET 16 +#define GPMI_STAT_DEV7_ERROR (1 << 15) +#define GPMI_STAT_DEV6_ERROR (1 << 14) +#define GPMI_STAT_DEV5_ERROR (1 << 13) +#define GPMI_STAT_DEV4_ERROR (1 << 12) +#define GPMI_STAT_DEV3_ERROR (1 << 11) +#define GPMI_STAT_DEV2_ERROR (1 << 10) +#define GPMI_STAT_DEV1_ERROR (1 << 9) +#define GPMI_STAT_DEV0_ERROR (1 << 8) +#define GPMI_STAT_ATA_IRQ (1 << 4) +#define GPMI_STAT_INVALID_BUFFER_MASK (1 << 3) +#define GPMI_STAT_FIFO_EMPTY (1 << 2) +#define GPMI_STAT_FIFO_FULL (1 << 1) +#define GPMI_STAT_PRESENT (1 << 0) + +#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xff << 24) +#define GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET 24 +#define GPMI_DEBUG_DMA_SENSE_MASK (0xff << 16) +#define GPMI_DEBUG_DMA_SENSE_OFFSET 16 +#define GPMI_DEBUG_DMAREQ_MASK (0xff << 8) +#define GPMI_DEBUG_DMAREQ_OFFSET 8 +#define GPMI_DEBUG_CMD_END_MASK 0xff +#define GPMI_DEBUG_CMD_END_OFFSET 0 + +#define GPMI_VERSION_MAJOR_MASK (0xff << 24) +#define GPMI_VERSION_MAJOR_OFFSET 24 +#define GPMI_VERSION_MINOR_MASK (0xff << 16) +#define GPMI_VERSION_MINOR_OFFSET 16 +#define GPMI_VERSION_STEP_MASK 0xffff +#define GPMI_VERSION_STEP_OFFSET 0 + +#define GPMI_DEBUG2_UDMA_STATE_MASK (0xf << 24) +#define GPMI_DEBUG2_UDMA_STATE_OFFSET 24 +#define GPMI_DEBUG2_BUSY (1 << 23) +#define GPMI_DEBUG2_PIN_STATE_MASK (0x7 << 20) +#define GPMI_DEBUG2_PIN_STATE_OFFSET 20 +#define GPMI_DEBUG2_PIN_STATE_PSM_IDLE (0x0 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT (0x1 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_ADDR (0x2 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_STALL (0x3 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_STROBE (0x4 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_ATARDY (0x5 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_DHOLD (0x6 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_DONE (0x7 << 20) +#define GPMI_DEBUG2_MAIN_STATE_MASK (0xf << 16) +#define GPMI_DEBUG2_MAIN_STATE_OFFSET 16 +#define GPMI_DEBUG2_MAIN_STATE_MSM_IDLE (0x0 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT (0x1 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE (0x2 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR (0x3 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ (0x4 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK (0x5 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF (0x6 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO (0x7 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR (0x8 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP (0x9 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_DONE (0xa << 16) +#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xf << 12) +#define GPMI_DEBUG2_SYND2GPMI_BE_OFFSET 12 +#define GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11) +#define GPMI_DEBUG2_GPMI2SYND_READY (1 << 10) +#define GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9) +#define GPMI_DEBUG2_SYND2GPMI_READY (1 << 8) +#define GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7) +#define GPMI_DEBUG2_UPDATE_WINDOW (1 << 6) +#define GPMI_DEBUG2_RDN_TAP_MASK 0x3f +#define GPMI_DEBUG2_RDN_TAP_OFFSET 0 + +#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xffff << 16) +#define GPMI_DEBUG3_APB_WORD_CNTR_OFFSET 16 +#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK 0xffff +#define GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET 0 + +#endif /* __MX28_REGS_GPMI_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/regs-lcdif.h b/roms/u-boot/arch/arm/include/asm/mach-imx/regs-lcdif.h new file mode 100644 index 000000000..587463879 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/regs-lcdif.h @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX28/6SX/6UL/7D LCDIF Register Definitions + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __IMX_REGS_LCDIF_H__ +#define __IMX_REGS_LCDIF_H__ + +#ifndef __ASSEMBLY__ +#include + +struct mxs_lcdif_regs { + mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */ + mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */ +#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ + defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ + defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT) + mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ +#endif + mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */ + mxs_reg_32(hw_lcdif_cur_buf) /* 0x30/0x40 */ + mxs_reg_32(hw_lcdif_next_buf) /* 0x40/0x50 */ + +#if defined(CONFIG_MX23) + uint32_t reserved1[4]; +#endif + + mxs_reg_32(hw_lcdif_timing) /* 0x60 */ + mxs_reg_32(hw_lcdif_vdctrl0) /* 0x70 */ + mxs_reg_32(hw_lcdif_vdctrl1) /* 0x80 */ + mxs_reg_32(hw_lcdif_vdctrl2) /* 0x90 */ + mxs_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */ + mxs_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */ + mxs_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */ + mxs_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */ + mxs_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */ + mxs_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */ + mxs_reg_32(hw_lcdif_dvictrl4) /* 0x100 */ + mxs_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */ + mxs_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */ + mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */ + mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */ + mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */ + mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */ + mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */ + +#if defined(CONFIG_MX23) + uint32_t reserved2[12]; +#endif + mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */ + mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */ +#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ + defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ + defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT) + mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ +#endif + mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */ + mxs_reg_32(hw_lcdif_version) /* 0x1e0/0x1c0 */ + mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */ + mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */ + mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */ +#if defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ + defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ + defined(CONFIG_IMX8M) + mxs_reg_32(hw_lcdif_thres) + mxs_reg_32(hw_lcdif_as_ctrl) + mxs_reg_32(hw_lcdif_as_buf) + mxs_reg_32(hw_lcdif_as_next_buf) + mxs_reg_32(hw_lcdif_as_clrkeylow) + mxs_reg_32(hw_lcdif_as_clrkeyhigh) + mxs_reg_32(hw_lcdif_as_sync_delay) + mxs_reg_32(hw_lcdif_as_debug3) + mxs_reg_32(hw_lcdif_as_debug4) + mxs_reg_32(hw_lcdif_as_debug5) +#endif +}; +#endif + +#define LCDIF_CTRL_SFTRST (1 << 31) +#define LCDIF_CTRL_CLKGATE (1 << 30) +#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29) +#define LCDIF_CTRL_READ_WRITEB (1 << 28) +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27) +#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26) +#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21) +#define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21 +#define LCDIF_CTRL_DVI_MODE (1 << 20) +#define LCDIF_CTRL_BYPASS_COUNT (1 << 19) +#define LCDIF_CTRL_VSYNC_MODE (1 << 18) +#define LCDIF_CTRL_DOTCLK_MODE (1 << 17) +#define LCDIF_CTRL_DATA_SELECT (1 << 16) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14 +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12 +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10 +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10) +#define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8) +#define LCDIF_CTRL_WORD_LENGTH_OFFSET 8 +#define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8) +#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8) +#define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8) +#define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8) +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7) +#define LCDIF_CTRL_LCDIF_MASTER (1 << 5) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1) +#define LCDIF_CTRL_RUN (1 << 0) + +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26) +#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24) +#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22) +#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16 +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12) +#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11) +#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8) +#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2) +#define LCDIF_CTRL1_MODE86 (1 << 1) +#define LCDIF_CTRL1_RESET (1 << 0) + +#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21 +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21) +#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16 +#define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12 +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12) +#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10) +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9) +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4 +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1) +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1 + +#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16) +#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16 +#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0) +#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0 + +#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff +#define LCDIF_CUR_BUF_ADDR_OFFSET 0 + +#define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff +#define LCDIF_NEXT_BUF_ADDR_OFFSET 0 + +#define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24) +#define LCDIF_TIMING_CMD_HOLD_OFFSET 24 +#define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16) +#define LCDIF_TIMING_CMD_SETUP_OFFSET 16 +#define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8) +#define LCDIF_TIMING_DATA_HOLD_OFFSET 8 +#define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0) +#define LCDIF_TIMING_DATA_SETUP_OFFSET 0 + +#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29) +#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28) +#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27) +#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26) +#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25) +#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) +#define LCDIF_VDCTRL0_HALF_LINE (1 << 19) +#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0 + +#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff +#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0 + +#if defined(CONFIG_MX23) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24 +#else +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 +#endif +#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff +#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0 + +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) +#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16 +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0 + +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29 +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 + +#endif /* __IMX_REGS_LCDIF_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/regs-usbphy.h b/roms/u-boot/arch/arm/include/asm/mach-imx/regs-usbphy.h new file mode 100644 index 000000000..2b18ec20f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/regs-usbphy.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale USB PHY Register Definitions + * + */ + +#ifndef __REGS_USBPHY_H__ +#define __REGS_USBPHY_H__ + +#define USBPHY_CTRL 0x00000030 +#define USBPHY_CTRL_SET 0x00000034 +#define USBPHY_CTRL_CLR 0x00000038 +#define USBPHY_CTRL_TOG 0x0000003C +#define USBPHY_PWD 0x00000000 +#define USBPHY_TX 0x00000010 +#define USBPHY_RX 0x00000020 +#define USBPHY_DEBUG 0x00000050 + +#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14) +#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15) +#define USBPHY_CTRL_OTG_ID (1 << 27) +#define USBPHY_CTRL_CLKGATE (1 << 30) +#define USBPHY_CTRL_SFTRST (1 << 31) + +#endif /* __REGS_USBPHY_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/sata.h b/roms/u-boot/arch/arm/include/asm/mach-imx/sata.h new file mode 100644 index 000000000..cf9b73e68 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/sata.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + */ + +#ifndef __IMX_SATA_H_ +#define __IMX_SATA_H_ + +/* + * SATA setup for i.mx6 quad based platform + */ + +int setup_sata(void); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/spi.h b/roms/u-boot/arch/arm/include/asm/mach-imx/spi.h new file mode 100644 index 000000000..598a996a3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/spi.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + */ + +#ifndef __MXC_SPI_H_ +#define __MXC_SPI_H_ + +/* + * Board-level chip-select callback + * Should return GPIO # to be used for chip-select + */ + +int board_spi_cs_gpio(unsigned bus, unsigned cs); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/sys_proto.h b/roms/u-boot/arch/arm/include/asm/mach-imx/sys_proto.h new file mode 100644 index 000000000..b61218984 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/sys_proto.h @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +#include +#include +#include +#include +#include "../arch-imx/cpu.h" + +struct bd_info; + +#define soc_rev() (get_cpu_rev() & 0xFF) +#define is_soc_rev(rev) (soc_rev() == rev) + +/* returns MXC_CPU_ value */ +#define cpu_type(rev) (((rev) >> 12) & 0x1ff) +#define soc_type(rev) (((rev) >> 12) & 0xf0) +/* both macros return/take MXC_CPU_ constants */ +#define get_cpu_type() (cpu_type(get_cpu_rev())) +#define get_soc_type() (soc_type(get_cpu_rev())) +#define is_cpu_type(cpu) (get_cpu_type() == cpu) +#define is_soc_type(soc) (get_soc_type() == soc) + +#define is_mx6() (is_soc_type(MXC_SOC_MX6)) +#define is_mx7() (is_soc_type(MXC_SOC_MX7)) +#define is_imx8m() (is_soc_type(MXC_SOC_IMX8M)) +#define is_imx8() (is_soc_type(MXC_SOC_IMX8)) +#define is_imxrt() (is_soc_type(MXC_SOC_IMXRT)) + +#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) +#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) +#define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL)) +#define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL)) +#define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX)) +#define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL)) +#define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO)) +#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL)) +#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL) || is_cpu_type(MXC_CPU_MX6ULZ)) +#define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ)) +#define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL)) + +#define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) + +#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ) || is_cpu_type(MXC_CPU_IMX8MD) || is_cpu_type(MXC_CPU_IMX8MQL)) +#define is_imx8md() (is_cpu_type(MXC_CPU_IMX8MD)) +#define is_imx8mql() (is_cpu_type(MXC_CPU_IMX8MQL)) +#define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM)) +#define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\ + is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \ + is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL)) +#define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML)) +#define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD)) +#define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL)) +#define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS)) +#define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL)) +#define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \ + is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \ + is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL) || \ + is_cpu_type(MXC_CPU_IMX8MNUD) || is_cpu_type(MXC_CPU_IMX8MNUS) || is_cpu_type(MXC_CPU_IMX8MNUQ)) +#define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND)) +#define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS)) +#define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL)) +#define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL)) +#define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL)) +#define is_imx8mnuq() (is_cpu_type(MXC_CPU_IMX8MNUQ)) +#define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD)) +#define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS)) +#define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \ + is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6)) +#define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD)) +#define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL)) +#define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6)) + +#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) + +#define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020)) +#define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050)) + +#ifdef CONFIG_MX6 +#define IMX6_SRC_GPR10_BMODE BIT(28) +#define IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30) + +#define IMX6_BMODE_MASK GENMASK(7, 0) +#define IMX6_BMODE_SHIFT 4 +#define IMX6_BMODE_EMI_MASK BIT(3) +#define IMX6_BMODE_EMI_SHIFT 3 +#define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24) +#define IMX6_BMODE_SERIAL_ROM_SHIFT 24 + +enum imx6_bmode_serial_rom { + IMX6_BMODE_ECSPI1, + IMX6_BMODE_ECSPI2, + IMX6_BMODE_ECSPI3, + IMX6_BMODE_ECSPI4, + IMX6_BMODE_ECSPI5, + IMX6_BMODE_I2C1, + IMX6_BMODE_I2C2, + IMX6_BMODE_I2C3, +}; + +enum imx6_bmode_emi { + IMX6_BMODE_NOR, + IMX6_BMODE_ONENAND, +}; + +enum imx6_bmode { + IMX6_BMODE_EMI, +#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) + IMX6_BMODE_QSPI, + IMX6_BMODE_RESERVED, +#else + IMX6_BMODE_RESERVED, + IMX6_BMODE_SATA, +#endif + IMX6_BMODE_SERIAL_ROM, + IMX6_BMODE_SD, + IMX6_BMODE_ESD, + IMX6_BMODE_MMC, + IMX6_BMODE_EMMC, + IMX6_BMODE_NAND_MIN, + IMX6_BMODE_NAND_MAX = 0xf, +}; + +u32 imx6_src_get_boot_mode(void); +void gpr_init(void); + +#endif /* CONFIG_MX6 */ + +#ifdef CONFIG_MX7 +#define IMX7_SRC_GPR10_BMODE BIT(28) +#define IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30) +#endif + +/* address translation table */ +struct rproc_att { + u32 da; /* device address (From Cortex M4 view) */ + u32 sa; /* system bus address */ + u32 size; /* size of reg range */ +}; + +#ifdef CONFIG_IMX8M +struct rom_api { + u16 ver; + u16 tag; + u32 reserved1; + u32 (*download_image)(u8 *dest, u32 offset, u32 size, u32 xor); + u32 (*query_boot_infor)(u32 info_type, u32 *info, u32 xor); +}; + +enum boot_dev_type_e { + BT_DEV_TYPE_SD = 1, + BT_DEV_TYPE_MMC = 2, + BT_DEV_TYPE_NAND = 3, + BT_DEV_TYPE_FLEXSPINOR = 4, + + BT_DEV_TYPE_USB = 0xE, + BT_DEV_TYPE_MEM_DEV = 0xF, + + BT_DEV_TYPE_INVALID = 0xFF +}; + +#define QUERY_ROM_VER 1 +#define QUERY_BT_DEV 2 +#define QUERY_PAGE_SZ 3 +#define QUERY_IVT_OFF 4 +#define QUERY_BT_STAGE 5 +#define QUERY_IMG_OFF 6 + +#define ROM_API_OKAY 0xF0 + +extern struct rom_api *g_rom_api; +#endif + +u32 get_nr_cpus(void); +u32 get_cpu_rev(void); +u32 get_cpu_speed_grade_hz(void); +u32 get_cpu_temp_grade(int *minc, int *maxc); +const char *get_imx_type(u32 imxtype); +u32 imx_ddr_size(void); +void sdelay(unsigned long); +void set_chipselect_size(int const); + +void init_aips(void); +void init_src(void); +void init_snvs(void); +void imx_wdog_disable_powerdown(void); + +void board_mem_get_layout(u64 *phys_sdram_1_start, + u64 *phys_sdram_1_size, + u64 *phys_sdram_2_start, + u64 *phys_sdram_2_size); + +int arch_auxiliary_core_check_up(u32 core_id); + +int board_mmc_get_env_dev(int devno); + +int nxp_board_rev(void); +char nxp_board_rev_string(void); + +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +int fecmxc_initialize(struct bd_info *bis); +u32 get_ahb_clk(void); +u32 get_periph_clk(void); + +void lcdif_power_down(void); + +int mxs_reset_block(struct mxs_register_32 *reg); +int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout); +int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout); + +unsigned long call_imx_sip(unsigned long id, unsigned long reg0, + unsigned long reg1, unsigned long reg2, + unsigned long reg3); +unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0, + unsigned long *reg1, unsigned long reg2, + unsigned long reg3); + +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/syscounter.h b/roms/u-boot/arch/arm/include/asm/mach-imx/syscounter.h new file mode 100644 index 000000000..a2cae1edb --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/syscounter.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ + +#ifndef _ASM_ARCH_SYSTEM_COUNTER_H +#define _ASM_ARCH_SYSTEM_COUNTER_H + +/* System Counter */ +struct sctr_regs { + u32 cntcr; + u32 cntsr; + u32 cntcv1; + u32 cntcv2; + u32 resv1[4]; + u32 cntfid0; + u32 cntfid1; + u32 cntfid2; + u32 resv2[1001]; + u32 counterid[1]; +}; + +#define SC_CNTCR_ENABLE (1 << 0) +#define SC_CNTCR_HDBG (1 << 1) +#define SC_CNTCR_FREQ0 (1 << 8) +#define SC_CNTCR_FREQ1 (1 << 9) + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/mach-imx/video.h b/roms/u-boot/arch/arm/include/asm/mach-imx/video.h new file mode 100644 index 000000000..d1a14ad7d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-imx/video.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __IMX_VIDEO_H_ +#define __IMX_VIDEO_H_ + +#include +#include + +struct display_info_t { + int bus; + int addr; + int pixfmt; + int di; + int (*detect)(struct display_info_t const *dev); + void (*enable)(struct display_info_t const *dev); + struct fb_videomode mode; +}; + +#ifdef CONFIG_IMX_HDMI +extern int detect_hdmi(struct display_info_t const *dev); +#endif + +#ifdef CONFIG_IMX_VIDEO_SKIP +extern struct display_info_t const displays[]; +extern size_t display_count; +#endif + +int ipu_set_ldb_clock(int rate); +int ipu_displays_init(void); +#endif diff --git a/roms/u-boot/arch/arm/include/asm/mach-types.h b/roms/u-boot/arch/arm/include/asm/mach-types.h new file mode 100644 index 000000000..32532b3ca --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mach-types.h @@ -0,0 +1,5054 @@ +/* + * This was automagically generated from arch/arm/tools/mach-types! + * Do NOT edit + */ + +#ifndef __ASM_ARM_MACH_TYPE_H +#define __ASM_ARM_MACH_TYPE_H + +/* see arch/arm/kernel/arch.c for a description of these */ +#define MACH_TYPE_EBSA110 0 +#define MACH_TYPE_RISCPC 1 +#define MACH_TYPE_NEXUSPCI 3 +#define MACH_TYPE_EBSA285 4 +#define MACH_TYPE_NETWINDER 5 +#define MACH_TYPE_CATS 6 +#define MACH_TYPE_TBOX 7 +#define MACH_TYPE_CO285 8 +#define MACH_TYPE_CLPS7110 9 +#define MACH_TYPE_ARCHIMEDES 10 +#define MACH_TYPE_A5K 11 +#define MACH_TYPE_ETOILE 12 +#define MACH_TYPE_LACIE_NAS 13 +#define MACH_TYPE_CLPS7500 14 +#define MACH_TYPE_SHARK 15 +#define MACH_TYPE_BRUTUS 16 +#define MACH_TYPE_PERSONAL_SERVER 17 +#define MACH_TYPE_ITSY 18 +#define MACH_TYPE_L7200 19 +#define MACH_TYPE_PLEB 20 +#define MACH_TYPE_INTEGRATOR 21 +#define MACH_TYPE_H3600 22 +#define MACH_TYPE_IXP1200 23 +#define MACH_TYPE_P720T 24 +#define MACH_TYPE_ASSABET 25 +#define MACH_TYPE_VICTOR 26 +#define MACH_TYPE_LART 27 +#define MACH_TYPE_RANGER 28 +#define MACH_TYPE_GRAPHICSCLIENT 29 +#define MACH_TYPE_XP860 30 +#define MACH_TYPE_CERF 31 +#define MACH_TYPE_NANOENGINE 32 +#define MACH_TYPE_FPIC 33 +#define MACH_TYPE_EXTENEX1 34 +#define MACH_TYPE_SHERMAN 35 +#define MACH_TYPE_ACCELENT_SA 36 +#define MACH_TYPE_ACCELENT_L7200 37 +#define MACH_TYPE_NETPORT 38 +#define MACH_TYPE_PANGOLIN 39 +#define MACH_TYPE_YOPY 40 +#define MACH_TYPE_COOLIDGE 41 +#define MACH_TYPE_HUW_WEBPANEL 42 +#define MACH_TYPE_SPOTME 43 +#define MACH_TYPE_FREEBIRD 44 +#define MACH_TYPE_TI925 45 +#define MACH_TYPE_RISCSTATION 46 +#define MACH_TYPE_CAVY 47 +#define MACH_TYPE_JORNADA720 48 +#define MACH_TYPE_OMNIMETER 49 +#define MACH_TYPE_EDB7211 50 +#define MACH_TYPE_CITYGO 51 +#define MACH_TYPE_PFS168 52 +#define MACH_TYPE_SPOT 53 +#define MACH_TYPE_FLEXANET 54 +#define MACH_TYPE_WEBPAL 55 +#define MACH_TYPE_LINPDA 56 +#define MACH_TYPE_ANAKIN 57 +#define MACH_TYPE_MVI 58 +#define MACH_TYPE_JUPITER 59 +#define MACH_TYPE_PSIONW 60 +#define MACH_TYPE_ALN 61 +#define MACH_TYPE_CAMELOT 62 +#define MACH_TYPE_GDS2200 63 +#define MACH_TYPE_PSION_SERIES7 64 +#define MACH_TYPE_XFILE 65 +#define MACH_TYPE_ACCELENT_EP9312 66 +#define MACH_TYPE_IC200 67 +#define MACH_TYPE_CREDITLART 68 +#define MACH_TYPE_HTM 69 +#define MACH_TYPE_IQ80310 70 +#define MACH_TYPE_FREEBOT 71 +#define MACH_TYPE_ENTEL 72 +#define MACH_TYPE_ENP3510 73 +#define MACH_TYPE_TRIZEPS 74 +#define MACH_TYPE_NESA 75 +#define MACH_TYPE_VENUS 76 +#define MACH_TYPE_TARDIS 77 +#define MACH_TYPE_MERCURY 78 +#define MACH_TYPE_EMPEG 79 +#define MACH_TYPE_I80200FCC 80 +#define MACH_TYPE_ITT_CPB 81 +#define MACH_TYPE_SVC 82 +#define MACH_TYPE_ALPHA2 84 +#define MACH_TYPE_ALPHA1 85 +#define MACH_TYPE_NETARM 86 +#define MACH_TYPE_SIMPAD 87 +#define MACH_TYPE_PDA1 88 +#define MACH_TYPE_LUBBOCK 89 +#define MACH_TYPE_ANIKO 90 +#define MACH_TYPE_CLEP7212 91 +#define MACH_TYPE_CS89712 92 +#define MACH_TYPE_WEARARM 93 +#define MACH_TYPE_POSSIO_PX 94 +#define MACH_TYPE_SIDEARM 95 +#define MACH_TYPE_STORK 96 +#define MACH_TYPE_SHANNON 97 +#define MACH_TYPE_ACE 98 +#define MACH_TYPE_BALLYARM 99 +#define MACH_TYPE_SIMPUTER 100 +#define MACH_TYPE_NEXTERM 101 +#define MACH_TYPE_SA1100_ELF 102 +#define MACH_TYPE_GATOR 103 +#define MACH_TYPE_GRANITE 104 +#define MACH_TYPE_CONSUS 105 +#define MACH_TYPE_AAED2000 106 +#define MACH_TYPE_CDB89712 107 +#define MACH_TYPE_GRAPHICSMASTER 108 +#define MACH_TYPE_ADSBITSY 109 +#define MACH_TYPE_PXA_IDP 110 +#define MACH_TYPE_PLCE 111 +#define MACH_TYPE_PT_SYSTEM3 112 +#define MACH_TYPE_MEDALB 113 +#define MACH_TYPE_EAGLE 114 +#define MACH_TYPE_DSC21 115 +#define MACH_TYPE_DSC24 116 +#define MACH_TYPE_TI5472 117 +#define MACH_TYPE_AUTCPU12 118 +#define MACH_TYPE_UENGINE 119 +#define MACH_TYPE_BLUESTEM 120 +#define MACH_TYPE_XINGU8 121 +#define MACH_TYPE_BUSHSTB 122 +#define MACH_TYPE_EPSILON1 123 +#define MACH_TYPE_BALLOON 124 +#define MACH_TYPE_PUPPY 125 +#define MACH_TYPE_ELROY 126 +#define MACH_TYPE_GMS720 127 +#define MACH_TYPE_S24X 128 +#define MACH_TYPE_JTEL_CLEP7312 129 +#define MACH_TYPE_CX821XX 130 +#define MACH_TYPE_EDB7312 131 +#define MACH_TYPE_BSA1110 132 +#define MACH_TYPE_POWERPIN 133 +#define MACH_TYPE_OPENARM 134 +#define MACH_TYPE_WHITECHAPEL 135 +#define MACH_TYPE_H3100 136 +#define MACH_TYPE_H3800 137 +#define MACH_TYPE_BLUE_V1 138 +#define MACH_TYPE_PXA_CERF 139 +#define MACH_TYPE_ARM7TEVB 140 +#define MACH_TYPE_D7400 141 +#define MACH_TYPE_PIRANHA 142 +#define MACH_TYPE_SBCAMELOT 143 +#define MACH_TYPE_KINGS 144 +#define MACH_TYPE_SMDK2400 145 +#define MACH_TYPE_COLLIE 146 +#define MACH_TYPE_IDR 147 +#define MACH_TYPE_BADGE4 148 +#define MACH_TYPE_WEBNET 149 +#define MACH_TYPE_D7300 150 +#define MACH_TYPE_CEP 151 +#define MACH_TYPE_FORTUNET 152 +#define MACH_TYPE_VC547X 153 +#define MACH_TYPE_FILEWALKER 154 +#define MACH_TYPE_NETGATEWAY 155 +#define MACH_TYPE_SYMBOL2800 156 +#define MACH_TYPE_SUNS 157 +#define MACH_TYPE_FRODO 158 +#define MACH_TYPE_MACH_TYTE_MS301 159 +#define MACH_TYPE_MX1ADS 160 +#define MACH_TYPE_H7201 161 +#define MACH_TYPE_H7202 162 +#define MACH_TYPE_AMICO 163 +#define MACH_TYPE_IAM 164 +#define MACH_TYPE_TT530 165 +#define MACH_TYPE_SAM2400 166 +#define MACH_TYPE_JORNADA56X 167 +#define MACH_TYPE_ACTIVE 168 +#define MACH_TYPE_IQ80321 169 +#define MACH_TYPE_WID 170 +#define MACH_TYPE_SABINAL 171 +#define MACH_TYPE_IXP425_MATACUMBE 172 +#define MACH_TYPE_MINIPRINT 173 +#define MACH_TYPE_ADM510X 174 +#define MACH_TYPE_SVS200 175 +#define MACH_TYPE_ATG_TCU 176 +#define MACH_TYPE_JORNADA820 177 +#define MACH_TYPE_S3C44B0 178 +#define MACH_TYPE_MARGIS2 179 +#define MACH_TYPE_KS8695 180 +#define MACH_TYPE_BRH 181 +#define MACH_TYPE_S3C2410 182 +#define MACH_TYPE_POSSIO_PX30 183 +#define MACH_TYPE_S3C2800 184 +#define MACH_TYPE_FLEETWOOD 185 +#define MACH_TYPE_OMAHA 186 +#define MACH_TYPE_TA7 187 +#define MACH_TYPE_NOVA 188 +#define MACH_TYPE_HMK 189 +#define MACH_TYPE_KARO 190 +#define MACH_TYPE_FESTER 191 +#define MACH_TYPE_GPI 192 +#define MACH_TYPE_SMDK2410 193 +#define MACH_TYPE_I519 194 +#define MACH_TYPE_NEXIO 195 +#define MACH_TYPE_BITBOX 196 +#define MACH_TYPE_G200 197 +#define MACH_TYPE_GILL 198 +#define MACH_TYPE_PXA_MERCURY 199 +#define MACH_TYPE_CEIVA 200 +#define MACH_TYPE_FRET 201 +#define MACH_TYPE_EMAILPHONE 202 +#define MACH_TYPE_H3900 203 +#define MACH_TYPE_PXA1 204 +#define MACH_TYPE_KOAN369 205 +#define MACH_TYPE_COGENT 206 +#define MACH_TYPE_ESL_SIMPUTER 207 +#define MACH_TYPE_ESL_SIMPUTER_CLR 208 +#define MACH_TYPE_ESL_SIMPUTER_BW 209 +#define MACH_TYPE_HHP_CRADLE 210 +#define MACH_TYPE_HE500 211 +#define MACH_TYPE_INHANDELF2 212 +#define MACH_TYPE_INHANDFTIP 213 +#define MACH_TYPE_DNP1110 214 +#define MACH_TYPE_PNP1110 215 +#define MACH_TYPE_CSB226 216 +#define MACH_TYPE_ARNOLD 217 +#define MACH_TYPE_VOICEBLUE 218 +#define MACH_TYPE_JZ8028 219 +#define MACH_TYPE_H5400 220 +#define MACH_TYPE_FORTE 221 +#define MACH_TYPE_ACAM 222 +#define MACH_TYPE_ABOX 223 +#define MACH_TYPE_ATMEL 224 +#define MACH_TYPE_SITSANG 225 +#define MACH_TYPE_CPU1110LCDNET 226 +#define MACH_TYPE_MPL_VCMA9 227 +#define MACH_TYPE_OPUS_A1 228 +#define MACH_TYPE_DAYTONA 229 +#define MACH_TYPE_KILLBEAR 230 +#define MACH_TYPE_YOHO 231 +#define MACH_TYPE_JASPER 232 +#define MACH_TYPE_DSC25 233 +#define MACH_TYPE_OMAP_INNOVATOR 234 +#define MACH_TYPE_RAMSES 235 +#define MACH_TYPE_S28X 236 +#define MACH_TYPE_MPORT3 237 +#define MACH_TYPE_PXA_EAGLE250 238 +#define MACH_TYPE_PDB 239 +#define MACH_TYPE_BLUE_2G 240 +#define MACH_TYPE_BLUEARCH 241 +#define MACH_TYPE_IXDP2400 242 +#define MACH_TYPE_IXDP2800 243 +#define MACH_TYPE_EXPLORER 244 +#define MACH_TYPE_IXDP425 245 +#define MACH_TYPE_CHIMP 246 +#define MACH_TYPE_STORK_NEST 247 +#define MACH_TYPE_STORK_EGG 248 +#define MACH_TYPE_WISMO 249 +#define MACH_TYPE_EZLINX 250 +#define MACH_TYPE_AT91RM9200 251 +#define MACH_TYPE_ADTECH_ORION 252 +#define MACH_TYPE_NEPTUNE 253 +#define MACH_TYPE_HACKKIT 254 +#define MACH_TYPE_PXA_WINS30 255 +#define MACH_TYPE_LAVINNA 256 +#define MACH_TYPE_PXA_UENGINE 257 +#define MACH_TYPE_INNOKOM 258 +#define MACH_TYPE_BMS 259 +#define MACH_TYPE_IXCDP1100 260 +#define MACH_TYPE_PRPMC1100 261 +#define MACH_TYPE_AT91RM9200DK 262 +#define MACH_TYPE_ARMSTICK 263 +#define MACH_TYPE_ARMONIE 264 +#define MACH_TYPE_MPORT1 265 +#define MACH_TYPE_S3C5410 266 +#define MACH_TYPE_ZCP320A 267 +#define MACH_TYPE_I_BOX 268 +#define MACH_TYPE_STLC1502 269 +#define MACH_TYPE_SIREN 270 +#define MACH_TYPE_GREENLAKE 271 +#define MACH_TYPE_ARGUS 272 +#define MACH_TYPE_COMBADGE 273 +#define MACH_TYPE_ROKEPXA 274 +#define MACH_TYPE_CINTEGRATOR 275 +#define MACH_TYPE_GUIDEA07 276 +#define MACH_TYPE_TAT257 277 +#define MACH_TYPE_IGP2425 278 +#define MACH_TYPE_BLUEGRAMMA 279 +#define MACH_TYPE_IPOD 280 +#define MACH_TYPE_ADSBITSYX 281 +#define MACH_TYPE_TRIZEPS2 282 +#define MACH_TYPE_VIPER 283 +#define MACH_TYPE_ADSBITSYPLUS 284 +#define MACH_TYPE_ADSAGC 285 +#define MACH_TYPE_STP7312 286 +#define MACH_TYPE_NX_PHNX 287 +#define MACH_TYPE_WEP_EP250 288 +#define MACH_TYPE_INHANDELF3 289 +#define MACH_TYPE_ADI_COYOTE 290 +#define MACH_TYPE_IYONIX 291 +#define MACH_TYPE_DAMICAM_SA1110 292 +#define MACH_TYPE_MEG03 293 +#define MACH_TYPE_PXA_WHITECHAPEL 294 +#define MACH_TYPE_NWSC 295 +#define MACH_TYPE_NWLARM 296 +#define MACH_TYPE_IXP425_MGUARD 297 +#define MACH_TYPE_PXA_NETDCU4 298 +#define MACH_TYPE_IXDP2401 299 +#define MACH_TYPE_IXDP2801 300 +#define MACH_TYPE_ZODIAC 301 +#define MACH_TYPE_ARMMODUL 302 +#define MACH_TYPE_KETOP 303 +#define MACH_TYPE_AV7200 304 +#define MACH_TYPE_ARCH_TI925 305 +#define MACH_TYPE_ACQ200 306 +#define MACH_TYPE_PT_DAFIT 307 +#define MACH_TYPE_IHBA 308 +#define MACH_TYPE_QUINQUE 309 +#define MACH_TYPE_NIMBRAONE 310 +#define MACH_TYPE_NIMBRA29X 311 +#define MACH_TYPE_NIMBRA210 312 +#define MACH_TYPE_HHP_D95XX 313 +#define MACH_TYPE_LABARM 314 +#define MACH_TYPE_M825XX 315 +#define MACH_TYPE_M7100 316 +#define MACH_TYPE_NIPC2 317 +#define MACH_TYPE_FU7202 318 +#define MACH_TYPE_ADSAGX 319 +#define MACH_TYPE_PXA_POOH 320 +#define MACH_TYPE_BANDON 321 +#define MACH_TYPE_PCM7210 322 +#define MACH_TYPE_NMS9200 323 +#define MACH_TYPE_LOGODL 324 +#define MACH_TYPE_M7140 325 +#define MACH_TYPE_KOREBOT 326 +#define MACH_TYPE_IQ31244 327 +#define MACH_TYPE_KOAN393 328 +#define MACH_TYPE_INHANDFTIP3 329 +#define MACH_TYPE_GONZO 330 +#define MACH_TYPE_BAST 331 +#define MACH_TYPE_SCANPASS 332 +#define MACH_TYPE_EP7312_POOH 333 +#define MACH_TYPE_TA7S 334 +#define MACH_TYPE_TA7V 335 +#define MACH_TYPE_ICARUS 336 +#define MACH_TYPE_H1900 337 +#define MACH_TYPE_GEMINI 338 +#define MACH_TYPE_AXIM 339 +#define MACH_TYPE_AUDIOTRON 340 +#define MACH_TYPE_H2200 341 +#define MACH_TYPE_LOOX600 342 +#define MACH_TYPE_NIOP 343 +#define MACH_TYPE_DM310 344 +#define MACH_TYPE_SEEDPXA_C2 345 +#define MACH_TYPE_IXP4XX_MGUARD_PCI 346 +#define MACH_TYPE_H1940 347 +#define MACH_TYPE_SCORPIO 348 +#define MACH_TYPE_VIVA 349 +#define MACH_TYPE_PXA_XCARD 350 +#define MACH_TYPE_CSB335 351 +#define MACH_TYPE_IXRD425 352 +#define MACH_TYPE_IQ80315 353 +#define MACH_TYPE_NMP7312 354 +#define MACH_TYPE_CX861XX 355 +#define MACH_TYPE_ENP2611 356 +#define MACH_TYPE_XDA 357 +#define MACH_TYPE_CSIR_IMS 358 +#define MACH_TYPE_IXP421_DNAEETH 359 +#define MACH_TYPE_POCKETSERV9200 360 +#define MACH_TYPE_TOTO 361 +#define MACH_TYPE_S3C2440 362 +#define MACH_TYPE_KS8695P 363 +#define MACH_TYPE_SE4000 364 +#define MACH_TYPE_QUADRICEPS 365 +#define MACH_TYPE_BRONCO 366 +#define MACH_TYPE_ESL_WIRELESS_TAB 367 +#define MACH_TYPE_ESL_SOFCOMP 368 +#define MACH_TYPE_S5C7375 369 +#define MACH_TYPE_SPEARHEAD 370 +#define MACH_TYPE_PANTERA 371 +#define MACH_TYPE_PRAYOGLITE 372 +#define MACH_TYPE_GUMSTIX 373 +#define MACH_TYPE_RCUBE 374 +#define MACH_TYPE_REA_OLV 375 +#define MACH_TYPE_PXA_IPHONE 376 +#define MACH_TYPE_S3C3410 377 +#define MACH_TYPE_ESPD_4510B 378 +#define MACH_TYPE_MP1X 379 +#define MACH_TYPE_AT91RM9200TB 380 +#define MACH_TYPE_ADSVGX 381 +#define MACH_TYPE_OMAP_H2 382 +#define MACH_TYPE_PELEE 383 +#define MACH_TYPE_E740 384 +#define MACH_TYPE_IQ80331 385 +#define MACH_TYPE_VERSATILE_PB 387 +#define MACH_TYPE_KEV7A400 388 +#define MACH_TYPE_LPD7A400 389 +#define MACH_TYPE_LPD7A404 390 +#define MACH_TYPE_FUJITSU_CAMELOT 391 +#define MACH_TYPE_JANUS2M 392 +#define MACH_TYPE_EMBTF 393 +#define MACH_TYPE_HPM 394 +#define MACH_TYPE_SMDK2410TK 395 +#define MACH_TYPE_SMDK2410AJ 396 +#define MACH_TYPE_STREETRACER 397 +#define MACH_TYPE_EFRAME 398 +#define MACH_TYPE_CSB337 399 +#define MACH_TYPE_PXA_LARK 400 +#define MACH_TYPE_PNP2110 401 +#define MACH_TYPE_TCC72X 402 +#define MACH_TYPE_ALTAIR 403 +#define MACH_TYPE_KC3 404 +#define MACH_TYPE_SINTEFTD 405 +#define MACH_TYPE_MAINSTONE 406 +#define MACH_TYPE_ADAY4X 407 +#define MACH_TYPE_LITE300 408 +#define MACH_TYPE_S5C7376 409 +#define MACH_TYPE_MT02 410 +#define MACH_TYPE_MPORT3S 411 +#define MACH_TYPE_RA_ALPHA 412 +#define MACH_TYPE_XCEP 413 +#define MACH_TYPE_ARCOM_VULCAN 414 +#define MACH_TYPE_STARGATE 415 +#define MACH_TYPE_ARMADILLOJ 416 +#define MACH_TYPE_ELROY_JACK 417 +#define MACH_TYPE_BACKEND 418 +#define MACH_TYPE_S5LINBOX 419 +#define MACH_TYPE_NOMADIK 420 +#define MACH_TYPE_IA_CPU_9200 421 +#define MACH_TYPE_AT91_BJA1 422 +#define MACH_TYPE_CORGI 423 +#define MACH_TYPE_POODLE 424 +#define MACH_TYPE_TEN 425 +#define MACH_TYPE_ROVERP5P 426 +#define MACH_TYPE_SC2700 427 +#define MACH_TYPE_EX_EAGLE 428 +#define MACH_TYPE_NX_PXA12 429 +#define MACH_TYPE_NX_PXA5 430 +#define MACH_TYPE_BLACKBOARD2 431 +#define MACH_TYPE_I819 432 +#define MACH_TYPE_IXMB995E 433 +#define MACH_TYPE_SKYRIDER 434 +#define MACH_TYPE_SKYHAWK 435 +#define MACH_TYPE_ENTERPRISE 436 +#define MACH_TYPE_DEP2410 437 +#define MACH_TYPE_ARMCORE 438 +#define MACH_TYPE_HOBBIT 439 +#define MACH_TYPE_H7210 440 +#define MACH_TYPE_PXA_NETDCU5 441 +#define MACH_TYPE_ACC 442 +#define MACH_TYPE_ESL_SARVA 443 +#define MACH_TYPE_XM250 444 +#define MACH_TYPE_T6TC1XB 445 +#define MACH_TYPE_ESS710 446 +#define MACH_TYPE_MX31ADS 447 +#define MACH_TYPE_HIMALAYA 448 +#define MACH_TYPE_BOLFENK 449 +#define MACH_TYPE_AT91RM9200KR 450 +#define MACH_TYPE_EDB9312 451 +#define MACH_TYPE_OMAP_GENERIC 452 +#define MACH_TYPE_AXIMX3 453 +#define MACH_TYPE_EB67XDIP 454 +#define MACH_TYPE_WEBTXS 455 +#define MACH_TYPE_HAWK 456 +#define MACH_TYPE_CCAT91SBC001 457 +#define MACH_TYPE_EXPRESSO 458 +#define MACH_TYPE_H4000 459 +#define MACH_TYPE_DINO 460 +#define MACH_TYPE_ML675K 461 +#define MACH_TYPE_EDB9301 462 +#define MACH_TYPE_EDB9315 463 +#define MACH_TYPE_RECIVA_TT 464 +#define MACH_TYPE_CSTCB01 465 +#define MACH_TYPE_CSTCB1 466 +#define MACH_TYPE_SHADWELL 467 +#define MACH_TYPE_GOEPEL263 468 +#define MACH_TYPE_ACQ100 469 +#define MACH_TYPE_MX1FS2 470 +#define MACH_TYPE_HIPTOP_G1 471 +#define MACH_TYPE_SPARKY 472 +#define MACH_TYPE_NS9750 473 +#define MACH_TYPE_PHOENIX 474 +#define MACH_TYPE_VR1000 475 +#define MACH_TYPE_DEISTERPXA 476 +#define MACH_TYPE_BCM1160 477 +#define MACH_TYPE_PCM022 478 +#define MACH_TYPE_ADSGCX 479 +#define MACH_TYPE_DREADNAUGHT 480 +#define MACH_TYPE_DM320 481 +#define MACH_TYPE_MARKOV 482 +#define MACH_TYPE_COS7A400 483 +#define MACH_TYPE_MILANO 484 +#define MACH_TYPE_UE9328 485 +#define MACH_TYPE_UEX255 486 +#define MACH_TYPE_UE2410 487 +#define MACH_TYPE_A620 488 +#define MACH_TYPE_OCELOT 489 +#define MACH_TYPE_CHEETAH 490 +#define MACH_TYPE_OMAP_PERSEUS2 491 +#define MACH_TYPE_ZVUE 492 +#define MACH_TYPE_ROVERP1 493 +#define MACH_TYPE_ASIDIAL2 494 +#define MACH_TYPE_S3C24A0 495 +#define MACH_TYPE_E800 496 +#define MACH_TYPE_E750 497 +#define MACH_TYPE_S3C5500 498 +#define MACH_TYPE_SMDK5500 499 +#define MACH_TYPE_SIGNALSYNC 500 +#define MACH_TYPE_NBC 501 +#define MACH_TYPE_KODIAK 502 +#define MACH_TYPE_NETBOOKPRO 503 +#define MACH_TYPE_HW90200 504 +#define MACH_TYPE_CONDOR 505 +#define MACH_TYPE_CUP 506 +#define MACH_TYPE_KITE 507 +#define MACH_TYPE_SCB9328 508 +#define MACH_TYPE_OMAP_H3 509 +#define MACH_TYPE_OMAP_H4 510 +#define MACH_TYPE_N10 511 +#define MACH_TYPE_MONTAJADE 512 +#define MACH_TYPE_SG560 513 +#define MACH_TYPE_DP1000 514 +#define MACH_TYPE_OMAP_OSK 515 +#define MACH_TYPE_RG100V3 516 +#define MACH_TYPE_MX2ADS 517 +#define MACH_TYPE_PXA_KILO 518 +#define MACH_TYPE_IXP4XX_EAGLE 519 +#define MACH_TYPE_TOSA 520 +#define MACH_TYPE_MB2520F 521 +#define MACH_TYPE_EMC1000 522 +#define MACH_TYPE_TIDSC25 523 +#define MACH_TYPE_AKCPMXL 524 +#define MACH_TYPE_AV3XX 525 +#define MACH_TYPE_AVILA 526 +#define MACH_TYPE_PXA_MPM10 527 +#define MACH_TYPE_PXA_KYANITE 528 +#define MACH_TYPE_SGOLD 529 +#define MACH_TYPE_OSCAR 530 +#define MACH_TYPE_EPXA4USB2 531 +#define MACH_TYPE_XSENGINE 532 +#define MACH_TYPE_IP600 533 +#define MACH_TYPE_MCAN2 534 +#define MACH_TYPE_DDI_BLUERIDGE 535 +#define MACH_TYPE_SKYMINDER 536 +#define MACH_TYPE_LPD79520 537 +#define MACH_TYPE_EDB9302 538 +#define MACH_TYPE_HW90340 539 +#define MACH_TYPE_CIP_BOX 540 +#define MACH_TYPE_IVPN 541 +#define MACH_TYPE_RSOC2 542 +#define MACH_TYPE_HUSKY 543 +#define MACH_TYPE_BOXER 544 +#define MACH_TYPE_SHEPHERD 545 +#define MACH_TYPE_AML42800AA 546 +#define MACH_TYPE_LPC2294 548 +#define MACH_TYPE_SWITCHGRASS 549 +#define MACH_TYPE_ENS_CMU 550 +#define MACH_TYPE_MM6_SDB 551 +#define MACH_TYPE_SATURN 552 +#define MACH_TYPE_I30030EVB 553 +#define MACH_TYPE_MXC27530EVB 554 +#define MACH_TYPE_SMDK2800 555 +#define MACH_TYPE_MTWILSON 556 +#define MACH_TYPE_ZITI 557 +#define MACH_TYPE_GRANDFATHER 558 +#define MACH_TYPE_TENGINE 559 +#define MACH_TYPE_S3C2460 560 +#define MACH_TYPE_PDM 561 +#define MACH_TYPE_H4700 562 +#define MACH_TYPE_H6300 563 +#define MACH_TYPE_RZ1700 564 +#define MACH_TYPE_A716 565 +#define MACH_TYPE_ESTK2440A 566 +#define MACH_TYPE_ATWIXP425 567 +#define MACH_TYPE_CSB336 568 +#define MACH_TYPE_RIRM2 569 +#define MACH_TYPE_CX23518 570 +#define MACH_TYPE_CX2351X 571 +#define MACH_TYPE_COMPUTIME 572 +#define MACH_TYPE_IZARUS 573 +#define MACH_TYPE_RTS 574 +#define MACH_TYPE_SE5100 575 +#define MACH_TYPE_S3C2510 576 +#define MACH_TYPE_CSB437TL 577 +#define MACH_TYPE_SLAUSON 578 +#define MACH_TYPE_PEARLRIVER 579 +#define MACH_TYPE_TDC_P210 580 +#define MACH_TYPE_SG580 581 +#define MACH_TYPE_WRSBCARM7 582 +#define MACH_TYPE_IPD 583 +#define MACH_TYPE_PXA_DNP2110 584 +#define MACH_TYPE_XAENIAX 585 +#define MACH_TYPE_SOMN4250 586 +#define MACH_TYPE_PLEB2 587 +#define MACH_TYPE_CORNWALLIS 588 +#define MACH_TYPE_GURNEY_DRV 589 +#define MACH_TYPE_CHAFFEE 590 +#define MACH_TYPE_RMS101 591 +#define MACH_TYPE_RX3715 592 +#define MACH_TYPE_SWIFT 593 +#define MACH_TYPE_ROVERP7 594 +#define MACH_TYPE_PR818S 595 +#define MACH_TYPE_TRXPRO 596 +#define MACH_TYPE_NSLU2 597 +#define MACH_TYPE_E400 598 +#define MACH_TYPE_TRAB 599 +#define MACH_TYPE_CMC_PU2 600 +#define MACH_TYPE_FULCRUM 601 +#define MACH_TYPE_NETGATE42X 602 +#define MACH_TYPE_STR710 603 +#define MACH_TYPE_IXDPG425 604 +#define MACH_TYPE_TOMTOMGO 605 +#define MACH_TYPE_VERSATILE_AB 606 +#define MACH_TYPE_EDB9307 607 +#define MACH_TYPE_SG565 608 +#define MACH_TYPE_LPD79524 609 +#define MACH_TYPE_LPD79525 610 +#define MACH_TYPE_RMS100 611 +#define MACH_TYPE_KB9200 612 +#define MACH_TYPE_SX1 613 +#define MACH_TYPE_HMS39C7092 614 +#define MACH_TYPE_ARMADILLO 615 +#define MACH_TYPE_IPCU 616 +#define MACH_TYPE_LOOX720 617 +#define MACH_TYPE_IXDP465 618 +#define MACH_TYPE_IXDP2351 619 +#define MACH_TYPE_ADSVIX 620 +#define MACH_TYPE_DM270 621 +#define MACH_TYPE_SOCLTPLUS 622 +#define MACH_TYPE_ECIA 623 +#define MACH_TYPE_CM4008 624 +#define MACH_TYPE_P2001 625 +#define MACH_TYPE_MUDSHARK 627 +#define MACH_TYPE_HB2 628 +#define MACH_TYPE_IQ80332 629 +#define MACH_TYPE_SENDT 630 +#define MACH_TYPE_MX2JAZZ 631 +#define MACH_TYPE_MULTIIO 632 +#define MACH_TYPE_HRDISPLAY 633 +#define MACH_TYPE_MXC27530ADS 634 +#define MACH_TYPE_TRIZEPS3 635 +#define MACH_TYPE_ZEFEERDZA 636 +#define MACH_TYPE_ZEFEERDZB 637 +#define MACH_TYPE_ZEFEERDZG 638 +#define MACH_TYPE_ZEFEERDZN 639 +#define MACH_TYPE_ZEFEERDZQ 640 +#define MACH_TYPE_GTWX5715 641 +#define MACH_TYPE_ASTRO_JACK 643 +#define MACH_TYPE_TIP03 644 +#define MACH_TYPE_A9200EC 645 +#define MACH_TYPE_PNX0105 646 +#define MACH_TYPE_ADCPOECPU 647 +#define MACH_TYPE_CSB637 648 +#define MACH_TYPE_MB9200 650 +#define MACH_TYPE_KULUN 651 +#define MACH_TYPE_SNAPPER 652 +#define MACH_TYPE_OPTIMA 653 +#define MACH_TYPE_DLHSBC 654 +#define MACH_TYPE_X30 655 +#define MACH_TYPE_N30 656 +#define MACH_TYPE_MANGA_KS8695 657 +#define MACH_TYPE_AJAX 658 +#define MACH_TYPE_NEC_MP900 659 +#define MACH_TYPE_VVTK1000 661 +#define MACH_TYPE_KAFA 662 +#define MACH_TYPE_VVTK3000 663 +#define MACH_TYPE_PIMX1 664 +#define MACH_TYPE_OLLIE 665 +#define MACH_TYPE_SKYMAX 666 +#define MACH_TYPE_JAZZ 667 +#define MACH_TYPE_TEL_T3 668 +#define MACH_TYPE_AISINO_FCR255 669 +#define MACH_TYPE_BTWEB 670 +#define MACH_TYPE_DBG_LH79520 671 +#define MACH_TYPE_CM41XX 672 +#define MACH_TYPE_TS72XX 673 +#define MACH_TYPE_NGGPXA 674 +#define MACH_TYPE_CSB535 675 +#define MACH_TYPE_CSB536 676 +#define MACH_TYPE_PXA_TRAKPOD 677 +#define MACH_TYPE_PRAXIS 678 +#define MACH_TYPE_LH75411 679 +#define MACH_TYPE_OTOM 680 +#define MACH_TYPE_NEXCODER_2440 681 +#define MACH_TYPE_LOOX410 682 +#define MACH_TYPE_WESTLAKE 683 +#define MACH_TYPE_NSB 684 +#define MACH_TYPE_ESL_SARVA_STN 685 +#define MACH_TYPE_ESL_SARVA_TFT 686 +#define MACH_TYPE_ESL_SARVA_IAD 687 +#define MACH_TYPE_ESL_SARVA_ACC 688 +#define MACH_TYPE_TYPHOON 689 +#define MACH_TYPE_CNAV 690 +#define MACH_TYPE_A730 691 +#define MACH_TYPE_NETSTAR 692 +#define MACH_TYPE_PHASEFALE_SUPERCON 693 +#define MACH_TYPE_SHIVA1100 694 +#define MACH_TYPE_ETEXSC 695 +#define MACH_TYPE_IXDPG465 696 +#define MACH_TYPE_A9M2410 697 +#define MACH_TYPE_A9M2440 698 +#define MACH_TYPE_A9M9750 699 +#define MACH_TYPE_A9M9360 700 +#define MACH_TYPE_UNC90 701 +#define MACH_TYPE_ECO920 702 +#define MACH_TYPE_SATVIEW 703 +#define MACH_TYPE_ROADRUNNER 704 +#define MACH_TYPE_AT91RM9200EK 705 +#define MACH_TYPE_GP32 706 +#define MACH_TYPE_GEM 707 +#define MACH_TYPE_I858 708 +#define MACH_TYPE_HX2750 709 +#define MACH_TYPE_MXC91131EVB 710 +#define MACH_TYPE_P700 711 +#define MACH_TYPE_CPE 712 +#define MACH_TYPE_SPITZ 713 +#define MACH_TYPE_NIMBRA340 714 +#define MACH_TYPE_LPC22XX 715 +#define MACH_TYPE_COMET3 716 +#define MACH_TYPE_COMET4 717 +#define MACH_TYPE_CSB625 718 +#define MACH_TYPE_FORTUNET2 719 +#define MACH_TYPE_S5H2200 720 +#define MACH_TYPE_OPTORM920 721 +#define MACH_TYPE_ADSBITSYXB 722 +#define MACH_TYPE_ADSSPHERE 723 +#define MACH_TYPE_ADSPORTAL 724 +#define MACH_TYPE_LN2410SBC 725 +#define MACH_TYPE_CB3RUFC 726 +#define MACH_TYPE_MP2USB 727 +#define MACH_TYPE_NTNP425C 728 +#define MACH_TYPE_COLIBRI 729 +#define MACH_TYPE_PCM7220 730 +#define MACH_TYPE_GATEWAY7001 731 +#define MACH_TYPE_PCM027 732 +#define MACH_TYPE_CMPXA 733 +#define MACH_TYPE_ANUBIS 734 +#define MACH_TYPE_ITE8152 735 +#define MACH_TYPE_LPC3XXX 736 +#define MACH_TYPE_PUPPETEER 737 +#define MACH_TYPE_E570 739 +#define MACH_TYPE_X50 740 +#define MACH_TYPE_RECON 741 +#define MACH_TYPE_XBOARDGP8 742 +#define MACH_TYPE_FPIC2 743 +#define MACH_TYPE_AKITA 744 +#define MACH_TYPE_A81 745 +#define MACH_TYPE_SVM_SC25X 746 +#define MACH_TYPE_VADATECH020 747 +#define MACH_TYPE_TLI 748 +#define MACH_TYPE_EDB9315LC 749 +#define MACH_TYPE_PASSEC 750 +#define MACH_TYPE_DS_TIGER 751 +#define MACH_TYPE_E310 752 +#define MACH_TYPE_E330 753 +#define MACH_TYPE_RT3000 754 +#define MACH_TYPE_NOKIA770 755 +#define MACH_TYPE_PNX0106 756 +#define MACH_TYPE_HX21XX 757 +#define MACH_TYPE_FARADAY 758 +#define MACH_TYPE_SBC9312 759 +#define MACH_TYPE_BATMAN 760 +#define MACH_TYPE_JPD201 761 +#define MACH_TYPE_MIPSA 762 +#define MACH_TYPE_KACOM 763 +#define MACH_TYPE_SWARCOCPU 764 +#define MACH_TYPE_SWARCODSL 765 +#define MACH_TYPE_BLUEANGEL 766 +#define MACH_TYPE_HAIRYGRAMA 767 +#define MACH_TYPE_BANFF 768 +#define MACH_TYPE_CARMEVA 769 +#define MACH_TYPE_SAM255 770 +#define MACH_TYPE_PPM10 771 +#define MACH_TYPE_EDB9315A 772 +#define MACH_TYPE_SUNSET 773 +#define MACH_TYPE_STARGATE2 774 +#define MACH_TYPE_INTELMOTE2 775 +#define MACH_TYPE_TRIZEPS4 776 +#define MACH_TYPE_MAINSTONE2 777 +#define MACH_TYPE_EZ_IXP42X 778 +#define MACH_TYPE_TAPWAVE_ZODIAC 779 +#define MACH_TYPE_UNIVERSALMETER 780 +#define MACH_TYPE_HICOARM9 781 +#define MACH_TYPE_PNX4008 782 +#define MACH_TYPE_KWS6000 783 +#define MACH_TYPE_PORTUX920T 784 +#define MACH_TYPE_EZ_X5 785 +#define MACH_TYPE_OMAP_RUDOLPH 786 +#define MACH_TYPE_CPUAT91 787 +#define MACH_TYPE_REA9200 788 +#define MACH_TYPE_ACTS_PUNE_SA1110 789 +#define MACH_TYPE_IXP425 790 +#define MACH_TYPE_I30030ADS 791 +#define MACH_TYPE_PERCH 792 +#define MACH_TYPE_EIS05R1 793 +#define MACH_TYPE_PEPPERPAD 794 +#define MACH_TYPE_SB3010 795 +#define MACH_TYPE_RM9200 796 +#define MACH_TYPE_DMA03 797 +#define MACH_TYPE_ROAD_S101 798 +#define MACH_TYPE_IQ81340SC 799 +#define MACH_TYPE_IQ_NEXTGEN_B 800 +#define MACH_TYPE_IQ81340MC 801 +#define MACH_TYPE_IQ_NEXTGEN_D 802 +#define MACH_TYPE_IQ_NEXTGEN_E 803 +#define MACH_TYPE_MALLOW_AT91 804 +#define MACH_TYPE_CYBERTRACKER_I 805 +#define MACH_TYPE_GESBC931X 806 +#define MACH_TYPE_CENTIPAD 807 +#define MACH_TYPE_ARMSOC 808 +#define MACH_TYPE_SE4200 809 +#define MACH_TYPE_EMS197A 810 +#define MACH_TYPE_MICRO9 811 +#define MACH_TYPE_MICRO9L 812 +#define MACH_TYPE_UC5471DSP 813 +#define MACH_TYPE_SJ5471ENG 814 +#define MACH_TYPE_CMPXA26X 815 +#define MACH_TYPE_NC 816 +#define MACH_TYPE_OMAP_PALMTE 817 +#define MACH_TYPE_AJAX52X 818 +#define MACH_TYPE_SIRIUSTAR 819 +#define MACH_TYPE_IODATA_HDLG 820 +#define MACH_TYPE_AT91RM9200UTL 821 +#define MACH_TYPE_BIOSAFE 822 +#define MACH_TYPE_MP1000 823 +#define MACH_TYPE_PARSY 824 +#define MACH_TYPE_CCXP 825 +#define MACH_TYPE_OMAP_GSAMPLE 826 +#define MACH_TYPE_REALVIEW_EB 827 +#define MACH_TYPE_SAMOA 828 +#define MACH_TYPE_PALMT3 829 +#define MACH_TYPE_I878 830 +#define MACH_TYPE_BORZOI 831 +#define MACH_TYPE_GECKO 832 +#define MACH_TYPE_DS101 833 +#define MACH_TYPE_OMAP_PALMTT2 834 +#define MACH_TYPE_PALMLD 835 +#define MACH_TYPE_CC9C 836 +#define MACH_TYPE_SBC1670 837 +#define MACH_TYPE_IXDP28X5 838 +#define MACH_TYPE_OMAP_PALMTT 839 +#define MACH_TYPE_ML696K 840 +#define MACH_TYPE_ARCOM_ZEUS 841 +#define MACH_TYPE_OSIRIS 842 +#define MACH_TYPE_MAESTRO 843 +#define MACH_TYPE_PALMTE2 844 +#define MACH_TYPE_IXBBM 845 +#define MACH_TYPE_MX27ADS 846 +#define MACH_TYPE_AX8004 847 +#define MACH_TYPE_AT91SAM9261EK 848 +#define MACH_TYPE_LOFT 849 +#define MACH_TYPE_MAGPIE 850 +#define MACH_TYPE_MX21ADS 851 +#define MACH_TYPE_MB87M3400 852 +#define MACH_TYPE_MGUARD_DELTA 853 +#define MACH_TYPE_DAVINCI_DVDP 854 +#define MACH_TYPE_HTCUNIVERSAL 855 +#define MACH_TYPE_TPAD 856 +#define MACH_TYPE_ROVERP3 857 +#define MACH_TYPE_JORNADA928 858 +#define MACH_TYPE_MV88FXX81 859 +#define MACH_TYPE_STMP36XX 860 +#define MACH_TYPE_SXNI79524 861 +#define MACH_TYPE_AMS_DELTA 862 +#define MACH_TYPE_URANIUM 863 +#define MACH_TYPE_UCON 864 +#define MACH_TYPE_NAS100D 865 +#define MACH_TYPE_L083_1000 866 +#define MACH_TYPE_EZX 867 +#define MACH_TYPE_PNX5220 868 +#define MACH_TYPE_BUTTE 869 +#define MACH_TYPE_SRM2 870 +#define MACH_TYPE_DSBR 871 +#define MACH_TYPE_CRYSTALBALL 872 +#define MACH_TYPE_TINYPXA27X 873 +#define MACH_TYPE_HERBIE 874 +#define MACH_TYPE_MAGICIAN 875 +#define MACH_TYPE_CM4002 876 +#define MACH_TYPE_B4 877 +#define MACH_TYPE_MAUI 878 +#define MACH_TYPE_CYBERTRACKER_G 879 +#define MACH_TYPE_NXDKN 880 +#define MACH_TYPE_MIO8390 881 +#define MACH_TYPE_OMI_BOARD 882 +#define MACH_TYPE_MX21CIV 883 +#define MACH_TYPE_MAHI_CDAC 884 +#define MACH_TYPE_PALMTX 885 +#define MACH_TYPE_S3C2413 887 +#define MACH_TYPE_SAMSYS_EP0 888 +#define MACH_TYPE_WG302V1 889 +#define MACH_TYPE_WG302V2 890 +#define MACH_TYPE_EB42X 891 +#define MACH_TYPE_IQ331ES 892 +#define MACH_TYPE_COSYDSP 893 +#define MACH_TYPE_UPLAT7D 894 +#define MACH_TYPE_PTDAVINCI 895 +#define MACH_TYPE_MBUS 896 +#define MACH_TYPE_NADIA2VB 897 +#define MACH_TYPE_R1000 898 +#define MACH_TYPE_HW90250 899 +#define MACH_TYPE_OMAP_2430SDP 900 +#define MACH_TYPE_DAVINCI_EVM 901 +#define MACH_TYPE_OMAP_TORNADO 902 +#define MACH_TYPE_OLOCREEK 903 +#define MACH_TYPE_PALMZ72 904 +#define MACH_TYPE_NXDB500 905 +#define MACH_TYPE_APF9328 906 +#define MACH_TYPE_OMAP_WIPOQ 907 +#define MACH_TYPE_OMAP_TWIP 908 +#define MACH_TYPE_TREO650 909 +#define MACH_TYPE_ACUMEN 910 +#define MACH_TYPE_XP100 911 +#define MACH_TYPE_FS2410 912 +#define MACH_TYPE_PXA270_CERF 913 +#define MACH_TYPE_SQ2FTLPALM 914 +#define MACH_TYPE_BSEMSERVER 915 +#define MACH_TYPE_NETCLIENT 916 +#define MACH_TYPE_PALMT5 917 +#define MACH_TYPE_PALMTC 918 +#define MACH_TYPE_OMAP_APOLLON 919 +#define MACH_TYPE_MXC30030EVB 920 +#define MACH_TYPE_REA_2D 921 +#define MACH_TYPE_TI3E524 922 +#define MACH_TYPE_ATEB9200 923 +#define MACH_TYPE_AUCKLAND 924 +#define MACH_TYPE_AK3320M 925 +#define MACH_TYPE_DURAMAX 926 +#define MACH_TYPE_N35 927 +#define MACH_TYPE_PRONGHORN 928 +#define MACH_TYPE_FUNDY 929 +#define MACH_TYPE_LOGICPD_PXA270 930 +#define MACH_TYPE_CPU777 931 +#define MACH_TYPE_SIMICON9201 932 +#define MACH_TYPE_LEAP2_HPM 933 +#define MACH_TYPE_CM922TXA10 934 +#define MACH_TYPE_PXA 935 +#define MACH_TYPE_SANDGATE2 936 +#define MACH_TYPE_SANDGATE2G 937 +#define MACH_TYPE_SANDGATE2P 938 +#define MACH_TYPE_FRED_JACK 939 +#define MACH_TYPE_TTG_COLOR1 940 +#define MACH_TYPE_NXEB500HMI 941 +#define MACH_TYPE_NETDCU8 942 +#define MACH_TYPE_NG_FVX538 944 +#define MACH_TYPE_NG_FVS338 945 +#define MACH_TYPE_PNX4103 946 +#define MACH_TYPE_HESDB 947 +#define MACH_TYPE_XSILO 948 +#define MACH_TYPE_ESPRESSO 949 +#define MACH_TYPE_EMLC 950 +#define MACH_TYPE_SISTERON 951 +#define MACH_TYPE_RX1950 952 +#define MACH_TYPE_TSC_VENUS 953 +#define MACH_TYPE_DS101J 954 +#define MACH_TYPE_MXC30030ADS 955 +#define MACH_TYPE_FUJITSU_WIMAXSOC 956 +#define MACH_TYPE_DUALPCMODEM 957 +#define MACH_TYPE_GESBC9312 958 +#define MACH_TYPE_HTCAPACHE 959 +#define MACH_TYPE_IXDP435 960 +#define MACH_TYPE_CATPROVT100 961 +#define MACH_TYPE_PICOTUX1XX 962 +#define MACH_TYPE_PICOTUX2XX 963 +#define MACH_TYPE_DSMG600 964 +#define MACH_TYPE_EMPC2 965 +#define MACH_TYPE_VENTURA 966 +#define MACH_TYPE_PHIDGET_SBC 967 +#define MACH_TYPE_IJ3K 968 +#define MACH_TYPE_PISGAH 969 +#define MACH_TYPE_OMAP_FSAMPLE 970 +#define MACH_TYPE_SG720 971 +#define MACH_TYPE_REDFOX 972 +#define MACH_TYPE_MYSH_EP9315_1 973 +#define MACH_TYPE_TPF106 974 +#define MACH_TYPE_AT91RM9200KG 975 +#define MACH_TYPE_SLEDB 976 +#define MACH_TYPE_ONTRACK 977 +#define MACH_TYPE_PM1200 978 +#define MACH_TYPE_ESS24XXX 979 +#define MACH_TYPE_COREMP7 980 +#define MACH_TYPE_NEXCODER_6446 981 +#define MACH_TYPE_STVC8380 982 +#define MACH_TYPE_TEKLYNX 983 +#define MACH_TYPE_CARBONADO 984 +#define MACH_TYPE_SYSMOS_MP730 985 +#define MACH_TYPE_SNAPPER_CL15 986 +#define MACH_TYPE_PGIGIM 987 +#define MACH_TYPE_PTX9160P2 988 +#define MACH_TYPE_DCORE1 989 +#define MACH_TYPE_VICTORPXA 990 +#define MACH_TYPE_MX2DTB 991 +#define MACH_TYPE_PXA_IREX_ER0100 992 +#define MACH_TYPE_OMAP_PALMZ71 993 +#define MACH_TYPE_BARTEC_DEG 994 +#define MACH_TYPE_HW50251 995 +#define MACH_TYPE_IBOX 996 +#define MACH_TYPE_ATLASLH7A404 997 +#define MACH_TYPE_PT2026 998 +#define MACH_TYPE_HTCALPINE 999 +#define MACH_TYPE_BARTEC_VTU 1000 +#define MACH_TYPE_VCOREII 1001 +#define MACH_TYPE_PDNB3 1002 +#define MACH_TYPE_HTCBEETLES 1003 +#define MACH_TYPE_S3C6400 1004 +#define MACH_TYPE_S3C2443 1005 +#define MACH_TYPE_OMAP_LDK 1006 +#define MACH_TYPE_SMDK2460 1007 +#define MACH_TYPE_SMDK2440 1008 +#define MACH_TYPE_SMDK2412 1009 +#define MACH_TYPE_WEBBOX 1010 +#define MACH_TYPE_CWWNDP 1011 +#define MACH_TYPE_DRAGON 1012 +#define MACH_TYPE_OPENDO_CPU_BOARD 1013 +#define MACH_TYPE_CCM2200 1014 +#define MACH_TYPE_ETWARM 1015 +#define MACH_TYPE_M93030 1016 +#define MACH_TYPE_CC7U 1017 +#define MACH_TYPE_MTT_RANGER 1018 +#define MACH_TYPE_NEXUS 1019 +#define MACH_TYPE_DESMAN 1020 +#define MACH_TYPE_BKDE303 1021 +#define MACH_TYPE_SMDK2413 1022 +#define MACH_TYPE_AML_M7200 1023 +#define MACH_TYPE_AML_M5900 1024 +#define MACH_TYPE_SG640 1025 +#define MACH_TYPE_EDG79524 1026 +#define MACH_TYPE_AI2410 1027 +#define MACH_TYPE_IXP465 1028 +#define MACH_TYPE_BALLOON3 1029 +#define MACH_TYPE_HEINS 1030 +#define MACH_TYPE_MPLUSEVA 1031 +#define MACH_TYPE_RT042 1032 +#define MACH_TYPE_CWIEM 1033 +#define MACH_TYPE_CM_X270 1034 +#define MACH_TYPE_CM_X255 1035 +#define MACH_TYPE_ESH_AT91 1036 +#define MACH_TYPE_SANDGATE3 1037 +#define MACH_TYPE_PRIMO 1038 +#define MACH_TYPE_GEMSTONE 1039 +#define MACH_TYPE_PRONGHORNMETRO 1040 +#define MACH_TYPE_SIDEWINDER 1041 +#define MACH_TYPE_PICOMOD1 1042 +#define MACH_TYPE_SG590 1043 +#define MACH_TYPE_AKAI9307 1044 +#define MACH_TYPE_FONTAINE 1045 +#define MACH_TYPE_WOMBAT 1046 +#define MACH_TYPE_ACQ300 1047 +#define MACH_TYPE_MOD_270 1048 +#define MACH_TYPE_VC0820 1049 +#define MACH_TYPE_ANI_AIM 1050 +#define MACH_TYPE_JELLYFISH 1051 +#define MACH_TYPE_AMANITA 1052 +#define MACH_TYPE_VLINK 1053 +#define MACH_TYPE_DEXFLEX 1054 +#define MACH_TYPE_EIGEN_TTQ 1055 +#define MACH_TYPE_ARCOM_TITAN 1056 +#define MACH_TYPE_TABLA 1057 +#define MACH_TYPE_MDIRAC3 1058 +#define MACH_TYPE_MRHFBP2 1059 +#define MACH_TYPE_AT91RM9200RB 1060 +#define MACH_TYPE_ANI_APM 1061 +#define MACH_TYPE_ELLA1 1062 +#define MACH_TYPE_INHAND_PXA27X 1063 +#define MACH_TYPE_INHAND_PXA25X 1064 +#define MACH_TYPE_EMPOS_XM 1065 +#define MACH_TYPE_EMPOS 1066 +#define MACH_TYPE_EMPOS_TINY 1067 +#define MACH_TYPE_EMPOS_SM 1068 +#define MACH_TYPE_EGRET 1069 +#define MACH_TYPE_OSTRICH 1070 +#define MACH_TYPE_N50 1071 +#define MACH_TYPE_ECBAT91 1072 +#define MACH_TYPE_STAREAST 1073 +#define MACH_TYPE_DSPG_DW 1074 +#define MACH_TYPE_ONEARM 1075 +#define MACH_TYPE_MRG110_6 1076 +#define MACH_TYPE_WRT300NV2 1077 +#define MACH_TYPE_XM_BULVERDE 1078 +#define MACH_TYPE_MSM6100 1079 +#define MACH_TYPE_ETI_B1 1080 +#define MACH_TYPE_ZILOG_ZA9L 1081 +#define MACH_TYPE_BIT2440 1082 +#define MACH_TYPE_NBI 1083 +#define MACH_TYPE_SMDK2443 1084 +#define MACH_TYPE_VDAVINCI 1085 +#define MACH_TYPE_ATC6 1086 +#define MACH_TYPE_MULTMDW 1087 +#define MACH_TYPE_MBA2440 1088 +#define MACH_TYPE_ECSD 1089 +#define MACH_TYPE_PALMZ31 1090 +#define MACH_TYPE_FSG 1091 +#define MACH_TYPE_RAZOR101 1092 +#define MACH_TYPE_OPERA_TDM 1093 +#define MACH_TYPE_COMCERTO 1094 +#define MACH_TYPE_TB0319 1095 +#define MACH_TYPE_KWS8000 1096 +#define MACH_TYPE_B2 1097 +#define MACH_TYPE_LCL54 1098 +#define MACH_TYPE_AT91SAM9260EK 1099 +#define MACH_TYPE_GLANTANK 1100 +#define MACH_TYPE_N2100 1101 +#define MACH_TYPE_N4100 1102 +#define MACH_TYPE_VERTICAL_RSC4 1103 +#define MACH_TYPE_SG8100 1104 +#define MACH_TYPE_IM42XX 1105 +#define MACH_TYPE_FTXX 1106 +#define MACH_TYPE_LWFUSION 1107 +#define MACH_TYPE_QT2410 1108 +#define MACH_TYPE_KIXRP435 1109 +#define MACH_TYPE_CCW9C 1110 +#define MACH_TYPE_DABHS 1111 +#define MACH_TYPE_GZMX 1112 +#define MACH_TYPE_IPNW100AP 1113 +#define MACH_TYPE_CC9P9360DEV 1114 +#define MACH_TYPE_CC9P9750DEV 1115 +#define MACH_TYPE_CC9P9360VAL 1116 +#define MACH_TYPE_CC9P9750VAL 1117 +#define MACH_TYPE_NX70V 1118 +#define MACH_TYPE_AT91RM9200DF 1119 +#define MACH_TYPE_SE_PILOT2 1120 +#define MACH_TYPE_MTCN_T800 1121 +#define MACH_TYPE_VCMX212 1122 +#define MACH_TYPE_LYNX 1123 +#define MACH_TYPE_AT91SAM9260ID 1124 +#define MACH_TYPE_HW86052 1125 +#define MACH_TYPE_PILZ_PMI3 1126 +#define MACH_TYPE_EDB9302A 1127 +#define MACH_TYPE_EDB9307A 1128 +#define MACH_TYPE_CT_DFS 1129 +#define MACH_TYPE_PILZ_PMI4 1130 +#define MACH_TYPE_XCEEDNP_IXP 1131 +#define MACH_TYPE_SMDK2442B 1132 +#define MACH_TYPE_XNODE 1133 +#define MACH_TYPE_AIDX270 1134 +#define MACH_TYPE_REMA 1135 +#define MACH_TYPE_BPS1000 1136 +#define MACH_TYPE_HW90350 1137 +#define MACH_TYPE_OMAP_3430SDP 1138 +#define MACH_TYPE_BLUETOUCH 1139 +#define MACH_TYPE_VSTMS 1140 +#define MACH_TYPE_XSBASE270 1141 +#define MACH_TYPE_AT91SAM9260EK_CN 1142 +#define MACH_TYPE_ADSTURBOXB 1143 +#define MACH_TYPE_OTI4110 1144 +#define MACH_TYPE_HME_PXA 1145 +#define MACH_TYPE_DEISTERDCA 1146 +#define MACH_TYPE_CES_SSEM2 1147 +#define MACH_TYPE_CES_MTR 1148 +#define MACH_TYPE_TDS_AVNG_SBC 1149 +#define MACH_TYPE_EVEREST 1150 +#define MACH_TYPE_PNX4010 1151 +#define MACH_TYPE_OXNAS 1152 +#define MACH_TYPE_FIORI 1153 +#define MACH_TYPE_ML1200 1154 +#define MACH_TYPE_PECOS 1155 +#define MACH_TYPE_NB2XXX 1156 +#define MACH_TYPE_HW6900 1157 +#define MACH_TYPE_CDCS_QUOLL 1158 +#define MACH_TYPE_QUICKSILVER 1159 +#define MACH_TYPE_UPLAT926 1160 +#define MACH_TYPE_DEP2410_THOMAS 1161 +#define MACH_TYPE_DTK2410 1162 +#define MACH_TYPE_CHILI 1163 +#define MACH_TYPE_DEMETER 1164 +#define MACH_TYPE_DIONYSUS 1165 +#define MACH_TYPE_AS352X 1166 +#define MACH_TYPE_SERVICE 1167 +#define MACH_TYPE_CS_E9301 1168 +#define MACH_TYPE_MICRO9M 1169 +#define MACH_TYPE_IA_MOSPCK 1170 +#define MACH_TYPE_QL201B 1171 +#define MACH_TYPE_BBM 1174 +#define MACH_TYPE_EXXX 1175 +#define MACH_TYPE_WMA11B 1176 +#define MACH_TYPE_PELCO_ATLAS 1177 +#define MACH_TYPE_G500 1178 +#define MACH_TYPE_BUG 1179 +#define MACH_TYPE_MX33ADS 1180 +#define MACH_TYPE_CHUB 1181 +#define MACH_TYPE_NEO1973_GTA01 1182 +#define MACH_TYPE_W90N740 1183 +#define MACH_TYPE_MEDALLION_SA2410 1184 +#define MACH_TYPE_IA_CPU_9200_2 1185 +#define MACH_TYPE_DIMMRM9200 1186 +#define MACH_TYPE_PM9261 1187 +#define MACH_TYPE_ML7304 1189 +#define MACH_TYPE_UCP250 1190 +#define MACH_TYPE_INTBOARD 1191 +#define MACH_TYPE_GULFSTREAM 1192 +#define MACH_TYPE_LABQUEST 1193 +#define MACH_TYPE_VCMX313 1194 +#define MACH_TYPE_URG200 1195 +#define MACH_TYPE_CPUX255LCDNET 1196 +#define MACH_TYPE_NETDCU9 1197 +#define MACH_TYPE_NETDCU10 1198 +#define MACH_TYPE_DSPG_DGA 1199 +#define MACH_TYPE_DSPG_DVW 1200 +#define MACH_TYPE_SOLOS 1201 +#define MACH_TYPE_AT91SAM9263EK 1202 +#define MACH_TYPE_OSSTBOX 1203 +#define MACH_TYPE_KBAT9261 1204 +#define MACH_TYPE_CT1100 1205 +#define MACH_TYPE_AKCPPXA 1206 +#define MACH_TYPE_OCHAYA1020 1207 +#define MACH_TYPE_HITRACK 1208 +#define MACH_TYPE_SYME1 1209 +#define MACH_TYPE_SYHL1 1210 +#define MACH_TYPE_EMPCA400 1211 +#define MACH_TYPE_EM7210 1212 +#define MACH_TYPE_HTCHERMES 1213 +#define MACH_TYPE_ETI_C1 1214 +#define MACH_TYPE_AC100 1216 +#define MACH_TYPE_SNEETCH 1217 +#define MACH_TYPE_STUDENTMATE 1218 +#define MACH_TYPE_ZIR2410 1219 +#define MACH_TYPE_ZIR2413 1220 +#define MACH_TYPE_DLONIP3 1221 +#define MACH_TYPE_INSTREAM 1222 +#define MACH_TYPE_AMBARELLA 1223 +#define MACH_TYPE_NEVIS 1224 +#define MACH_TYPE_HTC_TRINITY 1225 +#define MACH_TYPE_QL202B 1226 +#define MACH_TYPE_VPAC270 1227 +#define MACH_TYPE_RD129 1228 +#define MACH_TYPE_HTCWIZARD 1229 +#define MACH_TYPE_TREO680 1230 +#define MACH_TYPE_TECON_TMEZON 1231 +#define MACH_TYPE_ZYLONITE 1233 +#define MACH_TYPE_GENE1270 1234 +#define MACH_TYPE_ZIR2412 1235 +#define MACH_TYPE_MX31LITE 1236 +#define MACH_TYPE_T700WX 1237 +#define MACH_TYPE_VF100 1238 +#define MACH_TYPE_NSB2 1239 +#define MACH_TYPE_NXHMI_BB 1240 +#define MACH_TYPE_NXHMI_RE 1241 +#define MACH_TYPE_N4100PRO 1242 +#define MACH_TYPE_SAM9260 1243 +#define MACH_TYPE_OMAP_TREO600 1244 +#define MACH_TYPE_INDY2410 1245 +#define MACH_TYPE_NELT_A 1246 +#define MACH_TYPE_N311 1248 +#define MACH_TYPE_AT91SAM9260VGK 1249 +#define MACH_TYPE_AT91LEPPE 1250 +#define MACH_TYPE_AT91LEPCCN 1251 +#define MACH_TYPE_APC7100 1252 +#define MACH_TYPE_STARGAZER 1253 +#define MACH_TYPE_SONATA 1254 +#define MACH_TYPE_SCHMOOGIE 1255 +#define MACH_TYPE_AZTOOL 1256 +#define MACH_TYPE_MIOA701 1257 +#define MACH_TYPE_SXNI9260 1258 +#define MACH_TYPE_MXC27520EVB 1259 +#define MACH_TYPE_ARMADILLO5X0 1260 +#define MACH_TYPE_MB9260 1261 +#define MACH_TYPE_MB9263 1262 +#define MACH_TYPE_IPAC9302 1263 +#define MACH_TYPE_CC9P9360JS 1264 +#define MACH_TYPE_GALLIUM 1265 +#define MACH_TYPE_MSC2410 1266 +#define MACH_TYPE_GHI270 1267 +#define MACH_TYPE_DAVINCI_LEONARDO 1268 +#define MACH_TYPE_OIAB 1269 +#define MACH_TYPE_SMDK6400 1270 +#define MACH_TYPE_NOKIA_N800 1271 +#define MACH_TYPE_GREENPHONE 1272 +#define MACH_TYPE_COMPEXWP18 1273 +#define MACH_TYPE_XMATE 1274 +#define MACH_TYPE_ENERGIZER 1275 +#define MACH_TYPE_IME1 1276 +#define MACH_TYPE_SWEDATMS 1277 +#define MACH_TYPE_NTNP435C 1278 +#define MACH_TYPE_SPECTRO2 1279 +#define MACH_TYPE_H6039 1280 +#define MACH_TYPE_EP80219 1281 +#define MACH_TYPE_SAMOA_II 1282 +#define MACH_TYPE_CWMXL 1283 +#define MACH_TYPE_AS9200 1284 +#define MACH_TYPE_SFX1149 1285 +#define MACH_TYPE_NAVI010 1286 +#define MACH_TYPE_MULTMDP 1287 +#define MACH_TYPE_SCB9520 1288 +#define MACH_TYPE_HTCATHENA 1289 +#define MACH_TYPE_XP179 1290 +#define MACH_TYPE_H4300 1291 +#define MACH_TYPE_GORAMO_MLR 1292 +#define MACH_TYPE_MXC30020EVB 1293 +#define MACH_TYPE_ADSBITSYG5 1294 +#define MACH_TYPE_ADSPORTALPLUS 1295 +#define MACH_TYPE_MMSP2PLUS 1296 +#define MACH_TYPE_EM_X270 1297 +#define MACH_TYPE_TPP302 1298 +#define MACH_TYPE_TPM104 1299 +#define MACH_TYPE_TPM102 1300 +#define MACH_TYPE_TPM109 1301 +#define MACH_TYPE_FBXO1 1302 +#define MACH_TYPE_HXD8 1303 +#define MACH_TYPE_NEO1973_GTA02 1304 +#define MACH_TYPE_EMTEST 1305 +#define MACH_TYPE_AD6900 1306 +#define MACH_TYPE_EUROPA 1307 +#define MACH_TYPE_METROCONNECT 1308 +#define MACH_TYPE_EZ_S2410 1309 +#define MACH_TYPE_EZ_S2440 1310 +#define MACH_TYPE_EZ_EP9312 1311 +#define MACH_TYPE_EZ_EP9315 1312 +#define MACH_TYPE_EZ_X7 1313 +#define MACH_TYPE_GODOTDB 1314 +#define MACH_TYPE_MISTRAL 1315 +#define MACH_TYPE_MSM 1316 +#define MACH_TYPE_CT5910 1317 +#define MACH_TYPE_CT5912 1318 +#define MACH_TYPE_HYNET_INE 1319 +#define MACH_TYPE_HYNET_APP 1320 +#define MACH_TYPE_MSM7200 1321 +#define MACH_TYPE_MSM7600 1322 +#define MACH_TYPE_CEB255 1323 +#define MACH_TYPE_CIEL 1324 +#define MACH_TYPE_SLM5650 1325 +#define MACH_TYPE_AT91SAM9RLEK 1326 +#define MACH_TYPE_COMTECH_ROUTER 1327 +#define MACH_TYPE_SBC2410X 1328 +#define MACH_TYPE_AT4X0BD 1329 +#define MACH_TYPE_CBIFR 1330 +#define MACH_TYPE_ARCOM_QUANTUM 1331 +#define MACH_TYPE_MATRIX520 1332 +#define MACH_TYPE_MATRIX510 1333 +#define MACH_TYPE_MATRIX500 1334 +#define MACH_TYPE_M501 1335 +#define MACH_TYPE_AAEON1270 1336 +#define MACH_TYPE_MATRIX500EV 1337 +#define MACH_TYPE_PAC500 1338 +#define MACH_TYPE_PNX8181 1339 +#define MACH_TYPE_COLIBRI320 1340 +#define MACH_TYPE_AZTOOLBB 1341 +#define MACH_TYPE_AZTOOLG2 1342 +#define MACH_TYPE_DVLHOST 1343 +#define MACH_TYPE_ZIR9200 1344 +#define MACH_TYPE_ZIR9260 1345 +#define MACH_TYPE_COCOPAH 1346 +#define MACH_TYPE_NDS 1347 +#define MACH_TYPE_ROSENCRANTZ 1348 +#define MACH_TYPE_FTTX_ODSC 1349 +#define MACH_TYPE_CLASSE_R6904 1350 +#define MACH_TYPE_CAM60 1351 +#define MACH_TYPE_MXC30031ADS 1352 +#define MACH_TYPE_DATACALL 1353 +#define MACH_TYPE_AT91EB01 1354 +#define MACH_TYPE_RTY 1355 +#define MACH_TYPE_DWL2100 1356 +#define MACH_TYPE_VINSI 1357 +#define MACH_TYPE_DB88F5281 1358 +#define MACH_TYPE_CSB726 1359 +#define MACH_TYPE_TIK27 1360 +#define MACH_TYPE_MX_UC7420 1361 +#define MACH_TYPE_RIRM3 1362 +#define MACH_TYPE_PELCO_ODYSSEY 1363 +#define MACH_TYPE_ADX_ABOX 1365 +#define MACH_TYPE_ADX_TPID 1366 +#define MACH_TYPE_MINICHECK 1367 +#define MACH_TYPE_IDAM 1368 +#define MACH_TYPE_MARIO_MX 1369 +#define MACH_TYPE_VI1888 1370 +#define MACH_TYPE_ZR4230 1371 +#define MACH_TYPE_T1_IX_BLUE 1372 +#define MACH_TYPE_SYHQ2 1373 +#define MACH_TYPE_COMPUTIME_R3 1374 +#define MACH_TYPE_ORATIS 1375 +#define MACH_TYPE_MIKKO 1376 +#define MACH_TYPE_HOLON 1377 +#define MACH_TYPE_OLIP8 1378 +#define MACH_TYPE_GHI270HG 1379 +#define MACH_TYPE_DAVINCI_DM6467_EVM 1380 +#define MACH_TYPE_DAVINCI_DM355_EVM 1381 +#define MACH_TYPE_BLACKRIVER 1383 +#define MACH_TYPE_SANDGATEWP 1384 +#define MACH_TYPE_CDOTBWSG 1385 +#define MACH_TYPE_QUARK963 1386 +#define MACH_TYPE_CSB735 1387 +#define MACH_TYPE_LITTLETON 1388 +#define MACH_TYPE_MIO_P550 1389 +#define MACH_TYPE_MOTION2440 1390 +#define MACH_TYPE_IMM500 1391 +#define MACH_TYPE_HOMEMATIC 1392 +#define MACH_TYPE_ERMINE 1393 +#define MACH_TYPE_KB9202B 1394 +#define MACH_TYPE_HS1XX 1395 +#define MACH_TYPE_STUDENTMATE2440 1396 +#define MACH_TYPE_ARVOO_L1_Z1 1397 +#define MACH_TYPE_DEP2410K 1398 +#define MACH_TYPE_XXSVIDEO 1399 +#define MACH_TYPE_IM4004 1400 +#define MACH_TYPE_OCHAYA1050 1401 +#define MACH_TYPE_LEP9261 1402 +#define MACH_TYPE_SVENMEB 1403 +#define MACH_TYPE_FORTUNET2NE 1404 +#define MACH_TYPE_NXHX 1406 +#define MACH_TYPE_REALVIEW_PB11MP 1407 +#define MACH_TYPE_IDS500 1408 +#define MACH_TYPE_ORS_N725 1409 +#define MACH_TYPE_HSDARM 1410 +#define MACH_TYPE_SHA_PON003 1411 +#define MACH_TYPE_SHA_PON004 1412 +#define MACH_TYPE_SHA_PON007 1413 +#define MACH_TYPE_SHA_PON011 1414 +#define MACH_TYPE_H6042 1415 +#define MACH_TYPE_H6043 1416 +#define MACH_TYPE_LOOXC550 1417 +#define MACH_TYPE_CNTY_TITAN 1418 +#define MACH_TYPE_APP3XX 1419 +#define MACH_TYPE_SIDEOATSGRAMA 1420 +#define MACH_TYPE_TREO700P 1421 +#define MACH_TYPE_TREO700W 1422 +#define MACH_TYPE_TREO750 1423 +#define MACH_TYPE_TREO755P 1424 +#define MACH_TYPE_EZREGANUT9200 1425 +#define MACH_TYPE_SARGE 1426 +#define MACH_TYPE_A696 1427 +#define MACH_TYPE_TURTLE 1428 +#define MACH_TYPE_MX27_3DS 1430 +#define MACH_TYPE_BISHOP 1431 +#define MACH_TYPE_PXX 1432 +#define MACH_TYPE_REDWOOD 1433 +#define MACH_TYPE_OMAP_2430DLP 1436 +#define MACH_TYPE_OMAP_2430OSK 1437 +#define MACH_TYPE_SARDINE 1438 +#define MACH_TYPE_HALIBUT 1439 +#define MACH_TYPE_TROUT 1440 +#define MACH_TYPE_GOLDFISH 1441 +#define MACH_TYPE_GESBC2440 1442 +#define MACH_TYPE_NOMAD 1443 +#define MACH_TYPE_ROSALIND 1444 +#define MACH_TYPE_CC9P9215 1445 +#define MACH_TYPE_CC9P9210 1446 +#define MACH_TYPE_CC9P9215JS 1447 +#define MACH_TYPE_CC9P9210JS 1448 +#define MACH_TYPE_NASFFE 1449 +#define MACH_TYPE_TN2X0BD 1450 +#define MACH_TYPE_GWMPXA 1451 +#define MACH_TYPE_EXYPLUS 1452 +#define MACH_TYPE_JADOO21 1453 +#define MACH_TYPE_LOOXN560 1454 +#define MACH_TYPE_BONSAI 1455 +#define MACH_TYPE_ADSMILGATO 1456 +#define MACH_TYPE_GBA 1457 +#define MACH_TYPE_H6044 1458 +#define MACH_TYPE_APP 1459 +#define MACH_TYPE_TCT_HAMMER 1460 +#define MACH_TYPE_HERALD 1461 +#define MACH_TYPE_ARTEMIS 1462 +#define MACH_TYPE_HTCTITAN 1463 +#define MACH_TYPE_QRANIUM 1464 +#define MACH_TYPE_ADX_WSC2 1465 +#define MACH_TYPE_ADX_MEDCOM 1466 +#define MACH_TYPE_BBOARD 1467 +#define MACH_TYPE_CAMBRIA 1468 +#define MACH_TYPE_MT7XXX 1469 +#define MACH_TYPE_MATRIX512 1470 +#define MACH_TYPE_MATRIX522 1471 +#define MACH_TYPE_IPAC5010 1472 +#define MACH_TYPE_SAKURA 1473 +#define MACH_TYPE_GROCX 1474 +#define MACH_TYPE_PM9263 1475 +#define MACH_TYPE_SIM_ONE 1476 +#define MACH_TYPE_ACQ132 1477 +#define MACH_TYPE_DATR 1478 +#define MACH_TYPE_ACTUX1 1479 +#define MACH_TYPE_ACTUX2 1480 +#define MACH_TYPE_ACTUX3 1481 +#define MACH_TYPE_FLEXIT 1482 +#define MACH_TYPE_BH2X0BD 1483 +#define MACH_TYPE_ATB2002 1484 +#define MACH_TYPE_XENON 1485 +#define MACH_TYPE_FM607 1486 +#define MACH_TYPE_MATRIX514 1487 +#define MACH_TYPE_MATRIX524 1488 +#define MACH_TYPE_INPOD 1489 +#define MACH_TYPE_JIVE 1490 +#define MACH_TYPE_TLL_MX21 1491 +#define MACH_TYPE_SBC2800 1492 +#define MACH_TYPE_CC7UCAMRY 1493 +#define MACH_TYPE_UBISYS_P9_SC15 1494 +#define MACH_TYPE_UBISYS_P9_SSC2D10 1495 +#define MACH_TYPE_UBISYS_P9_RCU3 1496 +#define MACH_TYPE_AML_M8000 1497 +#define MACH_TYPE_SNAPPER_270 1498 +#define MACH_TYPE_OMAP_BBX 1499 +#define MACH_TYPE_UCN2410 1500 +#define MACH_TYPE_SAM9_L9260 1501 +#define MACH_TYPE_ETI_C2 1502 +#define MACH_TYPE_AVALANCHE 1503 +#define MACH_TYPE_REALVIEW_PB1176 1504 +#define MACH_TYPE_DP1500 1505 +#define MACH_TYPE_APPLE_IPHONE 1506 +#define MACH_TYPE_YL9200 1507 +#define MACH_TYPE_RD88F5182 1508 +#define MACH_TYPE_KUROBOX_PRO 1509 +#define MACH_TYPE_SE_POET 1510 +#define MACH_TYPE_MX31_3DS 1511 +#define MACH_TYPE_R270 1512 +#define MACH_TYPE_ARMOUR21 1513 +#define MACH_TYPE_DT2 1514 +#define MACH_TYPE_VT4 1515 +#define MACH_TYPE_TYCO320 1516 +#define MACH_TYPE_ADMA 1517 +#define MACH_TYPE_WP188 1518 +#define MACH_TYPE_CORSICA 1519 +#define MACH_TYPE_BIGEYE 1520 +#define MACH_TYPE_TLL5000 1522 +#define MACH_TYPE_BEBOT 1523 +#define MACH_TYPE_QONG 1524 +#define MACH_TYPE_TCOMPACT 1525 +#define MACH_TYPE_PUMA5 1526 +#define MACH_TYPE_ELARA 1527 +#define MACH_TYPE_ELLINGTON 1528 +#define MACH_TYPE_XDA_ATOM 1529 +#define MACH_TYPE_ENERGIZER2 1530 +#define MACH_TYPE_ODIN 1531 +#define MACH_TYPE_ACTUX4 1532 +#define MACH_TYPE_ESL_OMAP 1533 +#define MACH_TYPE_OMAP2EVM 1534 +#define MACH_TYPE_OMAP3EVM 1535 +#define MACH_TYPE_ADX_PCU57 1536 +#define MACH_TYPE_MONACO 1537 +#define MACH_TYPE_LEVANTE 1538 +#define MACH_TYPE_TMXIPX425 1539 +#define MACH_TYPE_LEEP 1540 +#define MACH_TYPE_RAAD 1541 +#define MACH_TYPE_DNS323 1542 +#define MACH_TYPE_AP1000 1543 +#define MACH_TYPE_A9SAM6432 1544 +#define MACH_TYPE_SHINY 1545 +#define MACH_TYPE_OMAP3_BEAGLE 1546 +#define MACH_TYPE_CSR_BDB2 1547 +#define MACH_TYPE_NOKIA_N810 1548 +#define MACH_TYPE_C270 1549 +#define MACH_TYPE_SENTRY 1550 +#define MACH_TYPE_PCM038 1551 +#define MACH_TYPE_ANC300 1552 +#define MACH_TYPE_HTCKAISER 1553 +#define MACH_TYPE_SBAT100 1554 +#define MACH_TYPE_MODUNORM 1555 +#define MACH_TYPE_PELOS_TWARM 1556 +#define MACH_TYPE_FLANK 1557 +#define MACH_TYPE_SIRLOIN 1558 +#define MACH_TYPE_BRISKET 1559 +#define MACH_TYPE_CHUCK 1560 +#define MACH_TYPE_OTTER 1561 +#define MACH_TYPE_DAVINCI_LDK 1562 +#define MACH_TYPE_PHREEDOM 1563 +#define MACH_TYPE_SG310 1564 +#define MACH_TYPE_TS209 1565 +#define MACH_TYPE_AT91CAP9ADK 1566 +#define MACH_TYPE_TION9315 1567 +#define MACH_TYPE_MAST 1568 +#define MACH_TYPE_PFW 1569 +#define MACH_TYPE_YL_P2440 1570 +#define MACH_TYPE_ZSBC32 1571 +#define MACH_TYPE_OMAP_PACE2 1572 +#define MACH_TYPE_IMX_PACE2 1573 +#define MACH_TYPE_MX31MOBOARD 1574 +#define MACH_TYPE_MX37_3DS 1575 +#define MACH_TYPE_RCC 1576 +#define MACH_TYPE_ARM9 1577 +#define MACH_TYPE_VISION_EP9307 1578 +#define MACH_TYPE_SCLY1000 1579 +#define MACH_TYPE_FONTEL_EP 1580 +#define MACH_TYPE_VOICEBLUE3G 1581 +#define MACH_TYPE_TT9200 1582 +#define MACH_TYPE_DIGI2410 1583 +#define MACH_TYPE_TERASTATION_PRO2 1584 +#define MACH_TYPE_LINKSTATION_PRO 1585 +#define MACH_TYPE_MOTOROLA_A780 1587 +#define MACH_TYPE_MOTOROLA_E6 1588 +#define MACH_TYPE_MOTOROLA_E2 1589 +#define MACH_TYPE_MOTOROLA_E680 1590 +#define MACH_TYPE_UR2410 1591 +#define MACH_TYPE_TAS9261 1592 +#define MACH_TYPE_HERMES_HD 1593 +#define MACH_TYPE_PERSEO_HD 1594 +#define MACH_TYPE_STARGAZER2 1595 +#define MACH_TYPE_E350 1596 +#define MACH_TYPE_WPCM450 1597 +#define MACH_TYPE_CARTESIO 1598 +#define MACH_TYPE_TOYBOX 1599 +#define MACH_TYPE_TX27 1600 +#define MACH_TYPE_TS409 1601 +#define MACH_TYPE_P300 1602 +#define MACH_TYPE_XDACOMET 1603 +#define MACH_TYPE_DEXFLEX2 1604 +#define MACH_TYPE_OW 1605 +#define MACH_TYPE_ARMEBS3 1606 +#define MACH_TYPE_U3 1607 +#define MACH_TYPE_SMDK2450 1608 +#define MACH_TYPE_RSI_EWS 1609 +#define MACH_TYPE_TNB 1610 +#define MACH_TYPE_TOEPATH 1611 +#define MACH_TYPE_KB9263 1612 +#define MACH_TYPE_MT7108 1613 +#define MACH_TYPE_SMTR2440 1614 +#define MACH_TYPE_MANAO 1615 +#define MACH_TYPE_CM_X300 1616 +#define MACH_TYPE_GULFSTREAM_KP 1617 +#define MACH_TYPE_LANREADYFN522 1618 +#define MACH_TYPE_ARMA37 1619 +#define MACH_TYPE_MENDEL 1620 +#define MACH_TYPE_PELCO_ILIAD 1621 +#define MACH_TYPE_UNIT2P 1622 +#define MACH_TYPE_INC20OTTER 1623 +#define MACH_TYPE_AT91SAM9G20EK 1624 +#define MACH_TYPE_STORCENTER 1625 +#define MACH_TYPE_SMDK6410 1626 +#define MACH_TYPE_U300 1627 +#define MACH_TYPE_U500 1628 +#define MACH_TYPE_DS9260 1629 +#define MACH_TYPE_RIVERROCK 1630 +#define MACH_TYPE_SCIBATH 1631 +#define MACH_TYPE_AT91SAM7SE512EK 1632 +#define MACH_TYPE_WRT350N_V2 1633 +#define MACH_TYPE_MULTIMEDIA 1634 +#define MACH_TYPE_MARVIN 1635 +#define MACH_TYPE_X500 1636 +#define MACH_TYPE_AWLUG4LCU 1637 +#define MACH_TYPE_PALERMOC 1638 +#define MACH_TYPE_OMAP_LDP 1639 +#define MACH_TYPE_IP500 1640 +#define MACH_TYPE_ASE2 1642 +#define MACH_TYPE_MX35EVB 1643 +#define MACH_TYPE_AML_M8050 1644 +#define MACH_TYPE_MX35_3DS 1645 +#define MACH_TYPE_MARS 1646 +#define MACH_TYPE_NEUROS_OSD2 1647 +#define MACH_TYPE_BADGER 1648 +#define MACH_TYPE_TRIZEPS4WL 1649 +#define MACH_TYPE_TRIZEPS5 1650 +#define MACH_TYPE_MARLIN 1651 +#define MACH_TYPE_TS78XX 1652 +#define MACH_TYPE_HPIPAQ214 1653 +#define MACH_TYPE_AT572D940DCM 1654 +#define MACH_TYPE_NE1BOARD 1655 +#define MACH_TYPE_ZANTE 1656 +#define MACH_TYPE_SFFSDR 1657 +#define MACH_TYPE_TW2662 1658 +#define MACH_TYPE_VF10XX 1659 +#define MACH_TYPE_ZORAN43XX 1660 +#define MACH_TYPE_SONIX926 1661 +#define MACH_TYPE_CELESTIALSEMI 1662 +#define MACH_TYPE_CC9M2443JS 1663 +#define MACH_TYPE_TW5334 1664 +#define MACH_TYPE_HTCARTEMIS 1665 +#define MACH_TYPE_NAL_HLITE 1666 +#define MACH_TYPE_HTCVOGUE 1667 +#define MACH_TYPE_SMARTWEB 1668 +#define MACH_TYPE_MV86XX 1669 +#define MACH_TYPE_MV87XX 1670 +#define MACH_TYPE_SONGYOUNGHO 1671 +#define MACH_TYPE_YOUNGHOTEMA 1672 +#define MACH_TYPE_PCM037 1673 +#define MACH_TYPE_MMVP 1674 +#define MACH_TYPE_MMAP 1675 +#define MACH_TYPE_PTID2410 1676 +#define MACH_TYPE_JAMES_926 1677 +#define MACH_TYPE_FM6000 1678 +#define MACH_TYPE_DB88F6281_BP 1680 +#define MACH_TYPE_RD88F6192_NAS 1681 +#define MACH_TYPE_RD88F6281 1682 +#define MACH_TYPE_DB78X00_BP 1683 +#define MACH_TYPE_SMDK2416 1685 +#define MACH_TYPE_OCE_SPIDER_SI 1686 +#define MACH_TYPE_OCE_SPIDER_SK 1687 +#define MACH_TYPE_ROVERN6 1688 +#define MACH_TYPE_PELCO_EVOLUTION 1689 +#define MACH_TYPE_WBD111 1690 +#define MACH_TYPE_ELARACPE 1691 +#define MACH_TYPE_MABV3 1692 +#define MACH_TYPE_MV2120 1693 +#define MACH_TYPE_CSB737 1695 +#define MACH_TYPE_MX51_3DS 1696 +#define MACH_TYPE_G900 1697 +#define MACH_TYPE_APF27 1698 +#define MACH_TYPE_GGUS2000 1699 +#define MACH_TYPE_OMAP_2430_MIMIC 1700 +#define MACH_TYPE_IMX27LITE 1701 +#define MACH_TYPE_ALMEX 1702 +#define MACH_TYPE_CONTROL 1703 +#define MACH_TYPE_MBA2410 1704 +#define MACH_TYPE_VOLCANO 1705 +#define MACH_TYPE_ZENITH 1706 +#define MACH_TYPE_MUCHIP 1707 +#define MACH_TYPE_MAGELLAN 1708 +#define MACH_TYPE_USB_A9260 1709 +#define MACH_TYPE_USB_A9263 1710 +#define MACH_TYPE_QIL_A9260 1711 +#define MACH_TYPE_CME9210 1712 +#define MACH_TYPE_HCZH4 1713 +#define MACH_TYPE_SPEARBASIC 1714 +#define MACH_TYPE_DEP2440 1715 +#define MACH_TYPE_HDL_GXR 1716 +#define MACH_TYPE_HDL_GT 1717 +#define MACH_TYPE_HDL_4G 1718 +#define MACH_TYPE_S3C6000 1719 +#define MACH_TYPE_MMSP2_MDK 1720 +#define MACH_TYPE_MPX220 1721 +#define MACH_TYPE_KZM_ARM11_01 1722 +#define MACH_TYPE_HTC_POLARIS 1723 +#define MACH_TYPE_HTC_KAISER 1724 +#define MACH_TYPE_LG_KS20 1725 +#define MACH_TYPE_HHGPS 1726 +#define MACH_TYPE_NOKIA_N810_WIMAX 1727 +#define MACH_TYPE_INSIGHT 1728 +#define MACH_TYPE_SAPPHIRE 1729 +#define MACH_TYPE_CSB637XO 1730 +#define MACH_TYPE_EVISIONG 1731 +#define MACH_TYPE_STMP37XX 1732 +#define MACH_TYPE_STMP378X 1733 +#define MACH_TYPE_TNT 1734 +#define MACH_TYPE_TBXT 1735 +#define MACH_TYPE_PLAYMATE 1736 +#define MACH_TYPE_PNS10 1737 +#define MACH_TYPE_EZNAVI 1738 +#define MACH_TYPE_PS4000 1739 +#define MACH_TYPE_EZX_A780 1740 +#define MACH_TYPE_EZX_E680 1741 +#define MACH_TYPE_EZX_A1200 1742 +#define MACH_TYPE_EZX_E6 1743 +#define MACH_TYPE_EZX_E2 1744 +#define MACH_TYPE_EZX_A910 1745 +#define MACH_TYPE_CWMX31 1746 +#define MACH_TYPE_SL2312 1747 +#define MACH_TYPE_BLENNY 1748 +#define MACH_TYPE_DS107 1749 +#define MACH_TYPE_DSX07 1750 +#define MACH_TYPE_PICOCOM1 1751 +#define MACH_TYPE_LYNX_WOLVERINE 1752 +#define MACH_TYPE_UBISYS_P9_SC19 1753 +#define MACH_TYPE_KRATOS_LOW 1754 +#define MACH_TYPE_M700 1755 +#define MACH_TYPE_EDMINI_V2 1756 +#define MACH_TYPE_ZIPIT2 1757 +#define MACH_TYPE_HSLFEMTOCELL 1758 +#define MACH_TYPE_DAINTREE_AT91 1759 +#define MACH_TYPE_SG560USB 1760 +#define MACH_TYPE_OMAP3_PANDORA 1761 +#define MACH_TYPE_USR8200 1762 +#define MACH_TYPE_S1S65K 1763 +#define MACH_TYPE_S2S65A 1764 +#define MACH_TYPE_ICORE 1765 +#define MACH_TYPE_MSS2 1766 +#define MACH_TYPE_BELMONT 1767 +#define MACH_TYPE_ASUSP525 1768 +#define MACH_TYPE_LB88RC8480 1769 +#define MACH_TYPE_HIPXA 1770 +#define MACH_TYPE_MX25_3DS 1771 +#define MACH_TYPE_M800 1772 +#define MACH_TYPE_OMAP3530_LV_SOM 1773 +#define MACH_TYPE_PRIMA_EVB 1774 +#define MACH_TYPE_MX31BT1 1775 +#define MACH_TYPE_ATLAS4_EVB 1776 +#define MACH_TYPE_MX31CICADA 1777 +#define MACH_TYPE_MI424WR 1778 +#define MACH_TYPE_AXS_ULTRAX 1779 +#define MACH_TYPE_AT572D940DEB 1780 +#define MACH_TYPE_DAVINCI_DA830_EVM 1781 +#define MACH_TYPE_EP9302 1782 +#define MACH_TYPE_AT572D940HFEB 1783 +#define MACH_TYPE_CYBOOK3 1784 +#define MACH_TYPE_WDG002 1785 +#define MACH_TYPE_SG560ADSL 1786 +#define MACH_TYPE_NEXTIO_N2800_ICA 1787 +#define MACH_TYPE_DOVE_DB 1788 +#define MACH_TYPE_VANDIHUD 1790 +#define MACH_TYPE_MAGX_E8 1791 +#define MACH_TYPE_MAGX_Z6 1792 +#define MACH_TYPE_MAGX_V8 1793 +#define MACH_TYPE_MAGX_U9 1794 +#define MACH_TYPE_TOUGHCF08 1795 +#define MACH_TYPE_ZW4400 1796 +#define MACH_TYPE_MARAT91 1797 +#define MACH_TYPE_OVERO 1798 +#define MACH_TYPE_AT2440EVB 1799 +#define MACH_TYPE_NEOCORE926 1800 +#define MACH_TYPE_WNR854T 1801 +#define MACH_TYPE_IMX27 1802 +#define MACH_TYPE_MOOSE_DB 1803 +#define MACH_TYPE_FAB4 1804 +#define MACH_TYPE_HTCDIAMOND 1805 +#define MACH_TYPE_FIONA 1806 +#define MACH_TYPE_MXC30030_X 1807 +#define MACH_TYPE_BMP1000 1808 +#define MACH_TYPE_LOGI9200 1809 +#define MACH_TYPE_TQMA31 1810 +#define MACH_TYPE_CCW9P9215JS 1811 +#define MACH_TYPE_RD88F5181L_GE 1812 +#define MACH_TYPE_SIFMAIN 1813 +#define MACH_TYPE_SAM9_L9261 1814 +#define MACH_TYPE_CC9M2443 1815 +#define MACH_TYPE_XARIA300 1816 +#define MACH_TYPE_IT9200 1817 +#define MACH_TYPE_RD88F5181L_FXO 1818 +#define MACH_TYPE_KRISS_SENSOR 1819 +#define MACH_TYPE_PILZ_PMI5 1820 +#define MACH_TYPE_JADE 1821 +#define MACH_TYPE_KS8695_SOFTPLC 1822 +#define MACH_TYPE_GPRISC3 1823 +#define MACH_TYPE_STAMP9G20 1824 +#define MACH_TYPE_SMDK6430 1825 +#define MACH_TYPE_SMDKC100 1826 +#define MACH_TYPE_TAVOREVB 1827 +#define MACH_TYPE_SAAR 1828 +#define MACH_TYPE_DEISTER_EYECAM 1829 +#define MACH_TYPE_AT91SAM9M10G45EK 1830 +#define MACH_TYPE_LINKSTATION_PRODUO 1831 +#define MACH_TYPE_HIT_B0 1832 +#define MACH_TYPE_ADX_RMU 1833 +#define MACH_TYPE_XG_CPE_MAIN 1834 +#define MACH_TYPE_EDB9407A 1835 +#define MACH_TYPE_DTB9608 1836 +#define MACH_TYPE_EM104V1 1837 +#define MACH_TYPE_DEMO 1838 +#define MACH_TYPE_LOGI9260 1839 +#define MACH_TYPE_MX31_EXM32 1840 +#define MACH_TYPE_USB_A9G20 1841 +#define MACH_TYPE_PICPROJE2008 1842 +#define MACH_TYPE_CS_E9315 1843 +#define MACH_TYPE_QIL_A9G20 1844 +#define MACH_TYPE_SHA_PON020 1845 +#define MACH_TYPE_NAD 1846 +#define MACH_TYPE_SBC35_A9260 1847 +#define MACH_TYPE_SBC35_A9G20 1848 +#define MACH_TYPE_DAVINCI_BEGINNING 1849 +#define MACH_TYPE_UWC 1850 +#define MACH_TYPE_MXLADS 1851 +#define MACH_TYPE_HTCNIKE 1852 +#define MACH_TYPE_DEISTER_PXA270 1853 +#define MACH_TYPE_CME9210JS 1854 +#define MACH_TYPE_CC9P9360 1855 +#define MACH_TYPE_MOCHA 1856 +#define MACH_TYPE_WAPD170AG 1857 +#define MACH_TYPE_LINKSTATION_MINI 1858 +#define MACH_TYPE_AFEB9260 1859 +#define MACH_TYPE_W90X900 1860 +#define MACH_TYPE_W90X700 1861 +#define MACH_TYPE_KT300IP 1862 +#define MACH_TYPE_KT300IP_G20 1863 +#define MACH_TYPE_SRCM 1864 +#define MACH_TYPE_WLNX_9260 1865 +#define MACH_TYPE_OPENMOKO_GTA03 1866 +#define MACH_TYPE_OSPREY2 1867 +#define MACH_TYPE_KBIO9260 1868 +#define MACH_TYPE_GINZA 1869 +#define MACH_TYPE_A636N 1870 +#define MACH_TYPE_IMX27IPCAM 1871 +#define MACH_TYPE_NEMOC 1872 +#define MACH_TYPE_GENEVA 1873 +#define MACH_TYPE_HTCPHAROS 1874 +#define MACH_TYPE_NEONC 1875 +#define MACH_TYPE_NAS7100 1876 +#define MACH_TYPE_TEUPHONE 1877 +#define MACH_TYPE_ANNAX_ETH2 1878 +#define MACH_TYPE_CSB733 1879 +#define MACH_TYPE_BK3 1880 +#define MACH_TYPE_OMAP_EM32 1881 +#define MACH_TYPE_ET9261CP 1882 +#define MACH_TYPE_JASPERC 1883 +#define MACH_TYPE_ISSI_ARM9 1884 +#define MACH_TYPE_UED 1885 +#define MACH_TYPE_ESIBLADE 1886 +#define MACH_TYPE_EYE02 1887 +#define MACH_TYPE_IMX27KBD 1888 +#define MACH_TYPE_KIXVP435 1890 +#define MACH_TYPE_KIXNP435 1891 +#define MACH_TYPE_AFRICA 1892 +#define MACH_TYPE_NH233 1893 +#define MACH_TYPE_RD88F6183AP_GE 1894 +#define MACH_TYPE_BCM4760 1895 +#define MACH_TYPE_EDDY_V2 1896 +#define MACH_TYPE_REALVIEW_PBA8 1897 +#define MACH_TYPE_HID_A7 1898 +#define MACH_TYPE_HERO 1899 +#define MACH_TYPE_OMAP_POSEIDON 1900 +#define MACH_TYPE_REALVIEW_PBX 1901 +#define MACH_TYPE_MICRO9S 1902 +#define MACH_TYPE_MAKO 1903 +#define MACH_TYPE_XDAFLAME 1904 +#define MACH_TYPE_PHIDGET_SBC2 1905 +#define MACH_TYPE_LIMESTONE 1906 +#define MACH_TYPE_IPROBE_C32 1907 +#define MACH_TYPE_RUT100 1908 +#define MACH_TYPE_ASUSP535 1909 +#define MACH_TYPE_HTCRAPHAEL 1910 +#define MACH_TYPE_SYGDG1 1911 +#define MACH_TYPE_SYGDG2 1912 +#define MACH_TYPE_SEOUL 1913 +#define MACH_TYPE_SALERNO 1914 +#define MACH_TYPE_UCN_S3C64XX 1915 +#define MACH_TYPE_MSM7201A 1916 +#define MACH_TYPE_LPR1 1917 +#define MACH_TYPE_ARMADILLO500FX 1918 +#define MACH_TYPE_G3EVM 1919 +#define MACH_TYPE_Z3_DM355 1920 +#define MACH_TYPE_W90P910EVB 1921 +#define MACH_TYPE_W90P920EVB 1922 +#define MACH_TYPE_W90P950EVB 1923 +#define MACH_TYPE_W90N960EVB 1924 +#define MACH_TYPE_CAMHD 1925 +#define MACH_TYPE_MVC100 1926 +#define MACH_TYPE_ELECTRUM_200 1927 +#define MACH_TYPE_HTCJADE 1928 +#define MACH_TYPE_MEMPHIS 1929 +#define MACH_TYPE_IMX27SBC 1930 +#define MACH_TYPE_LEXTAR 1931 +#define MACH_TYPE_MV88F6281GTW_GE 1932 +#define MACH_TYPE_NCP 1933 +#define MACH_TYPE_Z32AN 1934 +#define MACH_TYPE_TMQ_CAPD 1935 +#define MACH_TYPE_OMAP3_WL 1936 +#define MACH_TYPE_CHUMBY 1937 +#define MACH_TYPE_ATSARM9 1938 +#define MACH_TYPE_DAVINCI_DM365_EVM 1939 +#define MACH_TYPE_BAHAMAS 1940 +#define MACH_TYPE_DAS 1941 +#define MACH_TYPE_MINIDAS 1942 +#define MACH_TYPE_VK1000 1943 +#define MACH_TYPE_CENTRO 1944 +#define MACH_TYPE_CTERA_2BAY 1945 +#define MACH_TYPE_EDGECONNECT 1946 +#define MACH_TYPE_ND27000 1947 +#define MACH_TYPE_GEMALTO_COBRA 1948 +#define MACH_TYPE_INGELABS_COMET 1949 +#define MACH_TYPE_POLLUX_WIZ 1950 +#define MACH_TYPE_BLACKSTONE 1951 +#define MACH_TYPE_TOPAZ 1952 +#define MACH_TYPE_AIXLE 1953 +#define MACH_TYPE_MW998 1954 +#define MACH_TYPE_NOKIA_RX51 1955 +#define MACH_TYPE_VSC5605EV 1956 +#define MACH_TYPE_NT98700DK 1957 +#define MACH_TYPE_ICONTACT 1958 +#define MACH_TYPE_SWARCO_FRCPU 1959 +#define MACH_TYPE_SWARCO_SCPU 1960 +#define MACH_TYPE_BBOX_P16 1961 +#define MACH_TYPE_BSTD 1962 +#define MACH_TYPE_SBC2440II 1963 +#define MACH_TYPE_PCM034 1964 +#define MACH_TYPE_NESO 1965 +#define MACH_TYPE_WLNX_9G20 1966 +#define MACH_TYPE_OMAP_ZOOM2 1967 +#define MACH_TYPE_TOTEMNOVA 1968 +#define MACH_TYPE_C5000 1969 +#define MACH_TYPE_UNIPO_AT91SAM9263 1970 +#define MACH_TYPE_ETHERNUT5 1971 +#define MACH_TYPE_ARM11 1972 +#define MACH_TYPE_CPUAT9260 1973 +#define MACH_TYPE_CPUPXA255 1974 +#define MACH_TYPE_EUKREA_CPUIMX27 1975 +#define MACH_TYPE_CHEFLUX 1976 +#define MACH_TYPE_EB_CPUX9K2 1977 +#define MACH_TYPE_OPCOTEC 1978 +#define MACH_TYPE_YT 1979 +#define MACH_TYPE_MOTOQ 1980 +#define MACH_TYPE_BSB1 1981 +#define MACH_TYPE_ACS5K 1982 +#define MACH_TYPE_MILAN 1983 +#define MACH_TYPE_QUARTZV2 1984 +#define MACH_TYPE_RSVP 1985 +#define MACH_TYPE_RMP200 1986 +#define MACH_TYPE_SNAPPER_9260 1987 +#define MACH_TYPE_DSM320 1988 +#define MACH_TYPE_ADSGCM 1989 +#define MACH_TYPE_ASE2_400 1990 +#define MACH_TYPE_PIZZA 1991 +#define MACH_TYPE_SPOT_NGPL 1992 +#define MACH_TYPE_ARMATA 1993 +#define MACH_TYPE_EXEDA 1994 +#define MACH_TYPE_MX31SF005 1995 +#define MACH_TYPE_F5D8231_4_V2 1996 +#define MACH_TYPE_Q2440 1997 +#define MACH_TYPE_QQ2440 1998 +#define MACH_TYPE_MINI2440 1999 +#define MACH_TYPE_COLIBRI300 2000 +#define MACH_TYPE_JADES 2001 +#define MACH_TYPE_SPARK 2002 +#define MACH_TYPE_BENZINA 2003 +#define MACH_TYPE_BLAZE 2004 +#define MACH_TYPE_LINKSTATION_LS_HGL 2005 +#define MACH_TYPE_HTCKOVSKY 2006 +#define MACH_TYPE_SONY_PRS505 2007 +#define MACH_TYPE_HANLIN_V3 2008 +#define MACH_TYPE_SAPPHIRA 2009 +#define MACH_TYPE_DACK_SDA_01 2010 +#define MACH_TYPE_ARMBOX 2011 +#define MACH_TYPE_HARRIS_RVP 2012 +#define MACH_TYPE_RIBALDO 2013 +#define MACH_TYPE_AGORA 2014 +#define MACH_TYPE_OMAP3_MINI 2015 +#define MACH_TYPE_A9SAM6432_B 2016 +#define MACH_TYPE_USG2410 2017 +#define MACH_TYPE_PC72052_I10_REVB 2018 +#define MACH_TYPE_MX35_EXM32 2019 +#define MACH_TYPE_TOPAS910 2020 +#define MACH_TYPE_HYENA 2021 +#define MACH_TYPE_POSPAX 2022 +#define MACH_TYPE_HDL_GX 2023 +#define MACH_TYPE_CTERA_4BAY 2024 +#define MACH_TYPE_CTERA_PLUG_C 2025 +#define MACH_TYPE_CRWEA_PLUG_I 2026 +#define MACH_TYPE_EGAUGE2 2027 +#define MACH_TYPE_DIDJ 2028 +#define MACH_TYPE_MEISTER 2029 +#define MACH_TYPE_HTCBLACKSTONE 2030 +#define MACH_TYPE_CPUAT9G20 2031 +#define MACH_TYPE_SMDK6440 2032 +#define MACH_TYPE_OMAP_35XX_MVP 2033 +#define MACH_TYPE_CTERA_PLUG_I 2034 +#define MACH_TYPE_PVG610 2035 +#define MACH_TYPE_HPRW6815 2036 +#define MACH_TYPE_OMAP3_OSWALD 2037 +#define MACH_TYPE_NAS4220B 2038 +#define MACH_TYPE_HTCRAPHAEL_CDMA 2039 +#define MACH_TYPE_HTCDIAMOND_CDMA 2040 +#define MACH_TYPE_SCALER 2041 +#define MACH_TYPE_ZYLONITE2 2042 +#define MACH_TYPE_ASPENITE 2043 +#define MACH_TYPE_TETON 2044 +#define MACH_TYPE_TTC_DKB 2045 +#define MACH_TYPE_BISHOP2 2046 +#define MACH_TYPE_IPPV5 2047 +#define MACH_TYPE_FARM926 2048 +#define MACH_TYPE_MMCCPU 2049 +#define MACH_TYPE_SGMSFL 2050 +#define MACH_TYPE_TT8000 2051 +#define MACH_TYPE_ZRN4300LP 2052 +#define MACH_TYPE_MPTC 2053 +#define MACH_TYPE_H6051 2054 +#define MACH_TYPE_PVG610_101 2055 +#define MACH_TYPE_STAMP9261_PC_EVB 2056 +#define MACH_TYPE_PELCO_ODYSSEUS 2057 +#define MACH_TYPE_TNY_A9260 2058 +#define MACH_TYPE_TNY_A9G20 2059 +#define MACH_TYPE_AESOP_MP2530F 2060 +#define MACH_TYPE_DX900 2061 +#define MACH_TYPE_CPODC2 2062 +#define MACH_TYPE_TILT_8925 2063 +#define MACH_TYPE_DAVINCI_DM357_EVM 2064 +#define MACH_TYPE_SWORDFISH 2065 +#define MACH_TYPE_CORVUS 2066 +#define MACH_TYPE_TAURUS 2067 +#define MACH_TYPE_AXM 2068 +#define MACH_TYPE_AXC 2069 +#define MACH_TYPE_BABY 2070 +#define MACH_TYPE_MP200 2071 +#define MACH_TYPE_PCM043 2072 +#define MACH_TYPE_HANLIN_V3C 2073 +#define MACH_TYPE_KBK9G20 2074 +#define MACH_TYPE_ADSTURBOG5 2075 +#define MACH_TYPE_AVENGER_LITE1 2076 +#define MACH_TYPE_SUC 2077 +#define MACH_TYPE_AT91SAM7S256 2078 +#define MACH_TYPE_MENDOZA 2079 +#define MACH_TYPE_KIRA 2080 +#define MACH_TYPE_MX1HBM 2081 +#define MACH_TYPE_QUATRO43XX 2082 +#define MACH_TYPE_QUATRO4230 2083 +#define MACH_TYPE_NSB400 2084 +#define MACH_TYPE_DRP255 2085 +#define MACH_TYPE_THOTH 2086 +#define MACH_TYPE_FIRESTONE 2087 +#define MACH_TYPE_ASUSP750 2088 +#define MACH_TYPE_CTERA_DL 2089 +#define MACH_TYPE_SOCR 2090 +#define MACH_TYPE_HTCOXYGEN 2091 +#define MACH_TYPE_HEROC 2092 +#define MACH_TYPE_ZENO6800 2093 +#define MACH_TYPE_SC2MCS 2094 +#define MACH_TYPE_GENE100 2095 +#define MACH_TYPE_AS353X 2096 +#define MACH_TYPE_SHEEVAPLUG 2097 +#define MACH_TYPE_AT91SAM9G20 2098 +#define MACH_TYPE_MV88F6192GTW_FE 2099 +#define MACH_TYPE_CC9200 2100 +#define MACH_TYPE_SM9200 2101 +#define MACH_TYPE_TP9200 2102 +#define MACH_TYPE_SNAPPERDV 2103 +#define MACH_TYPE_AVENGERS_LITE 2104 +#define MACH_TYPE_AVENGERS_LITE1 2105 +#define MACH_TYPE_OMAP3AXON 2106 +#define MACH_TYPE_MA8XX 2107 +#define MACH_TYPE_MP201EK 2108 +#define MACH_TYPE_DAVINCI_TUX 2109 +#define MACH_TYPE_MPA1600 2110 +#define MACH_TYPE_PELCO_TROY 2111 +#define MACH_TYPE_NSB667 2112 +#define MACH_TYPE_ROVERS5_4MPIX 2113 +#define MACH_TYPE_TWOCOM 2114 +#define MACH_TYPE_UBISYS_P9_RCU3R2 2115 +#define MACH_TYPE_HERO_ESPRESSO 2116 +#define MACH_TYPE_AFEUSB 2117 +#define MACH_TYPE_T830 2118 +#define MACH_TYPE_SPD8020_CC 2119 +#define MACH_TYPE_OM_3D7K 2120 +#define MACH_TYPE_PICOCOM2 2121 +#define MACH_TYPE_UWG4MX27 2122 +#define MACH_TYPE_UWG4MX31 2123 +#define MACH_TYPE_CHERRY 2124 +#define MACH_TYPE_MX51_BABBAGE 2125 +#define MACH_TYPE_S3C2440TURKIYE 2126 +#define MACH_TYPE_TX37 2127 +#define MACH_TYPE_SBC2800_9G20 2128 +#define MACH_TYPE_BENZGLB 2129 +#define MACH_TYPE_BENZTD 2130 +#define MACH_TYPE_CARTESIO_PLUS 2131 +#define MACH_TYPE_SOLRAD_G20 2132 +#define MACH_TYPE_MX27WALLACE 2133 +#define MACH_TYPE_FMZWEBMODUL 2134 +#define MACH_TYPE_RD78X00_MASA 2135 +#define MACH_TYPE_SMALLOGGER 2136 +#define MACH_TYPE_CCW9P9215 2137 +#define MACH_TYPE_DM355_LEOPARD 2138 +#define MACH_TYPE_TS219 2139 +#define MACH_TYPE_TNY_A9263 2140 +#define MACH_TYPE_APOLLO 2141 +#define MACH_TYPE_AT91CAP9STK 2142 +#define MACH_TYPE_SPC300 2143 +#define MACH_TYPE_EKO 2144 +#define MACH_TYPE_CCW9M2443 2145 +#define MACH_TYPE_CCW9M2443JS 2146 +#define MACH_TYPE_M2M_ROUTER_DEVICE 2147 +#define MACH_TYPE_STAR9104NAS 2148 +#define MACH_TYPE_PCA100 2149 +#define MACH_TYPE_Z3_DM365_MOD_01 2150 +#define MACH_TYPE_HIPOX 2151 +#define MACH_TYPE_OMAP3_PITEDS 2152 +#define MACH_TYPE_BM150R 2153 +#define MACH_TYPE_TBONE 2154 +#define MACH_TYPE_MERLIN 2155 +#define MACH_TYPE_FALCON 2156 +#define MACH_TYPE_DAVINCI_DA850_EVM 2157 +#define MACH_TYPE_S5P6440 2158 +#define MACH_TYPE_AT91SAM9G10EK 2159 +#define MACH_TYPE_OMAP_4430SDP 2160 +#define MACH_TYPE_LPC313X 2161 +#define MACH_TYPE_MAGX_ZN5 2162 +#define MACH_TYPE_MAGX_EM30 2163 +#define MACH_TYPE_MAGX_VE66 2164 +#define MACH_TYPE_MEESC 2165 +#define MACH_TYPE_OTC570 2166 +#define MACH_TYPE_BCU2412 2167 +#define MACH_TYPE_BEACON 2168 +#define MACH_TYPE_ACTIA_TGW 2169 +#define MACH_TYPE_E4430 2170 +#define MACH_TYPE_QL300 2171 +#define MACH_TYPE_BTMAVB101 2172 +#define MACH_TYPE_BTMAWB101 2173 +#define MACH_TYPE_SQ201 2174 +#define MACH_TYPE_QUATRO45XX 2175 +#define MACH_TYPE_OPENPAD 2176 +#define MACH_TYPE_TX25 2177 +#define MACH_TYPE_OMAP3_TORPEDO 2178 +#define MACH_TYPE_HTCRAPHAEL_K 2179 +#define MACH_TYPE_LAL43 2181 +#define MACH_TYPE_HTCRAPHAEL_CDMA500 2182 +#define MACH_TYPE_ANW6410 2183 +#define MACH_TYPE_HTCPROPHET 2185 +#define MACH_TYPE_CFA_10022 2186 +#define MACH_TYPE_IMX27_VISSTRIM_M10 2187 +#define MACH_TYPE_PX2IMX27 2188 +#define MACH_TYPE_STM3210E_EVAL 2189 +#define MACH_TYPE_DVS10 2190 +#define MACH_TYPE_PORTUXG20 2191 +#define MACH_TYPE_ARM_SPV 2192 +#define MACH_TYPE_SMDKC110 2193 +#define MACH_TYPE_CABESPRESSO 2194 +#define MACH_TYPE_HMC800 2195 +#define MACH_TYPE_SHOLES 2196 +#define MACH_TYPE_BTMXC31 2197 +#define MACH_TYPE_DT501 2198 +#define MACH_TYPE_KTX 2199 +#define MACH_TYPE_OMAP3517EVM 2200 +#define MACH_TYPE_NETSPACE_V2 2201 +#define MACH_TYPE_NETSPACE_MAX_V2 2202 +#define MACH_TYPE_D2NET_V2 2203 +#define MACH_TYPE_NET2BIG_V2 2204 +#define MACH_TYPE_NET4BIG_V2 2205 +#define MACH_TYPE_NET5BIG_V2 2206 +#define MACH_TYPE_ENDB2443 2207 +#define MACH_TYPE_INETSPACE_V2 2208 +#define MACH_TYPE_TROS 2209 +#define MACH_TYPE_PELCO_HOMER 2210 +#define MACH_TYPE_OFSP8 2211 +#define MACH_TYPE_AT91SAM9G45EKES 2212 +#define MACH_TYPE_GUF_CUPID 2213 +#define MACH_TYPE_EAB1R 2214 +#define MACH_TYPE_DESIREC 2215 +#define MACH_TYPE_CORDOBA 2216 +#define MACH_TYPE_IRVINE 2217 +#define MACH_TYPE_SFF772 2218 +#define MACH_TYPE_PELCO_MILANO 2219 +#define MACH_TYPE_PC7302 2220 +#define MACH_TYPE_BIP6000 2221 +#define MACH_TYPE_SILVERMOON 2222 +#define MACH_TYPE_VC0830 2223 +#define MACH_TYPE_DT430 2224 +#define MACH_TYPE_JI42PF 2225 +#define MACH_TYPE_GNET_KSM 2226 +#define MACH_TYPE_GNET_SGM 2227 +#define MACH_TYPE_GNET_SGR 2228 +#define MACH_TYPE_OMAP3_ICETEKEVM 2229 +#define MACH_TYPE_PNP 2230 +#define MACH_TYPE_CTERA_2BAY_K 2231 +#define MACH_TYPE_CTERA_2BAY_U 2232 +#define MACH_TYPE_SAS_C 2233 +#define MACH_TYPE_VMA2315 2234 +#define MACH_TYPE_VCS 2235 +#define MACH_TYPE_SPEAR600 2236 +#define MACH_TYPE_SPEAR300 2237 +#define MACH_TYPE_SPEAR1300 2238 +#define MACH_TYPE_LILLY1131 2239 +#define MACH_TYPE_ARVOO_AX301 2240 +#define MACH_TYPE_MAPPHONE 2241 +#define MACH_TYPE_LEGEND 2242 +#define MACH_TYPE_SALSA 2243 +#define MACH_TYPE_LOUNGE 2244 +#define MACH_TYPE_VISION 2245 +#define MACH_TYPE_VMB20 2246 +#define MACH_TYPE_HY2410 2247 +#define MACH_TYPE_HY9315 2248 +#define MACH_TYPE_BULLWINKLE 2249 +#define MACH_TYPE_ARM_ULTIMATOR2 2250 +#define MACH_TYPE_VS_V210 2252 +#define MACH_TYPE_VS_V212 2253 +#define MACH_TYPE_HMT 2254 +#define MACH_TYPE_KM_KIRKWOOD 2255 +#define MACH_TYPE_VESPER 2256 +#define MACH_TYPE_STR9 2257 +#define MACH_TYPE_OMAP3_WL_FF 2258 +#define MACH_TYPE_SIMCOM 2259 +#define MACH_TYPE_MCWEBIO 2260 +#define MACH_TYPE_OMAP3_PHRAZER 2261 +#define MACH_TYPE_DARWIN 2262 +#define MACH_TYPE_ORATISCOMU 2263 +#define MACH_TYPE_RTSBC20 2264 +#define MACH_TYPE_I780 2265 +#define MACH_TYPE_GEMINI324 2266 +#define MACH_TYPE_ORATISLAN 2267 +#define MACH_TYPE_ORATISALOG 2268 +#define MACH_TYPE_ORATISMADI 2269 +#define MACH_TYPE_ORATISOT16 2270 +#define MACH_TYPE_ORATISDESK 2271 +#define MACH_TYPE_VEXPRESS 2272 +#define MACH_TYPE_SINTEXO 2273 +#define MACH_TYPE_CM3389 2274 +#define MACH_TYPE_OMAP3_CIO 2275 +#define MACH_TYPE_SGH_I900 2276 +#define MACH_TYPE_BST100 2277 +#define MACH_TYPE_PASSION 2278 +#define MACH_TYPE_INDESIGN_AT91SAM 2279 +#define MACH_TYPE_C4_BADGER 2280 +#define MACH_TYPE_C4_VIPER 2281 +#define MACH_TYPE_D2NET 2282 +#define MACH_TYPE_BIGDISK 2283 +#define MACH_TYPE_NOTALVISION 2284 +#define MACH_TYPE_OMAP3_KBOC 2285 +#define MACH_TYPE_CYCLONE 2286 +#define MACH_TYPE_NINJA 2287 +#define MACH_TYPE_AT91SAM9G20EK_2MMC 2288 +#define MACH_TYPE_BCMRING 2289 +#define MACH_TYPE_RESOL_DL2 2290 +#define MACH_TYPE_IFOSW 2291 +#define MACH_TYPE_HTCRHODIUM 2292 +#define MACH_TYPE_HTCTOPAZ 2293 +#define MACH_TYPE_MATRIX504 2294 +#define MACH_TYPE_MRFSA 2295 +#define MACH_TYPE_SC_P270 2296 +#define MACH_TYPE_ATLAS5_EVB 2297 +#define MACH_TYPE_PELCO_LOBOX 2298 +#define MACH_TYPE_DILAX_PCU200 2299 +#define MACH_TYPE_LEONARDO 2300 +#define MACH_TYPE_ZORAN_APPROACH7 2301 +#define MACH_TYPE_DP6XX 2302 +#define MACH_TYPE_BCM2153_VESPER 2303 +#define MACH_TYPE_MAHIMAHI 2304 +#define MACH_TYPE_CLICKC 2305 +#define MACH_TYPE_ZB_GATEWAY 2306 +#define MACH_TYPE_TAZCARD 2307 +#define MACH_TYPE_TAZDEV 2308 +#define MACH_TYPE_ANNAX_CB_ARM 2309 +#define MACH_TYPE_ANNAX_DM3 2310 +#define MACH_TYPE_CEREBRIC 2311 +#define MACH_TYPE_ORCA 2312 +#define MACH_TYPE_PC9260 2313 +#define MACH_TYPE_EMS285A 2314 +#define MACH_TYPE_GEC2410 2315 +#define MACH_TYPE_GEC2440 2316 +#define MACH_TYPE_ARCH_MW903 2317 +#define MACH_TYPE_MW2440 2318 +#define MACH_TYPE_ECAC2378 2319 +#define MACH_TYPE_TAZKIOSK 2320 +#define MACH_TYPE_WHITERABBIT_MCH 2321 +#define MACH_TYPE_SBOX9263 2322 +#define MACH_TYPE_SMDK6442 2324 +#define MACH_TYPE_OPENRD_BASE 2325 +#define MACH_TYPE_INCREDIBLE 2326 +#define MACH_TYPE_INCREDIBLEC 2327 +#define MACH_TYPE_HEROCT 2328 +#define MACH_TYPE_MMNET1000 2329 +#define MACH_TYPE_DEVKIT8000 2330 +#define MACH_TYPE_DEVKIT9000 2331 +#define MACH_TYPE_MX31TXTR 2332 +#define MACH_TYPE_U380 2333 +#define MACH_TYPE_HUALU_BOARD 2334 +#define MACH_TYPE_NPCMX50 2335 +#define MACH_TYPE_MX51_EFIKAMX 2336 +#define MACH_TYPE_MX51_LANGE52 2337 +#define MACH_TYPE_RIOM 2338 +#define MACH_TYPE_COMCAS 2339 +#define MACH_TYPE_WSI_MX27 2340 +#define MACH_TYPE_CM_T35 2341 +#define MACH_TYPE_NET2BIG 2342 +#define MACH_TYPE_MOTOROLA_A1600 2343 +#define MACH_TYPE_IGEP0020 2344 +#define MACH_TYPE_IGEP0010 2345 +#define MACH_TYPE_MV6281GTWGE2 2346 +#define MACH_TYPE_SCAT100 2347 +#define MACH_TYPE_SANMINA 2348 +#define MACH_TYPE_MOMENTO 2349 +#define MACH_TYPE_NUC9XX 2350 +#define MACH_TYPE_NUC910EVB 2351 +#define MACH_TYPE_NUC920EVB 2352 +#define MACH_TYPE_NUC950EVB 2353 +#define MACH_TYPE_NUC945EVB 2354 +#define MACH_TYPE_NUC960EVB 2355 +#define MACH_TYPE_NUC932EVB 2356 +#define MACH_TYPE_NUC900 2357 +#define MACH_TYPE_SD1SOC 2358 +#define MACH_TYPE_LN2440BC 2359 +#define MACH_TYPE_RSBC 2360 +#define MACH_TYPE_OPENRD_CLIENT 2361 +#define MACH_TYPE_HPIPAQ11X 2362 +#define MACH_TYPE_WAYLAND 2363 +#define MACH_TYPE_ACNBSX102 2364 +#define MACH_TYPE_HWAT91 2365 +#define MACH_TYPE_AT91SAM9263CS 2366 +#define MACH_TYPE_CSB732 2367 +#define MACH_TYPE_U8500 2368 +#define MACH_TYPE_HUQIU 2369 +#define MACH_TYPE_MX51_EFIKASB 2370 +#define MACH_TYPE_PMT1G 2371 +#define MACH_TYPE_HTCELF 2372 +#define MACH_TYPE_ARMADILLO420 2373 +#define MACH_TYPE_ARMADILLO440 2374 +#define MACH_TYPE_U_CHIP_DUAL_ARM 2375 +#define MACH_TYPE_CSR_BDB3 2376 +#define MACH_TYPE_DOLBY_CAT1018 2377 +#define MACH_TYPE_HY9307 2378 +#define MACH_TYPE_A_ES 2379 +#define MACH_TYPE_DAVINCI_IRIF 2380 +#define MACH_TYPE_AGAMA9263 2381 +#define MACH_TYPE_MARVELL_JASPER 2382 +#define MACH_TYPE_FLINT 2383 +#define MACH_TYPE_TAVOREVB3 2384 +#define MACH_TYPE_SCH_M490 2386 +#define MACH_TYPE_RBL01 2387 +#define MACH_TYPE_OMNIFI 2388 +#define MACH_TYPE_OTAVALO 2389 +#define MACH_TYPE_HTC_EXCALIBUR_S620 2391 +#define MACH_TYPE_HTC_OPAL 2392 +#define MACH_TYPE_TOUCHBOOK 2393 +#define MACH_TYPE_LATTE 2394 +#define MACH_TYPE_XA200 2395 +#define MACH_TYPE_NIMROD 2396 +#define MACH_TYPE_CC9P9215_3G 2397 +#define MACH_TYPE_CC9P9215_3GJS 2398 +#define MACH_TYPE_TK71 2399 +#define MACH_TYPE_COMHAM3525 2400 +#define MACH_TYPE_MX31EREBUS 2401 +#define MACH_TYPE_MCARDMX27 2402 +#define MACH_TYPE_PARADISE 2403 +#define MACH_TYPE_TIDE 2404 +#define MACH_TYPE_WZL2440 2405 +#define MACH_TYPE_SDRDEMO 2406 +#define MACH_TYPE_ETHERCAN2 2407 +#define MACH_TYPE_ECMIMG20 2408 +#define MACH_TYPE_OMAP_DRAGON 2409 +#define MACH_TYPE_HALO 2410 +#define MACH_TYPE_HUANGSHAN 2411 +#define MACH_TYPE_VL_MA2SC 2412 +#define MACH_TYPE_RAUMFELD_RC 2413 +#define MACH_TYPE_RAUMFELD_CONNECTOR 2414 +#define MACH_TYPE_RAUMFELD_SPEAKER 2415 +#define MACH_TYPE_MULTIBUS_MASTER 2416 +#define MACH_TYPE_MULTIBUS_PBK 2417 +#define MACH_TYPE_TNETV107X 2418 +#define MACH_TYPE_SNAKE 2419 +#define MACH_TYPE_CWMX27 2420 +#define MACH_TYPE_SCH_M480 2421 +#define MACH_TYPE_PLATYPUS 2422 +#define MACH_TYPE_PSS2 2423 +#define MACH_TYPE_DAVINCI_APM150 2424 +#define MACH_TYPE_STR9100 2425 +#define MACH_TYPE_NET5BIG 2426 +#define MACH_TYPE_SEABED9263 2427 +#define MACH_TYPE_MX51_M2ID 2428 +#define MACH_TYPE_OCTVOCPLUS_EB 2429 +#define MACH_TYPE_KLK_FIREFOX 2430 +#define MACH_TYPE_KLK_WIRMA_MODULE 2431 +#define MACH_TYPE_KLK_WIRMA_MMI 2432 +#define MACH_TYPE_SUPERSONIC 2433 +#define MACH_TYPE_LIBERTY 2434 +#define MACH_TYPE_MH355 2435 +#define MACH_TYPE_PC7802 2436 +#define MACH_TYPE_GNET_SGC 2437 +#define MACH_TYPE_EINSTEIN15 2438 +#define MACH_TYPE_CMPD 2439 +#define MACH_TYPE_DAVINCI_HASE1 2440 +#define MACH_TYPE_LGEINCITEPHONE 2441 +#define MACH_TYPE_EA313X 2442 +#define MACH_TYPE_FWBD_39064 2443 +#define MACH_TYPE_FWBD_390128 2444 +#define MACH_TYPE_PELCO_MOE 2445 +#define MACH_TYPE_MINIMIX27 2446 +#define MACH_TYPE_OMAP3_THUNDER 2447 +#define MACH_TYPE_PASSIONC 2448 +#define MACH_TYPE_MX27AMATA 2449 +#define MACH_TYPE_BGAT1 2450 +#define MACH_TYPE_BUZZ 2451 +#define MACH_TYPE_MB9G20 2452 +#define MACH_TYPE_YUSHAN 2453 +#define MACH_TYPE_LIZARD 2454 +#define MACH_TYPE_OMAP3POLYCOM 2455 +#define MACH_TYPE_SMDKV210 2456 +#define MACH_TYPE_BRAVO 2457 +#define MACH_TYPE_SIOGENTOO1 2458 +#define MACH_TYPE_SIOGENTOO2 2459 +#define MACH_TYPE_SM3K 2460 +#define MACH_TYPE_ACER_TEMPO_F900 2461 +#define MACH_TYPE_GLITTERTIND 2463 +#define MACH_TYPE_OMAP_ZOOM3 2464 +#define MACH_TYPE_OMAP_3630SDP 2465 +#define MACH_TYPE_CYBOOK2440 2466 +#define MACH_TYPE_TORINO_S 2467 +#define MACH_TYPE_HAVANA 2468 +#define MACH_TYPE_BEAUMONT_11 2469 +#define MACH_TYPE_VANGUARD 2470 +#define MACH_TYPE_S5PC110_DRACO 2471 +#define MACH_TYPE_CARTESIO_TWO 2472 +#define MACH_TYPE_ASTER 2473 +#define MACH_TYPE_VOGUESV210 2474 +#define MACH_TYPE_ACM500X 2475 +#define MACH_TYPE_KM9260 2476 +#define MACH_TYPE_NIDEFLEXG1 2477 +#define MACH_TYPE_CTERA_PLUG_IO 2478 +#define MACH_TYPE_SMARTQ7 2479 +#define MACH_TYPE_AT91SAM9G10EK2 2480 +#define MACH_TYPE_ASUSP527 2481 +#define MACH_TYPE_AT91SAM9G20MPM2 2482 +#define MACH_TYPE_TOPASA900 2483 +#define MACH_TYPE_ELECTRUM_100 2484 +#define MACH_TYPE_MX51GRB 2485 +#define MACH_TYPE_XEA300 2486 +#define MACH_TYPE_HTCSTARTREK 2487 +#define MACH_TYPE_LIMA 2488 +#define MACH_TYPE_CSB740 2489 +#define MACH_TYPE_USB_S8815 2490 +#define MACH_TYPE_WATSON_EFM_PLUGIN 2491 +#define MACH_TYPE_MILKYWAY 2492 +#define MACH_TYPE_G4EVM 2493 +#define MACH_TYPE_PICOMOD6 2494 +#define MACH_TYPE_OMAPL138_HAWKBOARD 2495 +#define MACH_TYPE_IP6000 2496 +#define MACH_TYPE_IP6010 2497 +#define MACH_TYPE_UTM400 2498 +#define MACH_TYPE_OMAP3_ZYBEX 2499 +#define MACH_TYPE_WIRELESS_SPACE 2500 +#define MACH_TYPE_SX560 2501 +#define MACH_TYPE_TS41X 2502 +#define MACH_TYPE_ELPHEL10373 2503 +#define MACH_TYPE_RHOBOT 2504 +#define MACH_TYPE_MX51_REFRESH 2505 +#define MACH_TYPE_LS9260 2506 +#define MACH_TYPE_SHANK 2507 +#define MACH_TYPE_QSD8X50_ST1 2508 +#define MACH_TYPE_AT91SAM9M10EKES 2509 +#define MACH_TYPE_HIRAM 2510 +#define MACH_TYPE_PHY3250 2511 +#define MACH_TYPE_EA3250 2512 +#define MACH_TYPE_FDI3250 2513 +#define MACH_TYPE_AT91SAM9263NIT 2515 +#define MACH_TYPE_CCMX51 2516 +#define MACH_TYPE_CCMX51JS 2517 +#define MACH_TYPE_CCWMX51 2518 +#define MACH_TYPE_CCWMX51JS 2519 +#define MACH_TYPE_MINI6410 2520 +#define MACH_TYPE_TINY6410 2521 +#define MACH_TYPE_NANO6410 2522 +#define MACH_TYPE_AT572D940HFNLDB 2523 +#define MACH_TYPE_HTCLEO 2524 +#define MACH_TYPE_AVP13 2525 +#define MACH_TYPE_XXSVIDEOD 2526 +#define MACH_TYPE_VPNEXT 2527 +#define MACH_TYPE_SWARCO_ITC3 2528 +#define MACH_TYPE_TX51 2529 +#define MACH_TYPE_DOLBY_CAT1021 2530 +#define MACH_TYPE_MX28EVK 2531 +#define MACH_TYPE_PHOENIX260 2532 +#define MACH_TYPE_UVACA_STORK 2533 +#define MACH_TYPE_SMARTQ5 2534 +#define MACH_TYPE_ALL3078 2535 +#define MACH_TYPE_CTERA_2BAY_DS 2536 +#define MACH_TYPE_SIOGENTOO3 2537 +#define MACH_TYPE_EPB5000 2538 +#define MACH_TYPE_HY9263 2539 +#define MACH_TYPE_ACER_TEMPO_M900 2540 +#define MACH_TYPE_ACER_TEMPO_DX900 2541 +#define MACH_TYPE_ACER_TEMPO_X960 2542 +#define MACH_TYPE_ACER_ETEN_V900 2543 +#define MACH_TYPE_ACER_ETEN_X900 2544 +#define MACH_TYPE_BONNELL 2545 +#define MACH_TYPE_OHT_MX27 2546 +#define MACH_TYPE_HTCQUARTZ 2547 +#define MACH_TYPE_DAVINCI_DM6467TEVM 2548 +#define MACH_TYPE_C3AX03 2549 +#define MACH_TYPE_MXT_TD60 2550 +#define MACH_TYPE_ESYX 2551 +#define MACH_TYPE_DOVE_DB2 2552 +#define MACH_TYPE_BULLDOG 2553 +#define MACH_TYPE_DERELL_ME2000 2554 +#define MACH_TYPE_BCMRING_BASE 2555 +#define MACH_TYPE_BCMRING_EVM 2556 +#define MACH_TYPE_BCMRING_EVM_JAZZ 2557 +#define MACH_TYPE_BCMRING_SP 2558 +#define MACH_TYPE_BCMRING_SV 2559 +#define MACH_TYPE_BCMRING_SV_JAZZ 2560 +#define MACH_TYPE_BCMRING_TABLET 2561 +#define MACH_TYPE_BCMRING_VP 2562 +#define MACH_TYPE_BCMRING_EVM_SEIKOR 2563 +#define MACH_TYPE_BCMRING_SP_WQVGA 2564 +#define MACH_TYPE_BCMRING_CUSTOM 2565 +#define MACH_TYPE_ACER_S200 2566 +#define MACH_TYPE_BT270 2567 +#define MACH_TYPE_ISEO 2568 +#define MACH_TYPE_CEZANNE 2569 +#define MACH_TYPE_LUCCA 2570 +#define MACH_TYPE_SUPERSMART 2571 +#define MACH_TYPE_CS_MISANO 2572 +#define MACH_TYPE_MAGNOLIA2 2573 +#define MACH_TYPE_EMXX 2574 +#define MACH_TYPE_OUTLAW 2575 +#define MACH_TYPE_RIOT_BEI2 2576 +#define MACH_TYPE_RIOT_VOX 2577 +#define MACH_TYPE_RIOT_X37 2578 +#define MACH_TYPE_MEGA25MX 2579 +#define MACH_TYPE_BENZINA2 2580 +#define MACH_TYPE_IGNITE 2581 +#define MACH_TYPE_FOGGIA 2582 +#define MACH_TYPE_AREZZO 2583 +#define MACH_TYPE_LEICA_SKYWALKER 2584 +#define MACH_TYPE_JACINTO2_JAMR 2585 +#define MACH_TYPE_GTS_NOVA 2586 +#define MACH_TYPE_P3600 2587 +#define MACH_TYPE_DLT2 2588 +#define MACH_TYPE_DF3120 2589 +#define MACH_TYPE_ECUCORE_9G20 2590 +#define MACH_TYPE_NAUTEL_LPC3240 2591 +#define MACH_TYPE_GLACIER 2592 +#define MACH_TYPE_PHRAZER_BULLDOG 2593 +#define MACH_TYPE_OMAP3_BULLDOG 2594 +#define MACH_TYPE_PCA101 2595 +#define MACH_TYPE_BUZZC 2596 +#define MACH_TYPE_SASIE2 2597 +#define MACH_TYPE_SMARTMETER_DL 2599 +#define MACH_TYPE_WZL6410 2600 +#define MACH_TYPE_WZL6410M 2601 +#define MACH_TYPE_WZL6410F 2602 +#define MACH_TYPE_WZL6410I 2603 +#define MACH_TYPE_SPACECOM1 2604 +#define MACH_TYPE_PINGU920 2605 +#define MACH_TYPE_BRAVOC 2606 +#define MACH_TYPE_VDSSW 2608 +#define MACH_TYPE_ROMULUS 2609 +#define MACH_TYPE_OMAP_MAGIC 2610 +#define MACH_TYPE_ELTD100 2611 +#define MACH_TYPE_CAPC7117 2612 +#define MACH_TYPE_SWAN 2613 +#define MACH_TYPE_VEU 2614 +#define MACH_TYPE_RM2 2615 +#define MACH_TYPE_TT2100 2616 +#define MACH_TYPE_VENICE 2617 +#define MACH_TYPE_PC7323 2618 +#define MACH_TYPE_MASP 2619 +#define MACH_TYPE_FUJITSU_TVSTBSOC 2620 +#define MACH_TYPE_FUJITSU_TVSTBSOC1 2621 +#define MACH_TYPE_LEXIKON 2622 +#define MACH_TYPE_MINI2440V2 2623 +#define MACH_TYPE_ICONTROL 2624 +#define MACH_TYPE_GPLUGD 2625 +#define MACH_TYPE_QSD8X50A_ST1_1 2626 +#define MACH_TYPE_QSD8X50A_ST1_5 2627 +#define MACH_TYPE_BEE 2628 +#define MACH_TYPE_MX23EVK 2629 +#define MACH_TYPE_AP4EVB 2630 +#define MACH_TYPE_STOCKHOLM 2631 +#define MACH_TYPE_LPC_H3131 2632 +#define MACH_TYPE_STINGRAY 2633 +#define MACH_TYPE_KRAKEN 2634 +#define MACH_TYPE_GW2388 2635 +#define MACH_TYPE_JADECPU 2636 +#define MACH_TYPE_CARLISLE 2637 +#define MACH_TYPE_LUX_SF9 2638 +#define MACH_TYPE_NEMID_TB 2639 +#define MACH_TYPE_TERRIER 2640 +#define MACH_TYPE_TURBOT 2641 +#define MACH_TYPE_SANDDAB 2642 +#define MACH_TYPE_MX35_CICADA 2643 +#define MACH_TYPE_GHI2703D 2644 +#define MACH_TYPE_LUX_SFX9 2645 +#define MACH_TYPE_LUX_SF9G 2646 +#define MACH_TYPE_LUX_EDK9 2647 +#define MACH_TYPE_HW90240 2648 +#define MACH_TYPE_DM365_LEOPARD 2649 +#define MACH_TYPE_MITYOMAPL138 2650 +#define MACH_TYPE_SCAT110 2651 +#define MACH_TYPE_ACER_A1 2652 +#define MACH_TYPE_CMCONTROL 2653 +#define MACH_TYPE_PELCO_LAMAR 2654 +#define MACH_TYPE_RFP43 2655 +#define MACH_TYPE_SK86R0301 2656 +#define MACH_TYPE_CTPXA 2657 +#define MACH_TYPE_EPB_ARM9_A 2658 +#define MACH_TYPE_GURUPLUG 2659 +#define MACH_TYPE_SPEAR310 2660 +#define MACH_TYPE_SPEAR320 2661 +#define MACH_TYPE_ROBOTX 2662 +#define MACH_TYPE_LSXHL 2663 +#define MACH_TYPE_SMARTLITE 2664 +#define MACH_TYPE_CWS2 2665 +#define MACH_TYPE_M619 2666 +#define MACH_TYPE_SMARTVIEW 2667 +#define MACH_TYPE_LSA_SALSA 2668 +#define MACH_TYPE_KIZBOX 2669 +#define MACH_TYPE_HTCCHARMER 2670 +#define MACH_TYPE_GUF_NESO_LT 2671 +#define MACH_TYPE_PM9G45 2672 +#define MACH_TYPE_HTCPANTHER 2673 +#define MACH_TYPE_HTCPANTHER_CDMA 2674 +#define MACH_TYPE_REB01 2675 +#define MACH_TYPE_AQUILA 2676 +#define MACH_TYPE_SPARK_SLS_HW2 2677 +#define MACH_TYPE_ESATA_SHEEVAPLUG 2678 +#define MACH_TYPE_MSM7X30_SURF 2679 +#define MACH_TYPE_MICRO2440 2680 +#define MACH_TYPE_AM2440 2681 +#define MACH_TYPE_TQ2440 2682 +#define MACH_TYPE_EA2478DEVKIT 2683 +#define MACH_TYPE_AK880X 2684 +#define MACH_TYPE_COBRA3530 2685 +#define MACH_TYPE_PMPPB 2686 +#define MACH_TYPE_U6715 2687 +#define MACH_TYPE_AXAR1500_SENDER 2688 +#define MACH_TYPE_G30_DVB 2689 +#define MACH_TYPE_VC088X 2690 +#define MACH_TYPE_MIOA702 2691 +#define MACH_TYPE_HPMIN 2692 +#define MACH_TYPE_AK880XAK 2693 +#define MACH_TYPE_ARM926TOMAP850 2694 +#define MACH_TYPE_LKEVM 2695 +#define MACH_TYPE_MW6410 2696 +#define MACH_TYPE_TERASTATION_WXL 2697 +#define MACH_TYPE_CPU8000E 2698 +#define MACH_TYPE_TOKYO 2700 +#define MACH_TYPE_MSM7201A_SURF 2701 +#define MACH_TYPE_MSM7201A_FFA 2702 +#define MACH_TYPE_MSM7X25_SURF 2703 +#define MACH_TYPE_MSM7X25_FFA 2704 +#define MACH_TYPE_MSM7X27_SURF 2705 +#define MACH_TYPE_MSM7X27_FFA 2706 +#define MACH_TYPE_MSM7X30_FFA 2707 +#define MACH_TYPE_QSD8X50_SURF 2708 +#define MACH_TYPE_QSD8X50_COMET 2709 +#define MACH_TYPE_QSD8X50_FFA 2710 +#define MACH_TYPE_QSD8X50A_SURF 2711 +#define MACH_TYPE_QSD8X50A_FFA 2712 +#define MACH_TYPE_ADX_XGCP10 2713 +#define MACH_TYPE_MCGWUMTS2A 2714 +#define MACH_TYPE_MOBIKT 2715 +#define MACH_TYPE_MX53_EVK 2716 +#define MACH_TYPE_IGEP0030 2717 +#define MACH_TYPE_AXELL_H40_H50_CTRL 2718 +#define MACH_TYPE_DTCOMMOD 2719 +#define MACH_TYPE_GOULD 2720 +#define MACH_TYPE_SIBERIA 2721 +#define MACH_TYPE_SBC3530 2722 +#define MACH_TYPE_QARM 2723 +#define MACH_TYPE_MIPS 2724 +#define MACH_TYPE_MX27GRB 2725 +#define MACH_TYPE_SBC8100 2726 +#define MACH_TYPE_SAARB 2727 +#define MACH_TYPE_OMAP3MINI 2728 +#define MACH_TYPE_CNMBOOK7SE 2729 +#define MACH_TYPE_CATAN 2730 +#define MACH_TYPE_HARMONY 2731 +#define MACH_TYPE_TONGA 2732 +#define MACH_TYPE_CYBOOK_ORIZON 2733 +#define MACH_TYPE_HTCRHODIUMCDMA 2734 +#define MACH_TYPE_EPC_G45 2735 +#define MACH_TYPE_EPC_LPC3250 2736 +#define MACH_TYPE_MXC91341EVB 2737 +#define MACH_TYPE_RTW1000 2738 +#define MACH_TYPE_BOBCAT 2739 +#define MACH_TYPE_TRIZEPS6 2740 +#define MACH_TYPE_MSM7X30_FLUID 2741 +#define MACH_TYPE_NEDAP9263 2742 +#define MACH_TYPE_NETGEAR_MS2110 2743 +#define MACH_TYPE_BMX 2744 +#define MACH_TYPE_NETSTREAM 2745 +#define MACH_TYPE_VPNEXT_RCU 2746 +#define MACH_TYPE_VPNEXT_MPU 2747 +#define MACH_TYPE_BCMRING_TABLET_V1 2748 +#define MACH_TYPE_SGARM10 2749 +#define MACH_TYPE_OMAP3_CPS 2751 +#define MACH_TYPE_AXAR1500_RECEIVER 2752 +#define MACH_TYPE_WBD222 2753 +#define MACH_TYPE_MT65XX 2754 +#define MACH_TYPE_MSM8X60_SURF 2755 +#define MACH_TYPE_MSM8X60_SIM 2756 +#define MACH_TYPE_TCC8000_SDK 2758 +#define MACH_TYPE_NANOS 2759 +#define MACH_TYPE_STAMP9G10 2760 +#define MACH_TYPE_STAMP9G45 2761 +#define MACH_TYPE_H6053 2762 +#define MACH_TYPE_SMINT01 2763 +#define MACH_TYPE_PRTLVT2 2764 +#define MACH_TYPE_AP420 2765 +#define MACH_TYPE_DAVINCI_DM365_FC 2767 +#define MACH_TYPE_MSM8X55_SURF 2768 +#define MACH_TYPE_MSM8X55_FFA 2769 +#define MACH_TYPE_ESL_VAMANA 2770 +#define MACH_TYPE_SBC35 2771 +#define MACH_TYPE_MPX6446 2772 +#define MACH_TYPE_OREO_CONTROLLER 2773 +#define MACH_TYPE_KOPIN_MODELS 2774 +#define MACH_TYPE_TTC_VISION2 2775 +#define MACH_TYPE_CNS3420VB 2776 +#define MACH_TYPE_LPC2 2777 +#define MACH_TYPE_OLYMPUS 2778 +#define MACH_TYPE_VORTEX 2779 +#define MACH_TYPE_S5PC200 2780 +#define MACH_TYPE_ECUCORE_9263 2781 +#define MACH_TYPE_SMDKC200 2782 +#define MACH_TYPE_EMSISO_SX27 2783 +#define MACH_TYPE_APX_SOM9G45_EK 2784 +#define MACH_TYPE_SONGSHAN 2785 +#define MACH_TYPE_TIANSHAN 2786 +#define MACH_TYPE_VPX500 2787 +#define MACH_TYPE_AM3517SAM 2788 +#define MACH_TYPE_SKAT91_SIM508 2789 +#define MACH_TYPE_SKAT91_S3E 2790 +#define MACH_TYPE_OMAP4_PANDA 2791 +#define MACH_TYPE_DF7220 2792 +#define MACH_TYPE_NEMINI 2793 +#define MACH_TYPE_T8200 2794 +#define MACH_TYPE_APF51 2795 +#define MACH_TYPE_DR_RC_UNIT 2796 +#define MACH_TYPE_BORDEAUX 2797 +#define MACH_TYPE_CATANIA_B 2798 +#define MACH_TYPE_MX51_OCEAN 2799 +#define MACH_TYPE_TI8168EVM 2800 +#define MACH_TYPE_NEOCOREOMAP 2801 +#define MACH_TYPE_WITHINGS_WBP 2802 +#define MACH_TYPE_DBPS 2803 +#define MACH_TYPE_PCBFP0001 2805 +#define MACH_TYPE_SPEEDY 2806 +#define MACH_TYPE_CHRYSAOR 2807 +#define MACH_TYPE_TANGO 2808 +#define MACH_TYPE_SYNOLOGY_DSX11 2809 +#define MACH_TYPE_HANLIN_V3EXT 2810 +#define MACH_TYPE_HANLIN_V5 2811 +#define MACH_TYPE_HANLIN_V3PLUS 2812 +#define MACH_TYPE_IRIVER_STORY 2813 +#define MACH_TYPE_IREX_ILIAD 2814 +#define MACH_TYPE_IREX_DR1000 2815 +#define MACH_TYPE_TETON_BGA 2816 +#define MACH_TYPE_SNAPPER9G45 2817 +#define MACH_TYPE_TAM3517 2818 +#define MACH_TYPE_PDC100 2819 +#define MACH_TYPE_EUKREA_CPUIMX25SD 2820 +#define MACH_TYPE_EUKREA_CPUIMX35SD 2821 +#define MACH_TYPE_EUKREA_CPUIMX51SD 2822 +#define MACH_TYPE_EUKREA_CPUIMX51 2823 +#define MACH_TYPE_P565 2824 +#define MACH_TYPE_ACER_A4 2825 +#define MACH_TYPE_DAVINCI_DM368_BIP 2826 +#define MACH_TYPE_ESHARE 2827 +#define MACH_TYPE_WLBARGN 2829 +#define MACH_TYPE_BM170 2830 +#define MACH_TYPE_NETSPACE_MINI_V2 2831 +#define MACH_TYPE_NETSPACE_PLUG_V2 2832 +#define MACH_TYPE_SIEMENS_L1 2833 +#define MACH_TYPE_ELV_LCU1 2834 +#define MACH_TYPE_MCU1 2835 +#define MACH_TYPE_OMAP3_TAO3530 2836 +#define MACH_TYPE_OMAP3_PCUTOUCH 2837 +#define MACH_TYPE_SMDKC210 2838 +#define MACH_TYPE_OMAP3_BRAILLO 2839 +#define MACH_TYPE_SPYPLUG 2840 +#define MACH_TYPE_GINGER 2841 +#define MACH_TYPE_TNY_T3530 2842 +#define MACH_TYPE_PCAAL1 2843 +#define MACH_TYPE_SPADE 2844 +#define MACH_TYPE_MXC25_TOPAZ 2845 +#define MACH_TYPE_T5325 2846 +#define MACH_TYPE_GW2361 2847 +#define MACH_TYPE_ELOG 2848 +#define MACH_TYPE_INCOME 2849 +#define MACH_TYPE_BCM589X 2850 +#define MACH_TYPE_ETNA 2851 +#define MACH_TYPE_HAWKS 2852 +#define MACH_TYPE_MESON 2853 +#define MACH_TYPE_XSBASE255 2854 +#define MACH_TYPE_PVM2030 2855 +#define MACH_TYPE_MIOA502 2856 +#define MACH_TYPE_VVBOX_SDORIG2 2857 +#define MACH_TYPE_VVBOX_SDLITE2 2858 +#define MACH_TYPE_VVBOX_SDPRO4 2859 +#define MACH_TYPE_HTC_SPV_M700 2860 +#define MACH_TYPE_MX257SX 2861 +#define MACH_TYPE_GONI 2862 +#define MACH_TYPE_MSM8X55_SVLTE_FFA 2863 +#define MACH_TYPE_MSM8X55_SVLTE_SURF 2864 +#define MACH_TYPE_QUICKSTEP 2865 +#define MACH_TYPE_DMW96 2866 +#define MACH_TYPE_HAMMERHEAD 2867 +#define MACH_TYPE_TRIDENT 2868 +#define MACH_TYPE_LIGHTNING 2869 +#define MACH_TYPE_ICONNECT 2870 +#define MACH_TYPE_AUTOBOT 2871 +#define MACH_TYPE_COCONUT 2872 +#define MACH_TYPE_DURIAN 2873 +#define MACH_TYPE_CAYENNE 2874 +#define MACH_TYPE_FUJI 2875 +#define MACH_TYPE_SYNOLOGY_6282 2876 +#define MACH_TYPE_EM1SY 2877 +#define MACH_TYPE_M502 2878 +#define MACH_TYPE_MATRIX518 2879 +#define MACH_TYPE_TINY_GURNARD 2880 +#define MACH_TYPE_SPEAR1310 2881 +#define MACH_TYPE_BV07 2882 +#define MACH_TYPE_MXT_TD61 2883 +#define MACH_TYPE_OPENRD_ULTIMATE 2884 +#define MACH_TYPE_DEVIXP 2885 +#define MACH_TYPE_MICCPT 2886 +#define MACH_TYPE_MIC256 2887 +#define MACH_TYPE_AS1167 2888 +#define MACH_TYPE_OMAP3_IBIZA 2889 +#define MACH_TYPE_U5500 2890 +#define MACH_TYPE_DAVINCI_PICTO 2891 +#define MACH_TYPE_MECHA 2892 +#define MACH_TYPE_BUBBA3 2893 +#define MACH_TYPE_PUPITRE 2894 +#define MACH_TYPE_TEGRA_VOGUE 2896 +#define MACH_TYPE_TEGRA_E1165 2897 +#define MACH_TYPE_SIMPLENET 2898 +#define MACH_TYPE_EC4350TBM 2899 +#define MACH_TYPE_PEC_TC 2900 +#define MACH_TYPE_PEC_HC2 2901 +#define MACH_TYPE_ESL_MOBILIS_A 2902 +#define MACH_TYPE_ESL_MOBILIS_B 2903 +#define MACH_TYPE_ESL_WAVE_A 2904 +#define MACH_TYPE_ESL_WAVE_B 2905 +#define MACH_TYPE_UNISENSE_MMM 2906 +#define MACH_TYPE_BLUESHARK 2907 +#define MACH_TYPE_E10 2908 +#define MACH_TYPE_APP3K_ROBIN 2909 +#define MACH_TYPE_POV15HD 2910 +#define MACH_TYPE_STELLA 2911 +#define MACH_TYPE_LINKSTATION_LSCHL 2913 +#define MACH_TYPE_NETWALKER 2914 +#define MACH_TYPE_ACSX106 2915 +#define MACH_TYPE_ATLAS5_C1 2916 +#define MACH_TYPE_NSB3AST 2917 +#define MACH_TYPE_GNET_SLC 2918 +#define MACH_TYPE_AF4000 2919 +#define MACH_TYPE_ARK9431 2920 +#define MACH_TYPE_FS_S5PC100 2921 +#define MACH_TYPE_OMAP3505NOVA8 2922 +#define MACH_TYPE_OMAP3621_EDP1 2923 +#define MACH_TYPE_ORATISAES 2924 +#define MACH_TYPE_SMDKV310 2925 +#define MACH_TYPE_SIEMENS_L0 2926 +#define MACH_TYPE_VENTANA 2927 +#define MACH_TYPE_WM8505_7IN_NETBOOK 2928 +#define MACH_TYPE_EC4350SDB 2929 +#define MACH_TYPE_MIMAS 2930 +#define MACH_TYPE_TITAN 2931 +#define MACH_TYPE_CRANEBOARD 2932 +#define MACH_TYPE_ES2440 2933 +#define MACH_TYPE_NAJAY_A9263 2934 +#define MACH_TYPE_HTCTORNADO 2935 +#define MACH_TYPE_DIMM_MX257 2936 +#define MACH_TYPE_JIGEN 2937 +#define MACH_TYPE_SMDK6450 2938 +#define MACH_TYPE_MENO_QNG 2939 +#define MACH_TYPE_NS2416 2940 +#define MACH_TYPE_RPC353 2941 +#define MACH_TYPE_TQ6410 2942 +#define MACH_TYPE_SKY6410 2943 +#define MACH_TYPE_DYNASTY 2944 +#define MACH_TYPE_VIVO 2945 +#define MACH_TYPE_BURY_BL7582 2946 +#define MACH_TYPE_BURY_BPS5270 2947 +#define MACH_TYPE_BASI 2948 +#define MACH_TYPE_TN200 2949 +#define MACH_TYPE_C2MMI 2950 +#define MACH_TYPE_MESON_6236M 2951 +#define MACH_TYPE_MESON_8626M 2952 +#define MACH_TYPE_TUBE 2953 +#define MACH_TYPE_MESSINA 2954 +#define MACH_TYPE_MX50_ARM2 2955 +#define MACH_TYPE_CETUS9263 2956 +#define MACH_TYPE_BROWNSTONE 2957 +#define MACH_TYPE_VMX25 2958 +#define MACH_TYPE_VMX51 2959 +#define MACH_TYPE_ABACUS 2960 +#define MACH_TYPE_CM4745 2961 +#define MACH_TYPE_ORATISLINK 2962 +#define MACH_TYPE_DAVINCI_DM365_DVR 2963 +#define MACH_TYPE_NETVIZ 2964 +#define MACH_TYPE_FLEXIBITY 2965 +#define MACH_TYPE_WLAN_COMPUTER 2966 +#define MACH_TYPE_LPC24XX 2967 +#define MACH_TYPE_SPICA 2968 +#define MACH_TYPE_GPSDISPLAY 2969 +#define MACH_TYPE_BIPNET 2970 +#define MACH_TYPE_OVERO_CTU_INERTIAL 2971 +#define MACH_TYPE_DAVINCI_DM355_MMM 2972 +#define MACH_TYPE_PC9260_V2 2973 +#define MACH_TYPE_PTX7545 2974 +#define MACH_TYPE_TM_EFDC 2975 +#define MACH_TYPE_OMAP3_WALDO1 2977 +#define MACH_TYPE_FLYER 2978 +#define MACH_TYPE_TORNADO3240 2979 +#define MACH_TYPE_SOLI_01 2980 +#define MACH_TYPE_OMAPL138_EUROPALC 2981 +#define MACH_TYPE_HELIOS_V1 2982 +#define MACH_TYPE_NETSPACE_LITE_V2 2983 +#define MACH_TYPE_SSC 2984 +#define MACH_TYPE_PREMIERWAVE_EN 2985 +#define MACH_TYPE_WASABI 2986 +#define MACH_TYPE_MX50_RDP 2988 +#define MACH_TYPE_UNIVERSAL_C210 2989 +#define MACH_TYPE_REAL6410 2990 +#define MACH_TYPE_SPX_SAKURA 2991 +#define MACH_TYPE_IJ3K_2440 2992 +#define MACH_TYPE_OMAP3_BC10 2993 +#define MACH_TYPE_THEBE 2994 +#define MACH_TYPE_RV082 2995 +#define MACH_TYPE_ARMLGUEST 2996 +#define MACH_TYPE_TJINC1000 2997 +#define MACH_TYPE_DOCKSTAR 2998 +#define MACH_TYPE_AX8008 2999 +#define MACH_TYPE_GNET_SGCE 3000 +#define MACH_TYPE_PXWNAS_500_1000 3001 +#define MACH_TYPE_AWM2 3003 +#define MACH_TYPE_TI8148EVM 3004 +#define MACH_TYPE_SEABOARD 3005 +#define MACH_TYPE_LINKSTATION_CHLV2 3006 +#define MACH_TYPE_TERA_PRO2_RACK 3007 +#define MACH_TYPE_RUBYS 3008 +#define MACH_TYPE_AQUARIUS 3009 +#define MACH_TYPE_MX53_ARD 3010 +#define MACH_TYPE_MX53_SMD 3011 +#define MACH_TYPE_LSWXL 3012 +#define MACH_TYPE_DOVE_AVNG_V3 3013 +#define MACH_TYPE_SDI_ESS_9263 3014 +#define MACH_TYPE_JOCPU550 3015 +#define MACH_TYPE_MSM8X60_RUMI3 3016 +#define MACH_TYPE_MSM8X60_FFA 3017 +#define MACH_TYPE_YANOMAMI 3018 +#define MACH_TYPE_GTA04 3019 +#define MACH_TYPE_CM_A510 3020 +#define MACH_TYPE_OMAP3_RFS200 3021 +#define MACH_TYPE_KX33XX 3022 +#define MACH_TYPE_PTX7510 3023 +#define MACH_TYPE_TOP9000 3024 +#define MACH_TYPE_TEENOTE 3025 +#define MACH_TYPE_TS3 3026 +#define MACH_TYPE_A0 3027 +#define MACH_TYPE_FSM9XXX_SURF 3028 +#define MACH_TYPE_FSM9XXX_FFA 3029 +#define MACH_TYPE_FRRHWCDMA60W 3030 +#define MACH_TYPE_REMUS 3031 +#define MACH_TYPE_AT91CAP7XDK 3032 +#define MACH_TYPE_AT91CAP7STK 3033 +#define MACH_TYPE_KT_SBC_SAM9_1 3034 +#define MACH_TYPE_ARMADA_XP_DB 3036 +#define MACH_TYPE_SPDM 3037 +#define MACH_TYPE_GTIB 3038 +#define MACH_TYPE_DGM3240 3039 +#define MACH_TYPE_ATLAS_I_LPE 3040 +#define MACH_TYPE_HTCMEGA 3041 +#define MACH_TYPE_TRICORDER 3042 +#define MACH_TYPE_TX28 3043 +#define MACH_TYPE_BSTBRD 3044 +#define MACH_TYPE_PWB3090 3045 +#define MACH_TYPE_IDEA6410 3046 +#define MACH_TYPE_QBC9263 3047 +#define MACH_TYPE_BORABORA 3048 +#define MACH_TYPE_VALDEZ 3049 +#define MACH_TYPE_LS9G20 3050 +#define MACH_TYPE_MIOS_V1 3051 +#define MACH_TYPE_S5PC110_CRESPO 3052 +#define MACH_TYPE_CONTROLTEK9G20 3053 +#define MACH_TYPE_TIN307 3054 +#define MACH_TYPE_TIN510 3055 +#define MACH_TYPE_EP3517 3056 +#define MACH_TYPE_BLUECHEESE 3057 +#define MACH_TYPE_TEM3X30 3058 +#define MACH_TYPE_HARVEST_DESOTO 3059 +#define MACH_TYPE_MSM8X60_QRDC 3060 +#define MACH_TYPE_SPEAR900 3061 +#define MACH_TYPE_PCONTROL_G20 3062 +#define MACH_TYPE_RDSTOR 3063 +#define MACH_TYPE_USDLOADER 3064 +#define MACH_TYPE_TSOPLOADER 3065 +#define MACH_TYPE_KRONOS 3066 +#define MACH_TYPE_FFCORE 3067 +#define MACH_TYPE_MONE 3068 +#define MACH_TYPE_UNIT2S 3069 +#define MACH_TYPE_ACER_A5 3070 +#define MACH_TYPE_ETHERPRO_ISP 3071 +#define MACH_TYPE_STRETCHS7000 3072 +#define MACH_TYPE_P87_SMARTSIM 3073 +#define MACH_TYPE_TULIP 3074 +#define MACH_TYPE_SUNFLOWER 3075 +#define MACH_TYPE_RIB 3076 +#define MACH_TYPE_CLOD 3077 +#define MACH_TYPE_RUMP 3078 +#define MACH_TYPE_TENDERLOIN 3079 +#define MACH_TYPE_SHORTLOIN 3080 +#define MACH_TYPE_ANTARES 3082 +#define MACH_TYPE_WB40N 3083 +#define MACH_TYPE_HERRING 3084 +#define MACH_TYPE_NAXY400 3085 +#define MACH_TYPE_NAXY1200 3086 +#define MACH_TYPE_VPR200 3087 +#define MACH_TYPE_BUG20 3088 +#define MACH_TYPE_GOFLEXNET 3089 +#define MACH_TYPE_TORBRECK 3090 +#define MACH_TYPE_SAARB_MG1 3091 +#define MACH_TYPE_CALLISTO 3092 +#define MACH_TYPE_MULTHSU 3093 +#define MACH_TYPE_SALUDA 3094 +#define MACH_TYPE_PEMP_OMAP3_APOLLO 3095 +#define MACH_TYPE_VC0718 3096 +#define MACH_TYPE_MVBLX 3097 +#define MACH_TYPE_INHAND_APEIRON 3098 +#define MACH_TYPE_INHAND_FURY 3099 +#define MACH_TYPE_INHAND_SIREN 3100 +#define MACH_TYPE_HDNVP 3101 +#define MACH_TYPE_SOFTWINNER 3102 +#define MACH_TYPE_PRIMA2_EVB 3103 +#define MACH_TYPE_NAS6210 3104 +#define MACH_TYPE_UNISDEV 3105 +#define MACH_TYPE_SBCA11 3106 +#define MACH_TYPE_SAGA 3107 +#define MACH_TYPE_NS_K330 3108 +#define MACH_TYPE_TANNA 3109 +#define MACH_TYPE_IMATE8502 3110 +#define MACH_TYPE_ASPEN 3111 +#define MACH_TYPE_DAINTREE_CWAC 3112 +#define MACH_TYPE_ZMX25 3113 +#define MACH_TYPE_MAPLE1 3114 +#define MACH_TYPE_QSD8X72_SURF 3115 +#define MACH_TYPE_QSD8X72_FFA 3116 +#define MACH_TYPE_ABILENE 3117 +#define MACH_TYPE_EIGEN_TTR 3118 +#define MACH_TYPE_IOMEGA_IX2_200 3119 +#define MACH_TYPE_CORETEC_VCX7400 3120 +#define MACH_TYPE_SANTIAGO 3121 +#define MACH_TYPE_MX257SOL 3122 +#define MACH_TYPE_STRASBOURG 3123 +#define MACH_TYPE_MSM8X60_FLUID 3124 +#define MACH_TYPE_SMARTQV5 3125 +#define MACH_TYPE_SMARTQV3 3126 +#define MACH_TYPE_SMARTQV7 3127 +#define MACH_TYPE_PAZ00 3128 +#define MACH_TYPE_ACMENETUSFOXG20 3129 +#define MACH_TYPE_FWBD_0404 3131 +#define MACH_TYPE_HDGU 3132 +#define MACH_TYPE_PYRAMID 3133 +#define MACH_TYPE_EPIPHAN 3134 +#define MACH_TYPE_OMAP_BENDER 3135 +#define MACH_TYPE_GURNARD 3136 +#define MACH_TYPE_GTL_IT5100 3137 +#define MACH_TYPE_BCM2708 3138 +#define MACH_TYPE_MX51_GGC 3139 +#define MACH_TYPE_SHARESPACE 3140 +#define MACH_TYPE_HABA_KNX_EXPLORER 3141 +#define MACH_TYPE_SIMTEC_KIRKMOD 3142 +#define MACH_TYPE_CRUX 3143 +#define MACH_TYPE_MX51_BRAVO 3144 +#define MACH_TYPE_CHARON 3145 +#define MACH_TYPE_PICOCOM3 3146 +#define MACH_TYPE_PICOCOM4 3147 +#define MACH_TYPE_SERRANO 3148 +#define MACH_TYPE_DOUBLESHOT 3149 +#define MACH_TYPE_EVSY 3150 +#define MACH_TYPE_HUASHAN 3151 +#define MACH_TYPE_LAUSANNE 3152 +#define MACH_TYPE_EMERALD 3153 +#define MACH_TYPE_TQMA35 3154 +#define MACH_TYPE_MARVEL 3155 +#define MACH_TYPE_MANUAE 3156 +#define MACH_TYPE_CHACHA 3157 +#define MACH_TYPE_LEMON 3158 +#define MACH_TYPE_CSC 3159 +#define MACH_TYPE_GIRA_KNXIP_ROUTER 3160 +#define MACH_TYPE_T20 3161 +#define MACH_TYPE_HDMINI 3162 +#define MACH_TYPE_SCIPHONE_G2 3163 +#define MACH_TYPE_EXPRESS 3164 +#define MACH_TYPE_EXPRESS_KT 3165 +#define MACH_TYPE_MAXIMASP 3166 +#define MACH_TYPE_NITROGEN_IMX51 3167 +#define MACH_TYPE_NITROGEN_IMX53 3168 +#define MACH_TYPE_SUNFIRE 3169 +#define MACH_TYPE_AROWANA 3170 +#define MACH_TYPE_TEGRA_DAYTONA 3171 +#define MACH_TYPE_TEGRA_SWORDFISH 3172 +#define MACH_TYPE_EDISON 3173 +#define MACH_TYPE_SVP8500V1 3174 +#define MACH_TYPE_SVP8500V2 3175 +#define MACH_TYPE_SVP5500 3176 +#define MACH_TYPE_B5500 3177 +#define MACH_TYPE_S5500 3178 +#define MACH_TYPE_ICON 3179 +#define MACH_TYPE_ELEPHANT 3180 +#define MACH_TYPE_SHOOTER 3182 +#define MACH_TYPE_SPADE_LTE 3183 +#define MACH_TYPE_PHILHWANI 3184 +#define MACH_TYPE_GSNCOMM 3185 +#define MACH_TYPE_STRASBOURG_A2 3186 +#define MACH_TYPE_MMM 3187 +#define MACH_TYPE_DAVINCI_DM365_BV 3188 +#define MACH_TYPE_AG5EVM 3189 +#define MACH_TYPE_SC575PLC 3190 +#define MACH_TYPE_SC575IPC 3191 +#define MACH_TYPE_OMAP3_TDM3730 3192 +#define MACH_TYPE_TOP9000_EVAL 3194 +#define MACH_TYPE_TOP9000_SU 3195 +#define MACH_TYPE_UTM300 3196 +#define MACH_TYPE_TSUNAGI 3197 +#define MACH_TYPE_TS75XX 3198 +#define MACH_TYPE_TS47XX 3200 +#define MACH_TYPE_DA850_K5 3201 +#define MACH_TYPE_AX502 3202 +#define MACH_TYPE_IGEP0032 3203 +#define MACH_TYPE_ANTERO 3204 +#define MACH_TYPE_SYNERGY 3205 +#define MACH_TYPE_ICS_IF_VOIP 3206 +#define MACH_TYPE_WLF_CRAGG_6410 3207 +#define MACH_TYPE_PUNICA 3208 +#define MACH_TYPE_TRIMSLICE 3209 +#define MACH_TYPE_MX27_WMULTRA 3210 +#define MACH_TYPE_MACKEREL 3211 +#define MACH_TYPE_FA9X27 3213 +#define MACH_TYPE_NS2816TB 3214 +#define MACH_TYPE_NS2816_NTPAD 3215 +#define MACH_TYPE_NS2816_NTNB 3216 +#define MACH_TYPE_KAEN 3217 +#define MACH_TYPE_NV1000 3218 +#define MACH_TYPE_NUC950TS 3219 +#define MACH_TYPE_NOKIA_RM680 3220 +#define MACH_TYPE_AST2200 3221 +#define MACH_TYPE_LEAD 3222 +#define MACH_TYPE_UNINO1 3223 +#define MACH_TYPE_GREECO 3224 +#define MACH_TYPE_VERDI 3225 +#define MACH_TYPE_DM6446_ADBOX 3226 +#define MACH_TYPE_QUAD_SALSA 3227 +#define MACH_TYPE_ABB_GMA_1_1 3228 +#define MACH_TYPE_SVCID 3229 +#define MACH_TYPE_MSM8960_SIM 3230 +#define MACH_TYPE_MSM8960_RUMI3 3231 +#define MACH_TYPE_ICON_G 3232 +#define MACH_TYPE_MB3 3233 +#define MACH_TYPE_GSIA18S 3234 +#define MACH_TYPE_PIVICC 3235 +#define MACH_TYPE_PCM048 3236 +#define MACH_TYPE_DDS 3237 +#define MACH_TYPE_CHALTEN_XA1 3238 +#define MACH_TYPE_TS48XX 3239 +#define MACH_TYPE_TONGA2_TFTTIMER 3240 +#define MACH_TYPE_WHISTLER 3241 +#define MACH_TYPE_ASL_PHOENIX 3242 +#define MACH_TYPE_AT91SAM9263OTLITE 3243 +#define MACH_TYPE_DDPLUG 3244 +#define MACH_TYPE_D2PLUG 3245 +#define MACH_TYPE_KZM9D 3246 +#define MACH_TYPE_VERDI_LTE 3247 +#define MACH_TYPE_NANOZOOM 3248 +#define MACH_TYPE_DM3730_SOM_LV 3249 +#define MACH_TYPE_DM3730_TORPEDO 3250 +#define MACH_TYPE_ANCHOVY 3251 +#define MACH_TYPE_RE2REV20 3253 +#define MACH_TYPE_RE2REV21 3254 +#define MACH_TYPE_CNS21XX 3255 +#define MACH_TYPE_RIDER 3257 +#define MACH_TYPE_NSK330 3258 +#define MACH_TYPE_CNS2133EVB 3259 +#define MACH_TYPE_Z3_816X_MOD 3260 +#define MACH_TYPE_Z3_814X_MOD 3261 +#define MACH_TYPE_BEECT 3262 +#define MACH_TYPE_DMA_THUNDERBUG 3263 +#define MACH_TYPE_OMN_AT91SAM9G20 3264 +#define MACH_TYPE_MX25_E2S_UC 3265 +#define MACH_TYPE_MIONE 3266 +#define MACH_TYPE_TOP9000_TCU 3267 +#define MACH_TYPE_TOP9000_BSL 3268 +#define MACH_TYPE_KINGDOM 3269 +#define MACH_TYPE_ARMADILLO460 3270 +#define MACH_TYPE_LQ2 3271 +#define MACH_TYPE_SWEDA_TMS2 3272 +#define MACH_TYPE_MX53_LOCO 3273 +#define MACH_TYPE_ACER_A8 3275 +#define MACH_TYPE_ACER_GAUGUIN 3276 +#define MACH_TYPE_GUPPY 3277 +#define MACH_TYPE_MX61_ARD 3278 +#define MACH_TYPE_TX53 3279 +#define MACH_TYPE_OMAPL138_CASE_A3 3280 +#define MACH_TYPE_UEMD 3281 +#define MACH_TYPE_CCWMX51MUT 3282 +#define MACH_TYPE_ROCKHOPPER 3283 +#define MACH_TYPE_ENCORE 3284 +#define MACH_TYPE_HKDKC100 3285 +#define MACH_TYPE_TS42XX 3286 +#define MACH_TYPE_AEBL 3287 +#define MACH_TYPE_WARIO 3288 +#define MACH_TYPE_GFS_SPM 3289 +#define MACH_TYPE_CM_T3730 3290 +#define MACH_TYPE_ISC3 3291 +#define MACH_TYPE_RASCAL 3292 +#define MACH_TYPE_HREFV60 3293 +#define MACH_TYPE_TPT_2_0 3294 +#define MACH_TYPE_PYRAMID_TD 3295 +#define MACH_TYPE_SPLENDOR 3296 +#define MACH_TYPE_GUF_PLANET 3297 +#define MACH_TYPE_MSM8X60_QT 3298 +#define MACH_TYPE_HTC_HD_MINI 3299 +#define MACH_TYPE_ATHENE 3300 +#define MACH_TYPE_DEEP_R_EK_1 3301 +#define MACH_TYPE_VIVOW_CT 3302 +#define MACH_TYPE_NERY_1000 3303 +#define MACH_TYPE_RFL109145_SSRV 3304 +#define MACH_TYPE_NMH 3305 +#define MACH_TYPE_WN802T 3306 +#define MACH_TYPE_DRAGONET 3307 +#define MACH_TYPE_GENEVA_B 3308 +#define MACH_TYPE_AT91SAM9263DESK16L 3309 +#define MACH_TYPE_BCMHANA_SV 3310 +#define MACH_TYPE_BCMHANA_TABLET 3311 +#define MACH_TYPE_KOI 3312 +#define MACH_TYPE_TS4800 3313 +#define MACH_TYPE_TQMA9263 3314 +#define MACH_TYPE_HOLIDAY 3315 +#define MACH_TYPE_DMA6410 3316 +#define MACH_TYPE_PCATS_OVERLAY 3317 +#define MACH_TYPE_HWGW6410 3318 +#define MACH_TYPE_SHENZHOU 3319 +#define MACH_TYPE_CWME9210 3320 +#define MACH_TYPE_CWME9210JS 3321 +#define MACH_TYPE_PGS_SITARA 3322 +#define MACH_TYPE_COLIBRI_TEGRA2 3323 +#define MACH_TYPE_W21 3324 +#define MACH_TYPE_POLYSAT1 3325 +#define MACH_TYPE_DATAWAY 3326 +#define MACH_TYPE_COBRAL138 3327 +#define MACH_TYPE_ROVERPCS8 3328 +#define MACH_TYPE_MARVELC 3329 +#define MACH_TYPE_NAVEFIHID 3330 +#define MACH_TYPE_DM365_CV100 3331 +#define MACH_TYPE_ABLE 3332 +#define MACH_TYPE_LEGACY 3333 +#define MACH_TYPE_ICONG 3334 +#define MACH_TYPE_ROVER_G8 3335 +#define MACH_TYPE_T5388P 3336 +#define MACH_TYPE_DINGO 3337 +#define MACH_TYPE_GOFLEXHOME 3338 +#define MACH_TYPE_LANREADYFN511 3340 +#define MACH_TYPE_OMAP3_BAIA 3341 +#define MACH_TYPE_OMAP3SMARTDISPLAY 3342 +#define MACH_TYPE_XILINX 3343 +#define MACH_TYPE_A2F 3344 +#define MACH_TYPE_SKY25 3345 +#define MACH_TYPE_CCMX53 3346 +#define MACH_TYPE_CCMX53JS 3347 +#define MACH_TYPE_CCWMX53 3348 +#define MACH_TYPE_CCWMX53JS 3349 +#define MACH_TYPE_FRISMS 3350 +#define MACH_TYPE_MSM7X27A_FFA 3351 +#define MACH_TYPE_MSM7X27A_SURF 3352 +#define MACH_TYPE_MSM7X27A_RUMI3 3353 +#define MACH_TYPE_DIMMSAM9G20 3354 +#define MACH_TYPE_DIMM_IMX28 3355 +#define MACH_TYPE_AMK_A4 3356 +#define MACH_TYPE_GNET_SGME 3357 +#define MACH_TYPE_SHOOTER_U 3358 +#define MACH_TYPE_VMX53 3359 +#define MACH_TYPE_RHINO 3360 +#define MACH_TYPE_ARMLEX4210 3361 +#define MACH_TYPE_SWARCOEXTMODEM 3362 +#define MACH_TYPE_SNOWBALL 3363 +#define MACH_TYPE_PCM049 3364 +#define MACH_TYPE_VIGOR 3365 +#define MACH_TYPE_OSLO_AMUNDSEN 3366 +#define MACH_TYPE_GSL_DIAMOND 3367 +#define MACH_TYPE_CV2201 3368 +#define MACH_TYPE_CV2202 3369 +#define MACH_TYPE_CV2203 3370 +#define MACH_TYPE_VIT_IBOX 3371 +#define MACH_TYPE_DM6441_ESP 3372 +#define MACH_TYPE_AT91SAM9X5EK 3373 +#define MACH_TYPE_LIBRA 3374 +#define MACH_TYPE_EASYCRRH 3375 +#define MACH_TYPE_TRIPEL 3376 +#define MACH_TYPE_ENDIAN_MINI 3377 +#define MACH_TYPE_XILINX_EP107 3378 +#define MACH_TYPE_NURI 3379 +#define MACH_TYPE_JANUS 3380 +#define MACH_TYPE_DDNAS 3381 +#define MACH_TYPE_TAG 3382 +#define MACH_TYPE_TAGW 3383 +#define MACH_TYPE_NITROGEN_VM_IMX51 3384 +#define MACH_TYPE_VIPRINET 3385 +#define MACH_TYPE_BOCKW 3386 +#define MACH_TYPE_EVA2000 3387 +#define MACH_TYPE_STEELYARD 3388 +#define MACH_TYPE_LPC2468OEM 3389 +#define MACH_TYPE_MACH_SDH001 3390 +#define MACH_TYPE_LPC2478MICROBLOX 3391 +#define MACH_TYPE_NSSLSBOARD 3392 +#define MACH_TYPE_GENEVA_B5 3393 +#define MACH_TYPE_SPEAR1340 3394 +#define MACH_TYPE_REXMAS 3395 +#define MACH_TYPE_MSM8960_CDP 3396 +#define MACH_TYPE_MSM8960_MDP 3397 +#define MACH_TYPE_MSM8960_FLUID 3398 +#define MACH_TYPE_MSM8960_APQ 3399 +#define MACH_TYPE_HELIOS_V2 3400 +#define MACH_TYPE_MIF10P 3401 +#define MACH_TYPE_IAM28 3402 +#define MACH_TYPE_PICASSO 3403 +#define MACH_TYPE_MR301A 3404 +#define MACH_TYPE_NOTLE 3405 +#define MACH_TYPE_EELX2 3406 +#define MACH_TYPE_MOON 3407 +#define MACH_TYPE_RUBY 3408 +#define MACH_TYPE_GOLDENGATE 3409 +#define MACH_TYPE_CTBU_GEN2 3410 +#define MACH_TYPE_KMP_AM17_01 3411 +#define MACH_TYPE_WTPLUG 3412 +#define MACH_TYPE_MX27SU2 3413 +#define MACH_TYPE_NB31 3414 +#define MACH_TYPE_HJSDU 3415 +#define MACH_TYPE_TD3_REV1 3416 +#define MACH_TYPE_EAG_CI4000 3417 +#define MACH_TYPE_NET5BIG_NAND_V2 3418 +#define MACH_TYPE_CPX2 3419 +#define MACH_TYPE_NET2BIG_NAND_V2 3420 +#define MACH_TYPE_ECUV5 3421 +#define MACH_TYPE_HSGX6D 3422 +#define MACH_TYPE_DAWAD7 3423 +#define MACH_TYPE_SAM9REPEATER 3424 +#define MACH_TYPE_GT_I5700 3425 +#define MACH_TYPE_CTERA_PLUG_C2 3426 +#define MACH_TYPE_MARVELCT 3427 +#define MACH_TYPE_AG11005 3428 +#define MACH_TYPE_OMAP_BLAZE 3429 +#define MACH_TYPE_VANGOGH 3430 +#define MACH_TYPE_MATRIX505 3431 +#define MACH_TYPE_OCE_NIGMA 3432 +#define MACH_TYPE_T55 3433 +#define MACH_TYPE_BIO3K 3434 +#define MACH_TYPE_EXPRESSCT 3435 +#define MACH_TYPE_CARDHU 3436 +#define MACH_TYPE_ARUBA 3437 +#define MACH_TYPE_BONAIRE 3438 +#define MACH_TYPE_NUC700EVB 3439 +#define MACH_TYPE_NUC710EVB 3440 +#define MACH_TYPE_NUC740EVB 3441 +#define MACH_TYPE_NUC745EVB 3442 +#define MACH_TYPE_TRANSCEDE 3443 +#define MACH_TYPE_MORA 3444 +#define MACH_TYPE_NDA_EVM 3445 +#define MACH_TYPE_TIMU 3446 +#define MACH_TYPE_EXPRESSH 3447 +#define MACH_TYPE_VERIDIS_A300 3448 +#define MACH_TYPE_DM368_LEOPARD 3449 +#define MACH_TYPE_OMAP_MCOP 3450 +#define MACH_TYPE_TRITIP 3451 +#define MACH_TYPE_SM1K 3452 +#define MACH_TYPE_MONCH 3453 +#define MACH_TYPE_CURACAO 3454 +#define MACH_TYPE_ORIGEN 3455 +#define MACH_TYPE_EPC10 3456 +#define MACH_TYPE_SGH_I740 3457 +#define MACH_TYPE_TUNA 3458 +#define MACH_TYPE_MX51_TULIP 3459 +#define MACH_TYPE_MX51_ASTER7 3460 +#define MACH_TYPE_ACRO37XBRD 3461 +#define MACH_TYPE_ELKE 3462 +#define MACH_TYPE_SBC6000X 3463 +#define MACH_TYPE_R1801E 3464 +#define MACH_TYPE_H1600 3465 +#define MACH_TYPE_MINI210 3466 +#define MACH_TYPE_MINI8168 3467 +#define MACH_TYPE_PC7308 3468 +#define MACH_TYPE_GE863 3469 +#define MACH_TYPE_KMM2M01 3470 +#define MACH_TYPE_MX51EREBUS 3471 +#define MACH_TYPE_WM8650REFBOARD 3472 +#define MACH_TYPE_TUXRAIL 3473 +#define MACH_TYPE_ARTHUR 3474 +#define MACH_TYPE_DOORBOY 3475 +#define MACH_TYPE_XARINA 3476 +#define MACH_TYPE_ROVERX7 3477 +#define MACH_TYPE_SDVR 3478 +#define MACH_TYPE_ACER_MAYA 3479 +#define MACH_TYPE_PICO 3480 +#define MACH_TYPE_CWMX233 3481 +#define MACH_TYPE_CWAM1808 3482 +#define MACH_TYPE_CWDM365 3483 +#define MACH_TYPE_MX51_MORAY 3484 +#define MACH_TYPE_THALES_CBC 3485 +#define MACH_TYPE_BLUEPOINT 3486 +#define MACH_TYPE_DIR665 3487 +#define MACH_TYPE_ACMEROVER1 3488 +#define MACH_TYPE_SHOOTER_CT 3489 +#define MACH_TYPE_BLISS 3490 +#define MACH_TYPE_BLISSC 3491 +#define MACH_TYPE_THALES_ADC 3492 +#define MACH_TYPE_UBISYS_P9D_EVP 3493 +#define MACH_TYPE_ATDGP318 3494 +#define MACH_TYPE_DMA210U 3495 +#define MACH_TYPE_EM_T3 3496 +#define MACH_TYPE_HTX3250 3497 +#define MACH_TYPE_G50 3498 +#define MACH_TYPE_ECO5 3499 +#define MACH_TYPE_WINTERGRASP 3500 +#define MACH_TYPE_PURO 3501 +#define MACH_TYPE_SHOOTER_K 3502 +#define MACH_TYPE_NSPIRE 3503 +#define MACH_TYPE_MICKXX 3504 +#define MACH_TYPE_LXMB 3505 +#define MACH_TYPE_TMDXSCBP6616X 3506 +#define MACH_TYPE_ADAM 3507 +#define MACH_TYPE_B1004 3508 +#define MACH_TYPE_OBOEA 3509 +#define MACH_TYPE_A1015 3510 +#define MACH_TYPE_ROBIN_VBDT30 3511 +#define MACH_TYPE_TEGRA_ENTERPRISE 3512 +#define MACH_TYPE_RFL108200_MK10 3513 +#define MACH_TYPE_RFL108300_MK16 3514 +#define MACH_TYPE_ROVER_V7 3515 +#define MACH_TYPE_MIPHONE 3516 +#define MACH_TYPE_FEMTOBTS 3517 +#define MACH_TYPE_MONOPOLI 3518 +#define MACH_TYPE_BOSS 3519 +#define MACH_TYPE_DAVINCI_DM368_VTAM 3520 +#define MACH_TYPE_CLCON 3521 +#define MACH_TYPE_NOKIA_RM696 3522 +#define MACH_TYPE_TAHITI 3523 +#define MACH_TYPE_FIGHTER 3524 +#define MACH_TYPE_SGH_I710 3525 +#define MACH_TYPE_INTEGREPROSCB 3526 +#define MACH_TYPE_MONZA 3527 +#define MACH_TYPE_MX6Q_SABREAUTO 3529 +#define MACH_TYPE_GMA01X 3530 +#define MACH_TYPE_SBC51 3531 +#define MACH_TYPE_FIT 3532 +#define MACH_TYPE_STEELHEAD 3533 +#define MACH_TYPE_PANTHER 3534 +#define MACH_TYPE_MSM8960_LIQUID 3535 +#define MACH_TYPE_LEXIKONCT 3536 +#define MACH_TYPE_NS2816_STB 3537 +#define MACH_TYPE_SEI_MM2_LPC3250 3538 +#define MACH_TYPE_CMIMX53 3539 +#define MACH_TYPE_SANDWICH 3540 +#define MACH_TYPE_CHIEF 3541 +#define MACH_TYPE_POGO_E02 3542 +#define MACH_TYPE_MIKRAP_X168 3543 +#define MACH_TYPE_HTCMOZART 3544 +#define MACH_TYPE_HTCGOLD 3545 +#define MACH_TYPE_MT72XX 3546 +#define MACH_TYPE_MX51_IVY 3547 +#define MACH_TYPE_MX51_LVD 3548 +#define MACH_TYPE_OMAP3_WISER2 3549 +#define MACH_TYPE_DREAMPLUG 3550 +#define MACH_TYPE_COBAS_C_111 3551 +#define MACH_TYPE_COBAS_U_411 3552 +#define MACH_TYPE_HSSD 3553 +#define MACH_TYPE_IOM35X 3554 +#define MACH_TYPE_PSOM_OMAP 3555 +#define MACH_TYPE_IPHONE_2G 3556 +#define MACH_TYPE_IPHONE_3G 3557 +#define MACH_TYPE_IPOD_TOUCH_1G 3558 +#define MACH_TYPE_PHAROS_TPC 3559 +#define MACH_TYPE_MX53_HYDRA 3560 +#define MACH_TYPE_NS2816_DEV_BOARD 3561 +#define MACH_TYPE_IPHONE_3GS 3562 +#define MACH_TYPE_IPHONE_4 3563 +#define MACH_TYPE_IPOD_TOUCH_4G 3564 +#define MACH_TYPE_DRAGON_E1100 3565 +#define MACH_TYPE_TOPSIDE 3566 +#define MACH_TYPE_IRISIII 3567 +#define MACH_TYPE_DETO_MACARM9 3568 +#define MACH_TYPE_ETI_D1 3569 +#define MACH_TYPE_SOM3530SDK 3570 +#define MACH_TYPE_OC_ENGINE 3571 +#define MACH_TYPE_APQ8064_SIM 3572 +#define MACH_TYPE_ALPS 3575 +#define MACH_TYPE_TNY_T3730 3576 +#define MACH_TYPE_GERYON_NFE 3577 +#define MACH_TYPE_NS2816_REF_BOARD 3578 +#define MACH_TYPE_SILVERSTONE 3579 +#define MACH_TYPE_MTT2440 3580 +#define MACH_TYPE_YNICDB 3581 +#define MACH_TYPE_BCT 3582 +#define MACH_TYPE_TUSCAN 3583 +#define MACH_TYPE_XBT_SAM9G45 3584 +#define MACH_TYPE_ENBW_CMC 3585 +#define MACH_TYPE_APQ8060_DRAGON 3586 +#define MACH_TYPE_CH104MX257 3587 +#define MACH_TYPE_OPENPRI 3588 +#define MACH_TYPE_AM335XEVM 3589 +#define MACH_TYPE_PICODMB 3590 +#define MACH_TYPE_WALUIGI 3591 +#define MACH_TYPE_PUNICAG7 3592 +#define MACH_TYPE_IPAD_1G 3593 +#define MACH_TYPE_APPLETV_2G 3594 +#define MACH_TYPE_MACH_ECOG45 3595 +#define MACH_TYPE_AIT_CAM_ENC_4XX 3596 +#define MACH_TYPE_RUNNYMEDE 3597 +#define MACH_TYPE_PLAY 3598 +#define MACH_TYPE_HW90260 3599 +#define MACH_TYPE_TAGH 3600 +#define MACH_TYPE_FILBERT 3601 +#define MACH_TYPE_GETINGE_NETCOMV3 3602 +#define MACH_TYPE_CW20 3603 +#define MACH_TYPE_CINEMA 3604 +#define MACH_TYPE_CINEMA_TEA 3605 +#define MACH_TYPE_CINEMA_COFFEE 3606 +#define MACH_TYPE_CINEMA_JUICE 3607 +#define MACH_TYPE_THEPAD 3608 +#define MACH_TYPE_MX53_MIRAGE2 3609 +#define MACH_TYPE_MX53_EFIKASB 3610 +#define MACH_TYPE_STM_B2000 3612 +#define MACH_TYPE_M28EVK 3613 +#define MACH_TYPE_PDA 3614 +#define MACH_TYPE_MERAKI_MR58 3615 +#define MACH_TYPE_KOTA2 3616 +#define MACH_TYPE_LETCOOL 3617 +#define MACH_TYPE_MX27IAT 3618 +#define MACH_TYPE_APOLLO_TD 3619 +#define MACH_TYPE_ARENA 3620 +#define MACH_TYPE_GSNGATEWAY 3621 +#define MACH_TYPE_LF2000 3622 +#define MACH_TYPE_BONITO 3623 +#define MACH_TYPE_ASYMPTOTE 3624 +#define MACH_TYPE_BST2BRD 3625 +#define MACH_TYPE_TX335S 3626 +#define MACH_TYPE_PELCO_TESLA 3627 +#define MACH_TYPE_RRHTESTPLAT 3628 +#define MACH_TYPE_VIDTONIC_PRO 3629 +#define MACH_TYPE_PL_APOLLO 3630 +#define MACH_TYPE_PL_PHOENIX 3631 +#define MACH_TYPE_M28CU3 3632 +#define MACH_TYPE_VVBOX_HD 3633 +#define MACH_TYPE_COREWARE_SAM9260_ 3634 +#define MACH_TYPE_MARMADUKE 3635 +#define MACH_TYPE_AMG_XLCORE_CAMERA 3636 +#define MACH_TYPE_OMAP3_EGF 3637 +#define MACH_TYPE_SMDK4212 3638 +#define MACH_TYPE_DNP9200 3639 +#define MACH_TYPE_TF101 3640 +#define MACH_TYPE_OMAP3SILVIO 3641 +#define MACH_TYPE_PICASSO2 3642 +#define MACH_TYPE_VANGOGH2 3643 +#define MACH_TYPE_OLPC_XO_1_75 3644 +#define MACH_TYPE_GX400 3645 +#define MACH_TYPE_GS300 3646 +#define MACH_TYPE_ACER_A9 3647 +#define MACH_TYPE_VIVOW_EVM 3648 +#define MACH_TYPE_VELOCE_CXQ 3649 +#define MACH_TYPE_VELOCE_CXM 3650 +#define MACH_TYPE_P1852 3651 +#define MACH_TYPE_NAXY100 3652 +#define MACH_TYPE_TAISHAN 3653 +#define MACH_TYPE_TOUCHLINK 3654 +#define MACH_TYPE_STM32F103ZE 3655 +#define MACH_TYPE_STM_NMHDK_FLI7610 3657 +#define MACH_TYPE_TOP28X 3658 +#define MACH_TYPE_OKL4VP_MICROVISOR 3659 +#define MACH_TYPE_POP 3660 +#define MACH_TYPE_LAYER 3661 +#define MACH_TYPE_TRONDHEIM 3662 +#define MACH_TYPE_EVA 3663 +#define MACH_TYPE_TRUST_TAURUS 3664 +#define MACH_TYPE_NS2816_HUASHAN 3665 +#define MACH_TYPE_NS2816_YANGCHENG 3666 +#define MACH_TYPE_P852 3667 +#define MACH_TYPE_FLEA3 3668 +#define MACH_TYPE_BOWFIN 3669 +#define MACH_TYPE_MV88DE3100 3670 +#define MACH_TYPE_PIA_AM35X 3671 +#define MACH_TYPE_CEDAR 3672 +#define MACH_TYPE_PICASSO_E 3673 +#define MACH_TYPE_SAMSUNG_E60 3674 +#define MACH_TYPE_MDM9615 3675 +#define MACH_TYPE_SDVR_MINI 3676 +#define MACH_TYPE_OMAP3_IJ3K 3677 +#define MACH_TYPE_MODASMC1 3678 +#define MACH_TYPE_APQ8064_RUMI3 3679 +#define MACH_TYPE_MATRIX506 3680 +#define MACH_TYPE_MSM9615_MTP 3681 +#define MACH_TYPE_DM36X_SPAWNDC 3682 +#define MACH_TYPE_SFF792 3683 +#define MACH_TYPE_AM335XIAEVM 3684 +#define MACH_TYPE_G3C2440 3685 +#define MACH_TYPE_TION270 3686 +#define MACH_TYPE_W22Q7ARM02 3687 +#define MACH_TYPE_OMAP_CAT 3688 +#define MACH_TYPE_AT91SAM9N12EK 3689 +#define MACH_TYPE_MORRISON 3690 +#define MACH_TYPE_SVDU 3691 +#define MACH_TYPE_LPP01 3692 +#define MACH_TYPE_UBC283 3693 +#define MACH_TYPE_ZEPPELIN 3694 +#define MACH_TYPE_MOTUS 3695 +#define MACH_TYPE_NEOMAINBOARD 3696 +#define MACH_TYPE_DEVKIT3250 3697 +#define MACH_TYPE_DEVKIT7000 3698 +#define MACH_TYPE_FMC_UIC 3699 +#define MACH_TYPE_FMC_DCM 3700 +#define MACH_TYPE_BATWM 3701 +#define MACH_TYPE_ATLAS6CB 3702 +#define MACH_TYPE_QUATTROF 3703 +#define MACH_TYPE_QUATTROU 3704 +#define MACH_TYPE_BLUE 3705 +#define MACH_TYPE_COLORADO 3706 +#define MACH_TYPE_POPC 3707 +#define MACH_TYPE_PROMWAD_JADE 3708 +#define MACH_TYPE_AMP 3709 +#define MACH_TYPE_GNET_AMP 3710 +#define MACH_TYPE_TOQUES 3711 +#define MACH_TYPE_APX4DEVKIT 3712 +#define MACH_TYPE_DCT_STORM 3713 +#define MACH_TYPE_Z3 3714 +#define MACH_TYPE_OWL 3715 +#define MACH_TYPE_COGENT_CSB1741 3716 +#define MACH_TYPE_OMAP3 3717 +#define MACH_TYPE_ADILLUSTRA610 3718 +#define MACH_TYPE_ECAFE_NA04 3719 +#define MACH_TYPE_POPCT 3720 +#define MACH_TYPE_OMAP3_HELENA 3721 +#define MACH_TYPE_ACH 3722 +#define MACH_TYPE_MODULE_DTB 3723 +#define MACH_TYPE_RACKBOX 3724 +#define MACH_TYPE_OSLO_ELISABETH 3725 +#define MACH_TYPE_TT01 3726 +#define MACH_TYPE_MSM8930_CDP 3727 +#define MACH_TYPE_MSM8930_MTP 3728 +#define MACH_TYPE_MSM8930_FLUID 3729 +#define MACH_TYPE_LTU11 3730 +#define MACH_TYPE_AM1808_SPAWNCO 3731 +#define MACH_TYPE_FLX6410 3732 +#define MACH_TYPE_MX6Q_QSB 3733 +#define MACH_TYPE_MX53_PLT424 3734 +#define MACH_TYPE_JASMINE 3735 +#define MACH_TYPE_L138_OWLBOARD_PLUS 3736 +#define MACH_TYPE_WR21 3737 +#define MACH_TYPE_PEABOY 3739 +#define MACH_TYPE_MX28_PLATO 3740 +#define MACH_TYPE_KACOM2 3741 +#define MACH_TYPE_SLCO 3742 +#define MACH_TYPE_IMX51PICO 3743 +#define MACH_TYPE_GLINK1 3744 +#define MACH_TYPE_DIAMOND 3745 +#define MACH_TYPE_D9000 3746 +#define MACH_TYPE_W5300E01 3747 +#define MACH_TYPE_IM6000 3748 +#define MACH_TYPE_MX51_FRED51 3749 +#define MACH_TYPE_STM32F2 3750 +#define MACH_TYPE_VILLE 3751 +#define MACH_TYPE_PTIP_MURNAU 3752 +#define MACH_TYPE_PTIP_CLASSIC 3753 +#define MACH_TYPE_MX53GRB 3754 +#define MACH_TYPE_GAGARIN 3755 +#define MACH_TYPE_MSM7X27A_QRD1 3756 +#define MACH_TYPE_NAS2BIG 3757 +#define MACH_TYPE_SUPERFEMTO 3758 +#define MACH_TYPE_TEUFEL 3759 +#define MACH_TYPE_DINARA 3760 +#define MACH_TYPE_VANQUISH 3761 +#define MACH_TYPE_ZIPABOX1 3762 +#define MACH_TYPE_U9540 3763 +#define MACH_TYPE_JET 3764 +#define MACH_TYPE_SMDK4412 3765 +#define MACH_TYPE_ELITE 3766 +#define MACH_TYPE_SPEAR320_HMI 3767 +#define MACH_TYPE_ONTARIO 3768 +#define MACH_TYPE_MX6Q_SABRELITE 3769 +#define MACH_TYPE_VC200 3770 +#define MACH_TYPE_MSM7625A_FFA 3771 +#define MACH_TYPE_MSM7625A_SURF 3772 +#define MACH_TYPE_BENTHOSSBP 3773 +#define MACH_TYPE_SMDK5210 3774 +#define MACH_TYPE_EMPQ2300 3775 +#define MACH_TYPE_MINIPOS 3776 +#define MACH_TYPE_OMAP5_SEVM 3777 +#define MACH_TYPE_SHELTER 3778 +#define MACH_TYPE_OMAP3_DEVKIT8500 3779 +#define MACH_TYPE_EDGETD 3780 +#define MACH_TYPE_COPPERYARD 3781 +#define MACH_TYPE_EDGE 3782 +#define MACH_TYPE_EDGE_U 3783 +#define MACH_TYPE_EDGE_TD 3784 +#define MACH_TYPE_WDSS 3785 +#define MACH_TYPE_DL_PB25 3786 +#define MACH_TYPE_DSS11 3787 +#define MACH_TYPE_CPA 3788 +#define MACH_TYPE_APTP2000 3789 +#define MACH_TYPE_MARZEN 3790 +#define MACH_TYPE_ST_TURBINE 3791 +#define MACH_TYPE_GTL_IT3300 3792 +#define MACH_TYPE_MX6_MULE 3793 +#define MACH_TYPE_V7PXA_DT 3794 +#define MACH_TYPE_V7MMP_DT 3795 +#define MACH_TYPE_DRAGON7 3796 +#define MACH_TYPE_KROME 3797 +#define MACH_TYPE_ORATISDANTE 3798 +#define MACH_TYPE_FATHOM 3799 +#define MACH_TYPE_DNS325 3800 +#define MACH_TYPE_SARNEN 3801 +#define MACH_TYPE_UBISYS_G1 3802 +#define MACH_TYPE_MX53_PF1 3803 +#define MACH_TYPE_ASANTI 3804 +#define MACH_TYPE_VOLTA 3805 +#define MACH_TYPE_S5P6450 3806 +#define MACH_TYPE_KNIGHT 3807 +#define MACH_TYPE_BEAGLEBONE 3808 +#define MACH_TYPE_BECKER 3809 +#define MACH_TYPE_FC360 3810 +#define MACH_TYPE_PMI2_XLS 3811 +#define MACH_TYPE_TARANTO 3812 +#define MACH_TYPE_PLUTUX 3813 +#define MACH_TYPE_IPMP_MEDCOM 3814 +#define MACH_TYPE_ABSOLUT 3815 +#define MACH_TYPE_AWPB3 3816 +#define MACH_TYPE_NFP32XX_DT 3817 +#define MACH_TYPE_DL_PB53 3818 +#define MACH_TYPE_ACU_II 3819 +#define MACH_TYPE_AVALON 3820 +#define MACH_TYPE_SPHINX 3821 +#define MACH_TYPE_TITAN_T 3822 +#define MACH_TYPE_HARVEST_BORIS 3823 +#define MACH_TYPE_MACH_MSM7X30_M3S 3824 +#define MACH_TYPE_SMDK5250 3825 +#define MACH_TYPE_IMXT_LITE 3826 +#define MACH_TYPE_IMXT_STD 3827 +#define MACH_TYPE_IMXT_LOG 3828 +#define MACH_TYPE_IMXT_NAV 3829 +#define MACH_TYPE_IMXT_FULL 3830 +#define MACH_TYPE_AG09015 3831 +#define MACH_TYPE_DP1ARM9 3833 +#define MACH_TYPE_PICASSO_M 3834 +#define MACH_TYPE_VIDEO_GADGET 3835 +#define MACH_TYPE_MTT_OM3X 3836 +#define MACH_TYPE_MX6Q_ARM2 3837 +#define MACH_TYPE_PICOSAM9G45 3838 +#define MACH_TYPE_VPM_DM365 3839 +#define MACH_TYPE_BONFIRE 3840 +#define MACH_TYPE_MT2P2D 3841 +#define MACH_TYPE_SIGPDA01 3842 +#define MACH_TYPE_CN27 3843 +#define MACH_TYPE_MX25_CWTAP 3844 +#define MACH_TYPE_APF28 3845 +#define MACH_TYPE_PELCO_MAXWELL 3846 +#define MACH_TYPE_GE_PHOENIX 3847 +#define MACH_TYPE_EMPC_A500 3848 +#define MACH_TYPE_IMS_ARM9 3849 +#define MACH_TYPE_MINI2416 3850 +#define MACH_TYPE_MINI2450 3851 +#define MACH_TYPE_MINI310 3852 +#define MACH_TYPE_SPEAR_HURRICANE 3853 +#define MACH_TYPE_MT7208 3854 +#define MACH_TYPE_LPC178X 3855 +#define MACH_TYPE_FARLEYS 3856 +#define MACH_TYPE_EFM32GG_DK3750 3857 +#define MACH_TYPE_ZEUS_BOARD 3858 +#define MACH_TYPE_CC51 3859 +#define MACH_TYPE_FXI_C210 3860 +#define MACH_TYPE_MSM8627_CDP 3861 +#define MACH_TYPE_MSM8627_MTP 3862 +#define MACH_TYPE_ARMADILLO800EVA 3863 +#define MACH_TYPE_PRIMOU 3864 +#define MACH_TYPE_PRIMOC 3865 +#define MACH_TYPE_PRIMOCT 3866 +#define MACH_TYPE_A9500 3867 +#define MACH_TYPE_PULSE_TD 3868 +#define MACH_TYPE_PLUTO 3869 +#define MACH_TYPE_ACFX100 3870 +#define MACH_TYPE_MSM8625_RUMI3 3871 +#define MACH_TYPE_VALENTE 3872 +#define MACH_TYPE_CRFS_RFEYE 3873 +#define MACH_TYPE_RFEYE 3874 +#define MACH_TYPE_PHIDGET_SBC3 3875 +#define MACH_TYPE_TCW_MIKA 3876 +#define MACH_TYPE_IMX28_EGF 3877 +#define MACH_TYPE_VALENTE_WX 3878 +#define MACH_TYPE_HUANGSHANS 3879 +#define MACH_TYPE_BOSPHORUS1 3880 +#define MACH_TYPE_PRIMA 3881 +#define MACH_TYPE_M3_SKT 3882 +#define MACH_TYPE_M3_REF 3883 +#define MACH_TYPE_EVITA_ULK 3884 +#define MACH_TYPE_MERISC600 3885 +#define MACH_TYPE_DOLAK 3886 +#define MACH_TYPE_SBC53 3887 +#define MACH_TYPE_ELITE_ULK 3888 +#define MACH_TYPE_POV2 3889 +#define MACH_TYPE_IPOD_TOUCH_2G 3890 +#define MACH_TYPE_DA850_PQAB 3891 +#define MACH_TYPE_FERMI 3892 +#define MACH_TYPE_CCARDWMX28 3893 +#define MACH_TYPE_CCARDMX28 3894 +#define MACH_TYPE_FS20_FCM2050 3895 +#define MACH_TYPE_KINETIS 3896 +#define MACH_TYPE_KAI 3897 +#define MACH_TYPE_BCTHB2 3898 +#define MACH_TYPE_INELS3_CU 3899 +#define MACH_TYPE_JUNIPER 3900 +#define MACH_TYPE_DA850_APOLLO 3901 +#define MACH_TYPE_TRACNAS 3902 +#define MACH_TYPE_MITYARM335X 3903 +#define MACH_TYPE_XCGZ7X 3904 +#define MACH_TYPE_CUBOX 3905 +#define MACH_TYPE_TERMINATOR 3906 +#define MACH_TYPE_EYE03 3907 +#define MACH_TYPE_KOTA3 3908 +#define MACH_TYPE_MX5 3909 +#define MACH_TYPE_PSCPE 3910 +#define MACH_TYPE_AKT1100 3911 +#define MACH_TYPE_PCAAXL2 3912 +#define MACH_TYPE_PRIMODD_CT 3913 +#define MACH_TYPE_NSBC 3914 +#define MACH_TYPE_MESON2_SKT 3915 +#define MACH_TYPE_MESON2_REF 3916 +#define MACH_TYPE_CCARDWMX28JS 3917 +#define MACH_TYPE_CCARDMX28JS 3918 +#define MACH_TYPE_INDICO 3919 +#define MACH_TYPE_MSM8960DT 3920 +#define MACH_TYPE_PRIMODS 3921 +#define MACH_TYPE_BELUGA_M1388 3922 +#define MACH_TYPE_PRIMOTD 3923 +#define MACH_TYPE_VARAN_MASTER 3924 +#define MACH_TYPE_PRIMODD 3925 +#define MACH_TYPE_JETDUO 3926 +#define MACH_TYPE_MX53_UMOBO 3927 +#define MACH_TYPE_TRATS 3928 +#define MACH_TYPE_STARCRAFT 3929 +#define MACH_TYPE_QSEVEN_TEGRA2 3930 +#define MACH_TYPE_LICHEE_SUN4I_DEVBD 3931 +#define MACH_TYPE_MOVENOW 3932 +#define MACH_TYPE_GOLF_U 3933 +#define MACH_TYPE_MSM7627A_EVB 3934 +#define MACH_TYPE_RAMBO 3935 +#define MACH_TYPE_GOLFU 3936 +#define MACH_TYPE_MANGO310 3937 +#define MACH_TYPE_DNS343 3938 +#define MACH_TYPE_VAR_SOM_OM44 3939 +#define MACH_TYPE_NAON 3940 +#define MACH_TYPE_VP4000 3941 +#define MACH_TYPE_IMPCARD 3942 +#define MACH_TYPE_SMOOVCAM 3943 +#define MACH_TYPE_COBHAM3725 3944 +#define MACH_TYPE_COBHAM3730 3945 +#define MACH_TYPE_COBHAM3703 3946 +#define MACH_TYPE_QUETZAL 3947 +#define MACH_TYPE_APQ8064_CDP 3948 +#define MACH_TYPE_APQ8064_MTP 3949 +#define MACH_TYPE_APQ8064_FLUID 3950 +#define MACH_TYPE_APQ8064_LIQUID 3951 +#define MACH_TYPE_MANGO210 3952 +#define MACH_TYPE_MANGO100 3953 +#define MACH_TYPE_MANGO24 3954 +#define MACH_TYPE_MANGO64 3955 +#define MACH_TYPE_NSA320 3956 +#define MACH_TYPE_ELV_CCU2 3957 +#define MACH_TYPE_TRITON_X00 3958 +#define MACH_TYPE_TRITON_1500_2000 3959 +#define MACH_TYPE_POGOPLUGV4 3960 +#define MACH_TYPE_VENUS_CL 3961 +#define MACH_TYPE_VULCANO_G20 3962 +#define MACH_TYPE_SGS_I9100 3963 +#define MACH_TYPE_STSV2 3964 +#define MACH_TYPE_CSB1724 3965 +#define MACH_TYPE_OMAPL138_LCDK 3966 +#define MACH_TYPE_JEWEL_DD 3967 +#define MACH_TYPE_PVD_MX25 3968 +#define MACH_TYPE_MESON6_SKT 3969 +#define MACH_TYPE_MESON6_REF 3970 +#define MACH_TYPE_PXM 3971 +#define MACH_TYPE_S3 3972 +#define MACH_TYPE_POGOPLUGV3 3973 +#define MACH_TYPE_MLP89626 3974 +#define MACH_TYPE_IOMEGAHMNDCE 3975 +#define MACH_TYPE_POGOPLUGV3PCI 3976 +#define MACH_TYPE_BNTV250 3977 +#define MACH_TYPE_MX53_QSEVEN 3978 +#define MACH_TYPE_GTL_IT1100 3979 +#define MACH_TYPE_MX6Q_SABRESD 3980 +#define MACH_TYPE_MT4 3981 +#define MACH_TYPE_JUMBO_D 3982 +#define MACH_TYPE_JUMBO_I 3983 +#define MACH_TYPE_FS20_DMP 3984 +#define MACH_TYPE_DNS320 3985 +#define MACH_TYPE_MX28BACOS 3986 +#define MACH_TYPE_TL80 3987 +#define MACH_TYPE_POLATIS_NIC_1001 3988 +#define MACH_TYPE_TELY 3989 +#define MACH_TYPE_U8520 3990 +#define MACH_TYPE_MANTA 3991 +#define MACH_TYPE_SPEAR_EM_S900 3992 +#define MACH_TYPE_MPQ8064_CDP 3993 +#define MACH_TYPE_MPQ8064_STB 3994 +#define MACH_TYPE_MPQ8064_DTV 3995 +#define MACH_TYPE_DM368SOM 3996 +#define MACH_TYPE_GPRISB2 3997 +#define MACH_TYPE_CHAMMID 3998 +#define MACH_TYPE_SEOUL2 3999 +#define MACH_TYPE_OMAP4_NOOKTABLET 4000 +#define MACH_TYPE_AALTO 4001 +#define MACH_TYPE_METRO 4002 +#define MACH_TYPE_CYDM3730 4003 +#define MACH_TYPE_TQMA53 4004 +#define MACH_TYPE_MSM7627A_QRD3 4005 +#define MACH_TYPE_MX28_CANBY 4006 +#define MACH_TYPE_TIGER 4007 +#define MACH_TYPE_PCATS_9307_TYPE_A 4008 +#define MACH_TYPE_PCATS_9307_TYPE_O 4009 +#define MACH_TYPE_PCATS_9307_TYPE_R 4010 +#define MACH_TYPE_STREAMPLUG 4011 +#define MACH_TYPE_ICECHICKEN_DEV 4012 +#define MACH_TYPE_HEDGEHOG 4013 +#define MACH_TYPE_YUSEND_OBC 4014 +#define MACH_TYPE_IMXNINJA 4015 +#define MACH_TYPE_OMAP4_JAROD 4016 +#define MACH_TYPE_ECO5_PK 4017 +#define MACH_TYPE_QJ2440 4018 +#define MACH_TYPE_MX6Q_MERCURY 4019 +#define MACH_TYPE_CM6810 4020 +#define MACH_TYPE_OMAP4_TORPEDO 4021 +#define MACH_TYPE_NSA310 4022 +#define MACH_TYPE_TMX536 4023 +#define MACH_TYPE_KTT20 4024 +#define MACH_TYPE_DRAGONIX 4025 +#define MACH_TYPE_LUNGCHING 4026 +#define MACH_TYPE_BULOGICS 4027 +#define MACH_TYPE_MX535_SX 4028 +#define MACH_TYPE_NGUI3250 4029 +#define MACH_TYPE_SALUTEC_DAC 4030 +#define MACH_TYPE_LOCO 4031 +#define MACH_TYPE_CTERA_PLUG_USI 4032 +#define MACH_TYPE_SCEPTER 4033 +#define MACH_TYPE_SGA 4034 +#define MACH_TYPE_P_81_J5 4035 +#define MACH_TYPE_P_81_O4 4036 +#define MACH_TYPE_MSM8625_SURF 4037 +#define MACH_TYPE_CARALLON_SHARK 4038 +#define MACH_TYPE_LSGCICAM 4039 +#define MACH_TYPE_ORDOG 4040 +#define MACH_TYPE_PUENTE_IO 4041 +#define MACH_TYPE_MSM8625_EVB 4042 +#define MACH_TYPE_EV_AM1707 4043 +#define MACH_TYPE_EV_AM1707E2 4044 +#define MACH_TYPE_EV_AM3517E2 4045 +#define MACH_TYPE_CALABRIA 4046 +#define MACH_TYPE_EV_IMX287 4047 +#define MACH_TYPE_ERAU 4048 +#define MACH_TYPE_SICHUAN 4049 +#define MACH_TYPE_WIRMA3 4050 +#define MACH_TYPE_DAVINCI_DA850 4051 +#define MACH_TYPE_OMAP138_TRUNARC 4052 +#define MACH_TYPE_BCM4761 4053 +#define MACH_TYPE_PICASSO_E2 4054 +#define MACH_TYPE_PICASSO_MF 4055 +#define MACH_TYPE_MIRO 4056 +#define MACH_TYPE_AT91SAM9G20EWON3 4057 +#define MACH_TYPE_YOYO 4058 +#define MACH_TYPE_WINDJKL 4059 +#define MACH_TYPE_MONARUDO 4060 +#define MACH_TYPE_BATAN 4061 +#define MACH_TYPE_TADAO 4062 +#define MACH_TYPE_BASO 4063 +#define MACH_TYPE_MAHON 4064 +#define MACH_TYPE_VILLEC2 4065 +#define MACH_TYPE_ASI1230 4066 +#define MACH_TYPE_ALASKA 4067 +#define MACH_TYPE_SWARCO_SHDSL2 4068 +#define MACH_TYPE_OXRTU 4069 +#define MACH_TYPE_OMAP5_PANDA 4070 +#define MACH_TYPE_MX28XDI 4071 +#define MACH_TYPE_C8000 4072 +#define MACH_TYPE_BJE_DISPLAY3_5 4073 +#define MACH_TYPE_PICOMOD7 4074 +#define MACH_TYPE_PICOCOM5 4075 +#define MACH_TYPE_QBLISSA8 4076 +#define MACH_TYPE_ARMSTONEA8 4077 +#define MACH_TYPE_NETDCU14 4078 +#define MACH_TYPE_AT91SAM9X5_EPIPHAN 4079 +#define MACH_TYPE_P2U 4080 +#define MACH_TYPE_DORIS 4081 +#define MACH_TYPE_J49 4082 +#define MACH_TYPE_VDSS2E 4083 +#define MACH_TYPE_VC300 4084 +#define MACH_TYPE_NS115_PAD_TEST 4085 +#define MACH_TYPE_NS115_PAD_REF 4086 +#define MACH_TYPE_NS115_PHONE_TEST 4087 +#define MACH_TYPE_NS115_PHONE_REF 4088 +#define MACH_TYPE_GOLFC 4089 +#define MACH_TYPE_XEROX_OLYMPUS 4090 +#define MACH_TYPE_MX6SL_ARM2 4091 +#define MACH_TYPE_CSB1701_CSB1726 4092 +#define MACH_TYPE_AT91SAM9XEEK 4093 +#define MACH_TYPE_EBV210 4094 +#define MACH_TYPE_MSM7627A_QRD7 4095 +#define MACH_TYPE_SVTHIN 4096 +#define MACH_TYPE_DUOVERO 4097 +#define MACH_TYPE_CHUPACABRA 4098 +#define MACH_TYPE_SCORPION 4099 +#define MACH_TYPE_DAVINCI_HE_HMI10 4100 +#define MACH_TYPE_TOPKICK 4101 +#define MACH_TYPE_M3_AUGUESTRUSH 4102 +#define MACH_TYPE_IPC335X 4103 +#define MACH_TYPE_SUN4I 4104 +#define MACH_TYPE_IMX233_OLINUXINO 4105 +#define MACH_TYPE_K2_WL 4106 +#define MACH_TYPE_K2_UL 4107 +#define MACH_TYPE_K2_CL 4108 +#define MACH_TYPE_MINBARI_W 4109 +#define MACH_TYPE_MINBARI_M 4110 +#define MACH_TYPE_K035 4111 +#define MACH_TYPE_ARIEL 4112 +#define MACH_TYPE_ARIELSAARC 4113 +#define MACH_TYPE_ARIELDKB 4114 +#define MACH_TYPE_ARMADILLO810 4115 +#define MACH_TYPE_TAM335X 4116 +#define MACH_TYPE_GROUPER 4117 +#define MACH_TYPE_MPCSA21_9G20 4118 +#define MACH_TYPE_M6U_CPU 4119 +#define MACH_TYPE_DAVINCI_DP10 4120 +#define MACH_TYPE_GINKGO 4121 +#define MACH_TYPE_CGT_QMX6 4122 +#define MACH_TYPE_PROFPGA 4123 +#define MACH_TYPE_ACFX100OC 4124 +#define MACH_TYPE_ACFX100NB 4125 +#define MACH_TYPE_CAPRICORN 4126 +#define MACH_TYPE_PISCES 4127 +#define MACH_TYPE_ARIES 4128 +#define MACH_TYPE_CANCER 4129 +#define MACH_TYPE_LEO 4130 +#define MACH_TYPE_VIRGO 4131 +#define MACH_TYPE_SAGITTARIUS 4132 +#define MACH_TYPE_DEVIL 4133 +#define MACH_TYPE_BALLANTINES 4134 +#define MACH_TYPE_OMAP3_PROCERUSVPU 4135 +#define MACH_TYPE_MY27 4136 +#define MACH_TYPE_SUN6I 4137 +#define MACH_TYPE_SUN5I 4138 +#define MACH_TYPE_MX512_MX 4139 +#define MACH_TYPE_KZM9G 4140 +#define MACH_TYPE_VDSTBN 4141 +#define MACH_TYPE_CFA10036 4142 +#define MACH_TYPE_CFA10049 4143 +#define MACH_TYPE_PCM051 4144 +#define MACH_TYPE_VYBRID_VF7XX 4145 +#define MACH_TYPE_VYBRID_VF6XX 4146 +#define MACH_TYPE_VYBRID_VF5XX 4147 +#define MACH_TYPE_VYBRID_VF4XX 4148 +#define MACH_TYPE_ARIA_G25 4149 +#define MACH_TYPE_BCM21553 4150 +#define MACH_TYPE_SMDK5410 4151 +#define MACH_TYPE_LPC18XX 4152 +#define MACH_TYPE_ORATISPARTY 4153 +#define MACH_TYPE_QSEVEN 4154 +#define MACH_TYPE_GMV_GENERIC 4155 +#define MACH_TYPE_TH_LINK_ETH 4156 +#define MACH_TYPE_TN_MUNINN 4157 +#define MACH_TYPE_RAMPAGE 4158 +#define MACH_TYPE_VISSTRIM_MV10 4159 +#define MACH_TYPE_MONACO_TDU 4160 +#define MACH_TYPE_MONACO_UL 4161 +#define MACH_TYPE_ENRC2_U 4162 +#define MACH_TYPE_EVITA_UL 4163 +#define MACH_TYPE_MX28_WILMA 4164 +#define MACH_TYPE_MONACO_U 4165 +#define MACH_TYPE_MSM8625_FFA 4166 +#define MACH_TYPE_VPU101 4167 +#define MACH_TYPE_OPERA_UL 4168 +#define MACH_TYPE_BAILEYS 4169 +#define MACH_TYPE_FAMILYBOX 4170 +#define MACH_TYPE_ENSEMBLE_MX35 4171 +#define MACH_TYPE_SC_SPS_1 4172 +#define MACH_TYPE_UCSIMPLY_SAM9260 4173 +#define MACH_TYPE_UNICORN 4174 +#define MACH_TYPE_M9G45A 4175 +#define MACH_TYPE_MTWEBIF 4176 +#define MACH_TYPE_PLAYSTONE 4177 +#define MACH_TYPE_CHELSEA 4178 +#define MACH_TYPE_BAYERN 4179 +#define MACH_TYPE_MITWO 4180 +#define MACH_TYPE_MX25_NOAH 4181 +#define MACH_TYPE_STM_B2020 4182 +#define MACH_TYPE_ANNAX_SRC 4183 +#define MACH_TYPE_IONICS_STRATUS 4184 +#define MACH_TYPE_HUGO 4185 +#define MACH_TYPE_EM300 4186 +#define MACH_TYPE_MMP3_QSEVEN 4187 +#define MACH_TYPE_BOSPHORUS2 4188 +#define MACH_TYPE_TT2200 4189 +#define MACH_TYPE_OCELOT3 4190 +#define MACH_TYPE_TEK_COBRA 4191 +#define MACH_TYPE_PROTOU 4192 +#define MACH_TYPE_MSM8625_EVT 4193 +#define MACH_TYPE_MX53_SELLWOOD 4194 +#define MACH_TYPE_SOMIQ_AM35 4195 +#define MACH_TYPE_SOMIQ_AM37 4196 +#define MACH_TYPE_K2_PLC_CL 4197 +#define MACH_TYPE_TC2 4198 +#define MACH_TYPE_DULEX_J 4199 +#define MACH_TYPE_STM_B2044 4200 +#define MACH_TYPE_DELUXE_J 4201 +#define MACH_TYPE_MANGO2443 4202 +#define MACH_TYPE_CP2DCG 4203 +#define MACH_TYPE_CP2DTG 4204 +#define MACH_TYPE_CP2DUG 4205 +#define MACH_TYPE_VAR_SOM_AM33 4206 +#define MACH_TYPE_PEPPER 4207 +#define MACH_TYPE_MANGO2450 4208 +#define MACH_TYPE_VALENTE_WX_C9 4209 +#define MACH_TYPE_MINITV 4210 +#define MACH_TYPE_U8540 4211 +#define MACH_TYPE_IV_ATLAS_I_Z7E 4212 +#define MACH_TYPE_COGENT_CSB1733 4213 +#define MACH_TYPE_MACH_TYPE_SKY 4214 +#define MACH_TYPE_BLUESKY 4215 +#define MACH_TYPE_NGROUTER 4216 +#define MACH_TYPE_MX53_DENETIM 4217 +#define MACH_TYPE_OPAL 4218 +#define MACH_TYPE_GNET_US3GREF 4219 +#define MACH_TYPE_GNET_NC3G 4220 +#define MACH_TYPE_GNET_GE3G 4221 +#define MACH_TYPE_ADP2 4222 +#define MACH_TYPE_TQMA28 4223 +#define MACH_TYPE_KACOM3 4224 +#define MACH_TYPE_RRHDEMO 4225 +#define MACH_TYPE_PROTODUG 4226 +#define MACH_TYPE_LAGO 4227 +#define MACH_TYPE_KTT30 4228 +#define MACH_TYPE_TS43XX 4229 +#define MACH_TYPE_MX6Q_DENSO 4230 +#define MACH_TYPE_COMSAT_GSMUMTS8 4231 +#define MACH_TYPE_DREAMX 4232 +#define MACH_TYPE_THUNDERSTONEM 4233 +#define MACH_TYPE_YOYOPAD 4234 +#define MACH_TYPE_YOYOPATIENT 4235 +#define MACH_TYPE_A10L 4236 +#define MACH_TYPE_MQ60 4237 +#define MACH_TYPE_LINKSTATION_LSQL 4238 +#define MACH_TYPE_AM3703GATEWAY 4239 +#define MACH_TYPE_ACCIPITER 4240 +#define MACH_TYPE_P1853 4241 +#define MACH_TYPE_MAGNIDUG 4242 +#define MACH_TYPE_HYDRA 4243 +#define MACH_TYPE_SUN3I 4244 +#define MACH_TYPE_STM_B2078 4245 +#define MACH_TYPE_AT91SAM9263DESKV2 4246 +#define MACH_TYPE_DELUXE_R 4247 +#define MACH_TYPE_P_98_V 4248 +#define MACH_TYPE_P_98_C 4249 +#define MACH_TYPE_DAVINCI_AM18XX_OMN 4250 +#define MACH_TYPE_SOCFPGA_CYCLONE5 4251 +#define MACH_TYPE_CABATUIN 4252 +#define MACH_TYPE_YOYOPAD_FT 4253 +#define MACH_TYPE_DAN2400EVB 4254 +#define MACH_TYPE_DAN3400EVB 4255 +#define MACH_TYPE_EDM_SF_IMX6 4256 +#define MACH_TYPE_EDM_CF_IMX6 4257 +#define MACH_TYPE_VPOS3XX 4258 +#define MACH_TYPE_VULCANO_9X5 4259 +#define MACH_TYPE_SPMP8000 4260 +#define MACH_TYPE_CATALINA 4261 +#define MACH_TYPE_RD88F5181L_FE 4262 +#define MACH_TYPE_MX535_MX 4263 +#define MACH_TYPE_ARMADILLO840 4264 +#define MACH_TYPE_SPC9000BASEBOARD 4265 +#define MACH_TYPE_IRIS 4266 +#define MACH_TYPE_PROTODCG 4267 +#define MACH_TYPE_PALMTREE 4268 +#define MACH_TYPE_NOVENA 4269 +#define MACH_TYPE_MA_UM 4270 +#define MACH_TYPE_MA_AM 4271 +#define MACH_TYPE_EMS348 4272 +#define MACH_TYPE_CM_FX6 4273 +#define MACH_TYPE_ARNDALE 4274 +#define MACH_TYPE_Q5XR5 4275 +#define MACH_TYPE_WILLOW 4276 +#define MACH_TYPE_OMAP3621_ODYV3 4277 +#define MACH_TYPE_OMAPL138_PRESONUS 4278 +#define MACH_TYPE_DVF99 4279 +#define MACH_TYPE_IMPRESSION_J 4280 +#define MACH_TYPE_QBLISSA9 4281 +#define MACH_TYPE_ROBIN_HELIVIEW10 4282 +#define MACH_TYPE_SUN7I 4283 +#define MACH_TYPE_MX6Q_HDMIDONGLE 4284 +#define MACH_TYPE_MX6_SID2 4285 +#define MACH_TYPE_HELIOS_V3 4286 +#define MACH_TYPE_HELIOS_V4 4287 +#define MACH_TYPE_Q7_IMX6 4288 +#define MACH_TYPE_ODROIDX 4289 +#define MACH_TYPE_ROBPRO 4290 +#define MACH_TYPE_RESEARCH59IF_MK1 4291 +#define MACH_TYPE_BOBSLEIGH 4292 +#define MACH_TYPE_DCSHGWT3 4293 +#define MACH_TYPE_GLD1018 4294 +#define MACH_TYPE_EV10 4295 +#define MACH_TYPE_NITROGEN6X 4296 +#define MACH_TYPE_P_107_BB 4297 +#define MACH_TYPE_EVITA_UTL 4298 +#define MACH_TYPE_FALCONWING 4299 +#define MACH_TYPE_DCT3 4300 +#define MACH_TYPE_CPX2E_CELL 4301 +#define MACH_TYPE_AMIRO 4302 +#define MACH_TYPE_MX6Q_BRASSBOARD 4303 +#define MACH_TYPE_DALMORE 4304 +#define MACH_TYPE_OMAP3_PORTAL7CP 4305 +#define MACH_TYPE_TEGRA_PLUTO 4306 +#define MACH_TYPE_MX6SL_EVK 4307 +#define MACH_TYPE_M7 4308 +#define MACH_TYPE_PXM2 4309 +#define MACH_TYPE_HABA_KNX_LITE 4310 +#define MACH_TYPE_TAI 4311 +#define MACH_TYPE_PROTOTD 4312 +#define MACH_TYPE_DST_TONTO 4313 +#define MACH_TYPE_DRACO 4314 +#define MACH_TYPE_DXR2 4315 +#define MACH_TYPE_RUT 4316 +#define MACH_TYPE_AM180X_WSC 4317 +#define MACH_TYPE_DELUXE_U 4318 +#define MACH_TYPE_DELUXE_UL 4319 +#define MACH_TYPE_AT91SAM9260MEDTHS 4320 +#define MACH_TYPE_MATRIX516 4321 +#define MACH_TYPE_VID401X 4322 +#define MACH_TYPE_HELIOS_V5 4323 +#define MACH_TYPE_PLAYPAQ2 4324 +#define MACH_TYPE_IGAM 4325 +#define MACH_TYPE_AMICO_I 4326 +#define MACH_TYPE_AMICO_E 4327 +#define MACH_TYPE_SENTIENT_MM3_CK 4328 +#define MACH_TYPE_SMX6 4329 +#define MACH_TYPE_PANGO 4330 +#define MACH_TYPE_NS115_STICK 4331 +#define MACH_TYPE_BCTRM3 4332 +#define MACH_TYPE_DOCTORWS 4333 +#define MACH_TYPE_M2601 4334 +#define MACH_TYPE_GRIDCO_TRINITY 4335 +#define MACH_TYPE_PC3032 4336 +#define MACH_TYPE_VGG1111 4337 +#define MACH_TYPE_COUNTACH 4338 +#define MACH_TYPE_VISSTRIM_SM20 4339 +#define MACH_TYPE_A639 4340 +#define MACH_TYPE_SPACEMONKEY 4341 +#define MACH_TYPE_ZPDU_STAMP 4342 +#define MACH_TYPE_HTC_G7_CLONE 4343 +#define MACH_TYPE_FT2080_CORVUS 4344 +#define MACH_TYPE_FISLAND 4345 +#define MACH_TYPE_ZPDU 4346 +#define MACH_TYPE_URT 4347 +#define MACH_TYPE_CONTI_OVIP 4348 +#define MACH_TYPE_OMAPL138_NAGRA 4349 +#define MACH_TYPE_DA850_AT3KP1 4350 +#define MACH_TYPE_DA850_AT3KP2 4351 +#define MACH_TYPE_SURMA 4352 +#define MACH_TYPE_STM_B2092 4353 +#define MACH_TYPE_MX535_YCR 4354 +#define MACH_TYPE_M7_WL 4355 +#define MACH_TYPE_M7_U 4356 +#define MACH_TYPE_OMAP3_STNDT_EVM 4357 +#define MACH_TYPE_M7_WLV 4358 +#define MACH_TYPE_XAM3517 4359 +#define MACH_TYPE_A220 4360 +#define MACH_TYPE_ACLIMA_ODIE 4361 +#define MACH_TYPE_VIBBLE 4362 +#define MACH_TYPE_K2_U 4363 +#define MACH_TYPE_MX53_EGF 4364 +#define MACH_TYPE_NOVPEK_IMX53 4365 +#define MACH_TYPE_NOVPEK_IMX6X 4366 +#define MACH_TYPE_MX25_SMARTBOX 4367 +#define MACH_TYPE_EICG6410 4368 +#define MACH_TYPE_PICASSO_E3 4369 +#define MACH_TYPE_MOTONAVIGATOR 4370 +#define MACH_TYPE_VARIOCONNECT2 4371 +#define MACH_TYPE_DELUXE_TW 4372 +#define MACH_TYPE_KORE3 4374 +#define MACH_TYPE_MX6S_DRS 4375 +#define MACH_TYPE_CMIMX6 4376 +#define MACH_TYPE_ROTH 4377 +#define MACH_TYPE_EQ4UX 4378 +#define MACH_TYPE_X1PLUS 4379 +#define MACH_TYPE_MODIMX27 4380 +#define MACH_TYPE_VIDEON_HDUAC 4381 +#define MACH_TYPE_BLACKBIRD 4382 +#define MACH_TYPE_RUNMASTER 4383 +#define MACH_TYPE_CERES 4384 +#define MACH_TYPE_NAD435 4385 +#define MACH_TYPE_NS115_PROTO_TYPE 4386 +#define MACH_TYPE_FS20_VCC 4387 +#define MACH_TYPE_MESON6TV 4388 +#define MACH_TYPE_MESON6TV_SKT 4389 +#define MACH_TYPE_KEYSTONE 4390 +#define MACH_TYPE_PCM052 4391 +#define MACH_TYPE_TYPE 4392 +#define MACH_TYPE_QRD_SKUD_PRIME 4393 +#define MACH_TYPE_RAINBOWG15 4394 +#define MACH_TYPE_GUF_SANTARO 4395 +#define MACH_TYPE_SHEEPSHEAD 4396 +#define MACH_TYPE_MX6_IWG15M_MXM 4397 +#define MACH_TYPE_MX6_IWG15M_Q7 4398 +#define MACH_TYPE_AT91SAM9263IF8MIC 4399 +#define MACH_TYPE_EXCEL 4400 +#define MACH_TYPE_MARCOPOLO 4401 +#define MACH_TYPE_MX535_SDCR 4402 +#define MACH_TYPE_MX53_CSB2733 4403 +#define MACH_TYPE_DIVA 4404 +#define MACH_TYPE_NCR_7744 4405 +#define MACH_TYPE_MACALLAN 4406 +#define MACH_TYPE_WNR3500 4407 +#define MACH_TYPE_PGAVRF 4408 +#define MACH_TYPE_HELIOS_V6 4409 +#define MACH_TYPE_LCCT 4410 +#define MACH_TYPE_CSNDUG 4411 +#define MACH_TYPE_WANDBOARD_IMX6 4412 +#define MACH_TYPE_OMAP4_JET 4413 +#define MACH_TYPE_TEGRA_ROTH 4414 +#define MACH_TYPE_M7DCG 4415 +#define MACH_TYPE_M7DUG 4416 +#define MACH_TYPE_M7DTG 4417 +#define MACH_TYPE_AP42X 4418 +#define MACH_TYPE_VAR_SOM_MX6 4419 +#define MACH_TYPE_PDLU 4420 +#define MACH_TYPE_HYDROGEN 4421 +#define MACH_TYPE_NPA211E 4422 +#define MACH_TYPE_ARCADIA 4423 +#define MACH_TYPE_ARCADIA_L 4424 +#define MACH_TYPE_MSM8930DT 4425 +#define MACH_TYPE_KTAM3874 4426 +#define MACH_TYPE_CEC4 4427 +#define MACH_TYPE_APE6EVM 4428 +#define MACH_TYPE_TX6 4429 +#define MACH_TYPE_OWENSOM 4430 +#define MACH_TYPE_CFA10037 4431 +#define MACH_TYPE_NATEKS_VOIP 4432 +#define MACH_TYPE_EZP1000 4433 +#define MACH_TYPE_WGR826V 4434 +#define MACH_TYPE_EXUMA 4435 +#define MACH_TYPE_FREGATE 4436 +#define MACH_TYPE_OSIRISIMX508 4437 +#define MACH_TYPE_ST_EXIGO 4438 +#define MACH_TYPE_PISMO 4439 +#define MACH_TYPE_ATC7 4440 +#define MACH_TYPE_NSPIRECLP 4441 +#define MACH_TYPE_NSPIRETP 4442 +#define MACH_TYPE_NSPIRECX 4443 +#define MACH_TYPE_MAYA 4444 +#define MACH_TYPE_WECCT 4445 +#define MACH_TYPE_M2S 4446 +#define MACH_TYPE_MSM8625Q_EVBD 4447 +#define MACH_TYPE_TINY210 4448 +#define MACH_TYPE_G3 4449 +#define MACH_TYPE_HURRICANE 4450 +#define MACH_TYPE_MX6_POD 4451 +#define MACH_TYPE_ELONDCN 4452 +#define MACH_TYPE_CWMX535 4453 +#define MACH_TYPE_M7_WLJ 4454 +#define MACH_TYPE_QSP_ARM 4455 +#define MACH_TYPE_MSM8625Q_SKUD 4456 +#define MACH_TYPE_HTCMONDRIAN 4457 +#define MACH_TYPE_WATSON_EAD 4458 +#define MACH_TYPE_MITWOA 4459 +#define MACH_TYPE_OMAP3_WOLVERINE 4460 +#define MACH_TYPE_MAPLETREE 4461 +#define MACH_TYPE_MSM8625_FIH_SAE 4462 +#define MACH_TYPE_EPC35 4463 +#define MACH_TYPE_SMARTRTU 4464 +#define MACH_TYPE_RCM101 4465 +#define MACH_TYPE_AMX_IMX53_MXX 4466 +#define MACH_TYPE_CP3DCG 4467 +#define MACH_TYPE_CP3DTG 4468 +#define MACH_TYPE_CP3DUG 4469 +#define MACH_TYPE_ACER_A12 4470 +#define MACH_TYPE_SBC6X 4471 +#define MACH_TYPE_U2 4472 +#define MACH_TYPE_SMDK4270 4473 +#define MACH_TYPE_PRISCILLAG 4474 +#define MACH_TYPE_PRISCILLAC 4475 +#define MACH_TYPE_PRISCILLA 4476 +#define MACH_TYPE_INNOVA_SHPU_V2 4477 +#define MACH_TYPE_M7CDTU 4478 +#define MACH_TYPE_MACH_TYPE_DEP2410 4479 +#define MACH_TYPE_BCTRE3 4480 +#define MACH_TYPE_OMAP_M100 4481 +#define MACH_TYPE_FLO 4482 +#define MACH_TYPE_NANOBONE 4483 +#define MACH_TYPE_STM_B2105 4484 +#define MACH_TYPE_OMAP4_BSC_BAP_V3 4485 +#define MACH_TYPE_SS1PAM 4486 +#define MACH_TYPE_DLXP_WL 4487 +#define MACH_TYPE_PRIMOMINIU 4488 +#define MACH_TYPE_MRT_35HD_DUALNAS_E 4489 +#define MACH_TYPE_KIWI 4490 +#define MACH_TYPE_HW90496 4491 +#define MACH_TYPE_MEP2440 4492 +#define MACH_TYPE_COLIBRI_T30 4493 +#define MACH_TYPE_CWV1 4494 +#define MACH_TYPE_NSA325 4495 +#define MACH_TYPE_DLXP_UL 4496 +#define MACH_TYPE_DPXMTC 4497 +#define MACH_TYPE_TT_STUTTGART 4498 +#define MACH_TYPE_MIRANDA_APCII 4499 +#define MACH_TYPE_MX6Q_MODEROX 4500 +#define MACH_TYPE_MUDSKIPPER 4501 +#define MACH_TYPE_URANIA 4502 +#define MACH_TYPE_STM_B2112 4503 +#define MACH_TYPE_GTOU 4504 +#define MACH_TYPE_MX6Q_ATS_PHOENIX 4505 +#define MACH_TYPE_STM_B2116 4506 +#define MACH_TYPE_MYTHOLOGY 4507 +#define MACH_TYPE_FC360V1 4508 +#define MACH_TYPE_GPS_SENSOR 4509 +#define MACH_TYPE_GAZELLE 4510 +#define MACH_TYPE_MPQ8064_DMA 4511 +#define MACH_TYPE_WEMS_ASD01 4512 +#define MACH_TYPE_APALIS_T30 4513 +#define MACH_TYPE_MX6Q_QSBC35_C398 4514 +#define MACH_TYPE_ARMSTONEA9 4515 +#define MACH_TYPE_OMAP_BLAZETABLET 4516 +#define MACH_TYPE_AR6MXQ 4517 +#define MACH_TYPE_AR6MXS 4518 +#define MACH_TYPE_DETO_APOS_MX6 4519 +#define MACH_TYPE_GWVENTANA 4520 +#define MACH_TYPE_IGEP0033 4521 +#define MACH_TYPE_RACA 4522 +#define MACH_TYPE_APPLESODA 4523 +#define MACH_TYPE_H52C1_CONCERTO 4524 +#define MACH_TYPE_FCMBRD 4525 +#define MACH_TYPE_PCAAXS1 4526 +#define MACH_TYPE_LS_ORCA 4527 +#define MACH_TYPE_PCM051LB 4528 +#define MACH_TYPE_MX6S_LP507_GVCI 4529 +#define MACH_TYPE_DIDO 4530 +#define MACH_TYPE_SWARCO_ITC3_9G20 4531 +#define MACH_TYPE_ROBO_ROADY 4532 +#define MACH_TYPE_RSKRZA1 4533 +#define MACH_TYPE_SWARCO_SID 4534 +#define MACH_TYPE_MX6_IWG15S_SBC 4535 +#define MACH_TYPE_MX6Q_CAMARO 4536 +#define MACH_TYPE_HB6MXS 4537 +#define MACH_TYPE_LAGER 4538 +#define MACH_TYPE_LP8X4X 4539 +#define MACH_TYPE_TEGRATAB7 4540 +#define MACH_TYPE_ANDROMEDA 4541 +#define MACH_TYPE_BOOTES 4542 +#define MACH_TYPE_NETHMI 4543 +#define MACH_TYPE_TEGRATAB 4544 +#define MACH_TYPE_SOM5_EVB 4545 +#define MACH_TYPE_VENATICORUM 4546 +#define MACH_TYPE_STM_B2110 4547 +#define MACH_TYPE_ELUX_HATHOR 4548 +#define MACH_TYPE_HELIOS_V7 4549 +#define MACH_TYPE_XC10V1 4550 +#define MACH_TYPE_CP2U 4551 +#define MACH_TYPE_IAP_F 4552 +#define MACH_TYPE_IAP_G 4553 +#define MACH_TYPE_AAE 4554 +#define MACH_TYPE_PEGASUS 4555 +#define MACH_TYPE_CYGNUS 4556 +#define MACH_TYPE_CENTAURUS 4557 +#define MACH_TYPE_MSM8930_QRD8930 4558 +#define MACH_TYPE_QUBY_TIM 4559 +#define MACH_TYPE_ZEDI3250A 4560 +#define MACH_TYPE_GRUS 4561 +#define MACH_TYPE_APOLLO3 4562 +#define MACH_TYPE_COWON_R7 4563 +#define MACH_TYPE_TONGA3 4564 +#define MACH_TYPE_P535 4565 +#define MACH_TYPE_SA3874I 4566 +#define MACH_TYPE_MX6_NAVICO_COM 4567 +#define MACH_TYPE_PROXMOBIL2 4568 +#define MACH_TYPE_UBINUX1 4569 +#define MACH_TYPE_ISTOS 4570 +#define MACH_TYPE_BENVOLIO4 4571 +#define MACH_TYPE_ECO5_BX2 4572 +#define MACH_TYPE_EUKREA_CPUIMX28SD 4573 +#define MACH_TYPE_DOMOTAB 4574 +#define MACH_TYPE_PFLA03 4575 +#define MACH_TYPE_ET_CPU_301_16 4576 +#define MACH_TYPE_SKYWALKER 4577 +#define MACH_TYPE_SCORPIUS 4578 +#define MACH_TYPE_CAPRICORNUS 4579 +#define MACH_TYPE_LYRA 4580 +#define MACH_TYPE_GATERO 4581 +#define MACH_TYPE_GATERO01 4582 +#define MACH_TYPE_Z4DTG 4583 +#define MACH_TYPE_LUPUS 4584 +#define MACH_TYPE_LEAP101 4585 +#define MACH_TYPE_CM_T335 4586 +#define MACH_TYPE_PNA 4587 +#define MACH_TYPE_ECOFOREST_CPU2013 4588 +#define MACH_TYPE_APQ8064_DMA 4589 +#define MACH_TYPE_MX53_ARMOUR 4590 +#define MACH_TYPE_EUROFUNK_AEPL3 4591 +#define MACH_TYPE_EUROFUNK_MHLS3 4592 +#define MACH_TYPE_EUROFUNK_E1IF 4593 +#define MACH_TYPE_LEPUS 4594 +#define MACH_TYPE_BORA 4595 +#define MACH_TYPE_ADS4011 4596 +#define MACH_TYPE_BEAVER 4597 +#define MACH_TYPE_IMX233_IUNGO 4598 +#define MACH_TYPE_CEPHEUS 4599 +#define MACH_TYPE_CETUS 4600 +#define MACH_TYPE_CHAMAELEON 4601 +#define MACH_TYPE_ARDBEG 4602 +#define MACH_TYPE_IXORA 4603 +#define MACH_TYPE_JUGLANS 4604 +#define MACH_TYPE_CANISMAJOR 4605 +#define MACH_TYPE_AT91SAM9263MIB 4606 +#define MACH_TYPE_COSINO_9G35 4607 +#define MACH_TYPE_TINY4412 4608 +#define MACH_TYPE_BALLOON4 4609 +#define MACH_TYPE_PGG 4610 +#define MACH_TYPE_XXSQ701 4611 +#define MACH_TYPE_MX6_NAVICO_RDR 4612 +#define MACH_TYPE_PHANTOM 4613 +#define MACH_TYPE_CANISMINORH 4614 +#define MACH_TYPE_CARINA 4615 +#define MACH_TYPE_E1859 4616 +#define MACH_TYPE_ARMSTONEA5 4617 +#define MACH_TYPE_PICOCOMA5 4618 +#define MACH_TYPE_NETDCUA5 4619 +#define MACH_TYPE_MOLLY 4620 +#define MACH_TYPE_MASERATI 4621 +#define MACH_TYPE_MX53_IDEBX 4622 +#define MACH_TYPE_MX53_C2CB 4623 +#define MACH_TYPE_MIPSEE 4624 +#define MACH_TYPE_SEEKLOP 4625 +#define MACH_TYPE_AUDISEE 4626 +#define MACH_TYPE_TX48 4627 +#define MACH_TYPE_TL7689_PAD_REF 4628 +#define MACH_TYPE_TL7689_PAD_TEST 4629 +#define MACH_TYPE_TL7689_PHONE_REF 4630 +#define MACH_TYPE_TL7689_PHONE_TEST 4631 +#define MACH_TYPE_SWARCO_SCC_WKS 4632 +#define MACH_TYPE_ACCORDO2 4633 +#define MACH_TYPE_TRIZEPS7 4634 +#define MACH_TYPE_F100 4635 +#define MACH_TYPE_ARMADILLO410 4636 +#define MACH_TYPE_TINY2416 4637 +#define MACH_TYPE_TINY2451 4638 +#define MACH_TYPE_MINI2451 4639 +#define MACH_TYPE_TINY5250 4640 +#define MACH_TYPE_TINY3358 4641 +#define MACH_TYPE_T6_UL 4642 +#define MACH_TYPE_T6_U 4643 +#define MACH_TYPE_T6_ULA 4644 +#define MACH_TYPE_T6_WL 4645 +#define MACH_TYPE_T6_WHL 4646 +#define MACH_TYPE_CIRCINUS 4647 +#define MACH_TYPE_SOCPK255 4648 +#define MACH_TYPE_SOCPRV270 4649 +#define MACH_TYPE_SOCPRC270 4650 +#define MACH_TYPE_MACH_CP5DTU 4651 +#define MACH_TYPE_CP5DTU 4652 +#define MACH_TYPE_CP5DUG 4653 +#define MACH_TYPE_CP5DWG 4654 +#define MACH_TYPE_AM335X_EGF 4655 +#define MACH_TYPE_AZM9G45 4656 +#define MACH_TYPE_AZM335X 4657 +#define MACH_TYPE_LYNBRD 4658 +#define MACH_TYPE_AM35X_EGF 4659 +#define MACH_TYPE_SEVULCAN 4660 +#define MACH_TYPE_AX8008M 4661 +#define MACH_TYPE_AX8008MR 4662 +#define MACH_TYPE_XYNIX 4663 +#define MACH_TYPE_OMAP3621_ODYV4 4664 +#define MACH_TYPE_MX6_CAMERONET 4665 +#define MACH_TYPE_OMAP4_DART 4666 +#define MACH_TYPE_MX6Q_ENZO 4667 +#define MACH_TYPE_EV_IMX287MICRO 4668 +#define MACH_TYPE_EV_IMX287MINI 4669 +#define MACH_TYPE_MX53_CEC2 4670 +#define MACH_TYPE_HELIOS_V8 4671 +#define MACH_TYPE_HELIOS_V9 4672 +#define MACH_TYPE_COGNAC 4673 +#define MACH_TYPE_ZEST 4674 +#define MACH_TYPE_GC3 4675 +#define MACH_TYPE_DAD_MEDIA 4676 +#define MACH_TYPE_HTOUCH 4677 +#define MACH_TYPE_SPT7500BASEBOARD 4678 +#define MACH_TYPE_OMAP4_DART_EVM 4679 +#define MACH_TYPE_MX53_TLV 4680 +#define MACH_TYPE_PDAK2H 4681 +#define MACH_TYPE_MATRIX513 4682 +#define MACH_TYPE_LIVEBOX01 4683 +#define MACH_TYPE_CEVRZA1L 4684 +#define MACH_TYPE_B1010 4685 +#define MACH_TYPE_FWTMK1 4686 +#define MACH_TYPE_GRENADA 4687 +#define MACH_TYPE_HASSEL 4688 +#define MACH_TYPE_ODROIDXU 4689 +#define MACH_TYPE_ODROIDU2 4690 +#define MACH_TYPE_NAIAD 4691 +#define MACH_TYPE_HARRIER 4692 +#define MACH_TYPE_PCL052 4693 +#define MACH_TYPE_LIBRA2404 4694 +#define MACH_TYPE_MX6_LEMONBOARD 4695 +#define MACH_TYPE_MX6_ATLAS 4696 +#define MACH_TYPE_ELECSYS_Z2 4697 +#define MACH_TYPE_ELECSYS_Z4 4698 +#define MACH_TYPE_IPQ806X_DB149 4699 +#define MACH_TYPE_PULSAR 4700 +#define MACH_TYPE_SCALANCEM 4701 +#define MACH_TYPE_NA11 4702 +#define MACH_TYPE_IPQ806X_DB147 4703 +#define MACH_TYPE_IPQ806X_AP148 4704 +#define MACH_TYPE_AMLTD_IMX6 4705 +#define MACH_TYPE_PIA_AM335X 4706 +#define MACH_TYPE_BLADE 4707 +#define MACH_TYPE_MATISSE 4708 +#define MACH_TYPE_IKEBANA 4709 +#define MACH_TYPE_LF3000 4710 +#define MACH_TYPE_CARALLON_STINGRAY 4711 +#define MACH_TYPE_MENSA 4712 +#define MACH_TYPE_CES_COREBOARD 4713 +#define MACH_TYPE_VYBRID_IWG16M_UMXM 4714 +#define MACH_TYPE_LOKI 4715 +#define MACH_TYPE_PCM053 4716 +#define MACH_TYPE_SMM200 4717 +#define MACH_TYPE_M507 4718 +#define MACH_TYPE_ORSOC_ARMSOC_8695 4719 +#define MACH_TYPE_AM335X_ZY 4720 +#define MACH_TYPE_ARRAKIS 4721 +#define MACH_TYPE_SXLT 4722 +#define MACH_TYPE_YLCM 4723 +#define MACH_TYPE_EAGLE6D 4724 +#define MACH_TYPE_LCU1 4725 +#define MACH_TYPE_MX6DL_IWG15M_Q7 4726 +#define MACH_TYPE_SBCPHYFLEXAM335 4727 +#define MACH_TYPE_SBCPHYCARDAM335 4728 +#define MACH_TYPE_SBCPHYFLEXIMX6 4729 +#define MACH_TYPE_HOMESERVERSTICK 4730 +#define MACH_TYPE_ECXEC 4731 +#define MACH_TYPE_HH300 4732 +#define MACH_TYPE_CPUCA8 4733 +#define MACH_TYPE_A0057_LSEMBEDDEDPC 4734 +#define MACH_TYPE_IPROC 4735 +#define MACH_TYPE_NEMESIS_NFE 4736 +#define MACH_TYPE_MABV3X25 4737 +#define MACH_TYPE_OCTANT 4738 +#define MACH_TYPE_MSM7X27_THUNDER 4739 +#define MACH_TYPE_MAXIM 4740 +#define MACH_TYPE_TELEMATICCTRLUNIT 4741 +#define MACH_TYPE_MX6Q_JCDBOX 4742 +#define MACH_TYPE_CKB_1808 4743 +#define MACH_TYPE_CKB_3352 4744 +#define MACH_TYPE_HIKIRK 4745 +#define MACH_TYPE_DNS320L 4746 +#define MACH_TYPE_STM_B2120 4747 +#define MACH_TYPE_STM_B2089 4748 +#define MACH_TYPE_COLIBRI_VF50 4749 +#define MACH_TYPE_COLIBRI_VF61 4750 +#define MACH_TYPE_SYNERGY2 4751 +#define MACH_TYPE_PCM051_HMI 4752 +#define MACH_TYPE_TEK2 4753 +#define MACH_TYPE_DUCKBILL 4754 +#define MACH_TYPE_MX50_SEISMIC 4755 +#define MACH_TYPE_TWOFACE 4756 +#define MACH_TYPE_T10 4757 +#define MACH_TYPE_LIB1313 4758 +#define MACH_TYPE_HIMX 4759 +#define MACH_TYPE_VCM30_T30 4760 +#define MACH_TYPE_CORNERVIEW 4761 +#define MACH_TYPE_P01600 4762 +#define MACH_TYPE_AXEL 4763 +#define MACH_TYPE_IMX6_ANDY 4764 +#define MACH_TYPE_NSA220 4765 +#define MACH_TYPE_TI8168HSC1 4766 +#define MACH_TYPE_DORY 4767 +#define MACH_TYPE_ECV4 4768 +#define MACH_TYPE_WEBBG3FLIGHT 4769 +#define MACH_TYPE_SBC_PHYCORE_AM335X 4770 +#define MACH_TYPE_TSC 4771 +#define MACH_TYPE_IMX6_CLOUS 4772 +#define MACH_TYPE_C1 4773 +#define MACH_TYPE_VCM30T30 4774 +#define MACH_TYPE_IMX6_EMSYM_BLURR 4775 +#define MACH_TYPE_PDIS_M 4776 +#define MACH_TYPE_MX6Q_REX 4777 +#define MACH_TYPE_SWARCO_FR_ANYBUS 4778 +#define MACH_TYPE_SHMAC 4779 +#define MACH_TYPE_CKB_RZA1H 4780 +#define MACH_TYPE_AZETI_SP_NG01 4781 +#define MACH_TYPE_E6210 4782 +#define MACH_TYPE_MH9001 4783 +#define MACH_TYPE_STM_B2147 4784 +#define MACH_TYPE_OMAP5_VARSOM 4785 +#define MACH_TYPE_CUBEA5 4786 +#define MACH_TYPE_CP5 4787 +#define MACH_TYPE_FORNAX 4788 +#define MACH_TYPE_ICU 4789 +#define MACH_TYPE_COMUS3 4790 +#define MACH_TYPE_LIBRA4344 4791 +#define MACH_TYPE_LIBRA4644 4792 +#define MACH_TYPE_PAVO 4793 +#define MACH_TYPE_XL824 4794 +#define MACH_TYPE_XL850 4795 +#define MACH_TYPE_MX6_PICO_ITX 4796 +#define MACH_TYPE_AMICO_S 4797 +#define MACH_TYPE_AMICO_P 4798 +#define MACH_TYPE_MINNOW 4799 +#define MACH_TYPE_DAVINCI_DM365_ZY 4800 +#define MACH_TYPE_PAVO_2 4801 +#define MACH_TYPE_IAVS 4802 +#define MACH_TYPE_RANA 4803 +#define MACH_TYPE_MERAKI_MS26 4804 +#define MACH_TYPE_VP2_REFRESH 4805 +#define MACH_TYPE_MCB1800 4806 +#define MACH_TYPE_MX6Q_DEVONIT_TC3 4807 +#define MACH_TYPE_UC81XX 4808 +#define MACH_TYPE_UC84XX 4809 +#define MACH_TYPE_IPQ806X_AP145 4810 +#define MACH_TYPE_IPQ806X_DB149_MMC 4811 +#define MACH_TYPE_IPQ806X_AP145_MMC 4812 +#define MACH_TYPE_E3QT 4813 +#define MACH_TYPE_U222 4814 +#define MACH_TYPE_UFO878 4815 +#define MACH_TYPE_GEKKO 4816 +#define MACH_TYPE_MINI2440ARM 4817 +#define MACH_TYPE_MPCSB2_9G20 4818 +#define MACH_TYPE_TL7689_PAD_706 4819 +#define MACH_TYPE_TDA7 4820 +#define MACH_TYPE_CUBOXI 4821 +#define MACH_TYPE_TIBIDABO 4822 +#define MACH_TYPE_T216MINI 4823 +#define MACH_TYPE_HERA_IMX6 4824 +#define MACH_TYPE_GRIDPOINT_EC1K 4825 +#define MACH_TYPE_LIBRA4404 4826 +#define MACH_TYPE_MI_MOCHA 4827 +#define MACH_TYPE_BCM2835 4828 +#define MACH_TYPE_NFP6XXX 4829 +#define MACH_TYPE_TETRA 4830 +#define MACH_TYPE_NECO 4831 +#define MACH_TYPE_PROTONEX_VPM402 4832 +#define MACH_TYPE_MX6Q_SAVAGE 4833 +#define MACH_TYPE_MX6Q_SOMB 4834 +#define MACH_TYPE_FILI_DL 4835 +#define MACH_TYPE_ADAPT_SDRDC 4836 +#define MACH_TYPE_DS_QUARTZ 4837 +#define MACH_TYPE_ULTRAFLEX 4838 +#define MACH_TYPE_APQ8064_ADP_2 4839 +#define MACH_TYPE_BEAN 4840 +#define MACH_TYPE_BALDR 4841 +#define MACH_TYPE_CCIMX6ADPT 4842 +#define MACH_TYPE_TS4900 4843 +#define MACH_TYPE_ZEPLUG 4844 +#define MACH_TYPE_MSM8X60_DUPLICITY 4845 +#define MACH_TYPE_CTERA_2BAY_A 4846 +#define MACH_TYPE_AM335X_BAP_V3_1 4847 +#define MACH_TYPE_XPECT01 4848 +#define MACH_TYPE_ESI23 4849 +#define MACH_TYPE_MX6DL_SBC35_C398 4850 +#define MACH_TYPE_MX6SOLO_SBC35_C398 4851 +#define MACH_TYPE_KSP5012 4852 +#define MACH_TYPE_MX6Q_ZEUS 4853 +#define MACH_TYPE_INNOVA_MATRIX 4854 +#define MACH_TYPE_RF6XXR 4855 +#define MACH_TYPE_PECORINO 4856 +#define MACH_TYPE_MHPLAY_W 4857 +#define MACH_TYPE_PELCO_DRAGONFLY 4858 +#define MACH_TYPE_VSM_CHAMHIGH 4859 +#define MACH_TYPE_HACHIKO 4860 +#define MACH_TYPE_TL7689_PHONE_IN260 4861 +#define MACH_TYPE_CWMX6 4862 +#define MACH_TYPE_HD3 4863 +#define MACH_TYPE_UHD4 4864 +#define MACH_TYPE_BULPRINT_BOARD 4865 +#define MACH_TYPE_PELCO_SPECTRAHD2 4866 +#define MACH_TYPE_VISTEONV2X 4867 +#define MACH_TYPE_PHIDGET_VINTSBC 4868 +#define MACH_TYPE_LMU7030 4869 +#define MACH_TYPE_ECC2 4870 +#define MACH_TYPE_CDS_CTS 4871 +#define MACH_TYPE_AXELLITE 4872 +#define MACH_TYPE_ARNIE 4873 +#define MACH_TYPE_AGATEWAY 4874 +#define MACH_TYPE_PICOMODA9 4875 +#define MACH_TYPE_P_137_I6 4876 +#define MACH_TYPE_VVDN_MCAM 4877 +#define MACH_TYPE_MX6_INSIGHT 4878 +#define MACH_TYPE_VIPRINET_200 4879 +#define MACH_TYPE_ELLYPTO 4880 +#define MACH_TYPE_G7P 4881 +#define MACH_TYPE_YSE5250 4882 +#define MACH_TYPE_NG500 4883 +#define MACH_TYPE_DTSC02 4884 +#define MACH_TYPE_MX6DL_SBB 4885 +#define MACH_TYPE_APALIS_IMX6Q 4886 +#define MACH_TYPE_WOMBAT6 4887 +#define MACH_TYPE_BALTO 4888 +#define MACH_TYPE_TNGSBL 4889 +#define MACH_TYPE_H6061 4890 +#define MACH_TYPE_XA300 4891 +#define MACH_TYPE_PELCO_WOOFF 4892 +#define MACH_TYPE_PELCO_EVM 4893 +#define MACH_TYPE_MX6Q_IMXB 4894 +#define MACH_TYPE_SMARTTAB_V55 4895 +#define MACH_TYPE_SMARTTAB_V11A 4896 +#define MACH_TYPE_SMARTTAB_V71A 4897 +#define MACH_TYPE_NOVASOM5 4898 +#define MACH_TYPE_CCIMX6SBC 4899 +#define MACH_TYPE_INTOUCH 4900 +#define MACH_TYPE_MX6S_HAWTHORNE 4901 +#define MACH_TYPE_SEAH 4902 +#define MACH_TYPE_AM335X_EC3 4903 +#define MACH_TYPE_EMBEST_MARS 4904 +#define MACH_TYPE_MX6DL_VIKITOUCH 4905 +#define MACH_TYPE_IX2_NG 4906 +#define MACH_TYPE_PEKQSD 4907 +#define MACH_TYPE_PTEKN 4908 +#define MACH_TYPE_APQ8064_ADP2_ES2 4909 +#define MACH_TYPE_GHIIMX6 4910 +#define MACH_TYPE_M3000 4911 +#define MACH_TYPE_TCW101 4912 +#define MACH_TYPE_IPQ806X_AP148_1XX 4913 +#define MACH_TYPE_HNS_ACADIA 4914 +#define MACH_TYPE_MX6S_VIKITOUCH 4915 +#define MACH_TYPE_CM_QS600 4916 +#define MACH_TYPE_IPQ806X_DB149_2XX 4917 +#define MACH_TYPE_EAG_UGW400 4918 +#define MACH_TYPE_SK_GRANT_OEM 4919 +#define MACH_TYPE_KNOBLOCH_TXT 4920 +#define MACH_TYPE_MX6SL_SHD 4921 +#define MACH_TYPE_HIMX0294 4922 +#define MACH_TYPE_MX6Q_TTJ500 4923 +#define MACH_TYPE_CONTI_SGM358 4924 +#define MACH_TYPE_DENSOJ6REF 4925 +#define MACH_TYPE_KEVIN 4926 +#define MACH_TYPE_VVDN_TOII 4927 +#define MACH_TYPE_PENGWYN 4928 +#define MACH_TYPE_XARINA_ENTRY 4929 +#define MACH_TYPE_CONTI_MRNEVO 4930 +#define MACH_TYPE_NSA310S 4931 +#define MACH_TYPE_POWERECU 4932 +#define MACH_TYPE_Q7M120 4933 +#define MACH_TYPE_H6829 4934 +#define MACH_TYPE_AG13008 4935 +#define MACH_TYPE_IPQ806X_STORM 4936 +#define MACH_TYPE_DM3725_GSOM 4937 +#define MACH_TYPE_HP_PRIME 4938 +#define MACH_TYPE_FIRESTORM 4939 +#define MACH_TYPE_WINGZ 4940 +#define MACH_TYPE_ANDROMED 4941 +#define MACH_TYPE_SCM120 4942 +#define MACH_TYPE_CM_3G 4943 +#define MACH_TYPE_IPA400 4944 +#define MACH_TYPE_HYDRA_MKII 4945 +#define MACH_TYPE_AXM2 4946 +#define MACH_TYPE_CALOPUS 4947 +#define MACH_TYPE_BCTRM3S 4948 +#define MACH_TYPE_DM385LB 4949 +#define MACH_TYPE_SURMA_MKII 4950 +#define MACH_TYPE_OMAP4_SKHU_HCAM 4951 +#define MACH_TYPE_SCMCON 4952 +#define MACH_TYPE_KLK_IMX6S_G 4953 +#define MACH_TYPE_AM335XMX 4954 +#define MACH_TYPE_DMVA2_BTFU_WCAM 4955 +#define MACH_TYPE_UXC 4956 +#define MACH_TYPE_ELARM_A 4957 +#define MACH_TYPE_EMPC_AIMX6 4958 +#define MACH_TYPE_BCTRE2G2 4959 +#define MACH_TYPE_DMD 4960 +#define MACH_TYPE_DISCOVERY 4961 +#define MACH_TYPE_RELIAGATE_10_20 4962 +#define MACH_TYPE_MX6Q_DSA2LS 4963 +#define MACH_TYPE_MX6SL_ECT5 4964 +#define MACH_TYPE_COBHAM_MDC3 4965 +#define MACH_TYPE_TS_WAV 4966 +#define MACH_TYPE_XIN_GIGE_CAM 4967 +#define MACH_TYPE_ASAIIOTG 4968 +#define MACH_TYPE_DAU 4969 +#define MACH_TYPE_SOCFPGA_ARRIA5 4970 +#define MACH_TYPE_IPQ806X_AP160 4971 +#define MACH_TYPE_IPQ806X_AP161 4972 +#define MACH_TYPE_GEMX6 4973 +#define MACH_TYPE_EFUSA9 4974 +#define MACH_TYPE_DYNACOR_10_20 4975 +#define MACH_TYPE_BLUELIGHTNING 4976 +#define MACH_TYPE_SILVERBULLET 4977 +#define MACH_TYPE_MX6_MAEXLE 4978 +#define MACH_TYPE_PAYTEC_EPT 4979 +#define MACH_TYPE_ATLASCOPCO_ITMK2 4980 +#define MACH_TYPE_ATLASCOPCO_FLEXDRV 4981 +#define MACH_TYPE_ATLASCOPCO_FLEXIT 4982 +#define MACH_TYPE_PCDON 4983 +#define MACH_TYPE_DM8168_IWG12M_Q7 4984 +#define MACH_TYPE_RTM9431 4985 +#define MACH_TYPE_ARM11_CAR 4986 +#define MACH_TYPE_VIDEOPHONE 4987 +#define MACH_TYPE_MPFA 4988 +#define MACH_TYPE_PS10 4989 +#define MACH_TYPE_HGATEWAY 4990 +#define MACH_TYPE_IPQ806X_AP160_2 4991 +#define MACH_TYPE_ECP5COM 4992 +#define MACH_TYPE_H6064 4993 +#define MACH_TYPE_MX6X_MX 4994 +#define MACH_TYPE_MAJIC5422 4995 +#define MACH_TYPE_EMINDS 4996 +#define MACH_TYPE_TI8168TOII 4997 +#define MACH_TYPE_VXR10 4998 +#define MACH_TYPE_DS5 4999 +#define MACH_TYPE_DS3 5000 +#define MACH_TYPE_NOKIAN97 5001 +#define MACH_TYPE_TECNINT_ODBC 5002 +#define MACH_TYPE_C111 5003 +#define MACH_TYPE_ML300DU 5004 +#define MACH_TYPE_YAK 5005 +#define MACH_TYPE_NSA221 5006 +#define MACH_TYPE_GINKGOP 5007 +#define MACH_TYPE_MANGO 5008 +#define MACH_TYPE_AMBS2E 5009 +#define MACH_TYPE_AMBS3L 5010 +#define MACH_TYPE_DRA7XX_EVM 5011 +#define MACH_TYPE_DENSODRA74XMID 5012 +#define MACH_TYPE_MILD 5013 +#define MACH_TYPE_YLCM_MK2 5014 +#define MACH_TYPE_DS_CB 5015 +#define MACH_TYPE_EMPEROR 5016 +#define MACH_TYPE_ARTPEC 5017 +#define MACH_TYPE_DCIM 5018 +#define MACH_TYPE_WS1XX 5019 +#define MACH_TYPE_IPQ806X_AK01_1XX 5020 +#define MACH_TYPE_MGWACE_DEC 5021 +#define MACH_TYPE_W6000 5022 +#define MACH_TYPE_WATSON_FIB_PLUGIN 5023 +#define MACH_TYPE_MX6Q_TINYREX 5024 +#define MACH_TYPE_MX6S_TINYREX 5025 +#define MACH_TYPE_MX6Q_MODEROS 5026 +#define MACH_TYPE_AFI 5027 +#define MACH_TYPE_RCPRO 5028 +#define MACH_TYPE_ONBOX 5029 +#define MACH_TYPE_EXYNOS4412 5030 +#define MACH_TYPE_EXYNOS4413 5031 +#define MACH_TYPE_PELCO_DF20_EVT 5032 +#define MACH_TYPE_LION_DUG 5033 +#define MACH_TYPE_LIONP_DUG 5034 +#define MACH_TYPE_ESSE 5035 +#define MACH_TYPE_ILLINOIS 5036 +#define MACH_TYPE_TI8168KSIPOLARIS 5037 +#define MACH_TYPE_YSE_BOARD 5038 +#define MACH_TYPE_PELCO_HWE0_EVT 5039 +#define MACH_TYPE_PELCO_S2E_EVM 5040 +#define MACH_TYPE_PELCO_DRAGONFLY20 5041 +#define MACH_TYPE_PELCO_HAWKEYE 5042 +#define MACH_TYPE_ARM 5043 +#define MACH_TYPE_TCAM 5044 +#define MACH_TYPE_MX6Q_HOBBY 5045 +#define MACH_TYPE_H6067 5046 +#define MACH_TYPE_DENSODRA72XLOW 5047 +#define MACH_TYPE_MX6_UNETBIT 5048 +#define MACH_TYPE_BT_OAK 5049 +#define MACH_TYPE_BT500 5050 +#define MACH_TYPE_FARWATER_GEO 5051 +#define MACH_TYPE_YT2 5052 +#define MACH_TYPE_EH9000 5053 +#define MACH_TYPE_GVPU 5054 +#define MACH_TYPE_CEDEX 5055 +#define MACH_TYPE_NT450R5G 5056 +#define MACH_TYPE_MSA23XX 5057 +#define MACH_TYPE_OMAP3_MOSS 5058 +#define MACH_TYPE_KYEONGHAWOO 5059 +#define MACH_TYPE_GIRA_IM03 5060 +#define MACH_TYPE_EUROFUNK_AIIF 5061 +#define MACH_TYPE_BCU1 5062 +#define MACH_TYPE_DIYEFIS6410 5063 +#define MACH_TYPE_MX53_TURING 5064 +#define MACH_TYPE_MX6X_TURING 5065 +#define MACH_TYPE_MX6DL_TURING 5066 +#define MACH_TYPE_MX53_INDASH 5067 +#define MACH_TYPE_MX6Q_INDASH 5068 +#define MACH_TYPE_MX6DL_INDASH 5069 +#define MACH_TYPE_RTS_G6 5070 +#define MACH_TYPE_KA_TITAN 5071 +#define MACH_TYPE_CL_SOM_IMX7 5072 +#define MACH_TYPE_VVDN_MGSI_VSIS 5073 +#define MACH_TYPE_MX6Q_NANO 5074 +#define MACH_TYPE_PDU001 5075 +#define MACH_TYPE_CAB_PROYK 5076 +#define MACH_TYPE_KLIN 5077 +#define MACH_TYPE_ENMAN_STEUERBOX 5078 +#define MACH_TYPE_LS_STINGRAY 5079 +#define MACH_TYPE_IPDU 5080 +#define MACH_TYPE_LINDA 5081 +#define MACH_TYPE_MX6Q_OPENREX 5082 +#define MACH_TYPE_ON100 5083 +#define MACH_TYPE_EMINDS_RTU12 5084 +#define MACH_TYPE_EMINDS_AVL10 5085 +#define MACH_TYPE_MAIN_PLC_LME 5086 +#define MACH_TYPE_MSPX 5087 +#define MACH_TYPE_CGW_300 5088 +#define MACH_TYPE_MX7D_CICADA 5089 +#define MACH_TYPE_VIRT2REAL_DM365 5090 +#define MACH_TYPE_DM365_VIRT2REAL 5091 +#define MACH_TYPE_H6073 5092 +#define MACH_TYPE_GTGATEWAY 5093 +#define MACH_TYPE_XARINA_STANDARD 5094 +#define MACH_TYPE_NOVASOMS 5095 +#define MACH_TYPE_NOVASOMP 5096 +#define MACH_TYPE_NOVASOMU 5097 +#define MACH_TYPE_MX6Q_MPBD 5098 +#define MACH_TYPE_NCR_1930 5099 +#define MACH_TYPE_UAP301 5100 +#define MACH_TYPE_URT02 5101 +#define MACH_TYPE_ATC8 5102 +#define MACH_TYPE_IOT_GATEWAY 5103 +#define MACH_TYPE_HSM_PHOENIX 5104 +#define MACH_TYPE_MISSOURI 5105 +#define MACH_TYPE_REMARKABLE 5106 +#define MACH_TYPE_FA0113 5107 +#define MACH_TYPE_INNOVA_STATNETTAWM 5108 +#define MACH_TYPE_TEGRA3 5109 +#define MACH_TYPE_MALI400 5110 +#define MACH_TYPE_MALI450 5111 +#define MACH_TYPE_NASM25 5112 +#define MACH_TYPE_TOMATO 5113 +#define MACH_TYPE_OMAP3_MRC3D 5114 +#endif diff --git a/roms/u-boot/arch/arm/include/asm/macro.h b/roms/u-boot/arch/arm/include/asm/macro.h new file mode 100644 index 000000000..bb33b4bc8 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/macro.h @@ -0,0 +1,337 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/asm-arm/macro.h + * + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD + */ + +#ifndef __ASM_ARM_MACRO_H__ +#define __ASM_ARM_MACRO_H__ + +#ifdef CONFIG_ARM64 +#include +#endif + +#ifdef __ASSEMBLY__ + +/* + * These macros provide a convenient way to write 8, 16 and 32 bit data + * to any address. + * Registers r4 and r5 are used, any data in these registers are + * overwritten by the macros. + * The macros are valid for any ARM architecture, they do not implement + * any memory barriers so caution is recommended when using these when the + * caches are enabled or on a multi-core system. + */ + +.macro write32, addr, data + ldr r4, =\addr + ldr r5, =\data + str r5, [r4] +.endm + +.macro write16, addr, data + ldr r4, =\addr + ldrh r5, =\data + strh r5, [r4] +.endm + +.macro write8, addr, data + ldr r4, =\addr + ldrb r5, =\data + strb r5, [r4] +.endm + +/* + * This macro generates a loop that can be used for delays in the code. + * Register r4 is used, any data in this register is overwritten by the + * macro. + * The macro is valid for any ARM architeture. The actual time spent in the + * loop will vary from CPU to CPU though. + */ + +.macro wait_timer, time + ldr r4, =\time +1: + nop + subs r4, r4, #1 + bcs 1b +.endm + +#ifdef CONFIG_ARM64 +/* + * Register aliases. + */ +lr .req x30 + +/* + * Branch according to exception level + */ +.macro switch_el, xreg, el3_label, el2_label, el1_label + mrs \xreg, CurrentEL + cmp \xreg, 0xc + b.eq \el3_label + cmp \xreg, 0x8 + b.eq \el2_label + cmp \xreg, 0x4 + b.eq \el1_label +.endm + +/* + * Branch if current processor is a Cortex-A57 core. + */ +.macro branch_if_a57_core, xreg, a57_label + mrs \xreg, midr_el1 + lsr \xreg, \xreg, #4 + and \xreg, \xreg, #0x00000FFF + cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */ + b.eq \a57_label +.endm + +/* + * Branch if current processor is a Cortex-A53 core. + */ +.macro branch_if_a53_core, xreg, a53_label + mrs \xreg, midr_el1 + lsr \xreg, \xreg, #4 + and \xreg, \xreg, #0x00000FFF + cmp \xreg, #0xD03 /* Cortex-A53 MPCore processor. */ + b.eq \a53_label +.endm + +/* + * Branch if current processor is a slave, + * choose processor with all zero affinity value as the master. + */ +.macro branch_if_slave, xreg, slave_label +#ifdef CONFIG_ARMV8_MULTIENTRY + /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */ + mrs \xreg, mpidr_el1 + tst \xreg, #0xff /* Test Affinity 0 */ + b.ne \slave_label + lsr \xreg, \xreg, #8 + tst \xreg, #0xff /* Test Affinity 1 */ + b.ne \slave_label + lsr \xreg, \xreg, #8 + tst \xreg, #0xff /* Test Affinity 2 */ + b.ne \slave_label + lsr \xreg, \xreg, #16 + tst \xreg, #0xff /* Test Affinity 3 */ + b.ne \slave_label +#endif +.endm + +/* + * Branch if current processor is a master, + * choose processor with all zero affinity value as the master. + */ +.macro branch_if_master, xreg1, xreg2, master_label +#ifdef CONFIG_ARMV8_MULTIENTRY + /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */ + mrs \xreg1, mpidr_el1 + lsr \xreg2, \xreg1, #32 + lsl \xreg2, \xreg2, #32 + lsl \xreg1, \xreg1, #40 + lsr \xreg1, \xreg1, #40 + orr \xreg1, \xreg1, \xreg2 + cbz \xreg1, \master_label +#else + b \master_label +#endif +.endm + +/* + * Switch from EL3 to EL2 for ARMv8 + * @ep: kernel entry point + * @flag: The execution state flag for lower exception + * level, ES_TO_AARCH64 or ES_TO_AARCH32 + * @tmp: temporary register + * + * For loading 32-bit OS, x1 is machine nr and x2 is ftaddr. + * For loading 64-bit OS, x0 is physical address to the FDT blob. + * They will be passed to the guest. + */ +.macro armv8_switch_to_el2_m, ep, flag, tmp + msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */ + mov \tmp, #CPTR_EL2_RES1 + msr cptr_el2, \tmp /* Disable coprocessor traps to EL2 */ + + /* Initialize Generic Timers */ + msr cntvoff_el2, xzr + + /* Initialize SCTLR_EL2 + * + * setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1 + * and RES0 bits (31,30,27,26,24,21,20,17,15-13,10-6) + + * EE,WXN,I,SA,C,A,M to 0 + */ + ldr \tmp, =(SCTLR_EL2_RES1 | SCTLR_EL2_EE_LE |\ + SCTLR_EL2_WXN_DIS | SCTLR_EL2_ICACHE_DIS |\ + SCTLR_EL2_SA_DIS | SCTLR_EL2_DCACHE_DIS |\ + SCTLR_EL2_ALIGN_DIS | SCTLR_EL2_MMU_DIS) + msr sctlr_el2, \tmp + + mov \tmp, sp + msr sp_el2, \tmp /* Migrate SP */ + mrs \tmp, vbar_el3 + msr vbar_el2, \tmp /* Migrate VBAR */ + + /* Check switch to AArch64 EL2 or AArch32 Hypervisor mode */ + cmp \flag, #ES_TO_AARCH32 + b.eq 1f + + /* + * The next lower exception level is AArch64, 64bit EL2 | HCE | + * RES1 (Bits[5:4]) | Non-secure EL0/EL1. + * and the SMD depends on requirements. + */ +#ifdef CONFIG_ARMV8_PSCI + ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\ + SCR_EL3_RES1 | SCR_EL3_NS_EN) +#else + ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\ + SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\ + SCR_EL3_NS_EN) +#endif + +#ifdef CONFIG_ARMV8_EA_EL3_FIRST + orr \tmp, \tmp, #SCR_EL3_EA_EN +#endif + msr scr_el3, \tmp + + /* Return to the EL2_SP2 mode from EL3 */ + ldr \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\ + SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\ + SPSR_EL_M_AARCH64 | SPSR_EL_M_EL2H) + msr spsr_el3, \tmp + msr elr_el3, \ep + eret + +1: + /* + * The next lower exception level is AArch32, 32bit EL2 | HCE | + * SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1. + */ + ldr \tmp, =(SCR_EL3_RW_AARCH32 | SCR_EL3_HCE_EN |\ + SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\ + SCR_EL3_NS_EN) + msr scr_el3, \tmp + + /* Return to AArch32 Hypervisor mode */ + ldr \tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\ + SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\ + SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\ + SPSR_EL_M_HYP) + msr spsr_el3, \tmp + msr elr_el3, \ep + eret +.endm + +/* + * Switch from EL2 to EL1 for ARMv8 + * @ep: kernel entry point + * @flag: The execution state flag for lower exception + * level, ES_TO_AARCH64 or ES_TO_AARCH32 + * @tmp: temporary register + * + * For loading 32-bit OS, x1 is machine nr and x2 is ftaddr. + * For loading 64-bit OS, x0 is physical address to the FDT blob. + * They will be passed to the guest. + */ +.macro armv8_switch_to_el1_m, ep, flag, tmp + /* Initialize Generic Timers */ + mrs \tmp, cnthctl_el2 + /* Enable EL1 access to timers */ + orr \tmp, \tmp, #(CNTHCTL_EL2_EL1PCEN_EN |\ + CNTHCTL_EL2_EL1PCTEN_EN) + msr cnthctl_el2, \tmp + msr cntvoff_el2, xzr + + /* Initilize MPID/MPIDR registers */ + mrs \tmp, midr_el1 + msr vpidr_el2, \tmp + mrs \tmp, mpidr_el1 + msr vmpidr_el2, \tmp + + /* Disable coprocessor traps */ + mov \tmp, #CPTR_EL2_RES1 + msr cptr_el2, \tmp /* Disable coprocessor traps to EL2 */ + msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */ + mov \tmp, #CPACR_EL1_FPEN_EN + msr cpacr_el1, \tmp /* Enable FP/SIMD at EL1 */ + + /* SCTLR_EL1 initialization + * + * setting RES1 bits (29,28,23,22,20,11) to 1 + * and RES0 bits (31,30,27,21,17,13,10,6) + + * UCI,EE,EOE,WXN,nTWE,nTWI,UCT,DZE,I,UMA,SED,ITD, + * CP15BEN,SA0,SA,C,A,M to 0 + */ + ldr \tmp, =(SCTLR_EL1_RES1 | SCTLR_EL1_UCI_DIS |\ + SCTLR_EL1_EE_LE | SCTLR_EL1_WXN_DIS |\ + SCTLR_EL1_NTWE_DIS | SCTLR_EL1_NTWI_DIS |\ + SCTLR_EL1_UCT_DIS | SCTLR_EL1_DZE_DIS |\ + SCTLR_EL1_ICACHE_DIS | SCTLR_EL1_UMA_DIS |\ + SCTLR_EL1_SED_EN | SCTLR_EL1_ITD_EN |\ + SCTLR_EL1_CP15BEN_DIS | SCTLR_EL1_SA0_DIS |\ + SCTLR_EL1_SA_DIS | SCTLR_EL1_DCACHE_DIS |\ + SCTLR_EL1_ALIGN_DIS | SCTLR_EL1_MMU_DIS) + msr sctlr_el1, \tmp + + mov \tmp, sp + msr sp_el1, \tmp /* Migrate SP */ + mrs \tmp, vbar_el2 + msr vbar_el1, \tmp /* Migrate VBAR */ + + /* Check switch to AArch64 EL1 or AArch32 Supervisor mode */ + cmp \flag, #ES_TO_AARCH32 + b.eq 1f + + /* Initialize HCR_EL2 */ + ldr \tmp, =(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS) + msr hcr_el2, \tmp + + /* Return to the EL1_SP1 mode from EL2 */ + ldr \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\ + SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\ + SPSR_EL_M_AARCH64 | SPSR_EL_M_EL1H) + msr spsr_el2, \tmp + msr elr_el2, \ep + eret + +1: + /* Initialize HCR_EL2 */ + ldr \tmp, =(HCR_EL2_RW_AARCH32 | HCR_EL2_HCD_DIS) + msr hcr_el2, \tmp + + /* Return to AArch32 Supervisor mode from EL2 */ + ldr \tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\ + SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\ + SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\ + SPSR_EL_M_SVC) + msr spsr_el2, \tmp + msr elr_el2, \ep + eret +.endm + +#if defined(CONFIG_GICV3) +.macro gic_wait_for_interrupt_m xreg1 +0 : wfi + mrs \xreg1, ICC_IAR1_EL1 + msr ICC_EOIR1_EL1, \xreg1 + cbnz \xreg1, 0b +.endm +#elif defined(CONFIG_GICV2) +.macro gic_wait_for_interrupt_m xreg1, wreg2 +0 : wfi + ldr \wreg2, [\xreg1, GICC_AIAR] + str \wreg2, [\xreg1, GICC_AEOIR] + and \wreg2, \wreg2, #0x3ff + cbnz \wreg2, 0b +.endm +#endif + +#endif /* CONFIG_ARM64 */ + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARM_MACRO_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/memory.h b/roms/u-boot/arch/arm/include/asm/memory.h new file mode 100644 index 000000000..6b460786e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/memory.h @@ -0,0 +1,136 @@ +/* + * linux/include/asm-arm/memory.h + * + * Copyright (C) 2000-2002 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Note: this file should not be included by non-asm/.h files + */ +#ifndef __ASM_ARM_MEMORY_H +#define __ASM_ARM_MEMORY_H + +#if 0 /* XXX###XXX */ + +#include + +/* + * PFNs are used to describe any physical page; this means + * PFN 0 == physical address 0. + * + * This is the PFN of the first RAM page in the kernel + * direct-mapped view. We assume this is the first page + * of RAM in the mem_map as well. + */ +#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT) + +/* + * These are *only* valid on the kernel direct mapped RAM memory. + */ +static inline unsigned long virt_to_phys(void *x) +{ + return __virt_to_phys((unsigned long)(x)); +} + +static inline void *phys_to_virt(unsigned long x) +{ + return (void *)(__phys_to_virt((unsigned long)(x))); +} + +#define __pa(x) __virt_to_phys((unsigned long)(x)) +#define __va(x) ((void *)__phys_to_virt((unsigned long)(x))) + +/* + * Virtual <-> DMA view memory address translations + * Again, these are *only* valid on the kernel direct mapped RAM + * memory. Use of these is *deprecated*. + */ +#define virt_to_bus(x) (__virt_to_bus((unsigned long)(x))) +#define bus_to_virt(x) ((void *)(__bus_to_virt((unsigned long)(x)))) + +/* + * Conversion between a struct page and a physical address. + * + * Note: when converting an unknown physical address to a + * struct page, the resulting pointer must be validated + * using VALID_PAGE(). It must return an invalid struct page + * for any physical address not corresponding to a system + * RAM address. + * + * page_to_pfn(page) convert a struct page * to a PFN number + * pfn_to_page(pfn) convert a _valid_ PFN number to struct page * + * pfn_valid(pfn) indicates whether a PFN number is valid + * + * virt_to_page(k) convert a _valid_ virtual address to struct page * + * virt_addr_valid(k) indicates whether a virtual address is valid + */ +#ifndef CONFIG_DISCONTIGMEM + +#define page_to_pfn(page) (((page) - mem_map) + PHYS_PFN_OFFSET) +#define pfn_to_page(pfn) ((mem_map + (pfn)) - PHYS_PFN_OFFSET) +#define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) + +#define virt_to_page(kaddr) (pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)) +#define virt_addr_valid(kaddr) ((kaddr) >= PAGE_OFFSET && (kaddr) < (unsigned long)high_memory) + +#define PHYS_TO_NID(addr) (0) + +#define VALID_PAGE(page) ((page - mem_map) < max_mapnr) + +#else + +/* + * This is more complex. We have a set of mem_map arrays spread + * around in memory. + */ +#define page_to_pfn(page) \ + (((page) - page_zone(page)->zone_mem_map) \ + + (page_zone(page)->zone_start_paddr >> PAGE_SHIFT)) + +#define pfn_to_page(pfn) \ + (PFN_TO_MAPBASE(pfn) + LOCAL_MAP_NR((pfn) << PAGE_SHIFT)) + +#define pfn_valid(pfn) \ + ({ \ + unsigned int node = PFN_TO_NID(pfn); \ + struct pglist_data *nd = NODE_DATA(node); \ + ((node < NR_NODES) && \ + ((pfn - (nd->node_start_paddr >> PAGE_SHIFT)) < nd->node_size));\ + }) + +#define virt_to_page(kaddr) \ + (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr)) + +#define virt_addr_valid(kaddr) (KVADDR_TO_NID(kaddr) < NR_NODES) + +/* + * Common discontigmem stuff. + * PHYS_TO_NID is used by the ARM kernel/setup.c + */ +#define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT) + +/* + * 2.4 compatibility + * + * VALID_PAGE returns a non-zero value if given page pointer is valid. + * This assumes all node's mem_maps are stored within the node they + * refer to. This is actually inherently buggy. + */ +#define VALID_PAGE(page) \ +({ unsigned int node = KVADDR_TO_NID(page); \ + ((node < NR_NODES) && \ + ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size)); \ +}) + +#endif + +/* + * We should really eliminate virt_to_bus() here - it's deprecated. + */ +#define page_to_bus(page) (virt_to_bus(page_address(page))) + +#endif /* XXX###XXX */ + +#endif /* __ASM_ARM_MEMORY_H */ diff --git a/roms/u-boot/arch/arm/include/asm/mmu.h b/roms/u-boot/arch/arm/include/asm/mmu.h new file mode 100644 index 000000000..9ac16f599 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/mmu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARM_MMU_H +#define __ASM_ARM_MMU_H + +void init_addr_map(void); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/omap_common.h b/roms/u-boot/arch/arm/include/asm/omap_common.h new file mode 100644 index 000000000..de8fc99d0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/omap_common.h @@ -0,0 +1,838 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments, + * + * Aneesh V + */ +#ifndef _OMAP_COMMON_H_ +#define _OMAP_COMMON_H_ + +#ifndef __ASSEMBLY__ + +#include + +#define NUM_SYS_CLKS 7 + +struct bd_info; + +struct prcm_regs { + /* cm1.ckgen */ + u32 cm_clksel_core; + u32 cm_clksel_abe; + u32 cm_dll_ctrl; + u32 cm_clkmode_dpll_core; + u32 cm_idlest_dpll_core; + u32 cm_autoidle_dpll_core; + u32 cm_clksel_dpll_core; + u32 cm_div_m2_dpll_core; + u32 cm_div_m3_dpll_core; + u32 cm_div_h11_dpll_core; + u32 cm_div_h12_dpll_core; + u32 cm_div_h13_dpll_core; + u32 cm_div_h14_dpll_core; + u32 cm_div_h21_dpll_core; + u32 cm_div_h24_dpll_core; + u32 cm_ssc_deltamstep_dpll_core; + u32 cm_ssc_modfreqdiv_dpll_core; + u32 cm_emu_override_dpll_core; + u32 cm_div_h22_dpllcore; + u32 cm_div_h23_dpll_core; + u32 cm_clkmode_dpll_mpu; + u32 cm_idlest_dpll_mpu; + u32 cm_autoidle_dpll_mpu; + u32 cm_clksel_dpll_mpu; + u32 cm_div_m2_dpll_mpu; + u32 cm_ssc_deltamstep_dpll_mpu; + u32 cm_ssc_modfreqdiv_dpll_mpu; + u32 cm_bypclk_dpll_mpu; + u32 cm_clkmode_dpll_iva; + u32 cm_idlest_dpll_iva; + u32 cm_autoidle_dpll_iva; + u32 cm_clksel_dpll_iva; + u32 cm_div_h11_dpll_iva; + u32 cm_div_h12_dpll_iva; + u32 cm_ssc_deltamstep_dpll_iva; + u32 cm_ssc_modfreqdiv_dpll_iva; + u32 cm_bypclk_dpll_iva; + u32 cm_clkmode_dpll_abe; + u32 cm_idlest_dpll_abe; + u32 cm_autoidle_dpll_abe; + u32 cm_clksel_dpll_abe; + u32 cm_div_m2_dpll_abe; + u32 cm_div_m3_dpll_abe; + u32 cm_ssc_deltamstep_dpll_abe; + u32 cm_ssc_modfreqdiv_dpll_abe; + u32 cm_clkmode_dpll_ddrphy; + u32 cm_idlest_dpll_ddrphy; + u32 cm_autoidle_dpll_ddrphy; + u32 cm_clksel_dpll_ddrphy; + u32 cm_div_m2_dpll_ddrphy; + u32 cm_div_h11_dpll_ddrphy; + u32 cm_div_h12_dpll_ddrphy; + u32 cm_div_h13_dpll_ddrphy; + u32 cm_ssc_deltamstep_dpll_ddrphy; + u32 cm_clkmode_dpll_dsp; + u32 cm_shadow_freq_config1; + u32 cm_clkmode_dpll_gmac; + u32 cm_mpu_mpu_clkctrl; + + /* cm1.dsp */ + u32 cm_dsp_clkstctrl; + u32 cm_dsp_dsp_clkctrl; + + /* cm1.abe */ + u32 cm1_abe_clkstctrl; + u32 cm1_abe_l4abe_clkctrl; + u32 cm1_abe_aess_clkctrl; + u32 cm1_abe_pdm_clkctrl; + u32 cm1_abe_dmic_clkctrl; + u32 cm1_abe_mcasp_clkctrl; + u32 cm1_abe_mcbsp1_clkctrl; + u32 cm1_abe_mcbsp2_clkctrl; + u32 cm1_abe_mcbsp3_clkctrl; + u32 cm1_abe_slimbus_clkctrl; + u32 cm1_abe_timer5_clkctrl; + u32 cm1_abe_timer6_clkctrl; + u32 cm1_abe_timer7_clkctrl; + u32 cm1_abe_timer8_clkctrl; + u32 cm1_abe_wdt3_clkctrl; + + /* cm2.ckgen */ + u32 cm_clksel_mpu_m3_iss_root; + u32 cm_clksel_usb_60mhz; + u32 cm_scale_fclk; + u32 cm_core_dvfs_perf1; + u32 cm_core_dvfs_perf2; + u32 cm_core_dvfs_perf3; + u32 cm_core_dvfs_perf4; + u32 cm_core_dvfs_current; + u32 cm_iva_dvfs_perf_tesla; + u32 cm_iva_dvfs_perf_ivahd; + u32 cm_iva_dvfs_perf_abe; + u32 cm_iva_dvfs_current; + u32 cm_clkmode_dpll_per; + u32 cm_idlest_dpll_per; + u32 cm_autoidle_dpll_per; + u32 cm_clksel_dpll_per; + u32 cm_div_m2_dpll_per; + u32 cm_div_m3_dpll_per; + u32 cm_div_h11_dpll_per; + u32 cm_div_h12_dpll_per; + u32 cm_div_h13_dpll_per; + u32 cm_div_h14_dpll_per; + u32 cm_ssc_deltamstep_dpll_per; + u32 cm_ssc_modfreqdiv_dpll_per; + u32 cm_emu_override_dpll_per; + u32 cm_clkmode_dpll_usb; + u32 cm_idlest_dpll_usb; + u32 cm_autoidle_dpll_usb; + u32 cm_clksel_dpll_usb; + u32 cm_div_m2_dpll_usb; + u32 cm_ssc_deltamstep_dpll_usb; + u32 cm_ssc_modfreqdiv_dpll_usb; + u32 cm_clkdcoldo_dpll_usb; + u32 cm_clkmode_dpll_pcie_ref; + u32 cm_clkmode_apll_pcie; + u32 cm_idlest_apll_pcie; + u32 cm_div_m2_apll_pcie; + u32 cm_clkvcoldo_apll_pcie; + u32 cm_clkmode_dpll_unipro; + u32 cm_idlest_dpll_unipro; + u32 cm_autoidle_dpll_unipro; + u32 cm_clksel_dpll_unipro; + u32 cm_div_m2_dpll_unipro; + u32 cm_ssc_deltamstep_dpll_unipro; + u32 cm_ssc_modfreqdiv_dpll_unipro; + u32 cm_coreaon_usb_phy1_core_clkctrl; + u32 cm_coreaon_usb_phy2_core_clkctrl; + u32 cm_coreaon_usb_phy3_core_clkctrl; + u32 cm_coreaon_l3init_60m_gfclk_clkctrl; + + /* cm2.core */ + u32 cm_coreaon_bandgap_clkctrl; + u32 cm_coreaon_io_srcomp_clkctrl; + u32 cm_l3_1_clkstctrl; + u32 cm_l3_1_dynamicdep; + u32 cm_l3_1_l3_1_clkctrl; + u32 cm_l3_2_clkstctrl; + u32 cm_l3_2_dynamicdep; + u32 cm_l3_2_l3_2_clkctrl; + u32 cm_l3_gpmc_clkctrl; + u32 cm_l3_2_ocmc_ram_clkctrl; + u32 cm_mpu_m3_clkstctrl; + u32 cm_mpu_m3_staticdep; + u32 cm_mpu_m3_dynamicdep; + u32 cm_mpu_m3_mpu_m3_clkctrl; + u32 cm_sdma_clkstctrl; + u32 cm_sdma_staticdep; + u32 cm_sdma_dynamicdep; + u32 cm_sdma_sdma_clkctrl; + u32 cm_memif_clkstctrl; + u32 cm_memif_dmm_clkctrl; + u32 cm_memif_emif_fw_clkctrl; + u32 cm_memif_emif_1_clkctrl; + u32 cm_memif_emif_2_clkctrl; + u32 cm_memif_dll_clkctrl; + u32 cm_memif_emif_h1_clkctrl; + u32 cm_memif_emif_h2_clkctrl; + u32 cm_memif_dll_h_clkctrl; + u32 cm_c2c_clkstctrl; + u32 cm_c2c_staticdep; + u32 cm_c2c_dynamicdep; + u32 cm_c2c_sad2d_clkctrl; + u32 cm_c2c_modem_icr_clkctrl; + u32 cm_c2c_sad2d_fw_clkctrl; + u32 cm_l4cfg_clkstctrl; + u32 cm_l4cfg_dynamicdep; + u32 cm_l4cfg_l4_cfg_clkctrl; + u32 cm_l4cfg_hw_sem_clkctrl; + u32 cm_l4cfg_mailbox_clkctrl; + u32 cm_l4cfg_sar_rom_clkctrl; + u32 cm_l3instr_clkstctrl; + u32 cm_l3instr_l3_3_clkctrl; + u32 cm_l3instr_l3_instr_clkctrl; + u32 cm_l3instr_intrconn_wp1_clkctrl; + + /* cm2.ivahd */ + u32 cm_ivahd_clkstctrl; + u32 cm_ivahd_ivahd_clkctrl; + u32 cm_ivahd_sl2_clkctrl; + + /* cm2.cam */ + u32 cm_cam_clkstctrl; + u32 cm_cam_iss_clkctrl; + u32 cm_cam_fdif_clkctrl; + u32 cm_cam_vip1_clkctrl; + u32 cm_cam_vip2_clkctrl; + u32 cm_cam_vip3_clkctrl; + u32 cm_cam_lvdsrx_clkctrl; + u32 cm_cam_csi1_clkctrl; + u32 cm_cam_csi2_clkctrl; + + /* cm2.dss */ + u32 cm_dss_clkstctrl; + u32 cm_dss_dss_clkctrl; + + /* cm2.sgx */ + u32 cm_sgx_clkstctrl; + u32 cm_sgx_sgx_clkctrl; + + /* cm2.l3init */ + u32 cm_l3init_clkstctrl; + + /* cm2.l3init */ + u32 cm_l3init_hsmmc1_clkctrl; + u32 cm_l3init_hsmmc2_clkctrl; + u32 cm_l3init_hsi_clkctrl; + u32 cm_l3init_hsusbhost_clkctrl; + u32 cm_l3init_hsusbotg_clkctrl; + u32 cm_l3init_hsusbtll_clkctrl; + u32 cm_l3init_p1500_clkctrl; + u32 cm_l3init_sata_clkctrl; + u32 cm_l3init_fsusb_clkctrl; + u32 cm_l3init_ocp2scp1_clkctrl; + u32 cm_l3init_ocp2scp3_clkctrl; + u32 cm_l3init_usb_otg_ss1_clkctrl; + u32 cm_l3init_usb_otg_ss2_clkctrl; + + u32 prm_irqstatus_mpu; + u32 prm_irqstatus_mpu_2; + + /* cm2.l4per */ + u32 cm_l4per_clkstctrl; + u32 cm_l4per_dynamicdep; + u32 cm_l4per_adc_clkctrl; + u32 cm_l4per_gptimer10_clkctrl; + u32 cm_l4per_gptimer11_clkctrl; + u32 cm_l4per_gptimer2_clkctrl; + u32 cm_l4per_gptimer3_clkctrl; + u32 cm_l4per_gptimer4_clkctrl; + u32 cm_l4per_gptimer9_clkctrl; + u32 cm_l4per_elm_clkctrl; + u32 cm_l4per_gpio2_clkctrl; + u32 cm_l4per_gpio3_clkctrl; + u32 cm_l4per_gpio4_clkctrl; + u32 cm_l4per_gpio5_clkctrl; + u32 cm_l4per_gpio6_clkctrl; + u32 cm_l4per_hdq1w_clkctrl; + u32 cm_l4per_hecc1_clkctrl; + u32 cm_l4per_hecc2_clkctrl; + u32 cm_l4per_i2c1_clkctrl; + u32 cm_l4per_i2c2_clkctrl; + u32 cm_l4per_i2c3_clkctrl; + u32 cm_l4per_i2c4_clkctrl; + u32 cm_l4per_l4per_clkctrl; + u32 cm_l4per_mcasp2_clkctrl; + u32 cm_l4per_mcasp3_clkctrl; + u32 cm_l4per_mgate_clkctrl; + u32 cm_l4per_mcspi1_clkctrl; + u32 cm_l4per_mcspi2_clkctrl; + u32 cm_l4per_mcspi3_clkctrl; + u32 cm_l4per_mcspi4_clkctrl; + u32 cm_l4per_gpio7_clkctrl; + u32 cm_l4per_gpio8_clkctrl; + u32 cm_l4per_mmcsd3_clkctrl; + u32 cm_l4per_mmcsd4_clkctrl; + u32 cm_l4per_msprohg_clkctrl; + u32 cm_l4per_slimbus2_clkctrl; + u32 cm_l4per_qspi_clkctrl; + u32 cm_l4per_uart1_clkctrl; + u32 cm_l4per_uart2_clkctrl; + u32 cm_l4per_uart3_clkctrl; + u32 cm_l4per_uart4_clkctrl; + u32 cm_l4per_mmcsd5_clkctrl; + u32 cm_l4per_i2c5_clkctrl; + u32 cm_l4per_uart5_clkctrl; + u32 cm_l4per_uart6_clkctrl; + u32 cm_l4sec_clkstctrl; + u32 cm_l4sec_staticdep; + u32 cm_l4sec_dynamicdep; + u32 cm_l4sec_aes1_clkctrl; + u32 cm_l4sec_aes2_clkctrl; + u32 cm_l4sec_des3des_clkctrl; + u32 cm_l4sec_pkaeip29_clkctrl; + u32 cm_l4sec_rng_clkctrl; + u32 cm_l4sec_sha2md51_clkctrl; + u32 cm_l4sec_cryptodma_clkctrl; + + /* l4 wkup regs */ + u32 cm_abe_pll_ref_clksel; + u32 cm_sys_clksel; + u32 cm_abe_pll_sys_clksel; + u32 cm_wkup_clkstctrl; + u32 cm_wkup_l4wkup_clkctrl; + u32 cm_wkup_wdtimer1_clkctrl; + u32 cm_wkup_wdtimer2_clkctrl; + u32 cm_wkup_gpio1_clkctrl; + u32 cm_wkup_gptimer1_clkctrl; + u32 cm_wkup_gptimer12_clkctrl; + u32 cm_wkup_synctimer_clkctrl; + u32 cm_wkup_usim_clkctrl; + u32 cm_wkup_sarram_clkctrl; + u32 cm_wkup_keyboard_clkctrl; + u32 cm_wkup_rtc_clkctrl; + u32 cm_wkup_bandgap_clkctrl; + u32 cm_wkupaon_scrm_clkctrl; + u32 cm_wkupaon_io_srcomp_clkctrl; + u32 prm_rstctrl; + u32 prm_rstst; + u32 prm_rsttime; + u32 prm_io_pmctrl; + u32 prm_vc_val_bypass; + u32 prm_vc_cfg_i2c_mode; + u32 prm_vc_cfg_i2c_clk; + u32 prm_abbldo_mpu_setup; + u32 prm_abbldo_mpu_ctrl; + u32 prm_abbldo_mm_setup; + u32 prm_abbldo_mm_ctrl; + u32 prm_abbldo_iva_setup; + u32 prm_abbldo_iva_ctrl; + u32 prm_abbldo_eve_setup; + u32 prm_abbldo_eve_ctrl; + u32 prm_abbldo_gpu_setup; + u32 prm_abbldo_gpu_ctrl; + + u32 cm_div_m4_dpll_core; + u32 cm_div_m5_dpll_core; + u32 cm_div_m6_dpll_core; + u32 cm_div_m7_dpll_core; + u32 cm_div_m4_dpll_iva; + u32 cm_div_m5_dpll_iva; + u32 cm_div_m4_dpll_ddrphy; + u32 cm_div_m5_dpll_ddrphy; + u32 cm_div_m6_dpll_ddrphy; + u32 cm_div_m4_dpll_per; + u32 cm_div_m5_dpll_per; + u32 cm_div_m6_dpll_per; + u32 cm_div_m7_dpll_per; + u32 cm_l3instr_intrconn_wp1_clkct; + u32 cm_l3init_usbphy_clkctrl; + u32 cm_l4per_mcbsp4_clkctrl; + u32 prm_vc_cfg_channel; + + /* SCRM stuff, used by some boards */ + u32 scrm_auxclk0; + u32 scrm_auxclk1; + + /* GMAC Clk Ctrl */ + u32 cm_gmac_gmac_clkctrl; + u32 cm_gmac_clkstctrl; + + /* IPU */ + u32 cm_ipu_clkstctrl; + u32 cm_ipu_i2c5_clkctrl; + + /*l3main1 edma*/ + u32 cm_l3main1_tptc1_clkctrl; + u32 cm_l3main1_tptc2_clkctrl; +}; + +struct omap_sys_ctrl_regs { + u32 control_status; + u32 control_core_mac_id_0_lo; + u32 control_core_mac_id_0_hi; + u32 control_core_mac_id_1_lo; + u32 control_core_mac_id_1_hi; + u32 control_phy_power_usb; + u32 control_core_mmr_lock1; + u32 control_core_mmr_lock2; + u32 control_core_mmr_lock3; + u32 control_core_mmr_lock4; + u32 control_core_mmr_lock5; + u32 control_core_control_io1; + u32 control_core_control_io2; + u32 control_id_code; + u32 control_std_fuse_die_id_0; + u32 control_std_fuse_die_id_1; + u32 control_std_fuse_die_id_2; + u32 control_std_fuse_die_id_3; + u32 control_std_fuse_opp_bgap; + u32 control_ldosram_iva_voltage_ctrl; + u32 control_ldosram_mpu_voltage_ctrl; + u32 control_ldosram_core_voltage_ctrl; + u32 control_usbotghs_ctrl; + u32 control_phy_power_sata; + u32 control_padconf_core_base; + u32 control_paconf_global; + u32 control_paconf_mode; + u32 control_smart1io_padconf_0; + u32 control_smart1io_padconf_1; + u32 control_smart1io_padconf_2; + u32 control_smart2io_padconf_0; + u32 control_smart2io_padconf_1; + u32 control_smart2io_padconf_2; + u32 control_smart3io_padconf_0; + u32 control_smart3io_padconf_1; + u32 control_pbias; + u32 control_i2c_0; + u32 control_camera_rx; + u32 control_hdmi_tx_phy; + u32 control_uniportm; + u32 control_dsiphy; + u32 control_mcbsplp; + u32 control_usb2phycore; + u32 control_hdmi_1; + u32 control_hsi; + u32 control_ddr3ch1_0; + u32 control_ddr3ch2_0; + u32 control_ddrch1_0; + u32 control_ddrch1_1; + u32 control_ddrch2_0; + u32 control_ddrch2_1; + u32 control_lpddr2ch1_0; + u32 control_lpddr2ch1_1; + u32 control_ddrio_0; + u32 control_ddrio_1; + u32 control_ddrio_2; + u32 control_ddr_control_ext_0; + u32 control_lpddr2io1_0; + u32 control_lpddr2io1_1; + u32 control_lpddr2io1_2; + u32 control_lpddr2io1_3; + u32 control_lpddr2io2_0; + u32 control_lpddr2io2_1; + u32 control_lpddr2io2_2; + u32 control_lpddr2io2_3; + u32 control_hyst_1; + u32 control_usbb_hsic_control; + u32 control_c2c; + u32 control_core_control_spare_rw; + u32 control_core_control_spare_r; + u32 control_core_control_spare_r_c0; + u32 control_srcomp_north_side; + u32 control_srcomp_south_side; + u32 control_srcomp_east_side; + u32 control_srcomp_west_side; + u32 control_srcomp_code_latch; + u32 control_pbiaslite; + u32 control_port_emif1_sdram_config; + u32 control_port_emif1_lpddr2_nvm_config; + u32 control_port_emif2_sdram_config; + u32 control_emif1_sdram_config_ext; + u32 control_emif2_sdram_config_ext; + u32 control_wkup_ldovbb_mpu_voltage_ctrl; + u32 control_wkup_ldovbb_mm_voltage_ctrl; + u32 control_wkup_ldovbb_iva_voltage_ctrl; + u32 control_wkup_ldovbb_eve_voltage_ctrl; + u32 control_wkup_ldovbb_gpu_voltage_ctrl; + u32 control_smart1nopmio_padconf_0; + u32 control_smart1nopmio_padconf_1; + u32 control_padconf_mode; + u32 control_xtal_oscillator; + u32 control_i2c_2; + u32 control_ckobuffer; + u32 control_wkup_control_spare_rw; + u32 control_wkup_control_spare_r; + u32 control_wkup_control_spare_r_c0; + u32 control_srcomp_east_side_wkup; + u32 control_efuse_1; + u32 control_efuse_2; + u32 control_efuse_3; + u32 control_efuse_4; + u32 control_efuse_5; + u32 control_efuse_6; + u32 control_efuse_7; + u32 control_efuse_8; + u32 control_efuse_9; + u32 control_efuse_10; + u32 control_efuse_11; + u32 control_efuse_12; + u32 control_efuse_13; + u32 control_padconf_wkup_base; + u32 iodelay_config_base; + u32 ctrl_core_sma_sw_0; + u32 ctrl_core_sma_sw_1; +}; + +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) +struct dpll_params { + u32 m; + u32 n; + s8 m2; + s8 m3; + s8 m4_h11; + s8 m5_h12; + s8 m6_h13; + s8 m7_h14; + s8 h21; + s8 h22; + s8 h23; + s8 h24; +}; + +struct dpll_regs { + u32 cm_clkmode_dpll; + u32 cm_idlest_dpll; + u32 cm_autoidle_dpll; + u32 cm_clksel_dpll; + u32 cm_div_m2_dpll; + u32 cm_div_m3_dpll; + u32 cm_div_m4_h11_dpll; + u32 cm_div_m5_h12_dpll; + u32 cm_div_m6_h13_dpll; + u32 cm_div_m7_h14_dpll; + u32 reserved[2]; + u32 cm_div_h21_dpll; + u32 cm_div_h22_dpll; + u32 cm_div_h23_dpll; + u32 cm_div_h24_dpll; +}; +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ + +struct dplls { + const struct dpll_params *mpu; + const struct dpll_params *core; + const struct dpll_params *per; + const struct dpll_params *abe; + const struct dpll_params *iva; + const struct dpll_params *usb; + const struct dpll_params *ddr; + const struct dpll_params *gmac; +}; + +struct pmic_data { + u32 base_offset; + u32 step; + u32 start_code; + unsigned gpio; + int gpio_en; + u32 i2c_slave_addr; + void (*pmic_bus_init)(void); + int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data); +}; + +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) +enum { + OPP_LOW, + OPP_NOM, + OPP_OD, + OPP_HIGH, + NUM_OPPS, +}; + +/** + * struct volts_efuse_data - efuse definition for voltage + * @reg: register address for efuse + * @reg_bits: Number of bits in a register address, mandatory. + */ +struct volts_efuse_data { + u32 reg[NUM_OPPS]; + u8 reg_bits; +}; + +struct volts { + u32 value[NUM_OPPS]; + u32 addr; + struct volts_efuse_data efuse; + struct pmic_data *pmic; + + u32 abb_tx_done_mask; +}; + +enum { + VOLT_MPU, + VOLT_CORE, + VOLT_MM, + VOLT_GPU, + VOLT_EVE, + VOLT_IVA, + NUM_VOLT_RAILS, +}; + +struct vcores_data { + struct volts mpu; + struct volts core; + struct volts mm; + struct volts gpu; + struct volts eve; + struct volts iva; +}; +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ + +extern struct prcm_regs const **prcm; +extern struct prcm_regs const omap5_es1_prcm; +extern struct prcm_regs const omap5_es2_prcm; +extern struct prcm_regs const omap4_prcm; +extern struct prcm_regs const dra7xx_prcm; +extern struct dplls const **dplls_data; +extern struct dplls dra7xx_dplls; +extern struct dplls dra72x_dplls; +extern struct dplls dra76x_dplls; +extern struct vcores_data const **omap_vcores; +extern const u32 sys_clk_array[8]; +extern struct omap_sys_ctrl_regs const **ctrl; +extern struct omap_sys_ctrl_regs const am33xx_ctrl; +extern struct omap_sys_ctrl_regs const omap3_ctrl; +extern struct omap_sys_ctrl_regs const omap4_ctrl; +extern struct omap_sys_ctrl_regs const omap5_ctrl; +extern struct omap_sys_ctrl_regs const dra7xx_ctrl; + +extern struct pmic_data tps659038; +extern struct pmic_data lp8733; +extern struct pmic_data lp87565; + +void hw_data_init(void); + +const struct dpll_params *get_mpu_dpll_params(struct dplls const *); +const struct dpll_params *get_core_dpll_params(struct dplls const *); +const struct dpll_params *get_per_dpll_params(struct dplls const *); +const struct dpll_params *get_iva_dpll_params(struct dplls const *); +const struct dpll_params *get_usb_dpll_params(struct dplls const *); +const struct dpll_params *get_abe_dpll_params(struct dplls const *); + +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) +void do_enable_clocks(u32 const *clk_domains, + u32 const *clk_modules_hw_auto, + u32 const *clk_modules_explicit_en, + u8 wait_for_enable); + +void do_disable_clocks(u32 const *clk_domains, + u32 const *clk_modules_disable, + u8 wait_for_disable); +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ + +void setup_post_dividers(u32 const base, + const struct dpll_params *params); +u32 omap_ddr_clk(void); +u32 get_sys_clk_index(void); +void enable_basic_clocks(void); +void enable_basic_uboot_clocks(void); + +void enable_usb_clocks(int index); +void disable_usb_clocks(int index); + +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) +void scale_vcores(struct vcores_data const *); +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ +int get_voltrail_opp(int rail_offset); +u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); +void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); +void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, + u32 txdone, u32 txdone_mask, u32 opp); +s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb); + +struct tag_serialnr; + +void omap_die_id_serial(void); +void omap_die_id_get_board_serial(struct tag_serialnr *serialnr); +void omap_die_id_usbethaddr(void); +void omap_die_id_display(void); + +#ifdef CONFIG_FASTBOOT_FLASH +void omap_set_fastboot_vars(void); +#else +static inline void omap_set_fastboot_vars(void) { } +#endif + +void recalibrate_iodelay(void); + +void omap_smc1(u32 service, u32 val); + +/* + * Low-level helper function used when performing secure ROM calls on high- + * security (HS) device variants by doing a specially-formed smc entry. + */ +u32 omap_smc_sec(u32 service, u32 proc_id, u32 flag, u32 *params); +u32 omap_smc_sec_cpu1(u32 service, u32 proc_id, u32 flag, u32 *params); + +void enable_edma3_clocks(void); +void disable_edma3_clocks(void); + +void omap_die_id(unsigned int *die_id); + +/* Initialize general purpose I2C(0) on the SoC */ +void gpi2c_init(void); + +/* Common FDT Fixups */ +int ft_hs_disable_rng(void *fdt, struct bd_info *bd); +int ft_hs_fixup_dram(void *fdt, struct bd_info *bd); +int ft_hs_add_tee(void *fdt, struct bd_info *bd); + +/* ABB */ +#define OMAP_ABB_NOMINAL_OPP 0 +#define OMAP_ABB_FAST_OPP 1 +#define OMAP_ABB_SLOW_OPP 3 +#define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK (0x1 << 0) +#define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK (0x1 << 1) +#define OMAP_ABB_CONTROL_OPP_CHANGE_MASK (0x1 << 2) +#define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK (0x1 << 6) +#define OMAP_ABB_SETUP_SR2EN_MASK (0x1 << 0) +#define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK (0x1 << 2) +#define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK (0x1 << 1) +#define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK (0xff << 8) + +static inline u32 omap_revision(void) +{ + extern u32 *const omap_si_rev; + return *omap_si_rev; +} + +#define OMAP44xx 0x44000000 + +static inline u8 is_omap44xx(void) +{ + extern u32 *const omap_si_rev; + return (*omap_si_rev & 0xFF000000) == OMAP44xx; +}; + +#define OMAP54xx 0x54000000 + +static inline u8 is_omap54xx(void) +{ + extern u32 *const omap_si_rev; + return ((*omap_si_rev & 0xFF000000) == OMAP54xx); +} + +#define DRA7XX 0x07000000 +#define DRA72X 0x07200000 +#define DRA76X 0x07600000 + +static inline u8 is_dra7xx(void) +{ + extern u32 *const omap_si_rev; + return ((*omap_si_rev & 0xFF000000) == DRA7XX); +} + +static inline u8 is_dra72x(void) +{ + extern u32 *const omap_si_rev; + return (*omap_si_rev & 0xFFF00000) == DRA72X; +} + +static inline u8 is_dra76x(void) +{ + extern u32 *const omap_si_rev; + return (*omap_si_rev & 0xFFF00000) == DRA76X; +} + +static inline u8 is_dra76x_abz(void) +{ + extern u32 *const omap_si_rev; + return (*omap_si_rev & 0xF) == 2; +} + +static inline u8 is_dra76x_acd(void) +{ + extern u32 *const omap_si_rev; + return (*omap_si_rev & 0xF) == 3; +} +#endif + +/* + * silicon revisions. + * Moving this to common, so that most of code can be moved to common, + * directories. + */ + +/* omap4 */ +#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF +#define OMAP4430_ES1_0 0x44300100 +#define OMAP4430_ES2_0 0x44300200 +#define OMAP4430_ES2_1 0x44300210 +#define OMAP4430_ES2_2 0x44300220 +#define OMAP4430_ES2_3 0x44300230 +#define OMAP4460_ES1_0 0x44600100 +#define OMAP4460_ES1_1 0x44600110 +#define OMAP4470_ES1_0 0x44700100 + +/* omap5 */ +#define OMAP5430_SILICON_ID_INVALID 0 +#define OMAP5430_ES1_0 0x54300100 +#define OMAP5432_ES1_0 0x54320100 +#define OMAP5430_ES2_0 0x54300200 +#define OMAP5432_ES2_0 0x54320200 + +/* DRA7XX */ +#define DRA762_ES1_0 0x07620100 +#define DRA752_ES1_0 0x07520100 +#define DRA752_ES1_1 0x07520110 +#define DRA752_ES2_0 0x07520200 +#define DRA722_ES1_0 0x07220100 +#define DRA722_ES2_0 0x07220200 +#define DRA722_ES2_1 0x07220210 + +#define DRA762_ABZ_ES1_0 0x07620102 +#define DRA762_ACD_ES1_0 0x07620103 +/* + * silicon device type + * Moving to common from cpu.h, since it is shared by various omap devices + */ +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + + +/* + * SRAM scratch space entries + */ +#define OMAP_SRAM_SCRATCH_OMAP_REV SRAM_SCRATCH_SPACE_ADDR +#define OMAP_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4) +#define OMAP_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) +#define OMAP_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) +#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) +#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) +#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) +#define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20) +#define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24) +#ifndef TI_SRAM_SCRATCH_BOARD_EEPROM_START +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28) +#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200) +#endif +#define OMAP_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END) + +/* Boot parameters */ +#define DEVICE_DATA_OFFSET 0x18 +#define BOOT_MODE_OFFSET 0x8 + +#define CH_FLAGS_CHSETTINGS (1 << 0) +#define CH_FLAGS_CHRAM (1 << 1) +#define CH_FLAGS_CHFLASH (1 << 2) +#define CH_FLAGS_CHMMCSD (1 << 3) + +#ifndef __ASSEMBLY__ +u32 omap_sys_boot_device(void); +#endif + +#endif /* _OMAP_COMMON_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/omap_gpio.h b/roms/u-boot/arch/arm/include/asm/omap_gpio.h new file mode 100644 index 000000000..408421002 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/omap_gpio.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This work is derived from the linux 2.6.27 kernel source + * To fetch, use the kernel repository + * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git + * Use the v2.6.27 tag. + * + * Below is the original's header including its copyright + * + * linux/arch/arm/plat-omap/gpio.c + * + * Support functions for OMAP GPIO + * + * Copyright (C) 2003-2005 Nokia Corporation + * Written by Juha Yrjölä + */ +#ifndef _GPIO_H +#define _GPIO_H + +#include + +#if CONFIG_IS_ENABLED(DM_GPIO) + +/* Information about a GPIO bank */ +struct omap_gpio_plat { + int bank_index; + ulong base; /* address of registers in physical memory */ + const char *port_name; +}; + +#else + +struct gpio_bank { + void *base; +}; + +extern const struct gpio_bank *const omap_gpio_bank; + +/** + * Check if gpio is valid. + * + * @param gpio GPIO number + * @return 1 if ok, 0 on error + */ +int gpio_is_valid(int gpio); +#endif + +#endif /* _GPIO_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/omap_i2c.h b/roms/u-boot/arch/arm/include/asm/omap_i2c.h new file mode 100644 index 000000000..9f0f27223 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/omap_i2c.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _OMAP_I2C_H +#define _OMAP_I2C_H + +#if CONFIG_IS_ENABLED(DM_I2C) + +/* Information about a GPIO bank */ +struct omap_i2c_plat { + ulong base; /* address of registers in physical memory */ + int speed; + int ip_rev; +}; + +#endif + +enum { + OMAP_I2C_REV_V1 = 0, + OMAP_I2C_REV_V2 = 1, +}; + +#endif /* _OMAP_I2C_H */ diff --git a/roms/u-boot/arch/arm/include/asm/omap_mmc.h b/roms/u-boot/arch/arm/include/asm/omap_mmc.h new file mode 100644 index 000000000..7933ad5a8 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/omap_mmc.h @@ -0,0 +1,240 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef OMAP_MMC_H_ +#define OMAP_MMC_H_ + +#include +#ifndef __ASSEMBLY__ +#include +#endif + +struct hsmmc { +#ifndef CONFIG_OMAP34XX + unsigned int hl_rev; + unsigned int hl_hwinfo; + unsigned int hl_sysconfig; + unsigned char res0[0xf4]; +#endif + unsigned char res1[0x10]; + unsigned int sysconfig; /* 0x10 */ + unsigned int sysstatus; /* 0x14 */ + unsigned char res2[0x14]; + unsigned int con; /* 0x2C */ + unsigned int pwcnt; /* 0x30 */ + unsigned int dll; /* 0x34 */ + unsigned char res3[0xcc]; + unsigned int blk; /* 0x104 */ + unsigned int arg; /* 0x108 */ + unsigned int cmd; /* 0x10C */ + unsigned int rsp10; /* 0x110 */ + unsigned int rsp32; /* 0x114 */ + unsigned int rsp54; /* 0x118 */ + unsigned int rsp76; /* 0x11C */ + unsigned int data; /* 0x120 */ + unsigned int pstate; /* 0x124 */ + unsigned int hctl; /* 0x128 */ + unsigned int sysctl; /* 0x12C */ + unsigned int stat; /* 0x130 */ + unsigned int ie; /* 0x134 */ + unsigned char res4[0x4]; + unsigned int ac12; /* 0x13C */ + unsigned int capa; /* 0x140 */ + unsigned int capa2; /* 0x144 */ + unsigned char res5[0xc]; + unsigned int admaes; /* 0x154 */ + unsigned int admasal; /* 0x158 */ +}; + +struct omap_hsmmc_plat { + struct mmc_config cfg; + struct hsmmc *base_addr; + struct mmc *mmc; + u32 controller_flags; + const char *hw_rev; +}; + +/* + * OMAP HS MMC Bit definitions + */ +#define MADMA_EN (0x1 << 0) +#define MMC_SOFTRESET (0x1 << 1) +#define RESETDONE (0x1 << 0) +#define NOOPENDRAIN (0x0 << 0) +#define OPENDRAIN (0x1 << 0) +#define OD (0x1 << 0) +#define INIT_NOINIT (0x0 << 1) +#define INIT_INITSTREAM (0x1 << 1) +#define HR_NOHOSTRESP (0x0 << 2) +#define STR_BLOCK (0x0 << 3) +#define MODE_FUNC (0x0 << 4) +#define DW8_1_4BITMODE (0x0 << 5) +#define MIT_CTO (0x0 << 6) +#define CDP_ACTIVEHIGH (0x0 << 7) +#define WPP_ACTIVEHIGH (0x0 << 8) +#define RESERVED_MASK (0x3 << 9) +#define CTPL_MMC_SD (0x0 << 11) +#define DDR (0x1 << 19) +#define DMA_MASTER (0x1 << 20) +#define BLEN_512BYTESLEN (0x200 << 0) +#define NBLK_STPCNT (0x0 << 16) +#define DE_ENABLE (0x1 << 0) +#define BCE_ENABLE (0x1 << 1) +#define ACEN_ENABLE (0x1 << 2) +#define DDIR_OFFSET (4) +#define DDIR_MASK (0x1 << 4) +#define DDIR_WRITE (0x0 << 4) +#define DDIR_READ (0x1 << 4) +#define MSBS_SGLEBLK (0x0 << 5) +#define MSBS_MULTIBLK (0x1 << 5) +#define RSP_TYPE_OFFSET (16) +#define RSP_TYPE_MASK (0x3 << 16) +#define RSP_TYPE_NORSP (0x0 << 16) +#define RSP_TYPE_LGHT136 (0x1 << 16) +#define RSP_TYPE_LGHT48 (0x2 << 16) +#define RSP_TYPE_LGHT48B (0x3 << 16) +#define CCCE_NOCHECK (0x0 << 19) +#define CCCE_CHECK (0x1 << 19) +#define CICE_NOCHECK (0x0 << 20) +#define CICE_CHECK (0x1 << 20) +#define DP_OFFSET (21) +#define DP_MASK (0x1 << 21) +#define DP_NO_DATA (0x0 << 21) +#define DP_DATA (0x1 << 21) +#define CMD_TYPE_NORMAL (0x0 << 22) +#define INDEX_OFFSET (24) +#define INDEX_MASK (0x3f << 24) +#define INDEX(i) (i << 24) +#define DATI_MASK (0x1 << 1) +#define CMDI_MASK (0x1 << 0) +#define DTW_1_BITMODE (0x0 << 1) +#define DTW_4_BITMODE (0x1 << 1) +#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/ +#define SDBP_PWROFF (0x0 << 8) +#define SDBP_PWRON (0x1 << 8) +#define SDVS_MASK (0x7 << 9) +#define SDVS_1V8 (0x5 << 9) +#define SDVS_3V0 (0x6 << 9) +#define SDVS_3V3 (0x7 << 9) +#define DMA_SELECT (0x2 << 3) +#define ICE_MASK (0x1 << 0) +#define ICE_STOP (0x0 << 0) +#define ICS_MASK (0x1 << 1) +#define ICS_NOTREADY (0x0 << 1) +#define ICE_OSCILLATE (0x1 << 0) +#define CEN_MASK (0x1 << 2) +#define CEN_ENABLE (0x1 << 2) +#define CLKD_OFFSET (6) +#define CLKD_MASK (0x3FF << 6) +#define DTO_MASK (0xF << 16) +#define DTO_15THDTO (0xE << 16) +#define SOFTRESETALL (0x1 << 24) +#define CC_MASK (0x1 << 0) +#define TC_MASK (0x1 << 1) +#define BWR_MASK (0x1 << 4) +#define BRR_MASK (0x1 << 5) +#define ERRI_MASK (0x1 << 15) +#define IE_CC (0x01 << 0) +#define IE_TC (0x01 << 1) +#define IE_BWR (0x01 << 4) +#define IE_BRR (0x01 << 5) +#define IE_CTO (0x01 << 16) +#define IE_CCRC (0x01 << 17) +#define IE_CEB (0x01 << 18) +#define IE_CIE (0x01 << 19) +#define IE_DTO (0x01 << 20) +#define IE_DCRC (0x01 << 21) +#define IE_DEB (0x01 << 22) +#define IE_ADMAE (0x01 << 25) +#define IE_CERR (0x01 << 28) +#define IE_BADA (0x01 << 29) + +#define VS33_3V3SUP BIT(24) +#define VS30_3V0SUP BIT(25) +#define VS18_1V8SUP BIT(26) + +#define AC12_ET BIT(22) +#define AC12_V1V8_SIGEN BIT(19) +#define AC12_SCLK_SEL BIT(23) +#define AC12_UHSMC_MASK (7 << 16) +#define AC12_UHSMC_DDR50 (4 << 16) +#define AC12_UHSMC_SDR104 (3 << 16) +#define AC12_UHSMC_SDR50 (2 << 16) +#define AC12_UHSMC_SDR25 (1 << 16) +#define AC12_UHSMC_SDR12 (0 << 16) +#define AC12_UHSMC_RES (0x7 << 16) + +/* Driver definitions */ +#define MMCSD_SECTOR_SIZE 512 +#define MMC_CARD 0 +#define SD_CARD 1 +#define BYTE_MODE 0 +#define SECTOR_MODE 1 +#define CLK_INITSEQ 0 +#define CLK_400KHZ 1 +#define CLK_MISC 2 + +#define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ + +#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) +#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) + +/* Clock Configurations and Macros */ +#ifdef CONFIG_OMAP54XX +#define MMC_CLOCK_REFERENCE 192 /* MHz */ +#else +#define MMC_CLOCK_REFERENCE 96 /* MHz */ +#endif + +/* DLL */ +#define DLL_SWT BIT(20) +#define DLL_FORCE_SR_C_SHIFT 13 +#define DLL_FORCE_SR_C_MASK 0x7f +#define DLL_FORCE_VALUE BIT(12) +#define DLL_CALIB BIT(1) + +#define MAX_PHASE_DELAY 0x7c + +/* CAPA2 */ +#define CAPA2_TSDR50 BIT(13) + +#define mmc_reg_out(addr, mask, val)\ + writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) + +#define INT_EN_MASK (IE_BADA | IE_CERR | IE_DEB | IE_DCRC |\ + IE_DTO | IE_CIE | IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO |\ + IE_BRR | IE_BWR | IE_TC | IE_CC) + +#define CON_CLKEXTFREE BIT(16) +#define CON_PADEN BIT(15) +#define PSTATE_CLEV BIT(24) +#define PSTATE_DLEV (0xF << 20) +#define PSTATE_DLEV_DAT0 (0x1 << 20) + +int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, + int wp_gpio); + +void vmmc_pbias_config(uint voltage); +void board_mmc_poweron_ldo(uint voltage); +#endif /* OMAP_MMC_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/omap_musb.h b/roms/u-boot/arch/arm/include/asm/omap_musb.h new file mode 100644 index 000000000..614c93def --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/omap_musb.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Board data structure for musb gadget on OMAPs + * + * Copyright (C) 2012, Ilya Yanok + */ + +#ifndef __ASM_ARM_OMAP_MUSB_H +#define __ASM_ARM_OMAP_MUSB_H +#include + +extern struct musb_platform_ops musb_dsps_ops; +extern const struct musb_platform_ops am35x_ops; +extern const struct musb_platform_ops omap2430_ops; + +struct omap_musb_board_data { + u8 interface_type; + struct udevice *dev; + void (*set_phy_power)(struct udevice *dev, u8 on); + void (*clear_irq)(struct udevice *dev); + void (*reset)(struct udevice *dev); +}; + +enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI}; + +struct ti_musb_plat { + void *base; + void *ctrl_mod_base; + struct musb_hdrc_platform_data plat; +}; + +#endif /* __ASM_ARM_OMAP_MUSB_H */ diff --git a/roms/u-boot/arch/arm/include/asm/omap_sec_common.h b/roms/u-boot/arch/arm/include/asm/omap_sec_common.h new file mode 100644 index 000000000..30f0a9f5c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/omap_sec_common.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 + * Texas Instruments, + * + * Andreas Dannenberg + */ +#ifndef _OMAP_SEC_COMMON_H_ +#define _OMAP_SEC_COMMON_H_ + +/* + * Invoke secure ROM API on high-security (HS) device variants. It formats + * the variable argument list into the format expected by the ROM code before + * triggering the actual low-level smc entry. + */ +u32 secure_rom_call(u32 service, u32 proc_id, u32 flag, ...); + +/* + * Invoke a secure ROM API on high-secure (HS) device variants that can be used + * to verify a secure blob by authenticating and optionally decrypting it. The + * exact operation performed depends on how the certificate that was embedded + * into the blob during the signing/encryption step when the secure blob was + * first created. + */ +int secure_boot_verify_image(void **p_image, size_t *p_size); + +/* + * Return the start of secure reserved RAM, if a default start address has + * not been configured then return a region at the end of the external DRAM. + */ +u32 get_sec_mem_start(void); + +/* + * Invoke a secure HAL API that allows configuration of the external memory + * firewall regions. + */ +int secure_emif_firewall_setup(uint8_t region_num, uint32_t start_addr, + uint32_t size, uint32_t access_perm, + uint32_t initiator_perm); + +/* + * Invoke a secure HAL API on high-secure (HS) device variants that reserves a + * region of external memory for secure world use, and protects it using memory + * firewalls that prevent public world access. This API is intended to setaside + * memory that will be used for a secure world OS/TEE. + */ +int secure_emif_reserve(void); + +/* + * Invoke a secure HAL API to lock the external memory firewall configurations. + * After this API is called, none of the HAL APIs for configuring the that + * firewall will be usable (calls to those APIs will return failure and have + * no effect). + */ +int secure_emif_firewall_lock(void); + +/* + * Invoke a secure HAL API to authenticate and install a Trusted Execution + * Environment (TEE) image. + */ +int secure_tee_install(u32 tee_image); + +#endif /* _OMAP_SEC_COMMON_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/opcodes-sec.h b/roms/u-boot/arch/arm/include/asm/opcodes-sec.h new file mode 100644 index 000000000..55c696c5b --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/opcodes-sec.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 ARM Limited + */ + +#ifndef __ASM_ARM_OPCODES_SEC_H +#define __ASM_ARM_OPCODES_SEC_H + +#include + +#define __SMC(imm4) __inst_arm_thumb32( \ + 0xE1600070 | (((imm4) & 0xF) << 0), \ + 0xF7F08000 | (((imm4) & 0xF) << 16) \ +) + +#endif /* __ASM_ARM_OPCODES_SEC_H */ diff --git a/roms/u-boot/arch/arm/include/asm/opcodes-virt.h b/roms/u-boot/arch/arm/include/asm/opcodes-virt.h new file mode 100644 index 000000000..437b9a899 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/opcodes-virt.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * opcodes-virt.h: Opcode definitions for the ARM virtualization extensions + * Copyright (C) 2012 Linaro Limited + */ +#ifndef __ASM_ARM_OPCODES_VIRT_H +#define __ASM_ARM_OPCODES_VIRT_H + +#include + +#define __HVC(imm16) __inst_arm_thumb32( \ + 0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F), \ + 0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF) \ +) + +#define __ERET __inst_arm_thumb32( \ + 0xE160006E, \ + 0xF3DE8F00 \ +) + +#define __MSR_ELR_HYP(regnum) __inst_arm_thumb32( \ + 0xE12EF300 | regnum, \ + 0xF3808E30 | (regnum << 16) \ +) + +#endif /* ! __ASM_ARM_OPCODES_VIRT_H */ diff --git a/roms/u-boot/arch/arm/include/asm/opcodes.h b/roms/u-boot/arch/arm/include/asm/opcodes.h new file mode 100644 index 000000000..21b334429 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/opcodes.h @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * arch/arm/include/asm/opcodes.h + */ + +#ifndef __ASM_ARM_OPCODES_H +#define __ASM_ARM_OPCODES_H + +#ifndef __ASSEMBLY__ +#include +extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr); +#endif + +#define ARM_OPCODE_CONDTEST_FAIL 0 +#define ARM_OPCODE_CONDTEST_PASS 1 +#define ARM_OPCODE_CONDTEST_UNCOND 2 + + +/* + * Assembler opcode byteswap helpers. + * These are only intended for use by this header: don't use them directly, + * because they will be suboptimal in most cases. + */ +#define ___asm_opcode_swab32(x) ( \ + (((x) << 24) & 0xFF000000) \ + | (((x) << 8) & 0x00FF0000) \ + | (((x) >> 8) & 0x0000FF00) \ + | (((x) >> 24) & 0x000000FF) \ +) +#define ___asm_opcode_swab16(x) ( \ + (((x) << 8) & 0xFF00) \ + | (((x) >> 8) & 0x00FF) \ +) +#define ___asm_opcode_swahb32(x) ( \ + (((x) << 8) & 0xFF00FF00) \ + | (((x) >> 8) & 0x00FF00FF) \ +) +#define ___asm_opcode_swahw32(x) ( \ + (((x) << 16) & 0xFFFF0000) \ + | (((x) >> 16) & 0x0000FFFF) \ +) +#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF) +#define ___asm_opcode_identity16(x) ((x) & 0xFFFF) + + +/* + * Opcode byteswap helpers + * + * These macros help with converting instructions between a canonical integer + * format and in-memory representation, in an endianness-agnostic manner. + * + * __mem_to_opcode_*() convert from in-memory representation to canonical form. + * __opcode_to_mem_*() convert from canonical form to in-memory representation. + * + * + * Canonical instruction representation: + * + * ARM: 0xKKLLMMNN + * Thumb 16-bit: 0x0000KKLL, where KK < 0xE8 + * Thumb 32-bit: 0xKKLLMMNN, where KK >= 0xE8 + * + * There is no way to distinguish an ARM instruction in canonical representation + * from a Thumb instruction (just as these cannot be distinguished in memory). + * Where this distinction is important, it needs to be tracked separately. + * + * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not + * represent any valid Thumb-2 instruction. For this range, + * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false. + * + * The ___asm variants are intended only for use by this header, in situations + * involving inline assembler. For .S files, the normal __opcode_*() macros + * should do the right thing. + */ +#ifdef __ASSEMBLY__ + +#define ___opcode_swab32(x) ___asm_opcode_swab32(x) +#define ___opcode_swab16(x) ___asm_opcode_swab16(x) +#define ___opcode_swahb32(x) ___asm_opcode_swahb32(x) +#define ___opcode_swahw32(x) ___asm_opcode_swahw32(x) +#define ___opcode_identity32(x) ___asm_opcode_identity32(x) +#define ___opcode_identity16(x) ___asm_opcode_identity16(x) + +#else /* ! __ASSEMBLY__ */ + +#include +#include + +#define ___opcode_swab32(x) swab32(x) +#define ___opcode_swab16(x) swab16(x) +#define ___opcode_swahb32(x) swahb32(x) +#define ___opcode_swahw32(x) swahw32(x) +#define ___opcode_identity32(x) ((u32)(x)) +#define ___opcode_identity16(x) ((u16)(x)) + +#endif /* ! __ASSEMBLY__ */ + + +#ifdef CONFIG_CPU_ENDIAN_BE8 + +#define __opcode_to_mem_arm(x) ___opcode_swab32(x) +#define __opcode_to_mem_thumb16(x) ___opcode_swab16(x) +#define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x) +#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x) +#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x) +#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x) + +#else /* ! CONFIG_CPU_ENDIAN_BE8 */ + +#define __opcode_to_mem_arm(x) ___opcode_identity32(x) +#define __opcode_to_mem_thumb16(x) ___opcode_identity16(x) +#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x) +#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_identity16(x) +#ifndef CONFIG_CPU_ENDIAN_BE32 +/* + * On BE32 systems, using 32-bit accesses to store Thumb instructions will not + * work in all cases, due to alignment constraints. For now, a correct + * version is not provided for BE32. + */ +#define __opcode_to_mem_thumb32(x) ___opcode_swahw32(x) +#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahw32(x) +#endif + +#endif /* ! CONFIG_CPU_ENDIAN_BE8 */ + +#define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x) +#define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x) +#ifndef CONFIG_CPU_ENDIAN_BE32 +#define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x) +#endif + +/* Operations specific to Thumb opcodes */ + +/* Instruction size checks: */ +#define __opcode_is_thumb32(x) ( \ + ((x) & 0xF8000000) == 0xE8000000 \ + || ((x) & 0xF0000000) == 0xF0000000 \ +) +#define __opcode_is_thumb16(x) ( \ + ((x) & 0xFFFF0000) == 0 \ + && !(((x) & 0xF800) == 0xE800 || ((x) & 0xF000) == 0xF000) \ +) + +/* Operations to construct or split 32-bit Thumb instructions: */ +#define __opcode_thumb32_first(x) (___opcode_identity16((x) >> 16)) +#define __opcode_thumb32_second(x) (___opcode_identity16(x)) +#define __opcode_thumb32_compose(first, second) ( \ + (___opcode_identity32(___opcode_identity16(first)) << 16) \ + | ___opcode_identity32(___opcode_identity16(second)) \ +) +#define ___asm_opcode_thumb32_first(x) (___asm_opcode_identity16((x) >> 16)) +#define ___asm_opcode_thumb32_second(x) (___asm_opcode_identity16(x)) +#define ___asm_opcode_thumb32_compose(first, second) ( \ + (___asm_opcode_identity32(___asm_opcode_identity16(first)) << 16) \ + | ___asm_opcode_identity32(___asm_opcode_identity16(second)) \ +) + +/* + * Opcode injection helpers + * + * In rare cases it is necessary to assemble an opcode which the + * assembler does not support directly, or which would normally be + * rejected because of the CFLAGS or AFLAGS used to build the affected + * file. + * + * Before using these macros, consider carefully whether it is feasible + * instead to change the build flags for your file, or whether it really + * makes sense to support old assembler versions when building that + * particular kernel feature. + * + * The macros defined here should only be used where there is no viable + * alternative. + * + * + * __inst_arm(x): emit the specified ARM opcode + * __inst_thumb16(x): emit the specified 16-bit Thumb opcode + * __inst_thumb32(x): emit the specified 32-bit Thumb opcode + * + * __inst_arm_thumb16(arm, thumb): emit either the specified arm or + * 16-bit Thumb opcode, depending on whether an ARM or Thumb-2 + * kernel is being built + * + * __inst_arm_thumb32(arm, thumb): emit either the specified arm or + * 32-bit Thumb opcode, depending on whether an ARM or Thumb-2 + * kernel is being built + * + * + * Note that using these macros directly is poor practice. Instead, you + * should use them to define human-readable wrapper macros to encode the + * instructions that you care about. In code which might run on ARMv7 or + * above, you can usually use the __inst_arm_thumb{16,32} macros to + * specify the ARM and Thumb alternatives at the same time. This ensures + * that the correct opcode gets emitted depending on the instruction set + * used for the kernel build. + * + * Look at opcodes-virt.h for an example of how to use these macros. + */ +#include + +#define __inst_arm(x) ___inst_arm(___asm_opcode_to_mem_arm(x)) +#define __inst_thumb32(x) ___inst_thumb32( \ + ___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_first(x)), \ + ___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_second(x)) \ +) +#define __inst_thumb16(x) ___inst_thumb16(___asm_opcode_to_mem_thumb16(x)) + +#ifdef CONFIG_THUMB2_KERNEL +#define __inst_arm_thumb16(arm_opcode, thumb_opcode) \ + __inst_thumb16(thumb_opcode) +#define __inst_arm_thumb32(arm_opcode, thumb_opcode) \ + __inst_thumb32(thumb_opcode) +#else +#define __inst_arm_thumb16(arm_opcode, thumb_opcode) __inst_arm(arm_opcode) +#define __inst_arm_thumb32(arm_opcode, thumb_opcode) __inst_arm(arm_opcode) +#endif + +/* Helpers for the helpers. Don't use these directly. */ +#ifdef __ASSEMBLY__ +#define ___inst_arm(x) .long x +#define ___inst_thumb16(x) .short x +#define ___inst_thumb32(first, second) .short first, second +#else +#define ___inst_arm(x) ".long " __stringify(x) "\n\t" +#define ___inst_thumb16(x) ".short " __stringify(x) "\n\t" +#define ___inst_thumb32(first, second) \ + ".short " __stringify(first) ", " __stringify(second) "\n\t" +#endif + +#endif /* __ASM_ARM_OPCODES_H */ diff --git a/roms/u-boot/arch/arm/include/asm/pl310.h b/roms/u-boot/arch/arm/include/asm/pl310.h new file mode 100644 index 000000000..f69e9e45f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/pl310.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments, + * Aneesh V + */ +#ifndef _PL310_H_ +#define _PL310_H_ + +#include + +/* Register bit fields */ +#define PL310_AUX_CTRL_ASSOCIATIVITY_MASK (1 << 16) +#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1) +#define L2X0_STNDBY_MODE_EN (1 << 0) +#define L2X0_CTRL_EN 1 + +#define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) +#define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28) +#define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29) +#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0) +#define L310_LATENCY_CTRL_RD(n) ((n) << 4) +#define L310_LATENCY_CTRL_WR(n) ((n) << 8) + +#define L2X0_CACHE_ID_PART_MASK (0xf << 6) +#define L2X0_CACHE_ID_PART_L310 (3 << 6) +#define L2X0_CACHE_ID_RTL_MASK 0x3f +#define L2X0_CACHE_ID_RTL_R3P2 0x8 + +struct pl310_regs { + u32 pl310_cache_id; + u32 pl310_cache_type; + u32 pad1[62]; + u32 pl310_ctrl; + u32 pl310_aux_ctrl; + u32 pl310_tag_latency_ctrl; + u32 pl310_data_latency_ctrl; + u32 pad2[60]; + u32 pl310_event_cnt_ctrl; + u32 pl310_event_cnt1_cfg; + u32 pl310_event_cnt0_cfg; + u32 pl310_event_cnt1_val; + u32 pl310_event_cnt0_val; + u32 pl310_intr_mask; + u32 pl310_masked_intr_stat; + u32 pl310_raw_intr_stat; + u32 pl310_intr_clear; + u32 pad3[323]; + u32 pl310_cache_sync; + u32 pad4[15]; + u32 pl310_inv_line_pa; + u32 pad5[2]; + u32 pl310_inv_way; + u32 pad6[12]; + u32 pl310_clean_line_pa; + u32 pad7[1]; + u32 pl310_clean_line_idx; + u32 pl310_clean_way; + u32 pad8[12]; + u32 pl310_clean_inv_line_pa; + u32 pad9[1]; + u32 pl310_clean_inv_line_idx; + u32 pl310_clean_inv_way; + u32 pad10[64]; + u32 pl310_lockdown_dbase; + u32 pl310_lockdown_ibase; + u32 pad11[190]; + u32 pl310_addr_filter_start; + u32 pl310_addr_filter_end; + u32 pad12[190]; + u32 pl310_test_operation; + u32 pad13[3]; + u32 pl310_line_data; + u32 pad14[7]; + u32 pl310_line_tag; + u32 pad15[3]; + u32 pl310_debug_ctrl; + u32 pad16[7]; + u32 pl310_prefetch_ctrl; + u32 pad17[7]; + u32 pl310_power_ctrl; +}; + +void pl310_inval_all(void); +void pl310_clean_inval_all(void); +void pl310_inval_range(u32 start, u32 end); +void pl310_clean_inval_range(u32 start, u32 end); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/posix_types.h b/roms/u-boot/arch/arm/include/asm/posix_types.h new file mode 100644 index 000000000..d254b95b2 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/posix_types.h @@ -0,0 +1,87 @@ +/* + * linux/include/asm-arm/posix_types.h + * + * Copyright (C) 1996-1998 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Changelog: + * 27-06-1996 RMK Created + */ +#ifndef __ARCH_ARM_POSIX_TYPES_H +#define __ARCH_ARM_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; + +#ifdef __aarch64__ +typedef unsigned long __kernel_size_t; +typedef long __kernel_ssize_t; +typedef long __kernel_ptrdiff_t; +#else +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +#endif + +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31))) + +#undef __FD_CLR +#define __FD_CLR(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31))) + +#undef __FD_ISSET +#define __FD_ISSET(fd, fdsetp) \ + ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0) + +#undef __FD_ZERO +#define __FD_ZERO(fdsetp) \ + (memset (fdsetp, 0, sizeof (*(fd_set *)fdsetp))) + +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/proc-armv/domain.h b/roms/u-boot/arch/arm/include/asm/proc-armv/domain.h new file mode 100644 index 000000000..aadc83187 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/proc-armv/domain.h @@ -0,0 +1,50 @@ +/* + * linux/include/asm-arm/proc-armv/domain.h + * + * Copyright (C) 1999 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_PROC_DOMAIN_H +#define __ASM_PROC_DOMAIN_H + +/* + * Domain numbers + * + * DOMAIN_IO - domain 2 includes all IO only + * DOMAIN_KERNEL - domain 1 includes all kernel memory only + * DOMAIN_USER - domain 0 includes all user memory only + */ +#define DOMAIN_USER 0 +#define DOMAIN_KERNEL 1 +#define DOMAIN_TABLE 1 +#define DOMAIN_IO 2 + +/* + * Domain types + */ +#define DOMAIN_NOACCESS 0 +#define DOMAIN_CLIENT 1 +#define DOMAIN_MANAGER 3 + +#define domain_val(dom,type) ((type) << 2*(dom)) + +#define set_domain(x) \ + do { \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c3, c0 @ set domain" \ + : : "r" (x)); \ + } while (0) + +#define modify_domain(dom,type) \ + do { \ + unsigned int domain = current->thread.domain; \ + domain &= ~domain_val(dom, DOMAIN_MANAGER); \ + domain |= domain_val(dom, type); \ + current->thread.domain = domain; \ + set_domain(current->thread.domain); \ + } while (0) + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/proc-armv/processor.h b/roms/u-boot/arch/arm/include/asm/proc-armv/processor.h new file mode 100644 index 000000000..532f2079e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/proc-armv/processor.h @@ -0,0 +1,74 @@ +/* + * linux/include/asm-arm/proc-armv/processor.h + * + * Copyright (C) 1996-1999 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Changelog: + * 20-09-1996 RMK Created + * 26-09-1996 RMK Added 'EXTRA_THREAD_STRUCT*' + * 28-09-1996 RMK Moved start_thread into the processor dependencies + * 09-09-1998 PJB Delete redundant `wp_works_ok' + * 30-05-1999 PJB Save sl across context switches + * 31-07-1999 RMK Added 'domain' stuff + */ +#ifndef __ASM_PROC_PROCESSOR_H +#define __ASM_PROC_PROCESSOR_H + +#include + +#define KERNEL_STACK_SIZE PAGE_SIZE + +struct context_save_struct { + unsigned long cpsr; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long sl; + unsigned long fp; + unsigned long pc; +}; + +#define INIT_CSS (struct context_save_struct){ SVC_MODE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + +#define EXTRA_THREAD_STRUCT \ + unsigned int domain; + +#define EXTRA_THREAD_STRUCT_INIT \ + domain: domain_val(DOMAIN_USER, DOMAIN_CLIENT) | \ + domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ + domain_val(DOMAIN_IO, DOMAIN_CLIENT) + +#define start_thread(regs,pc,sp) \ +({ \ + unsigned long *stack = (unsigned long *)sp; \ + set_fs(USER_DS); \ + memzero(regs->uregs, sizeof(regs->uregs)); \ + if (current->personality & ADDR_LIMIT_32BIT) \ + regs->ARM_cpsr = USR_MODE; \ + else \ + regs->ARM_cpsr = USR26_MODE; \ + regs->ARM_pc = pc; /* pc */ \ + regs->ARM_sp = sp; /* sp */ \ + regs->ARM_r2 = stack[2]; /* r2 (envp) */ \ + regs->ARM_r1 = stack[1]; /* r1 (argv) */ \ + regs->ARM_r0 = stack[0]; /* r0 (argc) */ \ +}) + +#define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1019]) +#define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1017]) + +/* Allocation and freeing of basic task resources. */ +/* + * NOTE! The task struct and the stack go together + */ +#define ll_alloc_task_struct() ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) +#define ll_free_task_struct(p) free_pages((unsigned long)(p),1) + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/proc-armv/ptrace.h b/roms/u-boot/arch/arm/include/asm/proc-armv/ptrace.h new file mode 100644 index 000000000..e37ad8fd1 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/proc-armv/ptrace.h @@ -0,0 +1,131 @@ +/* + * linux/include/asm-arm/proc-armv/ptrace.h + * + * Copyright (C) 1996-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_PROC_PTRACE_H +#define __ASM_PROC_PTRACE_H + +#ifdef CONFIG_ARM64 + +#define PCMASK 0 + +#ifndef __ASSEMBLY__ + +/* + * This struct defines the way the registers are stored + * on the stack during an exception. + */ +struct pt_regs { + unsigned long elr; + unsigned long regs[31]; +}; + +#endif /* __ASSEMBLY__ */ + +#else /* CONFIG_ARM64 */ + +#define USR26_MODE 0x00 +#define FIQ26_MODE 0x01 +#define IRQ26_MODE 0x02 +#define SVC26_MODE 0x03 +#define USR_MODE 0x10 +#define FIQ_MODE 0x11 +#define IRQ_MODE 0x12 +#define SVC_MODE 0x13 +#define MON_MODE 0x16 +#define ABT_MODE 0x17 +#define HYP_MODE 0x1a +#define UND_MODE 0x1b +#define SYSTEM_MODE 0x1f +#define MODE_MASK 0x1f +#define T_BIT 0x20 +#define F_BIT 0x40 +#define I_BIT 0x80 +#define A_BIT 0x100 +#define CC_V_BIT (1 << 28) +#define CC_C_BIT (1 << 29) +#define CC_Z_BIT (1 << 30) +#define CC_N_BIT (1 << 31) +#define PCMASK 0 + +#ifndef __ASSEMBLY__ + +/* this struct defines the way the registers are stored on the + stack during a system call. */ + +struct pt_regs { + long uregs[18]; +}; + +#define ARM_cpsr uregs[16] +#define ARM_pc uregs[15] +#define ARM_lr uregs[14] +#define ARM_sp uregs[13] +#define ARM_ip uregs[12] +#define ARM_fp uregs[11] +#define ARM_r10 uregs[10] +#define ARM_r9 uregs[9] +#define ARM_r8 uregs[8] +#define ARM_r7 uregs[7] +#define ARM_r6 uregs[6] +#define ARM_r5 uregs[5] +#define ARM_r4 uregs[4] +#define ARM_r3 uregs[3] +#define ARM_r2 uregs[2] +#define ARM_r1 uregs[1] +#define ARM_r0 uregs[0] +#define ARM_ORIG_r0 uregs[17] + +#ifdef __KERNEL__ + +#define user_mode(regs) \ + (((regs)->ARM_cpsr & 0xf) == 0) + +#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) +#define thumb_mode(regs) \ + (((regs)->ARM_cpsr & T_BIT)) +#else +#define thumb_mode(regs) (0) +#endif + +#define processor_mode(regs) \ + ((regs)->ARM_cpsr & MODE_MASK) + +#define interrupts_enabled(regs) \ + (!((regs)->ARM_cpsr & I_BIT)) + +#define fast_interrupts_enabled(regs) \ + (!((regs)->ARM_cpsr & F_BIT)) + +#define condition_codes(regs) \ + ((regs)->ARM_cpsr & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT)) + +/* Are the current registers suitable for user mode? + * (used to maintain security in signal handlers) + */ +static inline int valid_user_regs(struct pt_regs *regs) +{ + if ((regs->ARM_cpsr & 0xf) == 0 && + (regs->ARM_cpsr & (F_BIT|I_BIT)) == 0) + return 1; + + /* + * Force CPSR to something logical... + */ + regs->ARM_cpsr &= (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT|0x10); + + return 0; +} + +#endif /* __KERNEL__ */ + +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_ARM64 */ + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/proc-armv/system.h b/roms/u-boot/arch/arm/include/asm/proc-armv/system.h new file mode 100644 index 000000000..c61374e9f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/proc-armv/system.h @@ -0,0 +1,224 @@ +/* + * linux/include/asm-arm/proc-armv/system.h + * + * Copyright (C) 1996 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_PROC_SYSTEM_H +#define __ASM_PROC_SYSTEM_H + +/* + * Save the current interrupt enable state & disable IRQs + */ +#ifdef CONFIG_ARM64 + +/* + * Save the current interrupt enable state + * and disable IRQs/FIQs + */ +#define local_irq_save(flags) \ + ({ \ + asm volatile( \ + "mrs %0, daif\n" \ + "msr daifset, #3" \ + : "=r" (flags) \ + : \ + : "memory"); \ + }) + +/* + * restore saved IRQ & FIQ state + */ +#define local_irq_restore(flags) \ + ({ \ + asm volatile( \ + "msr daif, %0" \ + : \ + : "r" (flags) \ + : "memory"); \ + }) + +/* + * Enable IRQs/FIQs + */ +#define local_irq_enable() \ + ({ \ + asm volatile( \ + "msr daifclr, #3" \ + : \ + : \ + : "memory"); \ + }) + +/* + * Disable IRQs/FIQs + */ +#define local_irq_disable() \ + ({ \ + asm volatile( \ + "msr daifset, #3" \ + : \ + : \ + : "memory"); \ + }) + +#else /* CONFIG_ARM64 */ + +#define local_irq_save(x) \ + ({ \ + unsigned long temp; \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ local_irq_save\n" \ +" orr %1, %0, #128\n" \ +" msr cpsr_c, %1" \ + : "=r" (x), "=r" (temp) \ + : \ + : "memory"); \ + }) + +/* + * Enable IRQs + */ +#define local_irq_enable() \ + ({ \ + unsigned long temp; \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ local_irq_enable\n" \ +" bic %0, %0, #128\n" \ +" msr cpsr_c, %0" \ + : "=r" (temp) \ + : \ + : "memory"); \ + }) + +/* + * Disable IRQs + */ +#define local_irq_disable() \ + ({ \ + unsigned long temp; \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ local_irq_disable\n" \ +" orr %0, %0, #128\n" \ +" msr cpsr_c, %0" \ + : "=r" (temp) \ + : \ + : "memory"); \ + }) + +/* + * Enable FIQs + */ +#define __stf() \ + ({ \ + unsigned long temp; \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ stf\n" \ +" bic %0, %0, #64\n" \ +" msr cpsr_c, %0" \ + : "=r" (temp) \ + : \ + : "memory"); \ + }) + +/* + * Disable FIQs + */ +#define __clf() \ + ({ \ + unsigned long temp; \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ clf\n" \ +" orr %0, %0, #64\n" \ +" msr cpsr_c, %0" \ + : "=r" (temp) \ + : \ + : "memory"); \ + }) + +/* + * Save the current interrupt enable state. + */ +#define local_save_flags(x) \ + ({ \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ local_save_flags\n" \ + : "=r" (x) \ + : \ + : "memory"); \ + }) + +/* + * restore saved IRQ & FIQ state + */ +#define local_irq_restore(x) \ + __asm__ __volatile__( \ + "msr cpsr_c, %0 @ local_irq_restore\n" \ + : \ + : "r" (x) \ + : "memory") + +#endif /* CONFIG_ARM64 */ + +#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) || \ + defined(CONFIG_ARM64) +/* + * On the StrongARM, "swp" is terminally broken since it bypasses the + * cache totally. This means that the cache becomes inconsistent, and, + * since we use normal loads/stores as well, this is really bad. + * Typically, this causes oopsen in filp_close, but could have other, + * more disasterous effects. There are two work-arounds: + * 1. Disable interrupts and emulate the atomic swap + * 2. Clean the cache, perform atomic swap, flush the cache + * + * We choose (1) since its the "easiest" to achieve here and is not + * dependent on the processor type. + */ +#define swp_is_buggy +#endif + +static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) +{ + extern void __bad_xchg(volatile void *, int); + unsigned long ret; +#ifdef swp_is_buggy + unsigned long flags; +#endif + + switch (size) { +#ifdef swp_is_buggy + case 1: + local_irq_save(flags); + ret = *(volatile unsigned char *)ptr; + *(volatile unsigned char *)ptr = x; + local_irq_restore(flags); + break; + + case 4: + local_irq_save(flags); + ret = *(volatile unsigned long *)ptr; + *(volatile unsigned long *)ptr = x; + local_irq_restore(flags); + break; +#else + case 1: __asm__ __volatile__ ("swpb %0, %1, [%2]" + : "=&r" (ret) + : "r" (x), "r" (ptr) + : "memory"); + break; + case 4: __asm__ __volatile__ ("swp %0, %1, [%2]" + : "=&r" (ret) + : "r" (x), "r" (ptr) + : "memory"); + break; +#endif + default: __bad_xchg(ptr, size), ret = 0; + } + + return ret; +} + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/processor.h b/roms/u-boot/arch/arm/include/asm/processor.h new file mode 100644 index 000000000..83481c6cd --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/processor.h @@ -0,0 +1,134 @@ +/* + * linux/include/asm-arm/processor.h + * + * Copyright (C) 1995-2002 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARM_PROCESSOR_H +#define __ASM_ARM_PROCESSOR_H + +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ __label__ _l; _l: &&_l;}) + +#define FP_SIZE 35 + +struct fp_hard_struct { + unsigned int save[FP_SIZE]; /* as yet undefined */ +}; + +struct fp_soft_struct { + unsigned int save[FP_SIZE]; /* undefined information */ +}; + +union fp_state { + struct fp_hard_struct hard; + struct fp_soft_struct soft; +}; + +typedef unsigned long mm_segment_t; /* domain register */ + +#ifdef __KERNEL__ + +#define EISA_bus 0 +#define MCA_bus 0 +#define MCA_bus__is_a_macro + +#include +#include +#if 0 /* XXX###XXX */ +#include +#endif /* XXX###XXX */ +#include +#include + +union debug_insn { + u32 arm; + u16 thumb; +}; + +struct debug_entry { + u32 address; + union debug_insn insn; +}; + +struct debug_info { + int nsaved; + struct debug_entry bp[2]; +}; + +struct thread_struct { + atomic_t refcount; + /* fault info */ + unsigned long address; + unsigned long trap_no; + unsigned long error_code; + /* floating point */ + union fp_state fpstate; + /* debugging */ + struct debug_info debug; + /* context info */ + struct context_save_struct *save; + EXTRA_THREAD_STRUCT +}; + +#define INIT_THREAD { \ + refcount: ATOMIC_INIT(1), \ + EXTRA_THREAD_STRUCT_INIT \ +} + +/* + * Return saved PC of a blocked thread. + */ +static inline unsigned long thread_saved_pc(struct thread_struct *t) +{ + return t->save ? pc_pointer(t->save->pc) : 0; +} + +static inline unsigned long thread_saved_fp(struct thread_struct *t) +{ + return t->save ? t->save->fp : 0; +} + +/* Forward declaration, a strange C thing */ +struct task_struct; + +/* Free all resources held by a thread. */ +extern void release_thread(struct task_struct *); + +/* Copy and release all segment info associated with a VM */ +#define copy_segments(tsk, mm) do { } while (0) +#define release_segments(mm) do { } while (0) + +unsigned long get_wchan(struct task_struct *p); + +#define THREAD_SIZE (8192) + +extern struct task_struct *alloc_task_struct(void); +extern void __free_task_struct(struct task_struct *); +#define get_task_struct(p) atomic_inc(&(p)->thread.refcount) +#define free_task_struct(p) \ + do { \ + if (atomic_dec_and_test(&(p)->thread.refcount)) \ + __free_task_struct((p)); \ + } while (0) + +#define init_task (init_task_union.task) +#define init_stack (init_task_union.stack) + +#define cpu_relax() barrier() + +/* + * Create a new kernel thread + */ +extern int arch_kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); + +#endif + +#endif /* __ASM_ARM_PROCESSOR_H */ diff --git a/roms/u-boot/arch/arm/include/asm/psci.h b/roms/u-boot/arch/arm/include/asm/psci.h new file mode 100644 index 000000000..67e923406 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/psci.h @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2013 - ARM Ltd + * Author: Marc Zyngier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __ARM_PSCI_H__ +#define __ARM_PSCI_H__ + +#ifndef __ASSEMBLY__ +#include +#endif + +#define ARM_PSCI_VER_1_0 (0x00010000) +#define ARM_PSCI_VER_0_2 (0x00000002) + +/* PSCI 0.1 interface */ +#define ARM_PSCI_FN_BASE 0x95c1ba5e +#define ARM_PSCI_FN(n) (ARM_PSCI_FN_BASE + (n)) + +#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0) +#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1) +#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2) +#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3) + +#define ARM_PSCI_RET_SUCCESS 0 +#define ARM_PSCI_RET_NI (-1) +#define ARM_PSCI_RET_INVAL (-2) +#define ARM_PSCI_RET_DENIED (-3) +#define ARM_PSCI_RET_ALREADY_ON (-4) +#define ARM_PSCI_RET_ON_PENDING (-5) +#define ARM_PSCI_RET_INTERNAL_FAILURE (-6) +#define ARM_PSCI_RET_NOT_PRESENT (-7) +#define ARM_PSCI_RET_DISABLED (-8) +#define ARM_PSCI_RET_INVALID_ADDRESS (-9) + +/* PSCI 0.2 interface */ +#define ARM_PSCI_0_2_FN_BASE 0x84000000 +#define ARM_PSCI_0_2_FN(n) (ARM_PSCI_0_2_FN_BASE + (n)) + +#define ARM_PSCI_0_2_FN64_BASE 0xC4000000 +#define ARM_PSCI_0_2_FN64(n) (ARM_PSCI_0_2_FN64_BASE + (n)) + +#define ARM_PSCI_0_2_FN_PSCI_VERSION ARM_PSCI_0_2_FN(0) +#define ARM_PSCI_0_2_FN_CPU_SUSPEND ARM_PSCI_0_2_FN(1) +#define ARM_PSCI_0_2_FN_CPU_OFF ARM_PSCI_0_2_FN(2) +#define ARM_PSCI_0_2_FN_CPU_ON ARM_PSCI_0_2_FN(3) +#define ARM_PSCI_0_2_FN_AFFINITY_INFO ARM_PSCI_0_2_FN(4) +#define ARM_PSCI_0_2_FN_MIGRATE ARM_PSCI_0_2_FN(5) +#define ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE ARM_PSCI_0_2_FN(6) +#define ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN(7) +#define ARM_PSCI_0_2_FN_SYSTEM_OFF ARM_PSCI_0_2_FN(8) +#define ARM_PSCI_0_2_FN_SYSTEM_RESET ARM_PSCI_0_2_FN(9) + +#define ARM_PSCI_0_2_FN64_CPU_SUSPEND ARM_PSCI_0_2_FN64(1) +#define ARM_PSCI_0_2_FN64_CPU_ON ARM_PSCI_0_2_FN64(3) +#define ARM_PSCI_0_2_FN64_AFFINITY_INFO ARM_PSCI_0_2_FN64(4) +#define ARM_PSCI_0_2_FN64_MIGRATE ARM_PSCI_0_2_FN64(5) +#define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN64(7) +#define ARM_PSCI_0_2_FN64_SYSTEM_RESET2 ARM_PSCI_0_2_FN64(18) + +/* PSCI 1.0 interface */ +#define ARM_PSCI_1_0_FN_PSCI_FEATURES ARM_PSCI_0_2_FN(10) +#define ARM_PSCI_1_0_FN_CPU_FREEZE ARM_PSCI_0_2_FN(11) +#define ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND ARM_PSCI_0_2_FN(12) +#define ARM_PSCI_1_0_FN_NODE_HW_STATE ARM_PSCI_0_2_FN(13) +#define ARM_PSCI_1_0_FN_SYSTEM_SUSPEND ARM_PSCI_0_2_FN(14) +#define ARM_PSCI_1_0_FN_SET_SUSPEND_MODE ARM_PSCI_0_2_FN(15) +#define ARM_PSCI_1_0_FN_STAT_RESIDENCY ARM_PSCI_0_2_FN(16) +#define ARM_PSCI_1_0_FN_STAT_COUNT ARM_PSCI_0_2_FN(17) + +#define ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND ARM_PSCI_0_2_FN64(12) +#define ARM_PSCI_1_0_FN64_NODE_HW_STATE ARM_PSCI_0_2_FN64(13) +#define ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND ARM_PSCI_0_2_FN64(14) +#define ARM_PSCI_1_0_FN64_STAT_RESIDENCY ARM_PSCI_0_2_FN64(16) +#define ARM_PSCI_1_0_FN64_STAT_COUNT ARM_PSCI_0_2_FN64(17) + +/* 1KB stack per core */ +#define ARM_PSCI_STACK_SHIFT 10 +#define ARM_PSCI_STACK_SIZE (1 << ARM_PSCI_STACK_SHIFT) + +/* PSCI affinity level state returned by AFFINITY_INFO */ +#define PSCI_AFFINITY_LEVEL_ON 0 +#define PSCI_AFFINITY_LEVEL_OFF 1 +#define PSCI_AFFINITY_LEVEL_ON_PENDING 2 + +#define PSCI_RESET2_TYPE_VENDOR_SHIFT 31 +#define PSCI_RESET2_TYPE_VENDOR BIT(PSCI_RESET2_TYPE_VENDOR_SHIFT) + +#ifndef __ASSEMBLY__ +#include +#include + +/* These 3 helper functions assume cpu < CONFIG_ARMV7_PSCI_NR_CPUS */ +u32 psci_get_target_pc(int cpu); +u32 psci_get_context_id(int cpu); +void psci_save(int cpu, u32 pc, u32 context_id); + +void psci_cpu_entry(void); +u32 psci_get_cpu_id(void); +void psci_cpu_off_common(void); + +int psci_update_dt(void *fdt); +void psci_board_init(void); +int fdt_psci(void *fdt); + +void psci_v7_flush_dcache_all(void); +#endif /* ! __ASSEMBLY__ */ + +#endif /* __ARM_PSCI_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/ptrace.h b/roms/u-boot/arch/arm/include/asm/ptrace.h new file mode 100644 index 000000000..a836f6cc6 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/ptrace.h @@ -0,0 +1,33 @@ +#ifndef __ASM_ARM_PTRACE_H +#define __ASM_ARM_PTRACE_H + +#define PTRACE_GETREGS 12 +#define PTRACE_SETREGS 13 +#define PTRACE_GETFPREGS 14 +#define PTRACE_SETFPREGS 15 + +#define PTRACE_SETOPTIONS 21 + +/* options set using PTRACE_SETOPTIONS */ +#define PTRACE_O_TRACESYSGOOD 0x00000001 + +#include + +#ifndef __ASSEMBLY__ +#define pc_pointer(v) \ + ((v) & ~PCMASK) + +#define instruction_pointer(regs) \ + (pc_pointer((regs)->ARM_pc)) + +#ifdef __KERNEL__ +extern void show_regs(struct pt_regs *); + +#define predicate(x) (x & 0xf0000000) +#define PREDICATE_ALWAYS 0xe0000000 + +#endif + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/sections.h b/roms/u-boot/arch/arm/include/asm/sections.h new file mode 100644 index 000000000..dff3bc260 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/sections.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2012 The Chromium OS Authors. + */ + +#ifndef __ASM_ARM_SECTIONS_H +#define __ASM_ARM_SECTIONS_H + +#include + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/secure.h b/roms/u-boot/arch/arm/include/asm/secure.h new file mode 100644 index 000000000..c7b00be8e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/secure.h @@ -0,0 +1,61 @@ +#ifndef __ASM_SECURE_H +#define __ASM_SECURE_H + +#include +#include + +#define __secure __section("._secure.text") +#define __secure_data __section("._secure.data") + +#ifndef __ASSEMBLY__ + +typedef struct secure_svc_tbl { + u32 id; +#ifdef CONFIG_ARMV8_PSCI + u8 pad[4]; +#endif + void *func; +} secure_svc_tbl_t; + +/* + * Macro to declare a SiP function service in '_secure_svc_tbl_entries' section + */ +#define DECLARE_SECURE_SVC(_name, _id, _fn) \ + static const secure_svc_tbl_t __secure_svc_ ## _name \ + __used __section("._secure_svc_tbl_entries") \ + = { \ + .id = _id, \ + .func = _fn } + +#else + +#ifdef CONFIG_ARMV8_PSCI +#define SECURE_SVC_TBL_OFFSET 16 +#else +#define SECURE_SVC_TBL_OFFSET 8 + +#endif + +#endif /* __ASSEMBLY__ */ + +#if defined(CONFIG_ARMV7_SECURE_BASE) || defined(CONFIG_ARMV8_SECURE_BASE) +/* + * Warning, horror ahead. + * + * The target code lives in our "secure ram", but u-boot doesn't know + * that, and has blindly added reloc_off to every relocation + * entry. Gahh. Do the opposite conversion. This hack also prevents + * GCC from generating code veeners, which u-boot doesn't relocate at + * all... + */ +#define secure_ram_addr(_fn) ({ \ + DECLARE_GLOBAL_DATA_PTR; \ + void *__fn = _fn; \ + typeof(_fn) *__tmp = (__fn - gd->reloc_off); \ + __tmp; \ + }) +#else +#define secure_ram_addr(_fn) (_fn) +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/setjmp.h b/roms/u-boot/arch/arm/include/asm/setjmp.h new file mode 100644 index 000000000..662bec863 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/setjmp.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * (C) Copyright 2016 Alexander Graf + */ + +#ifndef _SETJMP_H_ +#define _SETJMP_H_ 1 + +/* + * This really should be opaque, but the EFI implementation wrongly + * assumes that a 'struct jmp_buf_data' is defined. + */ +struct jmp_buf_data { +#if defined(__aarch64__) + u64 regs[13]; +#else + u32 regs[10]; /* r4-r9, sl, fp, sp, lr */ +#endif +}; + +typedef struct jmp_buf_data jmp_buf[1]; + +int setjmp(jmp_buf jmp); +void longjmp(jmp_buf jmp, int ret); + +#endif /* _SETJMP_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/setup.h b/roms/u-boot/arch/arm/include/asm/setup.h new file mode 100644 index 000000000..e0e2d7e36 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/setup.h @@ -0,0 +1,274 @@ +/* + * linux/include/asm/setup.h + * + * Copyright (C) 1997-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Structure passed to kernel to tell it about the + * hardware it's running on. See linux/Documentation/arm/Setup + * for more info. + * + * NOTE: + * This file contains two ways to pass information from the boot + * loader to the kernel. The old struct param_struct is deprecated, + * but it will be kept in the kernel for 5 years from now + * (2001). This will allow boot loaders to convert to the new struct + * tag way. + */ +#ifndef __ASMARM_SETUP_H +#define __ASMARM_SETUP_H + +/* + * Usage: + * - do not go blindly adding fields, add them at the end + * - when adding fields, don't rely on the address until + * a patch from me has been released + * - unused fields should be zero (for future expansion) + * - this structure is relatively short-lived - only + * guaranteed to contain useful data in setup_arch() + */ +#define COMMAND_LINE_SIZE 1024 + +/* This is the old deprecated way to pass parameters to the kernel */ +struct param_struct { + union { + struct { + unsigned long page_size; /* 0 */ + unsigned long nr_pages; /* 4 */ + unsigned long ramdisk_size; /* 8 */ + unsigned long flags; /* 12 */ +#define FLAG_READONLY 1 +#define FLAG_RDLOAD 4 +#define FLAG_RDPROMPT 8 + unsigned long rootdev; /* 16 */ + unsigned long video_num_cols; /* 20 */ + unsigned long video_num_rows; /* 24 */ + unsigned long video_x; /* 28 */ + unsigned long video_y; /* 32 */ + unsigned long memc_control_reg; /* 36 */ + unsigned char sounddefault; /* 40 */ + unsigned char adfsdrives; /* 41 */ + unsigned char bytes_per_char_h; /* 42 */ + unsigned char bytes_per_char_v; /* 43 */ + unsigned long pages_in_bank[4]; /* 44 */ + unsigned long pages_in_vram; /* 60 */ + unsigned long initrd_start; /* 64 */ + unsigned long initrd_size; /* 68 */ + unsigned long rd_start; /* 72 */ + unsigned long system_rev; /* 76 */ + unsigned long system_serial_low; /* 80 */ + unsigned long system_serial_high; /* 84 */ + unsigned long mem_fclk_21285; /* 88 */ + } s; + char unused[256]; + } u1; + union { + char paths[8][128]; + struct { + unsigned long magic; + char n[1024 - sizeof(unsigned long)]; + } s; + } u2; + char commandline[COMMAND_LINE_SIZE]; +}; + + +/* + * The new way of passing information: a list of tagged entries + */ + +/* The list ends with an ATAG_NONE node. */ +#define ATAG_NONE 0x00000000 + +struct tag_header { + u32 size; + u32 tag; +}; + +/* The list must start with an ATAG_CORE node */ +#define ATAG_CORE 0x54410001 + +struct tag_core { + u32 flags; /* bit 0 = read-only */ + u32 pagesize; + u32 rootdev; +}; + +/* it is allowed to have multiple ATAG_MEM nodes */ +#define ATAG_MEM 0x54410002 + +struct tag_mem32 { + u32 size; + u32 start; /* physical start address */ +}; + +/* VGA text type displays */ +#define ATAG_VIDEOTEXT 0x54410003 + +struct tag_videotext { + u8 x; + u8 y; + u16 video_page; + u8 video_mode; + u8 video_cols; + u16 video_ega_bx; + u8 video_lines; + u8 video_isvga; + u16 video_points; +}; + +/* describes how the ramdisk will be used in kernel */ +#define ATAG_RAMDISK 0x54410004 + +struct tag_ramdisk { + u32 flags; /* bit 0 = load, bit 1 = prompt */ + u32 size; /* decompressed ramdisk size in _kilo_ bytes */ + u32 start; /* starting block of floppy-based RAM disk image */ +}; + +/* describes where the compressed ramdisk image lives (virtual address) */ +/* + * this one accidentally used virtual addresses - as such, + * it's deprecated. + */ +#define ATAG_INITRD 0x54410005 + +/* describes where the compressed ramdisk image lives (physical address) */ +#define ATAG_INITRD2 0x54420005 + +struct tag_initrd { + u32 start; /* physical start address */ + u32 size; /* size of compressed ramdisk image in bytes */ +}; + +/* board serial number. "64 bits should be enough for everybody" */ +#define ATAG_SERIAL 0x54410006 + +struct tag_serialnr { + u32 low; + u32 high; +}; + +/* board revision */ +#define ATAG_REVISION 0x54410007 + +struct tag_revision { + u32 rev; +}; + +/* initial values for vesafb-type framebuffers. see struct screen_info + * in include/linux/tty.h + */ +#define ATAG_VIDEOLFB 0x54410008 + +struct tag_videolfb { + u16 lfb_width; + u16 lfb_height; + u16 lfb_depth; + u16 lfb_linelength; + u32 lfb_base; + u32 lfb_size; + u8 red_size; + u8 red_pos; + u8 green_size; + u8 green_pos; + u8 blue_size; + u8 blue_pos; + u8 rsvd_size; + u8 rsvd_pos; +}; + +/* command line: \0 terminated string */ +#define ATAG_CMDLINE 0x54410009 + +struct tag_cmdline { + char cmdline[1]; /* this is the minimum size */ +}; + +/* acorn RiscPC specific information */ +#define ATAG_ACORN 0x41000101 + +struct tag_acorn { + u32 memc_control_reg; + u32 vram_pages; + u8 sounddefault; + u8 adfsdrives; +}; + +/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */ +#define ATAG_MEMCLK 0x41000402 + +struct tag_memclk { + u32 fmemclk; +}; + +struct tag { + struct tag_header hdr; + union { + struct tag_core core; + struct tag_mem32 mem; + struct tag_videotext videotext; + struct tag_ramdisk ramdisk; + struct tag_initrd initrd; + struct tag_serialnr serialnr; + struct tag_revision revision; + struct tag_videolfb videolfb; + struct tag_cmdline cmdline; + + /* + * Acorn specific + */ + struct tag_acorn acorn; + + /* + * DC21285 specific + */ + struct tag_memclk memclk; + } u; +}; + +struct tagtable { + u32 tag; + int (*parse)(const struct tag *); +}; + +#define __tag __attribute__((unused)) __section(".taglist") +#define __tagtable(tag, fn) \ +static struct tagtable __tagtable_##fn __tag = { tag, fn } + +#define tag_member_present(tag,member) \ + ((unsigned long)(&((struct tag *)0L)->member + 1) \ + <= (tag)->hdr.size * 4) + +#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) +#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) + +#define for_each_tag(t,base) \ + for (t = base; t->hdr.size; t = tag_next(t)) + +/* + * Memory map description + */ +#define NR_BANKS 8 + +struct meminfo { + int nr_banks; + unsigned long end; + struct { + unsigned long start; + unsigned long size; + int node; + } bank[NR_BANKS]; +}; + +extern struct meminfo meminfo; + +#endif + +/* + * Board specified tags + */ +void setup_board_tags(struct tag **in_params); diff --git a/roms/u-boot/arch/arm/include/asm/spin_table.h b/roms/u-boot/arch/arm/include/asm/spin_table.h new file mode 100644 index 000000000..dec18c6e5 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/spin_table.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_SPIN_TABLE_H__ +#define __ASM_SPIN_TABLE_H__ + +extern u64 spin_table_cpu_release_addr; +extern char spin_table_reserve_begin; +extern char spin_table_reserve_end; + +int spin_table_update_dt(void *fdt); + +#endif /* __ASM_SPIN_TABLE_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/spl.h b/roms/u-boot/arch/arm/include/asm/spl.h new file mode 100644 index 000000000..e568af256 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/spl.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Texas Instruments, + */ +#ifndef _ASM_SPL_H_ +#define _ASM_SPL_H_ + +#if defined(CONFIG_ARCH_OMAP2PLUS) \ + || defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \ + || defined(CONFIG_EXYNOS4210) || defined(CONFIG_ARCH_K3) +/* Platform-specific defines */ +#include + +#else +enum { + BOOT_DEVICE_RAM, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_NAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_NOR, + BOOT_DEVICE_UART, + BOOT_DEVICE_SPI, + BOOT_DEVICE_USB, + BOOT_DEVICE_SATA, + BOOT_DEVICE_I2C, + BOOT_DEVICE_BOARD, + BOOT_DEVICE_DFU, + BOOT_DEVICE_XIP, + BOOT_DEVICE_BOOTROM, + BOOT_DEVICE_NONE +}; +#endif + +/* Linker symbols. */ +extern char __bss_start[], __bss_end[]; + +#ifndef CONFIG_DM +extern gd_t gdata; +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/string.h b/roms/u-boot/arch/arm/include/asm/string.h new file mode 100644 index 000000000..11eaa34fa --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/string.h @@ -0,0 +1,53 @@ +#ifndef __ASM_ARM_STRING_H +#define __ASM_ARM_STRING_H + +#include + +/* + * We don't do inline string functions, since the + * optimised inline asm versions are not small. + */ + +#undef __HAVE_ARCH_STRRCHR +extern char * strrchr(const char * s, int c); + +#undef __HAVE_ARCH_STRCHR +extern char * strchr(const char * s, int c); + +#if CONFIG_IS_ENABLED(USE_ARCH_MEMCPY) +#define __HAVE_ARCH_MEMCPY +#endif +extern void * memcpy(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMMOVE +extern void * memmove(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMCHR +extern void * memchr(const void *, int, __kernel_size_t); + +#undef __HAVE_ARCH_MEMZERO +#if CONFIG_IS_ENABLED(USE_ARCH_MEMSET) +#define __HAVE_ARCH_MEMSET +#endif +extern void * memset(void *, int, __kernel_size_t); + +#if 0 +extern void __memzero(void *ptr, __kernel_size_t n); + +#define memset(p,v,n) \ + ({ \ + if ((n) != 0) { \ + if (__builtin_constant_p((v)) && (v) == 0) \ + __memzero((p),(n)); \ + else \ + memset((p),(v),(n)); \ + } \ + (p); \ + }) + +#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); }) +#else +extern void memzero(void *ptr, __kernel_size_t n); +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/system.h b/roms/u-boot/arch/arm/include/asm/system.h new file mode 100644 index 000000000..11fceec4d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/system.h @@ -0,0 +1,634 @@ +#ifndef __ASM_ARM_SYSTEM_H +#define __ASM_ARM_SYSTEM_H + +#include +#include + +#ifdef CONFIG_ARM64 + +/* + * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions + */ +#define CR_M (1 << 0) /* MMU enable */ +#define CR_A (1 << 1) /* Alignment abort enable */ +#define CR_C (1 << 2) /* Dcache enable */ +#define CR_SA (1 << 3) /* Stack Alignment Check Enable */ +#define CR_I (1 << 12) /* Icache enable */ +#define CR_WXN (1 << 19) /* Write Permision Imply XN */ +#define CR_EE (1 << 25) /* Exception (Big) Endian */ + +#define ES_TO_AARCH64 1 +#define ES_TO_AARCH32 0 + +/* + * SCR_EL3 bits definitions + */ +#define SCR_EL3_RW_AARCH64 (1 << 10) /* Next lower level is AArch64 */ +#define SCR_EL3_RW_AARCH32 (0 << 10) /* Lower lowers level are AArch32 */ +#define SCR_EL3_HCE_EN (1 << 8) /* Hypervisor Call enable */ +#define SCR_EL3_SMD_DIS (1 << 7) /* Secure Monitor Call disable */ +#define SCR_EL3_RES1 (3 << 4) /* Reserved, RES1 */ +#define SCR_EL3_EA_EN (1 << 3) /* External aborts taken to EL3 */ +#define SCR_EL3_NS_EN (1 << 0) /* EL0 and EL1 in Non-scure state */ + +/* + * SPSR_EL3/SPSR_EL2 bits definitions + */ +#define SPSR_EL_END_LE (0 << 9) /* Exception Little-endian */ +#define SPSR_EL_DEBUG_MASK (1 << 9) /* Debug exception masked */ +#define SPSR_EL_ASYN_MASK (1 << 8) /* Asynchronous data abort masked */ +#define SPSR_EL_SERR_MASK (1 << 8) /* System Error exception masked */ +#define SPSR_EL_IRQ_MASK (1 << 7) /* IRQ exception masked */ +#define SPSR_EL_FIQ_MASK (1 << 6) /* FIQ exception masked */ +#define SPSR_EL_T_A32 (0 << 5) /* AArch32 instruction set A32 */ +#define SPSR_EL_M_AARCH64 (0 << 4) /* Exception taken from AArch64 */ +#define SPSR_EL_M_AARCH32 (1 << 4) /* Exception taken from AArch32 */ +#define SPSR_EL_M_SVC (0x3) /* Exception taken from SVC mode */ +#define SPSR_EL_M_HYP (0xa) /* Exception taken from HYP mode */ +#define SPSR_EL_M_EL1H (5) /* Exception taken from EL1h mode */ +#define SPSR_EL_M_EL2H (9) /* Exception taken from EL2h mode */ + +/* + * CPTR_EL2 bits definitions + */ +#define CPTR_EL2_RES1 (3 << 12 | 0x3ff) /* Reserved, RES1 */ + +/* + * SCTLR_EL2 bits definitions + */ +#define SCTLR_EL2_RES1 (3 << 28 | 3 << 22 | 1 << 18 | 1 << 16 |\ + 1 << 11 | 3 << 4) /* Reserved, RES1 */ +#define SCTLR_EL2_EE_LE (0 << 25) /* Exception Little-endian */ +#define SCTLR_EL2_WXN_DIS (0 << 19) /* Write permission is not XN */ +#define SCTLR_EL2_ICACHE_DIS (0 << 12) /* Instruction cache disabled */ +#define SCTLR_EL2_SA_DIS (0 << 3) /* Stack Alignment Check disabled */ +#define SCTLR_EL2_DCACHE_DIS (0 << 2) /* Data cache disabled */ +#define SCTLR_EL2_ALIGN_DIS (0 << 1) /* Alignment check disabled */ +#define SCTLR_EL2_MMU_DIS (0) /* MMU disabled */ + +/* + * CNTHCTL_EL2 bits definitions + */ +#define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */ +#define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */ + +/* + * HCR_EL2 bits definitions + */ +#define HCR_EL2_RW_AARCH64 (1 << 31) /* EL1 is AArch64 */ +#define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */ +#define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */ + +/* + * CPACR_EL1 bits definitions + */ +#define CPACR_EL1_FPEN_EN (3 << 20) /* SIMD and FP instruction enabled */ + +/* + * SCTLR_EL1 bits definitions + */ +#define SCTLR_EL1_RES1 (3 << 28 | 3 << 22 | 1 << 20 |\ + 1 << 11) /* Reserved, RES1 */ +#define SCTLR_EL1_UCI_DIS (0 << 26) /* Cache instruction disabled */ +#define SCTLR_EL1_EE_LE (0 << 25) /* Exception Little-endian */ +#define SCTLR_EL1_WXN_DIS (0 << 19) /* Write permission is not XN */ +#define SCTLR_EL1_NTWE_DIS (0 << 18) /* WFE instruction disabled */ +#define SCTLR_EL1_NTWI_DIS (0 << 16) /* WFI instruction disabled */ +#define SCTLR_EL1_UCT_DIS (0 << 15) /* CTR_EL0 access disabled */ +#define SCTLR_EL1_DZE_DIS (0 << 14) /* DC ZVA instruction disabled */ +#define SCTLR_EL1_ICACHE_DIS (0 << 12) /* Instruction cache disabled */ +#define SCTLR_EL1_UMA_DIS (0 << 9) /* User Mask Access disabled */ +#define SCTLR_EL1_SED_EN (0 << 8) /* SETEND instruction enabled */ +#define SCTLR_EL1_ITD_EN (0 << 7) /* IT instruction enabled */ +#define SCTLR_EL1_CP15BEN_DIS (0 << 5) /* CP15 barrier operation disabled */ +#define SCTLR_EL1_SA0_DIS (0 << 4) /* Stack Alignment EL0 disabled */ +#define SCTLR_EL1_SA_DIS (0 << 3) /* Stack Alignment EL1 disabled */ +#define SCTLR_EL1_DCACHE_DIS (0 << 2) /* Data cache disabled */ +#define SCTLR_EL1_ALIGN_DIS (0 << 1) /* Alignment check disabled */ +#define SCTLR_EL1_MMU_DIS (0) /* MMU disabled */ + +#ifndef __ASSEMBLY__ + +struct pt_regs; + +u64 get_page_table_size(void); +#define PGTABLE_SIZE get_page_table_size() + +/* 2MB granularity */ +#define MMU_SECTION_SHIFT 21 +#define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT) + +/* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */ +enum dcache_option { + DCACHE_OFF = 0 << 2, + DCACHE_WRITETHROUGH = 3 << 2, + DCACHE_WRITEBACK = 4 << 2, + DCACHE_WRITEALLOC = 4 << 2, +}; + +#define wfi() \ + ({asm volatile( \ + "wfi" : : : "memory"); \ + }) + +static inline unsigned int current_el(void) +{ + unsigned long el; + + asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc"); + return 3 & (el >> 2); +} + +static inline unsigned int get_sctlr(void) +{ + unsigned int el; + unsigned long val; + + el = current_el(); + if (el == 1) + asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc"); + else if (el == 2) + asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc"); + else + asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc"); + + return val; +} + +static inline void set_sctlr(unsigned long val) +{ + unsigned int el; + + el = current_el(); + if (el == 1) + asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); + else if (el == 2) + asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc"); + else + asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc"); + + asm volatile("isb"); +} + +static inline unsigned long read_mpidr(void) +{ + unsigned long val; + + asm volatile("mrs %0, mpidr_el1" : "=r" (val)); + + return val; +} + +#define BSP_COREID 0 + +void __asm_flush_dcache_all(void); +void __asm_invalidate_dcache_all(void); +void __asm_flush_dcache_range(u64 start, u64 end); + +/** + * __asm_invalidate_dcache_range() - Invalidate a range of virtual addresses + * + * This performance an invalidate from @start to @end - 1. Both addresses + * should be cache-aligned, otherwise this function will align the start + * address and may continue past the end address. + * + * Data in the address range is evicted from the cache and is not written back + * to memory. + * + * @start: Start address to invalidate + * @end: End address to invalidate up to (exclusive) + */ +void __asm_invalidate_dcache_range(u64 start, u64 end); +void __asm_invalidate_tlb_all(void); +void __asm_invalidate_icache_all(void); +int __asm_invalidate_l3_dcache(void); +int __asm_flush_l3_dcache(void); +int __asm_invalidate_l3_icache(void); +void __asm_switch_ttbr(u64 new_ttbr); + +/* + * armv8_switch_to_el2() - switch from EL3 to EL2 for ARMv8 + * + * @args: For loading 64-bit OS, fdt address. + * For loading 32-bit OS, zero. + * @mach_nr: For loading 64-bit OS, zero. + * For loading 32-bit OS, machine nr + * @fdt_addr: For loading 64-bit OS, zero. + * For loading 32-bit OS, fdt address. + * @arg4: Input argument. + * @entry_point: kernel entry point + * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32 + */ +void __noreturn armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr, + u64 arg4, u64 entry_point, u64 es_flag); +/* + * armv8_switch_to_el1() - switch from EL2 to EL1 for ARMv8 + * + * @args: For loading 64-bit OS, fdt address. + * For loading 32-bit OS, zero. + * @mach_nr: For loading 64-bit OS, zero. + * For loading 32-bit OS, machine nr + * @fdt_addr: For loading 64-bit OS, zero. + * For loading 32-bit OS, fdt address. + * @arg4: Input argument. + * @entry_point: kernel entry point + * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32 + */ +void armv8_switch_to_el1(u64 args, u64 mach_nr, u64 fdt_addr, + u64 arg4, u64 entry_point, u64 es_flag); +void armv8_el2_to_aarch32(u64 args, u64 mach_nr, u64 fdt_addr, + u64 arg4, u64 entry_point); +void gic_init(void); +void gic_send_sgi(unsigned long sgino); +void wait_for_wakeup(void); +void protect_secure_region(void); +void smp_kick_all_cpus(void); + +void flush_l3_cache(void); +void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs); + +/* + * smc_call() - issue a secure monitor call + * + * Issue a secure monitor call in accordance with ARM "SMC Calling convention", + * DEN0028A + * + * @args: input and output arguments + */ +void smc_call(struct pt_regs *args); + +void __noreturn psci_system_reset(void); +void __noreturn psci_system_reset2(u32 reset_level, u32 cookie); +void __noreturn psci_system_off(void); + +#ifdef CONFIG_ARMV8_PSCI +extern char __secure_start[]; +extern char __secure_end[]; +extern char __secure_stack_start[]; +extern char __secure_stack_end[]; + +void armv8_setup_psci(void); +void psci_setup_vectors(void); +void psci_arch_init(void); +#endif + +#endif /* __ASSEMBLY__ */ + +#else /* CONFIG_ARM64 */ + +#ifdef __KERNEL__ + +#define CPU_ARCH_UNKNOWN 0 +#define CPU_ARCH_ARMv3 1 +#define CPU_ARCH_ARMv4 2 +#define CPU_ARCH_ARMv4T 3 +#define CPU_ARCH_ARMv5 4 +#define CPU_ARCH_ARMv5T 5 +#define CPU_ARCH_ARMv5TE 6 +#define CPU_ARCH_ARMv5TEJ 7 +#define CPU_ARCH_ARMv6 8 +#define CPU_ARCH_ARMv7 9 + +/* + * CR1 bits (CP#15 CR1) + */ +#define CR_M (1 << 0) /* MMU enable */ +#define CR_A (1 << 1) /* Alignment abort enable */ +#define CR_C (1 << 2) /* Dcache enable */ +#define CR_W (1 << 3) /* Write buffer enable */ +#define CR_P (1 << 4) /* 32-bit exception handler */ +#define CR_D (1 << 5) /* 32-bit data address range */ +#define CR_L (1 << 6) /* Implementation defined */ +#define CR_B (1 << 7) /* Big endian */ +#define CR_S (1 << 8) /* System MMU protection */ +#define CR_R (1 << 9) /* ROM MMU protection */ +#define CR_F (1 << 10) /* Implementation defined */ +#define CR_Z (1 << 11) /* Implementation defined */ +#define CR_I (1 << 12) /* Icache enable */ +#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ +#define CR_RR (1 << 14) /* Round Robin cache replacement */ +#define CR_L4 (1 << 15) /* LDR pc can set T bit */ +#define CR_DT (1 << 16) +#define CR_IT (1 << 18) +#define CR_ST (1 << 19) +#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ +#define CR_U (1 << 22) /* Unaligned access operation */ +#define CR_XP (1 << 23) /* Extended page tables */ +#define CR_VE (1 << 24) /* Vectored interrupts */ +#define CR_EE (1 << 25) /* Exception (Big) Endian */ +#define CR_TRE (1 << 28) /* TEX remap enable */ +#define CR_AFE (1 << 29) /* Access flag enable */ +#define CR_TE (1 << 30) /* Thumb exception enable */ + +#if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE) +#define PGTABLE_SIZE (4096 * 5) +#elif !defined(PGTABLE_SIZE) +#define PGTABLE_SIZE (4096 * 4) +#endif + +/* + * This is used to ensure the compiler did actually allocate the register we + * asked it for some inline assembly sequences. Apparently we can't trust + * the compiler from one version to another so a bit of paranoia won't hurt. + * This string is meant to be concatenated with the inline asm string and + * will cause compilation to stop on mismatch. + * (for details, see gcc PR 15089) + */ +#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_ARMV7_LPAE +void switch_to_hypervisor_ret(void); +#endif + +#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); + +#ifdef __ARM_ARCH_7A__ +#define wfi() __asm__ __volatile__ ("wfi" : : : "memory") +#else +#define wfi() +#endif + +static inline unsigned long get_cpsr(void) +{ + unsigned long cpsr; + + asm volatile("mrs %0, cpsr" : "=r"(cpsr): ); + return cpsr; +} + +static inline int is_hyp(void) +{ +#ifdef CONFIG_ARMV7_LPAE + /* HYP mode requires LPAE ... */ + return ((get_cpsr() & 0x1f) == 0x1a); +#else + /* ... so without LPAE support we can optimize all hyp code away */ + return 0; +#endif +} + +static inline unsigned int get_cr(void) +{ + unsigned int val; + + if (is_hyp()) + asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val) + : + : "cc"); + else + asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) + : + : "cc"); + return val; +} + +static inline void set_cr(unsigned int val) +{ + if (is_hyp()) + asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" : + : "r" (val) + : "cc"); + else + asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" : + : "r" (val) + : "cc"); + isb(); +} + +#ifdef CONFIG_ARMV7_LPAE +/* Long-Descriptor Translation Table Level 1/2 Bits */ +#define TTB_SECT_XN_MASK (1ULL << 54) +#define TTB_SECT_NG_MASK (1 << 11) +#define TTB_SECT_AF (1 << 10) +#define TTB_SECT_SH_MASK (3 << 8) +#define TTB_SECT_NS_MASK (1 << 5) +#define TTB_SECT_AP (1 << 6) +/* Note: TTB AP bits are set elsewhere */ +#define TTB_SECT_MAIR(x) ((x & 0x7) << 2) /* Index into MAIR */ +#define TTB_SECT (1 << 0) +#define TTB_PAGETABLE (3 << 0) + +/* TTBCR flags */ +#define TTBCR_EAE (1 << 31) +#define TTBCR_T0SZ(x) ((x) << 0) +#define TTBCR_T1SZ(x) ((x) << 16) +#define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0)) +#define TTBCR_IRGN0_NC (0 << 8) +#define TTBCR_IRGN0_WBWA (1 << 8) +#define TTBCR_IRGN0_WT (2 << 8) +#define TTBCR_IRGN0_WBNWA (3 << 8) +#define TTBCR_IRGN0_MASK (3 << 8) +#define TTBCR_ORGN0_NC (0 << 10) +#define TTBCR_ORGN0_WBWA (1 << 10) +#define TTBCR_ORGN0_WT (2 << 10) +#define TTBCR_ORGN0_WBNWA (3 << 10) +#define TTBCR_ORGN0_MASK (3 << 10) +#define TTBCR_SHARED_NON (0 << 12) +#define TTBCR_SHARED_OUTER (2 << 12) +#define TTBCR_SHARED_INNER (3 << 12) +#define TTBCR_EPD0 (0 << 7) + +/* + * VMSAv8-32 Long-descriptor format memory region attributes + * (ARM Architecture Reference Manual section G5.7.4 [DDI0487E.a]) + * + * MAIR0[ 7: 0] 0x00 Device-nGnRnE (aka Strongly-Ordered) + * MAIR0[15: 8] 0xaa Outer/Inner Write-Through, Read-Allocate No Write-Allocate + * MAIR0[23:16] 0xee Outer/Inner Write-Back, Read-Allocate No Write-Allocate + * MAIR0[31:24] 0xff Outer/Inner Write-Back, Read-Allocate Write-Allocate + */ +#define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0xaa << (1 * 8)) | \ + (0xee << (2 * 8)) | (0xff << (3 * 8))) + +/* options available for data cache on each page */ +enum dcache_option { + DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK, + DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1), + DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2), + DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3), +}; +#elif defined(CONFIG_CPU_V7A) +/* Short-Descriptor Translation Table Level 1 Bits */ +#define TTB_SECT_NS_MASK (1 << 19) +#define TTB_SECT_NG_MASK (1 << 17) +#define TTB_SECT_S_MASK (1 << 16) +/* Note: TTB AP bits are set elsewhere */ +#define TTB_SECT_AP (3 << 10) +#define TTB_SECT_TEX(x) ((x & 0x7) << 12) +#define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5) +#define TTB_SECT_XN_MASK (1 << 4) +#define TTB_SECT_C_MASK (1 << 3) +#define TTB_SECT_B_MASK (1 << 2) +#define TTB_SECT (2 << 0) + +/* + * Short-descriptor format memory region attributes, without TEX remap + * (ARM Architecture Reference Manual section G5.7.2 [DDI0487E.a]) + * + * TEX[0] C B + * 0 0 0 Device-nGnRnE (aka Strongly-Ordered) + * 0 1 0 Outer/Inner Write-Through, Read-Allocate No Write-Allocate + * 0 1 1 Outer/Inner Write-Back, Read-Allocate No Write-Allocate + * 1 1 1 Outer/Inner Write-Back, Read-Allocate Write-Allocate + */ +enum dcache_option { + DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT, + DCACHE_WRITETHROUGH = TTB_SECT_DOMAIN(0) | TTB_SECT | TTB_SECT_C_MASK, + DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, + DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1), +}; +#else +#define TTB_SECT_AP (3 << 10) +/* options available for data cache on each page */ +enum dcache_option { + DCACHE_OFF = 0x12, + DCACHE_WRITETHROUGH = 0x1a, + DCACHE_WRITEBACK = 0x1e, + DCACHE_WRITEALLOC = 0x16, +}; +#endif + +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK +#endif + +/* Size of an MMU section */ +enum { +#ifdef CONFIG_ARMV7_LPAE + MMU_SECTION_SHIFT = 21, /* 2MB */ +#else + MMU_SECTION_SHIFT = 20, /* 1MB */ +#endif + MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, +}; + +#ifdef CONFIG_CPU_V7A +/* TTBR0 bits */ +#define TTBR0_BASE_ADDR_MASK 0xFFFFC000 +#define TTBR0_RGN_NC (0 << 3) +#define TTBR0_RGN_WBWA (1 << 3) +#define TTBR0_RGN_WT (2 << 3) +#define TTBR0_RGN_WB (3 << 3) +/* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */ +#define TTBR0_IRGN_NC (0 << 0 | 0 << 6) +#define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6) +#define TTBR0_IRGN_WT (1 << 0 | 0 << 6) +#define TTBR0_IRGN_WB (1 << 0 | 1 << 6) +#endif + +/** + * mmu_page_table_flush() - register an update to page tables + * + * Register an update to the page tables, and flush the TLB + * + * @start: start address of update in page table + * @stop: stop address of update in page table + */ +void mmu_page_table_flush(unsigned long start, unsigned long stop); + +#ifdef CONFIG_ARMV7_PSCI +void psci_arch_cpu_entry(void); +void psci_arch_init(void); +u32 psci_version(void); +s32 psci_features(u32 function_id, u32 psci_fid); +s32 psci_cpu_off(void); +s32 psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc, + u32 context_id); +s32 psci_affinity_info(u32 function_id, u32 target_affinity, + u32 lowest_affinity_level); +u32 psci_migrate_info_type(void); +void psci_system_off(void); +void psci_system_reset(void); +s32 psci_features(u32 function_id, u32 psci_fid); +#endif + +#endif /* __ASSEMBLY__ */ + +#define arch_align_stack(x) (x) + +#endif /* __KERNEL__ */ + +#endif /* CONFIG_ARM64 */ + +#ifndef __ASSEMBLY__ +/** + * save_boot_params() - Save boot parameters before starting reset sequence + * + * If you provide this function it will be called immediately U-Boot starts, + * both for SPL and U-Boot proper. + * + * All registers are unchanged from U-Boot entry. No registers need be + * preserved. + * + * This is not a normal C function. There is no stack. Return by branching to + * save_boot_params_ret. + * + * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3); + */ + +/** + * save_boot_params_ret() - Return from save_boot_params() + * + * If you provide save_boot_params(), then you should jump back to this + * function when done. Try to preserve all registers. + * + * If your implementation of save_boot_params() is in C then it is acceptable + * to simply call save_boot_params_ret() at the end of your function. Since + * there is no link register set up, you cannot just exit the function. U-Boot + * will return to the (initialised) value of lr, and likely crash/hang. + * + * If your implementation of save_boot_params() is in assembler then you + * should use 'b' or 'bx' to return to save_boot_params_ret. + */ +void save_boot_params_ret(void); + +/** + * mmu_set_region_dcache_behaviour_phys() - set virt/phys mapping + * + * Change the virt/phys mapping and cache settings for a region. + * + * @virt: virtual start address of memory region to change + * @phys: physical address for the memory region to set + * @size: size of memory region to change + * @option: dcache option to select + */ +void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys, + size_t size, enum dcache_option option); + +/** + * mmu_set_region_dcache_behaviour() - set cache settings + * + * Change the cache settings for a region. + * + * @start: start address of memory region to change + * @size: size of memory region to change + * @option: dcache option to select + */ +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option); + +#ifdef CONFIG_SYS_NONCACHED_MEMORY +/** + * noncached_init() - Initialize non-cached memory region + * + * Initialize non-cached memory area. This memory region will be typically + * located right below the malloc() area and mapped uncached in the MMU. + * + * It is called during the generic post-relocation init sequence. + * + * Return: 0 if OK + */ +int noncached_init(void); + +phys_addr_t noncached_alloc(size_t size, size_t align); +#endif /* CONFIG_SYS_NONCACHED_MEMORY */ + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/ti-common/davinci_nand.h b/roms/u-boot/arch/arm/include/asm/ti-common/davinci_nand.h new file mode 100644 index 000000000..28842c3b1 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/ti-common/davinci_nand.h @@ -0,0 +1,98 @@ +/* + * NAND Flash Driver + * + * Copyright (C) 2006-2014 Texas Instruments. + * + * Based on Linux DaVinci NAND driver by TI. + */ + +#ifndef _DAVINCI_NAND_H_ +#define _DAVINCI_NAND_H_ + +#include +#include + +#define NAND_READ_START 0x00 +#define NAND_READ_END 0x30 +#define NAND_STATUS 0x70 + +#define MASK_CLE 0x10 +#define MASK_ALE 0x08 + +#ifdef CONFIG_SYS_NAND_MASK_CLE +#undef MASK_CLE +#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE +#endif +#ifdef CONFIG_SYS_NAND_MASK_ALE +#undef MASK_ALE +#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE +#endif + +struct davinci_emif_regs { + uint32_t ercsr; + uint32_t awccr; + uint32_t sdbcr; + uint32_t sdrcr; + union { + uint32_t abncr[4]; + struct { + uint32_t ab1cr; + uint32_t ab2cr; + uint32_t ab3cr; + uint32_t ab4cr; + }; + }; + uint32_t sdtimr; + uint32_t ddrsr; + uint32_t ddrphycr; + uint32_t ddrphysr; + uint32_t totar; + uint32_t totactr; + uint32_t ddrphyid_rev; + uint32_t sdsretr; + uint32_t eirr; + uint32_t eimr; + uint32_t eimsr; + uint32_t eimcr; + uint32_t ioctrlr; + uint32_t iostatr; + uint32_t rsvd0; + uint32_t one_nand_cr; + uint32_t nandfcr; + uint32_t nandfsr; + uint32_t rsvd1[2]; + uint32_t nandfecc[4]; + uint32_t rsvd2[15]; + uint32_t nand4biteccload; + uint32_t nand4bitecc[4]; + uint32_t nanderradd1; + uint32_t nanderradd2; + uint32_t nanderrval1; + uint32_t nanderrval2; +}; + +#define davinci_emif_regs \ + ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) + +#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2)) +#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) +#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4) +#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2))) +#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) +#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) +#define DAVINCI_NANDFCR_CS2NAND (1 << 0) + +/* Chip Select setup */ +#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) +#define DAVINCI_ABCR_EXT_WAIT (1 << 30) +#define DAVINCI_ABCR_WSETUP(n) (n << 26) +#define DAVINCI_ABCR_WSTROBE(n) (n << 20) +#define DAVINCI_ABCR_WHOLD(n) (n << 17) +#define DAVINCI_ABCR_RSETUP(n) (n << 13) +#define DAVINCI_ABCR_RSTROBE(n) (n << 7) +#define DAVINCI_ABCR_RHOLD(n) (n << 4) +#define DAVINCI_ABCR_TA(n) (n << 2) +#define DAVINCI_ABCR_ASIZE_16BIT 1 +#define DAVINCI_ABCR_ASIZE_8BIT 0 + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/ti-common/keystone_nav.h b/roms/u-boot/arch/arm/include/asm/ti-common/keystone_nav.h new file mode 100644 index 000000000..e57751442 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/ti-common/keystone_nav.h @@ -0,0 +1,190 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Multicore Navigator definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + */ + +#ifndef _KEYSTONE_NAV_H_ +#define _KEYSTONE_NAV_H_ + +#include +#include + +#define QM_OK 0 +#define QM_ERR -1 +#define QM_DESC_TYPE_HOST 0 +#define QM_DESC_PSINFO_IN_DESCR 0 +#define QM_DESC_DEFAULT_DESCINFO (QM_DESC_TYPE_HOST << 30) | \ + (QM_DESC_PSINFO_IN_DESCR << 22) + +/* Packet Info */ +#define QM_DESC_PINFO_EPIB 1 +#define QM_DESC_PINFO_RETURN_OWN 1 +#define QM_DESC_DEFAULT_PINFO (QM_DESC_PINFO_EPIB << 31) | \ + (QM_DESC_PINFO_RETURN_OWN << 15) + +struct qm_cfg_reg { + u32 revision; + u32 __pad1; + u32 divert; + u32 link_ram_base0; + u32 link_ram_size0; + u32 link_ram_base1; + u32 link_ram_size1; + u32 link_ram_base2; + u32 starvation[0]; +}; + +struct descr_mem_setup_reg { + u32 base_addr; + u32 start_idx; + u32 desc_reg_size; + u32 _res0; +}; + +struct qm_reg_queue { + u32 entry_count; + u32 byte_count; + u32 packet_size; + u32 ptr_size_thresh; +}; + +struct qm_config { + /* QM module addresses */ + u32 stat_cfg; /* status and config */ + struct qm_reg_queue *queue; /* management region */ + u32 mngr_vbusm; /* management region (VBUSM) */ + u32 i_lram; /* internal linking RAM */ + struct qm_reg_queue *proxy; + u32 status_ram; + struct qm_cfg_reg *mngr_cfg; + /* Queue manager config region */ + u32 intd_cfg; /* QMSS INTD config region */ + struct descr_mem_setup_reg *desc_mem; + /* descritor memory setup region*/ + u32 region_num; + u32 pdsp_cmd; /* PDSP1 command interface */ + u32 pdsp_ctl; /* PDSP1 control registers */ + u32 pdsp_iram; + /* QM configuration parameters */ + + u32 qpool_num; /* */ +}; + +struct qm_host_desc { + u32 desc_info; + u32 tag_info; + u32 packet_info; + u32 buff_len; + u32 buff_ptr; + u32 next_bdptr; + u32 orig_buff_len; + u32 orig_buff_ptr; + u32 timestamp; + u32 swinfo[3]; + u32 ps_data[20]; +}; + +#define HDESC_NUM 256 + +int qm_init(void); +void qm_close(void); +void qm_push(struct qm_host_desc *hd, u32 qnum); +struct qm_host_desc *qm_pop(u32 qnum); + +void qm_buff_push(struct qm_host_desc *hd, u32 qnum, + void *buff_ptr, u32 buff_len); + +struct qm_host_desc *qm_pop_from_free_pool(void); +void queue_close(u32 qnum); + +/* + * DMA API + */ +#define CPDMA_REG_VAL_MAKE_RX_FLOW_A(einfo, psinfo, rxerr, desc, \ + psloc, sopoff, qmgr, qnum) \ + (((einfo & 1) << 30) | \ + ((psinfo & 1) << 29) | \ + ((rxerr & 1) << 28) | \ + ((desc & 3) << 26) | \ + ((psloc & 1) << 25) | \ + ((sopoff & 0x1ff) << 16) | \ + ((qmgr & 3) << 12) | \ + ((qnum & 0xfff) << 0)) + +#define CPDMA_REG_VAL_MAKE_RX_FLOW_D(fd0qm, fd0qnum, fd1qm, fd1qnum) \ + (((fd0qm & 3) << 28) | \ + ((fd0qnum & 0xfff) << 16) | \ + ((fd1qm & 3) << 12) | \ + ((fd1qnum & 0xfff) << 0)) + +#define CPDMA_CHAN_A_ENABLE ((u32)1 << 31) +#define CPDMA_CHAN_A_TDOWN (1 << 30) +#define TDOWN_TIMEOUT_COUNT 100 + +struct global_ctl_regs { + u32 revision; + u32 perf_control; + u32 emulation_control; + u32 priority_control; + u32 qm_base_addr[4]; +}; + +struct tx_chan_regs { + u32 cfg_a; + u32 cfg_b; + u32 res[6]; +}; + +struct rx_chan_regs { + u32 cfg_a; + u32 res[7]; +}; + +struct rx_flow_regs { + u32 control; + u32 tags; + u32 tag_sel; + u32 fdq_sel[2]; + u32 thresh[3]; +}; + +struct pktdma_cfg { + struct global_ctl_regs *global; + struct tx_chan_regs *tx_ch; + u32 tx_ch_num; + struct rx_chan_regs *rx_ch; + u32 rx_ch_num; + u32 *tx_sched; + struct rx_flow_regs *rx_flows; + u32 rx_flow_num; + + u32 rx_free_q; + u32 rx_rcv_q; + u32 tx_snd_q; + + u32 rx_flow; /* flow that is used for RX */ +}; + +extern struct pktdma_cfg netcp_pktdma; + +/* + * packet dma user allocates memory for rx buffers + * and describe it in the following structure + */ +struct rx_buff_desc { + u8 *buff_ptr; + u32 num_buffs; + u32 buff_len; + u32 rx_flow; +}; + +int ksnav_close(struct pktdma_cfg *pktdma); +int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers); +int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2); +void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes); +void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd); + +#endif /* _KEYSTONE_NAV_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/ti-common/keystone_net.h b/roms/u-boot/arch/arm/include/asm/ti-common/keystone_net.h new file mode 100644 index 000000000..0852ce80a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/ti-common/keystone_net.h @@ -0,0 +1,235 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * emac definitions for keystone2 devices + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + */ + +#ifndef _KEYSTONE_NET_H_ +#define _KEYSTONE_NET_H_ + +#include +#include +#ifndef __ASSEMBLY__ +#include +#endif + +/* EMAC */ +#ifdef CONFIG_KSNET_NETCP_V1_0 + +#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00090000) +#define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x900) +#define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x300) +#define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x100) +#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x040) + +/* Register offsets */ +#define CPGMACSL_REG_CTL 0x04 +#define CPGMACSL_REG_STATUS 0x08 +#define CPGMACSL_REG_RESET 0x0c +#define CPGMACSL_REG_MAXLEN 0x10 + +#elif defined CONFIG_KSNET_NETCP_V1_5 + +#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00200000) +#define CPGMACSL_REG_RX_PRI_MAP 0x020 +#define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x22000) +#define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x00f00) +#define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x00100) +#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x1000) + +/* Register offsets */ +#define CPGMACSL_REG_CTL 0x330 +#define CPGMACSL_REG_STATUS 0x334 +#define CPGMACSL_REG_RESET 0x338 +#define CPGMACSL_REG_MAXLEN 0x024 + +#endif + +#define KEYSTONE2_EMAC_GIG_ENABLE + +#define MAC_ID_BASE_ADDR CONFIG_KSNET_MAC_ID_BASE + +/* MDIO module input frequency */ +#ifdef CONFIG_SOC_K2G +#define EMAC_MDIO_BUS_FREQ (ks_clk_get_rate(sys_clk0_3_clk)) +#else +#define EMAC_MDIO_BUS_FREQ (ks_clk_get_rate(pass_pll_clk)) +#endif +/* MDIO clock output frequency */ +#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ + +#define EMAC_MACCONTROL_MIIEN_ENABLE 0x20 +#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE 0x1 +#define EMAC_MACCONTROL_GIGABIT_ENABLE BIT(7) +#define EMAC_MACCONTROL_GIGFORCE BIT(17) +#define EMAC_MACCONTROL_RMIISPEED_100 BIT(15) + +#define EMAC_MIN_ETHERNET_PKT_SIZE 60 + +struct mac_sl_cfg { + u_int32_t max_rx_len; /* Maximum receive packet length. */ + u_int32_t ctl; /* Control bitfield */ +}; + +/** + * Definition: Control bitfields used in the ctl field of mac_sl_cfg + */ +#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES BIT(24) +#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES BIT(23) +#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES BIT(22) +#define GMACSL_RX_ENABLE_EXT_CTL BIT(18) +#define GMACSL_RX_ENABLE_GIG_FORCE BIT(17) +#define GMACSL_RX_ENABLE_IFCTL_B BIT(16) +#define GMACSL_RX_ENABLE_IFCTL_A BIT(15) +#define GMACSL_RX_ENABLE_CMD_IDLE BIT(11) +#define GMACSL_TX_ENABLE_SHORT_GAP BIT(10) +#define GMACSL_ENABLE_GIG_MODE BIT(7) +#define GMACSL_TX_ENABLE_PACE BIT(6) +#define GMACSL_ENABLE BIT(5) +#define GMACSL_TX_ENABLE_FLOW_CTL BIT(4) +#define GMACSL_RX_ENABLE_FLOW_CTL BIT(3) +#define GMACSL_ENABLE_LOOPBACK BIT(1) +#define GMACSL_ENABLE_FULL_DUPLEX BIT(0) + +/* EMAC SL function return values */ +#define GMACSL_RET_OK 0 +#define GMACSL_RET_INVALID_PORT -1 +#define GMACSL_RET_WARN_RESET_INCOMPLETE -2 +#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3 +#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4 + +/* EMAC SL register definitions */ +#define DEVICE_EMACSL_RESET_POLL_COUNT 100 + +/* Soft reset register values */ +#define CPGMAC_REG_RESET_VAL_RESET_MASK BIT(0) +#define CPGMAC_REG_RESET_VAL_RESET BIT(0) +#define CPGMAC_REG_MAXLEN_LEN 0x3fff + +/* CPSW */ +/* Control bitfields */ +#define CPSW_CTL_P2_PASS_PRI_TAGGED BIT(5) +#define CPSW_CTL_P1_PASS_PRI_TAGGED BIT(4) +#define CPSW_CTL_P0_PASS_PRI_TAGGED BIT(3) +#define CPSW_CTL_P0_ENABLE BIT(2) +#define CPSW_CTL_VLAN_AWARE BIT(1) +#define CPSW_CTL_FIFO_LOOPBACK BIT(0) + +#define DEVICE_CPSW_NUM_PORTS CONFIG_KSNET_CPSW_NUM_PORTS +#define DEVICE_N_GMACSL_PORTS (DEVICE_CPSW_NUM_PORTS - 1) + +#ifdef CONFIG_KSNET_NETCP_V1_0 + +#define DEVICE_CPSW_BASE (GBETH_BASE + 0x800) +#define CPSW_REG_CTL 0x004 +#define CPSW_REG_STAT_PORT_EN 0x00c +#define CPSW_REG_MAXLEN 0x040 +#define CPSW_REG_ALE_CONTROL 0x608 +#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x) * 4) +#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf + +#elif defined CONFIG_KSNET_NETCP_V1_5 + +#define DEVICE_CPSW_BASE (GBETH_BASE + 0x20000) +#define CPSW_REG_CTL 0x00004 +#define CPSW_REG_STAT_PORT_EN 0x00014 +#define CPSW_REG_MAXLEN 0x01024 +#define CPSW_REG_ALE_CONTROL 0x1e008 +#define CPSW_REG_ALE_PORTCTL(x) (0x1e040 + (x) * 4) +#define CPSW_REG_VAL_STAT_ENABLE_ALL 0x1ff + +#endif + +#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000) +#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010) +#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3 + +#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE +#define SWITCH_MAX_PKT_SIZE 9000 + +/* SGMII */ +#define SGMII_REG_STATUS_LOCK BIT(4) +#define SGMII_REG_STATUS_LINK BIT(0) +#define SGMII_REG_STATUS_AUTONEG BIT(2) +#define SGMII_REG_CONTROL_AUTONEG BIT(0) +#define SGMII_REG_CONTROL_MASTER BIT(5) +#define SGMII_REG_MR_ADV_ENABLE BIT(0) +#define SGMII_REG_MR_ADV_LINK BIT(15) +#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12) +#define SGMII_REG_MR_ADV_GIG_MODE BIT(11) + +#define SGMII_LINK_MAC_MAC_AUTONEG 0 +#define SGMII_LINK_MAC_PHY 1 +#define SGMII_LINK_MAC_MAC_FORCED 2 +#define SGMII_LINK_MAC_FIBER 3 +#define SGMII_LINK_MAC_PHY_FORCED 4 + +#ifdef CONFIG_KSNET_NETCP_V1_0 +#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100)) +#elif defined CONFIG_KSNET_NETCP_V1_5 +#define SGMII_OFFSET(x) ((x) * 0x100) +#endif + +#define SGMII_IDVER_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000) +#define SGMII_SRESET_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004) +#define SGMII_CTL_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010) +#define SGMII_STATUS_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014) +#define SGMII_MRADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018) +#define SGMII_LPADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020) +#define SGMII_TXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030) +#define SGMII_RXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034) +#define SGMII_AUXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038) + +/* RGMII */ +#define RGMII_REG_STATUS_LINK BIT(0) + +#define RGMII_STATUS_REG (GBETH_BASE + 0x18) + +/* PSS */ +#ifdef CONFIG_KSNET_NETCP_V1_0 + +#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x604) +#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x06060606 +#define hw_config_streaming_switch()\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR); + +#elif defined CONFIG_KSNET_NETCP_V1_5 + +#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x500) +#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x0 + +#define hw_config_streaming_switch()\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR);\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR+4);\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR+8);\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR+12); + +#endif + +/* EMAC MDIO Registers Structure */ +struct mdio_regs { + u32 version; + u32 control; + u32 alive; + u32 link; + u32 linkintraw; + u32 linkintmasked; + u32 rsvd0[2]; + u32 userintraw; + u32 userintmasked; + u32 userintmaskset; + u32 userintmaskclear; + u32 rsvd1[20]; + u32 useraccess0; + u32 userphysel0; + u32 useraccess1; + u32 userphysel1; +}; + +#endif /* _KEYSTONE_NET_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/ti-common/keystone_serdes.h b/roms/u-boot/arch/arm/include/asm/ti-common/keystone_serdes.h new file mode 100644 index 000000000..623438856 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/ti-common/keystone_serdes.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Texas Instruments Keystone SerDes driver + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + */ + +#ifndef __TI_KEYSTONE_SERDES_H__ +#define __TI_KEYSTONE_SERDES_H__ + +/* SERDES Reference clock */ +enum ks2_serdes_clock { + SERDES_CLOCK_100M, /* 100 MHz */ + SERDES_CLOCK_122P88M, /* 122.88 MHz */ + SERDES_CLOCK_125M, /* 125 MHz */ + SERDES_CLOCK_156P25M, /* 156.25 MHz */ + SERDES_CLOCK_312P5M, /* 312.5 MHz */ +}; + +/* SERDES Lane Baud Rate */ +enum ks2_serdes_rate { + SERDES_RATE_4P9152G, /* 4.9152 GBaud */ + SERDES_RATE_5G, /* 5 GBaud */ + SERDES_RATE_6P144G, /* 6.144 GBaud */ + SERDES_RATE_6P25G, /* 6.25 GBaud */ + SERDES_RATE_10p3125g, /* 10.3215 GBaud */ + SERDES_RATE_12p5g, /* 12.5 GBaud */ +}; + +/* SERDES Lane Rate Mode */ +enum ks2_serdes_rate_mode { + SERDES_FULL_RATE, + SERDES_HALF_RATE, + SERDES_QUARTER_RATE, +}; + +/* SERDES PHY TYPE */ +enum ks2_serdes_interface { + SERDES_PHY_SGMII, + SERDES_PHY_PCSR, /* XGE SERDES */ +}; + +struct ks2_serdes { + enum ks2_serdes_clock clk; + enum ks2_serdes_rate rate; + enum ks2_serdes_rate_mode rate_mode; + enum ks2_serdes_interface intf; + u32 loopback; +}; + +int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes); + +#endif /* __TI_KEYSTONE_SERDES_H__ */ diff --git a/roms/u-boot/arch/arm/include/asm/ti-common/omap_wdt.h b/roms/u-boot/arch/arm/include/asm/ti-common/omap_wdt.h new file mode 100644 index 000000000..42d7e4c98 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/ti-common/omap_wdt.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * omap_wdt.h + * + * OMAP Watchdog header file + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef __OMAP_WDT_H__ +#define __OMAP_WDT_H__ + +#ifndef __ASSEMBLY__ +#include +#endif + +/* + * Watchdog: + * Using the prescaler, the OMAP watchdog could go for many + * months before firing. These limits work without scaling, + * with the 60 second default assumed by most tools and docs. + */ +#define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */ +#define TIMER_MARGIN_DEFAULT 60 /* 60 secs */ +#define TIMER_MARGIN_MIN 1 + +#define PTV 0 /* prescale */ +#define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1< + */ +#ifndef _TI_COMMON_SYS_PROTO_H_ +#define _TI_COMMON_SYS_PROTO_H_ + +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_ARCH_OMAP2PLUS +#define TI_ARMV7_DRAM_ADDR_SPACE_START 0x80000000 +#define TI_ARMV7_DRAM_ADDR_SPACE_END 0xFFFFFFFF + +#define OMAP_INIT_CONTEXT_SPL 0 +#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1 +#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2 +#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3 + +static inline u32 running_from_sdram(void) +{ + u32 pc; + asm volatile ("mov %0, pc" : "=r" (pc)); + return ((pc >= TI_ARMV7_DRAM_ADDR_SPACE_START) && + (pc < TI_ARMV7_DRAM_ADDR_SPACE_END)); +} + +static inline u8 uboot_loaded_by_spl(void) +{ + /* + * u-boot can be running from sdram either because of configuration + * Header or by SPL. If because of CH, then the romcode sets the + * CHSETTINGS executed bit to true in the boot parameter structure that + * it passes to the bootloader.This parameter is stored in the ch_flags + * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a + * mandatory section if CH is present. + */ + if (gd->arch.omap_ch_flags & CH_FLAGS_CHSETTINGS) + return 0; + else + return running_from_sdram(); +} + +/* + * The basic hardware init of OMAP(s_init()) can happen in 4 + * different contexts: + * 1. SPL running from SRAM + * 2. U-Boot running from FLASH + * 3. Non-XIP U-Boot loaded to SDRAM by SPL + * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the + * Configuration Header feature + * + * This function finds this context. + * Defining as inline may help in compiling out unused functions in SPL + */ +static inline u32 omap_hw_init_context(void) +{ +#ifdef CONFIG_SPL_BUILD + return OMAP_INIT_CONTEXT_SPL; +#else + if (uboot_loaded_by_spl()) + return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL; + else if (running_from_sdram()) + return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH; + else + return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR; +#endif +} +#endif + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/ti-common/ti-aemif.h b/roms/u-boot/arch/arm/include/asm/ti-common/ti-aemif.h new file mode 100644 index 000000000..a77538673 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/ti-common/ti-aemif.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * AEMIF definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + */ + +#ifndef _AEMIF_H_ +#define _AEMIF_H_ + +#define AEMIF_NUM_CS 4 +#define AEMIF_MODE_NOR 0 +#define AEMIF_MODE_NAND 1 +#define AEMIF_MODE_ONENAND 2 +#define AEMIF_PRESERVE -1 + +struct aemif_config { + unsigned mode; + unsigned select_strobe; + unsigned extend_wait; + unsigned wr_setup; + unsigned wr_strobe; + unsigned wr_hold; + unsigned rd_setup; + unsigned rd_strobe; + unsigned rd_hold; + unsigned turn_around; + enum { + AEMIF_WIDTH_8 = 0, + AEMIF_WIDTH_16 = 1, + AEMIF_WIDTH_32 = 2, + } width; +}; + +void aemif_init(int num_cs, struct aemif_config *config); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/ti-common/ti-edma3.h b/roms/u-boot/arch/arm/include/asm/ti-common/ti-edma3.h new file mode 100644 index 000000000..9abdbc88e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/ti-common/ti-edma3.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Enhanced Direct Memory Access (EDMA3) Controller + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + */ + +#ifndef _EDMA3_H_ +#define _EDMA3_H_ + +#ifndef __ASSEMBLY__ +#include +#endif +#include + +#define EDMA3_PARSET_NULL_LINK 0xffff + +/* + * All parameter RAM set options + * opt field in edma3_param_set_config structure + */ +#define EDMA3_SLOPT_PRIV_LEVEL BIT(31) +#define EDMA3_SLOPT_PRIV_ID(id) ((0xf & (id)) << 24) +#define EDMA3_SLOPT_INTERM_COMP_CHAIN_ENB BIT(23) +#define EDMA3_SLOPT_TRANS_COMP_CHAIN_ENB BIT(22) +#define EDMA3_SLOPT_INTERM_COMP_INT_ENB BIT(21) +#define EDMA3_SLOPT_TRANS_COMP_INT_ENB BIT(20) +#define EDMA3_SLOPT_COMP_CODE(code) ((0x3f & (code)) << 12) +#define EDMA3_SLOPT_FIFO_WIDTH_8 0 +#define EDMA3_SLOPT_FIFO_WIDTH_16 (1 << 8) +#define EDMA3_SLOPT_FIFO_WIDTH_32 (2 << 8) +#define EDMA3_SLOPT_FIFO_WIDTH_64 (3 << 8) +#define EDMA3_SLOPT_FIFO_WIDTH_128 (4 << 8) +#define EDMA3_SLOPT_FIFO_WIDTH_256 (5 << 8) +#define EDMA3_SLOPT_FIFO_WIDTH_SET(w) ((w & 0x7) << 8) +#define EDMA3_SLOPT_STATIC BIT(3) +#define EDMA3_SLOPT_AB_SYNC BIT(2) +#define EDMA3_SLOPT_DST_ADDR_CONST_MODE BIT(1) +#define EDMA3_SLOPT_SRC_ADDR_CONST_MODE BIT(0) + +enum edma3_address_mode { + INCR = 0, + FIFO = 1 +}; + +enum edma3_fifo_width { + W8BIT = 0, + W16BIT = 1, + W32BIT = 2, + W64BIT = 3, + W128BIT = 4, + W256BIT = 5 +}; + +enum edma3_sync_dimension { + ASYNC = 0, + ABSYNC = 1 +}; + +/* PaRAM slots are laid out like this */ +struct edma3_slot_layout { + u32 opt; + u32 src; + u32 a_b_cnt; + u32 dst; + u32 src_dst_bidx; + u32 link_bcntrld; + u32 src_dst_cidx; + u32 ccnt; +} __packed; + +/* + * Use this to assign trigger word number of edma3_slot_layout struct. + * trigger_word_name - is the exact name from edma3_slot_layout. + */ +#define EDMA3_TWORD(trigger_word_name)\ + (offsetof(struct edma3_slot_layout, trigger_word_name) / 4) + +struct edma3_slot_config { + u32 opt; + u32 src; + u32 dst; + int bcnt; + int acnt; + int ccnt; + int src_bidx; + int dst_bidx; + int src_cidx; + int dst_cidx; + int bcntrld; + int link; +}; + +struct edma3_channel_config { + int slot; + int chnum; + int complete_code; /* indicate pending complete interrupt */ + int trigger_slot_word; /* only used for qedma */ +}; + +void qedma3_start(u32 base, struct edma3_channel_config *cfg); +void qedma3_stop(u32 base, struct edma3_channel_config *cfg); +void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg); +int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg); +void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param); +void edma3_read_slot(u32 base, int slot, struct edma3_slot_layout *param); + +void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode, + enum edma3_fifo_width width); +void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx); +void edma3_set_dest_addr(u32 base, int slot, u32 dst); + +void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode, + enum edma3_fifo_width width); +void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx); +void edma3_set_src_addr(u32 base, int slot, u32 src); + +void edma3_set_transfer_params(u32 base, int slot, int acnt, + int bcnt, int ccnt, u16 bcnt_rld, + enum edma3_sync_dimension sync_mode); +void edma3_transfer(unsigned long edma3_base_addr, unsigned int + edma_slot_num, void *dst, void *src, size_t len); +void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num, + void *dst, u8 val, size_t len); + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/types.h b/roms/u-boot/arch/arm/include/asm/types.h new file mode 100644 index 000000000..900b2619a --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/types.h @@ -0,0 +1,45 @@ +#ifndef __ASM_ARM_TYPES_H +#define __ASM_ARM_TYPES_H + +#include + +typedef unsigned short umode_t; + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +#ifdef CONFIG_ARM64 +#define BITS_PER_LONG 64 +#else /* CONFIG_ARM64 */ +#define BITS_PER_LONG 32 +#endif /* CONFIG_ARM64 */ + +#ifdef CONFIG_PHYS_64BIT +typedef unsigned long long phys_addr_t; +typedef unsigned long long phys_size_t; +#else +/* DMA addresses are 32-bits wide */ +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; +#endif + +/* + * A dma_addr_t can hold any valid DMA address, i.e., any address returned + * by the DMA API. + * + * If the DMA API only uses 32-bit addresses, dma_addr_t need only be 32 + * bits wide. Bus addresses, e.g., PCI BARs, may be wider than 32 bits, + * but drivers do memory-mapped I/O to ioremapped kernel virtual addresses, + * so they don't care about the size of the actual bus addresses. + */ +#ifdef CONFIG_DMA_ADDR_T_64BIT +typedef unsigned long long dma_addr_t; +#else +typedef u32 dma_addr_t; +#endif + +#endif /* __KERNEL__ */ + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/u-boot-arm.h b/roms/u-boot/arch/arm/include/asm/u-boot-arm.h new file mode 100644 index 000000000..0b93cc48c --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/u-boot-arm.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + */ + +#ifndef _U_BOOT_ARM_H_ +#define _U_BOOT_ARM_H_ 1 + +#ifndef __ASSEMBLY__ + +/* for the following variables, see start.S */ +extern ulong IRQ_STACK_START; /* top of IRQ stack */ +extern ulong FIQ_STACK_START; /* top of FIQ stack */ +extern ulong _datarel_start_ofs; +extern ulong _datarelrolocal_start_ofs; +extern ulong _datarellocal_start_ofs; +extern ulong _datarelro_start_ofs; +extern ulong IRQ_STACK_START_IN; /* 8 bytes in IRQ stack */ + +void s_init(void); + +/* cpu/.../cpu.c */ +int cleanup_before_linux(void); + +/* Set up ARMv7 MMU, caches and TLBs */ +void cpu_init_cp15(void); + +/* cpu/.../arch/cpu.c */ +int arch_misc_init(void); + +/* board/.../... */ +int board_init(void); + +/* calls to c from vectors.S */ +struct pt_regs; + +void bad_mode(void); +void do_undefined_instruction(struct pt_regs *pt_regs); +void do_software_interrupt(struct pt_regs *pt_regs); +void do_prefetch_abort(struct pt_regs *pt_regs); +void do_data_abort(struct pt_regs *pt_regs); +void do_not_used(struct pt_regs *pt_regs); +#ifdef CONFIG_ARM64 +void do_fiq(struct pt_regs *pt_regs, unsigned int esr); +void do_irq(struct pt_regs *pt_regs, unsigned int esr); +#else +void do_fiq(struct pt_regs *pt_regs); +void do_irq(struct pt_regs *pt_regswq); +#endif + +void reset_misc(void); + +#endif /* __ASSEMBLY__ */ + +#endif /* _U_BOOT_ARM_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/u-boot.h b/roms/u-boot/arch/arm/include/asm/u-boot.h new file mode 100644 index 000000000..07528a46f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/u-boot.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef _U_BOOT_H_ +#define _U_BOOT_H_ 1 + +/* Use the generic board which requires a unified bd_info */ +#include +#include + +/* For image.h:image_check_target_arch() */ +#ifndef CONFIG_ARM64 +#define IH_ARCH_DEFAULT IH_ARCH_ARM +#else +#define IH_ARCH_DEFAULT IH_ARCH_ARM64 +#endif + +#endif /* _U_BOOT_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/unaligned.h b/roms/u-boot/arch/arm/include/asm/unaligned.h new file mode 100644 index 000000000..0a228fb8e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/unaligned.h @@ -0,0 +1,19 @@ +#ifndef _ASM_ARM_UNALIGNED_H +#define _ASM_ARM_UNALIGNED_H + +#include +#include +#include + +/* + * Select endianness + */ +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le +#else +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be +#endif + +#endif /* _ASM_ARM_UNALIGNED_H */ diff --git a/roms/u-boot/arch/arm/include/asm/unified.h b/roms/u-boot/arch/arm/include/asm/unified.h new file mode 100644 index 000000000..2fae54ebd --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/unified.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * include/asm-arm/unified.h - Unified Assembler Syntax helper macros + * + * Copyright (C) 2008 ARM Limited + */ + +#ifndef __ASM_UNIFIED_H +#define __ASM_UNIFIED_H + +#if defined(__ASSEMBLY__) && defined(CONFIG_ARM_ASM_UNIFIED) + .syntax unified +#endif + +#ifdef CONFIG_CPU_V7M +#define AR_CLASS(x...) +#define M_CLASS(x...) x +#else +#define AR_CLASS(x...) x +#define M_CLASS(x...) +#endif + +#ifdef CONFIG_THUMB2_KERNEL + +#if __GNUC__ < 4 +#error Thumb-2 kernel requires gcc >= 4 +#endif + +/* The CPSR bit describing the instruction set (Thumb) */ +#define PSR_ISETSTATE PSR_T_BIT + +#define ARM(x...) +#define THUMB(x...) x +#ifdef __ASSEMBLY__ +#define W(instr) instr.w +#else +#define WASM(instr) #instr ".w" +#endif + +#else /* !CONFIG_THUMB2_KERNEL */ + +/* The CPSR bit describing the instruction set (ARM) */ +#define PSR_ISETSTATE 0 + +#define ARM(x...) x +#define THUMB(x...) +#ifdef __ASSEMBLY__ +#define W(instr) instr +#else +#define WASM(instr) #instr +#endif + +#endif /* CONFIG_THUMB2_KERNEL */ + +#ifndef CONFIG_ARM_ASM_UNIFIED + +/* + * If the unified assembly syntax isn't used (in ARM mode), these + * macros expand to an empty string + */ +#ifdef __ASSEMBLY__ + .macro it, cond + .endm + .macro itt, cond + .endm + .macro ite, cond + .endm + .macro ittt, cond + .endm + .macro itte, cond + .endm + .macro itet, cond + .endm + .macro itee, cond + .endm + .macro itttt, cond + .endm + .macro ittte, cond + .endm + .macro ittet, cond + .endm + .macro ittee, cond + .endm + .macro itett, cond + .endm + .macro itete, cond + .endm + .macro iteet, cond + .endm + .macro iteee, cond + .endm +#else /* !__ASSEMBLY__ */ +__asm__( +" .macro it, cond\n" +" .endm\n" +" .macro itt, cond\n" +" .endm\n" +" .macro ite, cond\n" +" .endm\n" +" .macro ittt, cond\n" +" .endm\n" +" .macro itte, cond\n" +" .endm\n" +" .macro itet, cond\n" +" .endm\n" +" .macro itee, cond\n" +" .endm\n" +" .macro itttt, cond\n" +" .endm\n" +" .macro ittte, cond\n" +" .endm\n" +" .macro ittet, cond\n" +" .endm\n" +" .macro ittee, cond\n" +" .endm\n" +" .macro itett, cond\n" +" .endm\n" +" .macro itete, cond\n" +" .endm\n" +" .macro iteet, cond\n" +" .endm\n" +" .macro iteee, cond\n" +" .endm\n"); +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_ARM_ASM_UNIFIED */ + +#endif /* !__ASM_UNIFIED_H */ diff --git a/roms/u-boot/arch/arm/include/asm/utils.h b/roms/u-boot/arch/arm/include/asm/utils.h new file mode 100644 index 000000000..eee60c50e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/utils.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments, + * Aneesh V + */ +#ifndef _UTILS_H_ +#define _UTILS_H_ + +static inline s32 log_2_n_round_up(u32 n) +{ + s32 log2n = -1; + u32 temp = n; + + while (temp) { + log2n++; + temp >>= 1; + } + + if (n & (n - 1)) + return log2n + 1; /* not power of 2 - round up */ + else + return log2n; /* power of 2 */ +} + +static inline s32 log_2_n_round_down(u32 n) +{ + s32 log2n = -1; + u32 temp = n; + + while (temp) { + log2n++; + temp >>= 1; + } + + return log2n; +} + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/xen.h b/roms/u-boot/arch/arm/include/asm/xen.h new file mode 100644 index 000000000..8e2ee3d64 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/xen.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * (C) 2020 EPAM Systems Inc. + */ + +extern unsigned long rom_pointer[]; + diff --git a/roms/u-boot/arch/arm/include/asm/xen/hypercall.h b/roms/u-boot/arch/arm/include/asm/xen/hypercall.h new file mode 100644 index 000000000..a4fd07707 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/xen/hypercall.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * hypercall.h + * + * Linux-specific hypervisor handling. + * + * Stefano Stabellini , Citrix, 2012 + */ + +#ifndef _ASM_ARM_XEN_HYPERCALL_H +#define _ASM_ARM_XEN_HYPERCALL_H + +#include + +int HYPERVISOR_xen_version(int cmd, void *arg); +int HYPERVISOR_console_io(int cmd, int count, char *str); +int HYPERVISOR_grant_table_op(unsigned int cmd, void *uop, unsigned int count); +int HYPERVISOR_sched_op(int cmd, void *arg); +int HYPERVISOR_event_channel_op(int cmd, void *arg); +unsigned long HYPERVISOR_hvm_op(int op, void *arg); +int HYPERVISOR_memory_op(unsigned int cmd, void *arg); +#endif /* _ASM_ARM_XEN_HYPERCALL_H */ diff --git a/roms/u-boot/arch/arm/include/asm/xen/system.h b/roms/u-boot/arch/arm/include/asm/xen/system.h new file mode 100644 index 000000000..0fc8a7995 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/xen/system.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * (C) 2014 Karim Allah Ahmed + * (C) 2020, EPAM Systems Inc. + */ +#ifndef _ASM_ARM_XEN_SYSTEM_H +#define _ASM_ARM_XEN_SYSTEM_H + +#include +#include + +/* If *ptr == old, then store new there (and return new). + * Otherwise, return the old value. + * Atomic. + */ +#define synch_cmpxchg(ptr, old, new) \ +({ __typeof__(*ptr) stored = old; \ + __atomic_compare_exchange_n(ptr, &stored, new, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST) ? new : old; \ +}) + +/* As test_and_clear_bit, but using __ATOMIC_SEQ_CST */ +static inline int synch_test_and_clear_bit(int nr, volatile void *addr) +{ + u8 *byte = ((u8 *)addr) + (nr >> 3); + u8 bit = 1 << (nr & 7); + u8 orig; + + orig = __atomic_fetch_and(byte, ~bit, __ATOMIC_SEQ_CST); + + return (orig & bit) != 0; +} + +/* As test_and_set_bit, but using __ATOMIC_SEQ_CST */ +static inline int synch_test_and_set_bit(int nr, volatile void *base) +{ + u8 *byte = ((u8 *)base) + (nr >> 3); + u8 bit = 1 << (nr & 7); + u8 orig; + + orig = __atomic_fetch_or(byte, bit, __ATOMIC_SEQ_CST); + + return (orig & bit) != 0; +} + +/* As set_bit, but using __ATOMIC_SEQ_CST */ +static inline void synch_set_bit(int nr, volatile void *addr) +{ + synch_test_and_set_bit(nr, addr); +} + +/* As clear_bit, but using __ATOMIC_SEQ_CST */ +static inline void synch_clear_bit(int nr, volatile void *addr) +{ + synch_test_and_clear_bit(nr, addr); +} + +/* As test_bit, but with a following memory barrier. */ +//static inline int synch_test_bit(int nr, volatile void *addr) +static inline int synch_test_bit(int nr, const void *addr) +{ + int result; + + result = test_bit(nr, addr); + barrier(); + return result; +} + +#define xchg(ptr, v) __atomic_exchange_n(ptr, v, __ATOMIC_SEQ_CST) +#define xchg(ptr, v) __atomic_exchange_n(ptr, v, __ATOMIC_SEQ_CST) + +#define xen_mb() mb() +#define xen_rmb() rmb() +#define xen_wmb() wmb() + +#define to_phys(x) ((unsigned long)(x)) +#define to_virt(x) ((void *)(x)) + +#define PFN_UP(x) (unsigned long)(((x) + PAGE_SIZE - 1) >> PAGE_SHIFT) +#define PFN_DOWN(x) (unsigned long)((x) >> PAGE_SHIFT) +#define PFN_PHYS(x) ((unsigned long)(x) << PAGE_SHIFT) +#define PHYS_PFN(x) (unsigned long)((x) >> PAGE_SHIFT) + +#define virt_to_pfn(_virt) (PFN_DOWN(to_phys(_virt))) +#define virt_to_mfn(_virt) (PFN_DOWN(to_phys(_virt))) +#define mfn_to_virt(_mfn) (to_virt(PFN_PHYS(_mfn))) +#define pfn_to_virt(_pfn) (to_virt(PFN_PHYS(_pfn))) + +#endif diff --git a/roms/u-boot/arch/arm/include/debug/8250.S b/roms/u-boot/arch/arm/include/debug/8250.S new file mode 100644 index 000000000..5e37536af --- /dev/null +++ b/roms/u-boot/arch/arm/include/debug/8250.S @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * arch/arm/include/debug/8250.S + * + * Copyright (C) 1994-2013 Russell King + */ +#include + + .macro addruart, rp, rv, tmp + ldr \rp, =CONFIG_DEBUG_UART_PHYS + ldr \rv, =CONFIG_DEBUG_UART_VIRT + .endm + +#ifdef CONFIG_DEBUG_UART_8250_WORD + .macro store, rd, rx:vararg + str \rd, \rx + .endm + + .macro load, rd, rx:vararg + ldr \rd, \rx + .endm +#else + .macro store, rd, rx:vararg + strb \rd, \rx + .endm + + .macro load, rd, rx:vararg + ldrb \rd, \rx + .endm +#endif + +#define UART_SHIFT CONFIG_DEBUG_UART_8250_SHIFT + + .macro senduart,rd,rx + store \rd, [\rx, #UART_TX << UART_SHIFT] + .endm + + .macro busyuart,rd,rx +1002: load \rd, [\rx, #UART_LSR << UART_SHIFT] + and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE + teq \rd, #UART_LSR_TEMT | UART_LSR_THRE + bne 1002b + .endm + + .macro waituart,rd,rx +#ifdef CONFIG_DEBUG_UART_8250_FLOW_CONTROL +1001: load \rd, [\rx, #UART_MSR << UART_SHIFT] + tst \rd, #UART_MSR_CTS + beq 1001b +#endif + .endm -- cgit 1.2.3-korg