From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001 From: Angelos Mouzakitis Date: Tue, 10 Oct 2023 14:33:42 +0000 Subject: Add submodule dependency files Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec --- roms/u-boot/arch/arm/mach-at91/armv7/timer.c | 64 ++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 roms/u-boot/arch/arm/mach-at91/armv7/timer.c (limited to 'roms/u-boot/arch/arm/mach-at91/armv7/timer.c') diff --git a/roms/u-boot/arch/arm/mach-at91/armv7/timer.c b/roms/u-boot/arch/arm/mach-at91/armv7/timer.c new file mode 100644 index 000000000..1f54c5dca --- /dev/null +++ b/roms/u-boot/arch/arm/mach-at91/armv7/timer.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * (C) Copyright 2013 + * Bo Shen + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if !defined(CONFIG_AT91FAMILY) +# error You need to define CONFIG_AT91FAMILY in your board config! +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* + * We're using the SAMA5D3x PITC in 32 bit mode, by + * setting the 20 bit counter period to its maximum (0xfffff). + * (See the relevant data sheets to understand that this really works) + * + * We do also mimic the typical powerpc way of incrementing + * two 32 bit registers called tbl and tbu. + * + * Those registers increment at 1/16 the main clock rate. + */ + +#define TIMER_LOAD_VAL 0xfffff + +/* + * Use the PITC in full 32 bit incrementing mode + */ +int timer_init(void) +{ + at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; + + /* Enable PITC Clock */ + at91_periph_clk_enable(ATMEL_ID_PIT); + + /* Enable PITC */ + writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); + + gd->arch.timer_rate_hz = get_pit_clk_rate() / 16; + + return 0; +} + +/* + * Return the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return gd->arch.timer_rate_hz; +} -- cgit 1.2.3-korg