From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001 From: Angelos Mouzakitis Date: Tue, 10 Oct 2023 14:33:42 +0000 Subject: Add submodule dependency files Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec --- roms/u-boot/arch/arm/mach-snapdragon/Kconfig | 43 ++++++ roms/u-boot/arch/arm/mach-snapdragon/Makefile | 14 ++ .../arch/arm/mach-snapdragon/clock-apq8016.c | 113 ++++++++++++++++ .../arch/arm/mach-snapdragon/clock-apq8096.c | 95 +++++++++++++ .../arch/arm/mach-snapdragon/clock-snapdragon.c | 148 +++++++++++++++++++++ .../arch/arm/mach-snapdragon/clock-snapdragon.h | 45 +++++++ roms/u-boot/arch/arm/mach-snapdragon/dram.c | 100 ++++++++++++++ .../arch/arm/mach-snapdragon/include/mach/dram.h | 12 ++ .../arch/arm/mach-snapdragon/include/mach/gpio.h | 8 ++ .../arch/arm/mach-snapdragon/include/mach/misc.h | 13 ++ .../mach-snapdragon/include/mach/sysmap-apq8016.h | 39 ++++++ .../mach-snapdragon/include/mach/sysmap-apq8096.h | 37 ++++++ roms/u-boot/arch/arm/mach-snapdragon/misc.c | 53 ++++++++ .../arch/arm/mach-snapdragon/pinctrl-apq8016.c | 62 +++++++++ .../arch/arm/mach-snapdragon/pinctrl-apq8096.c | 56 ++++++++ .../arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 129 ++++++++++++++++++ .../arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 31 +++++ .../arch/arm/mach-snapdragon/sysmap-apq8016.c | 31 +++++ .../arch/arm/mach-snapdragon/sysmap-apq8096.c | 31 +++++ 19 files changed, 1060 insertions(+) create mode 100644 roms/u-boot/arch/arm/mach-snapdragon/Kconfig create mode 100644 roms/u-boot/arch/arm/mach-snapdragon/Makefile create mode 100644 roms/u-boot/arch/arm/mach-snapdragon/clock-apq8016.c create mode 100644 roms/u-boot/arch/arm/mach-snapdragon/clock-apq8096.c create mode 100644 roms/u-boot/arch/arm/mach-snapdragon/clock-snapdragon.c create mode 100644 roms/u-boot/arch/arm/mach-snapdragon/clock-snapdragon.h create mode 100644 roms/u-boot/arch/arm/mach-snapdragon/dram.c create mode 100644 roms/u-boot/arch/arm/mach-snapdragon/include/mach/dram.h create mode 100644 roms/u-boot/arch/arm/mach-snapdragon/include/mach/gpio.h create mode 100644 roms/u-boot/arch/arm/mach-snapdragon/include/mach/misc.h create mode 100644 roms/u-boot/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h create mode 100644 roms/u-boot/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h create mode 100644 roms/u-boot/arch/arm/mach-snapdragon/misc.c create mode 100644 roms/u-boot/arch/arm/mach-snapdragon/pinctrl-apq8016.c create mode 100644 roms/u-boot/arch/arm/mach-snapdragon/pinctrl-apq8096.c create mode 100644 roms/u-boot/arch/arm/mach-snapdragon/pinctrl-snapdragon.c create mode 100644 roms/u-boot/arch/arm/mach-snapdragon/pinctrl-snapdragon.h create mode 100644 roms/u-boot/arch/arm/mach-snapdragon/sysmap-apq8016.c create mode 100644 roms/u-boot/arch/arm/mach-snapdragon/sysmap-apq8096.c (limited to 'roms/u-boot/arch/arm/mach-snapdragon') diff --git a/roms/u-boot/arch/arm/mach-snapdragon/Kconfig b/roms/u-boot/arch/arm/mach-snapdragon/Kconfig new file mode 100644 index 000000000..e562d693c --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/Kconfig @@ -0,0 +1,43 @@ +if ARCH_SNAPDRAGON + +config SYS_SOC + default "snapdragon" + +config SYS_MALLOC_F_LEN + default 0x2000 + +config SPL_SYS_MALLOC_F_LEN + default 0x2000 + +choice + prompt "Snapdragon board select" + +config TARGET_DRAGONBOARD410C + bool "96Boards Dragonboard 410C" + select BOARD_LATE_INIT + help + Support for 96Boards Dragonboard 410C. This board complies with + 96Board Open Platform Specifications. Features: + - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306) + - 1GiB RAM + - 8GiB eMMC, uSD slot + - WiFi, Bluetooth and GPS module + - 2x Host, 1x Device USB port + - HDMI + - 20-pin low speed and 40-pin high speed expanders, 4 LED, 3 buttons + +config TARGET_DRAGONBOARD820C + bool "96Boards Dragonboard 820C" + help + Support for 96Boards Dragonboard 820C. This board complies with + 96Board Open Platform Specifications. Features: + - Qualcomm Snapdragon 820C SoC - APQ8096 (4xKyro CPU) + - 3GiB RAM + - 32GiB UFS drive + +endchoice + +source "board/qualcomm/dragonboard410c/Kconfig" +source "board/qualcomm/dragonboard820c/Kconfig" + +endif diff --git a/roms/u-boot/arch/arm/mach-snapdragon/Makefile b/roms/u-boot/arch/arm/mach-snapdragon/Makefile new file mode 100644 index 000000000..709919fce --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2015 Mateusz Kulikowski + +obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o +obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o +obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o +obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o +obj-y += misc.o +obj-y += clock-snapdragon.o +obj-y += dram.o +obj-y += pinctrl-snapdragon.o +obj-y += pinctrl-apq8016.o +obj-y += pinctrl-apq8096.o diff --git a/roms/u-boot/arch/arm/mach-snapdragon/clock-apq8016.c b/roms/u-boot/arch/arm/mach-snapdragon/clock-apq8016.c new file mode 100644 index 000000000..6e4a0ccb9 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/clock-apq8016.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm APQ8016 + * + * (C) Copyright 2015 Mateusz Kulikowski + * + * Based on Little Kernel driver, simplified + */ + +#include +#include +#include +#include +#include +#include +#include "clock-snapdragon.h" + +/* GPLL0 clock control registers */ +#define GPLL0_STATUS_ACTIVE BIT(17) + +static const struct bcr_regs sdc_regs[] = { + { + .cfg_rcgr = SDCC_CFG_RCGR(1), + .cmd_rcgr = SDCC_CMD_RCGR(1), + .M = SDCC_M(1), + .N = SDCC_N(1), + .D = SDCC_D(1), + }, + { + .cfg_rcgr = SDCC_CFG_RCGR(2), + .cmd_rcgr = SDCC_CMD_RCGR(2), + .M = SDCC_M(2), + .N = SDCC_N(2), + .D = SDCC_D(2), + } +}; + +static struct pll_vote_clk gpll0_vote_clk = { + .status = GPLL0_STATUS, + .status_bit = GPLL0_STATUS_ACTIVE, + .ena_vote = APCS_GPLL_ENA_VOTE, + .vote_bit = BIT(0), +}; + +static struct vote_clk gcc_blsp1_ahb_clk = { + .cbcr_reg = BLSP1_AHB_CBCR, + .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE, + .vote_bit = BIT(10), +}; + +/* SDHCI */ +static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) +{ + int div = 8; /* 100MHz default */ + + if (rate == 200000000) + div = 4; + + clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot)); + /* 800Mhz/div, gpll0 */ + clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0, + CFG_CLK_SRC_GPLL0); + clk_enable_gpll0(priv->base, &gpll0_vote_clk); + clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot)); + + return rate; +} + +static const struct bcr_regs uart2_regs = { + .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR, + .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR, + .M = BLSP1_UART2_APPS_M, + .N = BLSP1_UART2_APPS_N, + .D = BLSP1_UART2_APPS_D, +}; + +/* UART: 115200 */ +static int clk_init_uart(struct msm_clk_priv *priv) +{ + /* Enable AHB clock */ + clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk); + + /* 7372800 uart block clock @ GPLL0 */ + clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625, + CFG_CLK_SRC_GPLL0); + + /* Vote for gpll0 clock */ + clk_enable_gpll0(priv->base, &gpll0_vote_clk); + + /* Enable core clk */ + clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR); + + return 0; +} + +ulong msm_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case 0: /* SDC1 */ + return clk_init_sdc(priv, 0, rate); + break; + case 1: /* SDC2 */ + return clk_init_sdc(priv, 1, rate); + break; + case 4: /* UART2 */ + return clk_init_uart(priv); + break; + default: + return 0; + } +} diff --git a/roms/u-boot/arch/arm/mach-snapdragon/clock-apq8096.c b/roms/u-boot/arch/arm/mach-snapdragon/clock-apq8096.c new file mode 100644 index 000000000..e5011be8f --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/clock-apq8096.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm APQ8096 + * + * (C) Copyright 2017 Jorge Ramirez Ortiz + * + * Based on Little Kernel driver, simplified + */ + +#include +#include +#include +#include +#include +#include +#include "clock-snapdragon.h" + +/* GPLL0 clock control registers */ +#define GPLL0_STATUS_ACTIVE BIT(30) +#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0) + +static const struct bcr_regs sdc_regs = { + .cfg_rcgr = SDCC2_CFG_RCGR, + .cmd_rcgr = SDCC2_CMD_RCGR, + .M = SDCC2_M, + .N = SDCC2_N, + .D = SDCC2_D, +}; + +static const struct pll_vote_clk gpll0_vote_clk = { + .status = GPLL0_STATUS, + .status_bit = GPLL0_STATUS_ACTIVE, + .ena_vote = APCS_GPLL_ENA_VOTE, + .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0, +}; + +static struct vote_clk gcc_blsp2_ahb_clk = { + .cbcr_reg = BLSP2_AHB_CBCR, + .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE, + .vote_bit = BIT(15), +}; + +static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) +{ + int div = 3; + + clk_enable_cbc(priv->base + SDCC2_AHB_CBCR); + clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0, + CFG_CLK_SRC_GPLL0); + clk_enable_gpll0(priv->base, &gpll0_vote_clk); + clk_enable_cbc(priv->base + SDCC2_APPS_CBCR); + + return rate; +} + +static const struct bcr_regs uart2_regs = { + .cfg_rcgr = BLSP2_UART2_APPS_CFG_RCGR, + .cmd_rcgr = BLSP2_UART2_APPS_CMD_RCGR, + .M = BLSP2_UART2_APPS_M, + .N = BLSP2_UART2_APPS_N, + .D = BLSP2_UART2_APPS_D, +}; + +static int clk_init_uart(struct msm_clk_priv *priv) +{ + /* Enable AHB clock */ + clk_enable_vote_clk(priv->base, &gcc_blsp2_ahb_clk); + + /* 7372800 uart block clock @ GPLL0 */ + clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625, + CFG_CLK_SRC_GPLL0); + + /* Vote for gpll0 clock */ + clk_enable_gpll0(priv->base, &gpll0_vote_clk); + + /* Enable core clk */ + clk_enable_cbc(priv->base + BLSP2_UART2_APPS_CBCR); + + return 0; +} + +ulong msm_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case 0: /* SDC1 */ + return clk_init_sdc(priv, rate); + break; + case 4: /*UART2*/ + return clk_init_uart(priv); + default: + return 0; + } +} diff --git a/roms/u-boot/arch/arm/mach-snapdragon/clock-snapdragon.c b/roms/u-boot/arch/arm/mach-snapdragon/clock-snapdragon.c new file mode 100644 index 000000000..fbe0b5212 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm APQ8016, APQ8096 + * + * (C) Copyright 2015 Mateusz Kulikowski + * + * Based on Little Kernel driver, simplified + */ + +#include +#include +#include +#include +#include +#include +#include "clock-snapdragon.h" + +/* CBCR register fields */ +#define CBCR_BRANCH_ENABLE_BIT BIT(0) +#define CBCR_BRANCH_OFF_BIT BIT(31) + +extern ulong msm_set_rate(struct clk *clk, ulong rate); + +/* Enable clock controlled by CBC soft macro */ +void clk_enable_cbc(phys_addr_t cbcr) +{ + setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT); + + while (readl(cbcr) & CBCR_BRANCH_OFF_BIT) + ; +} + +void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0) +{ + if (readl(base + gpll0->status) & gpll0->status_bit) + return; /* clock already enabled */ + + setbits_le32(base + gpll0->ena_vote, gpll0->vote_bit); + + while ((readl(base + gpll0->status) & gpll0->status_bit) == 0) + ; +} + +#define BRANCH_ON_VAL (0) +#define BRANCH_NOC_FSM_ON_VAL BIT(29) +#define BRANCH_CHECK_MASK GENMASK(31, 28) + +void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk) +{ + u32 val; + + setbits_le32(base + vclk->ena_vote, vclk->vote_bit); + do { + val = readl(base + vclk->cbcr_reg); + val &= BRANCH_CHECK_MASK; + } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL)); +} + +#define APPS_CMD_RGCR_UPDATE BIT(0) + +/* Update clock command via CMD_RGCR */ +void clk_bcr_update(phys_addr_t apps_cmd_rgcr) +{ + setbits_le32(apps_cmd_rgcr, APPS_CMD_RGCR_UPDATE); + + /* Wait for frequency to be updated. */ + while (readl(apps_cmd_rgcr) & APPS_CMD_RGCR_UPDATE) + ; +} + +#define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */ + +#define CFG_MASK 0x3FFF + +#define CFG_DIVIDER_MASK 0x1F + +/* root set rate for clocks with half integer and MND divider */ +void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, + int div, int m, int n, int source) +{ + u32 cfg; + /* M value for MND divider. */ + u32 m_val = m; + /* NOT(N-M) value for MND divider. */ + u32 n_val = ~((n) - (m)) * !!(n); + /* NOT 2D value for MND divider. */ + u32 d_val = ~(n); + + /* Program MND values */ + writel(m_val, base + regs->M); + writel(n_val, base + regs->N); + writel(d_val, base + regs->D); + + /* setup src select and divider */ + cfg = readl(base + regs->cfg_rcgr); + cfg &= ~CFG_MASK; + cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */ + + /* Set the divider; HW permits fraction dividers (+0.5), but + for simplicity, we will support integers only */ + if (div) + cfg |= (2 * div - 1) & CFG_DIVIDER_MASK; + + if (n_val) + cfg |= CFG_MODE_DUAL_EDGE; + + writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */ + + /* Inform h/w to start using the new config. */ + clk_bcr_update(base + regs->cmd_rcgr); +} + +static int msm_clk_probe(struct udevice *dev) +{ + struct msm_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + return 0; +} + +static ulong msm_clk_set_rate(struct clk *clk, ulong rate) +{ + return msm_set_rate(clk, rate); +} + +static struct clk_ops msm_clk_ops = { + .set_rate = msm_clk_set_rate, +}; + +static const struct udevice_id msm_clk_ids[] = { + { .compatible = "qcom,gcc-msm8916" }, + { .compatible = "qcom,gcc-apq8016" }, + { .compatible = "qcom,gcc-msm8996" }, + { .compatible = "qcom,gcc-apq8096" }, + { } +}; + +U_BOOT_DRIVER(clk_msm) = { + .name = "clk_msm", + .id = UCLASS_CLK, + .of_match = msm_clk_ids, + .ops = &msm_clk_ops, + .priv_auto = sizeof(struct msm_clk_priv), + .probe = msm_clk_probe, +}; diff --git a/roms/u-boot/arch/arm/mach-snapdragon/clock-snapdragon.h b/roms/u-boot/arch/arm/mach-snapdragon/clock-snapdragon.h new file mode 100644 index 000000000..58fab40a2 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/clock-snapdragon.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Qualcomm APQ8016, APQ8096 + * + * (C) Copyright 2017 Jorge Ramirez-Ortiz + */ +#ifndef _CLOCK_SNAPDRAGON_H +#define _CLOCK_SNAPDRAGON_H + +#define CFG_CLK_SRC_CXO (0 << 8) +#define CFG_CLK_SRC_GPLL0 (1 << 8) +#define CFG_CLK_SRC_MASK (7 << 8) + +struct pll_vote_clk { + uintptr_t status; + int status_bit; + uintptr_t ena_vote; + int vote_bit; +}; + +struct vote_clk { + uintptr_t cbcr_reg; + uintptr_t ena_vote; + int vote_bit; +}; +struct bcr_regs { + uintptr_t cfg_rcgr; + uintptr_t cmd_rcgr; + uintptr_t M; + uintptr_t N; + uintptr_t D; +}; + +struct msm_clk_priv { + phys_addr_t base; +}; + +void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0); +void clk_bcr_update(phys_addr_t apps_cmd_rgcr); +void clk_enable_cbc(phys_addr_t cbcr); +void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk); +void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, + int div, int m, int n, int source); + +#endif diff --git a/roms/u-boot/arch/arm/mach-snapdragon/dram.c b/roms/u-boot/arch/arm/mach-snapdragon/dram.c new file mode 100644 index 000000000..2a161be13 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/dram.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Onboard memory detection for Snapdragon boards + * + * (C) Copyright 2018 Ramon Fried + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SMEM_USABLE_RAM_PARTITION_TABLE 402 +#define RAM_PART_NAME_LENGTH 16 +#define RAM_NUM_PART_ENTRIES 32 +#define CATEGORY_SDRAM 0x0E +#define TYPE_SYSMEM 0x01 + +struct smem_ram_ptable_hdr { + u32 magic[2]; + u32 version; + u32 reserved; + u32 len; +} __attribute__ ((__packed__)); + +struct smem_ram_ptn { + char name[RAM_PART_NAME_LENGTH]; + u64 start; + u64 size; + u32 attr; + u32 category; + u32 domain; + u32 type; + u32 num_partitions; + u32 reserved[3]; +} __attribute__ ((__packed__)); + +struct smem_ram_ptable { + struct smem_ram_ptable_hdr hdr; + u32 reserved; /* Added for 8 bytes alignment of header */ + struct smem_ram_ptn parts[RAM_NUM_PART_ENTRIES]; +} __attribute__ ((__packed__)); + +#ifndef MEMORY_BANKS_MAX +#define MEMORY_BANKS_MAX 4 +#endif + +int msm_fixup_memory(void *blob) +{ + u64 bank_start[MEMORY_BANKS_MAX]; + u64 bank_size[MEMORY_BANKS_MAX]; + size_t size; + int i; + int count = 0; + struct udevice *smem; + int ret; + struct smem_ram_ptable *ram_ptable; + struct smem_ram_ptn *p; + + ret = uclass_get_device_by_name(UCLASS_SMEM, "smem", &smem); + if (ret < 0) { + printf("Failed to find SMEM node. Check device tree\n"); + return 0; + } + + ram_ptable = smem_get(smem, -1, SMEM_USABLE_RAM_PARTITION_TABLE, &size); + + if (!ram_ptable) { + printf("Failed to find SMEM partition.\n"); + return -ENODEV; + } + + /* Check validy of RAM */ + for (i = 0; i < RAM_NUM_PART_ENTRIES; i++) { + p = &ram_ptable->parts[i]; + if (p->category == CATEGORY_SDRAM && p->type == TYPE_SYSMEM) { + bank_start[count] = p->start; + bank_size[count] = p->size; + debug("Detected memory bank %u: start: 0x%llx size: 0x%llx\n", + count, p->start, p->size); + count++; + } + } + + if (!count) { + printf("Failed to detect any memory bank\n"); + return -ENODEV; + } + + ret = fdt_fixup_memory_banks(blob, bank_start, bank_size, count); + if (ret) + return ret; + + return 0; +} + diff --git a/roms/u-boot/arch/arm/mach-snapdragon/include/mach/dram.h b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/dram.h new file mode 100644 index 000000000..0a9eedda4 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/dram.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Snapdragon DRAM + * Copyright (C) 2018 Ramon Fried + */ + +#ifndef DRAM_H +#define DRAM_H + +int msm_fixup_memory(void *blob); + +#endif diff --git a/roms/u-boot/arch/arm/mach-snapdragon/include/mach/gpio.h b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/gpio.h new file mode 100644 index 000000000..bbc2bc161 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Empty gpio.h + * + * This file must stay as arch/arm/include/asm/gpio.h requires it. + * + * (C) Copyright 2015 Mateusz Kulikowski + */ diff --git a/roms/u-boot/arch/arm/mach-snapdragon/include/mach/misc.h b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/misc.h new file mode 100644 index 000000000..c60e3e472 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/misc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Snapdragon DRAM + * Copyright (C) 2018 Ramon Fried + */ + +#ifndef MISC_H +#define MISC_H + +u32 msm_board_serial(void); +void msm_generate_mac_addr(u8 *mac); + +#endif diff --git a/roms/u-boot/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h new file mode 100644 index 000000000..520e2e6bd --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Qualcomm APQ8916 sysmap + * + * (C) Copyright 2015 Mateusz Kulikowski + */ +#ifndef _MACH_SYSMAP_APQ8016_H +#define _MACH_SYSMAP_APQ8016_H + +#define GICD_BASE (0x0b000000) +#define GICC_BASE (0x0a20c000) + +/* Clocks: (from CLK_CTL_BASE) */ +#define GPLL0_STATUS (0x2101C) +#define APCS_GPLL_ENA_VOTE (0x45000) +#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) + +#define SDCC_BCR(n) ((n * 0x1000) + 0x41000) +#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004) +#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008) +#define SDCC_M(n) ((n * 0x1000) + 0x4100C) +#define SDCC_N(n) ((n * 0x1000) + 0x41010) +#define SDCC_D(n) ((n * 0x1000) + 0x41014) +#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018) +#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C) + +/* BLSP1 AHB clock (root clock for BLSP) */ +#define BLSP1_AHB_CBCR 0x1008 + +/* Uart clock control registers */ +#define BLSP1_UART2_BCR (0x3028) +#define BLSP1_UART2_APPS_CBCR (0x302C) +#define BLSP1_UART2_APPS_CMD_RCGR (0x3034) +#define BLSP1_UART2_APPS_CFG_RCGR (0x3038) +#define BLSP1_UART2_APPS_M (0x303C) +#define BLSP1_UART2_APPS_N (0x3040) +#define BLSP1_UART2_APPS_D (0x3044) + +#endif diff --git a/roms/u-boot/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h new file mode 100644 index 000000000..36a902bd9 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Qualcomm APQ8096 sysmap + * + * (C) Copyright 2017 Jorge Ramirez-Ortiz + */ +#ifndef _MACH_SYSMAP_APQ8096_H +#define _MACH_SYSMAP_APQ8096_H + +#define TLMM_BASE_ADDR (0x1010000) + +/* Strength (sdc1) */ +#define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000) + +/* Clocks: (from CLK_CTL_BASE) */ +#define GPLL0_STATUS (0x0000) +#define APCS_GPLL_ENA_VOTE (0x52000) +#define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004) + +#define SDCC2_BCR (0x14000) /* block reset */ +#define SDCC2_APPS_CBCR (0x14004) /* branch control */ +#define SDCC2_AHB_CBCR (0x14008) +#define SDCC2_CMD_RCGR (0x14010) +#define SDCC2_CFG_RCGR (0x14014) +#define SDCC2_M (0x14018) +#define SDCC2_N (0x1401C) +#define SDCC2_D (0x14020) + +#define BLSP2_AHB_CBCR (0x25004) +#define BLSP2_UART2_APPS_CBCR (0x29004) +#define BLSP2_UART2_APPS_CMD_RCGR (0x2900C) +#define BLSP2_UART2_APPS_CFG_RCGR (0x29010) +#define BLSP2_UART2_APPS_M (0x29014) +#define BLSP2_UART2_APPS_N (0x29018) +#define BLSP2_UART2_APPS_D (0x2901C) + +#endif diff --git a/roms/u-boot/arch/arm/mach-snapdragon/misc.c b/roms/u-boot/arch/arm/mach-snapdragon/misc.c new file mode 100644 index 000000000..aaa561c2c --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/misc.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Miscellaneous Snapdragon functionality + * + * (C) Copyright 2018 Ramon Fried + * + */ + +#include +#include +#include + +/* UNSTUFF_BITS macro taken from Linux Kernel: drivers/mmc/core/sd.c */ +#define UNSTUFF_BITS(resp, start, size) \ + ({ \ + const int __size = size; \ + const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \ + const int __off = 3 - ((start) / 32); \ + const int __shft = (start) & 31; \ + u32 __res; \ + \ + __res = resp[__off] >> __shft; \ + if (__size + __shft > 32) \ + __res |= resp[__off - 1] << ((32 - __shft) % 32); \ + __res & __mask; \ + }) + +u32 msm_board_serial(void) +{ + struct mmc *mmc_dev; + + mmc_dev = find_mmc_device(0); + if (!mmc_dev) + return 0; + + return UNSTUFF_BITS(mmc_dev->cid, 16, 32); +} + +void msm_generate_mac_addr(u8 *mac) +{ + int i; + char sn[9]; + + snprintf(sn, 9, "%08x", msm_board_serial()); + + /* fill in the mac with serialno, use locally adminstrated pool */ + mac[0] = 0x02; + mac[1] = 00; + for (i = 3; i >= 0; i--) { + mac[i + 2] = simple_strtoul(&sn[2 * i], NULL, 16); + sn[2 * i] = 0; + } +} diff --git a/roms/u-boot/arch/arm/mach-snapdragon/pinctrl-apq8016.c b/roms/u-boot/arch/arm/mach-snapdragon/pinctrl-apq8016.c new file mode 100644 index 000000000..1042b564c --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/pinctrl-apq8016.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm APQ8016 pinctrl + * + * (C) Copyright 2018 Ramon Fried + * + */ + +#include "pinctrl-snapdragon.h" +#include + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN]; +static const char * const msm_pinctrl_pins[] = { + "SDC1_CLK", + "SDC1_CMD", + "SDC1_DATA", + "SDC2_CLK", + "SDC2_CMD", + "SDC2_DATA", + "QDSD_CLK", + "QDSD_CMD", + "QDSD_DATA0", + "QDSD_DATA1", + "QDSD_DATA2", + "QDSD_DATA3", +}; + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"blsp1_uart", 2}, +}; + +static const char *apq8016_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *apq8016_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + if (selector < 122) { + snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); + return pin_name; + } else { + return msm_pinctrl_pins[selector - 122]; + } +} + +static unsigned int apq8016_get_function_mux(unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +struct msm_pinctrl_data apq8016_data = { + .pin_count = 133, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = apq8016_get_function_name, + .get_function_mux = apq8016_get_function_mux, + .get_pin_name = apq8016_get_pin_name, +}; + diff --git a/roms/u-boot/arch/arm/mach-snapdragon/pinctrl-apq8096.c b/roms/u-boot/arch/arm/mach-snapdragon/pinctrl-apq8096.c new file mode 100644 index 000000000..20a71c319 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/pinctrl-apq8096.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm APQ8096 pinctrl + * + * (C) Copyright 2019 Ramon Fried + * + */ + +#include "pinctrl-snapdragon.h" +#include + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN]; +static const char * const msm_pinctrl_pins[] = { + "SDC1_CLK", + "SDC1_CMD", + "SDC1_DATA", + "SDC2_CLK", + "SDC2_CMD", + "SDC2_DATA", + "SDC1_RCLK", +}; + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"blsp_uart8", 2}, +}; + +static const char *apq8096_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *apq8096_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + if (selector < 150) { + snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); + return pin_name; + } else { + return msm_pinctrl_pins[selector - 150]; + } +} + +static unsigned int apq8096_get_function_mux(unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +struct msm_pinctrl_data apq8096_data = { + .pin_count = 157, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = apq8096_get_function_name, + .get_function_mux = apq8096_get_function_mux, + .get_pin_name = apq8096_get_pin_name, +}; diff --git a/roms/u-boot/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/roms/u-boot/arch/arm/mach-snapdragon/pinctrl-snapdragon.c new file mode 100644 index 000000000..e6b87c357 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * TLMM driver for Qualcomm APQ8016, APQ8096 + * + * (C) Copyright 2018 Ramon Fried + * + */ + +#include +#include +#include +#include +#include +#include +#include "pinctrl-snapdragon.h" + +struct msm_pinctrl_priv { + phys_addr_t base; + struct msm_pinctrl_data *data; +}; + +#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000) +#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) +#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) +#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) +#define TLMM_GPIO_DISABLE BIT(9) + +static const struct pinconf_param msm_conf_params[] = { + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 }, + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, +}; + +static int msm_get_functions_count(struct udevice *dev) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->data->functions_count; +} + +static int msm_get_pins_count(struct udevice *dev) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->data->pin_count; +} + +static const char *msm_get_function_name(struct udevice *dev, + unsigned int selector) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->data->get_function_name(dev, selector); +} + +static int msm_pinctrl_probe(struct udevice *dev) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + priv->data = (struct msm_pinctrl_data *)dev->driver_data; + + return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0; +} + +static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->data->get_pin_name(dev, selector); +} + +static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, + unsigned int func_selector) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, + priv->data->get_function_mux(func_selector) << 2); + return 0; +} + +static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, + unsigned int param, unsigned int argument) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + switch (param) { + case PIN_CONFIG_DRIVE_STRENGTH: + clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + TLMM_DRV_STRENGTH_MASK, argument << 6); + break; + case PIN_CONFIG_BIAS_DISABLE: + clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + TLMM_GPIO_PULL_MASK); + break; + default: + return 0; + } + + return 0; +} + +static struct pinctrl_ops msm_pinctrl_ops = { + .get_pins_count = msm_get_pins_count, + .get_pin_name = msm_get_pin_name, + .set_state = pinctrl_generic_set_state, + .pinmux_set = msm_pinmux_set, + .pinconf_num_params = ARRAY_SIZE(msm_conf_params), + .pinconf_params = msm_conf_params, + .pinconf_set = msm_pinconf_set, + .get_functions_count = msm_get_functions_count, + .get_function_name = msm_get_function_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data }, + { .compatible = "qcom,tlmm-apq8096", .data = (ulong)&apq8096_data }, + { } +}; + +U_BOOT_DRIVER(pinctrl_snapdraon) = { + .name = "pinctrl_msm", + .id = UCLASS_PINCTRL, + .of_match = msm_pinctrl_ids, + .priv_auto = sizeof(struct msm_pinctrl_priv), + .ops = &msm_pinctrl_ops, + .probe = msm_pinctrl_probe, +}; diff --git a/roms/u-boot/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/roms/u-boot/arch/arm/mach-snapdragon/pinctrl-snapdragon.h new file mode 100644 index 000000000..61d466f4d --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/pinctrl-snapdragon.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Qualcomm Pin control + * + * (C) Copyright 2018 Ramon Fried + * + */ +#ifndef _PINCTRL_SNAPDRAGON_H +#define _PINCTRL_SNAPDRAGON_H + +struct udevice; + +struct msm_pinctrl_data { + int pin_count; + int functions_count; + const char *(*get_function_name)(struct udevice *dev, + unsigned int selector); + unsigned int (*get_function_mux)(unsigned int selector); + const char *(*get_pin_name)(struct udevice *dev, + unsigned int selector); +}; + +struct pinctrl_function { + const char *name; + int val; +}; + +extern struct msm_pinctrl_data apq8016_data; +extern struct msm_pinctrl_data apq8096_data; + +#endif diff --git a/roms/u-boot/arch/arm/mach-snapdragon/sysmap-apq8016.c b/roms/u-boot/arch/arm/mach-snapdragon/sysmap-apq8016.c new file mode 100644 index 000000000..ffa3f9aa3 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/sysmap-apq8016.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm APQ8016 memory map + * + * (C) Copyright 2016 Mateusz Kulikowski + */ + +#include +#include + +static struct mm_region apq8016_mem_map[] = { + { + .virt = 0x0UL, /* Peripheral block */ + .phys = 0x0UL, /* Peripheral block */ + .size = 0x8000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x80000000UL, /* DDR */ + .phys = 0x80000000UL, /* DDR */ + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = apq8016_mem_map; diff --git a/roms/u-boot/arch/arm/mach-snapdragon/sysmap-apq8096.c b/roms/u-boot/arch/arm/mach-snapdragon/sysmap-apq8096.c new file mode 100644 index 000000000..0614f8308 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/sysmap-apq8096.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm APQ8096 memory map + * + * (C) Copyright 2017 Jorge Ramirez Ortiz + */ + +#include +#include + +static struct mm_region apq8096_mem_map[] = { + { + .virt = 0x0UL, /* Peripheral block */ + .phys = 0x0UL, /* Peripheral block */ + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x80000000UL, /* DDR */ + .phys = 0x80000000UL, /* DDR */ + .size = 0xC0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = apq8096_mem_map; -- cgit 1.2.3-korg