From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001
From: Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com>
Date: Tue, 10 Oct 2023 14:33:42 +0000
Subject: Add submodule dependency files
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
---
roms/u-boot/arch/arm/mach-tegra/gpu.c | 58 +++++++++++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 roms/u-boot/arch/arm/mach-tegra/gpu.c
(limited to 'roms/u-boot/arch/arm/mach-tegra/gpu.c')
diff --git a/roms/u-boot/arch/arm/mach-tegra/gpu.c b/roms/u-boot/arch/arm/mach-tegra/gpu.c
new file mode 100644
index 000000000..13ffade04
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-tegra/gpu.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
+ */
+
+/* Tegra vpr routines */
+
+#include <common.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/mc.h>
+#include <asm/arch-tegra/ap.h>
+
+#include <fdt_support.h>
+
+static bool _configured;
+
+void tegra_gpu_config(void)
+{
+ struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
+
+#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
+ if (!tegra_cpu_is_non_secure())
+#endif
+ {
+ /* Turn VPR off */
+ writel(0, &mc->mc_video_protect_size_mb);
+ writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
+ &mc->mc_video_protect_reg_ctrl);
+ /* read back to ensure the write went through */
+ readl(&mc->mc_video_protect_reg_ctrl);
+ }
+
+ debug("configured VPR\n");
+
+ _configured = true;
+}
+
+#if defined(CONFIG_OF_LIBFDT)
+
+int tegra_gpu_enable_node(void *blob, const char *compat)
+{
+ int offset;
+
+ if (!_configured)
+ return 0;
+
+ offset = fdt_node_offset_by_compatible(blob, -1, compat);
+ while (offset != -FDT_ERR_NOTFOUND) {
+ fdt_status_okay(blob, offset);
+ offset = fdt_node_offset_by_compatible(blob, offset, compat);
+ }
+
+ return 0;
+}
+
+#endif
--
cgit