From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001
From: Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com>
Date: Tue, 10 Oct 2023 14:33:42 +0000
Subject: Add submodule dependency files
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
---
roms/u-boot/arch/arm/mach-uniphier/dram/Makefile | 20 +
.../arch/arm/mach-uniphier/dram/cmd_ddrmphy.c | 346 +++++++++++
.../arch/arm/mach-uniphier/dram/cmd_ddrphy.c | 312 ++++++++++
.../arch/arm/mach-uniphier/dram/ddrmphy-regs.h | 145 +++++
.../arch/arm/mach-uniphier/dram/ddrphy-init.h | 16 +
.../arch/arm/mach-uniphier/dram/ddrphy-ld4.c | 78 +++
.../arch/arm/mach-uniphier/dram/ddrphy-regs.h | 143 +++++
.../arch/arm/mach-uniphier/dram/ddrphy-training.c | 146 +++++
roms/u-boot/arch/arm/mach-uniphier/dram/umc-ld4.c | 191 ++++++
roms/u-boot/arch/arm/mach-uniphier/dram/umc-pro4.c | 186 ++++++
roms/u-boot/arch/arm/mach-uniphier/dram/umc-pro5.c | 11 +
roms/u-boot/arch/arm/mach-uniphier/dram/umc-pxs2.c | 643 +++++++++++++++++++++
roms/u-boot/arch/arm/mach-uniphier/dram/umc-regs.h | 106 ++++
roms/u-boot/arch/arm/mach-uniphier/dram/umc-sld8.c | 194 +++++++
14 files changed, 2537 insertions(+)
create mode 100644 roms/u-boot/arch/arm/mach-uniphier/dram/Makefile
create mode 100644 roms/u-boot/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c
create mode 100644 roms/u-boot/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
create mode 100644 roms/u-boot/arch/arm/mach-uniphier/dram/ddrmphy-regs.h
create mode 100644 roms/u-boot/arch/arm/mach-uniphier/dram/ddrphy-init.h
create mode 100644 roms/u-boot/arch/arm/mach-uniphier/dram/ddrphy-ld4.c
create mode 100644 roms/u-boot/arch/arm/mach-uniphier/dram/ddrphy-regs.h
create mode 100644 roms/u-boot/arch/arm/mach-uniphier/dram/ddrphy-training.c
create mode 100644 roms/u-boot/arch/arm/mach-uniphier/dram/umc-ld4.c
create mode 100644 roms/u-boot/arch/arm/mach-uniphier/dram/umc-pro4.c
create mode 100644 roms/u-boot/arch/arm/mach-uniphier/dram/umc-pro5.c
create mode 100644 roms/u-boot/arch/arm/mach-uniphier/dram/umc-pxs2.c
create mode 100644 roms/u-boot/arch/arm/mach-uniphier/dram/umc-regs.h
create mode 100644 roms/u-boot/arch/arm/mach-uniphier/dram/umc-sld8.c
(limited to 'roms/u-boot/arch/arm/mach-uniphier/dram')
diff --git a/roms/u-boot/arch/arm/mach-uniphier/dram/Makefile b/roms/u-boot/arch/arm/mach-uniphier/dram/Makefile
new file mode 100644
index 000000000..7d11315d0
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-uniphier/dram/Makefile
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+ifdef CONFIG_SPL_BUILD
+
+obj-$(CONFIG_ARCH_UNIPHIER_LD4) += umc-ld4.o \
+ ddrphy-training.o ddrphy-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += umc-pro4.o \
+ ddrphy-training.o ddrphy-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += umc-sld8.o \
+ ddrphy-training.o ddrphy-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += umc-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o
+
+else
+
+obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
+obj-$(CONFIG_CMD_DDRMPHY_DUMP) += cmd_ddrmphy.o
+
+endif
diff --git a/roms/u-boot/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c b/roms/u-boot/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c
new file mode 100644
index 000000000..629f8b90c
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c
@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <command.h>
+#include <stdio.h>
+#include <linux/io.h>
+#include <linux/printk.h>
+#include <linux/sizes.h>
+
+#include "../soc-info.h"
+#include "ddrmphy-regs.h"
+
+/* Select either decimal or hexadecimal */
+#if 1
+#define PRINTF_FORMAT "%2d"
+#else
+#define PRINTF_FORMAT "%02x"
+#endif
+/* field separator */
+#define FS " "
+
+#define ptr_to_uint(p) ((unsigned int)(unsigned long)(p))
+
+#define UNIPHIER_MAX_NR_DDRMPHY 3
+
+struct uniphier_ddrmphy_param {
+ unsigned int soc_id;
+ unsigned int nr_phy;
+ struct {
+ resource_size_t base;
+ unsigned int nr_zq;
+ unsigned int nr_dx;
+ } phy[UNIPHIER_MAX_NR_DDRMPHY];
+};
+
+static const struct uniphier_ddrmphy_param uniphier_ddrmphy_param[] = {
+ {
+ .soc_id = UNIPHIER_PXS2_ID,
+ .nr_phy = 3,
+ .phy = {
+ { .base = 0x5b830000, .nr_zq = 3, .nr_dx = 4, },
+ { .base = 0x5ba30000, .nr_zq = 3, .nr_dx = 4, },
+ { .base = 0x5bc30000, .nr_zq = 2, .nr_dx = 2, },
+ },
+ },
+ {
+ .soc_id = UNIPHIER_LD6B_ID,
+ .nr_phy = 3,
+ .phy = {
+ { .base = 0x5b830000, .nr_zq = 3, .nr_dx = 4, },
+ { .base = 0x5ba30000, .nr_zq = 3, .nr_dx = 4, },
+ { .base = 0x5bc30000, .nr_zq = 2, .nr_dx = 2, },
+ },
+ },
+};
+UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_ddrmphy_param, uniphier_ddrmphy_param)
+
+static void print_bdl(void __iomem *reg, int n)
+{
+ u32 val = readl(reg);
+ int i;
+
+ for (i = 0; i < n; i++)
+ printf(FS PRINTF_FORMAT, (val >> i * 8) & 0x1f);
+}
+
+static void dump_loop(const struct uniphier_ddrmphy_param *param,
+ void (*callback)(void __iomem *))
+{
+ void __iomem *phy_base, *dx_base;
+ int phy, dx;
+
+ for (phy = 0; phy < param->nr_phy; phy++) {
+ phy_base = ioremap(param->phy[phy].base, SZ_4K);
+ dx_base = phy_base + MPHY_DX_BASE;
+
+ for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
+ printf("PHY%dDX%d:", phy, dx);
+ (*callback)(dx_base);
+ dx_base += MPHY_DX_STRIDE;
+ printf("\n");
+ }
+
+ iounmap(phy_base);
+ }
+}
+
+static void zq_dump(const struct uniphier_ddrmphy_param *param)
+{
+ void __iomem *phy_base, *zq_base;
+ u32 val;
+ int phy, zq, i;
+
+ printf("\n--- Impedance Data ---\n");
+ printf(" ZPD ZPU OPD OPU ZDV ODV\n");
+
+ for (phy = 0; phy < param->nr_phy; phy++) {
+ phy_base = ioremap(param->phy[phy].base, SZ_4K);
+ zq_base = phy_base + MPHY_ZQ_BASE;
+
+ for (zq = 0; zq < param->phy[phy].nr_zq; zq++) {
+ printf("PHY%dZQ%d:", phy, zq);
+
+ val = readl(zq_base + MPHY_ZQ_DR);
+ for (i = 0; i < 4; i++) {
+ printf(FS PRINTF_FORMAT, val & 0x7f);
+ val >>= 7;
+ }
+
+ val = readl(zq_base + MPHY_ZQ_PR);
+ for (i = 0; i < 2; i++) {
+ printf(FS PRINTF_FORMAT, val & 0xf);
+ val >>= 4;
+ }
+
+ zq_base += MPHY_ZQ_STRIDE;
+ printf("\n");
+ }
+
+ iounmap(phy_base);
+ }
+}
+
+static void __wbdl_dump(void __iomem *dx_base)
+{
+ print_bdl(dx_base + MPHY_DX_BDLR0, 4);
+ print_bdl(dx_base + MPHY_DX_BDLR1, 4);
+ print_bdl(dx_base + MPHY_DX_BDLR2, 2);
+
+ printf(FS "(+" PRINTF_FORMAT ")",
+ readl(dx_base + MPHY_DX_LCDLR1) & 0xff);
+}
+
+static void wbdl_dump(const struct uniphier_ddrmphy_param *param)
+{
+ printf("\n--- Write Bit Delay Line ---\n");
+ printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
+
+ dump_loop(param, &__wbdl_dump);
+}
+
+static void __rbdl_dump(void __iomem *dx_base)
+{
+ print_bdl(dx_base + MPHY_DX_BDLR3, 4);
+ print_bdl(dx_base + MPHY_DX_BDLR4, 4);
+ print_bdl(dx_base + MPHY_DX_BDLR5, 1);
+
+ printf(FS "(+" PRINTF_FORMAT ")",
+ (readl(dx_base + MPHY_DX_LCDLR1) >> 8) & 0xff);
+
+ printf(FS "(+" PRINTF_FORMAT ")",
+ (readl(dx_base + MPHY_DX_LCDLR1) >> 16) & 0xff);
+}
+
+static void rbdl_dump(const struct uniphier_ddrmphy_param *param)
+{
+ printf("\n--- Read Bit Delay Line ---\n");
+ printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD) (RDQSND)\n");
+
+ dump_loop(param, &__rbdl_dump);
+}
+
+static void __wld_dump(void __iomem *dx_base)
+{
+ int rank;
+ u32 lcdlr0 = readl(dx_base + MPHY_DX_LCDLR0);
+ u32 gtr = readl(dx_base + MPHY_DX_GTR);
+
+ for (rank = 0; rank < 4; rank++) {
+ u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
+ u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
+
+ printf(FS PRINTF_FORMAT "%sT", wld,
+ wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
+ }
+}
+
+static void wld_dump(const struct uniphier_ddrmphy_param *param)
+{
+ printf("\n--- Write Leveling Delay ---\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
+
+ dump_loop(param, &__wld_dump);
+}
+
+static void __dqsgd_dump(void __iomem *dx_base)
+{
+ int rank;
+ u32 lcdlr2 = readl(dx_base + MPHY_DX_LCDLR2);
+ u32 gtr = readl(dx_base + MPHY_DX_GTR);
+
+ for (rank = 0; rank < 4; rank++) {
+ u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
+ u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
+
+ printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
+ }
+}
+
+static void dqsgd_dump(const struct uniphier_ddrmphy_param *param)
+{
+ printf("\n--- DQS Gating Delay ---\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
+
+ dump_loop(param, &__dqsgd_dump);
+}
+
+static void __mdl_dump(void __iomem *dx_base)
+{
+ int i;
+ u32 mdl = readl(dx_base + MPHY_DX_MDLR);
+
+ for (i = 0; i < 3; i++)
+ printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
+}
+
+static void mdl_dump(const struct uniphier_ddrmphy_param *param)
+{
+ printf("\n--- Master Delay Line ---\n");
+ printf(" IPRD TPRD MDLD\n");
+
+ dump_loop(param, &__mdl_dump);
+}
+
+#define REG_DUMP(x) \
+ { int ofst = MPHY_ ## x; void __iomem *reg = phy_base + ofst; \
+ printf("%3d: %-10s: %p : %08x\n", \
+ ofst >> MPHY_SHIFT, #x, reg, readl(reg)); }
+
+#define DX_REG_DUMP(dx, x) \
+ { int ofst = MPHY_DX_BASE + MPHY_DX_STRIDE * (dx) + \
+ MPHY_DX_## x; \
+ void __iomem *reg = phy_base + ofst; \
+ printf("%3d: DX%d%-7s: %p : %08x\n", \
+ ofst >> MPHY_SHIFT, (dx), #x, reg, readl(reg)); }
+
+static void reg_dump(const struct uniphier_ddrmphy_param *param)
+{
+ void __iomem *phy_base;
+ int phy, dx;
+
+ printf("\n--- DDR Multi PHY registers ---\n");
+
+ for (phy = 0; phy < param->nr_phy; phy++) {
+ phy_base = ioremap(param->phy[phy].base, SZ_4K);
+
+ printf("== PHY%d (base: %08x) ==\n", phy,
+ ptr_to_uint(phy_base));
+ printf(" No: Name : Address : Data\n");
+
+ REG_DUMP(RIDR);
+ REG_DUMP(PIR);
+ REG_DUMP(PGCR0);
+ REG_DUMP(PGCR1);
+ REG_DUMP(PGCR2);
+ REG_DUMP(PGCR3);
+ REG_DUMP(PGSR0);
+ REG_DUMP(PGSR1);
+ REG_DUMP(PLLCR);
+ REG_DUMP(PTR0);
+ REG_DUMP(PTR1);
+ REG_DUMP(PTR2);
+ REG_DUMP(PTR3);
+ REG_DUMP(PTR4);
+ REG_DUMP(ACMDLR);
+ REG_DUMP(ACBDLR0);
+ REG_DUMP(DXCCR);
+ REG_DUMP(DSGCR);
+ REG_DUMP(DCR);
+ REG_DUMP(DTPR0);
+ REG_DUMP(DTPR1);
+ REG_DUMP(DTPR2);
+ REG_DUMP(DTPR3);
+ REG_DUMP(MR0);
+ REG_DUMP(MR1);
+ REG_DUMP(MR2);
+ REG_DUMP(MR3);
+
+ for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
+ DX_REG_DUMP(dx, GCR0);
+ DX_REG_DUMP(dx, GCR1);
+ DX_REG_DUMP(dx, GCR2);
+ DX_REG_DUMP(dx, GCR3);
+ DX_REG_DUMP(dx, GTR);
+ }
+
+ iounmap(phy_base);
+ }
+}
+
+static int do_ddrm(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ const struct uniphier_ddrmphy_param *param;
+ char *cmd;
+
+ param = uniphier_get_ddrmphy_param();
+ if (!param) {
+ pr_err("unsupported SoC\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (argc == 1)
+ cmd = "all";
+ else
+ cmd = argv[1];
+
+ if (!strcmp(cmd, "zq") || !strcmp(cmd, "all"))
+ zq_dump(param);
+
+ if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
+ wbdl_dump(param);
+
+ if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
+ rbdl_dump(param);
+
+ if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
+ wld_dump(param);
+
+ if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
+ dqsgd_dump(param);
+
+ if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
+ mdl_dump(param);
+
+ if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
+ reg_dump(param);
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ ddrm, 2, 1, do_ddrm,
+ "UniPhier DDR Multi PHY parameters dumper",
+ "- dump all of the following\n"
+ "ddrm zq - dump Impedance Data\n"
+ "ddrm wbdl - dump Write Bit Delay\n"
+ "ddrm rbdl - dump Read Bit Delay\n"
+ "ddrm wld - dump Write Leveling\n"
+ "ddrm dqsgd - dump DQS Gating Delay\n"
+ "ddrm mdl - dump Master Delay Line\n"
+ "ddrm reg - dump registers\n"
+);
diff --git a/roms/u-boot/arch/arm/mach-uniphier/dram/cmd_ddrphy.c b/roms/u-boot/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
new file mode 100644
index 000000000..ca519d1c7
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <command.h>
+#include <stdio.h>
+#include <linux/io.h>
+#include <linux/printk.h>
+#include <linux/sizes.h>
+
+#include "../soc-info.h"
+#include "ddrphy-regs.h"
+
+/* Select either decimal or hexadecimal */
+#if 1
+#define PRINTF_FORMAT "%2d"
+#else
+#define PRINTF_FORMAT "%02x"
+#endif
+/* field separator */
+#define FS " "
+
+#define ptr_to_uint(p) ((unsigned int)(unsigned long)(p))
+
+#define UNIPHIER_MAX_NR_DDRPHY 4
+
+struct uniphier_ddrphy_param {
+ unsigned int soc_id;
+ unsigned int nr_phy;
+ struct {
+ resource_size_t base;
+ unsigned int nr_dx;
+ } phy[UNIPHIER_MAX_NR_DDRPHY];
+};
+
+static const struct uniphier_ddrphy_param uniphier_ddrphy_param[] = {
+ {
+ .soc_id = UNIPHIER_LD4_ID,
+ .nr_phy = 2,
+ .phy = {
+ { .base = 0x5bc01000, .nr_dx = 2, },
+ { .base = 0x5be01000, .nr_dx = 2, },
+ },
+ },
+ {
+ .soc_id = UNIPHIER_PRO4_ID,
+ .nr_phy = 4,
+ .phy = {
+ { .base = 0x5bc01000, .nr_dx = 2, },
+ { .base = 0x5bc02000, .nr_dx = 2, },
+ { .base = 0x5be01000, .nr_dx = 2, },
+ { .base = 0x5be02000, .nr_dx = 2, },
+ },
+ },
+ {
+ .soc_id = UNIPHIER_SLD8_ID,
+ .nr_phy = 2,
+ .phy = {
+ { .base = 0x5bc01000, .nr_dx = 2, },
+ { .base = 0x5be01000, .nr_dx = 2, },
+ },
+ },
+ {
+ .soc_id = UNIPHIER_LD11_ID,
+ .nr_phy = 1,
+ .phy = {
+ { .base = 0x5bc01000, .nr_dx = 4, },
+ },
+ },
+};
+UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_ddrphy_param, uniphier_ddrphy_param)
+
+static void print_bdl(void __iomem *reg, int n)
+{
+ u32 val = readl(reg);
+ int i;
+
+ for (i = 0; i < n; i++)
+ printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f);
+}
+
+static void dump_loop(const struct uniphier_ddrphy_param *param,
+ void (*callback)(void __iomem *))
+{
+ void __iomem *phy_base, *dx_base;
+ int phy, dx;
+
+ for (phy = 0; phy < param->nr_phy; phy++) {
+ phy_base = ioremap(param->phy[phy].base, SZ_4K);
+ dx_base = phy_base + PHY_DX_BASE;
+
+ for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
+ printf("PHY%dDX%d:", phy, dx);
+ (*callback)(dx_base);
+ dx_base += PHY_DX_STRIDE;
+ printf("\n");
+ }
+
+ iounmap(phy_base);
+ }
+}
+
+static void __wbdl_dump(void __iomem *dx_base)
+{
+ print_bdl(dx_base + PHY_DX_BDLR0, 5);
+ print_bdl(dx_base + PHY_DX_BDLR1, 5);
+
+ printf(FS "(+" PRINTF_FORMAT ")",
+ readl(dx_base + PHY_DX_LCDLR1) & 0xff);
+}
+
+static void wbdl_dump(const struct uniphier_ddrphy_param *param)
+{
+ printf("\n--- Write Bit Delay Line ---\n");
+ printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
+
+ dump_loop(param, &__wbdl_dump);
+}
+
+static void __rbdl_dump(void __iomem *dx_base)
+{
+ print_bdl(dx_base + PHY_DX_BDLR3, 5);
+ print_bdl(dx_base + PHY_DX_BDLR4, 4);
+
+ printf(FS "(+" PRINTF_FORMAT ")",
+ (readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff);
+}
+
+static void rbdl_dump(const struct uniphier_ddrphy_param *param)
+{
+ printf("\n--- Read Bit Delay Line ---\n");
+ printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
+
+ dump_loop(param, &__rbdl_dump);
+}
+
+static void __wld_dump(void __iomem *dx_base)
+{
+ int rank;
+ u32 lcdlr0 = readl(dx_base + PHY_DX_LCDLR0);
+ u32 gtr = readl(dx_base + PHY_DX_GTR);
+
+ for (rank = 0; rank < 4; rank++) {
+ u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
+ u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
+
+ printf(FS PRINTF_FORMAT "%sT", wld,
+ wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
+ }
+}
+
+static void wld_dump(const struct uniphier_ddrphy_param *param)
+{
+ printf("\n--- Write Leveling Delay ---\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
+
+ dump_loop(param, &__wld_dump);
+}
+
+static void __dqsgd_dump(void __iomem *dx_base)
+{
+ int rank;
+ u32 lcdlr2 = readl(dx_base + PHY_DX_LCDLR2);
+ u32 gtr = readl(dx_base + PHY_DX_GTR);
+
+ for (rank = 0; rank < 4; rank++) {
+ u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
+ u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
+
+ printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
+ }
+}
+
+static void dqsgd_dump(const struct uniphier_ddrphy_param *param)
+{
+ printf("\n--- DQS Gating Delay ---\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
+
+ dump_loop(param, &__dqsgd_dump);
+}
+
+static void __mdl_dump(void __iomem *dx_base)
+{
+ int i;
+ u32 mdl = readl(dx_base + PHY_DX_MDLR);
+
+ for (i = 0; i < 3; i++)
+ printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
+}
+
+static void mdl_dump(const struct uniphier_ddrphy_param *param)
+{
+ printf("\n--- Master Delay Line ---\n");
+ printf(" IPRD TPRD MDLD\n");
+
+ dump_loop(param, &__mdl_dump);
+}
+
+#define REG_DUMP(x) \
+ { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \
+ printf("%3d: %-10s: %08x : %08x\n", \
+ ofst >> PHY_REG_SHIFT, #x, \
+ ptr_to_uint(reg), readl(reg)); }
+
+#define DX_REG_DUMP(dx, x) \
+ { int ofst = PHY_DX_BASE + PHY_DX_STRIDE * (dx) + \
+ PHY_DX_## x; \
+ void __iomem *reg = phy_base + ofst; \
+ printf("%3d: DX%d%-7s: %08x : %08x\n", \
+ ofst >> PHY_REG_SHIFT, (dx), #x, \
+ ptr_to_uint(reg), readl(reg)); }
+
+static void reg_dump(const struct uniphier_ddrphy_param *param)
+{
+ void __iomem *phy_base;
+ int phy, dx;
+
+ printf("\n--- DDR PHY registers ---\n");
+
+ for (phy = 0; phy < param->nr_phy; phy++) {
+ phy_base = ioremap(param->phy[phy].base, SZ_4K);
+
+ printf("== PHY%d (base: %08x) ==\n",
+ phy, ptr_to_uint(phy_base));
+ printf(" No: Name : Address : Data\n");
+
+ REG_DUMP(RIDR);
+ REG_DUMP(PIR);
+ REG_DUMP(PGCR0);
+ REG_DUMP(PGCR1);
+ REG_DUMP(PGSR0);
+ REG_DUMP(PGSR1);
+ REG_DUMP(PLLCR);
+ REG_DUMP(PTR0);
+ REG_DUMP(PTR1);
+ REG_DUMP(PTR2);
+ REG_DUMP(PTR3);
+ REG_DUMP(PTR4);
+ REG_DUMP(ACMDLR);
+ REG_DUMP(ACBDLR);
+ REG_DUMP(DXCCR);
+ REG_DUMP(DSGCR);
+ REG_DUMP(DCR);
+ REG_DUMP(DTPR0);
+ REG_DUMP(DTPR1);
+ REG_DUMP(DTPR2);
+ REG_DUMP(MR0);
+ REG_DUMP(MR1);
+ REG_DUMP(MR2);
+ REG_DUMP(MR3);
+
+ for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
+ DX_REG_DUMP(dx, GCR);
+ DX_REG_DUMP(dx, GTR);
+ }
+
+ iounmap(phy_base);
+ }
+}
+
+static int do_ddr(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ const struct uniphier_ddrphy_param *param;
+ char *cmd;
+
+ param = uniphier_get_ddrphy_param();
+ if (!param) {
+ pr_err("unsupported SoC\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (argc == 1)
+ cmd = "all";
+ else
+ cmd = argv[1];
+
+ if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
+ wbdl_dump(param);
+
+ if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
+ rbdl_dump(param);
+
+ if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
+ wld_dump(param);
+
+ if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
+ dqsgd_dump(param);
+
+ if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
+ mdl_dump(param);
+
+ if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
+ reg_dump(param);
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ ddr, 2, 1, do_ddr,
+ "UniPhier DDR PHY parameters dumper",
+ "- dump all of the following\n"
+ "ddr wbdl - dump Write Bit Delay\n"
+ "ddr rbdl - dump Read Bit Delay\n"
+ "ddr wld - dump Write Leveling\n"
+ "ddr dqsgd - dump DQS Gating Delay\n"
+ "ddr mdl - dump Master Delay Line\n"
+ "ddr reg - dump registers\n"
+);
diff --git a/roms/u-boot/arch/arm/mach-uniphier/dram/ddrmphy-regs.h b/roms/u-boot/arch/arm/mach-uniphier/dram/ddrmphy-regs.h
new file mode 100644
index 000000000..96bab9de5
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-uniphier/dram/ddrmphy-regs.h
@@ -0,0 +1,145 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * UniPhier DDR MultiPHY registers
+ *
+ * Copyright (C) 2015-2017 Socionext Inc.
+ */
+
+#ifndef UNIPHIER_DDRMPHY_REGS_H
+#define UNIPHIER_DDRMPHY_REGS_H
+
+#include <linux/bitops.h>
+
+#define MPHY_SHIFT 2
+
+#define MPHY_RIDR (0x000 << MPHY_SHIFT)
+#define MPHY_PIR (0x001 << MPHY_SHIFT)
+#define MPHY_PIR_INIT BIT(0) /* Initialization Trigger */
+#define MPHY_PIR_ZCAL BIT(1) /* Impedance Calibration */
+#define MPHY_PIR_PLLINIT BIT(4) /* PLL Initialization */
+#define MPHY_PIR_DCAL BIT(5) /* DDL Calibration */
+#define MPHY_PIR_PHYRST BIT(6) /* PHY Reset */
+#define MPHY_PIR_DRAMRST BIT(7) /* DRAM Reset */
+#define MPHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */
+#define MPHY_PIR_WL BIT(9) /* Write Leveling */
+#define MPHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */
+#define MPHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */
+#define MPHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
+#define MPHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
+#define MPHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */
+#define MPHY_PIR_WREYE BIT(15) /* Write Data Eye Training */
+#define MPHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
+#define MPHY_PIR_INITBYP BIT(31) /* Initialization Bypass */
+#define MPHY_PGCR0 (0x002 << MPHY_SHIFT)
+#define MPHY_PGCR0_PHYFRST BIT(26) /* PHY FIFO Reset */
+#define MPHY_PGCR1 (0x003 << MPHY_SHIFT)
+#define MPHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */
+#define MPHY_PGCR2 (0x004 << MPHY_SHIFT)
+#define MPHY_PGCR2_DUALCHN BIT(28) /* Dual Channel Configuration*/
+#define MPHY_PGCR2_ACPDDC BIT(29) /* AC Power-Down with Dual Ch*/
+#define MPHY_PGCR3 (0x005 << MPHY_SHIFT)
+#define MPHY_PGSR0 (0x006 << MPHY_SHIFT)
+#define MPHY_PGSR0_IDONE BIT(0) /* Initialization Done */
+#define MPHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */
+#define MPHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
+#define MPHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
+#define MPHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
+#define MPHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */
+#define MPHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
+#define MPHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
+#define MPHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
+#define MPHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
+#define MPHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */
+#define MPHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
+#define MPHY_PGSR0_ZCERR BIT(20) /* Impedance Calib Error */
+#define MPHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */
+#define MPHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
+#define MPHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
+#define MPHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
+#define MPHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
+#define MPHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */
+#define MPHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */
+#define MPHY_PGSR1 (0x007 << MPHY_SHIFT)
+#define MPHY_PGSR1_VTSTOP BIT(30) /* VT Stop */
+#define MPHY_PLLCR (0x008 << MPHY_SHIFT)
+#define MPHY_PTR0 (0x009 << MPHY_SHIFT)
+#define MPHY_PTR1 (0x00A << MPHY_SHIFT)
+#define MPHY_PTR2 (0x00B << MPHY_SHIFT)
+#define MPHY_PTR3 (0x00C << MPHY_SHIFT)
+#define MPHY_PTR4 (0x00D << MPHY_SHIFT)
+#define MPHY_ACMDLR (0x00E << MPHY_SHIFT)
+#define MPHY_ACLCDLR (0x00F << MPHY_SHIFT)
+#define MPHY_ACBDLR0 (0x010 << MPHY_SHIFT)
+#define MPHY_ACBDLR1 (0x011 << MPHY_SHIFT)
+#define MPHY_ACBDLR2 (0x012 << MPHY_SHIFT)
+#define MPHY_ACBDLR3 (0x013 << MPHY_SHIFT)
+#define MPHY_ACBDLR4 (0x014 << MPHY_SHIFT)
+#define MPHY_ACBDLR5 (0x015 << MPHY_SHIFT)
+#define MPHY_ACBDLR6 (0x016 << MPHY_SHIFT)
+#define MPHY_ACBDLR7 (0x017 << MPHY_SHIFT)
+#define MPHY_ACBDLR8 (0x018 << MPHY_SHIFT)
+#define MPHY_ACBDLR9 (0x019 << MPHY_SHIFT)
+#define MPHY_ACIOCR0 (0x01A << MPHY_SHIFT)
+#define MPHY_ACIOCR1 (0x01B << MPHY_SHIFT)
+#define MPHY_ACIOCR2 (0x01C << MPHY_SHIFT)
+#define MPHY_ACIOCR3 (0x01D << MPHY_SHIFT)
+#define MPHY_ACIOCR4 (0x01E << MPHY_SHIFT)
+#define MPHY_ACIOCR5 (0x01F << MPHY_SHIFT)
+#define MPHY_DXCCR (0x020 << MPHY_SHIFT)
+#define MPHY_DSGCR (0x021 << MPHY_SHIFT)
+#define MPHY_DCR (0x022 << MPHY_SHIFT)
+#define MPHY_DTPR0 (0x023 << MPHY_SHIFT)
+#define MPHY_DTPR1 (0x024 << MPHY_SHIFT)
+#define MPHY_DTPR2 (0x025 << MPHY_SHIFT)
+#define MPHY_DTPR3 (0x026 << MPHY_SHIFT)
+#define MPHY_MR0 (0x027 << MPHY_SHIFT)
+#define MPHY_MR1 (0x028 << MPHY_SHIFT)
+#define MPHY_MR2 (0x029 << MPHY_SHIFT)
+#define MPHY_MR3 (0x02A << MPHY_SHIFT)
+#define MPHY_ODTCR (0x02B << MPHY_SHIFT)
+#define MPHY_DTCR (0x02C << MPHY_SHIFT)
+#define MPHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */
+#define MPHY_DTCR_RANKEN_MASK (0xf << (MPHY_DTCR_RANKEN_SHIFT))
+#define MPHY_DTAR0 (0x02D << MPHY_SHIFT)
+#define MPHY_DTAR1 (0x02E << MPHY_SHIFT)
+#define MPHY_DTAR2 (0x02F << MPHY_SHIFT)
+#define MPHY_DTAR3 (0x030 << MPHY_SHIFT)
+#define MPHY_DTDR0 (0x031 << MPHY_SHIFT)
+#define MPHY_DTDR1 (0x032 << MPHY_SHIFT)
+#define MPHY_DTEDR0 (0x033 << MPHY_SHIFT)
+#define MPHY_DTEDR1 (0x034 << MPHY_SHIFT)
+#define MPHY_ZQCR (0x090 << MPHY_SHIFT)
+#define MPHY_ZQCR_AVGEN BIT(16) /* Average Algorithm */
+#define MPHY_ZQCR_FORCE_ZCAL_VT_UPDATE BIT(27) /* force VT update */
+/* ZQ */
+#define MPHY_ZQ_BASE (0x091 << MPHY_SHIFT)
+#define MPHY_ZQ_STRIDE (0x004 << MPHY_SHIFT)
+#define MPHY_ZQ_PR (0x000 << MPHY_SHIFT)
+#define MPHY_ZQ_DR (0x001 << MPHY_SHIFT)
+#define MPHY_ZQ_SR (0x002 << MPHY_SHIFT)
+/* DATX8 */
+#define MPHY_DX_BASE (0x0A0 << MPHY_SHIFT)
+#define MPHY_DX_STRIDE (0x020 << MPHY_SHIFT)
+#define MPHY_DX_GCR0 (0x000 << MPHY_SHIFT)
+#define MPHY_DX_GCR0_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
+#define MPHY_DX_GCR0_WLRKEN_MASK (0xf << (MPHY_DX_GCR0_WLRKEN_SHIFT))
+#define MPHY_DX_GCR1 (0x001 << MPHY_SHIFT)
+#define MPHY_DX_GCR2 (0x002 << MPHY_SHIFT)
+#define MPHY_DX_GCR3 (0x003 << MPHY_SHIFT)
+#define MPHY_DX_GSR0 (0x004 << MPHY_SHIFT)
+#define MPHY_DX_GSR1 (0x005 << MPHY_SHIFT)
+#define MPHY_DX_GSR2 (0x006 << MPHY_SHIFT)
+#define MPHY_DX_BDLR0 (0x007 << MPHY_SHIFT)
+#define MPHY_DX_BDLR1 (0x008 << MPHY_SHIFT)
+#define MPHY_DX_BDLR2 (0x009 << MPHY_SHIFT)
+#define MPHY_DX_BDLR3 (0x00A << MPHY_SHIFT)
+#define MPHY_DX_BDLR4 (0x00B << MPHY_SHIFT)
+#define MPHY_DX_BDLR5 (0x00C << MPHY_SHIFT)
+#define MPHY_DX_BDLR6 (0x00D << MPHY_SHIFT)
+#define MPHY_DX_LCDLR0 (0x00E << MPHY_SHIFT)
+#define MPHY_DX_LCDLR1 (0x00F << MPHY_SHIFT)
+#define MPHY_DX_LCDLR2 (0x010 << MPHY_SHIFT)
+#define MPHY_DX_MDLR (0x011 << MPHY_SHIFT)
+#define MPHY_DX_GTR (0x012 << MPHY_SHIFT)
+
+#endif /* UNIPHIER_DDRMPHY_REGS_H */
diff --git a/roms/u-boot/arch/arm/mach-uniphier/dram/ddrphy-init.h b/roms/u-boot/arch/arm/mach-uniphier/dram/ddrphy-init.h
new file mode 100644
index 000000000..09981f6e0
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-uniphier/dram/ddrphy-init.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ */
+
+#ifndef ARCH_DDRPHY_INIT_H
+#define ARCH_DDRPHY_INTT_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus);
+void ddrphy_prepare_training(void __iomem *phy_base, int rank);
+int ddrphy_training(void __iomem *phy_base);
+
+#endif /* ARCH_DDRPHY_INT_H */
diff --git a/roms/u-boot/arch/arm/mach-uniphier/dram/ddrphy-ld4.c b/roms/u-boot/arch/arm/mach-uniphier/dram/ddrphy-ld4.c
new file mode 100644
index 000000000..26f3ba9d5
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-uniphier/dram/ddrphy-ld4.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ */
+
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/printk.h>
+
+#include "ddrphy-init.h"
+#include "ddrphy-regs.h"
+
+enum dram_freq {
+ DRAM_FREQ_1333M,
+ DRAM_FREQ_1600M,
+ DRAM_FREQ_NR,
+};
+
+static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0a806844, 0x0c807d04};
+static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x208e0124, 0x2710015E};
+static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x0f051616, 0x12061A80};
+static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x06ae08d6, 0x08027100};
+static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x85589955, 0x999cbb66};
+static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x1a8363c0, 0x1a878400};
+static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x5002c200, 0xa00214f8};
+static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71};
+static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298};
+
+int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus)
+{
+ enum dram_freq freq_e;
+ u32 tmp;
+
+ switch (freq) {
+ case 1333:
+ freq_e = DRAM_FREQ_1333M;
+ break;
+ case 1600:
+ freq_e = DRAM_FREQ_1600M;
+ break;
+ default:
+ pr_err("unsupported DRAM frequency %d MHz\n", freq);
+ return -EINVAL;
+ }
+
+ writel(0x0300c473, phy_base + PHY_PGCR1);
+ writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0);
+ writel(ddrphy_ptr1[freq_e], phy_base + PHY_PTR1);
+ writel(0x00083DEF, phy_base + PHY_PTR2);
+ writel(ddrphy_ptr3[freq_e], phy_base + PHY_PTR3);
+ writel(ddrphy_ptr4[freq_e], phy_base + PHY_PTR4);
+ writel(0xF004001A, phy_base + PHY_DSGCR);
+
+ /* change the value of the on-die pull-up/pull-down registors */
+ tmp = readl(phy_base + PHY_DXCCR);
+ tmp &= ~0x0ee0;
+ tmp |= PHY_DXCCR_DQSNRES_688_OHM | PHY_DXCCR_DQSRES_688_OHM;
+ writel(tmp, phy_base + PHY_DXCCR);
+
+ writel(0x0000040B, phy_base + PHY_DCR);
+ writel(ddrphy_dtpr0[freq_e], phy_base + PHY_DTPR0);
+ writel(ddrphy_dtpr1[freq_e], phy_base + PHY_DTPR1);
+ writel(ddrphy_dtpr2[freq_e], phy_base + PHY_DTPR2);
+ writel(ddrphy_mr0[freq_e], phy_base + PHY_MR0);
+ writel(0x00000006, phy_base + PHY_MR1);
+ writel(ddrphy_mr2[freq_e], phy_base + PHY_MR2);
+ writel(ddr3plus ? 0x00000800 : 0x00000000, phy_base + PHY_MR3);
+
+ while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
+ ;
+
+ writel(0x0300C473, phy_base + PHY_PGCR1);
+ writel(0x0000005D, phy_base + PHY_ZQ_BASE + PHY_ZQ_CR1);
+
+ return 0;
+}
diff --git a/roms/u-boot/arch/arm/mach-uniphier/dram/ddrphy-regs.h b/roms/u-boot/arch/arm/mach-uniphier/dram/ddrphy-regs.h
new file mode 100644
index 000000000..8b342921b
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-uniphier/dram/ddrphy-regs.h
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * UniPhier DDR PHY registers
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ */
+
+#ifndef ARCH_DDRPHY_REGS_H
+#define ARCH_DDRPHY_REGS_H
+
+#include <linux/bitops.h>
+#define PHY_REG_SHIFT 2
+
+#define PHY_RIDR (0x000 << PHY_REG_SHIFT)
+#define PHY_PIR (0x001 << PHY_REG_SHIFT)
+#define PHY_PIR_INIT BIT(0) /* Initialization Trigger */
+#define PHY_PIR_ZCAL BIT(1) /* Impedance Calibration */
+#define PHY_PIR_PLLINIT BIT(4) /* PLL Initialization */
+#define PHY_PIR_DCAL BIT(5) /* DDL Calibration */
+#define PHY_PIR_PHYRST BIT(6) /* PHY Reset */
+#define PHY_PIR_DRAMRST BIT(7) /* DRAM Reset */
+#define PHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */
+#define PHY_PIR_WL BIT(9) /* Write Leveling */
+#define PHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */
+#define PHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */
+#define PHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
+#define PHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
+#define PHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */
+#define PHY_PIR_WREYE BIT(15) /* Write Data Eye Training */
+#define PHY_PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */
+#define PHY_PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */
+#define PHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
+#define PHY_PIR_INITBYP BIT(31) /* Initialization Bypass */
+#define PHY_PGCR0 (0x002 << PHY_REG_SHIFT)
+#define PHY_PGCR1 (0x003 << PHY_REG_SHIFT)
+#define PHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */
+#define PHY_PGSR0 (0x004 << PHY_REG_SHIFT)
+#define PHY_PGSR0_IDONE BIT(0) /* Initialization Done */
+#define PHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */
+#define PHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
+#define PHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
+#define PHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
+#define PHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */
+#define PHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
+#define PHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
+#define PHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
+#define PHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
+#define PHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */
+#define PHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
+#define PHY_PGSR0_DIERR BIT(20) /* DRAM Initialization Error */
+#define PHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */
+#define PHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
+#define PHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
+#define PHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
+#define PHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
+#define PHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */
+#define PHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */
+#define PHY_PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/
+#define PHY_PGSR0_DTERR (7 << (PHY_PGSR0_DTERR_SHIFT))
+#define PHY_PGSR1 (0x005 << PHY_REG_SHIFT)
+#define PHY_PGSR1_VTSTOP BIT(30) /* VT Stop (v3-) */
+#define PHY_PLLCR (0x006 << PHY_REG_SHIFT)
+#define PHY_PTR0 (0x007 << PHY_REG_SHIFT)
+#define PHY_PTR1 (0x008 << PHY_REG_SHIFT)
+#define PHY_PTR2 (0x009 << PHY_REG_SHIFT)
+#define PHY_PTR3 (0x00A << PHY_REG_SHIFT)
+#define PHY_PTR4 (0x00B << PHY_REG_SHIFT)
+#define PHY_ACMDLR (0x00C << PHY_REG_SHIFT)
+#define PHY_ACBDLR (0x00D << PHY_REG_SHIFT)
+#define PHY_ACIOCR (0x00E << PHY_REG_SHIFT)
+#define PHY_DXCCR (0x00F << PHY_REG_SHIFT)
+#define PHY_DXCCR_DQSRES_OPEN (0 << 5)
+#define PHY_DXCCR_DQSRES_688_OHM (1 << 5)
+#define PHY_DXCCR_DQSRES_611_OHM (2 << 5)
+#define PHY_DXCCR_DQSRES_550_OHM (3 << 5)
+#define PHY_DXCCR_DQSRES_500_OHM (4 << 5)
+#define PHY_DXCCR_DQSRES_458_OHM (5 << 5)
+#define PHY_DXCCR_DQSRES_393_OHM (6 << 5)
+#define PHY_DXCCR_DQSRES_344_OHM (7 << 5)
+#define PHY_DXCCR_DQSNRES_OPEN (0 << 9)
+#define PHY_DXCCR_DQSNRES_688_OHM (1 << 9)
+#define PHY_DXCCR_DQSNRES_611_OHM (2 << 9)
+#define PHY_DXCCR_DQSNRES_550_OHM (3 << 9)
+#define PHY_DXCCR_DQSNRES_500_OHM (4 << 9)
+#define PHY_DXCCR_DQSNRES_458_OHM (5 << 9)
+#define PHY_DXCCR_DQSNRES_393_OHM (6 << 9)
+#define PHY_DXCCR_DQSNRES_344_OHM (7 << 9)
+#define PHY_DSGCR (0x010 << PHY_REG_SHIFT)
+#define PHY_DCR (0x011 << PHY_REG_SHIFT)
+#define PHY_DTPR0 (0x012 << PHY_REG_SHIFT)
+#define PHY_DTPR1 (0x013 << PHY_REG_SHIFT)
+#define PHY_DTPR2 (0x014 << PHY_REG_SHIFT)
+#define PHY_MR0 (0x015 << PHY_REG_SHIFT)
+#define PHY_MR1 (0x016 << PHY_REG_SHIFT)
+#define PHY_MR2 (0x017 << PHY_REG_SHIFT)
+#define PHY_MR3 (0x018 << PHY_REG_SHIFT)
+#define PHY_ODTCR (0x019 << PHY_REG_SHIFT)
+#define PHY_DTCR (0x01A << PHY_REG_SHIFT)
+#define PHY_DTCR_DTRANK_SHIFT 4 /* Data Training Rank */
+#define PHY_DTCR_DTRANK_MASK (0x3 << (PHY_DTCR_DTRANK_SHIFT))
+#define PHY_DTCR_DTMPR BIT(6) /* Data Training using MPR */
+#define PHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */
+#define PHY_DTCR_RANKEN_MASK (0xf << (PHY_DTCR_RANKEN_SHIFT))
+#define PHY_DTAR0 (0x01B << PHY_REG_SHIFT)
+#define PHY_DTAR1 (0x01C << PHY_REG_SHIFT)
+#define PHY_DTAR2 (0x01D << PHY_REG_SHIFT)
+#define PHY_DTAR3 (0x01E << PHY_REG_SHIFT)
+#define PHY_DTDR0 (0x01F << PHY_REG_SHIFT)
+#define PHY_DTDR1 (0x020 << PHY_REG_SHIFT)
+#define PHY_DTEDR0 (0x021 << PHY_REG_SHIFT)
+#define PHY_DTEDR1 (0x022 << PHY_REG_SHIFT)
+#define PHY_PGCR2 (0x023 << PHY_REG_SHIFT)
+#define PHY_GPR0 (0x05E << PHY_REG_SHIFT)
+#define PHY_GPR1 (0x05F << PHY_REG_SHIFT)
+/* ZQ */
+#define PHY_ZQ_BASE (0x060 << PHY_REG_SHIFT)
+#define PHY_ZQ_STRIDE (0x004 << PHY_REG_SHIFT)
+#define PHY_ZQ_CR0 (0x000 << PHY_REG_SHIFT)
+#define PHY_ZQ_CR1 (0x001 << PHY_REG_SHIFT)
+#define PHY_ZQ_SR0 (0x002 << PHY_REG_SHIFT)
+#define PHY_ZQ_SR1 (0x003 << PHY_REG_SHIFT)
+/* DATX8 */
+#define PHY_DX_BASE (0x070 << PHY_REG_SHIFT)
+#define PHY_DX_STRIDE (0x010 << PHY_REG_SHIFT)
+#define PHY_DX_GCR (0x000 << PHY_REG_SHIFT)
+#define PHY_DX_GCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
+#define PHY_DX_GCR_WLRKEN_MASK (0xf << (PHY_DX_GCR_WLRKEN_SHIFT))
+#define PHY_DX_GSR0 (0x001 << PHY_REG_SHIFT)
+#define PHY_DX_GSR1 (0x002 << PHY_REG_SHIFT)
+#define PHY_DX_BDLR0 (0x003 << PHY_REG_SHIFT)
+#define PHY_DX_BDLR1 (0x004 << PHY_REG_SHIFT)
+#define PHY_DX_BDLR2 (0x005 << PHY_REG_SHIFT)
+#define PHY_DX_BDLR3 (0x006 << PHY_REG_SHIFT)
+#define PHY_DX_BDLR4 (0x007 << PHY_REG_SHIFT)
+#define PHY_DX_LCDLR0 (0x008 << PHY_REG_SHIFT)
+#define PHY_DX_LCDLR1 (0x009 << PHY_REG_SHIFT)
+#define PHY_DX_LCDLR2 (0x00A << PHY_REG_SHIFT)
+#define PHY_DX_MDLR (0x00B << PHY_REG_SHIFT)
+#define PHY_DX_GTR (0x00C << PHY_REG_SHIFT)
+#define PHY_DX_GSR2 (0x00D << PHY_REG_SHIFT)
+
+#endif /* ARCH_DDRPHY_REGS_H */
diff --git a/roms/u-boot/arch/arm/mach-uniphier/dram/ddrphy-training.c b/roms/u-boot/arch/arm/mach-uniphier/dram/ddrphy-training.c
new file mode 100644
index 000000000..1decdf1cb
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-uniphier/dram/ddrphy-training.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/printk.h>
+#include <time.h>
+
+#include "ddrphy-init.h"
+#include "ddrphy-regs.h"
+
+/* for LD4, Pro4, sLD8 */
+#define NR_DATX8_PER_DDRPHY 2
+
+void ddrphy_prepare_training(void __iomem *phy_base, int rank)
+{
+ void __iomem *dx_base = phy_base + PHY_DX_BASE;
+ int dx;
+ u32 tmp;
+
+ for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
+ tmp = readl(dx_base + PHY_DX_GCR);
+ /* Specify the rank that should be write leveled */
+ tmp &= ~PHY_DX_GCR_WLRKEN_MASK;
+ tmp |= (1 << (PHY_DX_GCR_WLRKEN_SHIFT + rank)) &
+ PHY_DX_GCR_WLRKEN_MASK;
+ writel(tmp, dx_base + PHY_DX_GCR);
+ dx_base += PHY_DX_STRIDE;
+ }
+
+ tmp = readl(phy_base + PHY_DTCR);
+ /* Specify the rank used during data bit deskew and eye centering */
+ tmp &= ~PHY_DTCR_DTRANK_MASK;
+ tmp |= (rank << PHY_DTCR_DTRANK_SHIFT) & PHY_DTCR_DTRANK_MASK;
+ /* Use Multi-Purpose Register for DQS gate training */
+ tmp |= PHY_DTCR_DTMPR;
+ /* Specify the rank enabled for data-training */
+ tmp &= ~PHY_DTCR_RANKEN_MASK;
+ tmp |= (1 << (PHY_DTCR_RANKEN_SHIFT + rank)) & PHY_DTCR_RANKEN_MASK;
+ writel(tmp, phy_base + PHY_DTCR);
+}
+
+struct ddrphy_init_sequence {
+ char *description;
+ u32 init_flag;
+ u32 done_flag;
+ u32 err_flag;
+};
+
+static const struct ddrphy_init_sequence init_sequence[] = {
+ {
+ "DRAM Initialization",
+ PHY_PIR_DRAMRST | PHY_PIR_DRAMINIT,
+ PHY_PGSR0_DIDONE,
+ PHY_PGSR0_DIERR
+ },
+ {
+ "Write Leveling",
+ PHY_PIR_WL,
+ PHY_PGSR0_WLDONE,
+ PHY_PGSR0_WLERR
+ },
+ {
+ "Read DQS Gate Training",
+ PHY_PIR_QSGATE,
+ PHY_PGSR0_QSGDONE,
+ PHY_PGSR0_QSGERR
+ },
+ {
+ "Write Leveling Adjustment",
+ PHY_PIR_WLADJ,
+ PHY_PGSR0_WLADONE,
+ PHY_PGSR0_WLAERR
+ },
+ {
+ "Read Bit Deskew",
+ PHY_PIR_RDDSKW,
+ PHY_PGSR0_RDDONE,
+ PHY_PGSR0_RDERR
+ },
+ {
+ "Write Bit Deskew",
+ PHY_PIR_WRDSKW,
+ PHY_PGSR0_WDDONE,
+ PHY_PGSR0_WDERR
+ },
+ {
+ "Read Eye Training",
+ PHY_PIR_RDEYE,
+ PHY_PGSR0_REDONE,
+ PHY_PGSR0_REERR
+ },
+ {
+ "Write Eye Training",
+ PHY_PIR_WREYE,
+ PHY_PGSR0_WEDONE,
+ PHY_PGSR0_WEERR
+ }
+};
+
+int ddrphy_training(void __iomem *phy_base)
+{
+ int i;
+ u32 pgsr0;
+ u32 init_flag = PHY_PIR_INIT;
+ u32 done_flag = PHY_PGSR0_IDONE;
+ int timeout = 50000; /* 50 msec is long enough */
+#ifdef DEBUG
+ ulong start = get_timer(0);
+#endif
+
+ for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
+ init_flag |= init_sequence[i].init_flag;
+ done_flag |= init_sequence[i].done_flag;
+ }
+
+ writel(init_flag, phy_base + PHY_PIR);
+
+ do {
+ if (--timeout < 0) {
+ pr_err("timeout during DDR training\n");
+ return -ETIMEDOUT;
+ }
+ udelay(1);
+ pgsr0 = readl(phy_base + PHY_PGSR0);
+ } while ((pgsr0 & done_flag) != done_flag);
+
+ for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
+ if (pgsr0 & init_sequence[i].err_flag) {
+ pr_err("%s failed\n", init_sequence[i].description);
+ return -EIO;
+ }
+ }
+
+#ifdef DEBUG
+ pr_debug("DDR training: elapsed time %ld msec\n", get_timer(start));
+#endif
+
+ return 0;
+}
diff --git a/roms/u-boot/arch/arm/mach-uniphier/dram/umc-ld4.c b/roms/u-boot/arch/arm/mach-uniphier/dram/umc-ld4.c
new file mode 100644
index 000000000..96acca256
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-uniphier/dram/umc-ld4.c
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <asm/processor.h>
+
+#include "../init.h"
+#include "ddrphy-init.h"
+#include "umc-regs.h"
+
+#define DRAM_CH_NR 2
+
+enum dram_freq {
+ DRAM_FREQ_1333M,
+ DRAM_FREQ_1600M,
+ DRAM_FREQ_NR,
+};
+
+enum dram_size {
+ DRAM_SZ_128M,
+ DRAM_SZ_256M,
+ DRAM_SZ_NR,
+};
+
+static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x36bb0f17};
+static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6aa24};
+static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+ {0x00240512, 0x00350512},
+ {0x002b0617, 0x003f0617},
+};
+static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
+static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ae};
+
+static int umc_get_rank(int ch)
+{
+ return ch; /* ch0: rank0, ch1: rank1 for this SoC */
+}
+
+static void umc_start_ssif(void __iomem *ssif_base)
+{
+ writel(0x00000000, ssif_base + 0x0000b004);
+ writel(0xffffffff, ssif_base + 0x0000c004);
+ writel(0x000fffcf, ssif_base + 0x0000c008);
+ writel(0x00000001, ssif_base + 0x0000b000);
+ writel(0x00000001, ssif_base + 0x0000c000);
+ writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+ writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+
+ writel(0x00000001, ssif_base + UMC_CPURST);
+ writel(0x00000001, ssif_base + UMC_IDSRST);
+ writel(0x00000001, ssif_base + UMC_IXMRST);
+ writel(0x00000001, ssif_base + UMC_MDMRST);
+ writel(0x00000001, ssif_base + UMC_MDDRST);
+ writel(0x00000001, ssif_base + UMC_SIORST);
+ writel(0x00000001, ssif_base + UMC_VIORST);
+ writel(0x00000001, ssif_base + UMC_FRCRST);
+ writel(0x00000001, ssif_base + UMC_RGLRST);
+ writel(0x00000001, ssif_base + UMC_AIORST);
+ writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
+ int freq, unsigned long size, bool ddr3plus)
+{
+ enum dram_freq freq_e;
+ enum dram_size size_e;
+
+ if (!ddr3plus) {
+ pr_err("DDR3 standard is not supported\n");
+ return -EINVAL;
+ }
+
+ switch (freq) {
+ case 1333:
+ freq_e = DRAM_FREQ_1333M;
+ break;
+ case 1600:
+ freq_e = DRAM_FREQ_1600M;
+ break;
+ default:
+ pr_err("unsupported DRAM frequency %d MHz\n", freq);
+ return -EINVAL;
+ }
+
+ switch (size) {
+ case 0:
+ return 0;
+ case SZ_128M:
+ size_e = DRAM_SZ_128M;
+ break;
+ case SZ_256M:
+ size_e = DRAM_SZ_256M;
+ break;
+ default:
+ pr_err("unsupported DRAM size 0x%08lx\n", size);
+ return -EINVAL;
+ }
+
+ writel(umc_cmdctla_plus[freq_e], dc_base + UMC_CMDCTLA);
+ writel(umc_cmdctlb_plus[freq_e], dc_base + UMC_CMDCTLB);
+ writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA);
+ writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB);
+ writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
+ writel(0x04060806, dc_base + UMC_WDATACTL_D0);
+ writel(0x04a02000, dc_base + UMC_DATASET);
+ writel(0x00000000, ca_base + 0x2300);
+ writel(0x00400020, dc_base + UMC_DCCGCTL);
+ writel(0x00000003, dc_base + 0x7000);
+ writel(0x0000000f, dc_base + 0x8000);
+ writel(0x000000c3, dc_base + 0x8004);
+ writel(0x00000071, dc_base + 0x8008);
+ writel(0x0000003b, dc_base + UMC_DICGCTLA);
+ writel(0x020a0808, dc_base + UMC_DICGCTLB);
+ writel(0x00000004, dc_base + UMC_FLOWCTLG);
+ writel(0x80000201, ca_base + 0xc20);
+ writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
+ writel(0x00200000, dc_base + UMC_FLOWCTLB);
+ writel(0x00004444, dc_base + UMC_FLOWCTLC);
+ writel(0x200a0a00, dc_base + UMC_SPCSETB);
+ writel(0x00000000, dc_base + UMC_SPCSETD);
+ writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
+
+ return 0;
+}
+
+static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
+ int freq, unsigned long size, bool ddr3plus, int ch)
+{
+ void __iomem *phy_base = dc_base + 0x00001000;
+ int ret;
+
+ writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
+ while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
+ cpu_relax();
+
+ writel(0x00000101, dc_base + UMC_DIOCTLA);
+
+ ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
+ if (ret)
+ return ret;
+
+ ddrphy_prepare_training(phy_base, umc_get_rank(ch));
+ ret = ddrphy_training(phy_base);
+ if (ret)
+ return ret;
+
+ return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus);
+}
+
+int uniphier_ld4_umc_init(const struct uniphier_board_data *bd)
+{
+ void __iomem *umc_base = (void __iomem *)0x5b800000;
+ void __iomem *ca_base = umc_base + 0x00001000;
+ void __iomem *dc_base = umc_base + 0x00400000;
+ void __iomem *ssif_base = umc_base;
+ int ch, ret;
+
+ for (ch = 0; ch < DRAM_CH_NR; ch++) {
+ ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
+ bd->dram_ch[ch].size,
+ !!(bd->flags & UNIPHIER_BD_DDR3PLUS), ch);
+ if (ret) {
+ pr_err("failed to initialize UMC ch%d\n", ch);
+ return ret;
+ }
+
+ ca_base += 0x00001000;
+ dc_base += 0x00200000;
+ }
+
+ umc_start_ssif(ssif_base);
+
+ return 0;
+}
diff --git a/roms/u-boot/arch/arm/mach-uniphier/dram/umc-pro4.c b/roms/u-boot/arch/arm/mach-uniphier/dram/umc-pro4.c
new file mode 100644
index 000000000..cde39b499
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-uniphier/dram/umc-pro4.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <asm/processor.h>
+
+#include "../init.h"
+#include "ddrphy-init.h"
+#include "umc-regs.h"
+
+#define DRAM_CH_NR 2
+
+enum dram_size {
+ DRAM_SZ_128M,
+ DRAM_SZ_256M,
+ DRAM_SZ_512M,
+ DRAM_SZ_NR,
+};
+
+static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617, 0x00770617};
+
+static void umc_start_ssif(void __iomem *ssif_base)
+{
+ writel(0x00000000, ssif_base + 0x0000b004);
+ writel(0xffffffff, ssif_base + 0x0000c004);
+ writel(0x000fffcf, ssif_base + 0x0000c008);
+ writel(0x00000001, ssif_base + 0x0000b000);
+ writel(0x00000001, ssif_base + 0x0000c000);
+
+ writel(0x03010100, ssif_base + UMC_HDMCHSEL);
+ writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+ writel(0x03010100, ssif_base + UMC_DVCCHSEL);
+ writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+ writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */
+
+ writel(0x00000001, ssif_base + UMC_CPURST);
+ writel(0x00000001, ssif_base + UMC_IDSRST);
+ writel(0x00000001, ssif_base + UMC_IXMRST);
+ writel(0x00000001, ssif_base + UMC_HDMRST);
+ writel(0x00000001, ssif_base + UMC_MDMRST);
+ writel(0x00000001, ssif_base + UMC_HDDRST);
+ writel(0x00000001, ssif_base + UMC_MDDRST);
+ writel(0x00000001, ssif_base + UMC_SIORST);
+ writel(0x00000001, ssif_base + UMC_GIORST);
+ writel(0x00000001, ssif_base + UMC_HD2RST);
+ writel(0x00000001, ssif_base + UMC_VIORST);
+ writel(0x00000001, ssif_base + UMC_DVCRST);
+ writel(0x00000001, ssif_base + UMC_RGLRST);
+ writel(0x00000001, ssif_base + UMC_VPERST);
+ writel(0x00000001, ssif_base + UMC_AIORST);
+ writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
+ int freq, unsigned long size, bool ddr3plus)
+{
+ enum dram_size size_e;
+
+ if (freq != 1600) {
+ pr_err("Unsupported DDR frequency %d MHz\n", freq);
+ return -EINVAL;
+ }
+
+ if (ddr3plus) {
+ pr_err("DDR3+ is not supported\n");
+ return -EINVAL;
+ }
+
+ switch (size) {
+ case SZ_128M:
+ size_e = DRAM_SZ_128M;
+ break;
+ case SZ_256M:
+ size_e = DRAM_SZ_256M;
+ break;
+ case SZ_512M:
+ size_e = DRAM_SZ_512M;
+ break;
+ default:
+ pr_err("unsupported DRAM size 0x%08lx (per 16bit)\n", size);
+ return -EINVAL;
+ }
+
+ writel(0x66bb0f17, dc_base + UMC_CMDCTLA);
+ writel(0x18c6aa44, dc_base + UMC_CMDCTLB);
+ writel(umc_spcctla[size_e], dc_base + UMC_SPCCTLA);
+ writel(0x00ff0008, dc_base + UMC_SPCCTLB);
+ writel(0x000c00ae, dc_base + UMC_RDATACTL_D0);
+ writel(0x000c00ae, dc_base + UMC_RDATACTL_D1);
+ writel(0x04060802, dc_base + UMC_WDATACTL_D0);
+ writel(0x04060802, dc_base + UMC_WDATACTL_D1);
+ writel(0x04a02000, dc_base + UMC_DATASET);
+ writel(0x00000000, ca_base + 0x2300);
+ writel(0x00400020, dc_base + UMC_DCCGCTL);
+ writel(0x0000000f, dc_base + 0x7000);
+ writel(0x0000000f, dc_base + 0x8000);
+ writel(0x000000c3, dc_base + 0x8004);
+ writel(0x00000071, dc_base + 0x8008);
+ writel(0x00000004, dc_base + UMC_FLOWCTLG);
+ writel(0x00000000, dc_base + 0x0060);
+ writel(0x80000201, ca_base + 0xc20);
+ writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
+ writel(0x00200000, dc_base + UMC_FLOWCTLB);
+ writel(0x00004444, dc_base + UMC_FLOWCTLC);
+ writel(0x200a0a00, dc_base + UMC_SPCSETB);
+ writel(0x00010000, dc_base + UMC_SPCSETD);
+ writel(0x80000020, dc_base + UMC_DFICUPDCTLA);
+
+ return 0;
+}
+
+static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
+ int freq, unsigned long size, unsigned int width,
+ bool ddr3plus)
+{
+ void __iomem *phy_base = dc_base + 0x00001000;
+ int nr_phy = width / 16;
+ int phy, ret;
+
+ writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
+ while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
+ cpu_relax();
+
+ for (phy = 0; phy < nr_phy; phy++) {
+ writel(0x00000100 | ((1 << (phy + 1)) - 1),
+ dc_base + UMC_DIOCTLA);
+
+ ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
+ if (ret)
+ return ret;
+
+ ddrphy_prepare_training(phy_base, phy);
+ ret = ddrphy_training(phy_base);
+ if (ret)
+ return ret;
+
+ phy_base += 0x00001000;
+ }
+
+ return umc_dramcont_init(dc_base, ca_base, freq, size / (width / 16),
+ ddr3plus);
+}
+
+int uniphier_pro4_umc_init(const struct uniphier_board_data *bd)
+{
+ void __iomem *umc_base = (void __iomem *)0x5b800000;
+ void __iomem *ca_base = umc_base + 0x00001000;
+ void __iomem *dc_base = umc_base + 0x00400000;
+ void __iomem *ssif_base = umc_base;
+ int ch, ret;
+
+ for (ch = 0; ch < DRAM_CH_NR; ch++) {
+ ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
+ bd->dram_ch[ch].size,
+ bd->dram_ch[ch].width,
+ !!(bd->flags & UNIPHIER_BD_DDR3PLUS));
+ if (ret) {
+ pr_err("failed to initialize UMC ch%d\n", ch);
+ return ret;
+ }
+
+ ca_base += 0x00001000;
+ dc_base += 0x00200000;
+ }
+
+ umc_start_ssif(ssif_base);
+
+ return 0;
+}
diff --git a/roms/u-boot/arch/arm/mach-uniphier/dram/umc-pro5.c b/roms/u-boot/arch/arm/mach-uniphier/dram/umc-pro5.c
new file mode 100644
index 000000000..a002b309e
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-uniphier/dram/umc-pro5.c
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ */
+
+#include "../init.h"
+
+int uniphier_pro5_umc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
diff --git a/roms/u-boot/arch/arm/mach-uniphier/dram/umc-pxs2.c b/roms/u-boot/arch/arm/mach-uniphier/dram/umc-pxs2.c
new file mode 100644
index 000000000..73574201e
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-uniphier/dram/umc-pxs2.c
@@ -0,0 +1,643 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * based on commit 21b6e480f92ccc38fe0502e3116411d6509d3bf2 of Diag by:
+ * Copyright (C) 2015 Socionext Inc.
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/printk.h>
+#include <linux/sizes.h>
+#include <asm/processor.h>
+#include <time.h>
+
+#include "../init.h"
+#include "../soc-info.h"
+#include "ddrmphy-regs.h"
+#include "umc-regs.h"
+
+#define DRAM_CH_NR 3
+
+enum dram_freq {
+ DRAM_FREQ_1866M,
+ DRAM_FREQ_2133M,
+ DRAM_FREQ_NR,
+};
+
+enum dram_size {
+ DRAM_SZ_256M,
+ DRAM_SZ_512M,
+ DRAM_SZ_NR,
+};
+
+/* PHY */
+static u32 ddrphy_pgcr2[DRAM_FREQ_NR] = {0x00FC7E5D, 0x00FC90AB};
+static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0EA09205, 0x10C0A6C6};
+static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x0DAC041B, 0x0FA104B1};
+static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x15171e45, 0x18182357};
+static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x0e9ad8e9, 0x10b34157};
+static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x35a00d88, 0x39e40e88};
+static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x2288cc2c, 0x228a04d0};
+static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x50005e00, 0x50006a00};
+static u32 ddrphy_dtpr3[DRAM_FREQ_NR] = {0x0010cb49, 0x0010ec89};
+static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000115, 0x00000125};
+static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x000002a0, 0x000002a8};
+
+/* dependent on package and board design */
+static u32 ddrphy_acbdlr0[DRAM_CH_NR] = {0x0000000c, 0x0000000c, 0x00000009};
+
+/* DDR multiPHY */
+static inline int ddrphy_get_rank(int dx)
+{
+ return dx / 2;
+}
+
+static void ddrphy_fifo_reset(void __iomem *phy_base)
+{
+ u32 tmp;
+
+ tmp = readl(phy_base + MPHY_PGCR0);
+ tmp &= ~MPHY_PGCR0_PHYFRST;
+ writel(tmp, phy_base + MPHY_PGCR0);
+
+ udelay(1);
+
+ tmp |= MPHY_PGCR0_PHYFRST;
+ writel(tmp, phy_base + MPHY_PGCR0);
+
+ udelay(1);
+}
+
+static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable)
+{
+ u32 tmp;
+
+ tmp = readl(phy_base + MPHY_PGCR1);
+
+ if (enable)
+ tmp &= ~MPHY_PGCR1_INHVT;
+ else
+ tmp |= MPHY_PGCR1_INHVT;
+
+ writel(tmp, phy_base + MPHY_PGCR1);
+
+ if (!enable) {
+ while (!(readl(phy_base + MPHY_PGSR1) & MPHY_PGSR1_VTSTOP))
+ cpu_relax();
+ }
+}
+
+static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step)
+{
+ int dx;
+ u32 lcdlr1, rdqsd;
+ void __iomem *dx_base = phy_base + MPHY_DX_BASE;
+
+ ddrphy_vt_ctrl(phy_base, 0);
+
+ for (dx = 0; dx < nr_dx; dx++) {
+ lcdlr1 = readl(dx_base + MPHY_DX_LCDLR1);
+ rdqsd = (lcdlr1 >> 8) & 0xff;
+ rdqsd = clamp(rdqsd + step, 0U, 0xffU);
+ lcdlr1 = (lcdlr1 & ~(0xff << 8)) | (rdqsd << 8);
+ writel(lcdlr1, dx_base + MPHY_DX_LCDLR1);
+ readl(dx_base + MPHY_DX_LCDLR1); /* relax */
+ dx_base += MPHY_DX_STRIDE;
+ }
+
+ ddrphy_vt_ctrl(phy_base, 1);
+}
+
+static int ddrphy_get_system_latency(void __iomem *phy_base, int width)
+{
+ void __iomem *dx_base = phy_base + MPHY_DX_BASE;
+ const int nr_dx = width / 8;
+ int dx, rank;
+ u32 gtr;
+ int dgsl, dgsl_min = INT_MAX, dgsl_max = 0;
+
+ for (dx = 0; dx < nr_dx; dx++) {
+ gtr = readl(dx_base + MPHY_DX_GTR);
+ for (rank = 0; rank < 4; rank++) {
+ dgsl = gtr & 0x7;
+ /* if dgsl is zero, this rank was not trained. skip. */
+ if (dgsl) {
+ dgsl_min = min(dgsl_min, dgsl);
+ dgsl_max = max(dgsl_max, dgsl);
+ }
+ gtr >>= 3;
+ }
+ dx_base += MPHY_DX_STRIDE;
+ }
+
+ if (dgsl_min != dgsl_max)
+ pr_warn("DQS Gateing System Latencies are not all leveled.\n");
+
+ return dgsl_max;
+}
+
+static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width,
+ int ch)
+{
+ u32 tmp;
+ void __iomem *zq_base, *dx_base;
+ int zq, dx;
+ int nr_dx;
+
+ nr_dx = width / 8;
+
+ writel(MPHY_PIR_ZCALBYP, phy_base + MPHY_PIR);
+ /*
+ * Disable RGLVT bit (Read DQS Gating LCDL Delay VT Compensation)
+ * to avoid read error issue.
+ */
+ writel(0x07d81e37, phy_base + MPHY_PGCR0);
+ writel(0x0200c4e0, phy_base + MPHY_PGCR1);
+
+ tmp = ddrphy_pgcr2[freq];
+ if (width >= 32)
+ tmp |= MPHY_PGCR2_DUALCHN | MPHY_PGCR2_ACPDDC;
+ writel(tmp, phy_base + MPHY_PGCR2);
+
+ writel(ddrphy_ptr0[freq], phy_base + MPHY_PTR0);
+ writel(ddrphy_ptr1[freq], phy_base + MPHY_PTR1);
+ writel(0x00083def, phy_base + MPHY_PTR2);
+ writel(ddrphy_ptr3[freq], phy_base + MPHY_PTR3);
+ writel(ddrphy_ptr4[freq], phy_base + MPHY_PTR4);
+
+ writel(ddrphy_acbdlr0[ch], phy_base + MPHY_ACBDLR0);
+
+ writel(0x55555555, phy_base + MPHY_ACIOCR1);
+ writel(0x00000000, phy_base + MPHY_ACIOCR2);
+ writel(0x55555555, phy_base + MPHY_ACIOCR3);
+ writel(0x00000000, phy_base + MPHY_ACIOCR4);
+ writel(0x00000055, phy_base + MPHY_ACIOCR5);
+ writel(0x00181aa4, phy_base + MPHY_DXCCR);
+
+ writel(0x0024641e, phy_base + MPHY_DSGCR);
+ writel(0x0000040b, phy_base + MPHY_DCR);
+ writel(ddrphy_dtpr0[freq], phy_base + MPHY_DTPR0);
+ writel(ddrphy_dtpr1[freq], phy_base + MPHY_DTPR1);
+ writel(ddrphy_dtpr2[freq], phy_base + MPHY_DTPR2);
+ writel(ddrphy_dtpr3[freq], phy_base + MPHY_DTPR3);
+ writel(ddrphy_mr0[freq], phy_base + MPHY_MR0);
+ writel(0x00000006, phy_base + MPHY_MR1);
+ writel(ddrphy_mr2[freq], phy_base + MPHY_MR2);
+ writel(0x00000000, phy_base + MPHY_MR3);
+
+ tmp = 0;
+ for (dx = 0; dx < nr_dx; dx++)
+ tmp |= BIT(MPHY_DTCR_RANKEN_SHIFT + ddrphy_get_rank(dx));
+ writel(0x90003087 | tmp, phy_base + MPHY_DTCR);
+
+ writel(0x00000000, phy_base + MPHY_DTAR0);
+ writel(0x00000008, phy_base + MPHY_DTAR1);
+ writel(0x00000010, phy_base + MPHY_DTAR2);
+ writel(0x00000018, phy_base + MPHY_DTAR3);
+ writel(0xdd22ee11, phy_base + MPHY_DTDR0);
+ writel(0x7788bb44, phy_base + MPHY_DTDR1);
+
+ /* impedance control settings */
+ writel(0x04048900, phy_base + MPHY_ZQCR);
+
+ zq_base = phy_base + MPHY_ZQ_BASE;
+ for (zq = 0; zq < 4; zq++) {
+ /*
+ * board-dependent
+ * PXS2: CH0ZQ0=0x5B, CH1ZQ0=0x5B, CH2ZQ0=0x59, others=0x5D
+ */
+ writel(0x0007BB5D, zq_base + MPHY_ZQ_PR);
+ zq_base += MPHY_ZQ_STRIDE;
+ }
+
+ /* DATX8 settings */
+ dx_base = phy_base + MPHY_DX_BASE;
+ for (dx = 0; dx < 4; dx++) {
+ tmp = readl(dx_base + MPHY_DX_GCR0);
+ tmp &= ~MPHY_DX_GCR0_WLRKEN_MASK;
+ tmp |= BIT(MPHY_DX_GCR0_WLRKEN_SHIFT + ddrphy_get_rank(dx)) &
+ MPHY_DX_GCR0_WLRKEN_MASK;
+ writel(tmp, dx_base + MPHY_DX_GCR0);
+
+ writel(0x00000000, dx_base + MPHY_DX_GCR1);
+ writel(0x00000000, dx_base + MPHY_DX_GCR2);
+ writel(0x00000000, dx_base + MPHY_DX_GCR3);
+ dx_base += MPHY_DX_STRIDE;
+ }
+
+ while (!(readl(phy_base + MPHY_PGSR0) & MPHY_PGSR0_IDONE))
+ cpu_relax();
+
+ ddrphy_dqs_delay_fixup(phy_base, nr_dx, -4);
+}
+
+struct ddrphy_init_sequence {
+ char *description;
+ u32 init_flag;
+ u32 done_flag;
+ u32 err_flag;
+};
+
+static const struct ddrphy_init_sequence impedance_calibration_sequence[] = {
+ {
+ "Impedance Calibration",
+ MPHY_PIR_ZCAL,
+ MPHY_PGSR0_ZCDONE,
+ MPHY_PGSR0_ZCERR,
+ },
+ { /* sentinel */ }
+};
+
+static const struct ddrphy_init_sequence dram_init_sequence[] = {
+ {
+ "DRAM Initialization",
+ MPHY_PIR_DRAMRST | MPHY_PIR_DRAMINIT,
+ MPHY_PGSR0_DIDONE,
+ 0,
+ },
+ { /* sentinel */ }
+};
+
+static const struct ddrphy_init_sequence training_sequence[] = {
+ {
+ "Write Leveling",
+ MPHY_PIR_WL,
+ MPHY_PGSR0_WLDONE,
+ MPHY_PGSR0_WLERR,
+ },
+ {
+ "Read DQS Gate Training",
+ MPHY_PIR_QSGATE,
+ MPHY_PGSR0_QSGDONE,
+ MPHY_PGSR0_QSGERR,
+ },
+ {
+ "Write Leveling Adjustment",
+ MPHY_PIR_WLADJ,
+ MPHY_PGSR0_WLADONE,
+ MPHY_PGSR0_WLAERR,
+ },
+ {
+ "Read Bit Deskew",
+ MPHY_PIR_RDDSKW,
+ MPHY_PGSR0_RDDONE,
+ MPHY_PGSR0_RDERR,
+ },
+ {
+ "Write Bit Deskew",
+ MPHY_PIR_WRDSKW,
+ MPHY_PGSR0_WDDONE,
+ MPHY_PGSR0_WDERR,
+ },
+ {
+ "Read Eye Training",
+ MPHY_PIR_RDEYE,
+ MPHY_PGSR0_REDONE,
+ MPHY_PGSR0_REERR,
+ },
+ {
+ "Write Eye Training",
+ MPHY_PIR_WREYE,
+ MPHY_PGSR0_WEDONE,
+ MPHY_PGSR0_WEERR,
+ },
+ { /* sentinel */ }
+};
+
+static int __ddrphy_training(void __iomem *phy_base,
+ const struct ddrphy_init_sequence *seq)
+{
+ const struct ddrphy_init_sequence *s;
+ u32 pgsr0;
+ u32 init_flag = MPHY_PIR_INIT;
+ u32 done_flag = MPHY_PGSR0_IDONE;
+ int timeout = 50000; /* 50 msec is long enough */
+ unsigned long start = 0;
+
+#ifdef DEBUG
+ start = get_timer(0);
+#endif
+
+ for (s = seq; s->description; s++) {
+ init_flag |= s->init_flag;
+ done_flag |= s->done_flag;
+ }
+
+ writel(init_flag, phy_base + MPHY_PIR);
+
+ do {
+ if (--timeout < 0) {
+ pr_err("%s: error: timeout during DDR training\n",
+ __func__);
+ return -ETIMEDOUT;
+ }
+ udelay(1);
+ pgsr0 = readl(phy_base + MPHY_PGSR0);
+ } while ((pgsr0 & done_flag) != done_flag);
+
+ for (s = seq; s->description; s++) {
+ if (pgsr0 & s->err_flag) {
+ pr_err("%s: error: %s failed\n", __func__,
+ s->description);
+ return -EIO;
+ }
+ }
+
+ pr_debug("DDRPHY training: elapsed time %ld msec\n", get_timer(start));
+
+ return 0;
+}
+
+static int ddrphy_impedance_calibration(void __iomem *phy_base)
+{
+ int ret;
+ u32 tmp;
+
+ ret = __ddrphy_training(phy_base, impedance_calibration_sequence);
+ if (ret)
+ return ret;
+
+ /*
+ * Because of a hardware bug, IDONE flag is set when the first ZQ block
+ * is calibrated. The flag does not guarantee the completion for all
+ * the ZQ blocks. Wait a little more just in case.
+ */
+ udelay(1);
+
+ /* reflect ZQ settings and enable average algorithm*/
+ tmp = readl(phy_base + MPHY_ZQCR);
+ tmp |= MPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
+ writel(tmp, phy_base + MPHY_ZQCR);
+ tmp &= ~MPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
+ tmp |= MPHY_ZQCR_AVGEN;
+ writel(tmp, phy_base + MPHY_ZQCR);
+
+ return 0;
+}
+
+static int ddrphy_dram_init(void __iomem *phy_base)
+{
+ return __ddrphy_training(phy_base, dram_init_sequence);
+}
+
+static int ddrphy_training(void __iomem *phy_base)
+{
+ return __ddrphy_training(phy_base, training_sequence);
+}
+
+/* UMC */
+static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x66DD131D, 0x77EE1722};
+/*
+ * The ch2 is a different generation UMC core.
+ * The register spec is different, unfortunately.
+ */
+static u32 umc_cmdctlb_ch01[DRAM_FREQ_NR] = {0x13E87C44, 0x18F88C44};
+static u32 umc_cmdctlb_ch2[DRAM_FREQ_NR] = {0x19E8DC44, 0x1EF8EC44};
+static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+ {0x004A071D, 0x0078071D},
+ {0x0055081E, 0x0089081E},
+};
+
+static u32 umc_spcctlb[] = {0x00FF000A, 0x00FF000B};
+/* The ch2 is different for some reason only hardware guys know... */
+static u32 umc_flowctla_ch01[] = {0x0800001E, 0x08000022};
+static u32 umc_flowctla_ch2[] = {0x0800001E, 0x0800001E};
+
+static void umc_set_system_latency(void __iomem *dc_base, int phy_latency)
+{
+ u32 val;
+ int latency;
+
+ val = readl(dc_base + UMC_RDATACTL_D0);
+ latency = (val & UMC_RDATACTL_RADLTY_MASK) >> UMC_RDATACTL_RADLTY_SHIFT;
+ latency += (val & UMC_RDATACTL_RAD2LTY_MASK) >>
+ UMC_RDATACTL_RAD2LTY_SHIFT;
+ /*
+ * UMC works at the half clock rate of the PHY.
+ * The LSB of latency is ignored
+ */
+ latency += phy_latency & ~1;
+
+ val &= ~(UMC_RDATACTL_RADLTY_MASK | UMC_RDATACTL_RAD2LTY_MASK);
+ if (latency > 0xf) {
+ val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
+ val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
+ } else {
+ val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
+ }
+
+ writel(val, dc_base + UMC_RDATACTL_D0);
+ writel(val, dc_base + UMC_RDATACTL_D1);
+
+ readl(dc_base + UMC_RDATACTL_D1); /* relax */
+}
+
+/* enable/disable auto refresh */
+static void umc_refresh_ctrl(void __iomem *dc_base, int enable)
+{
+ u32 tmp;
+
+ tmp = readl(dc_base + UMC_SPCSETB);
+ tmp &= ~UMC_SPCSETB_AREFMD_MASK;
+
+ if (enable)
+ tmp |= UMC_SPCSETB_AREFMD_ARB;
+ else
+ tmp |= UMC_SPCSETB_AREFMD_REG;
+
+ writel(tmp, dc_base + UMC_SPCSETB);
+ udelay(1);
+}
+
+static void umc_ud_init(void __iomem *umc_base, int ch)
+{
+ writel(0x00000003, umc_base + UMC_BITPERPIXELMODE_D0);
+
+ if (ch == 2)
+ writel(0x00000033, umc_base + UMC_PAIR1DOFF_D0);
+}
+
+static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
+ unsigned long size, int width, int ch)
+{
+ enum dram_size size_e;
+ int latency;
+ u32 val;
+
+ switch (size) {
+ case 0:
+ return 0;
+ case SZ_256M:
+ size_e = DRAM_SZ_256M;
+ break;
+ case SZ_512M:
+ size_e = DRAM_SZ_512M;
+ break;
+ default:
+ pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n",
+ size, ch);
+ return -EINVAL;
+ }
+
+ writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
+
+ writel(ch == 2 ? umc_cmdctlb_ch2[freq] : umc_cmdctlb_ch01[freq],
+ dc_base + UMC_CMDCTLB);
+
+ writel(umc_spcctla[freq][size_e], dc_base + UMC_SPCCTLA);
+ writel(umc_spcctlb[freq], dc_base + UMC_SPCCTLB);
+
+ val = 0x000e000e;
+ latency = 12;
+ /* ES2 inserted one more FF to the logic. */
+ if (uniphier_get_soc_model() >= 2)
+ latency += 2;
+
+ if (latency > 0xf) {
+ val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
+ val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
+ } else {
+ val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
+ }
+
+ writel(val, dc_base + UMC_RDATACTL_D0);
+ if (width >= 32)
+ writel(val, dc_base + UMC_RDATACTL_D1);
+
+ writel(0x04060A02, dc_base + UMC_WDATACTL_D0);
+ if (width >= 32)
+ writel(0x04060A02, dc_base + UMC_WDATACTL_D1);
+ writel(0x04000000, dc_base + UMC_DATASET);
+ writel(0x00400020, dc_base + UMC_DCCGCTL);
+ writel(0x00000084, dc_base + UMC_FLOWCTLG);
+ writel(0x00000000, dc_base + UMC_ACSSETA);
+
+ writel(ch == 2 ? umc_flowctla_ch2[freq] : umc_flowctla_ch01[freq],
+ dc_base + UMC_FLOWCTLA);
+
+ writel(0x00004400, dc_base + UMC_FLOWCTLC);
+ writel(0x200A0A00, dc_base + UMC_SPCSETB);
+ writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
+ writel(0x0000000D, dc_base + UMC_RESPCTL);
+
+ if (ch != 2) {
+ writel(0x00202000, dc_base + UMC_FLOWCTLB);
+ writel(0xFDBFFFFF, dc_base + UMC_FLOWCTLOB0);
+ writel(0xFFFFFFFF, dc_base + UMC_FLOWCTLOB1);
+ writel(0x00080700, dc_base + UMC_BSICMAPSET);
+ } else {
+ writel(0x00200000, dc_base + UMC_FLOWCTLB);
+ writel(0x00000000, dc_base + UMC_BSICMAPSET);
+ }
+
+ writel(0x00000000, dc_base + UMC_ERRMASKA);
+ writel(0x00000000, dc_base + UMC_ERRMASKB);
+
+ return 0;
+}
+
+static int umc_ch_init(void __iomem *umc_ch_base, enum dram_freq freq,
+ unsigned long size, unsigned int width, int ch)
+{
+ void __iomem *dc_base = umc_ch_base + 0x00011000;
+ void __iomem *phy_base = umc_ch_base + 0x00030000;
+ int ret;
+
+ writel(0x00000002, dc_base + UMC_INITSET);
+ while (readl(dc_base + UMC_INITSTAT) & BIT(2))
+ cpu_relax();
+
+ /* deassert PHY reset signals */
+ writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
+ dc_base + UMC_DIOCTLA);
+
+ ddrphy_init(phy_base, freq, width, ch);
+
+ ret = ddrphy_impedance_calibration(phy_base);
+ if (ret)
+ return ret;
+
+ ddrphy_dram_init(phy_base);
+ if (ret)
+ return ret;
+
+ ret = umc_dc_init(dc_base, freq, size, width, ch);
+ if (ret)
+ return ret;
+
+ umc_ud_init(umc_ch_base, ch);
+
+ ret = ddrphy_training(phy_base);
+ if (ret)
+ return ret;
+
+ udelay(1);
+
+ /* match the system latency between UMC and PHY */
+ umc_set_system_latency(dc_base,
+ ddrphy_get_system_latency(phy_base, width));
+
+ udelay(1);
+
+ /* stop auto refresh before clearing FIFO in PHY */
+ umc_refresh_ctrl(dc_base, 0);
+ ddrphy_fifo_reset(phy_base);
+ umc_refresh_ctrl(dc_base, 1);
+
+ udelay(10);
+
+ return 0;
+}
+
+static void um_init(void __iomem *um_base)
+{
+ writel(0x000000ff, um_base + UMC_MBUS0);
+ writel(0x000000ff, um_base + UMC_MBUS1);
+ writel(0x000000ff, um_base + UMC_MBUS2);
+ writel(0x000000ff, um_base + UMC_MBUS3);
+}
+
+int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd)
+{
+ void __iomem *um_base = (void __iomem *)0x5b600000;
+ void __iomem *umc_ch_base = (void __iomem *)0x5b800000;
+ enum dram_freq freq;
+ int ch, ret;
+
+ switch (bd->dram_freq) {
+ case 1866:
+ freq = DRAM_FREQ_1866M;
+ break;
+ case 2133:
+ freq = DRAM_FREQ_2133M;
+ break;
+ default:
+ pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
+ return -EINVAL;
+ }
+
+ for (ch = 0; ch < DRAM_CH_NR; ch++) {
+ unsigned long size = bd->dram_ch[ch].size;
+ unsigned int width = bd->dram_ch[ch].width;
+
+ if (size) {
+ ret = umc_ch_init(umc_ch_base, freq,
+ size / (width / 16), width, ch);
+ if (ret) {
+ pr_err("failed to initialize UMC ch%d\n", ch);
+ return ret;
+ }
+ }
+
+ umc_ch_base += 0x00200000;
+ }
+
+ um_init(um_base);
+
+ return 0;
+}
diff --git a/roms/u-boot/arch/arm/mach-uniphier/dram/umc-regs.h b/roms/u-boot/arch/arm/mach-uniphier/dram/umc-regs.h
new file mode 100644
index 000000000..02efab384
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-uniphier/dram/umc-regs.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * UniPhier UMC (Universal Memory Controller) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ */
+
+#ifndef ARCH_UMC_REGS_H
+#define ARCH_UMC_REGS_H
+
+#include <linux/bitops.h>
+
+#define UMC_CPURST 0x00000700
+#define UMC_IDSRST 0x0000070C
+#define UMC_IXMRST 0x00000714
+#define UMC_HDMRST 0x00000718
+#define UMC_MDMRST 0x0000071C
+#define UMC_HDDRST 0x00000720
+#define UMC_MDDRST 0x00000724
+#define UMC_SIORST 0x00000728
+#define UMC_GIORST 0x0000072C
+#define UMC_HD2RST 0x00000734
+#define UMC_VIORST 0x0000073C
+#define UMC_FRCRST 0x00000748 /* LD4/sLD8 */
+#define UMC_DVCRST 0x00000748 /* Pro4 */
+#define UMC_RGLRST 0x00000750
+#define UMC_VPERST 0x00000758
+#define UMC_AIORST 0x00000764
+#define UMC_DMDRST 0x00000770
+
+#define UMC_HDMCHSEL 0x00000898
+#define UMC_MDMCHSEL 0x0000089C
+#define UMC_DVCCHSEL 0x000008C8
+#define UMC_DMDCHSEL 0x000008F0
+
+#define UMC_CLKEN_SSIF_FETCH 0x0000C060
+#define UMC_CLKEN_SSIF_COMQUE0 0x0000C064
+#define UMC_CLKEN_SSIF_COMWC0 0x0000C068
+#define UMC_CLKEN_SSIF_COMRC0 0x0000C06C
+#define UMC_CLKEN_SSIF_COMQUE1 0x0000C070
+#define UMC_CLKEN_SSIF_COMWC1 0x0000C074
+#define UMC_CLKEN_SSIF_COMRC1 0x0000C078
+#define UMC_CLKEN_SSIF_WC 0x0000C07C
+#define UMC_CLKEN_SSIF_RC 0x0000C080
+#define UMC_CLKEN_SSIF_DST 0x0000C084
+
+#define UMC_CMDCTLA 0x00000000
+#define UMC_CMDCTLB 0x00000004
+#define UMC_INITSET 0x00000014
+#define UMC_INITSET_INIT1EN BIT(1) /* init without power-on wait */
+#define UMC_INITSET_INIT0EN BIT(0) /* init with power-on wait */
+#define UMC_INITSTAT 0x00000018
+#define UMC_INITSTAT_INIT1ST BIT(1) /* init without power-on wait */
+#define UMC_INITSTAT_INIT0ST BIT(0) /* init with power-on wait */
+#define UMC_SPCCTLA 0x00000030
+#define UMC_SPCCTLB 0x00000034
+#define UMC_SPCSETA 0x00000038
+#define UMC_SPCSETB 0x0000003C
+#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */
+#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */
+#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */
+#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */
+#define UMC_SPCSETC 0x00000040
+#define UMC_SPCSETD 0x00000044
+#define UMC_SPCSTATA 0x00000050
+#define UMC_SPCSTATB 0x00000054
+#define UMC_SPCSTATC 0x00000058
+#define UMC_ACSSETA 0x00000060
+#define UMC_FLOWCTLA 0x00000400
+#define UMC_FLOWCTLB 0x00000404
+#define UMC_FLOWCTLC 0x00000408
+#define UMC_FLOWCTLG 0x00000508
+#define UMC_FLOWCTLOB0 0x00000520
+#define UMC_FLOWCTLOB1 0x00000524
+#define UMC_RDATACTL_D0 0x00000600
+#define UMC_RDATACTL_RADLTY_SHIFT 4
+#define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT))
+#define UMC_RDATACTL_RAD2LTY_SHIFT 8
+#define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT))
+#define UMC_WDATACTL_D0 0x00000604
+#define UMC_RDATACTL_D1 0x00000608
+#define UMC_WDATACTL_D1 0x0000060C
+#define UMC_DATASET 0x00000610
+#define UMC_RESPCTL 0x00000624
+#define UMC_DCCGCTL 0x00000720
+#define UMC_DICGCTLA 0x00000724
+#define UMC_DICGCTLB 0x00000728
+#define UMC_ERRMASKA 0x00000958
+#define UMC_ERRMASKB 0x0000095c
+#define UMC_BSICMAPSET 0x00000988
+#define UMC_DIOCTLA 0x00000C00
+#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */
+#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */
+#define UMC_DFICUPDCTLA 0x00000C20
+
+/* UM registers */
+#define UMC_MBUS0 0x00080004
+#define UMC_MBUS1 0x00081004
+#define UMC_MBUS2 0x00082004
+#define UMC_MBUS3 0x00083004
+
+/* UD registers */
+#define UMC_BITPERPIXELMODE_D0 0x010
+#define UMC_PAIR1DOFF_D0 0x054
+
+#endif
diff --git a/roms/u-boot/arch/arm/mach-uniphier/dram/umc-sld8.c b/roms/u-boot/arch/arm/mach-uniphier/dram/umc-sld8.c
new file mode 100644
index 000000000..a11586952
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-uniphier/dram/umc-sld8.c
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <asm/processor.h>
+
+#include "../init.h"
+#include "ddrphy-init.h"
+#include "umc-regs.h"
+
+#define DRAM_CH_NR 2
+
+enum dram_freq {
+ DRAM_FREQ_1333M,
+ DRAM_FREQ_1600M,
+ DRAM_FREQ_NR,
+};
+
+enum dram_size {
+ DRAM_SZ_128M,
+ DRAM_SZ_256M,
+ DRAM_SZ_512M,
+ DRAM_SZ_NR,
+};
+
+static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x55990b11, 0x66bb0f17};
+static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x46bb0f17};
+static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x16958944, 0x18c6ab44};
+static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6ab24};
+static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+ {0x00240512, 0x00350512, 0x00000000}, /* no data for 1333MHz,128MB */
+ {0x002b0617, 0x003f0617, 0x00670617},
+};
+static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
+static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ac};
+
+static int umc_get_rank(int ch)
+{
+ return ch; /* ch0: rank0, ch1: rank1 for this SoC */
+}
+
+static void umc_start_ssif(void __iomem *ssif_base)
+{
+ writel(0x00000000, ssif_base + 0x0000b004);
+ writel(0xffffffff, ssif_base + 0x0000c004);
+ writel(0x000fffcf, ssif_base + 0x0000c008);
+ writel(0x00000001, ssif_base + 0x0000b000);
+ writel(0x00000001, ssif_base + 0x0000c000);
+ writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+ writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+
+ writel(0x00000001, ssif_base + UMC_CPURST);
+ writel(0x00000001, ssif_base + UMC_IDSRST);
+ writel(0x00000001, ssif_base + UMC_IXMRST);
+ writel(0x00000001, ssif_base + UMC_MDMRST);
+ writel(0x00000001, ssif_base + UMC_MDDRST);
+ writel(0x00000001, ssif_base + UMC_SIORST);
+ writel(0x00000001, ssif_base + UMC_VIORST);
+ writel(0x00000001, ssif_base + UMC_FRCRST);
+ writel(0x00000001, ssif_base + UMC_RGLRST);
+ writel(0x00000001, ssif_base + UMC_AIORST);
+ writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
+ int freq, unsigned long size, bool ddr3plus)
+{
+ enum dram_freq freq_e;
+ enum dram_size size_e;
+
+ switch (freq) {
+ case 1333:
+ freq_e = DRAM_FREQ_1333M;
+ break;
+ case 1600:
+ freq_e = DRAM_FREQ_1600M;
+ break;
+ default:
+ pr_err("unsupported DRAM frequency %d MHz\n", freq);
+ return -EINVAL;
+ }
+
+ switch (size) {
+ case 0:
+ return 0;
+ case SZ_128M:
+ size_e = DRAM_SZ_128M;
+ break;
+ case SZ_256M:
+ size_e = DRAM_SZ_256M;
+ break;
+ case SZ_512M:
+ size_e = DRAM_SZ_512M;
+ break;
+ default:
+ pr_err("unsupported DRAM size 0x%08lx\n", size);
+ return -EINVAL;
+ }
+
+ writel((ddr3plus ? umc_cmdctla_plus : umc_cmdctla)[freq_e],
+ dc_base + UMC_CMDCTLA);
+ writel((ddr3plus ? umc_cmdctlb_plus : umc_cmdctlb)[freq_e],
+ dc_base + UMC_CMDCTLB);
+ writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA);
+ writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB);
+ writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
+ writel(0x04060806, dc_base + UMC_WDATACTL_D0);
+ writel(0x04a02000, dc_base + UMC_DATASET);
+ writel(0x00000000, ca_base + 0x2300);
+ writel(0x00400020, dc_base + UMC_DCCGCTL);
+ writel(0x00000003, dc_base + 0x7000);
+ writel(0x0000004f, dc_base + 0x8000);
+ writel(0x000000c3, dc_base + 0x8004);
+ writel(0x00000077, dc_base + 0x8008);
+ writel(0x0000003b, dc_base + UMC_DICGCTLA);
+ writel(0x020a0808, dc_base + UMC_DICGCTLB);
+ writel(0x00000004, dc_base + UMC_FLOWCTLG);
+ writel(0x80000201, ca_base + 0xc20);
+ writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
+ writel(0x00200000, dc_base + UMC_FLOWCTLB);
+ writel(0x00004444, dc_base + UMC_FLOWCTLC);
+ writel(0x200a0a00, dc_base + UMC_SPCSETB);
+ writel(0x00000000, dc_base + UMC_SPCSETD);
+ writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
+
+ return 0;
+}
+
+static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
+ int freq, unsigned long size, bool ddr3plus, int ch)
+{
+ void __iomem *phy_base = dc_base + 0x00001000;
+ int ret;
+
+ writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
+ while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
+ cpu_relax();
+
+ writel(0x00000101, dc_base + UMC_DIOCTLA);
+
+ ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
+ if (ret)
+ return ret;
+
+ ddrphy_prepare_training(phy_base, umc_get_rank(ch));
+ ret = ddrphy_training(phy_base);
+ if (ret)
+ return ret;
+
+ return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus);
+}
+
+int uniphier_sld8_umc_init(const struct uniphier_board_data *bd)
+{
+ void __iomem *umc_base = (void __iomem *)0x5b800000;
+ void __iomem *ca_base = umc_base + 0x00001000;
+ void __iomem *dc_base = umc_base + 0x00400000;
+ void __iomem *ssif_base = umc_base;
+ int ch, ret;
+
+ for (ch = 0; ch < DRAM_CH_NR; ch++) {
+ ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
+ bd->dram_ch[ch].size,
+ !!(bd->flags & UNIPHIER_BD_DDR3PLUS), ch);
+ if (ret) {
+ pr_err("failed to initialize UMC ch%d\n", ch);
+ return ret;
+ }
+
+ ca_base += 0x00001000;
+ dc_base += 0x00200000;
+ }
+
+ umc_start_ssif(ssif_base);
+
+ return 0;
+}
--
cgit