From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001
From: Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com>
Date: Tue, 10 Oct 2023 14:33:42 +0000
Subject: Add submodule dependency files

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
---
 roms/u-boot/arch/microblaze/cpu/cache.c | 74 +++++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 roms/u-boot/arch/microblaze/cpu/cache.c

(limited to 'roms/u-boot/arch/microblaze/cpu/cache.c')

diff --git a/roms/u-boot/arch/microblaze/cpu/cache.c b/roms/u-boot/arch/microblaze/cpu/cache.c
new file mode 100644
index 000000000..aa832d6be
--- /dev/null
+++ b/roms/u-boot/arch/microblaze/cpu/cache.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <asm/asm.h>
+#include <asm/cache.h>
+
+int dcache_status(void)
+{
+	int i = 0;
+	int mask = 0x80;
+	__asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
+	/* i&=0x80 */
+	__asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
+	return i;
+}
+
+int icache_status(void)
+{
+	int i = 0;
+	int mask = 0x20;
+	__asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
+	/* i&=0x20 */
+	__asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
+	return i;
+}
+
+void icache_enable(void)
+{
+	MSRSET(0x20);
+}
+
+void icache_disable(void)
+{
+	/* we are not generate ICACHE size -> flush whole cache */
+	flush_cache(0, 32768);
+	MSRCLR(0x20);
+}
+
+void dcache_enable(void)
+{
+	MSRSET(0x80);
+}
+
+void dcache_disable(void)
+{
+#ifdef XILINX_USE_DCACHE
+	flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
+#endif
+	MSRCLR(0x80);
+}
+
+void flush_cache(ulong addr, ulong size)
+{
+	int i;
+	for (i = 0; i < size; i += 4)
+		asm volatile (
+#ifdef CONFIG_ICACHE
+				"wic	%0, r0;"
+#endif
+				"nop;"
+#ifdef CONFIG_DCACHE
+				"wdc.flush	%0, r0;"
+#endif
+				"nop;"
+				:
+				: "r" (addr + i)
+				: "memory");
+}
-- 
cgit