From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001 From: Angelos Mouzakitis Date: Tue, 10 Oct 2023 14:33:42 +0000 Subject: Add submodule dependency files Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec --- roms/u-boot/arch/powerpc/dts/mpc8548-post.dtsi | 36 ++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 roms/u-boot/arch/powerpc/dts/mpc8548-post.dtsi (limited to 'roms/u-boot/arch/powerpc/dts/mpc8548-post.dtsi') diff --git a/roms/u-boot/arch/powerpc/dts/mpc8548-post.dtsi b/roms/u-boot/arch/powerpc/dts/mpc8548-post.dtsi new file mode 100644 index 000000000..2206f2da9 --- /dev/null +++ b/roms/u-boot/arch/powerpc/dts/mpc8548-post.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * MPC8548 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2012 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +&soc { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,mpc8548-immr", "simple-bus"; + bus-frequency = <0x0>; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic"; + device_type = "open-pic"; + big-endian; + single-cpu-affinity; + last-interrupt-source = <255>; + }; +}; + +&pcie { + compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; -- cgit 1.2.3-korg