From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001
From: Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com>
Date: Tue, 10 Oct 2023 14:33:42 +0000
Subject: Add submodule dependency files

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
---
 .../arch/riscv/include/asm/arch-fu740/cache.h      | 14 ++++++++
 .../u-boot/arch/riscv/include/asm/arch-fu740/clk.h | 14 ++++++++
 .../arch/riscv/include/asm/arch-fu740/gpio.h       | 38 ++++++++++++++++++++++
 .../arch/riscv/include/asm/arch-fu740/reset.h      | 13 ++++++++
 .../u-boot/arch/riscv/include/asm/arch-fu740/spl.h | 14 ++++++++
 5 files changed, 93 insertions(+)
 create mode 100644 roms/u-boot/arch/riscv/include/asm/arch-fu740/cache.h
 create mode 100644 roms/u-boot/arch/riscv/include/asm/arch-fu740/clk.h
 create mode 100644 roms/u-boot/arch/riscv/include/asm/arch-fu740/gpio.h
 create mode 100644 roms/u-boot/arch/riscv/include/asm/arch-fu740/reset.h
 create mode 100644 roms/u-boot/arch/riscv/include/asm/arch-fu740/spl.h

(limited to 'roms/u-boot/arch/riscv/include/asm/arch-fu740')

diff --git a/roms/u-boot/arch/riscv/include/asm/arch-fu740/cache.h b/roms/u-boot/arch/riscv/include/asm/arch-fu740/cache.h
new file mode 100644
index 000000000..7d4fe9942
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/arch-fu740/cache.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc.
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifve.com>
+ */
+
+#ifndef _CACHE_SIFIVE_H
+#define _CACHE_SIFIVE_H
+
+int cache_enable_ways(void);
+
+#endif /* _CACHE_SIFIVE_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/arch-fu740/clk.h b/roms/u-boot/arch/riscv/include/asm/arch-fu740/clk.h
new file mode 100644
index 000000000..9f883616b
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/arch-fu740/clk.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020-2021 SiFive Inc
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#ifndef __CLK_SIFIVE_H
+#define __CLK_SIFIVE_H
+
+/* Note: This is a placeholder header for driver compilation. */
+
+#endif
diff --git a/roms/u-boot/arch/riscv/include/asm/arch-fu740/gpio.h b/roms/u-boot/arch/riscv/include/asm/arch-fu740/gpio.h
new file mode 100644
index 000000000..908e2e556
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/arch-fu740/gpio.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc.
+ */
+
+#ifndef _GPIO_SIFIVE_H
+#define _GPIO_SIFIVE_H
+
+#define GPIO_INPUT_VAL	0x00
+#define GPIO_INPUT_EN	0x04
+#define GPIO_OUTPUT_EN	0x08
+#define GPIO_OUTPUT_VAL	0x0C
+#define GPIO_RISE_IE	0x18
+#define GPIO_RISE_IP	0x1C
+#define GPIO_FALL_IE	0x20
+#define GPIO_FALL_IP	0x24
+#define GPIO_HIGH_IE	0x28
+#define GPIO_HIGH_IP	0x2C
+#define GPIO_LOW_IE	0x30
+#define GPIO_LOW_IP	0x34
+#define GPIO_OUTPUT_XOR	0x40
+
+#define NR_GPIOS	16
+
+enum gpio_state {
+	LOW,
+	HIGH
+};
+
+/* Details about a GPIO bank */
+struct sifive_gpio_plat {
+	void *base;     /* address of registers in physical memory */
+};
+
+#define SIFIVE_GENERIC_GPIO_NR(port, index) \
+		(((port) * NR_GPIOS) + ((index) & (NR_GPIOS - 1)))
+
+#endif /* _GPIO_SIFIVE_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/arch-fu740/reset.h b/roms/u-boot/arch/riscv/include/asm/arch-fu740/reset.h
new file mode 100644
index 000000000..538ef8741
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/arch-fu740/reset.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020-2021 SiFive, Inc.
+ *
+ * Author: Sagar Kadam <sagar.kadam@sifive.com>
+ */
+
+#ifndef __RESET_SIFIVE_H
+#define __RESET_SIFIVE_H
+
+int sifive_reset_bind(struct udevice *dev, ulong count);
+
+#endif
diff --git a/roms/u-boot/arch/riscv/include/asm/arch-fu740/spl.h b/roms/u-boot/arch/riscv/include/asm/arch-fu740/spl.h
new file mode 100644
index 000000000..15ad9e7c8
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/arch-fu740/spl.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc.
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifve.com>
+ */
+
+#ifndef _SPL_SIFIVE_H
+#define _SPL_SIFIVE_H
+
+int spl_soc_init(void);
+
+#endif /* _SPL_SIFIVE_H */
-- 
cgit