From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001
From: Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com>
Date: Tue, 10 Oct 2023 14:33:42 +0000
Subject: Add submodule dependency files
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
---
roms/u-boot/arch/sh/cpu/sh4/cache.c | 111 ++++++++++++++++++++++++++++++++++++
1 file changed, 111 insertions(+)
create mode 100644 roms/u-boot/arch/sh/cpu/sh4/cache.c
(limited to 'roms/u-boot/arch/sh/cpu/sh4/cache.c')
diff --git a/roms/u-boot/arch/sh/cpu/sh4/cache.c b/roms/u-boot/arch/sh/cpu/sh4/cache.c
new file mode 100644
index 000000000..0f7dfdd3c
--- /dev/null
+++ b/roms/u-boot/arch/sh/cpu/sh4/cache.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Vladimir Zapolskiy <vz@mleia.com>
+ * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+
+#define CACHE_VALID 1
+#define CACHE_UPDATED 2
+
+static inline void cache_wback_all(void)
+{
+ unsigned long addr, data, i, j;
+
+ for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) {
+ for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
+ addr = CACHE_OC_ADDRESS_ARRAY
+ | (j << CACHE_OC_WAY_SHIFT)
+ | (i << CACHE_OC_ENTRY_SHIFT);
+ data = inl(addr);
+ if (data & CACHE_UPDATED) {
+ data &= ~CACHE_UPDATED;
+ outl(data, addr);
+ }
+ }
+ }
+}
+
+#define CACHE_ENABLE 0
+#define CACHE_DISABLE 1
+
+static int cache_control(unsigned int cmd)
+{
+ unsigned long ccr;
+
+ jump_to_P2();
+ ccr = inl(CCR);
+
+ if (ccr & CCR_CACHE_ENABLE)
+ cache_wback_all();
+
+ if (cmd == CACHE_DISABLE)
+ outl(CCR_CACHE_STOP, CCR);
+ else
+ outl(CCR_CACHE_INIT, CCR);
+ back_to_P1();
+
+ return 0;
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+ u32 v;
+
+ start &= ~(L1_CACHE_BYTES - 1);
+ for (v = start; v < end; v += L1_CACHE_BYTES) {
+ asm volatile ("ocbp %0" : /* no output */
+ : "m" (__m(v)));
+ }
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+ u32 v;
+
+ start &= ~(L1_CACHE_BYTES - 1);
+ for (v = start; v < end; v += L1_CACHE_BYTES) {
+ asm volatile ("ocbi %0" : /* no output */
+ : "m" (__m(v)));
+ }
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+ flush_dcache_range(addr , addr + size);
+}
+
+void icache_enable(void)
+{
+ cache_control(CACHE_ENABLE);
+}
+
+void icache_disable(void)
+{
+ cache_control(CACHE_DISABLE);
+}
+
+int icache_status(void)
+{
+ return 0;
+}
+
+void dcache_enable(void)
+{
+}
+
+void dcache_disable(void)
+{
+}
+
+int dcache_status(void)
+{
+ return 0;
+}
--
cgit