From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001
From: Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com>
Date: Tue, 10 Oct 2023 14:33:42 +0000
Subject: Add submodule dependency files

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
---
 roms/u-boot/board/renesas/r2dplus/r2dplus.c | 54 +++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)
 create mode 100644 roms/u-boot/board/renesas/r2dplus/r2dplus.c

(limited to 'roms/u-boot/board/renesas/r2dplus/r2dplus.c')

diff --git a/roms/u-boot/board/renesas/r2dplus/r2dplus.c b/roms/u-boot/board/renesas/r2dplus/r2dplus.c
new file mode 100644
index 000000000..4b9959a43
--- /dev/null
+++ b/roms/u-boot/board/renesas/r2dplus/r2dplus.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2007,2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ */
+
+#include <common.h>
+#include <ide.h>
+#include <init.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+int checkboard(void)
+{
+	puts("BOARD: Renesas Solutions R2D Plus\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+#define FPGA_BASE		0xA4000000
+#define FPGA_CFCTL		(FPGA_BASE + 0x04)
+#define CFCTL_EN		(0x432)
+#define FPGA_CFPOW		(FPGA_BASE + 0x06)
+#define CFPOW_ON		(0x02)
+#define FPGA_CFCDINTCLR	(FPGA_BASE + 0x2A)
+#define CFCDINTCLR_EN	(0x01)
+
+void ide_set_reset(int idereset)
+{
+	/* if reset = 1 IDE reset will be asserted */
+	if (idereset) {
+		outw(CFCTL_EN, FPGA_CFCTL);	/* CF enable */
+		outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */
+		outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */
+	}
+}
+
+#ifndef CONFIG_DM_ETH
+int board_eth_init(struct bd_info *bis)
+{
+	return pci_eth_init(bis);
+}
+#endif
-- 
cgit 1.2.3-korg