From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001 From: Angelos Mouzakitis Date: Tue, 10 Oct 2023 14:33:42 +0000 Subject: Add submodule dependency files Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec --- roms/u-boot/board/ti/ks2_evm/ddr3_k2e.c | 47 +++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 roms/u-boot/board/ti/ks2_evm/ddr3_k2e.c (limited to 'roms/u-boot/board/ti/ks2_evm/ddr3_k2e.c') diff --git a/roms/u-boot/board/ti/ks2_evm/ddr3_k2e.c b/roms/u-boot/board/ti/ks2_evm/ddr3_k2e.c new file mode 100644 index 000000000..95fe3a902 --- /dev/null +++ b/roms/u-boot/board/ti/ks2_evm/ddr3_k2e.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Keystone2: DDR3 initialization + * + * (C) Copyright 2014-2015 + * Texas Instruments Incorporated, + */ + +#include +#include "ddr3_cfg.h" +#include + +static struct pll_init_data ddr3_400 = DDR3_PLL_400; +static struct pll_init_data ddr3_333 = DDR3_PLL_333; + +u32 ddr3_init(void) +{ + struct ddr3_spd_cb spd_cb; + + if (ddr3_get_dimm_params_from_spd(&spd_cb)) { + printf("Sorry, I don't know how to configure DDR3A.\n" + "Bye :(\n"); + for (;;) + ; + } + + printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name); + + printf("DDR3 speed %d\n", spd_cb.ddrspdclock); + if (spd_cb.ddrspdclock == 1600) + init_pll(&ddr3_400); + else + init_pll(&ddr3_333); + + /* Reset DDR3 PHY after PLL enabled */ + ddr3_reset_ddrphy(); + + spd_cb.phy_cfg.zq0cr1 |= 0x10000; + spd_cb.phy_cfg.zq1cr1 |= 0x10000; + spd_cb.phy_cfg.zq2cr1 |= 0x10000; + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg); + + printf("DRAM: %d GiB\n", spd_cb.ddr_size_gbyte); + + return (u32)spd_cb.ddr_size_gbyte; +} -- cgit