From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001
From: Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com>
Date: Tue, 10 Oct 2023 14:33:42 +0000
Subject: Add submodule dependency files

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
---
 roms/u-boot/board/ti/ks2_evm/ddr3_k2l.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 roms/u-boot/board/ti/ks2_evm/ddr3_k2l.c

(limited to 'roms/u-boot/board/ti/ks2_evm/ddr3_k2l.c')

diff --git a/roms/u-boot/board/ti/ks2_evm/ddr3_k2l.c b/roms/u-boot/board/ti/ks2_evm/ddr3_k2l.c
new file mode 100644
index 000000000..805bf81f6
--- /dev/null
+++ b/roms/u-boot/board/ti/ks2_evm/ddr3_k2l.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+
+static struct pll_init_data ddr3_400 = DDR3_PLL_400;
+
+u32 ddr3_init(void)
+{
+	init_pll(&ddr3_400);
+
+	/* No SO-DIMM, 2GB discreet DDR */
+	printf("DRAM: 2 GiB\n");
+
+	/* Reset DDR3 PHY after PLL enabled */
+	ddr3_reset_ddrphy();
+
+	ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g);
+	ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g);
+
+	return 2;
+}
-- 
cgit